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Put qemu code section in region 2 for ia64
[qemu-kvm/amd-iommu.git] / vl.h
blob1ad61c22645759cf009f2dbdb9ba4827e0521e3c
1 /*
2 * QEMU System Emulator header
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #ifndef VL_H
25 #define VL_H
26
27 /* we put basic includes here to avoid repeating them in device drivers */
28 #include <stdlib.h>
29 #include <stdio.h>
30 #include <stdarg.h>
31 #include <string.h>
32 #include <inttypes.h>
33 #include <limits.h>
34 #include <time.h>
35 #include <ctype.h>
36 #include <errno.h>
37 #include <unistd.h>
38 #include <fcntl.h>
39 #include <sys/stat.h>
40
41 #ifndef O_LARGEFILE
42 #define O_LARGEFILE 0
43 #endif
44 #ifndef O_BINARY
45 #define O_BINARY 0
46 #endif
47
48 #ifndef ENOMEDIUM
49 #define ENOMEDIUM ENODEV
50 #endif
51
52 #ifdef _WIN32
53 #include <windows.h>
54 #define fsync _commit
55 #define lseek _lseeki64
56 #define ENOTSUP 4096
57 extern int qemu_ftruncate64(int, int64_t);
58 #define ftruncate qemu_ftruncate64
59
60
61 static inline char *realpath(const char *path, char *resolved_path)
62 {
63 _fullpath(resolved_path, path, _MAX_PATH);
64 return resolved_path;
65 }
66
67 #define PRId64 "I64d"
68 #define PRIx64 "I64x"
69 #define PRIu64 "I64u"
70 #define PRIo64 "I64o"
71 #endif
72
73 #ifdef QEMU_TOOL
74
75 /* we use QEMU_TOOL in the command line tools which do not depend on
76 the target CPU type */
77 #include "config-host.h"
78 #include <setjmp.h>
79 #include "osdep.h"
80 #include "bswap.h"
81
82 #else
83
84 #include "audio/audio.h"
85 #include "cpu.h"
86
87 #endif /* !defined(QEMU_TOOL) */
88
89 #ifndef glue
90 #define xglue(x, y) x ## y
91 #define glue(x, y) xglue(x, y)
92 #define stringify(s) tostring(s)
93 #define tostring(s) #s
94 #endif
95
96 #ifndef likely
97 #if __GNUC__ < 3
98 #define __builtin_expect(x, n) (x)
99 #endif
100
101 #define likely(x) __builtin_expect(!!(x), 1)
102 #define unlikely(x) __builtin_expect(!!(x), 0)
103 #endif
104
105 #ifndef MIN
106 #define MIN(a, b) (((a) < (b)) ? (a) : (b))
107 #endif
108 #ifndef MAX
109 #define MAX(a, b) (((a) > (b)) ? (a) : (b))
110 #endif
111
112 #ifndef always_inline
113 #if (__GNUC__ < 3) || defined(__APPLE__)
114 #define always_inline inline
115 #else
116 #define always_inline __attribute__ (( always_inline )) inline
117 #endif
118 #endif
119
120 /* cutils.c */
121 void pstrcpy(char *buf, int buf_size, const char *str);
122 char *pstrcat(char *buf, int buf_size, const char *s);
123 int strstart(const char *str, const char *val, const char **ptr);
124 int stristart(const char *str, const char *val, const char **ptr);
125 int hex2bin(char ch);
126 char *urldecode(const char *ptr);
127
128 /* vl.c */
129 void qemu_get_launch_info(int *argc, char ***argv, int *opt_daemonize, const char **opt_incoming);
130
131 uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c);
132
133 void hw_error(const char *fmt, ...);
134
135 extern const char *bios_dir;
136
137 extern int vm_running;
138 extern const char *qemu_name;
139
140 typedef struct vm_change_state_entry VMChangeStateEntry;
141 typedef void VMChangeStateHandler(void *opaque, int running);
142 typedef void VMStopHandler(void *opaque, int reason);
143
144 VMChangeStateEntry *qemu_add_vm_change_state_handler(VMChangeStateHandler *cb,
145 void *opaque);
146 void qemu_del_vm_change_state_handler(VMChangeStateEntry *e);
147
148 int qemu_add_vm_stop_handler(VMStopHandler *cb, void *opaque);
149 void qemu_del_vm_stop_handler(VMStopHandler *cb, void *opaque);
150
151 void vm_start(void);
152 void vm_stop(int reason);
153
154 typedef void QEMUResetHandler(void *opaque);
155
156 void qemu_register_reset(QEMUResetHandler *func, void *opaque);
157 void qemu_system_reset(void);
158 void qemu_system_reset_request(void);
159 void qemu_system_shutdown_request(void);
160 void qemu_system_powerdown_request(void);
161 int qemu_shutdown_requested(void);
162 int qemu_reset_requested(void);
163 int qemu_powerdown_requested(void);
164
165 #if !defined(TARGET_SPARC)
166 // Please implement a power failure function to signal the OS
167 #define qemu_system_powerdown() do{}while(0)
168 #else
169 void qemu_system_powerdown(void);
170 #endif
171
172 void main_loop_wait(int timeout);
173
174 extern int64_t ram_size;
175 extern int bios_size;
176 extern int rtc_utc;
177 extern int cirrus_vga_enabled;
178 extern int vmsvga_enabled;
179 extern int graphic_width;
180 extern int graphic_height;
181 extern int graphic_depth;
182 extern const char *keyboard_layout;
183 extern int kqemu_allowed;
184 extern int kvm_allowed;
185 extern int kvm_irqchip;
186 extern int win2k_install_hack;
187 extern int alt_grab;
188 extern int usb_enabled;
189 extern int smp_cpus;
190 extern int cursor_hide;
191 extern int graphic_rotate;
192 extern int no_quit;
193 extern int semihosting_enabled;
194 extern int autostart;
195 extern int time_drift_fix;
196 extern int old_param;
197 extern const char *bootp_filename;
198
199 #define MAX_OPTION_ROMS 16
200 extern const char *option_rom[MAX_OPTION_ROMS];
201 extern int nb_option_roms;
202
203 #ifdef TARGET_SPARC
204 #define MAX_PROM_ENVS 128
205 extern const char *prom_envs[MAX_PROM_ENVS];
206 extern unsigned int nb_prom_envs;
207 #endif
208
209 /* XXX: make it dynamic */
210 #ifndef TARGET_IA64
211 #define MAX_BIOS_SIZE (4 * 1024 * 1024)
212 #else
213 #define MAX_BIOS_SIZE (16 * 1024 *1026)
214 #endif
215 #if defined (TARGET_PPC) || defined (TARGET_SPARC64)
216 #define BIOS_SIZE ((512 + 32) * 1024)
217 #elif defined(TARGET_MIPS)
218 #define BIOS_SIZE (4 * 1024 * 1024)
219 #endif
220
221 #if USE_KVM
222 #ifdef TARGET_IA64
223 #define KVM_EXTRA_PAGES 0
224 #else
225 #define KVM_EXTRA_PAGES 3
226 #endif
227 #endif
228
229 /* keyboard/mouse support */
230
231 #define MOUSE_EVENT_LBUTTON 0x01
232 #define MOUSE_EVENT_RBUTTON 0x02
233 #define MOUSE_EVENT_MBUTTON 0x04
234
235 typedef void QEMUPutKBDEvent(void *opaque, int keycode);
236 typedef void QEMUPutMouseEvent(void *opaque, int dx, int dy, int dz, int buttons_state);
237
238 typedef struct QEMUPutMouseEntry {
239 QEMUPutMouseEvent *qemu_put_mouse_event;
240 void *qemu_put_mouse_event_opaque;
241 int qemu_put_mouse_event_absolute;
242 char *qemu_put_mouse_event_name;
243
244 /* used internally by qemu for handling mice */
245 struct QEMUPutMouseEntry *next;
246 } QEMUPutMouseEntry;
247
248 void qemu_add_kbd_event_handler(QEMUPutKBDEvent *func, void *opaque);
249 QEMUPutMouseEntry *qemu_add_mouse_event_handler(QEMUPutMouseEvent *func,
250 void *opaque, int absolute,
251 const char *name);
252 void qemu_remove_mouse_event_handler(QEMUPutMouseEntry *entry);
253
254 void kbd_put_keycode(int keycode);
255 void kbd_mouse_event(int dx, int dy, int dz, int buttons_state);
256 int kbd_mouse_is_absolute(void);
257
258 void do_info_mice(void);
259 void do_mouse_set(int index);
260
261 /* keysym is a unicode code except for special keys (see QEMU_KEY_xxx
262 constants) */
263 #define QEMU_KEY_ESC1(c) ((c) | 0xe100)
264 #define QEMU_KEY_BACKSPACE 0x007f
265 #define QEMU_KEY_UP QEMU_KEY_ESC1('A')
266 #define QEMU_KEY_DOWN QEMU_KEY_ESC1('B')
267 #define QEMU_KEY_RIGHT QEMU_KEY_ESC1('C')
268 #define QEMU_KEY_LEFT QEMU_KEY_ESC1('D')
269 #define QEMU_KEY_HOME QEMU_KEY_ESC1(1)
270 #define QEMU_KEY_END QEMU_KEY_ESC1(4)
271 #define QEMU_KEY_PAGEUP QEMU_KEY_ESC1(5)
272 #define QEMU_KEY_PAGEDOWN QEMU_KEY_ESC1(6)
273 #define QEMU_KEY_DELETE QEMU_KEY_ESC1(3)
274
275 #define QEMU_KEY_CTRL_UP 0xe400
276 #define QEMU_KEY_CTRL_DOWN 0xe401
277 #define QEMU_KEY_CTRL_LEFT 0xe402
278 #define QEMU_KEY_CTRL_RIGHT 0xe403
279 #define QEMU_KEY_CTRL_HOME 0xe404
280 #define QEMU_KEY_CTRL_END 0xe405
281 #define QEMU_KEY_CTRL_PAGEUP 0xe406
282 #define QEMU_KEY_CTRL_PAGEDOWN 0xe407
283
284 void kbd_put_keysym(int keysym);
285
286 /* async I/O support */
287
288 typedef void IOReadHandler(void *opaque, const uint8_t *buf, int size);
289 typedef int IOCanRWHandler(void *opaque);
290 typedef void IOHandler(void *opaque);
291
292 int qemu_set_fd_handler2(int fd,
293 IOCanRWHandler *fd_read_poll,
294 IOHandler *fd_read,
295 IOHandler *fd_write,
296 void *opaque);
297 int qemu_set_fd_handler(int fd,
298 IOHandler *fd_read,
299 IOHandler *fd_write,
300 void *opaque);
301
302 /* Polling handling */
303
304 /* return TRUE if no sleep should be done afterwards */
305 typedef int PollingFunc(void *opaque);
306
307 int qemu_add_polling_cb(PollingFunc *func, void *opaque);
308 void qemu_del_polling_cb(PollingFunc *func, void *opaque);
309
310 #ifdef _WIN32
311 /* Wait objects handling */
312 typedef void WaitObjectFunc(void *opaque);
313
314 int qemu_add_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
315 void qemu_del_wait_object(HANDLE handle, WaitObjectFunc *func, void *opaque);
316 #endif
317
318 typedef struct QEMUBH QEMUBH;
319
320 /* character device */
321
322 #define CHR_EVENT_BREAK 0 /* serial break char */
323 #define CHR_EVENT_FOCUS 1 /* focus to this terminal (modal input needed) */
324 #define CHR_EVENT_RESET 2 /* new connection established */
325
326
327 #define CHR_IOCTL_SERIAL_SET_PARAMS 1
328 typedef struct {
329 int speed;
330 int parity;
331 int data_bits;
332 int stop_bits;
333 } QEMUSerialSetParams;
334
335 #define CHR_IOCTL_SERIAL_SET_BREAK 2
336
337 #define CHR_IOCTL_PP_READ_DATA 3
338 #define CHR_IOCTL_PP_WRITE_DATA 4
339 #define CHR_IOCTL_PP_READ_CONTROL 5
340 #define CHR_IOCTL_PP_WRITE_CONTROL 6
341 #define CHR_IOCTL_PP_READ_STATUS 7
342 #define CHR_IOCTL_PP_EPP_READ_ADDR 8
343 #define CHR_IOCTL_PP_EPP_READ 9
344 #define CHR_IOCTL_PP_EPP_WRITE_ADDR 10
345 #define CHR_IOCTL_PP_EPP_WRITE 11
346
347 typedef void IOEventHandler(void *opaque, int event);
348
349 typedef struct CharDriverState {
350 int (*chr_write)(struct CharDriverState *s, const uint8_t *buf, int len);
351 void (*chr_update_read_handler)(struct CharDriverState *s);
352 int (*chr_ioctl)(struct CharDriverState *s, int cmd, void *arg);
353 IOEventHandler *chr_event;
354 IOCanRWHandler *chr_can_read;
355 IOReadHandler *chr_read;
356 void *handler_opaque;
357 void (*chr_send_event)(struct CharDriverState *chr, int event);
358 void (*chr_close)(struct CharDriverState *chr);
359 void *opaque;
360 int focus;
361 QEMUBH *bh;
362 } CharDriverState;
363
364 CharDriverState *qemu_chr_open(const char *filename);
365 void qemu_chr_printf(CharDriverState *s, const char *fmt, ...);
366 int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
367 void qemu_chr_send_event(CharDriverState *s, int event);
368 void qemu_chr_add_handlers(CharDriverState *s,
369 IOCanRWHandler *fd_can_read,
370 IOReadHandler *fd_read,
371 IOEventHandler *fd_event,
372 void *opaque);
373 int qemu_chr_ioctl(CharDriverState *s, int cmd, void *arg);
374 void qemu_chr_reset(CharDriverState *s);
375 int qemu_chr_can_read(CharDriverState *s);
376 void qemu_chr_read(CharDriverState *s, uint8_t *buf, int len);
377
378 /* consoles */
379
380 typedef struct DisplayState DisplayState;
381 typedef struct TextConsole TextConsole;
382
383 typedef void (*vga_hw_update_ptr)(void *);
384 typedef void (*vga_hw_invalidate_ptr)(void *);
385 typedef void (*vga_hw_screen_dump_ptr)(void *, const char *);
386
387 TextConsole *graphic_console_init(DisplayState *ds, vga_hw_update_ptr update,
388 vga_hw_invalidate_ptr invalidate,
389 vga_hw_screen_dump_ptr screen_dump,
390 void *opaque);
391 void vga_hw_update(void);
392 void vga_hw_invalidate(void);
393 void vga_hw_screen_dump(const char *filename);
394
395 int is_graphic_console(void);
396 CharDriverState *text_console_init(DisplayState *ds, const char *p);
397 void console_select(unsigned int index);
398
399 /* vmchannel devices */
400
401 #define MAX_VMCHANNEL_DEVICES 4
402
403 /* serial ports */
404
405 #define MAX_SERIAL_PORTS 4
406
407 extern CharDriverState *serial_hds[MAX_SERIAL_PORTS];
408
409 /* parallel ports */
410
411 #define MAX_PARALLEL_PORTS 3
412
413 extern CharDriverState *parallel_hds[MAX_PARALLEL_PORTS];
414
415 struct ParallelIOArg {
416 void *buffer;
417 int count;
418 };
419
420 /* VLANs support */
421
422 typedef struct VLANClientState VLANClientState;
423
424 struct VLANClientState {
425 IOReadHandler *fd_read;
426 /* Packets may still be sent if this returns zero. It's used to
427 rate-limit the slirp code. */
428 IOCanRWHandler *fd_can_read;
429 void *opaque;
430 struct VLANClientState *next;
431 struct VLANState *vlan;
432 char info_str[256];
433 };
434
435 typedef struct VLANState {
436 int id;
437 VLANClientState *first_client;
438 struct VLANState *next;
439 unsigned int nb_guest_devs, nb_host_devs;
440 } VLANState;
441
442 VLANState *qemu_find_vlan(int id);
443 VLANClientState *qemu_new_vlan_client(VLANState *vlan,
444 IOReadHandler *fd_read,
445 IOCanRWHandler *fd_can_read,
446 void *opaque);
447 int qemu_can_send_packet(VLANClientState *vc);
448 void qemu_send_packet(VLANClientState *vc, const uint8_t *buf, int size);
449 void qemu_handler_true(void *opaque);
450
451 void do_info_network(void);
452
453 /* TAP win32 */
454 int tap_win32_init(VLANState *vlan, const char *ifname);
455
456 /* NIC info */
457
458 #define MAX_NICS 8
459
460 typedef struct NICInfo {
461 uint8_t macaddr[6];
462 const char *model;
463 VLANState *vlan;
464 } NICInfo;
465
466 extern int nb_nics;
467 extern NICInfo nd_table[MAX_NICS];
468
469 /* timers */
470
471 typedef struct QEMUClock QEMUClock;
472 typedef struct QEMUTimer QEMUTimer;
473 typedef void QEMUTimerCB(void *opaque);
474
475 /* The real time clock should be used only for stuff which does not
476 change the virtual machine state, as it is run even if the virtual
477 machine is stopped. The real time clock has a frequency of 1000
478 Hz. */
479 extern QEMUClock *rt_clock;
480
481 /* The virtual clock is only run during the emulation. It is stopped
482 when the virtual machine is stopped. Virtual timers use a high
483 precision clock, usually cpu cycles (use ticks_per_sec). */
484 extern QEMUClock *vm_clock;
485
486 int64_t qemu_get_clock(QEMUClock *clock);
487
488 QEMUTimer *qemu_new_timer(QEMUClock *clock, QEMUTimerCB *cb, void *opaque);
489 void qemu_free_timer(QEMUTimer *ts);
490 void qemu_del_timer(QEMUTimer *ts);
491 void qemu_mod_timer(QEMUTimer *ts, int64_t expire_time);
492 int qemu_timer_pending(QEMUTimer *ts);
493
494 extern int64_t ticks_per_sec;
495
496 int64_t cpu_get_ticks(void);
497 void cpu_enable_ticks(void);
498 void cpu_disable_ticks(void);
499
500 /* VM Load/Save */
501
502 typedef struct QEMUFile QEMUFile;
503
504 typedef void (QEMUFilePutBufferFunc)(void *opaque, const uint8_t *buf, int64_t pos, int size);
505 typedef int (QEMUFileGetBufferFunc)(void *opaque, uint8_t *buf, int64_t pos, int size);
506 typedef void (QEMUFileCloseFunc)(void *opaque);
507
508 QEMUFile *qemu_fopen(void *opaque, QEMUFilePutBufferFunc *put_buffer,
509 QEMUFileGetBufferFunc *get_buffer, QEMUFileCloseFunc *close);
510 QEMUFile *qemu_fopen_file(const char *filename, const char *mode);
511 QEMUFile *qemu_fopen_fd(int fd);
512 void qemu_fflush(QEMUFile *f);
513 void qemu_fclose(QEMUFile *f);
514 void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, int size);
515 void qemu_put_byte(QEMUFile *f, int v);
516 void qemu_put_be16(QEMUFile *f, unsigned int v);
517 void qemu_put_be32(QEMUFile *f, unsigned int v);
518 void qemu_put_be64(QEMUFile *f, uint64_t v);
519 int qemu_get_buffer(QEMUFile *f, uint8_t *buf, int size);
520 int qemu_get_byte(QEMUFile *f);
521 unsigned int qemu_get_be16(QEMUFile *f);
522 unsigned int qemu_get_be32(QEMUFile *f);
523 uint64_t qemu_get_be64(QEMUFile *f);
524
525 static inline void qemu_put_be64s(QEMUFile *f, const uint64_t *pv)
526 {
527 qemu_put_be64(f, *pv);
528 }
529
530 static inline void qemu_put_be32s(QEMUFile *f, const uint32_t *pv)
531 {
532 qemu_put_be32(f, *pv);
533 }
534
535 static inline void qemu_put_be16s(QEMUFile *f, const uint16_t *pv)
536 {
537 qemu_put_be16(f, *pv);
538 }
539
540 static inline void qemu_put_8s(QEMUFile *f, const uint8_t *pv)
541 {
542 qemu_put_byte(f, *pv);
543 }
544
545 static inline void qemu_get_be64s(QEMUFile *f, uint64_t *pv)
546 {
547 *pv = qemu_get_be64(f);
548 }
549
550 static inline void qemu_get_be32s(QEMUFile *f, uint32_t *pv)
551 {
552 *pv = qemu_get_be32(f);
553 }
554
555 static inline void qemu_get_be16s(QEMUFile *f, uint16_t *pv)
556 {
557 *pv = qemu_get_be16(f);
558 }
559
560 static inline void qemu_get_8s(QEMUFile *f, uint8_t *pv)
561 {
562 *pv = qemu_get_byte(f);
563 }
564
565 #if TARGET_LONG_BITS == 64
566 #define qemu_put_betl qemu_put_be64
567 #define qemu_get_betl qemu_get_be64
568 #define qemu_put_betls qemu_put_be64s
569 #define qemu_get_betls qemu_get_be64s
570 #else
571 #define qemu_put_betl qemu_put_be32
572 #define qemu_get_betl qemu_get_be32
573 #define qemu_put_betls qemu_put_be32s
574 #define qemu_get_betls qemu_get_be32s
575 #endif
576
577 int64_t qemu_ftell(QEMUFile *f);
578 int64_t qemu_fseek(QEMUFile *f, int64_t pos, int whence);
579
580 typedef void SaveStateHandler(QEMUFile *f, void *opaque);
581 typedef int LoadStateHandler(QEMUFile *f, void *opaque, int version_id);
582
583 int register_savevm(const char *idstr,
584 int instance_id,
585 int version_id,
586 SaveStateHandler *save_state,
587 LoadStateHandler *load_state,
588 void *opaque);
589 void qemu_get_timer(QEMUFile *f, QEMUTimer *ts);
590 void qemu_put_timer(QEMUFile *f, QEMUTimer *ts);
591
592 void cpu_save(QEMUFile *f, void *opaque);
593 int cpu_load(QEMUFile *f, void *opaque, int version_id);
594
595 void do_savevm(const char *name);
596 void do_loadvm(const char *name);
597 void do_delvm(const char *name);
598 void do_info_snapshots(void);
599
600 int qemu_live_savevm_state(QEMUFile *f);
601 int qemu_live_loadvm_state(QEMUFile *f);
602
603 /* bottom halves */
604 typedef void QEMUBHFunc(void *opaque);
605
606 QEMUBH *qemu_bh_new(QEMUBHFunc *cb, void *opaque);
607 void qemu_bh_schedule(QEMUBH *bh);
608 void qemu_bh_cancel(QEMUBH *bh);
609 void qemu_bh_delete(QEMUBH *bh);
610 int qemu_bh_poll(void);
611
612 /* block.c */
613 typedef struct BlockDriverState BlockDriverState;
614 typedef struct BlockDriver BlockDriver;
615
616 extern BlockDriver bdrv_raw;
617 extern BlockDriver bdrv_host_device;
618 extern BlockDriver bdrv_cow;
619 extern BlockDriver bdrv_qcow;
620 extern BlockDriver bdrv_vmdk;
621 extern BlockDriver bdrv_cloop;
622 extern BlockDriver bdrv_dmg;
623 extern BlockDriver bdrv_bochs;
624 extern BlockDriver bdrv_vpc;
625 extern BlockDriver bdrv_vvfat;
626 extern BlockDriver bdrv_qcow2;
627 extern BlockDriver bdrv_parallels;
628
629 typedef struct BlockDriverInfo {
630 /* in bytes, 0 if irrelevant */
631 int cluster_size;
632 /* offset at which the VM state can be saved (0 if not possible) */
633 int64_t vm_state_offset;
634 } BlockDriverInfo;
635
636 typedef struct QEMUSnapshotInfo {
637 char id_str[128]; /* unique snapshot id */
638 /* the following fields are informative. They are not needed for
639 the consistency of the snapshot */
640 char name[256]; /* user choosen name */
641 uint32_t vm_state_size; /* VM state info size */
642 uint32_t date_sec; /* UTC date of the snapshot */
643 uint32_t date_nsec;
644 uint64_t vm_clock_nsec; /* VM clock relative to boot */
645 } QEMUSnapshotInfo;
646
647 typedef struct DiskIOStatistics {
648 uint64_t read_byte_counter;
649 uint64_t write_byte_counter;
650 }DiskIOStatistics;
651
652 #define BDRV_O_RDONLY 0x0000
653 #define BDRV_O_RDWR 0x0002
654 #define BDRV_O_ACCESS 0x0003
655 #define BDRV_O_CREAT 0x0004 /* create an empty file */
656 #define BDRV_O_SNAPSHOT 0x0008 /* open the file read only and save writes in a snapshot */
657 #define BDRV_O_FILE 0x0010 /* open as a raw file (do not try to
658 use a disk image format on top of
659 it (default for
660 bdrv_file_open()) */
661
662 void bdrv_init(void);
663 BlockDriver *bdrv_find_format(const char *format_name);
664 int bdrv_create(BlockDriver *drv,
665 const char *filename, int64_t size_in_sectors,
666 const char *backing_file, int flags);
667 BlockDriverState *bdrv_new(const char *device_name);
668 void bdrv_delete(BlockDriverState *bs);
669 int bdrv_file_open(BlockDriverState **pbs, const char *filename, int flags);
670 int bdrv_open(BlockDriverState *bs, const char *filename, int flags);
671 int bdrv_open2(BlockDriverState *bs, const char *filename, int flags,
672 BlockDriver *drv);
673 void bdrv_close(BlockDriverState *bs);
674 int bdrv_read(BlockDriverState *bs, int64_t sector_num,
675 uint8_t *buf, int nb_sectors);
676 int bdrv_write(BlockDriverState *bs, int64_t sector_num,
677 const uint8_t *buf, int nb_sectors);
678 int bdrv_pread(BlockDriverState *bs, int64_t offset,
679 void *buf, int count);
680 int bdrv_pwrite(BlockDriverState *bs, int64_t offset,
681 const void *buf, int count);
682 int bdrv_truncate(BlockDriverState *bs, int64_t offset);
683 int64_t bdrv_getlength(BlockDriverState *bs);
684 void bdrv_get_geometry(BlockDriverState *bs, int64_t *nb_sectors_ptr);
685 int bdrv_commit(BlockDriverState *bs);
686 void bdrv_set_boot_sector(BlockDriverState *bs, const uint8_t *data, int size);
687 void bdrv_flush_all(void);
688 /* async block I/O */
689 typedef struct BlockDriverAIOCB BlockDriverAIOCB;
690 typedef void BlockDriverCompletionFunc(void *opaque, int ret);
691
692 BlockDriverAIOCB *bdrv_aio_read(BlockDriverState *bs, int64_t sector_num,
693 uint8_t *buf, int nb_sectors,
694 BlockDriverCompletionFunc *cb, void *opaque);
695 BlockDriverAIOCB *bdrv_aio_write(BlockDriverState *bs, int64_t sector_num,
696 const uint8_t *buf, int nb_sectors,
697 BlockDriverCompletionFunc *cb, void *opaque);
698 void bdrv_aio_cancel(BlockDriverAIOCB *acb);
699
700 void qemu_aio_init(void);
701 void qemu_aio_poll(void);
702 void qemu_aio_flush(void);
703 void qemu_aio_wait_start(void);
704 void qemu_aio_wait(void);
705 void qemu_aio_wait_end(void);
706
707 int qemu_key_check(BlockDriverState *bs, const char *name);
708
709 /* Ensure contents are flushed to disk. */
710 void bdrv_flush(BlockDriverState *bs);
711
712 #define BDRV_TYPE_HD 0
713 #define BDRV_TYPE_CDROM 1
714 #define BDRV_TYPE_FLOPPY 2
715 #define BIOS_ATA_TRANSLATION_AUTO 0
716 #define BIOS_ATA_TRANSLATION_NONE 1
717 #define BIOS_ATA_TRANSLATION_LBA 2
718 #define BIOS_ATA_TRANSLATION_LARGE 3
719 #define BIOS_ATA_TRANSLATION_RECHS 4
720
721 void bdrv_set_geometry_hint(BlockDriverState *bs,
722 int cyls, int heads, int secs);
723 void bdrv_set_type_hint(BlockDriverState *bs, int type);
724 void bdrv_set_translation_hint(BlockDriverState *bs, int translation);
725 void bdrv_get_geometry_hint(BlockDriverState *bs,
726 int *pcyls, int *pheads, int *psecs);
727 int bdrv_get_type_hint(BlockDriverState *bs);
728 int bdrv_get_translation_hint(BlockDriverState *bs);
729 int bdrv_is_removable(BlockDriverState *bs);
730 int bdrv_is_read_only(BlockDriverState *bs);
731 int bdrv_is_inserted(BlockDriverState *bs);
732 int bdrv_media_changed(BlockDriverState *bs);
733 int bdrv_is_locked(BlockDriverState *bs);
734 void bdrv_set_locked(BlockDriverState *bs, int locked);
735 void bdrv_eject(BlockDriverState *bs, int eject_flag);
736 void bdrv_set_change_cb(BlockDriverState *bs,
737 void (*change_cb)(void *opaque), void *opaque);
738 void bdrv_get_format(BlockDriverState *bs, char *buf, int buf_size);
739 void bdrv_info(void);
740 BlockDriverState *bdrv_find(const char *name);
741 void bdrv_iterate(void (*it)(void *opaque, const char *name), void *opaque);
742 int bdrv_is_encrypted(BlockDriverState *bs);
743 int bdrv_set_key(BlockDriverState *bs, const char *key);
744 void bdrv_iterate_format(void (*it)(void *opaque, const char *name),
745 void *opaque);
746 const char *bdrv_get_device_name(BlockDriverState *bs);
747 int bdrv_write_compressed(BlockDriverState *bs, int64_t sector_num,
748 const uint8_t *buf, int nb_sectors);
749 int bdrv_get_info(BlockDriverState *bs, BlockDriverInfo *bdi);
750
751 void bdrv_get_backing_filename(BlockDriverState *bs,
752 char *filename, int filename_size);
753 int bdrv_snapshot_create(BlockDriverState *bs,
754 QEMUSnapshotInfo *sn_info);
755 int bdrv_snapshot_goto(BlockDriverState *bs,
756 const char *snapshot_id);
757 int bdrv_snapshot_delete(BlockDriverState *bs, const char *snapshot_id);
758 int bdrv_snapshot_list(BlockDriverState *bs,
759 QEMUSnapshotInfo **psn_info);
760 char *bdrv_snapshot_dump(char *buf, int buf_size, QEMUSnapshotInfo *sn);
761
762 char *get_human_readable_size(char *buf, int buf_size, int64_t size);
763 int path_is_absolute(const char *path);
764 void path_combine(char *dest, int dest_size,
765 const char *base_path,
766 const char *filename);
767
768 #ifndef QEMU_TOOL
769
770 typedef void QEMUMachineInitFunc(ram_addr_t ram_size, int vga_ram_size,
771 int boot_device,
772 DisplayState *ds, const char **fd_filename, int snapshot,
773 const char *kernel_filename, const char *kernel_cmdline,
774 const char *initrd_filename, const char *cpu_model);
775
776 typedef struct QEMUMachine {
777 const char *name;
778 const char *desc;
779 QEMUMachineInitFunc *init;
780 struct QEMUMachine *next;
781 } QEMUMachine;
782
783 int qemu_register_machine(QEMUMachine *m);
784
785 typedef void SetIRQFunc(void *opaque, int irq_num, int level);
786
787 #if defined(TARGET_PPC)
788 void ppc_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
789 #endif
790
791 #if defined(TARGET_MIPS)
792 void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...));
793 #endif
794
795 #include "hw/irq.h"
796
797 /* ISA bus */
798
799 extern target_phys_addr_t isa_mem_base;
800
801 typedef void (IOPortWriteFunc)(void *opaque, uint32_t address, uint32_t data);
802 typedef uint32_t (IOPortReadFunc)(void *opaque, uint32_t address);
803
804 int register_ioport_read(int start, int length, int size,
805 IOPortReadFunc *func, void *opaque);
806 int register_ioport_write(int start, int length, int size,
807 IOPortWriteFunc *func, void *opaque);
808 void isa_unassign_ioport(int start, int length);
809
810 void isa_mmio_init(target_phys_addr_t base, target_phys_addr_t size);
811
812 /* PCI bus */
813
814 extern target_phys_addr_t pci_mem_base;
815
816 typedef struct PCIBus PCIBus;
817 typedef struct PCIDevice PCIDevice;
818
819 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
820 uint32_t address, uint32_t data, int len);
821 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
822 uint32_t address, int len);
823 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
824 uint32_t addr, uint32_t size, int type);
825
826 #define PCI_ADDRESS_SPACE_MEM 0x00
827 #define PCI_ADDRESS_SPACE_IO 0x01
828 #define PCI_ADDRESS_SPACE_MEM_PREFETCH 0x08
829
830 typedef struct PCIIORegion {
831 uint32_t addr; /* current PCI mapping address. -1 means not mapped */
832 uint32_t size;
833 uint8_t type;
834 PCIMapIORegionFunc *map_func;
835 } PCIIORegion;
836
837 #define PCI_ROM_SLOT 6
838 #define PCI_NUM_REGIONS 7
839
840 #define PCI_DEVICES_MAX 64
841
842 #define PCI_VENDOR_ID 0x00 /* 16 bits */
843 #define PCI_DEVICE_ID 0x02 /* 16 bits */
844 #define PCI_COMMAND 0x04 /* 16 bits */
845 #define PCI_COMMAND_IO 0x1 /* Enable response in I/O space */
846 #define PCI_COMMAND_MEMORY 0x2 /* Enable response in Memory space */
847 #define PCI_CLASS_DEVICE 0x0a /* Device class */
848 #define PCI_INTERRUPT_LINE 0x3c /* 8 bits */
849 #define PCI_INTERRUPT_PIN 0x3d /* 8 bits */
850 #define PCI_MIN_GNT 0x3e /* 8 bits */
851 #define PCI_MAX_LAT 0x3f /* 8 bits */
852
853 struct PCIDevice {
854 /* PCI config space */
855 uint8_t config[256];
856
857 /* the following fields are read only */
858 PCIBus *bus;
859 int devfn;
860 char name[64];
861 PCIIORegion io_regions[PCI_NUM_REGIONS];
862
863 /* do not access the following fields */
864 PCIConfigReadFunc *config_read;
865 PCIConfigWriteFunc *config_write;
866 /* ??? This is a PC-specific hack, and should be removed. */
867 int irq_index;
868
869 /* IRQ objects for the INTA-INTD pins. */
870 qemu_irq *irq;
871
872 /* Current IRQ levels. Used internally by the generic PCI code. */
873 int irq_state[4];
874 };
875
876 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
877 int instance_size, int devfn,
878 PCIConfigReadFunc *config_read,
879 PCIConfigWriteFunc *config_write);
880
881 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
882 uint32_t size, int type,
883 PCIMapIORegionFunc *map_func);
884
885 uint32_t pci_default_read_config(PCIDevice *d,
886 uint32_t address, int len);
887 void pci_default_write_config(PCIDevice *d,
888 uint32_t address, uint32_t val, int len);
889 void pci_device_save(PCIDevice *s, QEMUFile *f);
890 int pci_device_load(PCIDevice *s, QEMUFile *f);
891
892 typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
893 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
894 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
895 qemu_irq *pic, int devfn_min, int nirq);
896
897 void pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
898 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
899 uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
900 int pci_bus_num(PCIBus *s);
901 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
902
903 void pci_info(void);
904 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
905 pci_map_irq_fn map_irq, const char *name);
906
907 /* prep_pci.c */
908 PCIBus *pci_prep_init(qemu_irq *pic);
909
910 /* grackle_pci.c */
911 PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic);
912
913 /* unin_pci.c */
914 PCIBus *pci_pmac_init(qemu_irq *pic);
915
916 /* apb_pci.c */
917 PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
918 qemu_irq *pic);
919
920 PCIBus *pci_vpb_init(qemu_irq *pic, int irq, int realview);
921
922 /* piix_pci.c */
923 PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
924 void i440fx_set_smm(PCIDevice *d, int val);
925 int piix3_init(PCIBus *bus, int devfn);
926 void i440fx_init_memory_mappings(PCIDevice *d);
927
928 int piix4_init(PCIBus *bus, int devfn);
929
930 /* openpic.c */
931 /* OpenPIC have 5 outputs per CPU connected and one IRQ out single output */
932 enum {
933 OPENPIC_OUTPUT_INT = 0, /* IRQ */
934 OPENPIC_OUTPUT_CINT, /* critical IRQ */
935 OPENPIC_OUTPUT_MCK, /* Machine check event */
936 OPENPIC_OUTPUT_DEBUG, /* Inconditional debug event */
937 OPENPIC_OUTPUT_RESET, /* Core reset event */
938 OPENPIC_OUTPUT_NB,
939 };
940 qemu_irq *openpic_init (PCIBus *bus, int *pmem_index, int nb_cpus,
941 qemu_irq **irqs, qemu_irq irq_out);
942
943 /* heathrow_pic.c */
944 qemu_irq *heathrow_pic_init(int *pmem_index);
945
946 /* gt64xxx.c */
947 PCIBus *pci_gt64120_init(qemu_irq *pic);
948
949 #ifdef HAS_AUDIO
950 struct soundhw {
951 const char *name;
952 const char *descr;
953 int enabled;
954 int isa;
955 union {
956 int (*init_isa) (AudioState *s, qemu_irq *pic);
957 int (*init_pci) (PCIBus *bus, AudioState *s);
958 } init;
959 };
960
961 extern struct soundhw soundhw[];
962 #endif
963
964 /* vga.c */
965
966 #ifndef TARGET_SPARC
967 #define VGA_RAM_SIZE (8192 * 1024)
968 #else
969 #define VGA_RAM_SIZE (9 * 1024 * 1024)
970 #endif
971
972 struct DisplayState {
973 uint8_t *data;
974 int linesize;
975 int depth;
976 int bgr; /* BGR color order instead of RGB. Only valid for depth == 32 */
977 int width;
978 int height;
979 void *opaque;
980 QEMUTimer *gui_timer;
981
982 void (*dpy_update)(struct DisplayState *s, int x, int y, int w, int h);
983 void (*dpy_resize)(struct DisplayState *s, int w, int h);
984 void (*dpy_refresh)(struct DisplayState *s);
985 void (*dpy_copy)(struct DisplayState *s, int src_x, int src_y,
986 int dst_x, int dst_y, int w, int h);
987 void (*dpy_fill)(struct DisplayState *s, int x, int y,
988 int w, int h, uint32_t c);
989 void (*mouse_set)(int x, int y, int on);
990 void (*cursor_define)(int width, int height, int bpp, int hot_x, int hot_y,
991 uint8_t *image, uint8_t *mask);
992 };
993
994 static inline void dpy_update(DisplayState *s, int x, int y, int w, int h)
995 {
996 s->dpy_update(s, x, y, w, h);
997 }
998
999 static inline void dpy_resize(DisplayState *s, int w, int h)
1000 {
1001 s->dpy_resize(s, w, h);
1002 }
1003
1004 int isa_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
1005 unsigned long vga_ram_offset, int vga_ram_size);
1006 int pci_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
1007 unsigned long vga_ram_offset, int vga_ram_size,
1008 unsigned long vga_bios_offset, int vga_bios_size);
1009 int isa_vga_mm_init(DisplayState *ds, uint8_t *vga_ram_base,
1010 unsigned long vga_ram_offset, int vga_ram_size,
1011 target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
1012 int it_shift);
1013
1014 /* cirrus_vga.c */
1015 void pci_cirrus_vga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
1016 unsigned long vga_ram_offset, int vga_ram_size);
1017 void isa_cirrus_vga_init(DisplayState *ds, uint8_t *vga_ram_base,
1018 unsigned long vga_ram_offset, int vga_ram_size);
1019
1020 /* vmware_vga.c */
1021 void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
1022 unsigned long vga_ram_offset, int vga_ram_size);
1023
1024 /* sdl.c */
1025 void sdl_display_init(DisplayState *ds, int full_screen, int no_frame);
1026
1027 /* cocoa.m */
1028 void cocoa_display_init(DisplayState *ds, int full_screen);
1029
1030 /* vnc.c */
1031 void vnc_display_init(DisplayState *ds);
1032 void vnc_display_close(DisplayState *ds);
1033 int vnc_display_open(DisplayState *ds, const char *display);
1034 int vnc_display_password(DisplayState *ds, const char *password);
1035 void do_info_vnc(void);
1036
1037 /* x_keymap.c */
1038 extern uint8_t _translate_keycode(const int key);
1039
1040 /* ide.c */
1041 #define MAX_DISKS 4
1042
1043 extern BlockDriverState *bs_table[MAX_DISKS + 1];
1044 extern BlockDriverState *sd_bdrv;
1045 extern BlockDriverState *mtd_bdrv;
1046
1047 void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
1048 BlockDriverState *hd0, BlockDriverState *hd1);
1049 void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
1050 int secondary_ide_enabled);
1051 void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
1052 qemu_irq *pic);
1053 void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
1054 qemu_irq *pic);
1055 int pmac_ide_init (BlockDriverState **hd_table, qemu_irq irq);
1056
1057 /* cdrom.c */
1058 int cdrom_read_toc(int nb_sectors, uint8_t *buf, int msf, int start_track);
1059 int cdrom_read_toc_raw(int nb_sectors, uint8_t *buf, int msf, int session_num);
1060
1061 /* ds1225y.c */
1062 typedef struct ds1225y_t ds1225y_t;
1063 ds1225y_t *ds1225y_init(target_phys_addr_t mem_base, const char *filename);
1064
1065 /* es1370.c */
1066 int es1370_init (PCIBus *bus, AudioState *s);
1067
1068 /* sb16.c */
1069 int SB16_init (AudioState *s, qemu_irq *pic);
1070
1071 /* adlib.c */
1072 int Adlib_init (AudioState *s, qemu_irq *pic);
1073
1074 /* gus.c */
1075 int GUS_init (AudioState *s, qemu_irq *pic);
1076
1077 /* dma.c */
1078 typedef int (*DMA_transfer_handler) (void *opaque, int nchan, int pos, int size);
1079 int DMA_get_channel_mode (int nchan);
1080 int DMA_read_memory (int nchan, void *buf, int pos, int size);
1081 int DMA_write_memory (int nchan, void *buf, int pos, int size);
1082 void DMA_hold_DREQ (int nchan);
1083 void DMA_release_DREQ (int nchan);
1084 void DMA_schedule(int nchan);
1085 void DMA_run (void);
1086 void DMA_init (int high_page_enable);
1087 void DMA_register_channel (int nchan,
1088 DMA_transfer_handler transfer_handler,
1089 void *opaque);
1090 /* fdc.c */
1091 #define MAX_FD 2
1092 extern BlockDriverState *fd_table[MAX_FD];
1093
1094 typedef struct fdctrl_t fdctrl_t;
1095
1096 fdctrl_t *fdctrl_init (qemu_irq irq, int dma_chann, int mem_mapped,
1097 target_phys_addr_t io_base,
1098 BlockDriverState **fds);
1099 int fdctrl_get_drive_type(fdctrl_t *fdctrl, int drive_num);
1100
1101 /* eepro100.c */
1102
1103 void pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
1104 void pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
1105 void pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
1106
1107 /* ne2000.c */
1108
1109 void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
1110 void pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
1111
1112 /* rtl8139.c */
1113
1114 void pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
1115
1116 /* pcnet.c */
1117
1118 void pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
1119 void lance_init(NICInfo *nd, target_phys_addr_t leaddr, void *dma_opaque,
1120 qemu_irq irq, qemu_irq *reset);
1121
1122 /* vmmouse.c */
1123 void *vmmouse_init(void *m);
1124
1125 /* vmport.c */
1126 #ifdef TARGET_I386
1127 void vmport_init(CPUState *env);
1128 void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
1129 #endif
1130
1131 /* pckbd.c */
1132
1133 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
1134 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
1135 target_phys_addr_t base, int it_shift);
1136
1137 /* mc146818rtc.c */
1138
1139 typedef struct RTCState RTCState;
1140
1141 RTCState *rtc_init(int base, qemu_irq irq);
1142 RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq);
1143 void rtc_set_memory(RTCState *s, int addr, int val);
1144 void rtc_set_date(RTCState *s, const struct tm *tm);
1145
1146 /* serial.c */
1147
1148 typedef struct SerialState SerialState;
1149 SerialState *serial_init(int base, qemu_irq irq, CharDriverState *chr);
1150 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
1151 qemu_irq irq, CharDriverState *chr,
1152 int ioregister);
1153 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
1154 void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
1155 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
1156 void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
1157 uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
1158 void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
1159
1160 /* parallel.c */
1161
1162 typedef struct ParallelState ParallelState;
1163 ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
1164 ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
1165
1166 /* i8259.c */
1167
1168 typedef struct PicState2 PicState2;
1169 extern PicState2 *isa_pic;
1170 void pic_set_irq(int irq, int level);
1171 void pic_set_irq_new(void *opaque, int irq, int level);
1172 qemu_irq *i8259_init(qemu_irq parent_irq);
1173 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
1174 void *alt_irq_opaque);
1175 int pic_read_irq(PicState2 *s);
1176 void pic_update_irq(PicState2 *s);
1177 uint32_t pic_intack_read(PicState2 *s);
1178 void pic_info(void);
1179 void irq_info(void);
1180
1181 /* APIC */
1182 typedef struct IOAPICState IOAPICState;
1183
1184 int apic_init(CPUState *env);
1185 int apic_get_interrupt(CPUState *env);
1186 int apic_accept_pic_intr(CPUState *env);
1187 IOAPICState *ioapic_init(void);
1188 void ioapic_set_irq(void *opaque, int vector, int level);
1189
1190 /* i8254.c */
1191
1192 #define PIT_FREQ 1193182
1193
1194 typedef struct PITState PITState;
1195
1196 PITState *pit_init(int base, qemu_irq irq);
1197 void pit_set_gate(PITState *pit, int channel, int val);
1198 int pit_get_gate(PITState *pit, int channel);
1199 int pit_get_initial_count(PITState *pit, int channel);
1200 int pit_get_mode(PITState *pit, int channel);
1201 int pit_get_out(PITState *pit, int channel, int64_t current_time);
1202
1203 /* jazz_led.c */
1204 extern void jazz_led_init(DisplayState *ds, target_phys_addr_t base);
1205
1206 /* pcspk.c */
1207 void pcspk_init(PITState *);
1208 int pcspk_audio_init(AudioState *, qemu_irq *pic);
1209
1210 #include "hw/i2c.h"
1211
1212 #include "hw/smbus.h"
1213
1214 /* acpi.c */
1215 extern int acpi_enabled;
1216 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base);
1217 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
1218 void acpi_bios_init(void);
1219
1220 /* pc.c */
1221 extern QEMUMachine pc_machine;
1222 extern QEMUMachine isapc_machine;
1223 extern int fd_bootchk;
1224
1225 void ioport_set_a20(int enable);
1226 int ioport_get_a20(void);
1227
1228 /* ipf.c*/
1229 extern QEMUMachine ipf_machine;
1230
1231 /* ppc.c */
1232 extern QEMUMachine prep_machine;
1233 extern QEMUMachine core99_machine;
1234 extern QEMUMachine heathrow_machine;
1235 extern QEMUMachine ref405ep_machine;
1236 extern QEMUMachine taihu_machine;
1237
1238 /* mips_r4k.c */
1239 extern QEMUMachine mips_machine;
1240
1241 /* mips_malta.c */
1242 extern QEMUMachine mips_malta_machine;
1243
1244 /* mips_int.c */
1245 extern void cpu_mips_irq_init_cpu(CPUState *env);
1246
1247 /* mips_pica61.c */
1248 extern QEMUMachine mips_pica61_machine;
1249
1250 /* mips_timer.c */
1251 extern void cpu_mips_clock_init(CPUState *);
1252 extern void cpu_mips_irqctrl_init (void);
1253
1254 /* shix.c */
1255 extern QEMUMachine shix_machine;
1256
1257 /* r2d.c */
1258 extern QEMUMachine r2d_machine;
1259
1260 #ifdef TARGET_PPC
1261 /* PowerPC hardware exceptions management helpers */
1262 typedef void (*clk_setup_cb)(void *opaque, uint32_t freq);
1263 typedef struct clk_setup_t clk_setup_t;
1264 struct clk_setup_t {
1265 clk_setup_cb cb;
1266 void *opaque;
1267 };
1268 static inline void clk_setup (clk_setup_t *clk, uint32_t freq)
1269 {
1270 if (clk->cb != NULL)
1271 (*clk->cb)(clk->opaque, freq);
1272 }
1273
1274 clk_setup_cb cpu_ppc_tb_init (CPUState *env, uint32_t freq);
1275 /* Embedded PowerPC DCR management */
1276 typedef target_ulong (*dcr_read_cb)(void *opaque, int dcrn);
1277 typedef void (*dcr_write_cb)(void *opaque, int dcrn, target_ulong val);
1278 int ppc_dcr_init (CPUState *env, int (*dcr_read_error)(int dcrn),
1279 int (*dcr_write_error)(int dcrn));
1280 int ppc_dcr_register (CPUState *env, int dcrn, void *opaque,
1281 dcr_read_cb drc_read, dcr_write_cb dcr_write);
1282 clk_setup_cb ppc_emb_timers_init (CPUState *env, uint32_t freq);
1283 /* Embedded PowerPC reset */
1284 void ppc40x_core_reset (CPUState *env);
1285 void ppc40x_chip_reset (CPUState *env);
1286 void ppc40x_system_reset (CPUState *env);
1287 #endif
1288 void PREP_debug_write (void *opaque, uint32_t addr, uint32_t val);
1289
1290 extern CPUWriteMemoryFunc *PPC_io_write[];
1291 extern CPUReadMemoryFunc *PPC_io_read[];
1292 void PPC_debug_write (void *opaque, uint32_t addr, uint32_t val);
1293
1294 /* sun4m.c */
1295 extern QEMUMachine ss5_machine, ss10_machine;
1296
1297 /* iommu.c */
1298 void *iommu_init(target_phys_addr_t addr);
1299 void sparc_iommu_memory_rw(void *opaque, target_phys_addr_t addr,
1300 uint8_t *buf, int len, int is_write);
1301 static inline void sparc_iommu_memory_read(void *opaque,
1302 target_phys_addr_t addr,
1303 uint8_t *buf, int len)
1304 {
1305 sparc_iommu_memory_rw(opaque, addr, buf, len, 0);
1306 }
1307
1308 static inline void sparc_iommu_memory_write(void *opaque,
1309 target_phys_addr_t addr,
1310 uint8_t *buf, int len)
1311 {
1312 sparc_iommu_memory_rw(opaque, addr, buf, len, 1);
1313 }
1314
1315 /* tcx.c */
1316 void tcx_init(DisplayState *ds, target_phys_addr_t addr, uint8_t *vram_base,
1317 unsigned long vram_offset, int vram_size, int width, int height,
1318 int depth);
1319
1320 /* slavio_intctl.c */
1321 void *slavio_intctl_init(target_phys_addr_t addr, target_phys_addr_t addrg,
1322 const uint32_t *intbit_to_level,
1323 qemu_irq **irq, qemu_irq **cpu_irq,
1324 qemu_irq **parent_irq, unsigned int cputimer);
1325 void slavio_pic_info(void *opaque);
1326 void slavio_irq_info(void *opaque);
1327
1328 /* loader.c */
1329 int get_image_size(const char *filename);
1330 int load_image(const char *filename, uint8_t *addr);
1331 int load_elf(const char *filename, int64_t virt_to_phys_addend,
1332 uint64_t *pentry, uint64_t *lowaddr, uint64_t *highaddr);
1333 int load_aout(const char *filename, uint8_t *addr);
1334 int load_uboot(const char *filename, target_ulong *ep, int *is_linux);
1335
1336 /* slavio_timer.c */
1337 void slavio_timer_init(target_phys_addr_t addr, qemu_irq irq, int mode);
1338
1339 /* slavio_serial.c */
1340 SerialState *slavio_serial_init(target_phys_addr_t base, qemu_irq irq,
1341 CharDriverState *chr1, CharDriverState *chr2);
1342 void slavio_serial_ms_kbd_init(target_phys_addr_t base, qemu_irq irq);
1343
1344 /* slavio_misc.c */
1345 void *slavio_misc_init(target_phys_addr_t base, target_phys_addr_t power_base,
1346 qemu_irq irq);
1347 void slavio_set_power_fail(void *opaque, int power_failing);
1348
1349 /* esp.c */
1350 void esp_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1351 void *esp_init(BlockDriverState **bd, target_phys_addr_t espaddr,
1352 void *dma_opaque, qemu_irq irq, qemu_irq *reset);
1353
1354 /* sparc32_dma.c */
1355 void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
1356 void *iommu, qemu_irq **dev_irq, qemu_irq **reset);
1357 void ledma_memory_read(void *opaque, target_phys_addr_t addr,
1358 uint8_t *buf, int len, int do_bswap);
1359 void ledma_memory_write(void *opaque, target_phys_addr_t addr,
1360 uint8_t *buf, int len, int do_bswap);
1361 void espdma_memory_read(void *opaque, uint8_t *buf, int len);
1362 void espdma_memory_write(void *opaque, uint8_t *buf, int len);
1363
1364 /* cs4231.c */
1365 void cs_init(target_phys_addr_t base, int irq, void *intctl);
1366
1367 /* sun4u.c */
1368 extern QEMUMachine sun4u_machine;
1369
1370 /* NVRAM helpers */
1371 #include "hw/m48t59.h"
1372
1373 void NVRAM_set_byte (m48t59_t *nvram, uint32_t addr, uint8_t value);
1374 uint8_t NVRAM_get_byte (m48t59_t *nvram, uint32_t addr);
1375 void NVRAM_set_word (m48t59_t *nvram, uint32_t addr, uint16_t value);
1376 uint16_t NVRAM_get_word (m48t59_t *nvram, uint32_t addr);
1377 void NVRAM_set_lword (m48t59_t *nvram, uint32_t addr, uint32_t value);
1378 uint32_t NVRAM_get_lword (m48t59_t *nvram, uint32_t addr);
1379 void NVRAM_set_string (m48t59_t *nvram, uint32_t addr,
1380 const unsigned char *str, uint32_t max);
1381 int NVRAM_get_string (m48t59_t *nvram, uint8_t *dst, uint16_t addr, int max);
1382 void NVRAM_set_crc (m48t59_t *nvram, uint32_t addr,
1383 uint32_t start, uint32_t count);
1384 int PPC_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
1385 const unsigned char *arch,
1386 uint32_t RAM_size, int boot_device,
1387 uint32_t kernel_image, uint32_t kernel_size,
1388 const char *cmdline,
1389 uint32_t initrd_image, uint32_t initrd_size,
1390 uint32_t NVRAM_image,
1391 int width, int height, int depth);
1392
1393 /* adb.c */
1394
1395 #define MAX_ADB_DEVICES 16
1396
1397 #define ADB_MAX_OUT_LEN 16
1398
1399 typedef struct ADBDevice ADBDevice;
1400
1401 /* hypercall.c */
1402
1403 void pci_hypercall_init(PCIBus *bus);
1404 void vmchannel_init(CharDriverState *hd, uint32_t deviceid, uint32_t index);
1405
1406 /* buf = NULL means polling */
1407 typedef int ADBDeviceRequest(ADBDevice *d, uint8_t *buf_out,
1408 const uint8_t *buf, int len);
1409 typedef int ADBDeviceReset(ADBDevice *d);
1410
1411 struct ADBDevice {
1412 struct ADBBusState *bus;
1413 int devaddr;
1414 int handler;
1415 ADBDeviceRequest *devreq;
1416 ADBDeviceReset *devreset;
1417 void *opaque;
1418 };
1419
1420 typedef struct ADBBusState {
1421 ADBDevice devices[MAX_ADB_DEVICES];
1422 int nb_devices;
1423 int poll_index;
1424 } ADBBusState;
1425
1426 int adb_request(ADBBusState *s, uint8_t *buf_out,
1427 const uint8_t *buf, int len);
1428 int adb_poll(ADBBusState *s, uint8_t *buf_out);
1429
1430 ADBDevice *adb_register_device(ADBBusState *s, int devaddr,
1431 ADBDeviceRequest *devreq,
1432 ADBDeviceReset *devreset,
1433 void *opaque);
1434 void adb_kbd_init(ADBBusState *bus);
1435 void adb_mouse_init(ADBBusState *bus);
1436
1437 /* cuda.c */
1438
1439 extern ADBBusState adb_bus;
1440 int cuda_init(qemu_irq irq);
1441
1442 #include "hw/usb.h"
1443
1444 /* usb ports of the VM */
1445
1446 void qemu_register_usb_port(USBPort *port, void *opaque, int index,
1447 usb_attachfn attach);
1448
1449 #define VM_USB_HUB_SIZE 8
1450
1451 void do_usb_add(const char *devname);
1452 void do_usb_del(const char *devname);
1453 void usb_info(void);
1454
1455 /* scsi-disk.c */
1456 enum scsi_reason {
1457 SCSI_REASON_DONE, /* Command complete. */
1458 SCSI_REASON_DATA /* Transfer complete, more data required. */
1459 };
1460
1461 typedef struct SCSIDevice SCSIDevice;
1462 typedef void (*scsi_completionfn)(void *opaque, int reason, uint32_t tag,
1463 uint32_t arg);
1464
1465 SCSIDevice *scsi_disk_init(BlockDriverState *bdrv,
1466 int tcq,
1467 scsi_completionfn completion,
1468 void *opaque);
1469 void scsi_disk_destroy(SCSIDevice *s);
1470
1471 int32_t scsi_send_command(SCSIDevice *s, uint32_t tag, uint8_t *buf, int lun);
1472 /* SCSI data transfers are asynchrnonous. However, unlike the block IO
1473 layer the completion routine may be called directly by
1474 scsi_{read,write}_data. */
1475 void scsi_read_data(SCSIDevice *s, uint32_t tag);
1476 int scsi_write_data(SCSIDevice *s, uint32_t tag);
1477 void scsi_cancel_io(SCSIDevice *s, uint32_t tag);
1478 uint8_t *scsi_get_buf(SCSIDevice *s, uint32_t tag);
1479
1480 /* lsi53c895a.c */
1481 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
1482 void *lsi_scsi_init(PCIBus *bus, int devfn);
1483
1484 /* integratorcp.c */
1485 extern QEMUMachine integratorcp_machine;
1486
1487 /* versatilepb.c */
1488 extern QEMUMachine versatilepb_machine;
1489 extern QEMUMachine versatileab_machine;
1490
1491 /* realview.c */
1492 extern QEMUMachine realview_machine;
1493
1494 /* spitz.c */
1495 extern QEMUMachine akitapda_machine;
1496 extern QEMUMachine spitzpda_machine;
1497 extern QEMUMachine borzoipda_machine;
1498 extern QEMUMachine terrierpda_machine;
1499
1500 /* palm.c */
1501 extern QEMUMachine palmte_machine;
1502
1503 /* ps2.c */
1504 void *ps2_kbd_init(void (*update_irq)(void *, int), void *update_arg);
1505 void *ps2_mouse_init(void (*update_irq)(void *, int), void *update_arg);
1506 void ps2_write_mouse(void *, int val);
1507 void ps2_write_keyboard(void *, int val);
1508 uint32_t ps2_read_data(void *);
1509 void ps2_queue(void *, int b);
1510 void ps2_keyboard_set_translation(void *opaque, int mode);
1511 void ps2_mouse_fake_event(void *opaque);
1512
1513 /* smc91c111.c */
1514 void smc91c111_init(NICInfo *, uint32_t, qemu_irq);
1515
1516 /* pl031.c */
1517 void pl031_init(uint32_t base, qemu_irq irq);
1518
1519 /* pl110.c */
1520 void *pl110_init(DisplayState *ds, uint32_t base, qemu_irq irq, int);
1521
1522 /* pl011.c */
1523 void pl011_init(uint32_t base, qemu_irq irq, CharDriverState *chr);
1524
1525 /* pl050.c */
1526 void pl050_init(uint32_t base, qemu_irq irq, int is_mouse);
1527
1528 /* pl080.c */
1529 void *pl080_init(uint32_t base, qemu_irq irq, int nchannels);
1530
1531 /* pl181.c */
1532 void pl181_init(uint32_t base, BlockDriverState *bd,
1533 qemu_irq irq0, qemu_irq irq1);
1534
1535 /* pl190.c */
1536 qemu_irq *pl190_init(uint32_t base, qemu_irq irq, qemu_irq fiq);
1537
1538 /* arm-timer.c */
1539 void sp804_init(uint32_t base, qemu_irq irq);
1540 void icp_pit_init(uint32_t base, qemu_irq *pic, int irq);
1541
1542 /* arm_sysctl.c */
1543 void arm_sysctl_init(uint32_t base, uint32_t sys_id);
1544
1545 /* arm_gic.c */
1546 qemu_irq *arm_gic_init(uint32_t base, qemu_irq parent_irq);
1547
1548 /* arm_boot.c */
1549
1550 void arm_load_kernel(CPUState *env, int ram_size, const char *kernel_filename,
1551 const char *kernel_cmdline, const char *initrd_filename,
1552 int board_id, target_phys_addr_t loader_start);
1553
1554 /* sh7750.c */
1555 struct SH7750State;
1556
1557 struct SH7750State *sh7750_init(CPUState * cpu);
1558
1559 typedef struct {
1560 /* The callback will be triggered if any of the designated lines change */
1561 uint16_t portamask_trigger;
1562 uint16_t portbmask_trigger;
1563 /* Return 0 if no action was taken */
1564 int (*port_change_cb) (uint16_t porta, uint16_t portb,
1565 uint16_t * periph_pdtra,
1566 uint16_t * periph_portdira,
1567 uint16_t * periph_pdtrb,
1568 uint16_t * periph_portdirb);
1569 } sh7750_io_device;
1570
1571 int sh7750_register_io_device(struct SH7750State *s,
1572 sh7750_io_device * device);
1573 /* sh_timer.c */
1574 #define TMU012_FEAT_TOCR (1 << 0)
1575 #define TMU012_FEAT_3CHAN (1 << 1)
1576 #define TMU012_FEAT_EXTCLK (1 << 2)
1577 void tmu012_init(uint32_t base, int feat, uint32_t freq);
1578
1579 /* sh_serial.c */
1580 #define SH_SERIAL_FEAT_SCIF (1 << 0)
1581 void sh_serial_init (target_phys_addr_t base, int feat,
1582 uint32_t freq, CharDriverState *chr);
1583
1584 /* tc58128.c */
1585 int tc58128_init(struct SH7750State *s, char *zone1, char *zone2);
1586
1587 /* NOR flash devices */
1588 #define MAX_PFLASH 4
1589 extern BlockDriverState *pflash_table[MAX_PFLASH];
1590 typedef struct pflash_t pflash_t;
1591
1592 pflash_t *pflash_register (target_phys_addr_t base, ram_addr_t off,
1593 BlockDriverState *bs,
1594 uint32_t sector_len, int nb_blocs, int width,
1595 uint16_t id0, uint16_t id1,
1596 uint16_t id2, uint16_t id3);
1597
1598 /* nand.c */
1599 struct nand_flash_s;
1600 struct nand_flash_s *nand_init(int manf_id, int chip_id);
1601 void nand_done(struct nand_flash_s *s);
1602 void nand_setpins(struct nand_flash_s *s,
1603 int cle, int ale, int ce, int wp, int gnd);
1604 void nand_getpins(struct nand_flash_s *s, int *rb);
1605 void nand_setio(struct nand_flash_s *s, uint8_t value);
1606 uint8_t nand_getio(struct nand_flash_s *s);
1607
1608 #define NAND_MFR_TOSHIBA 0x98
1609 #define NAND_MFR_SAMSUNG 0xec
1610 #define NAND_MFR_FUJITSU 0x04
1611 #define NAND_MFR_NATIONAL 0x8f
1612 #define NAND_MFR_RENESAS 0x07
1613 #define NAND_MFR_STMICRO 0x20
1614 #define NAND_MFR_HYNIX 0xad
1615 #define NAND_MFR_MICRON 0x2c
1616
1617 /* ecc.c */
1618 struct ecc_state_s {
1619 uint8_t cp; /* Column parity */
1620 uint16_t lp[2]; /* Line parity */
1621 uint16_t count;
1622 };
1623
1624 uint8_t ecc_digest(struct ecc_state_s *s, uint8_t sample);
1625 void ecc_reset(struct ecc_state_s *s);
1626 void ecc_put(QEMUFile *f, struct ecc_state_s *s);
1627 void ecc_get(QEMUFile *f, struct ecc_state_s *s);
1628
1629 /* GPIO */
1630 typedef void (*gpio_handler_t)(int line, int level, void *opaque);
1631
1632 /* ads7846.c */
1633 struct ads7846_state_s;
1634 uint32_t ads7846_read(void *opaque);
1635 void ads7846_write(void *opaque, uint32_t value);
1636 struct ads7846_state_s *ads7846_init(qemu_irq penirq);
1637
1638 /* max111x.c */
1639 struct max111x_s;
1640 uint32_t max111x_read(void *opaque);
1641 void max111x_write(void *opaque, uint32_t value);
1642 struct max111x_s *max1110_init(qemu_irq cb);
1643 struct max111x_s *max1111_init(qemu_irq cb);
1644 void max111x_set_input(struct max111x_s *s, int line, uint8_t value);
1645
1646 /* PCMCIA/Cardbus */
1647
1648 struct pcmcia_socket_s {
1649 qemu_irq irq;
1650 int attached;
1651 const char *slot_string;
1652 const char *card_string;
1653 };
1654
1655 void pcmcia_socket_register(struct pcmcia_socket_s *socket);
1656 void pcmcia_socket_unregister(struct pcmcia_socket_s *socket);
1657 void pcmcia_info(void);
1658
1659 struct pcmcia_card_s {
1660 void *state;
1661 struct pcmcia_socket_s *slot;
1662 int (*attach)(void *state);
1663 int (*detach)(void *state);
1664 const uint8_t *cis;
1665 int cis_len;
1666
1667 /* Only valid if attached */
1668 uint8_t (*attr_read)(void *state, uint32_t address);
1669 void (*attr_write)(void *state, uint32_t address, uint8_t value);
1670 uint16_t (*common_read)(void *state, uint32_t address);
1671 void (*common_write)(void *state, uint32_t address, uint16_t value);
1672 uint16_t (*io_read)(void *state, uint32_t address);
1673 void (*io_write)(void *state, uint32_t address, uint16_t value);
1674 };
1675
1676 #define CISTPL_DEVICE 0x01 /* 5V Device Information Tuple */
1677 #define CISTPL_NO_LINK 0x14 /* No Link Tuple */
1678 #define CISTPL_VERS_1 0x15 /* Level 1 Version Tuple */
1679 #define CISTPL_JEDEC_C 0x18 /* JEDEC ID Tuple */
1680 #define CISTPL_JEDEC_A 0x19 /* JEDEC ID Tuple */
1681 #define CISTPL_CONFIG 0x1a /* Configuration Tuple */
1682 #define CISTPL_CFTABLE_ENTRY 0x1b /* 16-bit PCCard Configuration */
1683 #define CISTPL_DEVICE_OC 0x1c /* Additional Device Information */
1684 #define CISTPL_DEVICE_OA 0x1d /* Additional Device Information */
1685 #define CISTPL_DEVICE_GEO 0x1e /* Additional Device Information */
1686 #define CISTPL_DEVICE_GEO_A 0x1f /* Additional Device Information */
1687 #define CISTPL_MANFID 0x20 /* Manufacture ID Tuple */
1688 #define CISTPL_FUNCID 0x21 /* Function ID Tuple */
1689 #define CISTPL_FUNCE 0x22 /* Function Extension Tuple */
1690 #define CISTPL_END 0xff /* Tuple End */
1691 #define CISTPL_ENDMARK 0xff
1692
1693 /* dscm1xxxx.c */
1694 struct pcmcia_card_s *dscm1xxxx_init(BlockDriverState *bdrv);
1695
1696 /* ptimer.c */
1697 typedef struct ptimer_state ptimer_state;
1698 typedef void (*ptimer_cb)(void *opaque);
1699
1700 ptimer_state *ptimer_init(QEMUBH *bh);
1701 void ptimer_set_period(ptimer_state *s, int64_t period);
1702 void ptimer_set_freq(ptimer_state *s, uint32_t freq);
1703 void ptimer_set_limit(ptimer_state *s, uint64_t limit, int reload);
1704 uint64_t ptimer_get_count(ptimer_state *s);
1705 void ptimer_set_count(ptimer_state *s, uint64_t count);
1706 void ptimer_run(ptimer_state *s, int oneshot);
1707 void ptimer_stop(ptimer_state *s);
1708 void qemu_put_ptimer(QEMUFile *f, ptimer_state *s);
1709 void qemu_get_ptimer(QEMUFile *f, ptimer_state *s);
1710
1711 #include "hw/pxa.h"
1712
1713 #include "hw/omap.h"
1714
1715 /* mcf_uart.c */
1716 uint32_t mcf_uart_read(void *opaque, target_phys_addr_t addr);
1717 void mcf_uart_write(void *opaque, target_phys_addr_t addr, uint32_t val);
1718 void *mcf_uart_init(qemu_irq irq, CharDriverState *chr);
1719 void mcf_uart_mm_init(target_phys_addr_t base, qemu_irq irq,
1720 CharDriverState *chr);
1721
1722 /* mcf_intc.c */
1723 qemu_irq *mcf_intc_init(target_phys_addr_t base, CPUState *env);
1724
1725 /* mcf_fec.c */
1726 void mcf_fec_init(NICInfo *nd, target_phys_addr_t base, qemu_irq *irq);
1727
1728 /* mcf5206.c */
1729 qemu_irq *mcf5206_init(uint32_t base, CPUState *env);
1730
1731 /* an5206.c */
1732 extern QEMUMachine an5206_machine;
1733
1734 /* mcf5208.c */
1735 extern QEMUMachine mcf5208evb_machine;
1736
1737 #include "gdbstub.h"
1738
1739 #endif /* defined(QEMU_TOOL) */
1740
1741 /* migration.c */
1742 void do_info_migration(void);
1743 void do_migrate(int detach, const char *uri);
1744 void do_migrate_cancel(void);
1745 void do_migrate_set_speed(const char *value);
1746 int migrate_incoming(const char *device);
1747
1748 /* monitor.c */
1749 void monitor_init(CharDriverState *hd, int show_banner);
1750 void term_puts(const char *str);
1751 void term_vprintf(const char *fmt, va_list ap);
1752 void term_printf(const char *fmt, ...) __attribute__ ((__format__ (__printf__, 1, 2)));
1753 void term_print_filename(const char *filename);
1754 void term_flush(void);
1755 void term_print_help(void);
1756 void monitor_readline(const char *prompt, int is_password,
1757 char *buf, int buf_size);
1758 void monitor_suspend(void);
1759 void monitor_resume(void);
1760
1761 /* readline.c */
1762 typedef void ReadLineFunc(void *opaque, const char *str);
1763
1764 extern int completion_index;
1765 void add_completion(const char *str);
1766 void readline_handle_byte(int ch);
1767 void readline_find_completion(const char *cmdline);
1768 const char *readline_get_history(unsigned int index);
1769 void readline_start(const char *prompt, int is_password,
1770 ReadLineFunc *readline_func, void *opaque);
1771
1772 void kqemu_record_dump(void);
1773
1774 #endif /* VL_H */
AMD IOMMU emulation for KVM