target-i386/kvm.c

   1 /*
   2  * QEMU KVM support
   3  *
   4  * Copyright (C) 2006-2008 Qumranet Technologies
   5  * Copyright IBM, Corp. 2008
   6  *
   7  * Authors:
   8  *  Anthony Liguori   <aliguori@us.ibm.com>
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2 or later.
  11  * See the COPYING file in the top-level directory.
  12  *
  13  */
  14
  15 #include <sys/types.h>
  16 #include <sys/ioctl.h>
  17 #include <sys/mman.h>
  18
  19 #include <linux/kvm.h>
  20
  21 #include "qemu-common.h"
  22 #include "sysemu.h"
  23 #include "kvm.h"
  24 #include "cpu.h"
  25 #include "gdbstub.h"
  26 #include "host-utils.h"
  27 #include "hw/pc.h"
  28 #include "ioport.h"
  29
  30 #ifdef CONFIG_KVM_PARA
  31 #include <linux/kvm_para.h>
  32 #endif
  33 //
  34 //#define DEBUG_KVM
  35
  36 #ifdef DEBUG_KVM
  37 #define DPRINTF(fmt, ...) \
  38     do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
  39 #else
  40 #define DPRINTF(fmt, ...) \
  41     do { } while (0)
  42 #endif
  43
  44 #define MSR_KVM_WALL_CLOCK  0x11
  45 #define MSR_KVM_SYSTEM_TIME 0x12
  46
  47 #ifdef KVM_CAP_EXT_CPUID
  48
  49 static struct kvm_cpuid2 *try_get_cpuid(KVMState *s, int max)
  50 {
  51     struct kvm_cpuid2 *cpuid;
  52     int r, size;
  53
  54     size = sizeof(*cpuid) + max * sizeof(*cpuid->entries);
  55     cpuid = (struct kvm_cpuid2 *)qemu_mallocz(size);
  56     cpuid->nent = max;
  57     r = kvm_ioctl(s, KVM_GET_SUPPORTED_CPUID, cpuid);
  58     if (r == 0 && cpuid->nent >= max) {
  59         r = -E2BIG;
  60     }
  61     if (r < 0) {
  62         if (r == -E2BIG) {
  63             qemu_free(cpuid);
  64             return NULL;
  65         } else {
  66             fprintf(stderr, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
  67                     strerror(-r));
  68             exit(1);
  69         }
  70     }
  71     return cpuid;
  72 }
  73
  74 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
  75                                       uint32_t index, int reg)
  76 {
  77     struct kvm_cpuid2 *cpuid;
  78     int i, max;
  79     uint32_t ret = 0;
  80     uint32_t cpuid_1_edx;
  81
  82     if (!kvm_check_extension(env->kvm_state, KVM_CAP_EXT_CPUID)) {
  83         return -1U;
  84     }
  85
  86     max = 1;
  87     while ((cpuid = try_get_cpuid(env->kvm_state, max)) == NULL) {
  88         max *= 2;
  89     }
  90
  91     for (i = 0; i < cpuid->nent; ++i) {
  92         if (cpuid->entries[i].function == function &&
  93             cpuid->entries[i].index == index) {
  94             switch (reg) {
  95             case R_EAX:
  96                 ret = cpuid->entries[i].eax;
  97                 break;
  98             case R_EBX:
  99                 ret = cpuid->entries[i].ebx;
 100                 break;
 101             case R_ECX:
 102                 ret = cpuid->entries[i].ecx;
 103                 break;
 104             case R_EDX:
 105                 ret = cpuid->entries[i].edx;
 106                 switch (function) {
 107                 case 1:
 108                     /* KVM before 2.6.30 misreports the following features */
 109                     ret |= CPUID_MTRR | CPUID_PAT | CPUID_MCE | CPUID_MCA;
 110                     break;
 111                 case 0x80000001:
 112                     /* On Intel, kvm returns cpuid according to the Intel spec,
 113                      * so add missing bits according to the AMD spec:
 114                      */
 115                     cpuid_1_edx = kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 116                     ret |= cpuid_1_edx & 0x183f7ff;
 117                     break;
 118                 }
 119                 break;
 120             }
 121         }
 122     }
 123
 124     qemu_free(cpuid);
 125
 126     return ret;
 127 }
 128
 129 #else
 130
 131 uint32_t kvm_arch_get_supported_cpuid(CPUState *env, uint32_t function,
 132                                       uint32_t index, int reg)
 133 {
 134     return -1U;
 135 }
 136
 137 #endif
 138
 139 #ifdef CONFIG_KVM_PARA
 140 struct kvm_para_features {
 141         int cap;
 142         int feature;
 143 } para_features[] = {
 144 #ifdef KVM_CAP_CLOCKSOURCE
 145         { KVM_CAP_CLOCKSOURCE, KVM_FEATURE_CLOCKSOURCE },
 146 #endif
 147 #ifdef KVM_CAP_NOP_IO_DELAY
 148         { KVM_CAP_NOP_IO_DELAY, KVM_FEATURE_NOP_IO_DELAY },
 149 #endif
 150 #ifdef KVM_CAP_PV_MMU
 151         { KVM_CAP_PV_MMU, KVM_FEATURE_MMU_OP },
 152 #endif
 153         { -1, -1 }
 154 };
 155
 156 static int get_para_features(CPUState *env)
 157 {
 158         int i, features = 0;
 159
 160         for (i = 0; i < ARRAY_SIZE(para_features) - 1; i++) {
 161                 if (kvm_check_extension(env->kvm_state, para_features[i].cap))
 162                         features |= (1 << para_features[i].feature);
 163         }
 164
 165         return features;
 166 }
 167 #endif
 168
 169 static int _kvm_arch_init_vcpu(CPUState *env);
 170
 171 int kvm_arch_init_vcpu(CPUState *env)
 172 {
 173     int r;
 174     struct {
 175         struct kvm_cpuid2 cpuid;
 176         struct kvm_cpuid_entry2 entries[100];
 177     } __attribute__((packed)) cpuid_data;
 178     uint32_t limit, i, j, cpuid_i;
 179     uint32_t unused;
 180     struct kvm_cpuid_entry2 *c;
 181 #ifdef KVM_CPUID_SIGNATURE
 182     uint32_t signature[3];
 183 #endif
 184
 185     r = _kvm_arch_init_vcpu(env);
 186     if (r < 0) {
 187         return r;
 188     }
 189
 190 #ifdef KVM_UPSTREAM
 191
 192     env->mp_state = KVM_MP_STATE_RUNNABLE;
 193
 194 #endif
 195
 196     env->cpuid_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_EDX);
 197
 198     i = env->cpuid_ext_features & CPUID_EXT_HYPERVISOR;
 199     env->cpuid_ext_features &= kvm_arch_get_supported_cpuid(env, 1, 0, R_ECX);
 200     env->cpuid_ext_features |= i;
 201
 202     env->cpuid_ext2_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 203                                                              0, R_EDX);
 204     env->cpuid_ext3_features &= kvm_arch_get_supported_cpuid(env, 0x80000001,
 205                                                              0, R_ECX);
 206
 207     cpuid_i = 0;
 208
 209 #ifdef CONFIG_KVM_PARA
 210     /* Paravirtualization CPUIDs */
 211     memcpy(signature, "KVMKVMKVM\0\0\0", 12);
 212     c = &cpuid_data.entries[cpuid_i++];
 213     memset(c, 0, sizeof(*c));
 214     c->function = KVM_CPUID_SIGNATURE;
 215     c->eax = 0;
 216     c->ebx = signature[0];
 217     c->ecx = signature[1];
 218     c->edx = signature[2];
 219
 220     c = &cpuid_data.entries[cpuid_i++];
 221     memset(c, 0, sizeof(*c));
 222     c->function = KVM_CPUID_FEATURES;
 223     c->eax = env->cpuid_kvm_features & get_para_features(env);
 224 #endif
 225
 226     cpu_x86_cpuid(env, 0, 0, &limit, &unused, &unused, &unused);
 227
 228     for (i = 0; i <= limit; i++) {
 229         c = &cpuid_data.entries[cpuid_i++];
 230
 231         switch (i) {
 232         case 2: {
 233             /* Keep reading function 2 till all the input is received */
 234             int times;
 235
 236             c->function = i;
 237             c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC |
 238                        KVM_CPUID_FLAG_STATE_READ_NEXT;
 239             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 240             times = c->eax & 0xff;
 241
 242             for (j = 1; j < times; ++j) {
 243                 c = &cpuid_data.entries[cpuid_i++];
 244                 c->function = i;
 245                 c->flags = KVM_CPUID_FLAG_STATEFUL_FUNC;
 246                 cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 247             }
 248             break;
 249         }
 250         case 4:
 251         case 0xb:
 252         case 0xd:
 253             for (j = 0; ; j++) {
 254                 c->function = i;
 255                 c->flags = KVM_CPUID_FLAG_SIGNIFCANT_INDEX;
 256                 c->index = j;
 257                 cpu_x86_cpuid(env, i, j, &c->eax, &c->ebx, &c->ecx, &c->edx);
 258
 259                 if (i == 4 && c->eax == 0)
 260                     break;
 261                 if (i == 0xb && !(c->ecx & 0xff00))
 262                     break;
 263                 if (i == 0xd && c->eax == 0)
 264                     break;
 265
 266                 c = &cpuid_data.entries[cpuid_i++];
 267             }
 268             break;
 269         default:
 270             c->function = i;
 271             c->flags = 0;
 272             cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 273             break;
 274         }
 275     }
 276     cpu_x86_cpuid(env, 0x80000000, 0, &limit, &unused, &unused, &unused);
 277
 278     for (i = 0x80000000; i <= limit; i++) {
 279         c = &cpuid_data.entries[cpuid_i++];
 280
 281         c->function = i;
 282         c->flags = 0;
 283         cpu_x86_cpuid(env, i, 0, &c->eax, &c->ebx, &c->ecx, &c->edx);
 284     }
 285
 286     cpuid_data.cpuid.nent = cpuid_i;
 287
 288     return kvm_vcpu_ioctl(env, KVM_SET_CPUID2, &cpuid_data);
 289 }
 290
 291 void kvm_arch_reset_vcpu(CPUState *env)
 292 {
 293     env->exception_injected = -1;
 294     env->interrupt_injected = -1;
 295     env->nmi_injected = 0;
 296     env->nmi_pending = 0;
 297     /* Legal xcr0 for loading */
 298     env->xcr0 = 1;
 299 }
 300 #ifdef KVM_UPSTREAM
 301
 302 static int kvm_has_msr_star(CPUState *env)
 303 {
 304     static int has_msr_star;
 305     int ret;
 306
 307     /* first time */
 308     if (has_msr_star == 0) {
 309         struct kvm_msr_list msr_list, *kvm_msr_list;
 310
 311         has_msr_star = -1;
 312
 313         /* Obtain MSR list from KVM.  These are the MSRs that we must
 314          * save/restore */
 315         msr_list.nmsrs = 0;
 316         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, &msr_list);
 317         if (ret < 0 && ret != -E2BIG) {
 318             return 0;
 319         }
 320         /* Old kernel modules had a bug and could write beyond the provided
 321            memory. Allocate at least a safe amount of 1K. */
 322         kvm_msr_list = qemu_mallocz(MAX(1024, sizeof(msr_list) +
 323                                               msr_list.nmsrs *
 324                                               sizeof(msr_list.indices[0])));
 325
 326         kvm_msr_list->nmsrs = msr_list.nmsrs;
 327         ret = kvm_ioctl(env->kvm_state, KVM_GET_MSR_INDEX_LIST, kvm_msr_list);
 328         if (ret >= 0) {
 329             int i;
 330
 331             for (i = 0; i < kvm_msr_list->nmsrs; i++) {
 332                 if (kvm_msr_list->indices[i] == MSR_STAR) {
 333                     has_msr_star = 1;
 334                     break;
 335                 }
 336             }
 337         }
 338
 339         free(kvm_msr_list);
 340     }
 341
 342     if (has_msr_star == 1)
 343         return 1;
 344     return 0;
 345 }
 346
 347 static int kvm_init_identity_map_page(KVMState *s)
 348 {
 349 #ifdef KVM_CAP_SET_IDENTITY_MAP_ADDR
 350     int ret;
 351     uint64_t addr = 0xfffbc000;
 352
 353     if (!kvm_check_extension(s, KVM_CAP_SET_IDENTITY_MAP_ADDR)) {
 354         return 0;
 355     }
 356
 357     ret = kvm_vm_ioctl(s, KVM_SET_IDENTITY_MAP_ADDR, &addr);
 358     if (ret < 0) {
 359         fprintf(stderr, "kvm_set_identity_map_addr: %s\n", strerror(ret));
 360         return ret;
 361     }
 362 #endif
 363     return 0;
 364 }
 365
 366 int kvm_arch_init(KVMState *s, int smp_cpus)
 367 {
 368     int ret;
 369
 370     /* create vm86 tss.  KVM uses vm86 mode to emulate 16-bit code
 371      * directly.  In order to use vm86 mode, a TSS is needed.  Since this
 372      * must be part of guest physical memory, we need to allocate it.  Older
 373      * versions of KVM just assumed that it would be at the end of physical
 374      * memory but that doesn't work with more than 4GB of memory.  We simply
 375      * refuse to work with those older versions of KVM. */
 376     ret = kvm_ioctl(s, KVM_CHECK_EXTENSION, KVM_CAP_SET_TSS_ADDR);
 377     if (ret <= 0) {
 378         fprintf(stderr, "kvm does not support KVM_CAP_SET_TSS_ADDR\n");
 379         return ret;
 380     }
 381
 382     /* this address is 3 pages before the bios, and the bios should present
 383      * as unavaible memory.  FIXME, need to ensure the e820 map deals with
 384      * this?
 385      */
 386     /*
 387      * Tell fw_cfg to notify the BIOS to reserve the range.
 388      */
 389     if (e820_add_entry(0xfffbc000, 0x4000, E820_RESERVED) < 0) {
 390         perror("e820_add_entry() table is full");
 391         exit(1);
 392     }
 393     ret = kvm_vm_ioctl(s, KVM_SET_TSS_ADDR, 0xfffbd000);
 394     if (ret < 0) {
 395         return ret;
 396     }
 397
 398     return kvm_init_identity_map_page(s);
 399 }
 400
 401 static void set_v8086_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 402 {
 403     lhs->selector = rhs->selector;
 404     lhs->base = rhs->base;
 405     lhs->limit = rhs->limit;
 406     lhs->type = 3;
 407     lhs->present = 1;
 408     lhs->dpl = 3;
 409     lhs->db = 0;
 410     lhs->s = 1;
 411     lhs->l = 0;
 412     lhs->g = 0;
 413     lhs->avl = 0;
 414     lhs->unusable = 0;
 415 }
 416
 417 static void set_seg(struct kvm_segment *lhs, const SegmentCache *rhs)
 418 {
 419     unsigned flags = rhs->flags;
 420     lhs->selector = rhs->selector;
 421     lhs->base = rhs->base;
 422     lhs->limit = rhs->limit;
 423     lhs->type = (flags >> DESC_TYPE_SHIFT) & 15;
 424     lhs->present = (flags & DESC_P_MASK) != 0;
 425     lhs->dpl = rhs->selector & 3;
 426     lhs->db = (flags >> DESC_B_SHIFT) & 1;
 427     lhs->s = (flags & DESC_S_MASK) != 0;
 428     lhs->l = (flags >> DESC_L_SHIFT) & 1;
 429     lhs->g = (flags & DESC_G_MASK) != 0;
 430     lhs->avl = (flags & DESC_AVL_MASK) != 0;
 431     lhs->unusable = 0;
 432 }
 433
 434 static void get_seg(SegmentCache *lhs, const struct kvm_segment *rhs)
 435 {
 436     lhs->selector = rhs->selector;
 437     lhs->base = rhs->base;
 438     lhs->limit = rhs->limit;
 439     lhs->flags =
 440         (rhs->type << DESC_TYPE_SHIFT)
 441         | (rhs->present * DESC_P_MASK)
 442         | (rhs->dpl << DESC_DPL_SHIFT)
 443         | (rhs->db << DESC_B_SHIFT)
 444         | (rhs->s * DESC_S_MASK)
 445         | (rhs->l << DESC_L_SHIFT)
 446         | (rhs->g * DESC_G_MASK)
 447         | (rhs->avl * DESC_AVL_MASK);
 448 }
 449
 450 static void kvm_getput_reg(__u64 *kvm_reg, target_ulong *qemu_reg, int set)
 451 {
 452     if (set)
 453         *kvm_reg = *qemu_reg;
 454     else
 455         *qemu_reg = *kvm_reg;
 456 }
 457
 458 static int kvm_getput_regs(CPUState *env, int set)
 459 {
 460     struct kvm_regs regs;
 461     int ret = 0;
 462
 463     if (!set) {
 464         ret = kvm_vcpu_ioctl(env, KVM_GET_REGS, &regs);
 465         if (ret < 0)
 466             return ret;
 467     }
 468
 469     kvm_getput_reg(&regs.rax, &env->regs[R_EAX], set);
 470     kvm_getput_reg(&regs.rbx, &env->regs[R_EBX], set);
 471     kvm_getput_reg(&regs.rcx, &env->regs[R_ECX], set);
 472     kvm_getput_reg(&regs.rdx, &env->regs[R_EDX], set);
 473     kvm_getput_reg(&regs.rsi, &env->regs[R_ESI], set);
 474     kvm_getput_reg(&regs.rdi, &env->regs[R_EDI], set);
 475     kvm_getput_reg(&regs.rsp, &env->regs[R_ESP], set);
 476     kvm_getput_reg(&regs.rbp, &env->regs[R_EBP], set);
 477 #ifdef TARGET_X86_64
 478     kvm_getput_reg(&regs.r8, &env->regs[8], set);
 479     kvm_getput_reg(&regs.r9, &env->regs[9], set);
 480     kvm_getput_reg(&regs.r10, &env->regs[10], set);
 481     kvm_getput_reg(&regs.r11, &env->regs[11], set);
 482     kvm_getput_reg(&regs.r12, &env->regs[12], set);
 483     kvm_getput_reg(&regs.r13, &env->regs[13], set);
 484     kvm_getput_reg(&regs.r14, &env->regs[14], set);
 485     kvm_getput_reg(&regs.r15, &env->regs[15], set);
 486 #endif
 487
 488     kvm_getput_reg(&regs.rflags, &env->eflags, set);
 489     kvm_getput_reg(&regs.rip, &env->eip, set);
 490
 491     if (set)
 492         ret = kvm_vcpu_ioctl(env, KVM_SET_REGS, &regs);
 493
 494     return ret;
 495 }
 496
 497 static int kvm_put_fpu(CPUState *env)
 498 {
 499     struct kvm_fpu fpu;
 500     int i;
 501
 502     memset(&fpu, 0, sizeof fpu);
 503     fpu.fsw = env->fpus & ~(7 << 11);
 504     fpu.fsw |= (env->fpstt & 7) << 11;
 505     fpu.fcw = env->fpuc;
 506     for (i = 0; i < 8; ++i)
 507         fpu.ftwx |= (!env->fptags[i]) << i;
 508     memcpy(fpu.fpr, env->fpregs, sizeof env->fpregs);
 509     memcpy(fpu.xmm, env->xmm_regs, sizeof env->xmm_regs);
 510     fpu.mxcsr = env->mxcsr;
 511
 512     return kvm_vcpu_ioctl(env, KVM_SET_FPU, &fpu);
 513 }
 514
 515 static int kvm_put_sregs(CPUState *env)
 516 {
 517     struct kvm_sregs sregs;
 518
 519     memset(sregs.interrupt_bitmap, 0, sizeof(sregs.interrupt_bitmap));
 520     if (env->interrupt_injected >= 0) {
 521         sregs.interrupt_bitmap[env->interrupt_injected / 64] |=
 522                 (uint64_t)1 << (env->interrupt_injected % 64);
 523     }
 524
 525     if ((env->eflags & VM_MASK)) {
 526             set_v8086_seg(&sregs.cs, &env->segs[R_CS]);
 527             set_v8086_seg(&sregs.ds, &env->segs[R_DS]);
 528             set_v8086_seg(&sregs.es, &env->segs[R_ES]);
 529             set_v8086_seg(&sregs.fs, &env->segs[R_FS]);
 530             set_v8086_seg(&sregs.gs, &env->segs[R_GS]);
 531             set_v8086_seg(&sregs.ss, &env->segs[R_SS]);
 532     } else {
 533             set_seg(&sregs.cs, &env->segs[R_CS]);
 534             set_seg(&sregs.ds, &env->segs[R_DS]);
 535             set_seg(&sregs.es, &env->segs[R_ES]);
 536             set_seg(&sregs.fs, &env->segs[R_FS]);
 537             set_seg(&sregs.gs, &env->segs[R_GS]);
 538             set_seg(&sregs.ss, &env->segs[R_SS]);
 539
 540             if (env->cr[0] & CR0_PE_MASK) {
 541                 /* force ss cpl to cs cpl */
 542                 sregs.ss.selector = (sregs.ss.selector & ~3) |
 543                         (sregs.cs.selector & 3);
 544                 sregs.ss.dpl = sregs.ss.selector & 3;
 545             }
 546     }
 547
 548     set_seg(&sregs.tr, &env->tr);
 549     set_seg(&sregs.ldt, &env->ldt);
 550
 551     sregs.idt.limit = env->idt.limit;
 552     sregs.idt.base = env->idt.base;
 553     sregs.gdt.limit = env->gdt.limit;
 554     sregs.gdt.base = env->gdt.base;
 555
 556     sregs.cr0 = env->cr[0];
 557     sregs.cr2 = env->cr[2];
 558     sregs.cr3 = env->cr[3];
 559     sregs.cr4 = env->cr[4];
 560
 561     sregs.cr8 = cpu_get_apic_tpr(env->apic_state);
 562     sregs.apic_base = cpu_get_apic_base(env->apic_state);
 563
 564     sregs.efer = env->efer;
 565
 566     return kvm_vcpu_ioctl(env, KVM_SET_SREGS, &sregs);
 567 }
 568
 569 #endif
 570
 571 static void kvm_msr_entry_set(struct kvm_msr_entry *entry,
 572                               uint32_t index, uint64_t value)
 573 {
 574     entry->index = index;
 575     entry->data = value;
 576 }
 577
 578 #ifdef KVM_UPSTREAM
 579 static int kvm_put_msrs(CPUState *env, int level)
 580 {
 581     struct {
 582         struct kvm_msrs info;
 583         struct kvm_msr_entry entries[100];
 584     } msr_data;
 585     struct kvm_msr_entry *msrs = msr_data.entries;
 586     int n = 0;
 587
 588     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs);
 589     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp);
 590     kvm_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip);
 591     if (kvm_has_msr_star(env))
 592         kvm_msr_entry_set(&msrs[n++], MSR_STAR, env->star);
 593     kvm_msr_entry_set(&msrs[n++], MSR_VM_HSAVE_PA, env->vm_hsave);
 594 #ifdef TARGET_X86_64
 595     /* FIXME if lm capable */
 596     kvm_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar);
 597     kvm_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase);
 598     kvm_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask);
 599     kvm_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar);
 600 #endif
 601     if (level == KVM_PUT_FULL_STATE) {
 602         kvm_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc);
 603         kvm_msr_entry_set(&msrs[n++], MSR_KVM_SYSTEM_TIME,
 604                           env->system_time_msr);
 605         kvm_msr_entry_set(&msrs[n++], MSR_KVM_WALL_CLOCK, env->wall_clock_msr);
 606     }
 607
 608     msr_data.info.nmsrs = n;
 609
 610     return kvm_vcpu_ioctl(env, KVM_SET_MSRS, &msr_data);
 611
 612 }
 613
 614
 615 static int kvm_get_fpu(CPUState *env)
 616 {
 617     struct kvm_fpu fpu;
 618     int i, ret;
 619
 620     ret = kvm_vcpu_ioctl(env, KVM_GET_FPU, &fpu);
 621     if (ret < 0)
 622         return ret;
 623
 624     env->fpstt = (fpu.fsw >> 11) & 7;
 625     env->fpus = fpu.fsw;
 626     env->fpuc = fpu.fcw;
 627     for (i = 0; i < 8; ++i)
 628         env->fptags[i] = !((fpu.ftwx >> i) & 1);
 629     memcpy(env->fpregs, fpu.fpr, sizeof env->fpregs);
 630     memcpy(env->xmm_regs, fpu.xmm, sizeof env->xmm_regs);
 631     env->mxcsr = fpu.mxcsr;
 632
 633     return 0;
 634 }
 635
 636 static int kvm_get_sregs(CPUState *env)
 637 {
 638     struct kvm_sregs sregs;
 639     uint32_t hflags;
 640     int bit, i, ret;
 641
 642     ret = kvm_vcpu_ioctl(env, KVM_GET_SREGS, &sregs);
 643     if (ret < 0)
 644         return ret;
 645
 646     /* There can only be one pending IRQ set in the bitmap at a time, so try
 647        to find it and save its number instead (-1 for none). */
 648     env->interrupt_injected = -1;
 649     for (i = 0; i < ARRAY_SIZE(sregs.interrupt_bitmap); i++) {
 650         if (sregs.interrupt_bitmap[i]) {
 651             bit = ctz64(sregs.interrupt_bitmap[i]);
 652             env->interrupt_injected = i * 64 + bit;
 653             break;
 654         }
 655     }
 656
 657     get_seg(&env->segs[R_CS], &sregs.cs);
 658     get_seg(&env->segs[R_DS], &sregs.ds);
 659     get_seg(&env->segs[R_ES], &sregs.es);
 660     get_seg(&env->segs[R_FS], &sregs.fs);
 661     get_seg(&env->segs[R_GS], &sregs.gs);
 662     get_seg(&env->segs[R_SS], &sregs.ss);
 663
 664     get_seg(&env->tr, &sregs.tr);
 665     get_seg(&env->ldt, &sregs.ldt);
 666
 667     env->idt.limit = sregs.idt.limit;
 668     env->idt.base = sregs.idt.base;
 669     env->gdt.limit = sregs.gdt.limit;
 670     env->gdt.base = sregs.gdt.base;
 671
 672     env->cr[0] = sregs.cr0;
 673     env->cr[2] = sregs.cr2;
 674     env->cr[3] = sregs.cr3;
 675     env->cr[4] = sregs.cr4;
 676
 677     cpu_set_apic_base(env->apic_state, sregs.apic_base);
 678
 679     env->efer = sregs.efer;
 680     //cpu_set_apic_tpr(env->apic_state, sregs.cr8);
 681
 682 #define HFLAG_COPY_MASK ~( \
 683                         HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
 684                         HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
 685                         HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
 686                         HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
 687
 688
 689
 690     hflags = (env->segs[R_CS].flags >> DESC_DPL_SHIFT) & HF_CPL_MASK;
 691     hflags |= (env->cr[0] & CR0_PE_MASK) << (HF_PE_SHIFT - CR0_PE_SHIFT);
 692     hflags |= (env->cr[0] << (HF_MP_SHIFT - CR0_MP_SHIFT)) &
 693             (HF_MP_MASK | HF_EM_MASK | HF_TS_MASK);
 694     hflags |= (env->eflags & (HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK));
 695     hflags |= (env->cr[4] & CR4_OSFXSR_MASK) <<
 696             (HF_OSFXSR_SHIFT - CR4_OSFXSR_SHIFT);
 697
 698     if (env->efer & MSR_EFER_LMA) {
 699         hflags |= HF_LMA_MASK;
 700     }
 701
 702     if ((hflags & HF_LMA_MASK) && (env->segs[R_CS].flags & DESC_L_MASK)) {
 703         hflags |= HF_CS32_MASK | HF_SS32_MASK | HF_CS64_MASK;
 704     } else {
 705         hflags |= (env->segs[R_CS].flags & DESC_B_MASK) >>
 706                 (DESC_B_SHIFT - HF_CS32_SHIFT);
 707         hflags |= (env->segs[R_SS].flags & DESC_B_MASK) >>
 708                 (DESC_B_SHIFT - HF_SS32_SHIFT);
 709         if (!(env->cr[0] & CR0_PE_MASK) ||
 710                    (env->eflags & VM_MASK) ||
 711                    !(hflags & HF_CS32_MASK)) {
 712                 hflags |= HF_ADDSEG_MASK;
 713             } else {
 714                 hflags |= ((env->segs[R_DS].base |
 715                                 env->segs[R_ES].base |
 716                                 env->segs[R_SS].base) != 0) <<
 717                     HF_ADDSEG_SHIFT;
 718             }
 719     }
 720     env->hflags = (env->hflags & HFLAG_COPY_MASK) | hflags;
 721
 722     return 0;
 723 }
 724
 725 static int kvm_get_msrs(CPUState *env)
 726 {
 727     struct {
 728         struct kvm_msrs info;
 729         struct kvm_msr_entry entries[100];
 730     } msr_data;
 731     struct kvm_msr_entry *msrs = msr_data.entries;
 732     int ret, i, n;
 733
 734     n = 0;
 735     msrs[n++].index = MSR_IA32_SYSENTER_CS;
 736     msrs[n++].index = MSR_IA32_SYSENTER_ESP;
 737     msrs[n++].index = MSR_IA32_SYSENTER_EIP;
 738     if (kvm_has_msr_star(env))
 739         msrs[n++].index = MSR_STAR;
 740     msrs[n++].index = MSR_IA32_TSC;
 741     msrs[n++].index = MSR_VM_HSAVE_PA;
 742 #ifdef TARGET_X86_64
 743     /* FIXME lm_capable_kernel */
 744     msrs[n++].index = MSR_CSTAR;
 745     msrs[n++].index = MSR_KERNELGSBASE;
 746     msrs[n++].index = MSR_FMASK;
 747     msrs[n++].index = MSR_LSTAR;
 748 #endif
 749     msrs[n++].index = MSR_KVM_SYSTEM_TIME;
 750     msrs[n++].index = MSR_KVM_WALL_CLOCK;
 751
 752     msr_data.info.nmsrs = n;
 753     ret = kvm_vcpu_ioctl(env, KVM_GET_MSRS, &msr_data);
 754     if (ret < 0)
 755         return ret;
 756
 757     for (i = 0; i < ret; i++) {
 758         switch (msrs[i].index) {
 759         case MSR_IA32_SYSENTER_CS:
 760             env->sysenter_cs = msrs[i].data;
 761             break;
 762         case MSR_IA32_SYSENTER_ESP:
 763             env->sysenter_esp = msrs[i].data;
 764             break;
 765         case MSR_IA32_SYSENTER_EIP:
 766             env->sysenter_eip = msrs[i].data;
 767             break;
 768         case MSR_STAR:
 769             env->star = msrs[i].data;
 770             break;
 771 #ifdef TARGET_X86_64
 772         case MSR_CSTAR:
 773             env->cstar = msrs[i].data;
 774             break;
 775         case MSR_KERNELGSBASE:
 776             env->kernelgsbase = msrs[i].data;
 777             break;
 778         case MSR_FMASK:
 779             env->fmask = msrs[i].data;
 780             break;
 781         case MSR_LSTAR:
 782             env->lstar = msrs[i].data;
 783             break;
 784 #endif
 785         case MSR_IA32_TSC:
 786             env->tsc = msrs[i].data;
 787             break;
 788         case MSR_KVM_SYSTEM_TIME:
 789             env->system_time_msr = msrs[i].data;
 790             break;
 791         case MSR_KVM_WALL_CLOCK:
 792             env->wall_clock_msr = msrs[i].data;
 793             break;
 794         case MSR_VM_HSAVE_PA:
 795             env->vm_hsave = msrs[i].data;
 796             break;
 797         }
 798     }
 799
 800     return 0;
 801 }
 802
 803 static int kvm_put_mp_state(CPUState *env)
 804 {
 805     struct kvm_mp_state mp_state = { .mp_state = env->mp_state };
 806
 807     return kvm_vcpu_ioctl(env, KVM_SET_MP_STATE, &mp_state);
 808 }
 809
 810 static int kvm_get_mp_state(CPUState *env)
 811 {
 812     struct kvm_mp_state mp_state;
 813     int ret;
 814
 815     ret = kvm_vcpu_ioctl(env, KVM_GET_MP_STATE, &mp_state);
 816     if (ret < 0) {
 817         return ret;
 818     }
 819     env->mp_state = mp_state.mp_state;
 820     return 0;
 821 }
 822 #endif
 823
 824 static int kvm_put_vcpu_events(CPUState *env, int level)
 825 {
 826 #ifdef KVM_CAP_VCPU_EVENTS
 827     struct kvm_vcpu_events events;
 828
 829     if (!kvm_has_vcpu_events()) {
 830         return 0;
 831     }
 832
 833     events.exception.injected = (env->exception_injected >= 0);
 834     events.exception.nr = env->exception_injected;
 835     events.exception.has_error_code = env->has_error_code;
 836     events.exception.error_code = env->error_code;
 837
 838     events.interrupt.injected = (env->interrupt_injected >= 0);
 839     events.interrupt.nr = env->interrupt_injected;
 840     events.interrupt.soft = env->soft_interrupt;
 841
 842     events.nmi.injected = env->nmi_injected;
 843     events.nmi.pending = env->nmi_pending;
 844     events.nmi.masked = !!(env->hflags2 & HF2_NMI_MASK);
 845
 846     events.sipi_vector = env->sipi_vector;
 847
 848     events.flags = 0;
 849     if (level >= KVM_PUT_RESET_STATE) {
 850         events.flags |=
 851             KVM_VCPUEVENT_VALID_NMI_PENDING | KVM_VCPUEVENT_VALID_SIPI_VECTOR;
 852     }
 853
 854     return kvm_vcpu_ioctl(env, KVM_SET_VCPU_EVENTS, &events);
 855 #else
 856     return 0;
 857 #endif
 858 }
 859
 860 static int kvm_get_vcpu_events(CPUState *env)
 861 {
 862 #ifdef KVM_CAP_VCPU_EVENTS
 863     struct kvm_vcpu_events events;
 864     int ret;
 865
 866     if (!kvm_has_vcpu_events()) {
 867         return 0;
 868     }
 869
 870     ret = kvm_vcpu_ioctl(env, KVM_GET_VCPU_EVENTS, &events);
 871     if (ret < 0) {
 872        return ret;
 873     }
 874     env->exception_injected =
 875        events.exception.injected ? events.exception.nr : -1;
 876     env->has_error_code = events.exception.has_error_code;
 877     env->error_code = events.exception.error_code;
 878
 879     env->interrupt_injected =
 880         events.interrupt.injected ? events.interrupt.nr : -1;
 881     env->soft_interrupt = events.interrupt.soft;
 882
 883     env->nmi_injected = events.nmi.injected;
 884     env->nmi_pending = events.nmi.pending;
 885     if (events.nmi.masked) {
 886         env->hflags2 |= HF2_NMI_MASK;
 887     } else {
 888         env->hflags2 &= ~HF2_NMI_MASK;
 889     }
 890
 891     env->sipi_vector = events.sipi_vector;
 892 #endif
 893
 894     return 0;
 895 }
 896
 897 static int kvm_guest_debug_workarounds(CPUState *env)
 898 {
 899     int ret = 0;
 900 #ifdef KVM_CAP_SET_GUEST_DEBUG
 901     unsigned long reinject_trap = 0;
 902
 903     if (!kvm_has_vcpu_events()) {
 904         if (env->exception_injected == 1) {
 905             reinject_trap = KVM_GUESTDBG_INJECT_DB;
 906         } else if (env->exception_injected == 3) {
 907             reinject_trap = KVM_GUESTDBG_INJECT_BP;
 908         }
 909         env->exception_injected = -1;
 910     }
 911
 912     /*
 913      * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
 914      * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
 915      * by updating the debug state once again if single-stepping is on.
 916      * Another reason to call kvm_update_guest_debug here is a pending debug
 917      * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
 918      * reinject them via SET_GUEST_DEBUG.
 919      */
 920     if (reinject_trap ||
 921         (!kvm_has_robust_singlestep() && env->singlestep_enabled)) {
 922         ret = kvm_update_guest_debug(env, reinject_trap);
 923     }
 924 #endif /* KVM_CAP_SET_GUEST_DEBUG */
 925     return ret;
 926 }
 927
 928 static int kvm_put_debugregs(CPUState *env)
 929 {
 930 #ifdef KVM_CAP_DEBUGREGS
 931     struct kvm_debugregs dbgregs;
 932     int i;
 933
 934     if (!kvm_has_debugregs()) {
 935         return 0;
 936     }
 937
 938     for (i = 0; i < 4; i++) {
 939         dbgregs.db[i] = env->dr[i];
 940     }
 941     dbgregs.dr6 = env->dr[6];
 942     dbgregs.dr7 = env->dr[7];
 943     dbgregs.flags = 0;
 944
 945     return kvm_vcpu_ioctl(env, KVM_SET_DEBUGREGS, &dbgregs);
 946 #else
 947     return 0;
 948 #endif
 949 }
 950
 951 static int kvm_get_debugregs(CPUState *env)
 952 {
 953 #ifdef KVM_CAP_DEBUGREGS
 954     struct kvm_debugregs dbgregs;
 955     int i, ret;
 956
 957     if (!kvm_has_debugregs()) {
 958         return 0;
 959     }
 960
 961     ret = kvm_vcpu_ioctl(env, KVM_GET_DEBUGREGS, &dbgregs);
 962     if (ret < 0) {
 963        return ret;
 964     }
 965     for (i = 0; i < 4; i++) {
 966         env->dr[i] = dbgregs.db[i];
 967     }
 968     env->dr[4] = env->dr[6] = dbgregs.dr6;
 969     env->dr[5] = env->dr[7] = dbgregs.dr7;
 970 #endif
 971
 972     return 0;
 973 }
 974
 975 #ifdef KVM_UPSTREAM
 976 int kvm_arch_put_registers(CPUState *env, int level)
 977 {
 978     int ret;
 979
 980     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
 981
 982     ret = kvm_getput_regs(env, 1);
 983     if (ret < 0)
 984         return ret;
 985
 986     ret = kvm_put_fpu(env);
 987     if (ret < 0)
 988         return ret;
 989
 990     ret = kvm_put_sregs(env);
 991     if (ret < 0)
 992         return ret;
 993
 994     ret = kvm_put_msrs(env, level);
 995     if (ret < 0)
 996         return ret;
 997
 998     if (level >= KVM_PUT_RESET_STATE) {
 999         ret = kvm_put_mp_state(env);
1000         if (ret < 0)
1001             return ret;
1002     }
1003
1004     ret = kvm_put_vcpu_events(env, level);
1005     if (ret < 0)
1006         return ret;
1007
1008     /* must be last */
1009     ret = kvm_guest_debug_workarounds(env);
1010     if (ret < 0)
1011         return ret;
1012
1013     ret = kvm_put_debugregs(env);
1014     if (ret < 0)
1015         return ret;
1016
1017     return 0;
1018 }
1019
1020 int kvm_arch_get_registers(CPUState *env)
1021 {
1022     int ret;
1023
1024     assert(cpu_is_stopped(env) || qemu_cpu_self(env));
1025
1026     ret = kvm_getput_regs(env, 0);
1027     if (ret < 0)
1028         return ret;
1029
1030     ret = kvm_get_fpu(env);
1031     if (ret < 0)
1032         return ret;
1033
1034     ret = kvm_get_sregs(env);
1035     if (ret < 0)
1036         return ret;
1037
1038     ret = kvm_get_msrs(env);
1039     if (ret < 0)
1040         return ret;
1041
1042     ret = kvm_get_mp_state(env);
1043     if (ret < 0)
1044         return ret;
1045
1046     ret = kvm_get_vcpu_events(env);
1047     if (ret < 0)
1048         return ret;
1049
1050     ret = kvm_get_debugregs(env);
1051     if (ret < 0)
1052         return ret;
1053
1054     return 0;
1055 }
1056
1057 int kvm_arch_pre_run(CPUState *env, struct kvm_run *run)
1058 {
1059     /* Try to inject an interrupt if the guest can accept it */
1060     if (run->ready_for_interrupt_injection &&
1061         (env->interrupt_request & CPU_INTERRUPT_HARD) &&
1062         (env->eflags & IF_MASK)) {
1063         int irq;
1064
1065         env->interrupt_request &= ~CPU_INTERRUPT_HARD;
1066         irq = cpu_get_pic_interrupt(env);
1067         if (irq >= 0) {
1068             struct kvm_interrupt intr;
1069             intr.irq = irq;
1070             /* FIXME: errors */
1071             DPRINTF("injected interrupt %d\n", irq);
1072             kvm_vcpu_ioctl(env, KVM_INTERRUPT, &intr);
1073         }
1074     }
1075
1076     /* If we have an interrupt but the guest is not ready to receive an
1077      * interrupt, request an interrupt window exit.  This will
1078      * cause a return to userspace as soon as the guest is ready to
1079      * receive interrupts. */
1080     if ((env->interrupt_request & CPU_INTERRUPT_HARD))
1081         run->request_interrupt_window = 1;
1082     else
1083         run->request_interrupt_window = 0;
1084
1085     DPRINTF("setting tpr\n");
1086     run->cr8 = cpu_get_apic_tpr(env->apic_state);
1087
1088     return 0;
1089 }
1090 #endif
1091
1092 int kvm_arch_post_run(CPUState *env, struct kvm_run *run)
1093 {
1094     if (run->if_flag)
1095         env->eflags |= IF_MASK;
1096     else
1097         env->eflags &= ~IF_MASK;
1098
1099     cpu_set_apic_tpr(env->apic_state, run->cr8);
1100     cpu_set_apic_base(env->apic_state, run->apic_base);
1101
1102     return 0;
1103 }
1104
1105 #ifdef KVM_UPSTREAM
1106
1107 int kvm_arch_process_irqchip_events(CPUState *env)
1108 {
1109     if (env->interrupt_request & CPU_INTERRUPT_INIT) {
1110         kvm_cpu_synchronize_state(env);
1111         do_cpu_init(env);
1112         env->exception_index = EXCP_HALTED;
1113     }
1114
1115     if (env->interrupt_request & CPU_INTERRUPT_SIPI) {
1116         kvm_cpu_synchronize_state(env);
1117         do_cpu_sipi(env);
1118     }
1119
1120     return env->halted;
1121 }
1122
1123 static int kvm_handle_halt(CPUState *env)
1124 {
1125     if (!((env->interrupt_request & CPU_INTERRUPT_HARD) &&
1126           (env->eflags & IF_MASK)) &&
1127         !(env->interrupt_request & CPU_INTERRUPT_NMI)) {
1128         env->halted = 1;
1129         env->exception_index = EXCP_HLT;
1130         return 0;
1131     }
1132
1133     return 1;
1134 }
1135
1136 int kvm_arch_handle_exit(CPUState *env, struct kvm_run *run)
1137 {
1138     int ret = 0;
1139
1140     switch (run->exit_reason) {
1141     case KVM_EXIT_HLT:
1142         DPRINTF("handle_hlt\n");
1143         ret = kvm_handle_halt(env);
1144         break;
1145     }
1146
1147     return ret;
1148 }
1149 #endif
1150
1151 #ifdef KVM_CAP_SET_GUEST_DEBUG
1152 int kvm_arch_insert_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1153 {
1154     static const uint8_t int3 = 0xcc;
1155
1156     if (cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 0) ||
1157         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&int3, 1, 1))
1158         return -EINVAL;
1159     return 0;
1160 }
1161
1162 int kvm_arch_remove_sw_breakpoint(CPUState *env, struct kvm_sw_breakpoint *bp)
1163 {
1164     uint8_t int3;
1165
1166     if (cpu_memory_rw_debug(env, bp->pc, &int3, 1, 0) || int3 != 0xcc ||
1167         cpu_memory_rw_debug(env, bp->pc, (uint8_t *)&bp->saved_insn, 1, 1))
1168         return -EINVAL;
1169     return 0;
1170 }
1171
1172 static struct {
1173     target_ulong addr;
1174     int len;
1175     int type;
1176 } hw_breakpoint[4];
1177
1178 static int nb_hw_breakpoint;
1179
1180 static int find_hw_breakpoint(target_ulong addr, int len, int type)
1181 {
1182     int n;
1183
1184     for (n = 0; n < nb_hw_breakpoint; n++)
1185         if (hw_breakpoint[n].addr == addr && hw_breakpoint[n].type == type &&
1186             (hw_breakpoint[n].len == len || len == -1))
1187             return n;
1188     return -1;
1189 }
1190
1191 int kvm_arch_insert_hw_breakpoint(target_ulong addr,
1192                                   target_ulong len, int type)
1193 {
1194     switch (type) {
1195     case GDB_BREAKPOINT_HW:
1196         len = 1;
1197         break;
1198     case GDB_WATCHPOINT_WRITE:
1199     case GDB_WATCHPOINT_ACCESS:
1200         switch (len) {
1201         case 1:
1202             break;
1203         case 2:
1204         case 4:
1205         case 8:
1206             if (addr & (len - 1))
1207                 return -EINVAL;
1208             break;
1209         default:
1210             return -EINVAL;
1211         }
1212         break;
1213     default:
1214         return -ENOSYS;
1215     }
1216
1217     if (nb_hw_breakpoint == 4)
1218         return -ENOBUFS;
1219
1220     if (find_hw_breakpoint(addr, len, type) >= 0)
1221         return -EEXIST;
1222
1223     hw_breakpoint[nb_hw_breakpoint].addr = addr;
1224     hw_breakpoint[nb_hw_breakpoint].len = len;
1225     hw_breakpoint[nb_hw_breakpoint].type = type;
1226     nb_hw_breakpoint++;
1227
1228     return 0;
1229 }
1230
1231 int kvm_arch_remove_hw_breakpoint(target_ulong addr,
1232                                   target_ulong len, int type)
1233 {
1234     int n;
1235
1236     n = find_hw_breakpoint(addr, (type == GDB_BREAKPOINT_HW) ? 1 : len, type);
1237     if (n < 0)
1238         return -ENOENT;
1239
1240     nb_hw_breakpoint--;
1241     hw_breakpoint[n] = hw_breakpoint[nb_hw_breakpoint];
1242
1243     return 0;
1244 }
1245
1246 void kvm_arch_remove_all_hw_breakpoints(void)
1247 {
1248     nb_hw_breakpoint = 0;
1249 }
1250
1251 static CPUWatchpoint hw_watchpoint;
1252
1253 int kvm_arch_debug(struct kvm_debug_exit_arch *arch_info)
1254 {
1255     int handle = 0;
1256     int n;
1257
1258     if (arch_info->exception == 1) {
1259         if (arch_info->dr6 & (1 << 14)) {
1260             if (cpu_single_env->singlestep_enabled)
1261                 handle = 1;
1262         } else {
1263             for (n = 0; n < 4; n++)
1264                 if (arch_info->dr6 & (1 << n))
1265                     switch ((arch_info->dr7 >> (16 + n*4)) & 0x3) {
1266                     case 0x0:
1267                         handle = 1;
1268                         break;
1269                     case 0x1:
1270                         handle = 1;
1271                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1272                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1273                         hw_watchpoint.flags = BP_MEM_WRITE;
1274                         break;
1275                     case 0x3:
1276                         handle = 1;
1277                         cpu_single_env->watchpoint_hit = &hw_watchpoint;
1278                         hw_watchpoint.vaddr = hw_breakpoint[n].addr;
1279                         hw_watchpoint.flags = BP_MEM_ACCESS;
1280                         break;
1281                     }
1282         }
1283     } else if (kvm_find_sw_breakpoint(cpu_single_env, arch_info->pc))
1284         handle = 1;
1285
1286     if (!handle) {
1287         cpu_synchronize_state(cpu_single_env);
1288         assert(cpu_single_env->exception_injected == -1);
1289
1290         cpu_single_env->exception_injected = arch_info->exception;
1291         cpu_single_env->has_error_code = 0;
1292     }
1293
1294     return handle;
1295 }
1296
1297 void kvm_arch_update_guest_debug(CPUState *env, struct kvm_guest_debug *dbg)
1298 {
1299     const uint8_t type_code[] = {
1300         [GDB_BREAKPOINT_HW] = 0x0,
1301         [GDB_WATCHPOINT_WRITE] = 0x1,
1302         [GDB_WATCHPOINT_ACCESS] = 0x3
1303     };
1304     const uint8_t len_code[] = {
1305         [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
1306     };
1307     int n;
1308
1309     if (kvm_sw_breakpoints_active(env))
1310         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_SW_BP;
1311
1312     if (nb_hw_breakpoint > 0) {
1313         dbg->control |= KVM_GUESTDBG_ENABLE | KVM_GUESTDBG_USE_HW_BP;
1314         dbg->arch.debugreg[7] = 0x0600;
1315         for (n = 0; n < nb_hw_breakpoint; n++) {
1316             dbg->arch.debugreg[n] = hw_breakpoint[n].addr;
1317             dbg->arch.debugreg[7] |= (2 << (n * 2)) |
1318                 (type_code[hw_breakpoint[n].type] << (16 + n*4)) |
1319                 (len_code[hw_breakpoint[n].len] << (18 + n*4));
1320         }
1321     }
1322 }
1323 #endif /* KVM_CAP_SET_GUEST_DEBUG */
1324
1325 bool kvm_arch_stop_on_emulation_error(CPUState *env)
1326 {
1327       return !(env->cr[0] & CR0_PE_MASK) ||
1328               ((env->segs[R_CS].selector  & 3) != 3);
1329 }
1330
1331 #include "qemu-kvm-x86.c"