hw/vmware_vga.c

   1 /*
   2  * QEMU VMware-SVGA "chipset".
   3  *
   4  * Copyright (c) 2007 Andrzej Zaborowski  <balrog@zabor.org>
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "console.h"
  26 #include "pci.h"
  27
  28 #define VERBOSE
  29 #define EMBED_STDVGA
  30 #undef DIRECT_VRAM
  31 #define HW_RECT_ACCEL
  32 #define HW_FILL_ACCEL
  33 #define HW_MOUSE_ACCEL
  34
  35 #ifdef EMBED_STDVGA
  36 # include "vga_int.h"
  37 #endif
  38
  39 #include "qemu-kvm.h"
  40 #include "pc.h"
  41
  42 struct vmsvga_state_s {
  43 #ifdef EMBED_STDVGA
  44     VGA_STATE_COMMON
  45 #endif
  46
  47     int width;
  48     int height;
  49     int invalidated;
  50     int depth;
  51     int bypp;
  52     int enable;
  53     int config;
  54     struct {
  55         int id;
  56         int x;
  57         int y;
  58         int on;
  59     } cursor;
  60
  61 #ifndef EMBED_STDVGA
  62     DisplayState *ds;
  63     int vram_size;
  64 #endif
  65     uint8_t *vram;
  66     uint32_t vram_addr;
  67     int iomemtype;
  68
  69     int index;
  70     int scratch_size;
  71     uint32_t *scratch;
  72     int new_width;
  73     int new_height;
  74     uint32_t guest;
  75     uint32_t svgaid;
  76     uint32_t wred;
  77     uint32_t wgreen;
  78     uint32_t wblue;
  79     int syncing;
  80     int fb_size;
  81
  82     union {
  83         uint32_t *fifo;
  84         struct __attribute__((__packed__)) {
  85             uint32_t min;
  86             uint32_t max;
  87             uint32_t next_cmd;
  88             uint32_t stop;
  89             /* Add registers here when adding capabilities.  */
  90             uint32_t fifo[0];
  91         } *cmd;
  92     };
  93
  94 #define REDRAW_FIFO_LEN 512
  95     struct vmsvga_rect_s {
  96         int x, y, w, h;
  97     } redraw_fifo[REDRAW_FIFO_LEN];
  98     int redraw_fifo_first, redraw_fifo_last;
  99 };
 100
 101 struct pci_vmsvga_state_s {
 102     PCIDevice card;
 103     struct vmsvga_state_s chip;
 104 };
 105
 106 #define SVGA_MAGIC              0x900000UL
 107 #define SVGA_MAKE_ID(ver)       (SVGA_MAGIC << 8 | (ver))
 108 #define SVGA_ID_0               SVGA_MAKE_ID(0)
 109 #define SVGA_ID_1               SVGA_MAKE_ID(1)
 110 #define SVGA_ID_2               SVGA_MAKE_ID(2)
 111
 112 #define SVGA_LEGACY_BASE_PORT   0x4560
 113 #define SVGA_INDEX_PORT         0x0
 114 #define SVGA_VALUE_PORT         0x1
 115 #define SVGA_BIOS_PORT          0x2
 116
 117 #define SVGA_VERSION_2
 118
 119 #ifdef SVGA_VERSION_2
 120 # define SVGA_ID                SVGA_ID_2
 121 # define SVGA_IO_BASE           SVGA_LEGACY_BASE_PORT
 122 # define SVGA_IO_MUL            1
 123 # define SVGA_FIFO_SIZE         0x10000
 124 # define SVGA_MEM_BASE          0xe0000000
 125 # define SVGA_PCI_DEVICE_ID     PCI_DEVICE_ID_VMWARE_SVGA2
 126 #else
 127 # define SVGA_ID                SVGA_ID_1
 128 # define SVGA_IO_BASE           SVGA_LEGACY_BASE_PORT
 129 # define SVGA_IO_MUL            4
 130 # define SVGA_FIFO_SIZE         0x10000
 131 # define SVGA_MEM_BASE          0xe0000000
 132 # define SVGA_PCI_DEVICE_ID     PCI_DEVICE_ID_VMWARE_SVGA
 133 #endif
 134
 135 enum {
 136     /* ID 0, 1 and 2 registers */
 137     SVGA_REG_ID = 0,
 138     SVGA_REG_ENABLE = 1,
 139     SVGA_REG_WIDTH = 2,
 140     SVGA_REG_HEIGHT = 3,
 141     SVGA_REG_MAX_WIDTH = 4,
 142     SVGA_REG_MAX_HEIGHT = 5,
 143     SVGA_REG_DEPTH = 6,
 144     SVGA_REG_BITS_PER_PIXEL = 7,        /* Current bpp in the guest */
 145     SVGA_REG_PSEUDOCOLOR = 8,
 146     SVGA_REG_RED_MASK = 9,
 147     SVGA_REG_GREEN_MASK = 10,
 148     SVGA_REG_BLUE_MASK = 11,
 149     SVGA_REG_BYTES_PER_LINE = 12,
 150     SVGA_REG_FB_START = 13,
 151     SVGA_REG_FB_OFFSET = 14,
 152     SVGA_REG_VRAM_SIZE = 15,
 153     SVGA_REG_FB_SIZE = 16,
 154
 155     /* ID 1 and 2 registers */
 156     SVGA_REG_CAPABILITIES = 17,
 157     SVGA_REG_MEM_START = 18,            /* Memory for command FIFO */
 158     SVGA_REG_MEM_SIZE = 19,
 159     SVGA_REG_CONFIG_DONE = 20,          /* Set when memory area configured */
 160     SVGA_REG_SYNC = 21,                 /* Write to force synchronization */
 161     SVGA_REG_BUSY = 22,                 /* Read to check if sync is done */
 162     SVGA_REG_GUEST_ID = 23,             /* Set guest OS identifier */
 163     SVGA_REG_CURSOR_ID = 24,            /* ID of cursor */
 164     SVGA_REG_CURSOR_X = 25,             /* Set cursor X position */
 165     SVGA_REG_CURSOR_Y = 26,             /* Set cursor Y position */
 166     SVGA_REG_CURSOR_ON = 27,            /* Turn cursor on/off */
 167     SVGA_REG_HOST_BITS_PER_PIXEL = 28,  /* Current bpp in the host */
 168     SVGA_REG_SCRATCH_SIZE = 29,         /* Number of scratch registers */
 169     SVGA_REG_MEM_REGS = 30,             /* Number of FIFO registers */
 170     SVGA_REG_NUM_DISPLAYS = 31,         /* Number of guest displays */
 171     SVGA_REG_PITCHLOCK = 32,            /* Fixed pitch for all modes */
 172
 173     SVGA_PALETTE_BASE = 1024,           /* Base of SVGA color map */
 174     SVGA_PALETTE_END  = SVGA_PALETTE_BASE + 767,
 175     SVGA_SCRATCH_BASE = SVGA_PALETTE_BASE + 768,
 176 };
 177
 178 #define SVGA_CAP_NONE                   0
 179 #define SVGA_CAP_RECT_FILL              (1 << 0)
 180 #define SVGA_CAP_RECT_COPY              (1 << 1)
 181 #define SVGA_CAP_RECT_PAT_FILL          (1 << 2)
 182 #define SVGA_CAP_LEGACY_OFFSCREEN       (1 << 3)
 183 #define SVGA_CAP_RASTER_OP              (1 << 4)
 184 #define SVGA_CAP_CURSOR                 (1 << 5)
 185 #define SVGA_CAP_CURSOR_BYPASS          (1 << 6)
 186 #define SVGA_CAP_CURSOR_BYPASS_2        (1 << 7)
 187 #define SVGA_CAP_8BIT_EMULATION         (1 << 8)
 188 #define SVGA_CAP_ALPHA_CURSOR           (1 << 9)
 189 #define SVGA_CAP_GLYPH                  (1 << 10)
 190 #define SVGA_CAP_GLYPH_CLIPPING         (1 << 11)
 191 #define SVGA_CAP_OFFSCREEN_1            (1 << 12)
 192 #define SVGA_CAP_ALPHA_BLEND            (1 << 13)
 193 #define SVGA_CAP_3D                     (1 << 14)
 194 #define SVGA_CAP_EXTENDED_FIFO          (1 << 15)
 195 #define SVGA_CAP_MULTIMON               (1 << 16)
 196 #define SVGA_CAP_PITCHLOCK              (1 << 17)
 197
 198 /*
 199  * FIFO offsets (seen as an array of 32-bit words)
 200  */
 201 enum {
 202     /*
 203      * The original defined FIFO offsets
 204      */
 205     SVGA_FIFO_MIN = 0,
 206     SVGA_FIFO_MAX,      /* The distance from MIN to MAX must be at least 10K */
 207     SVGA_FIFO_NEXT_CMD,
 208     SVGA_FIFO_STOP,
 209
 210     /*
 211      * Additional offsets added as of SVGA_CAP_EXTENDED_FIFO
 212      */
 213     SVGA_FIFO_CAPABILITIES = 4,
 214     SVGA_FIFO_FLAGS,
 215     SVGA_FIFO_FENCE,
 216     SVGA_FIFO_3D_HWVERSION,
 217     SVGA_FIFO_PITCHLOCK,
 218 };
 219
 220 #define SVGA_FIFO_CAP_NONE              0
 221 #define SVGA_FIFO_CAP_FENCE             (1 << 0)
 222 #define SVGA_FIFO_CAP_ACCELFRONT        (1 << 1)
 223 #define SVGA_FIFO_CAP_PITCHLOCK         (1 << 2)
 224
 225 #define SVGA_FIFO_FLAG_NONE             0
 226 #define SVGA_FIFO_FLAG_ACCELFRONT       (1 << 0)
 227
 228 /* These values can probably be changed arbitrarily.  */
 229 #define SVGA_SCRATCH_SIZE               0x8000
 230 #define SVGA_MAX_WIDTH                  2360
 231 #define SVGA_MAX_HEIGHT                 1770
 232
 233 #ifdef VERBOSE
 234 # define GUEST_OS_BASE          0x5001
 235 static const char *vmsvga_guest_id[] = {
 236     [0x00 ... 0x15] = "an unknown OS",
 237     [0x00] = "Dos",
 238     [0x01] = "Windows 3.1",
 239     [0x02] = "Windows 95",
 240     [0x03] = "Windows 98",
 241     [0x04] = "Windows ME",
 242     [0x05] = "Windows NT",
 243     [0x06] = "Windows 2000",
 244     [0x07] = "Linux",
 245     [0x08] = "OS/2",
 246     [0x0a] = "BSD",
 247     [0x0b] = "Whistler",
 248     [0x15] = "Windows 2003",
 249 };
 250 #endif
 251
 252 enum {
 253     SVGA_CMD_INVALID_CMD = 0,
 254     SVGA_CMD_UPDATE = 1,
 255     SVGA_CMD_RECT_FILL = 2,
 256     SVGA_CMD_RECT_COPY = 3,
 257     SVGA_CMD_DEFINE_BITMAP = 4,
 258     SVGA_CMD_DEFINE_BITMAP_SCANLINE = 5,
 259     SVGA_CMD_DEFINE_PIXMAP = 6,
 260     SVGA_CMD_DEFINE_PIXMAP_SCANLINE = 7,
 261     SVGA_CMD_RECT_BITMAP_FILL = 8,
 262     SVGA_CMD_RECT_PIXMAP_FILL = 9,
 263     SVGA_CMD_RECT_BITMAP_COPY = 10,
 264     SVGA_CMD_RECT_PIXMAP_COPY = 11,
 265     SVGA_CMD_FREE_OBJECT = 12,
 266     SVGA_CMD_RECT_ROP_FILL = 13,
 267     SVGA_CMD_RECT_ROP_COPY = 14,
 268     SVGA_CMD_RECT_ROP_BITMAP_FILL = 15,
 269     SVGA_CMD_RECT_ROP_PIXMAP_FILL = 16,
 270     SVGA_CMD_RECT_ROP_BITMAP_COPY = 17,
 271     SVGA_CMD_RECT_ROP_PIXMAP_COPY = 18,
 272     SVGA_CMD_DEFINE_CURSOR = 19,
 273     SVGA_CMD_DISPLAY_CURSOR = 20,
 274     SVGA_CMD_MOVE_CURSOR = 21,
 275     SVGA_CMD_DEFINE_ALPHA_CURSOR = 22,
 276     SVGA_CMD_DRAW_GLYPH = 23,
 277     SVGA_CMD_DRAW_GLYPH_CLIPPED = 24,
 278     SVGA_CMD_UPDATE_VERBOSE = 25,
 279     SVGA_CMD_SURFACE_FILL = 26,
 280     SVGA_CMD_SURFACE_COPY = 27,
 281     SVGA_CMD_SURFACE_ALPHA_BLEND = 28,
 282     SVGA_CMD_FRONT_ROP_FILL = 29,
 283     SVGA_CMD_FENCE = 30,
 284 };
 285
 286 /* Legal values for the SVGA_REG_CURSOR_ON register in cursor bypass mode */
 287 enum {
 288     SVGA_CURSOR_ON_HIDE = 0,
 289     SVGA_CURSOR_ON_SHOW = 1,
 290     SVGA_CURSOR_ON_REMOVE_FROM_FB = 2,
 291     SVGA_CURSOR_ON_RESTORE_TO_FB = 3,
 292 };
 293
 294 static inline void vmsvga_update_rect(struct vmsvga_state_s *s,
 295                 int x, int y, int w, int h)
 296 {
 297 #ifndef DIRECT_VRAM
 298     int line = h;
 299     int bypl = s->bypp * s->width;
 300     int width = s->bypp * w;
 301     int start = s->bypp * x + bypl * y;
 302     uint8_t *src = s->vram + start;
 303     uint8_t *dst = s->ds->data + start;
 304
 305     for (; line > 0; line --, src += bypl, dst += bypl)
 306         memcpy(dst, src, width);
 307 #endif
 308
 309     dpy_update(s->ds, x, y, w, h);
 310 }
 311
 312 static inline void vmsvga_update_screen(struct vmsvga_state_s *s)
 313 {
 314 #ifndef DIRECT_VRAM
 315     memcpy(s->ds->data, s->vram, s->bypp * s->width * s->height);
 316 #endif
 317
 318     dpy_update(s->ds, 0, 0, s->width, s->height);
 319 }
 320
 321 #ifdef DIRECT_VRAM
 322 # define vmsvga_update_rect_delayed     vmsvga_update_rect
 323 #else
 324 static inline void vmsvga_update_rect_delayed(struct vmsvga_state_s *s,
 325                 int x, int y, int w, int h)
 326 {
 327     struct vmsvga_rect_s *rect = &s->redraw_fifo[s->redraw_fifo_last ++];
 328     s->redraw_fifo_last &= REDRAW_FIFO_LEN - 1;
 329     rect->x = x;
 330     rect->y = y;
 331     rect->w = w;
 332     rect->h = h;
 333 }
 334 #endif
 335
 336 static inline void vmsvga_update_rect_flush(struct vmsvga_state_s *s)
 337 {
 338     struct vmsvga_rect_s *rect;
 339     if (s->invalidated) {
 340         s->redraw_fifo_first = s->redraw_fifo_last;
 341         return;
 342     }
 343     /* Overlapping region updates can be optimised out here - if someone
 344      * knows a smart algorithm to do that, please share.  */
 345     while (s->redraw_fifo_first != s->redraw_fifo_last) {
 346         rect = &s->redraw_fifo[s->redraw_fifo_first ++];
 347         s->redraw_fifo_first &= REDRAW_FIFO_LEN - 1;
 348         vmsvga_update_rect(s, rect->x, rect->y, rect->w, rect->h);
 349     }
 350 }
 351
 352 #ifdef HW_RECT_ACCEL
 353 static inline void vmsvga_copy_rect(struct vmsvga_state_s *s,
 354                 int x0, int y0, int x1, int y1, int w, int h)
 355 {
 356 # ifdef DIRECT_VRAM
 357     uint8_t *vram = s->ds->data;
 358 # else
 359     uint8_t *vram = s->vram;
 360 # endif
 361     int bypl = s->bypp * s->width;
 362     int width = s->bypp * w;
 363     int line = h;
 364     uint8_t *ptr[2];
 365
 366 # ifdef DIRECT_VRAM
 367     if (s->ds->dpy_copy)
 368         s->ds->dpy_copy(s->ds, x0, y0, x1, y1, w, h);
 369     else
 370 # endif
 371     {
 372         if (y1 > y0) {
 373             ptr[0] = vram + s->bypp * x0 + bypl * (y0 + h - 1);
 374             ptr[1] = vram + s->bypp * x1 + bypl * (y1 + h - 1);
 375             for (; line > 0; line --, ptr[0] -= bypl, ptr[1] -= bypl)
 376                 memmove(ptr[1], ptr[0], width);
 377         } else {
 378             ptr[0] = vram + s->bypp * x0 + bypl * y0;
 379             ptr[1] = vram + s->bypp * x1 + bypl * y1;
 380             for (; line > 0; line --, ptr[0] += bypl, ptr[1] += bypl)
 381                 memmove(ptr[1], ptr[0], width);
 382         }
 383     }
 384
 385     vmsvga_update_rect_delayed(s, x1, y1, w, h);
 386 }
 387 #endif
 388
 389 #ifdef HW_FILL_ACCEL
 390 static inline void vmsvga_fill_rect(struct vmsvga_state_s *s,
 391                 uint32_t c, int x, int y, int w, int h)
 392 {
 393 # ifdef DIRECT_VRAM
 394     uint8_t *vram = s->ds->data;
 395 # else
 396     uint8_t *vram = s->vram;
 397 # endif
 398     int bypp = s->bypp;
 399     int bypl = bypp * s->width;
 400     int width = bypp * w;
 401     int line = h;
 402     int column;
 403     uint8_t *fst = vram + bypp * x + bypl * y;
 404     uint8_t *dst;
 405     uint8_t *src;
 406     uint8_t col[4];
 407
 408 # ifdef DIRECT_VRAM
 409     if (s->ds->dpy_fill)
 410         s->ds->dpy_fill(s->ds, x, y, w, h, c);
 411     else
 412 # endif
 413     {
 414         col[0] = c;
 415         col[1] = c >> 8;
 416         col[2] = c >> 16;
 417         col[3] = c >> 24;
 418
 419         if (line --) {
 420             dst = fst;
 421             src = col;
 422             for (column = width; column > 0; column --) {
 423                 *(dst ++) = *(src ++);
 424                 if (src - col == bypp)
 425                     src = col;
 426             }
 427             dst = fst;
 428             for (; line > 0; line --) {
 429                 dst += bypl;
 430                 memcpy(dst, fst, width);
 431             }
 432         }
 433     }
 434
 435     vmsvga_update_rect_delayed(s, x, y, w, h);
 436 }
 437 #endif
 438
 439 struct vmsvga_cursor_definition_s {
 440     int width;
 441     int height;
 442     int id;
 443     int bpp;
 444     int hot_x;
 445     int hot_y;
 446     uint32_t mask[1024];
 447     uint32_t image[1024];
 448 };
 449
 450 #define SVGA_BITMAP_SIZE(w, h)          ((((w) + 31) >> 5) * (h))
 451 #define SVGA_PIXMAP_SIZE(w, h, bpp)     (((((w) * (bpp)) + 31) >> 5) * (h))
 452
 453 #ifdef HW_MOUSE_ACCEL
 454 static inline void vmsvga_cursor_define(struct vmsvga_state_s *s,
 455                 struct vmsvga_cursor_definition_s *c)
 456 {
 457     int i;
 458     for (i = SVGA_BITMAP_SIZE(c->width, c->height) - 1; i >= 0; i --)
 459         c->mask[i] = ~c->mask[i];
 460
 461     if (s->ds->cursor_define)
 462         s->ds->cursor_define(c->width, c->height, c->bpp, c->hot_x, c->hot_y,
 463                         (uint8_t *) c->image, (uint8_t *) c->mask);
 464 }
 465 #endif
 466
 467 static inline int vmsvga_fifo_empty(struct vmsvga_state_s *s)
 468 {
 469     if (!s->config || !s->enable)
 470         return 1;
 471     return (s->cmd->next_cmd == s->cmd->stop);
 472 }
 473
 474 static inline uint32_t vmsvga_fifo_read(struct vmsvga_state_s *s)
 475 {
 476     uint32_t cmd = s->fifo[s->cmd->stop >> 2];
 477     s->cmd->stop += 4;
 478     if (s->cmd->stop >= s->cmd->max)
 479         s->cmd->stop = s->cmd->min;
 480     return cmd;
 481 }
 482
 483 static void vmsvga_fifo_run(struct vmsvga_state_s *s)
 484 {
 485     uint32_t cmd, colour;
 486     int args = 0;
 487     int x, y, dx, dy, width, height;
 488     struct vmsvga_cursor_definition_s cursor;
 489     while (!vmsvga_fifo_empty(s))
 490         switch (cmd = vmsvga_fifo_read(s)) {
 491         case SVGA_CMD_UPDATE:
 492         case SVGA_CMD_UPDATE_VERBOSE:
 493             x = vmsvga_fifo_read(s);
 494             y = vmsvga_fifo_read(s);
 495             width = vmsvga_fifo_read(s);
 496             height = vmsvga_fifo_read(s);
 497             vmsvga_update_rect_delayed(s, x, y, width, height);
 498             break;
 499
 500         case SVGA_CMD_RECT_FILL:
 501             colour = vmsvga_fifo_read(s);
 502             x = vmsvga_fifo_read(s);
 503             y = vmsvga_fifo_read(s);
 504             width = vmsvga_fifo_read(s);
 505             height = vmsvga_fifo_read(s);
 506 #ifdef HW_FILL_ACCEL
 507             vmsvga_fill_rect(s, colour, x, y, width, height);
 508             break;
 509 #else
 510             goto badcmd;
 511 #endif
 512
 513         case SVGA_CMD_RECT_COPY:
 514             x = vmsvga_fifo_read(s);
 515             y = vmsvga_fifo_read(s);
 516             dx = vmsvga_fifo_read(s);
 517             dy = vmsvga_fifo_read(s);
 518             width = vmsvga_fifo_read(s);
 519             height = vmsvga_fifo_read(s);
 520 #ifdef HW_RECT_ACCEL
 521             vmsvga_copy_rect(s, x, y, dx, dy, width, height);
 522             break;
 523 #else
 524             goto badcmd;
 525 #endif
 526
 527         case SVGA_CMD_DEFINE_CURSOR:
 528             cursor.id = vmsvga_fifo_read(s);
 529             cursor.hot_x = vmsvga_fifo_read(s);
 530             cursor.hot_y = vmsvga_fifo_read(s);
 531             cursor.width = x = vmsvga_fifo_read(s);
 532             cursor.height = y = vmsvga_fifo_read(s);
 533             vmsvga_fifo_read(s);
 534             cursor.bpp = vmsvga_fifo_read(s);
 535             for (args = 0; args < SVGA_BITMAP_SIZE(x, y); args ++)
 536                 cursor.mask[args] = vmsvga_fifo_read(s);
 537             for (args = 0; args < SVGA_PIXMAP_SIZE(x, y, cursor.bpp); args ++)
 538                 cursor.image[args] = vmsvga_fifo_read(s);
 539 #ifdef HW_MOUSE_ACCEL
 540             vmsvga_cursor_define(s, &cursor);
 541             break;
 542 #else
 543             args = 0;
 544             goto badcmd;
 545 #endif
 546
 547         /*
 548          * Other commands that we at least know the number of arguments
 549          * for so we can avoid FIFO desync if driver uses them illegally.
 550          */
 551         case SVGA_CMD_DEFINE_ALPHA_CURSOR:
 552             vmsvga_fifo_read(s);
 553             vmsvga_fifo_read(s);
 554             vmsvga_fifo_read(s);
 555             x = vmsvga_fifo_read(s);
 556             y = vmsvga_fifo_read(s);
 557             args = x * y;
 558             goto badcmd;
 559         case SVGA_CMD_RECT_ROP_FILL:
 560             args = 6;
 561             goto badcmd;
 562         case SVGA_CMD_RECT_ROP_COPY:
 563             args = 7;
 564             goto badcmd;
 565         case SVGA_CMD_DRAW_GLYPH_CLIPPED:
 566             vmsvga_fifo_read(s);
 567             vmsvga_fifo_read(s);
 568             args = 7 + (vmsvga_fifo_read(s) >> 2);
 569             goto badcmd;
 570         case SVGA_CMD_SURFACE_ALPHA_BLEND:
 571             args = 12;
 572             goto badcmd;
 573
 574         /*
 575          * Other commands that are not listed as depending on any
 576          * CAPABILITIES bits, but are not described in the README either.
 577          */
 578         case SVGA_CMD_SURFACE_FILL:
 579         case SVGA_CMD_SURFACE_COPY:
 580         case SVGA_CMD_FRONT_ROP_FILL:
 581         case SVGA_CMD_FENCE:
 582         case SVGA_CMD_INVALID_CMD:
 583             break; /* Nop */
 584
 585         default:
 586         badcmd:
 587             while (args --)
 588                 vmsvga_fifo_read(s);
 589             printf("%s: Unknown command 0x%02x in SVGA command FIFO\n",
 590                             __FUNCTION__, cmd);
 591             break;
 592         }
 593
 594     s->syncing = 0;
 595 }
 596
 597 static uint32_t vmsvga_index_read(void *opaque, uint32_t address)
 598 {
 599     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 600     return s->index;
 601 }
 602
 603 static void vmsvga_index_write(void *opaque, uint32_t address, uint32_t index)
 604 {
 605     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 606     s->index = index;
 607 }
 608
 609 static uint32_t vmsvga_value_read(void *opaque, uint32_t address)
 610 {
 611     uint32_t caps;
 612     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 613     switch (s->index) {
 614     case SVGA_REG_ID:
 615         return s->svgaid;
 616
 617     case SVGA_REG_ENABLE:
 618         return s->enable;
 619
 620     case SVGA_REG_WIDTH:
 621         return s->width;
 622
 623     case SVGA_REG_HEIGHT:
 624         return s->height;
 625
 626     case SVGA_REG_MAX_WIDTH:
 627         return SVGA_MAX_WIDTH;
 628
 629     case SVGA_REG_MAX_HEIGHT:
 630         return SVGA_MAX_HEIGHT;
 631
 632     case SVGA_REG_DEPTH:
 633         return s->depth;
 634
 635     case SVGA_REG_BITS_PER_PIXEL:
 636         return (s->depth + 7) & ~7;
 637
 638     case SVGA_REG_PSEUDOCOLOR:
 639         return 0x0;
 640
 641     case SVGA_REG_RED_MASK:
 642         return s->wred;
 643     case SVGA_REG_GREEN_MASK:
 644         return s->wgreen;
 645     case SVGA_REG_BLUE_MASK:
 646         return s->wblue;
 647
 648     case SVGA_REG_BYTES_PER_LINE:
 649         return ((s->depth + 7) >> 3) * s->new_width;
 650
 651     case SVGA_REG_FB_START:
 652         return s->vram_addr;
 653
 654     case SVGA_REG_FB_OFFSET:
 655         return 0x0;
 656
 657     case SVGA_REG_VRAM_SIZE:
 658         return s->vram_size - SVGA_FIFO_SIZE;
 659
 660     case SVGA_REG_FB_SIZE:
 661         return s->fb_size;
 662
 663     case SVGA_REG_CAPABILITIES:
 664         caps = SVGA_CAP_NONE;
 665 #ifdef HW_RECT_ACCEL
 666         caps |= SVGA_CAP_RECT_COPY;
 667 #endif
 668 #ifdef HW_FILL_ACCEL
 669         caps |= SVGA_CAP_RECT_FILL;
 670 #endif
 671 #ifdef HW_MOUSE_ACCEL
 672         if (s->ds->mouse_set)
 673             caps |= SVGA_CAP_CURSOR | SVGA_CAP_CURSOR_BYPASS_2 |
 674                     SVGA_CAP_CURSOR_BYPASS;
 675 #endif
 676         return caps;
 677
 678     case SVGA_REG_MEM_START:
 679         return s->vram_addr + s->vram_size - SVGA_FIFO_SIZE;
 680
 681     case SVGA_REG_MEM_SIZE:
 682         return SVGA_FIFO_SIZE;
 683
 684     case SVGA_REG_CONFIG_DONE:
 685         return s->config;
 686
 687     case SVGA_REG_SYNC:
 688     case SVGA_REG_BUSY:
 689         return s->syncing;
 690
 691     case SVGA_REG_GUEST_ID:
 692         return s->guest;
 693
 694     case SVGA_REG_CURSOR_ID:
 695         return s->cursor.id;
 696
 697     case SVGA_REG_CURSOR_X:
 698         return s->cursor.x;
 699
 700     case SVGA_REG_CURSOR_Y:
 701         return s->cursor.x;
 702
 703     case SVGA_REG_CURSOR_ON:
 704         return s->cursor.on;
 705
 706     case SVGA_REG_HOST_BITS_PER_PIXEL:
 707         return (s->depth + 7) & ~7;
 708
 709     case SVGA_REG_SCRATCH_SIZE:
 710         return s->scratch_size;
 711
 712     case SVGA_REG_MEM_REGS:
 713     case SVGA_REG_NUM_DISPLAYS:
 714     case SVGA_REG_PITCHLOCK:
 715     case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
 716         return 0;
 717
 718     default:
 719         if (s->index >= SVGA_SCRATCH_BASE &&
 720                 s->index < SVGA_SCRATCH_BASE + s->scratch_size)
 721             return s->scratch[s->index - SVGA_SCRATCH_BASE];
 722         printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
 723     }
 724
 725     return 0;
 726 }
 727
 728 static void vmsvga_value_write(void *opaque, uint32_t address, uint32_t value)
 729 {
 730     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 731     switch (s->index) {
 732     case SVGA_REG_ID:
 733         if (value == SVGA_ID_2 || value == SVGA_ID_1 || value == SVGA_ID_0)
 734             s->svgaid = value;
 735         break;
 736
 737     case SVGA_REG_ENABLE:
 738         s->enable = value;
 739         s->config &= !!value;
 740         s->width = -1;
 741         s->height = -1;
 742         s->invalidated = 1;
 743 #ifdef EMBED_STDVGA
 744         s->invalidate(opaque);
 745 #endif
 746         if (s->enable)
 747             s->fb_size = ((s->depth + 7) >> 3) * s->new_width * s->new_height;
 748         break;
 749
 750     case SVGA_REG_WIDTH:
 751         s->new_width = value;
 752         s->invalidated = 1;
 753         break;
 754
 755     case SVGA_REG_HEIGHT:
 756         s->new_height = value;
 757         s->invalidated = 1;
 758         break;
 759
 760     case SVGA_REG_DEPTH:
 761     case SVGA_REG_BITS_PER_PIXEL:
 762         if (value != s->depth) {
 763             printf("%s: Bad colour depth: %i bits\n", __FUNCTION__, value);
 764             s->config = 0;
 765         }
 766         break;
 767
 768     case SVGA_REG_CONFIG_DONE:
 769         if (value) {
 770             s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
 771             /* Check range and alignment.  */
 772             if ((s->cmd->min | s->cmd->max |
 773                         s->cmd->next_cmd | s->cmd->stop) & 3)
 774                 break;
 775             if (s->cmd->min < (uint8_t *) s->cmd->fifo - (uint8_t *) s->fifo)
 776                 break;
 777             if (s->cmd->max > SVGA_FIFO_SIZE)
 778                 break;
 779             if (s->cmd->max < s->cmd->min + 10 * 1024)
 780                 break;
 781         }
 782         s->config = !!value;
 783         break;
 784
 785     case SVGA_REG_SYNC:
 786         s->syncing = 1;
 787         vmsvga_fifo_run(s); /* Or should we just wait for update_display? */
 788         break;
 789
 790     case SVGA_REG_GUEST_ID:
 791         s->guest = value;
 792 #ifdef VERBOSE
 793         if (value >= GUEST_OS_BASE && value < GUEST_OS_BASE +
 794                 sizeof(vmsvga_guest_id) / sizeof(*vmsvga_guest_id))
 795             printf("%s: guest runs %s.\n", __FUNCTION__,
 796                             vmsvga_guest_id[value - GUEST_OS_BASE]);
 797 #endif
 798         break;
 799
 800     case SVGA_REG_CURSOR_ID:
 801         s->cursor.id = value;
 802         break;
 803
 804     case SVGA_REG_CURSOR_X:
 805         s->cursor.x = value;
 806         break;
 807
 808     case SVGA_REG_CURSOR_Y:
 809         s->cursor.y = value;
 810         break;
 811
 812     case SVGA_REG_CURSOR_ON:
 813         s->cursor.on |= (value == SVGA_CURSOR_ON_SHOW);
 814         s->cursor.on &= (value != SVGA_CURSOR_ON_HIDE);
 815 #ifdef HW_MOUSE_ACCEL
 816         if (s->ds->mouse_set && value <= SVGA_CURSOR_ON_SHOW)
 817             s->ds->mouse_set(s->cursor.x, s->cursor.y, s->cursor.on);
 818 #endif
 819         break;
 820
 821     case SVGA_REG_MEM_REGS:
 822     case SVGA_REG_NUM_DISPLAYS:
 823     case SVGA_REG_PITCHLOCK:
 824     case SVGA_PALETTE_BASE ... SVGA_PALETTE_END:
 825         break;
 826
 827     default:
 828         if (s->index >= SVGA_SCRATCH_BASE &&
 829                 s->index < SVGA_SCRATCH_BASE + s->scratch_size) {
 830             s->scratch[s->index - SVGA_SCRATCH_BASE] = value;
 831             break;
 832         }
 833         printf("%s: Bad register %02x\n", __FUNCTION__, s->index);
 834     }
 835 }
 836
 837 static uint32_t vmsvga_bios_read(void *opaque, uint32_t address)
 838 {
 839     printf("%s: what are we supposed to return?\n", __FUNCTION__);
 840     return 0xcafe;
 841 }
 842
 843 static void vmsvga_bios_write(void *opaque, uint32_t address, uint32_t data)
 844 {
 845     printf("%s: what are we supposed to do with (%08x)?\n",
 846                     __FUNCTION__, data);
 847 }
 848
 849 static inline void vmsvga_size(struct vmsvga_state_s *s)
 850 {
 851     if (s->new_width != s->width || s->new_height != s->height) {
 852         s->width = s->new_width;
 853         s->height = s->new_height;
 854         dpy_resize(s->ds, s->width, s->height);
 855         s->invalidated = 1;
 856     }
 857 }
 858
 859 static void vmsvga_update_display(void *opaque)
 860 {
 861     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 862     if (!s->enable) {
 863 #ifdef EMBED_STDVGA
 864         s->update(opaque);
 865 #endif
 866         return;
 867     }
 868
 869     vmsvga_size(s);
 870
 871     vmsvga_fifo_run(s);
 872     vmsvga_update_rect_flush(s);
 873
 874     /*
 875      * Is it more efficient to look at vram VGA-dirty bits or wait
 876      * for the driver to issue SVGA_CMD_UPDATE?
 877      */
 878     if (s->invalidated) {
 879         s->invalidated = 0;
 880         vmsvga_update_screen(s);
 881     }
 882 }
 883
 884 static void vmsvga_reset(struct vmsvga_state_s *s)
 885 {
 886     s->index = 0;
 887     s->enable = 0;
 888     s->config = 0;
 889     s->width = -1;
 890     s->height = -1;
 891     s->svgaid = SVGA_ID;
 892     s->depth = s->ds->depth ? s->ds->depth : 24;
 893     s->bypp = (s->depth + 7) >> 3;
 894     s->cursor.on = 0;
 895     s->redraw_fifo_first = 0;
 896     s->redraw_fifo_last = 0;
 897     switch (s->depth) {
 898     case 8:
 899         s->wred   = 0x00000007;
 900         s->wgreen = 0x00000038;
 901         s->wblue  = 0x000000c0;
 902         break;
 903     case 15:
 904         s->wred   = 0x0000001f;
 905         s->wgreen = 0x000003e0;
 906         s->wblue  = 0x00007c00;
 907         break;
 908     case 16:
 909         s->wred   = 0x0000001f;
 910         s->wgreen = 0x000007e0;
 911         s->wblue  = 0x0000f800;
 912         break;
 913     case 24:
 914         s->wred   = 0x00ff0000;
 915         s->wgreen = 0x0000ff00;
 916         s->wblue  = 0x000000ff;
 917         break;
 918     case 32:
 919         s->wred   = 0x00ff0000;
 920         s->wgreen = 0x0000ff00;
 921         s->wblue  = 0x000000ff;
 922         break;
 923     }
 924     s->syncing = 0;
 925 }
 926
 927 static void vmsvga_invalidate_display(void *opaque)
 928 {
 929     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 930     if (!s->enable) {
 931 #ifdef EMBED_STDVGA
 932         s->invalidate(opaque);
 933 #endif
 934         return;
 935     }
 936
 937     s->invalidated = 1;
 938 }
 939
 940 /* save the vga display in a PPM image even if no display is
 941    available */
 942 static void vmsvga_screen_dump(void *opaque, const char *filename)
 943 {
 944     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 945     if (!s->enable) {
 946 #ifdef EMBED_STDVGA
 947         s->screen_dump(opaque, filename);
 948 #endif
 949         return;
 950     }
 951
 952     if (s->depth == 32) {
 953         ppm_save(filename, s->vram, s->width, s->height, s->ds->linesize);
 954     }
 955 }
 956
 957 #ifdef DIRECT_VRAM
 958 static uint32_t vmsvga_vram_readb(void *opaque, target_phys_addr_t addr)
 959 {
 960     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 961     addr -= s->vram_addr;
 962     if (addr < s->fb_size)
 963         return *(uint8_t *) (s->ds->data + addr);
 964     else
 965         return *(uint8_t *) (s->vram + addr);
 966 }
 967
 968 static uint32_t vmsvga_vram_readw(void *opaque, target_phys_addr_t addr)
 969 {
 970     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 971     addr -= s->vram_addr;
 972     if (addr < s->fb_size)
 973         return *(uint16_t *) (s->ds->data + addr);
 974     else
 975         return *(uint16_t *) (s->vram + addr);
 976 }
 977
 978 static uint32_t vmsvga_vram_readl(void *opaque, target_phys_addr_t addr)
 979 {
 980     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 981     addr -= s->vram_addr;
 982     if (addr < s->fb_size)
 983         return *(uint32_t *) (s->ds->data + addr);
 984     else
 985         return *(uint32_t *) (s->vram + addr);
 986 }
 987
 988 static void vmsvga_vram_writeb(void *opaque, target_phys_addr_t addr,
 989                 uint32_t value)
 990 {
 991     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
 992     addr -= s->vram_addr;
 993     if (addr < s->fb_size)
 994         *(uint8_t *) (s->ds->data + addr) = value;
 995     else
 996         *(uint8_t *) (s->vram + addr) = value;
 997 }
 998
 999 static void vmsvga_vram_writew(void *opaque, target_phys_addr_t addr,
1000                 uint32_t value)
1001 {
1002     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1003     addr -= s->vram_addr;
1004     if (addr < s->fb_size)
1005         *(uint16_t *) (s->ds->data + addr) = value;
1006     else
1007         *(uint16_t *) (s->vram + addr) = value;
1008 }
1009
1010 static void vmsvga_vram_writel(void *opaque, target_phys_addr_t addr,
1011                 uint32_t value)
1012 {
1013     struct vmsvga_state_s *s = (struct vmsvga_state_s *) opaque;
1014     addr -= s->vram_addr;
1015     if (addr < s->fb_size)
1016         *(uint32_t *) (s->ds->data + addr) = value;
1017     else
1018         *(uint32_t *) (s->vram + addr) = value;
1019 }
1020
1021 static CPUReadMemoryFunc *vmsvga_vram_read[] = {
1022     vmsvga_vram_readb,
1023     vmsvga_vram_readw,
1024     vmsvga_vram_readl,
1025 };
1026
1027 static CPUWriteMemoryFunc *vmsvga_vram_write[] = {
1028     vmsvga_vram_writeb,
1029     vmsvga_vram_writew,
1030     vmsvga_vram_writel,
1031 };
1032 #endif
1033
1034 static void vmsvga_save(struct vmsvga_state_s *s, QEMUFile *f)
1035 {
1036     qemu_put_be32(f, s->depth);
1037     qemu_put_be32(f, s->enable);
1038     qemu_put_be32(f, s->config);
1039     qemu_put_be32(f, s->cursor.id);
1040     qemu_put_be32(f, s->cursor.x);
1041     qemu_put_be32(f, s->cursor.y);
1042     qemu_put_be32(f, s->cursor.on);
1043     qemu_put_be32(f, s->index);
1044     qemu_put_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
1045     qemu_put_be32(f, s->new_width);
1046     qemu_put_be32(f, s->new_height);
1047     qemu_put_be32s(f, &s->guest);
1048     qemu_put_be32s(f, &s->svgaid);
1049     qemu_put_be32(f, s->syncing);
1050     qemu_put_be32(f, s->fb_size);
1051 }
1052
1053 static int vmsvga_load(struct vmsvga_state_s *s, QEMUFile *f)
1054 {
1055     int depth;
1056     depth=qemu_get_be32(f);
1057     s->enable=qemu_get_be32(f);
1058     s->config=qemu_get_be32(f);
1059     s->cursor.id=qemu_get_be32(f);
1060     s->cursor.x=qemu_get_be32(f);
1061     s->cursor.y=qemu_get_be32(f);
1062     s->cursor.on=qemu_get_be32(f);
1063     s->index=qemu_get_be32(f);
1064     qemu_get_buffer(f, (uint8_t *) s->scratch, s->scratch_size * 4);
1065     s->new_width=qemu_get_be32(f);
1066     s->new_height=qemu_get_be32(f);
1067     qemu_get_be32s(f, &s->guest);
1068     qemu_get_be32s(f, &s->svgaid);
1069     s->syncing=qemu_get_be32(f);
1070     s->fb_size=qemu_get_be32(f);
1071
1072     if (s->enable && depth != s->depth) {
1073         printf("%s: need colour depth of %i bits to resume operation.\n",
1074                         __FUNCTION__, depth);
1075         return -EINVAL;
1076     }
1077
1078     s->invalidated = 1;
1079     if (s->config)
1080         s->fifo = (uint32_t *) &s->vram[s->vram_size - SVGA_FIFO_SIZE];
1081
1082     return 0;
1083 }
1084
1085 static void vmsvga_init(struct vmsvga_state_s *s, DisplayState *ds,
1086                 uint8_t *vga_ram_base, unsigned long vga_ram_offset,
1087                 int vga_ram_size)
1088 {
1089     s->ds = ds;
1090     s->vram = vga_ram_base;
1091     s->vram_size = vga_ram_size;
1092     s->vram_addr = 0;
1093
1094     s->scratch_size = SVGA_SCRATCH_SIZE;
1095     s->scratch = (uint32_t *) qemu_malloc(s->scratch_size * 4);
1096
1097     vmsvga_reset(s);
1098
1099 #ifdef DIRECT_VRAM
1100     s->iomemtype = cpu_register_io_memory(0, vmsvga_vram_read,
1101                                           vmsvga_vram_write, s);
1102 #else
1103     s->iomemtype = vga_ram_offset | IO_MEM_RAM;
1104 #endif
1105
1106     graphic_console_init(ds, vmsvga_update_display,
1107                     vmsvga_invalidate_display, vmsvga_screen_dump, s);
1108
1109 #ifdef EMBED_STDVGA
1110     vga_common_init((VGAState *) s, ds,
1111                     vga_ram_base, vga_ram_offset, vga_ram_size);
1112     vga_init((VGAState *) s);
1113 #endif
1114 }
1115
1116 static void pci_vmsvga_save(QEMUFile *f, void *opaque)
1117 {
1118     struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque;
1119     pci_device_save(&s->card, f);
1120     vmsvga_save(&s->chip, f);
1121 }
1122
1123 static int pci_vmsvga_load(QEMUFile *f, void *opaque, int version_id)
1124 {
1125     struct pci_vmsvga_state_s *s = (struct pci_vmsvga_state_s *) opaque;
1126     int ret;
1127
1128     ret = pci_device_load(&s->card, f);
1129     if (ret < 0)
1130         return ret;
1131
1132     ret = vmsvga_load(&s->chip, f);
1133     if (ret < 0)
1134         return ret;
1135
1136     return 0;
1137 }
1138
1139 static void pci_vmsvga_map(PCIDevice *pci_dev, int region_num,
1140                 uint32_t addr, uint32_t size, int type)
1141 {
1142     struct pci_vmsvga_state_s *d = (struct pci_vmsvga_state_s *) pci_dev;
1143     struct vmsvga_state_s *s = &d->chip;
1144
1145     if (region_num == 0) {
1146         register_ioport_read(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1147                              1, 4, vmsvga_index_read, s);
1148         register_ioport_write(addr + SVGA_IO_MUL * SVGA_INDEX_PORT,
1149                               1, 4, vmsvga_index_write, s);
1150         register_ioport_read(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1151                              1, 4, vmsvga_value_read, s);
1152         register_ioport_write(addr + SVGA_IO_MUL * SVGA_VALUE_PORT,
1153                               1, 4, vmsvga_value_write, s);
1154         register_ioport_read(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1155                              1, 4, vmsvga_bios_read, s);
1156         register_ioport_write(addr + SVGA_IO_MUL * SVGA_BIOS_PORT,
1157                               1, 4, vmsvga_bios_write, s);
1158     } else {
1159         cpu_register_physical_memory(addr, s->vram_size, s->iomemtype);
1160         s->vram_addr = addr;
1161         if (kvm_enabled())
1162             vga_update_vram_mapping((VGAState *)s, addr, addr + VGA_RAM_SIZE);
1163         s->vram = s->vram_ptr;
1164     }
1165 }
1166
1167 #define PCI_VENDOR_ID_VMWARE            0x15ad
1168 #define PCI_DEVICE_ID_VMWARE_SVGA2      0x0405
1169 #define PCI_DEVICE_ID_VMWARE_SVGA       0x0710
1170 #define PCI_DEVICE_ID_VMWARE_NET        0x0720
1171 #define PCI_DEVICE_ID_VMWARE_SCSI       0x0730
1172 #define PCI_DEVICE_ID_VMWARE_IDE        0x1729
1173 #define PCI_CLASS_BASE_DISPLAY          0x03
1174 #define PCI_CLASS_SUB_VGA               0x00
1175 #define PCI_CLASS_HEADERTYPE_00h        0x00
1176
1177 void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
1178                      unsigned long vga_ram_offset, int vga_ram_size)
1179 {
1180     struct pci_vmsvga_state_s *s;
1181
1182     /* Setup PCI configuration */
1183     s = (struct pci_vmsvga_state_s *)
1184         pci_register_device(bus, "QEMUware SVGA",
1185                 sizeof(struct pci_vmsvga_state_s), -1, 0, 0);
1186     s->card.config[PCI_VENDOR_ID]       = PCI_VENDOR_ID_VMWARE & 0xff;
1187     s->card.config[PCI_VENDOR_ID + 1]   = PCI_VENDOR_ID_VMWARE >> 8;
1188     s->card.config[PCI_DEVICE_ID]       = SVGA_PCI_DEVICE_ID & 0xff;
1189     s->card.config[PCI_DEVICE_ID + 1]   = SVGA_PCI_DEVICE_ID >> 8;
1190     s->card.config[PCI_COMMAND]         = 0x07;         /* I/O + Memory */
1191     s->card.config[PCI_CLASS_DEVICE]    = PCI_CLASS_SUB_VGA;
1192     s->card.config[0x0b]                = PCI_CLASS_BASE_DISPLAY;
1193     s->card.config[0x0c]                = 0x08;         /* Cache line size */
1194     s->card.config[0x0d]                = 0x40;         /* Latency timer */
1195     s->card.config[0x0e]                = PCI_CLASS_HEADERTYPE_00h;
1196     s->card.config[0x2c]                = PCI_VENDOR_ID_VMWARE & 0xff;
1197     s->card.config[0x2d]                = PCI_VENDOR_ID_VMWARE >> 8;
1198     s->card.config[0x2e]                = SVGA_PCI_DEVICE_ID & 0xff;
1199     s->card.config[0x2f]                = SVGA_PCI_DEVICE_ID >> 8;
1200     s->card.config[0x3c]                = 0xff;         /* End */
1201
1202     pci_register_io_region(&s->card, 0, 0x10,
1203                            PCI_ADDRESS_SPACE_IO, pci_vmsvga_map);
1204
1205     pci_register_io_region(&s->card, 1, vga_ram_size,
1206                            PCI_ADDRESS_SPACE_MEM, pci_vmsvga_map);
1207
1208     vmsvga_init(&s->chip, ds, vga_ram_base, vga_ram_offset, vga_ram_size);
1209
1210     register_savevm("vmware_vga", 0, 0, pci_vmsvga_save, pci_vmsvga_load, s);
1211 }