hw/i8259.c

   1 /*
   2  * QEMU 8259 interrupt controller emulation
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "isa.h"
  27 #include "console.h"
  28
  29 #include "qemu-kvm.h"
  30
  31 /* debug PIC */
  32 //#define DEBUG_PIC
  33
  34 //#define DEBUG_IRQ_LATENCY
  35 //#define DEBUG_IRQ_COUNT
  36
  37 typedef struct PicState {
  38     uint8_t last_irr; /* edge detection */
  39     uint8_t irr; /* interrupt request register */
  40     uint8_t imr; /* interrupt mask register */
  41     uint8_t isr; /* interrupt service register */
  42     uint8_t priority_add; /* highest irq priority */
  43     uint8_t irq_base;
  44     uint8_t read_reg_select;
  45     uint8_t poll;
  46     uint8_t special_mask;
  47     uint8_t init_state;
  48     uint8_t auto_eoi;
  49     uint8_t rotate_on_auto_eoi;
  50     uint8_t special_fully_nested_mode;
  51     uint8_t init4; /* true if 4 byte init */
  52     uint8_t single_mode; /* true if slave pic is not initialized */
  53     uint8_t elcr; /* PIIX edge/trigger selection*/
  54     uint8_t elcr_mask;
  55     PicState2 *pics_state;
  56 } PicState;
  57
  58 struct PicState2 {
  59     /* 0 is master pic, 1 is slave pic */
  60     /* XXX: better separation between the two pics */
  61     PicState pics[2];
  62     qemu_irq parent_irq;
  63     void *irq_request_opaque;
  64     /* IOAPIC callback support */
  65     SetIRQFunc *alt_irq_func;
  66     void *alt_irq_opaque;
  67 };
  68
  69 #if defined(DEBUG_PIC) || defined (DEBUG_IRQ_COUNT)
  70 static int irq_level[16];
  71 #endif
  72 #ifdef DEBUG_IRQ_COUNT
  73 static uint64_t irq_count[16];
  74 #endif
  75
  76 /* set irq level. If an edge is detected, then the IRR is set to 1 */
  77 static inline void pic_set_irq1(PicState *s, int irq, int level)
  78 {
  79     int mask;
  80     mask = 1 << irq;
  81     if (s->elcr & mask) {
  82         /* level triggered */
  83         if (level) {
  84             s->irr |= mask;
  85             s->last_irr |= mask;
  86         } else {
  87             s->irr &= ~mask;
  88             s->last_irr &= ~mask;
  89         }
  90     } else {
  91         /* edge triggered */
  92         if (level) {
  93             if ((s->last_irr & mask) == 0)
  94                 s->irr |= mask;
  95             s->last_irr |= mask;
  96         } else {
  97             s->last_irr &= ~mask;
  98         }
  99     }
 100 }
 101
 102 /* return the highest priority found in mask (highest = smallest
 103    number). Return 8 if no irq */
 104 static inline int get_priority(PicState *s, int mask)
 105 {
 106     int priority;
 107     if (mask == 0)
 108         return 8;
 109     priority = 0;
 110     while ((mask & (1 << ((priority + s->priority_add) & 7))) == 0)
 111         priority++;
 112     return priority;
 113 }
 114
 115 /* return the pic wanted interrupt. return -1 if none */
 116 static int pic_get_irq(PicState *s)
 117 {
 118     int mask, cur_priority, priority;
 119
 120     mask = s->irr & ~s->imr;
 121     priority = get_priority(s, mask);
 122     if (priority == 8)
 123         return -1;
 124     /* compute current priority. If special fully nested mode on the
 125        master, the IRQ coming from the slave is not taken into account
 126        for the priority computation. */
 127     mask = s->isr;
 128     if (s->special_fully_nested_mode && s == &s->pics_state->pics[0])
 129         mask &= ~(1 << 2);
 130     cur_priority = get_priority(s, mask);
 131     if (priority < cur_priority) {
 132         /* higher priority found: an irq should be generated */
 133         return (priority + s->priority_add) & 7;
 134     } else {
 135         return -1;
 136     }
 137 }
 138
 139 /* raise irq to CPU if necessary. must be called every time the active
 140    irq may change */
 141 /* XXX: should not export it, but it is needed for an APIC kludge */
 142 void pic_update_irq(PicState2 *s)
 143 {
 144     int irq2, irq;
 145
 146     /* first look at slave pic */
 147     irq2 = pic_get_irq(&s->pics[1]);
 148     if (irq2 >= 0) {
 149         /* if irq request by slave pic, signal master PIC */
 150         pic_set_irq1(&s->pics[0], 2, 1);
 151         pic_set_irq1(&s->pics[0], 2, 0);
 152     }
 153     /* look at requested irq */
 154     irq = pic_get_irq(&s->pics[0]);
 155     if (irq >= 0) {
 156 #if defined(DEBUG_PIC)
 157         {
 158             int i;
 159             for(i = 0; i < 2; i++) {
 160                 printf("pic%d: imr=%x irr=%x padd=%d\n",
 161                        i, s->pics[i].imr, s->pics[i].irr,
 162                        s->pics[i].priority_add);
 163
 164             }
 165         }
 166         printf("pic: cpu_interrupt\n");
 167 #endif
 168         qemu_irq_raise(s->parent_irq);
 169     }
 170
 171 /* all targets should do this rather than acking the IRQ in the cpu */
 172 #if defined(TARGET_MIPS) || defined(TARGET_PPC)
 173     else {
 174         qemu_irq_lower(s->parent_irq);
 175     }
 176 #endif
 177 }
 178
 179 #ifdef DEBUG_IRQ_LATENCY
 180 int64_t irq_time[16];
 181 #endif
 182
 183 static void i8259_set_irq(void *opaque, int irq, int level)
 184 {
 185     PicState2 *s = opaque;
 186 #ifdef KVM_CAP_IRQCHIP
 187     if (kvm_enabled())
 188         if (kvm_set_irq(irq, level))
 189             return;
 190 #endif
 191 #if defined(DEBUG_PIC) || defined(DEBUG_IRQ_COUNT)
 192     if (level != irq_level[irq]) {
 193 #if defined(DEBUG_PIC)
 194         printf("i8259_set_irq: irq=%d level=%d\n", irq, level);
 195 #endif
 196         irq_level[irq] = level;
 197 #ifdef DEBUG_IRQ_COUNT
 198         if (level == 1)
 199             irq_count[irq]++;
 200 #endif
 201     }
 202 #endif
 203 #ifdef DEBUG_IRQ_LATENCY
 204     if (level) {
 205         irq_time[irq] = qemu_get_clock(vm_clock);
 206     }
 207 #endif
 208     pic_set_irq1(&s->pics[irq >> 3], irq & 7, level);
 209     /* used for IOAPIC irqs */
 210     if (s->alt_irq_func)
 211         s->alt_irq_func(s->alt_irq_opaque, irq, level);
 212     pic_update_irq(s);
 213 }
 214
 215 /* acknowledge interrupt 'irq' */
 216 static inline void pic_intack(PicState *s, int irq)
 217 {
 218     if (s->auto_eoi) {
 219         if (s->rotate_on_auto_eoi)
 220             s->priority_add = (irq + 1) & 7;
 221     } else {
 222         s->isr |= (1 << irq);
 223     }
 224
 225     /* We don't clear a level sensitive interrupt here */
 226     if (!(s->elcr & (1 << irq)))
 227         s->irr &= ~(1 << irq);
 228
 229 }
 230
 231 extern int time_drift_fix;
 232
 233 int pic_read_irq(PicState2 *s)
 234 {
 235     int irq, irq2, intno;
 236
 237     irq = pic_get_irq(&s->pics[0]);
 238     if (irq >= 0) {
 239
 240         pic_intack(&s->pics[0], irq);
 241 #ifndef TARGET_IA64
 242         if (time_drift_fix && irq == 0) {
 243             extern int64_t timer_acks, timer_ints_to_push;
 244             timer_acks++;
 245             if (timer_ints_to_push > 0) {
 246                 timer_ints_to_push--;
 247                 /* simulate an edge irq0, like the one generated by i8254 */
 248                 pic_set_irq1(&s->pics[0], 0, 0);
 249                 pic_set_irq1(&s->pics[0], 0, 1);
 250             }
 251         }
 252 #endif
 253         if (irq == 2) {
 254             irq2 = pic_get_irq(&s->pics[1]);
 255             if (irq2 >= 0) {
 256                 pic_intack(&s->pics[1], irq2);
 257             } else {
 258                 /* spurious IRQ on slave controller */
 259                 irq2 = 7;
 260             }
 261             intno = s->pics[1].irq_base + irq2;
 262             irq = irq2 + 8;
 263         } else {
 264             intno = s->pics[0].irq_base + irq;
 265         }
 266     } else {
 267         /* spurious IRQ on host controller */
 268         irq = 7;
 269         intno = s->pics[0].irq_base + irq;
 270     }
 271     pic_update_irq(s);
 272
 273 #ifdef DEBUG_IRQ_LATENCY
 274     printf("IRQ%d latency=%0.3fus\n",
 275            irq,
 276            (double)(qemu_get_clock(vm_clock) - irq_time[irq]) * 1000000.0 / ticks_per_sec);
 277 #endif
 278 #if defined(DEBUG_PIC)
 279     printf("pic_interrupt: irq=%d\n", irq);
 280 #endif
 281     return intno;
 282 }
 283
 284 static void pic_reset(void *opaque)
 285 {
 286     PicState *s = opaque;
 287
 288     s->last_irr = 0;
 289     s->irr = 0;
 290     s->imr = 0;
 291     s->isr = 0;
 292     s->priority_add = 0;
 293     s->irq_base = 0;
 294     s->read_reg_select = 0;
 295     s->poll = 0;
 296     s->special_mask = 0;
 297     s->init_state = 0;
 298     s->auto_eoi = 0;
 299     s->rotate_on_auto_eoi = 0;
 300     s->special_fully_nested_mode = 0;
 301     s->init4 = 0;
 302     s->single_mode = 0;
 303     /* Note: ELCR is not reset */
 304 }
 305
 306 static void pic_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 307 {
 308     PicState *s = opaque;
 309     int priority, cmd, irq;
 310
 311 #ifdef DEBUG_PIC
 312     printf("pic_write: addr=0x%02x val=0x%02x\n", addr, val);
 313 #endif
 314     addr &= 1;
 315     if (addr == 0) {
 316         if (val & 0x10) {
 317             /* init */
 318             pic_reset(s);
 319             /* deassert a pending interrupt */
 320             qemu_irq_lower(s->pics_state->parent_irq);
 321             s->init_state = 1;
 322             s->init4 = val & 1;
 323             s->single_mode = val & 2;
 324             if (val & 0x08)
 325                 hw_error("level sensitive irq not supported");
 326         } else if (val & 0x08) {
 327             if (val & 0x04)
 328                 s->poll = 1;
 329             if (val & 0x02)
 330                 s->read_reg_select = val & 1;
 331             if (val & 0x40)
 332                 s->special_mask = (val >> 5) & 1;
 333         } else {
 334             cmd = val >> 5;
 335             switch(cmd) {
 336             case 0:
 337             case 4:
 338                 s->rotate_on_auto_eoi = cmd >> 2;
 339                 break;
 340             case 1: /* end of interrupt */
 341             case 5:
 342                 priority = get_priority(s, s->isr);
 343                 if (priority != 8) {
 344                     irq = (priority + s->priority_add) & 7;
 345                     s->isr &= ~(1 << irq);
 346                     if (cmd == 5)
 347                         s->priority_add = (irq + 1) & 7;
 348                     pic_update_irq(s->pics_state);
 349                 }
 350                 break;
 351             case 3:
 352                 irq = val & 7;
 353                 s->isr &= ~(1 << irq);
 354                 pic_update_irq(s->pics_state);
 355                 break;
 356             case 6:
 357                 s->priority_add = (val + 1) & 7;
 358                 pic_update_irq(s->pics_state);
 359                 break;
 360             case 7:
 361                 irq = val & 7;
 362                 s->isr &= ~(1 << irq);
 363                 s->priority_add = (irq + 1) & 7;
 364                 pic_update_irq(s->pics_state);
 365                 break;
 366             default:
 367                 /* no operation */
 368                 break;
 369             }
 370         }
 371     } else {
 372         switch(s->init_state) {
 373         case 0:
 374             /* normal mode */
 375             s->imr = val;
 376             pic_update_irq(s->pics_state);
 377             break;
 378         case 1:
 379             s->irq_base = val & 0xf8;
 380             s->init_state = s->single_mode ? (s->init4 ? 3 : 0) : 2;
 381             break;
 382         case 2:
 383             if (s->init4) {
 384                 s->init_state = 3;
 385             } else {
 386                 s->init_state = 0;
 387             }
 388             break;
 389         case 3:
 390             s->special_fully_nested_mode = (val >> 4) & 1;
 391             s->auto_eoi = (val >> 1) & 1;
 392             s->init_state = 0;
 393             break;
 394         }
 395     }
 396 }
 397
 398 static uint32_t pic_poll_read (PicState *s, uint32_t addr1)
 399 {
 400     int ret;
 401
 402     ret = pic_get_irq(s);
 403     if (ret >= 0) {
 404         if (addr1 >> 7) {
 405             s->pics_state->pics[0].isr &= ~(1 << 2);
 406             s->pics_state->pics[0].irr &= ~(1 << 2);
 407         }
 408         s->irr &= ~(1 << ret);
 409         s->isr &= ~(1 << ret);
 410         if (addr1 >> 7 || ret != 2)
 411             pic_update_irq(s->pics_state);
 412     } else {
 413         ret = 0x07;
 414         pic_update_irq(s->pics_state);
 415     }
 416
 417     return ret;
 418 }
 419
 420 static uint32_t pic_ioport_read(void *opaque, uint32_t addr1)
 421 {
 422     PicState *s = opaque;
 423     unsigned int addr;
 424     int ret;
 425
 426     addr = addr1;
 427     addr &= 1;
 428     if (s->poll) {
 429         ret = pic_poll_read(s, addr1);
 430         s->poll = 0;
 431     } else {
 432         if (addr == 0) {
 433             if (s->read_reg_select)
 434                 ret = s->isr;
 435             else
 436                 ret = s->irr;
 437         } else {
 438             ret = s->imr;
 439         }
 440     }
 441 #ifdef DEBUG_PIC
 442     printf("pic_read: addr=0x%02x val=0x%02x\n", addr1, ret);
 443 #endif
 444     return ret;
 445 }
 446
 447 /* memory mapped interrupt status */
 448 /* XXX: may be the same than pic_read_irq() */
 449 uint32_t pic_intack_read(PicState2 *s)
 450 {
 451     int ret;
 452
 453     ret = pic_poll_read(&s->pics[0], 0x00);
 454     if (ret == 2)
 455         ret = pic_poll_read(&s->pics[1], 0x80) + 8;
 456     /* Prepare for ISR read */
 457     s->pics[0].read_reg_select = 1;
 458
 459     return ret;
 460 }
 461
 462 static void elcr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 463 {
 464     PicState *s = opaque;
 465     s->elcr = val & s->elcr_mask;
 466 }
 467
 468 static uint32_t elcr_ioport_read(void *opaque, uint32_t addr1)
 469 {
 470     PicState *s = opaque;
 471     return s->elcr;
 472 }
 473
 474 static void kvm_kernel_pic_save_to_user(PicState *s)
 475 {
 476 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
 477     struct kvm_irqchip chip;
 478     struct kvm_pic_state *kpic;
 479
 480     chip.chip_id = (&s->pics_state->pics[0] == s) ?
 481                    KVM_IRQCHIP_PIC_MASTER :
 482                    KVM_IRQCHIP_PIC_SLAVE;
 483     kvm_get_irqchip(kvm_context, &chip);
 484     kpic = &chip.chip.pic;
 485
 486     s->last_irr = kpic->last_irr;
 487     s->irr = kpic->irr;
 488     s->imr = kpic->imr;
 489     s->isr = kpic->isr;
 490     s->priority_add = kpic->priority_add;
 491     s->irq_base = kpic->irq_base;
 492     s->read_reg_select = kpic->read_reg_select;
 493     s->poll = kpic->poll;
 494     s->special_mask = kpic->special_mask;
 495     s->init_state = kpic->init_state;
 496     s->auto_eoi = kpic->auto_eoi;
 497     s->rotate_on_auto_eoi = kpic->rotate_on_auto_eoi;
 498     s->special_fully_nested_mode = kpic->special_fully_nested_mode;
 499     s->init4 = kpic->init4;
 500     s->elcr = kpic->elcr;
 501     s->elcr_mask = kpic->elcr_mask;
 502 #endif
 503 }
 504
 505 static void kvm_kernel_pic_load_from_user(PicState *s)
 506 {
 507 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
 508     struct kvm_irqchip chip;
 509     struct kvm_pic_state *kpic;
 510
 511     chip.chip_id = (&s->pics_state->pics[0] == s) ?
 512                    KVM_IRQCHIP_PIC_MASTER :
 513                    KVM_IRQCHIP_PIC_SLAVE;
 514     kpic = &chip.chip.pic;
 515
 516     kpic->last_irr = s->last_irr;
 517     kpic->irr = s->irr;
 518     kpic->imr = s->imr;
 519     kpic->isr = s->isr;
 520     kpic->priority_add = s->priority_add;
 521     kpic->irq_base = s->irq_base;
 522     kpic->read_reg_select = s->read_reg_select;
 523     kpic->poll = s->poll;
 524     kpic->special_mask = s->special_mask;
 525     kpic->init_state = s->init_state;
 526     kpic->auto_eoi = s->auto_eoi;
 527     kpic->rotate_on_auto_eoi = s->rotate_on_auto_eoi;
 528     kpic->special_fully_nested_mode = s->special_fully_nested_mode;
 529     kpic->init4 = s->init4;
 530     kpic->elcr = s->elcr;
 531     kpic->elcr_mask = s->elcr_mask;
 532
 533     kvm_set_irqchip(kvm_context, &chip);
 534 #endif
 535 }
 536
 537 static void pic_save(QEMUFile *f, void *opaque)
 538 {
 539     PicState *s = opaque;
 540
 541     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 542         kvm_kernel_pic_save_to_user(s);
 543     }
 544
 545     qemu_put_8s(f, &s->last_irr);
 546     qemu_put_8s(f, &s->irr);
 547     qemu_put_8s(f, &s->imr);
 548     qemu_put_8s(f, &s->isr);
 549     qemu_put_8s(f, &s->priority_add);
 550     qemu_put_8s(f, &s->irq_base);
 551     qemu_put_8s(f, &s->read_reg_select);
 552     qemu_put_8s(f, &s->poll);
 553     qemu_put_8s(f, &s->special_mask);
 554     qemu_put_8s(f, &s->init_state);
 555     qemu_put_8s(f, &s->auto_eoi);
 556     qemu_put_8s(f, &s->rotate_on_auto_eoi);
 557     qemu_put_8s(f, &s->special_fully_nested_mode);
 558     qemu_put_8s(f, &s->init4);
 559     qemu_put_8s(f, &s->single_mode);
 560     qemu_put_8s(f, &s->elcr);
 561 }
 562
 563 static int pic_load(QEMUFile *f, void *opaque, int version_id)
 564 {
 565     PicState *s = opaque;
 566
 567     if (version_id != 1)
 568         return -EINVAL;
 569
 570     qemu_get_8s(f, &s->last_irr);
 571     qemu_get_8s(f, &s->irr);
 572     qemu_get_8s(f, &s->imr);
 573     qemu_get_8s(f, &s->isr);
 574     qemu_get_8s(f, &s->priority_add);
 575     qemu_get_8s(f, &s->irq_base);
 576     qemu_get_8s(f, &s->read_reg_select);
 577     qemu_get_8s(f, &s->poll);
 578     qemu_get_8s(f, &s->special_mask);
 579     qemu_get_8s(f, &s->init_state);
 580     qemu_get_8s(f, &s->auto_eoi);
 581     qemu_get_8s(f, &s->rotate_on_auto_eoi);
 582     qemu_get_8s(f, &s->special_fully_nested_mode);
 583     qemu_get_8s(f, &s->init4);
 584     qemu_get_8s(f, &s->single_mode);
 585     qemu_get_8s(f, &s->elcr);
 586
 587     if (kvm_enabled() && qemu_kvm_irqchip_in_kernel()) {
 588         kvm_kernel_pic_load_from_user(s);
 589     }
 590
 591     return 0;
 592 }
 593
 594 /* XXX: add generic master/slave system */
 595 static void pic_init1(int io_addr, int elcr_addr, PicState *s)
 596 {
 597     register_ioport_write(io_addr, 2, 1, pic_ioport_write, s);
 598     register_ioport_read(io_addr, 2, 1, pic_ioport_read, s);
 599     if (elcr_addr >= 0) {
 600         register_ioport_write(elcr_addr, 1, 1, elcr_ioport_write, s);
 601         register_ioport_read(elcr_addr, 1, 1, elcr_ioport_read, s);
 602     }
 603     register_savevm("i8259", io_addr, 1, pic_save, pic_load, s);
 604     qemu_register_reset(pic_reset, s);
 605 }
 606
 607 void pic_info(void)
 608 {
 609     int i;
 610     PicState *s;
 611
 612     if (!isa_pic)
 613         return;
 614
 615     for(i=0;i<2;i++) {
 616         s = &isa_pic->pics[i];
 617         term_printf("pic%d: irr=%02x imr=%02x isr=%02x hprio=%d irq_base=%02x rr_sel=%d elcr=%02x fnm=%d\n",
 618                     i, s->irr, s->imr, s->isr, s->priority_add,
 619                     s->irq_base, s->read_reg_select, s->elcr,
 620                     s->special_fully_nested_mode);
 621     }
 622 }
 623
 624 void irq_info(void)
 625 {
 626 #ifndef DEBUG_IRQ_COUNT
 627     term_printf("irq statistic code not compiled.\n");
 628 #else
 629     int i;
 630     int64_t count;
 631
 632     term_printf("IRQ statistics:\n");
 633     for (i = 0; i < 16; i++) {
 634         count = irq_count[i];
 635         if (count > 0)
 636             term_printf("%2d: %" PRId64 "\n", i, count);
 637     }
 638 #endif
 639 }
 640
 641 qemu_irq *i8259_init(qemu_irq parent_irq)
 642 {
 643     PicState2 *s;
 644
 645     s = qemu_mallocz(sizeof(PicState2));
 646     if (!s)
 647         return NULL;
 648     pic_init1(0x20, 0x4d0, &s->pics[0]);
 649     pic_init1(0xa0, 0x4d1, &s->pics[1]);
 650     s->pics[0].elcr_mask = 0xf8;
 651     s->pics[1].elcr_mask = 0xde;
 652     s->parent_irq = parent_irq;
 653     s->pics[0].pics_state = s;
 654     s->pics[1].pics_state = s;
 655     isa_pic = s;
 656     return qemu_allocate_irqs(i8259_set_irq, s, 16);
 657 }
 658
 659 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
 660                           void *alt_irq_opaque)
 661 {
 662     s->alt_irq_func = alt_irq_func;
 663     s->alt_irq_opaque = alt_irq_opaque;
 664 }