hw/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "pc.h"
  27 #include "nvram.h"
  28 #include "fdc.h"
  29 #include "net.h"
  30 #include "qemu-timer.h"
  31 #include "sysemu.h"
  32 #include "boards.h"
  33 #include "firmware_abi.h"
  34 #include "fw_cfg.h"
  35
  36 //#define DEBUG_IRQ
  37
  38 #ifdef DEBUG_IRQ
  39 #define DPRINTF(fmt, args...)                           \
  40     do { printf("CPUIRQ: " fmt , ##args); } while (0)
  41 #else
  42 #define DPRINTF(fmt, args...)
  43 #endif
  44
  45 #define KERNEL_LOAD_ADDR     0x00404000
  46 #define CMDLINE_ADDR         0x003ff000
  47 #define INITRD_LOAD_ADDR     0x00300000
  48 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  49 #define PROM_ADDR            0x1fff0000000ULL
  50 #define PROM_VADDR           0x000ffd00000ULL
  51 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  52 #define APB_MEM_BASE         0x1ff00000000ULL
  53 #define VGA_BASE             (APB_MEM_BASE + 0x400000ULL)
  54 #define PROM_FILENAME        "openbios-sparc64"
  55 #define NVRAM_SIZE           0x2000
  56 #define MAX_IDE_BUS          2
  57 #define BIOS_CFG_IOPORT      0x510
  58
  59 #define MAX_PILS 16
  60
  61 struct hwdef {
  62     const char * const default_cpu_model;
  63     uint16_t machine_id;
  64 };
  65
  66 int DMA_get_channel_mode (int nchan)
  67 {
  68     return 0;
  69 }
  70 int DMA_read_memory (int nchan, void *buf, int pos, int size)
  71 {
  72     return 0;
  73 }
  74 int DMA_write_memory (int nchan, void *buf, int pos, int size)
  75 {
  76     return 0;
  77 }
  78 void DMA_hold_DREQ (int nchan) {}
  79 void DMA_release_DREQ (int nchan) {}
  80 void DMA_schedule(int nchan) {}
  81 void DMA_run (void) {}
  82 void DMA_init (int high_page_enable) {}
  83 void DMA_register_channel (int nchan,
  84                            DMA_transfer_handler transfer_handler,
  85                            void *opaque)
  86 {
  87 }
  88
  89 static int nvram_boot_set(void *opaque, const char *boot_device)
  90 {
  91     unsigned int i;
  92     uint8_t image[sizeof(ohwcfg_v3_t)];
  93     ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
  94     m48t59_t *nvram = (m48t59_t *)opaque;
  95
  96     for (i = 0; i < sizeof(image); i++)
  97         image[i] = m48t59_read(nvram, i) & 0xff;
  98
  99     pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
 100             boot_device);
 101     header->nboot_devices = strlen(boot_device) & 0xff;
 102     header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
 103
 104     for (i = 0; i < sizeof(image); i++)
 105         m48t59_write(nvram, i, image[i]);
 106
 107     return 0;
 108 }
 109
 110 extern int nographic;
 111
 112 static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
 113                                    const char *arch,
 114                                    ram_addr_t RAM_size,
 115                                    const char *boot_devices,
 116                                    uint32_t kernel_image, uint32_t kernel_size,
 117                                    const char *cmdline,
 118                                    uint32_t initrd_image, uint32_t initrd_size,
 119                                    uint32_t NVRAM_image,
 120                                    int width, int height, int depth,
 121                                    const uint8_t *macaddr)
 122 {
 123     unsigned int i;
 124     uint32_t start, end;
 125     uint8_t image[0x1ff0];
 126     ohwcfg_v3_t *header = (ohwcfg_v3_t *)&image;
 127     struct sparc_arch_cfg *sparc_header;
 128     struct OpenBIOS_nvpart_v1 *part_header;
 129
 130     memset(image, '\0', sizeof(image));
 131
 132     // Try to match PPC NVRAM
 133     pstrcpy((char *)header->struct_ident, sizeof(header->struct_ident),
 134             "QEMU_BIOS");
 135     header->struct_version = cpu_to_be32(3); /* structure v3 */
 136
 137     header->nvram_size = cpu_to_be16(NVRAM_size);
 138     header->nvram_arch_ptr = cpu_to_be16(sizeof(ohwcfg_v3_t));
 139     header->nvram_arch_size = cpu_to_be16(sizeof(struct sparc_arch_cfg));
 140     pstrcpy((char *)header->arch, sizeof(header->arch), arch);
 141     header->nb_cpus = smp_cpus & 0xff;
 142     header->RAM0_base = 0;
 143     header->RAM0_size = cpu_to_be64((uint64_t)RAM_size);
 144     pstrcpy((char *)header->boot_devices, sizeof(header->boot_devices),
 145             boot_devices);
 146     header->nboot_devices = strlen(boot_devices) & 0xff;
 147     header->kernel_image = cpu_to_be64((uint64_t)kernel_image);
 148     header->kernel_size = cpu_to_be64((uint64_t)kernel_size);
 149     if (cmdline) {
 150         pstrcpy_targphys(CMDLINE_ADDR, TARGET_PAGE_SIZE, cmdline);
 151         header->cmdline = cpu_to_be64((uint64_t)CMDLINE_ADDR);
 152         header->cmdline_size = cpu_to_be64((uint64_t)strlen(cmdline));
 153     }
 154     header->initrd_image = cpu_to_be64((uint64_t)initrd_image);
 155     header->initrd_size = cpu_to_be64((uint64_t)initrd_size);
 156     header->NVRAM_image = cpu_to_be64((uint64_t)NVRAM_image);
 157
 158     header->width = cpu_to_be16(width);
 159     header->height = cpu_to_be16(height);
 160     header->depth = cpu_to_be16(depth);
 161     if (nographic)
 162         header->graphic_flags = cpu_to_be16(OHW_GF_NOGRAPHICS);
 163
 164     header->crc = cpu_to_be16(OHW_compute_crc(header, 0x00, 0xF8));
 165
 166     // Architecture specific header
 167     start = sizeof(ohwcfg_v3_t);
 168     sparc_header = (struct sparc_arch_cfg *)&image[start];
 169     sparc_header->valid = 0;
 170     start += sizeof(struct sparc_arch_cfg);
 171
 172     // OpenBIOS nvram variables
 173     // Variable partition
 174     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 175     part_header->signature = OPENBIOS_PART_SYSTEM;
 176     pstrcpy(part_header->name, sizeof(part_header->name), "system");
 177
 178     end = start + sizeof(struct OpenBIOS_nvpart_v1);
 179     for (i = 0; i < nb_prom_envs; i++)
 180         end = OpenBIOS_set_var(image, end, prom_envs[i]);
 181
 182     // End marker
 183     image[end++] = '\0';
 184
 185     end = start + ((end - start + 15) & ~15);
 186     OpenBIOS_finish_partition(part_header, end - start);
 187
 188     // free partition
 189     start = end;
 190     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 191     part_header->signature = OPENBIOS_PART_FREE;
 192     pstrcpy(part_header->name, sizeof(part_header->name), "free");
 193
 194     end = 0x1fd0;
 195     OpenBIOS_finish_partition(part_header, end - start);
 196
 197     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 198
 199     for (i = 0; i < sizeof(image); i++)
 200         m48t59_write(nvram, i, image[i]);
 201
 202     qemu_register_boot_set(nvram_boot_set, nvram);
 203
 204     return 0;
 205 }
 206
 207 void pic_info(void)
 208 {
 209 }
 210
 211 void irq_info(void)
 212 {
 213 }
 214
 215 void cpu_check_irqs(CPUState *env)
 216 {
 217     uint32_t pil = env->pil_in | (env->softint & ~SOFTINT_TIMER) |
 218         ((env->softint & SOFTINT_TIMER) << 14);
 219
 220     if (pil && (env->interrupt_index == 0 ||
 221                 (env->interrupt_index & ~15) == TT_EXTINT)) {
 222         unsigned int i;
 223
 224         for (i = 15; i > 0; i--) {
 225             if (pil & (1 << i)) {
 226                 int old_interrupt = env->interrupt_index;
 227
 228                 env->interrupt_index = TT_EXTINT | i;
 229                 if (old_interrupt != env->interrupt_index) {
 230                     DPRINTF("Set CPU IRQ %d\n", i);
 231                     cpu_interrupt(env, CPU_INTERRUPT_HARD);
 232                 }
 233                 break;
 234             }
 235         }
 236     } else if (!pil && (env->interrupt_index & ~15) == TT_EXTINT) {
 237         DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
 238         env->interrupt_index = 0;
 239         cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 240     }
 241 }
 242
 243 static void cpu_set_irq(void *opaque, int irq, int level)
 244 {
 245     CPUState *env = opaque;
 246
 247     if (level) {
 248         DPRINTF("Raise CPU IRQ %d\n", irq);
 249         env->halted = 0;
 250         env->pil_in |= 1 << irq;
 251         cpu_check_irqs(env);
 252     } else {
 253         DPRINTF("Lower CPU IRQ %d\n", irq);
 254         env->pil_in &= ~(1 << irq);
 255         cpu_check_irqs(env);
 256     }
 257 }
 258
 259 void qemu_system_powerdown(void)
 260 {
 261 }
 262
 263 static void main_cpu_reset(void *opaque)
 264 {
 265     CPUState *env = opaque;
 266
 267     cpu_reset(env);
 268     ptimer_set_limit(env->tick, 0x7fffffffffffffffULL, 1);
 269     ptimer_run(env->tick, 0);
 270     ptimer_set_limit(env->stick, 0x7fffffffffffffffULL, 1);
 271     ptimer_run(env->stick, 0);
 272     ptimer_set_limit(env->hstick, 0x7fffffffffffffffULL, 1);
 273     ptimer_run(env->hstick, 0);
 274 }
 275
 276 static void tick_irq(void *opaque)
 277 {
 278     CPUState *env = opaque;
 279
 280     env->softint |= SOFTINT_TIMER;
 281     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 282 }
 283
 284 static void stick_irq(void *opaque)
 285 {
 286     CPUState *env = opaque;
 287
 288     env->softint |= SOFTINT_TIMER;
 289     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 290 }
 291
 292 static void hstick_irq(void *opaque)
 293 {
 294     CPUState *env = opaque;
 295
 296     env->softint |= SOFTINT_TIMER;
 297     cpu_interrupt(env, CPU_INTERRUPT_TIMER);
 298 }
 299
 300 static const int ide_iobase[2] = { 0x1f0, 0x170 };
 301 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
 302 static const int ide_irq[2] = { 14, 15 };
 303
 304 static const int serial_io[MAX_SERIAL_PORTS] = { 0x3f8, 0x2f8, 0x3e8, 0x2e8 };
 305 static const int serial_irq[MAX_SERIAL_PORTS] = { 4, 3, 4, 3 };
 306
 307 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 308 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 309
 310 static fdctrl_t *floppy_controller;
 311
 312 static void sun4uv_init(ram_addr_t RAM_size, int vga_ram_size,
 313                         const char *boot_devices, DisplayState *ds,
 314                         const char *kernel_filename, const char *kernel_cmdline,
 315                         const char *initrd_filename, const char *cpu_model,
 316                         const struct hwdef *hwdef)
 317 {
 318     CPUState *env;
 319     char buf[1024];
 320     m48t59_t *nvram;
 321     int ret, linux_boot;
 322     unsigned int i;
 323     long prom_offset, initrd_size, kernel_size;
 324     PCIBus *pci_bus;
 325     QEMUBH *bh;
 326     qemu_irq *irq;
 327     int drive_index;
 328     BlockDriverState *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 329     BlockDriverState *fd[MAX_FD];
 330     void *fw_cfg;
 331
 332     linux_boot = (kernel_filename != NULL);
 333
 334     /* init CPUs */
 335     if (!cpu_model)
 336         cpu_model = hwdef->default_cpu_model;
 337
 338     env = cpu_init(cpu_model);
 339     if (!env) {
 340         fprintf(stderr, "Unable to find Sparc CPU definition\n");
 341         exit(1);
 342     }
 343     bh = qemu_bh_new(tick_irq, env);
 344     env->tick = ptimer_init(bh);
 345     ptimer_set_period(env->tick, 1ULL);
 346
 347     bh = qemu_bh_new(stick_irq, env);
 348     env->stick = ptimer_init(bh);
 349     ptimer_set_period(env->stick, 1ULL);
 350
 351     bh = qemu_bh_new(hstick_irq, env);
 352     env->hstick = ptimer_init(bh);
 353     ptimer_set_period(env->hstick, 1ULL);
 354     qemu_register_reset(main_cpu_reset, env);
 355     main_cpu_reset(env);
 356
 357     /* allocate RAM */
 358     cpu_register_physical_memory(0, RAM_size, 0);
 359
 360     prom_offset = RAM_size + vga_ram_size;
 361     cpu_register_physical_memory(PROM_ADDR,
 362                                  (PROM_SIZE_MAX + TARGET_PAGE_SIZE) &
 363                                  TARGET_PAGE_MASK,
 364                                  prom_offset | IO_MEM_ROM);
 365
 366     if (bios_name == NULL)
 367         bios_name = PROM_FILENAME;
 368     snprintf(buf, sizeof(buf), "%s/%s", bios_dir, bios_name);
 369     ret = load_elf(buf, PROM_ADDR - PROM_VADDR, NULL, NULL, NULL);
 370     if (ret < 0) {
 371         fprintf(stderr, "qemu: could not load prom '%s'\n",
 372                 buf);
 373         exit(1);
 374     }
 375
 376     kernel_size = 0;
 377     initrd_size = 0;
 378     if (linux_boot) {
 379         /* XXX: put correct offset */
 380         kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL);
 381         if (kernel_size < 0)
 382             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 383                                     ram_size - KERNEL_LOAD_ADDR);
 384         if (kernel_size < 0)
 385             kernel_size = load_image_targphys(kernel_filename,
 386                                               KERNEL_LOAD_ADDR,
 387                                               ram_size - KERNEL_LOAD_ADDR);
 388         if (kernel_size < 0) {
 389             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 390                     kernel_filename);
 391             exit(1);
 392         }
 393
 394         /* load initrd */
 395         if (initrd_filename) {
 396             initrd_size = load_image_targphys(initrd_filename,
 397                                               INITRD_LOAD_ADDR,
 398                                               ram_size - INITRD_LOAD_ADDR);
 399             if (initrd_size < 0) {
 400                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 401                         initrd_filename);
 402                 exit(1);
 403             }
 404         }
 405         if (initrd_size > 0) {
 406             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 407                 if (ldl_phys(KERNEL_LOAD_ADDR + i) == 0x48647253) { // HdrS
 408                     stl_phys(KERNEL_LOAD_ADDR + i + 16, INITRD_LOAD_ADDR);
 409                     stl_phys(KERNEL_LOAD_ADDR + i + 20, initrd_size);
 410                     break;
 411                 }
 412             }
 413         }
 414     }
 415     pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, NULL);
 416     isa_mem_base = VGA_BASE;
 417     pci_cirrus_vga_init(pci_bus, ds, phys_ram_base + RAM_size, RAM_size,
 418                         vga_ram_size);
 419
 420     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
 421         if (serial_hds[i]) {
 422             serial_init(serial_io[i], NULL/*serial_irq[i]*/, 115200,
 423                         serial_hds[i]);
 424         }
 425     }
 426
 427     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 428         if (parallel_hds[i]) {
 429             parallel_init(parallel_io[i], NULL/*parallel_irq[i]*/,
 430                           parallel_hds[i]);
 431         }
 432     }
 433
 434     for(i = 0; i < nb_nics; i++) {
 435         if (!nd_table[i].model)
 436             nd_table[i].model = "ne2k_pci";
 437         if (!pci_nic_init(pci_bus, &nd_table[i], -1))
 438             exit(1);
 439     }
 440
 441     irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
 442     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 443         fprintf(stderr, "qemu: too many IDE bus\n");
 444         exit(1);
 445     }
 446     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 447         drive_index = drive_get_index(IF_IDE, i / MAX_IDE_DEVS,
 448                                       i % MAX_IDE_DEVS);
 449        if (drive_index != -1)
 450            hd[i] = drives_table[drive_index].bdrv;
 451        else
 452            hd[i] = NULL;
 453     }
 454
 455     // XXX pci_cmd646_ide_init(pci_bus, hd, 1);
 456     pci_piix3_ide_init(pci_bus, hd, -1, irq);
 457     /* FIXME: wire up interrupts.  */
 458     i8042_init(NULL/*1*/, NULL/*12*/, 0x60);
 459     for(i = 0; i < MAX_FD; i++) {
 460         drive_index = drive_get_index(IF_FLOPPY, 0, i);
 461        if (drive_index != -1)
 462            fd[i] = drives_table[drive_index].bdrv;
 463        else
 464            fd[i] = NULL;
 465     }
 466     floppy_controller = fdctrl_init(NULL/*6*/, 2, 0, 0x3f0, fd);
 467     nvram = m48t59_init(NULL/*8*/, 0, 0x0074, NVRAM_SIZE, 59);
 468     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
 469                            KERNEL_LOAD_ADDR, kernel_size,
 470                            kernel_cmdline,
 471                            INITRD_LOAD_ADDR, initrd_size,
 472                            /* XXX: need an option to load a NVRAM image */
 473                            0,
 474                            graphic_width, graphic_height, graphic_depth,
 475                            (uint8_t *)&nd_table[0].macaddr);
 476
 477     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 478     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 479     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 480     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 481 }
 482
 483 enum {
 484     sun4u_id = 0,
 485     sun4v_id = 64,
 486 };
 487
 488 static const struct hwdef hwdefs[] = {
 489     /* Sun4u generic PC-like machine */
 490     {
 491         .default_cpu_model = "TI UltraSparc II",
 492         .machine_id = sun4u_id,
 493     },
 494     /* Sun4v generic PC-like machine */
 495     {
 496         .default_cpu_model = "Sun UltraSparc T1",
 497         .machine_id = sun4v_id,
 498     },
 499 };
 500
 501 /* Sun4u hardware initialisation */
 502 static void sun4u_init(ram_addr_t RAM_size, int vga_ram_size,
 503                        const char *boot_devices, DisplayState *ds,
 504                        const char *kernel_filename, const char *kernel_cmdline,
 505                        const char *initrd_filename, const char *cpu_model)
 506 {
 507     sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
 508                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
 509 }
 510
 511 /* Sun4v hardware initialisation */
 512 static void sun4v_init(ram_addr_t RAM_size, int vga_ram_size,
 513                        const char *boot_devices, DisplayState *ds,
 514                        const char *kernel_filename, const char *kernel_cmdline,
 515                        const char *initrd_filename, const char *cpu_model)
 516 {
 517     sun4uv_init(RAM_size, vga_ram_size, boot_devices, ds, kernel_filename,
 518                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
 519 }
 520
 521 QEMUMachine sun4u_machine = {
 522     .name = "sun4u",
 523     .desc = "Sun4u platform",
 524     .init = sun4u_init,
 525     .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,
 526     .nodisk_ok = 1,
 527 };
 528
 529 QEMUMachine sun4v_machine = {
 530     .name = "sun4v",
 531     .desc = "Sun4v platform",
 532     .init = sun4v_init,
 533     .ram_require = PROM_SIZE_MAX + VGA_RAM_SIZE,
 534     .nodisk_ok = 1,
 535 };