hw/pci.h

   1 #ifndef QEMU_PCI_H
   2 #define QEMU_PCI_H
   3
   4 /* PCI includes legacy ISA access.  */
   5 #include "isa.h"
   6
   7 /* imported from <linux/pci.h> */
   8 #define PCI_SLOT(devfn)         (((devfn) >> 3) & 0x1f)
   9 #define PCI_FUNC(devfn)         ((devfn) & 0x07)
  10
  11 /* PCI bus */
  12 extern target_phys_addr_t pci_mem_base;
  13
  14 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
  15                                 uint32_t address, uint32_t data, int len);
  16 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
  17                                    uint32_t address, int len);
  18 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
  19                                 uint32_t addr, uint32_t size, int type);
  20 typedef int PCIUnregisterFunc(PCIDevice *pci_dev);
  21
  22 #define PCI_ADDRESS_SPACE_MEM           0x00
  23 #define PCI_ADDRESS_SPACE_IO            0x01
  24 #define PCI_ADDRESS_SPACE_MEM_PREFETCH  0x08
  25
  26 typedef struct PCIIORegion {
  27     uint32_t addr; /* current PCI mapping address. -1 means not mapped */
  28     uint32_t size;
  29     uint8_t type;
  30     PCIMapIORegionFunc *map_func;
  31 } PCIIORegion;
  32
  33 #define PCI_ROM_SLOT 6
  34 #define PCI_NUM_REGIONS 7
  35
  36 #define PCI_DEVICES_MAX 64
  37
  38 #define PCI_VENDOR_ID           0x00    /* 16 bits */
  39 #define PCI_DEVICE_ID           0x02    /* 16 bits */
  40 #define PCI_COMMAND             0x04    /* 16 bits */
  41 #define  PCI_COMMAND_IO         0x1     /* Enable response in I/O space */
  42 #define  PCI_COMMAND_MEMORY     0x2     /* Enable response in Memory space */
  43 #define PCI_CLASS_DEVICE        0x0a    /* Device class */
  44 #define PCI_INTERRUPT_LINE      0x3c    /* 8 bits */
  45 #define PCI_INTERRUPT_PIN       0x3d    /* 8 bits */
  46 #define PCI_MIN_GNT             0x3e    /* 8 bits */
  47 #define PCI_MAX_LAT             0x3f    /* 8 bits */
  48
  49 struct PCIDevice {
  50     /* PCI config space */
  51     uint8_t config[256];
  52
  53     /* the following fields are read only */
  54     PCIBus *bus;
  55     int devfn;
  56     char name[64];
  57     PCIIORegion io_regions[PCI_NUM_REGIONS];
  58
  59     /* do not access the following fields */
  60     PCIConfigReadFunc *config_read;
  61     PCIConfigWriteFunc *config_write;
  62     PCIUnregisterFunc *unregister;
  63     /* ??? This is a PC-specific hack, and should be removed.  */
  64     int irq_index;
  65
  66     /* IRQ objects for the INTA-INTD pins.  */
  67     qemu_irq *irq;
  68
  69     /* Current IRQ levels.  Used internally by the generic PCI code.  */
  70     int irq_state[4];
  71 };
  72
  73 PCIDevice *pci_register_device(PCIBus *bus, const char *name,
  74                                int instance_size, int devfn,
  75                                PCIConfigReadFunc *config_read,
  76                                PCIConfigWriteFunc *config_write);
  77
  78 int pci_unregister_device(PCIDevice *pci_dev);
  79
  80 void pci_register_io_region(PCIDevice *pci_dev, int region_num,
  81                             uint32_t size, int type,
  82                             PCIMapIORegionFunc *map_func);
  83
  84 uint32_t pci_default_read_config(PCIDevice *d,
  85                                  uint32_t address, int len);
  86 void pci_default_write_config(PCIDevice *d,
  87                               uint32_t address, uint32_t val, int len);
  88 void pci_device_save(PCIDevice *s, QEMUFile *f);
  89 int pci_device_load(PCIDevice *s, QEMUFile *f);
  90
  91 typedef void (*pci_set_irq_fn)(qemu_irq *pic, int irq_num, int level);
  92 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
  93 PCIBus *pci_register_bus(pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
  94                          qemu_irq *pic, int devfn_min, int nirq);
  95
  96 PCIDevice *pci_nic_init(PCIBus *bus, NICInfo *nd, int devfn);
  97 void pci_data_write(void *opaque, uint32_t addr, uint32_t val, int len);
  98 uint32_t pci_data_read(void *opaque, uint32_t addr, int len);
  99 int pci_bus_num(PCIBus *s);
 100 void pci_for_each_device(int bus_num, void (*fn)(PCIDevice *d));
 101 PCIBus *pci_find_bus(int bus_num);
 102 PCIDevice *pci_find_device(int bus_num, int slot);
 103
 104 void pci_info(void);
 105 PCIBus *pci_bridge_init(PCIBus *bus, int devfn, uint32_t id,
 106                         pci_map_irq_fn map_irq, const char *name);
 107
 108 /* lsi53c895a.c */
 109 #define LSI_MAX_DEVS 7
 110 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id);
 111 void *lsi_scsi_init(PCIBus *bus, int devfn);
 112
 113 /* vmware_vga.c */
 114 void pci_vmsvga_init(PCIBus *bus, DisplayState *ds, uint8_t *vga_ram_base,
 115                      unsigned long vga_ram_offset, int vga_ram_size);
 116
 117 /* usb-uhci.c */
 118 void usb_uhci_piix3_init(PCIBus *bus, int devfn);
 119 void usb_uhci_piix4_init(PCIBus *bus, int devfn);
 120
 121 /* usb-ohci.c */
 122 void usb_ohci_init_pci(struct PCIBus *bus, int num_ports, int devfn);
 123
 124 /* eepro100.c */
 125
 126 PCIDevice *pci_i82551_init(PCIBus *bus, NICInfo *nd, int devfn);
 127 PCIDevice *pci_i82557b_init(PCIBus *bus, NICInfo *nd, int devfn);
 128 PCIDevice *pci_i82559er_init(PCIBus *bus, NICInfo *nd, int devfn);
 129
 130 /* ne2000.c */
 131
 132 PCIDevice *pci_ne2000_init(PCIBus *bus, NICInfo *nd, int devfn);
 133
 134 /* rtl8139.c */
 135
 136 PCIDevice *pci_rtl8139_init(PCIBus *bus, NICInfo *nd, int devfn);
 137
 138 /* e1000.c */
 139 PCIDevice *pci_e1000_init(PCIBus *bus, NICInfo *nd, int devfn);
 140
 141 /* pcnet.c */
 142 PCIDevice *pci_pcnet_init(PCIBus *bus, NICInfo *nd, int devfn);
 143
 144 /* prep_pci.c */
 145 PCIBus *pci_prep_init(qemu_irq *pic);
 146
 147 /* apb_pci.c */
 148 PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base,
 149                      qemu_irq *pic);
 150
 151 #endif