hw/lsi53c895a.c

   1 /*
   2  * QEMU LSI53C895A SCSI Host Bus Adapter emulation
   3  *
   4  * Copyright (c) 2006 CodeSourcery.
   5  * Written by Paul Brook
   6  *
   7  * This code is licenced under the LGPL.
   8  */
   9
  10 /* ??? Need to check if the {read,write}[wl] routines work properly on
  11    big-endian targets.  */
  12
  13 #include "hw.h"
  14 #include "pci.h"
  15 #include "scsi-disk.h"
  16 #include "block_int.h"
  17
  18 //#define DEBUG_LSI
  19 //#define DEBUG_LSI_REG
  20
  21 #ifdef DEBUG_LSI
  22 #define DPRINTF(fmt, args...) \
  23 do { printf("lsi_scsi: " fmt , ##args); } while (0)
  24 #define BADF(fmt, args...) \
  25 do { fprintf(stderr, "lsi_scsi: error: " fmt , ##args); exit(1);} while (0)
  26 #else
  27 #define DPRINTF(fmt, args...) do {} while(0)
  28 #define BADF(fmt, args...) \
  29 do { fprintf(stderr, "lsi_scsi: error: " fmt , ##args);} while (0)
  30 #endif
  31
  32 #define LSI_SCNTL0_TRG    0x01
  33 #define LSI_SCNTL0_AAP    0x02
  34 #define LSI_SCNTL0_EPC    0x08
  35 #define LSI_SCNTL0_WATN   0x10
  36 #define LSI_SCNTL0_START  0x20
  37
  38 #define LSI_SCNTL1_SST    0x01
  39 #define LSI_SCNTL1_IARB   0x02
  40 #define LSI_SCNTL1_AESP   0x04
  41 #define LSI_SCNTL1_RST    0x08
  42 #define LSI_SCNTL1_CON    0x10
  43 #define LSI_SCNTL1_DHP    0x20
  44 #define LSI_SCNTL1_ADB    0x40
  45 #define LSI_SCNTL1_EXC    0x80
  46
  47 #define LSI_SCNTL2_WSR    0x01
  48 #define LSI_SCNTL2_VUE0   0x02
  49 #define LSI_SCNTL2_VUE1   0x04
  50 #define LSI_SCNTL2_WSS    0x08
  51 #define LSI_SCNTL2_SLPHBEN 0x10
  52 #define LSI_SCNTL2_SLPMD  0x20
  53 #define LSI_SCNTL2_CHM    0x40
  54 #define LSI_SCNTL2_SDU    0x80
  55
  56 #define LSI_ISTAT0_DIP    0x01
  57 #define LSI_ISTAT0_SIP    0x02
  58 #define LSI_ISTAT0_INTF   0x04
  59 #define LSI_ISTAT0_CON    0x08
  60 #define LSI_ISTAT0_SEM    0x10
  61 #define LSI_ISTAT0_SIGP   0x20
  62 #define LSI_ISTAT0_SRST   0x40
  63 #define LSI_ISTAT0_ABRT   0x80
  64
  65 #define LSI_ISTAT1_SI     0x01
  66 #define LSI_ISTAT1_SRUN   0x02
  67 #define LSI_ISTAT1_FLSH   0x04
  68
  69 #define LSI_SSTAT0_SDP0   0x01
  70 #define LSI_SSTAT0_RST    0x02
  71 #define LSI_SSTAT0_WOA    0x04
  72 #define LSI_SSTAT0_LOA    0x08
  73 #define LSI_SSTAT0_AIP    0x10
  74 #define LSI_SSTAT0_OLF    0x20
  75 #define LSI_SSTAT0_ORF    0x40
  76 #define LSI_SSTAT0_ILF    0x80
  77
  78 #define LSI_SIST0_PAR     0x01
  79 #define LSI_SIST0_RST     0x02
  80 #define LSI_SIST0_UDC     0x04
  81 #define LSI_SIST0_SGE     0x08
  82 #define LSI_SIST0_RSL     0x10
  83 #define LSI_SIST0_SEL     0x20
  84 #define LSI_SIST0_CMP     0x40
  85 #define LSI_SIST0_MA      0x80
  86
  87 #define LSI_SIST1_HTH     0x01
  88 #define LSI_SIST1_GEN     0x02
  89 #define LSI_SIST1_STO     0x04
  90 #define LSI_SIST1_SBMC    0x10
  91
  92 #define LSI_SOCL_IO       0x01
  93 #define LSI_SOCL_CD       0x02
  94 #define LSI_SOCL_MSG      0x04
  95 #define LSI_SOCL_ATN      0x08
  96 #define LSI_SOCL_SEL      0x10
  97 #define LSI_SOCL_BSY      0x20
  98 #define LSI_SOCL_ACK      0x40
  99 #define LSI_SOCL_REQ      0x80
 100
 101 #define LSI_DSTAT_IID     0x01
 102 #define LSI_DSTAT_SIR     0x04
 103 #define LSI_DSTAT_SSI     0x08
 104 #define LSI_DSTAT_ABRT    0x10
 105 #define LSI_DSTAT_BF      0x20
 106 #define LSI_DSTAT_MDPE    0x40
 107 #define LSI_DSTAT_DFE     0x80
 108
 109 #define LSI_DCNTL_COM     0x01
 110 #define LSI_DCNTL_IRQD    0x02
 111 #define LSI_DCNTL_STD     0x04
 112 #define LSI_DCNTL_IRQM    0x08
 113 #define LSI_DCNTL_SSM     0x10
 114 #define LSI_DCNTL_PFEN    0x20
 115 #define LSI_DCNTL_PFF     0x40
 116 #define LSI_DCNTL_CLSE    0x80
 117
 118 #define LSI_DMODE_MAN     0x01
 119 #define LSI_DMODE_BOF     0x02
 120 #define LSI_DMODE_ERMP    0x04
 121 #define LSI_DMODE_ERL     0x08
 122 #define LSI_DMODE_DIOM    0x10
 123 #define LSI_DMODE_SIOM    0x20
 124
 125 #define LSI_CTEST2_DACK   0x01
 126 #define LSI_CTEST2_DREQ   0x02
 127 #define LSI_CTEST2_TEOP   0x04
 128 #define LSI_CTEST2_PCICIE 0x08
 129 #define LSI_CTEST2_CM     0x10
 130 #define LSI_CTEST2_CIO    0x20
 131 #define LSI_CTEST2_SIGP   0x40
 132 #define LSI_CTEST2_DDIR   0x80
 133
 134 #define LSI_CTEST5_BL2    0x04
 135 #define LSI_CTEST5_DDIR   0x08
 136 #define LSI_CTEST5_MASR   0x10
 137 #define LSI_CTEST5_DFSN   0x20
 138 #define LSI_CTEST5_BBCK   0x40
 139 #define LSI_CTEST5_ADCK   0x80
 140
 141 #define LSI_CCNTL0_DILS   0x01
 142 #define LSI_CCNTL0_DISFC  0x10
 143 #define LSI_CCNTL0_ENNDJ  0x20
 144 #define LSI_CCNTL0_PMJCTL 0x40
 145 #define LSI_CCNTL0_ENPMJ  0x80
 146
 147 #define PHASE_DO          0
 148 #define PHASE_DI          1
 149 #define PHASE_CMD         2
 150 #define PHASE_ST          3
 151 #define PHASE_MO          6
 152 #define PHASE_MI          7
 153 #define PHASE_MASK        7
 154
 155 /* Maximum length of MSG IN data.  */
 156 #define LSI_MAX_MSGIN_LEN 8
 157
 158 /* Flag set if this is a tagged command.  */
 159 #define LSI_TAG_VALID     (1 << 16)
 160
 161 typedef struct {
 162     uint32_t tag;
 163     uint32_t pending;
 164     int out;
 165 } lsi_queue;
 166
 167 typedef struct {
 168     PCIDevice pci_dev;
 169     int mmio_io_addr;
 170     int ram_io_addr;
 171     uint32_t script_ram_base;
 172
 173     int carry; /* ??? Should this be an a visible register somewhere?  */
 174     int sense;
 175     /* Action to take at the end of a MSG IN phase.
 176        0 = COMMAND, 1 = disconect, 2 = DATA OUT, 3 = DATA IN.  */
 177     int msg_action;
 178     int msg_len;
 179     uint8_t msg[LSI_MAX_MSGIN_LEN];
 180     /* 0 if SCRIPTS are running or stopped.
 181      * 1 if a Wait Reselect instruction has been issued.
 182      * 2 if processing DMA from lsi_execute_script.
 183      * 3 if a DMA operation is in progress.  */
 184     int waiting;
 185     SCSIDevice *scsi_dev[LSI_MAX_DEVS];
 186     SCSIDevice *current_dev;
 187     int current_lun;
 188     /* The tag is a combination of the device ID and the SCSI tag.  */
 189     uint32_t current_tag;
 190     uint32_t current_dma_len;
 191     int command_complete;
 192     uint8_t *dma_buf;
 193     lsi_queue *queue;
 194     int queue_len;
 195     int active_commands;
 196
 197     uint32_t dsa;
 198     uint32_t temp;
 199     uint32_t dnad;
 200     uint32_t dbc;
 201     uint8_t istat0;
 202     uint8_t istat1;
 203     uint8_t dcmd;
 204     uint8_t dstat;
 205     uint8_t dien;
 206     uint8_t sist0;
 207     uint8_t sist1;
 208     uint8_t sien0;
 209     uint8_t sien1;
 210     uint8_t mbox0;
 211     uint8_t mbox1;
 212     uint8_t dfifo;
 213     uint8_t ctest3;
 214     uint8_t ctest4;
 215     uint8_t ctest5;
 216     uint8_t ccntl0;
 217     uint8_t ccntl1;
 218     uint32_t dsp;
 219     uint32_t dsps;
 220     uint8_t dmode;
 221     uint8_t dcntl;
 222     uint8_t scntl0;
 223     uint8_t scntl1;
 224     uint8_t scntl2;
 225     uint8_t scntl3;
 226     uint8_t sstat0;
 227     uint8_t sstat1;
 228     uint8_t scid;
 229     uint8_t sxfer;
 230     uint8_t socl;
 231     uint8_t sdid;
 232     uint8_t ssid;
 233     uint8_t sfbr;
 234     uint8_t stest1;
 235     uint8_t stest2;
 236     uint8_t stest3;
 237     uint8_t sidl;
 238     uint8_t stime0;
 239     uint8_t respid0;
 240     uint8_t respid1;
 241     uint32_t mmrs;
 242     uint32_t mmws;
 243     uint32_t sfs;
 244     uint32_t drs;
 245     uint32_t sbms;
 246     uint32_t dmbs;
 247     uint32_t dnad64;
 248     uint32_t pmjad1;
 249     uint32_t pmjad2;
 250     uint32_t rbc;
 251     uint32_t ua;
 252     uint32_t ia;
 253     uint32_t sbc;
 254     uint32_t csbc;
 255     uint32_t scratch[18]; /* SCRATCHA-SCRATCHR */
 256
 257     /* Script ram is stored as 32-bit words in host byteorder.  */
 258     uint32_t script_ram[2048];
 259 } LSIState;
 260
 261 static void lsi_soft_reset(LSIState *s)
 262 {
 263     DPRINTF("Reset\n");
 264     s->carry = 0;
 265
 266     s->waiting = 0;
 267     s->dsa = 0;
 268     s->dnad = 0;
 269     s->dbc = 0;
 270     s->temp = 0;
 271     memset(s->scratch, 0, sizeof(s->scratch));
 272     s->istat0 = 0;
 273     s->istat1 = 0;
 274     s->dcmd = 0;
 275     s->dstat = 0;
 276     s->dien = 0;
 277     s->sist0 = 0;
 278     s->sist1 = 0;
 279     s->sien0 = 0;
 280     s->sien1 = 0;
 281     s->mbox0 = 0;
 282     s->mbox1 = 0;
 283     s->dfifo = 0;
 284     s->ctest3 = 0;
 285     s->ctest4 = 0;
 286     s->ctest5 = 0;
 287     s->ccntl0 = 0;
 288     s->ccntl1 = 0;
 289     s->dsp = 0;
 290     s->dsps = 0;
 291     s->dmode = 0;
 292     s->dcntl = 0;
 293     s->scntl0 = 0xc0;
 294     s->scntl1 = 0;
 295     s->scntl2 = 0;
 296     s->scntl3 = 0;
 297     s->sstat0 = 0;
 298     s->sstat1 = 0;
 299     s->scid = 7;
 300     s->sxfer = 0;
 301     s->socl = 0;
 302     s->stest1 = 0;
 303     s->stest2 = 0;
 304     s->stest3 = 0;
 305     s->sidl = 0;
 306     s->stime0 = 0;
 307     s->respid0 = 0x80;
 308     s->respid1 = 0;
 309     s->mmrs = 0;
 310     s->mmws = 0;
 311     s->sfs = 0;
 312     s->drs = 0;
 313     s->sbms = 0;
 314     s->dmbs = 0;
 315     s->dnad64 = 0;
 316     s->pmjad1 = 0;
 317     s->pmjad2 = 0;
 318     s->rbc = 0;
 319     s->ua = 0;
 320     s->ia = 0;
 321     s->sbc = 0;
 322     s->csbc = 0;
 323 }
 324
 325 static uint8_t lsi_reg_readb(LSIState *s, int offset);
 326 static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val);
 327 static void lsi_execute_script(LSIState *s);
 328
 329 static inline uint32_t read_dword(LSIState *s, uint32_t addr)
 330 {
 331     uint32_t buf;
 332
 333     /* Optimize reading from SCRIPTS RAM.  */
 334     if ((addr & 0xffffe000) == s->script_ram_base) {
 335         return s->script_ram[(addr & 0x1fff) >> 2];
 336     }
 337     cpu_physical_memory_read(addr, (uint8_t *)&buf, 4);
 338     return cpu_to_le32(buf);
 339 }
 340
 341 static void lsi_stop_script(LSIState *s)
 342 {
 343     s->istat1 &= ~LSI_ISTAT1_SRUN;
 344 }
 345
 346 static void lsi_update_irq(LSIState *s)
 347 {
 348     int level;
 349     static int last_level;
 350
 351     /* It's unclear whether the DIP/SIP bits should be cleared when the
 352        Interrupt Status Registers are cleared or when istat0 is read.
 353        We currently do the formwer, which seems to work.  */
 354     level = 0;
 355     if (s->dstat) {
 356         if (s->dstat & s->dien)
 357             level = 1;
 358         s->istat0 |= LSI_ISTAT0_DIP;
 359     } else {
 360         s->istat0 &= ~LSI_ISTAT0_DIP;
 361     }
 362
 363     if (s->sist0 || s->sist1) {
 364         if ((s->sist0 & s->sien0) || (s->sist1 & s->sien1))
 365             level = 1;
 366         s->istat0 |= LSI_ISTAT0_SIP;
 367     } else {
 368         s->istat0 &= ~LSI_ISTAT0_SIP;
 369     }
 370     if (s->istat0 & LSI_ISTAT0_INTF)
 371         level = 1;
 372
 373     if (level != last_level) {
 374         DPRINTF("Update IRQ level %d dstat %02x sist %02x%02x\n",
 375                 level, s->dstat, s->sist1, s->sist0);
 376         last_level = level;
 377     }
 378     qemu_set_irq(s->pci_dev.irq[0], level);
 379 }
 380
 381 /* Stop SCRIPTS execution and raise a SCSI interrupt.  */
 382 static void lsi_script_scsi_interrupt(LSIState *s, int stat0, int stat1)
 383 {
 384     uint32_t mask0;
 385     uint32_t mask1;
 386
 387     DPRINTF("SCSI Interrupt 0x%02x%02x prev 0x%02x%02x\n",
 388             stat1, stat0, s->sist1, s->sist0);
 389     s->sist0 |= stat0;
 390     s->sist1 |= stat1;
 391     /* Stop processor on fatal or unmasked interrupt.  As a special hack
 392        we don't stop processing when raising STO.  Instead continue
 393        execution and stop at the next insn that accesses the SCSI bus.  */
 394     mask0 = s->sien0 | ~(LSI_SIST0_CMP | LSI_SIST0_SEL | LSI_SIST0_RSL);
 395     mask1 = s->sien1 | ~(LSI_SIST1_GEN | LSI_SIST1_HTH);
 396     mask1 &= ~LSI_SIST1_STO;
 397     if (s->sist0 & mask0 || s->sist1 & mask1) {
 398         lsi_stop_script(s);
 399     }
 400     lsi_update_irq(s);
 401 }
 402
 403 /* Stop SCRIPTS execution and raise a DMA interrupt.  */
 404 static void lsi_script_dma_interrupt(LSIState *s, int stat)
 405 {
 406     DPRINTF("DMA Interrupt 0x%x prev 0x%x\n", stat, s->dstat);
 407     s->dstat |= stat;
 408     lsi_update_irq(s);
 409     lsi_stop_script(s);
 410 }
 411
 412 static inline void lsi_set_phase(LSIState *s, int phase)
 413 {
 414     s->sstat1 = (s->sstat1 & ~PHASE_MASK) | phase;
 415 }
 416
 417 static void lsi_bad_phase(LSIState *s, int out, int new_phase)
 418 {
 419     /* Trigger a phase mismatch.  */
 420     if (s->ccntl0 & LSI_CCNTL0_ENPMJ) {
 421         if ((s->ccntl0 & LSI_CCNTL0_PMJCTL) || out) {
 422             s->dsp = s->pmjad1;
 423         } else {
 424             s->dsp = s->pmjad2;
 425         }
 426         DPRINTF("Data phase mismatch jump to %08x\n", s->dsp);
 427     } else {
 428         DPRINTF("Phase mismatch interrupt\n");
 429         lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0);
 430         lsi_stop_script(s);
 431     }
 432     lsi_set_phase(s, new_phase);
 433 }
 434
 435
 436 /* Resume SCRIPTS execution after a DMA operation.  */
 437 static void lsi_resume_script(LSIState *s)
 438 {
 439     if (s->waiting != 2) {
 440         s->waiting = 0;
 441         lsi_execute_script(s);
 442     } else {
 443         s->waiting = 0;
 444     }
 445 }
 446
 447 /* Initiate a SCSI layer data transfer.  */
 448 static void lsi_do_dma(LSIState *s, int out)
 449 {
 450     uint32_t count;
 451     uint32_t addr;
 452
 453     if (!s->current_dma_len) {
 454         /* Wait until data is available.  */
 455         DPRINTF("DMA no data available\n");
 456         return;
 457     }
 458
 459     count = s->dbc;
 460     if (count > s->current_dma_len)
 461         count = s->current_dma_len;
 462     DPRINTF("DMA addr=0x%08x len=%d\n", s->dnad, count);
 463
 464     addr = s->dnad;
 465     s->csbc += count;
 466     s->dnad += count;
 467     s->dbc -= count;
 468
 469     if (s->dma_buf == NULL) {
 470         s->dma_buf = s->current_dev->get_buf(s->current_dev,
 471                                              s->current_tag);
 472     }
 473
 474     /* ??? Set SFBR to first data byte.  */
 475     if (out) {
 476         cpu_physical_memory_read(addr, s->dma_buf, count);
 477     } else {
 478         cpu_physical_memory_write(addr, s->dma_buf, count);
 479     }
 480     s->current_dma_len -= count;
 481     if (s->current_dma_len == 0) {
 482         s->dma_buf = NULL;
 483         if (out) {
 484             /* Write the data.  */
 485             s->current_dev->write_data(s->current_dev, s->current_tag);
 486         } else {
 487             /* Request any remaining data.  */
 488             s->current_dev->read_data(s->current_dev, s->current_tag);
 489         }
 490     } else {
 491         s->dma_buf += count;
 492         lsi_resume_script(s);
 493     }
 494 }
 495
 496
 497 /* Add a command to the queue.  */
 498 static void lsi_queue_command(LSIState *s)
 499 {
 500     lsi_queue *p;
 501
 502     DPRINTF("Queueing tag=0x%x\n", s->current_tag);
 503     if (s->queue_len == s->active_commands) {
 504         s->queue_len++;
 505         s->queue = qemu_realloc(s->queue, s->queue_len * sizeof(lsi_queue));
 506     }
 507     p = &s->queue[s->active_commands++];
 508     p->tag = s->current_tag;
 509     p->pending = 0;
 510     p->out = (s->sstat1 & PHASE_MASK) == PHASE_DO;
 511 }
 512
 513 /* Queue a byte for a MSG IN phase.  */
 514 static void lsi_add_msg_byte(LSIState *s, uint8_t data)
 515 {
 516     if (s->msg_len >= LSI_MAX_MSGIN_LEN) {
 517         BADF("MSG IN data too long\n");
 518     } else {
 519         DPRINTF("MSG IN 0x%02x\n", data);
 520         s->msg[s->msg_len++] = data;
 521     }
 522 }
 523
 524 /* Perform reselection to continue a command.  */
 525 static void lsi_reselect(LSIState *s, uint32_t tag)
 526 {
 527     lsi_queue *p;
 528     int n;
 529     int id;
 530
 531     p = NULL;
 532     for (n = 0; n < s->active_commands; n++) {
 533         p = &s->queue[n];
 534         if (p->tag == tag)
 535             break;
 536     }
 537     if (n == s->active_commands) {
 538         BADF("Reselected non-existant command tag=0x%x\n", tag);
 539         return;
 540     }
 541     id = (tag >> 8) & 0xf;
 542     s->ssid = id | 0x80;
 543     DPRINTF("Reselected target %d\n", id);
 544     s->current_dev = s->scsi_dev[id];
 545     s->current_tag = tag;
 546     s->scntl1 |= LSI_SCNTL1_CON;
 547     lsi_set_phase(s, PHASE_MI);
 548     s->msg_action = p->out ? 2 : 3;
 549     s->current_dma_len = p->pending;
 550     s->dma_buf = NULL;
 551     lsi_add_msg_byte(s, 0x80);
 552     if (s->current_tag & LSI_TAG_VALID) {
 553         lsi_add_msg_byte(s, 0x20);
 554         lsi_add_msg_byte(s, tag & 0xff);
 555     }
 556
 557     s->active_commands--;
 558     if (n != s->active_commands) {
 559         s->queue[n] = s->queue[s->active_commands];
 560     }
 561 }
 562
 563 /* Record that data is available for a queued command.  Returns zero if
 564    the device was reselected, nonzero if the IO is deferred.  */
 565 static int lsi_queue_tag(LSIState *s, uint32_t tag, uint32_t arg)
 566 {
 567     lsi_queue *p;
 568     int i;
 569     for (i = 0; i < s->active_commands; i++) {
 570         p = &s->queue[i];
 571         if (p->tag == tag) {
 572             if (p->pending) {
 573                 BADF("Multiple IO pending for tag %d\n", tag);
 574             }
 575             p->pending = arg;
 576             if (s->waiting == 1) {
 577                 /* Reselect device.  */
 578                 lsi_reselect(s, tag);
 579                 return 0;
 580             } else {
 581                DPRINTF("Queueing IO tag=0x%x\n", tag);
 582                 p->pending = arg;
 583                 return 1;
 584             }
 585         }
 586     }
 587     BADF("IO with unknown tag %d\n", tag);
 588     return 1;
 589 }
 590
 591 /* Callback to indicate that the SCSI layer has completed a transfer.  */
 592 static void lsi_command_complete(void *opaque, int reason, uint32_t tag,
 593                                  uint32_t arg)
 594 {
 595     LSIState *s = (LSIState *)opaque;
 596     int out;
 597
 598     out = (s->sstat1 & PHASE_MASK) == PHASE_DO;
 599     if (reason == SCSI_REASON_DONE) {
 600         DPRINTF("Command complete sense=%d\n", (int)arg);
 601         s->sense = arg;
 602         s->command_complete = 2;
 603         if (s->waiting && s->dbc != 0) {
 604             /* Raise phase mismatch for short transfers.  */
 605             lsi_bad_phase(s, out, PHASE_ST);
 606         } else {
 607             lsi_set_phase(s, PHASE_ST);
 608         }
 609         lsi_resume_script(s);
 610         return;
 611     }
 612
 613     if (s->waiting == 1 || tag != s->current_tag) {
 614         if (lsi_queue_tag(s, tag, arg))
 615             return;
 616     }
 617     DPRINTF("Data ready tag=0x%x len=%d\n", tag, arg);
 618     s->current_dma_len = arg;
 619     s->command_complete = 1;
 620     if (!s->waiting)
 621         return;
 622     if (s->waiting == 1 || s->dbc == 0) {
 623         lsi_resume_script(s);
 624     } else {
 625         lsi_do_dma(s, out);
 626     }
 627 }
 628
 629 static void lsi_do_command(LSIState *s)
 630 {
 631     uint8_t buf[16];
 632     int n;
 633
 634     DPRINTF("Send command len=%d\n", s->dbc);
 635     if (s->dbc > 16)
 636         s->dbc = 16;
 637     cpu_physical_memory_read(s->dnad, buf, s->dbc);
 638     s->sfbr = buf[0];
 639     s->command_complete = 0;
 640     n = s->current_dev->send_command(s->current_dev, s->current_tag, buf,
 641                                      s->current_lun);
 642     if (n > 0) {
 643         lsi_set_phase(s, PHASE_DI);
 644         s->current_dev->read_data(s->current_dev, s->current_tag);
 645     } else if (n < 0) {
 646         lsi_set_phase(s, PHASE_DO);
 647         s->current_dev->write_data(s->current_dev, s->current_tag);
 648     }
 649
 650     if (!s->command_complete) {
 651         if (n) {
 652             /* Command did not complete immediately so disconnect.  */
 653             lsi_add_msg_byte(s, 2); /* SAVE DATA POINTER */
 654             lsi_add_msg_byte(s, 4); /* DISCONNECT */
 655             /* wait data */
 656             lsi_set_phase(s, PHASE_MI);
 657             s->msg_action = 1;
 658             lsi_queue_command(s);
 659         } else {
 660             /* wait command complete */
 661             lsi_set_phase(s, PHASE_DI);
 662         }
 663     }
 664 }
 665
 666 static void lsi_do_status(LSIState *s)
 667 {
 668     uint8_t sense;
 669     DPRINTF("Get status len=%d sense=%d\n", s->dbc, s->sense);
 670     if (s->dbc != 1)
 671         BADF("Bad Status move\n");
 672     s->dbc = 1;
 673     sense = s->sense;
 674     s->sfbr = sense;
 675     cpu_physical_memory_write(s->dnad, &sense, 1);
 676     lsi_set_phase(s, PHASE_MI);
 677     s->msg_action = 1;
 678     lsi_add_msg_byte(s, 0); /* COMMAND COMPLETE */
 679 }
 680
 681 static void lsi_disconnect(LSIState *s)
 682 {
 683     s->scntl1 &= ~LSI_SCNTL1_CON;
 684     s->sstat1 &= ~PHASE_MASK;
 685 }
 686
 687 static void lsi_do_msgin(LSIState *s)
 688 {
 689     int len;
 690     DPRINTF("Message in len=%d/%d\n", s->dbc, s->msg_len);
 691     s->sfbr = s->msg[0];
 692     len = s->msg_len;
 693     if (len > s->dbc)
 694         len = s->dbc;
 695     cpu_physical_memory_write(s->dnad, s->msg, len);
 696     /* Linux drivers rely on the last byte being in the SIDL.  */
 697     s->sidl = s->msg[len - 1];
 698     s->msg_len -= len;
 699     if (s->msg_len) {
 700         memmove(s->msg, s->msg + len, s->msg_len);
 701     } else {
 702         /* ??? Check if ATN (not yet implemented) is asserted and maybe
 703            switch to PHASE_MO.  */
 704         switch (s->msg_action) {
 705         case 0:
 706             lsi_set_phase(s, PHASE_CMD);
 707             break;
 708         case 1:
 709             lsi_disconnect(s);
 710             break;
 711         case 2:
 712             lsi_set_phase(s, PHASE_DO);
 713             break;
 714         case 3:
 715             lsi_set_phase(s, PHASE_DI);
 716             break;
 717         default:
 718             abort();
 719         }
 720     }
 721 }
 722
 723 /* Read the next byte during a MSGOUT phase.  */
 724 static uint8_t lsi_get_msgbyte(LSIState *s)
 725 {
 726     uint8_t data;
 727     cpu_physical_memory_read(s->dnad, &data, 1);
 728     s->dnad++;
 729     s->dbc--;
 730     return data;
 731 }
 732
 733 static void lsi_do_msgout(LSIState *s)
 734 {
 735     uint8_t msg;
 736     int len;
 737
 738     DPRINTF("MSG out len=%d\n", s->dbc);
 739     while (s->dbc) {
 740         msg = lsi_get_msgbyte(s);
 741         s->sfbr = msg;
 742
 743         switch (msg) {
 744         case 0x00:
 745             DPRINTF("MSG: Disconnect\n");
 746             lsi_disconnect(s);
 747             break;
 748         case 0x08:
 749             DPRINTF("MSG: No Operation\n");
 750             lsi_set_phase(s, PHASE_CMD);
 751             break;
 752         case 0x01:
 753             len = lsi_get_msgbyte(s);
 754             msg = lsi_get_msgbyte(s);
 755             DPRINTF("Extended message 0x%x (len %d)\n", msg, len);
 756             switch (msg) {
 757             case 1:
 758                 DPRINTF("SDTR (ignored)\n");
 759                 s->dbc -= 2;
 760                 break;
 761             case 3:
 762                 DPRINTF("WDTR (ignored)\n");
 763                 s->dbc -= 1;
 764                 break;
 765             default:
 766                 goto bad;
 767             }
 768             break;
 769         case 0x20: /* SIMPLE queue */
 770             s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
 771             DPRINTF("SIMPLE queue tag=0x%x\n", s->current_tag & 0xff);
 772             break;
 773         case 0x21: /* HEAD of queue */
 774             BADF("HEAD queue not implemented\n");
 775             s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
 776             break;
 777         case 0x22: /* ORDERED queue */
 778             BADF("ORDERED queue not implemented\n");
 779             s->current_tag |= lsi_get_msgbyte(s) | LSI_TAG_VALID;
 780             break;
 781         default:
 782             if ((msg & 0x80) == 0) {
 783                 goto bad;
 784             }
 785             s->current_lun = msg & 7;
 786             DPRINTF("Select LUN %d\n", s->current_lun);
 787             lsi_set_phase(s, PHASE_CMD);
 788             break;
 789         }
 790     }
 791     return;
 792 bad:
 793     BADF("Unimplemented message 0x%02x\n", msg);
 794     lsi_set_phase(s, PHASE_MI);
 795     lsi_add_msg_byte(s, 7); /* MESSAGE REJECT */
 796     s->msg_action = 0;
 797 }
 798
 799 /* Sign extend a 24-bit value.  */
 800 static inline int32_t sxt24(int32_t n)
 801 {
 802     return (n << 8) >> 8;
 803 }
 804
 805 static void lsi_memcpy(LSIState *s, uint32_t dest, uint32_t src, int count)
 806 {
 807     int n;
 808     uint8_t buf[TARGET_PAGE_SIZE];
 809
 810     DPRINTF("memcpy dest 0x%08x src 0x%08x count %d\n", dest, src, count);
 811     while (count) {
 812         n = (count > TARGET_PAGE_SIZE) ? TARGET_PAGE_SIZE : count;
 813         cpu_physical_memory_read(src, buf, n);
 814         cpu_physical_memory_write(dest, buf, n);
 815         src += n;
 816         dest += n;
 817         count -= n;
 818     }
 819 }
 820
 821 static void lsi_wait_reselect(LSIState *s)
 822 {
 823     int i;
 824     DPRINTF("Wait Reselect\n");
 825     if (s->current_dma_len)
 826         BADF("Reselect with pending DMA\n");
 827     for (i = 0; i < s->active_commands; i++) {
 828         if (s->queue[i].pending) {
 829             lsi_reselect(s, s->queue[i].tag);
 830             break;
 831         }
 832     }
 833     if (s->current_dma_len == 0) {
 834         s->waiting = 1;
 835     }
 836 }
 837
 838 static void lsi_execute_script(LSIState *s)
 839 {
 840     uint32_t insn;
 841     uint32_t addr;
 842     int opcode;
 843     int insn_processed = 0;
 844
 845     s->istat1 |= LSI_ISTAT1_SRUN;
 846 again:
 847     insn_processed++;
 848     insn = read_dword(s, s->dsp);
 849     addr = read_dword(s, s->dsp + 4);
 850     DPRINTF("SCRIPTS dsp=%08x opcode %08x arg %08x\n", s->dsp, insn, addr);
 851     s->dsps = addr;
 852     s->dcmd = insn >> 24;
 853     s->dsp += 8;
 854     switch (insn >> 30) {
 855     case 0: /* Block move.  */
 856         if (s->sist1 & LSI_SIST1_STO) {
 857             DPRINTF("Delayed select timeout\n");
 858             lsi_stop_script(s);
 859             break;
 860         }
 861         s->dbc = insn & 0xffffff;
 862         s->rbc = s->dbc;
 863         if (insn & (1 << 29)) {
 864             /* Indirect addressing.  */
 865             addr = read_dword(s, addr);
 866         } else if (insn & (1 << 28)) {
 867             uint32_t buf[2];
 868             int32_t offset;
 869             /* Table indirect addressing.  */
 870             offset = sxt24(addr);
 871             cpu_physical_memory_read(s->dsa + offset, (uint8_t *)buf, 8);
 872             s->dbc = cpu_to_le32(buf[0]);
 873             s->rbc = s->dbc;
 874             addr = cpu_to_le32(buf[1]);
 875         }
 876         if ((s->sstat1 & PHASE_MASK) != ((insn >> 24) & 7)) {
 877             DPRINTF("Wrong phase got %d expected %d\n",
 878                     s->sstat1 & PHASE_MASK, (insn >> 24) & 7);
 879             lsi_script_scsi_interrupt(s, LSI_SIST0_MA, 0);
 880             break;
 881         }
 882         s->dnad = addr;
 883         /* ??? Set ESA.  */
 884         s->ia = s->dsp - 8;
 885         switch (s->sstat1 & 0x7) {
 886         case PHASE_DO:
 887             s->waiting = 2;
 888             lsi_do_dma(s, 1);
 889             if (s->waiting)
 890                 s->waiting = 3;
 891             break;
 892         case PHASE_DI:
 893             s->waiting = 2;
 894             lsi_do_dma(s, 0);
 895             if (s->waiting)
 896                 s->waiting = 3;
 897             break;
 898         case PHASE_CMD:
 899             lsi_do_command(s);
 900             break;
 901         case PHASE_ST:
 902             lsi_do_status(s);
 903             break;
 904         case PHASE_MO:
 905             lsi_do_msgout(s);
 906             break;
 907         case PHASE_MI:
 908             lsi_do_msgin(s);
 909             break;
 910         default:
 911             BADF("Unimplemented phase %d\n", s->sstat1 & PHASE_MASK);
 912             exit(1);
 913         }
 914         s->dfifo = s->dbc & 0xff;
 915         s->ctest5 = (s->ctest5 & 0xfc) | ((s->dbc >> 8) & 3);
 916         s->sbc = s->dbc;
 917         s->rbc -= s->dbc;
 918         s->ua = addr + s->dbc;
 919         break;
 920
 921     case 1: /* IO or Read/Write instruction.  */
 922         opcode = (insn >> 27) & 7;
 923         if (opcode < 5) {
 924             uint32_t id;
 925
 926             if (insn & (1 << 25)) {
 927                 id = read_dword(s, s->dsa + sxt24(insn));
 928             } else {
 929                 id = addr;
 930             }
 931             id = (id >> 16) & 0xf;
 932             if (insn & (1 << 26)) {
 933                 addr = s->dsp + sxt24(addr);
 934             }
 935             s->dnad = addr;
 936             switch (opcode) {
 937             case 0: /* Select */
 938                 s->sdid = id;
 939                 if (s->current_dma_len && (s->ssid & 0xf) == id) {
 940                     DPRINTF("Already reselected by target %d\n", id);
 941                     break;
 942                 }
 943                 s->sstat0 |= LSI_SSTAT0_WOA;
 944                 s->scntl1 &= ~LSI_SCNTL1_IARB;
 945                 if (id >= LSI_MAX_DEVS || !s->scsi_dev[id]) {
 946                     DPRINTF("Selected absent target %d\n", id);
 947                     lsi_script_scsi_interrupt(s, 0, LSI_SIST1_STO);
 948                     lsi_disconnect(s);
 949                     break;
 950                 }
 951                 DPRINTF("Selected target %d%s\n",
 952                         id, insn & (1 << 3) ? " ATN" : "");
 953                 /* ??? Linux drivers compain when this is set.  Maybe
 954                    it only applies in low-level mode (unimplemented).
 955                 lsi_script_scsi_interrupt(s, LSI_SIST0_CMP, 0); */
 956                 s->current_dev = s->scsi_dev[id];
 957                 s->current_tag = id << 8;
 958                 s->scntl1 |= LSI_SCNTL1_CON;
 959                 if (insn & (1 << 3)) {
 960                     s->socl |= LSI_SOCL_ATN;
 961                 }
 962                 lsi_set_phase(s, PHASE_MO);
 963                 break;
 964             case 1: /* Disconnect */
 965                 DPRINTF("Wait Disconect\n");
 966                 s->scntl1 &= ~LSI_SCNTL1_CON;
 967                 break;
 968             case 2: /* Wait Reselect */
 969                 lsi_wait_reselect(s);
 970                 break;
 971             case 3: /* Set */
 972                 DPRINTF("Set%s%s%s%s\n",
 973                         insn & (1 << 3) ? " ATN" : "",
 974                         insn & (1 << 6) ? " ACK" : "",
 975                         insn & (1 << 9) ? " TM" : "",
 976                         insn & (1 << 10) ? " CC" : "");
 977                 if (insn & (1 << 3)) {
 978                     s->socl |= LSI_SOCL_ATN;
 979                     lsi_set_phase(s, PHASE_MO);
 980                 }
 981                 if (insn & (1 << 9)) {
 982                     BADF("Target mode not implemented\n");
 983                     exit(1);
 984                 }
 985                 if (insn & (1 << 10))
 986                     s->carry = 1;
 987                 break;
 988             case 4: /* Clear */
 989                 DPRINTF("Clear%s%s%s%s\n",
 990                         insn & (1 << 3) ? " ATN" : "",
 991                         insn & (1 << 6) ? " ACK" : "",
 992                         insn & (1 << 9) ? " TM" : "",
 993                         insn & (1 << 10) ? " CC" : "");
 994                 if (insn & (1 << 3)) {
 995                     s->socl &= ~LSI_SOCL_ATN;
 996                 }
 997                 if (insn & (1 << 10))
 998                     s->carry = 0;
 999                 break;
1000             }
1001         } else {
1002             uint8_t op0;
1003             uint8_t op1;
1004             uint8_t data8;
1005             int reg;
1006             int operator;
1007 #ifdef DEBUG_LSI
1008             static const char *opcode_names[3] =
1009                 {"Write", "Read", "Read-Modify-Write"};
1010             static const char *operator_names[8] =
1011                 {"MOV", "SHL", "OR", "XOR", "AND", "SHR", "ADD", "ADC"};
1012 #endif
1013
1014             reg = ((insn >> 16) & 0x7f) | (insn & 0x80);
1015             data8 = (insn >> 8) & 0xff;
1016             opcode = (insn >> 27) & 7;
1017             operator = (insn >> 24) & 7;
1018             DPRINTF("%s reg 0x%x %s data8=0x%02x sfbr=0x%02x%s\n",
1019                     opcode_names[opcode - 5], reg,
1020                     operator_names[operator], data8, s->sfbr,
1021                     (insn & (1 << 23)) ? " SFBR" : "");
1022             op0 = op1 = 0;
1023             switch (opcode) {
1024             case 5: /* From SFBR */
1025                 op0 = s->sfbr;
1026                 op1 = data8;
1027                 break;
1028             case 6: /* To SFBR */
1029                 if (operator)
1030                     op0 = lsi_reg_readb(s, reg);
1031                 op1 = data8;
1032                 break;
1033             case 7: /* Read-modify-write */
1034                 if (operator)
1035                     op0 = lsi_reg_readb(s, reg);
1036                 if (insn & (1 << 23)) {
1037                     op1 = s->sfbr;
1038                 } else {
1039                     op1 = data8;
1040                 }
1041                 break;
1042             }
1043
1044             switch (operator) {
1045             case 0: /* move */
1046                 op0 = op1;
1047                 break;
1048             case 1: /* Shift left */
1049                 op1 = op0 >> 7;
1050                 op0 = (op0 << 1) | s->carry;
1051                 s->carry = op1;
1052                 break;
1053             case 2: /* OR */
1054                 op0 |= op1;
1055                 break;
1056             case 3: /* XOR */
1057                 op0 ^= op1;
1058                 break;
1059             case 4: /* AND */
1060                 op0 &= op1;
1061                 break;
1062             case 5: /* SHR */
1063                 op1 = op0 & 1;
1064                 op0 = (op0 >> 1) | (s->carry << 7);
1065                 s->carry = op1;
1066                 break;
1067             case 6: /* ADD */
1068                 op0 += op1;
1069                 s->carry = op0 < op1;
1070                 break;
1071             case 7: /* ADC */
1072                 op0 += op1 + s->carry;
1073                 if (s->carry)
1074                     s->carry = op0 <= op1;
1075                 else
1076                     s->carry = op0 < op1;
1077                 break;
1078             }
1079
1080             switch (opcode) {
1081             case 5: /* From SFBR */
1082             case 7: /* Read-modify-write */
1083                 lsi_reg_writeb(s, reg, op0);
1084                 break;
1085             case 6: /* To SFBR */
1086                 s->sfbr = op0;
1087                 break;
1088             }
1089         }
1090         break;
1091
1092     case 2: /* Transfer Control.  */
1093         {
1094             int cond;
1095             int jmp;
1096
1097             if ((insn & 0x002e0000) == 0) {
1098                 DPRINTF("NOP\n");
1099                 break;
1100             }
1101             if (s->sist1 & LSI_SIST1_STO) {
1102                 DPRINTF("Delayed select timeout\n");
1103                 lsi_stop_script(s);
1104                 break;
1105             }
1106             cond = jmp = (insn & (1 << 19)) != 0;
1107             if (cond == jmp && (insn & (1 << 21))) {
1108                 DPRINTF("Compare carry %d\n", s->carry == jmp);
1109                 cond = s->carry != 0;
1110             }
1111             if (cond == jmp && (insn & (1 << 17))) {
1112                 DPRINTF("Compare phase %d %c= %d\n",
1113                         (s->sstat1 & PHASE_MASK),
1114                         jmp ? '=' : '!',
1115                         ((insn >> 24) & 7));
1116                 cond = (s->sstat1 & PHASE_MASK) == ((insn >> 24) & 7);
1117             }
1118             if (cond == jmp && (insn & (1 << 18))) {
1119                 uint8_t mask;
1120
1121                 mask = (~insn >> 8) & 0xff;
1122                 DPRINTF("Compare data 0x%x & 0x%x %c= 0x%x\n",
1123                         s->sfbr, mask, jmp ? '=' : '!', insn & mask);
1124                 cond = (s->sfbr & mask) == (insn & mask);
1125             }
1126             if (cond == jmp) {
1127                 if (insn & (1 << 23)) {
1128                     /* Relative address.  */
1129                     addr = s->dsp + sxt24(addr);
1130                 }
1131                 switch ((insn >> 27) & 7) {
1132                 case 0: /* Jump */
1133                     DPRINTF("Jump to 0x%08x\n", addr);
1134                     s->dsp = addr;
1135                     break;
1136                 case 1: /* Call */
1137                     DPRINTF("Call 0x%08x\n", addr);
1138                     s->temp = s->dsp;
1139                     s->dsp = addr;
1140                     break;
1141                 case 2: /* Return */
1142                     DPRINTF("Return to 0x%08x\n", s->temp);
1143                     s->dsp = s->temp;
1144                     break;
1145                 case 3: /* Interrupt */
1146                     DPRINTF("Interrupt 0x%08x\n", s->dsps);
1147                     if ((insn & (1 << 20)) != 0) {
1148                         s->istat0 |= LSI_ISTAT0_INTF;
1149                         lsi_update_irq(s);
1150                     } else {
1151                         lsi_script_dma_interrupt(s, LSI_DSTAT_SIR);
1152                     }
1153                     break;
1154                 default:
1155                     DPRINTF("Illegal transfer control\n");
1156                     lsi_script_dma_interrupt(s, LSI_DSTAT_IID);
1157                     break;
1158                 }
1159             } else {
1160                 DPRINTF("Control condition failed\n");
1161             }
1162         }
1163         break;
1164
1165     case 3:
1166         if ((insn & (1 << 29)) == 0) {
1167             /* Memory move.  */
1168             uint32_t dest;
1169             /* ??? The docs imply the destination address is loaded into
1170                the TEMP register.  However the Linux drivers rely on
1171                the value being presrved.  */
1172             dest = read_dword(s, s->dsp);
1173             s->dsp += 4;
1174             lsi_memcpy(s, dest, addr, insn & 0xffffff);
1175         } else {
1176             uint8_t data[7];
1177             int reg;
1178             int n;
1179             int i;
1180
1181             if (insn & (1 << 28)) {
1182                 addr = s->dsa + sxt24(addr);
1183             }
1184             n = (insn & 7);
1185             reg = (insn >> 16) & 0xff;
1186             if (insn & (1 << 24)) {
1187                 cpu_physical_memory_read(addr, data, n);
1188                 DPRINTF("Load reg 0x%x size %d addr 0x%08x = %08x\n", reg, n,
1189                         addr, *(int *)data);
1190                 for (i = 0; i < n; i++) {
1191                     lsi_reg_writeb(s, reg + i, data[i]);
1192                 }
1193             } else {
1194                 DPRINTF("Store reg 0x%x size %d addr 0x%08x\n", reg, n, addr);
1195                 for (i = 0; i < n; i++) {
1196                     data[i] = lsi_reg_readb(s, reg + i);
1197                 }
1198                 cpu_physical_memory_write(addr, data, n);
1199             }
1200         }
1201     }
1202     if (insn_processed > 10000 && !s->waiting) {
1203         /* Some windows drivers make the device spin waiting for a memory
1204            location to change.  If we have been executed a lot of code then
1205            assume this is the case and force an unexpected device disconnect.
1206            This is apparently sufficient to beat the drivers into submission.
1207          */
1208         if (!(s->sien0 & LSI_SIST0_UDC))
1209             fprintf(stderr, "inf. loop with UDC masked\n");
1210         lsi_script_scsi_interrupt(s, LSI_SIST0_UDC, 0);
1211         lsi_disconnect(s);
1212     } else if (s->istat1 & LSI_ISTAT1_SRUN && !s->waiting) {
1213         if (s->dcntl & LSI_DCNTL_SSM) {
1214             lsi_script_dma_interrupt(s, LSI_DSTAT_SSI);
1215         } else {
1216             goto again;
1217         }
1218     }
1219     DPRINTF("SCRIPTS execution stopped\n");
1220 }
1221
1222 static uint8_t lsi_reg_readb(LSIState *s, int offset)
1223 {
1224     uint8_t tmp;
1225 #define CASE_GET_REG32(name, addr) \
1226     case addr: return s->name & 0xff; \
1227     case addr + 1: return (s->name >> 8) & 0xff; \
1228     case addr + 2: return (s->name >> 16) & 0xff; \
1229     case addr + 3: return (s->name >> 24) & 0xff;
1230
1231 #ifdef DEBUG_LSI_REG
1232     DPRINTF("Read reg %x\n", offset);
1233 #endif
1234     switch (offset) {
1235     case 0x00: /* SCNTL0 */
1236         return s->scntl0;
1237     case 0x01: /* SCNTL1 */
1238         return s->scntl1;
1239     case 0x02: /* SCNTL2 */
1240         return s->scntl2;
1241     case 0x03: /* SCNTL3 */
1242         return s->scntl3;
1243     case 0x04: /* SCID */
1244         return s->scid;
1245     case 0x05: /* SXFER */
1246         return s->sxfer;
1247     case 0x06: /* SDID */
1248         return s->sdid;
1249     case 0x07: /* GPREG0 */
1250         return 0x7f;
1251     case 0x08: /* Revision ID */
1252         return 0x00;
1253     case 0xa: /* SSID */
1254         return s->ssid;
1255     case 0xb: /* SBCL */
1256         /* ??? This is not correct. However it's (hopefully) only
1257            used for diagnostics, so should be ok.  */
1258         return 0;
1259     case 0xc: /* DSTAT */
1260         tmp = s->dstat | 0x80;
1261         if ((s->istat0 & LSI_ISTAT0_INTF) == 0)
1262             s->dstat = 0;
1263         lsi_update_irq(s);
1264         return tmp;
1265     case 0x0d: /* SSTAT0 */
1266         return s->sstat0;
1267     case 0x0e: /* SSTAT1 */
1268         return s->sstat1;
1269     case 0x0f: /* SSTAT2 */
1270         return s->scntl1 & LSI_SCNTL1_CON ? 0 : 2;
1271     CASE_GET_REG32(dsa, 0x10)
1272     case 0x14: /* ISTAT0 */
1273         return s->istat0;
1274     case 0x16: /* MBOX0 */
1275         return s->mbox0;
1276     case 0x17: /* MBOX1 */
1277         return s->mbox1;
1278     case 0x18: /* CTEST0 */
1279         return 0xff;
1280     case 0x19: /* CTEST1 */
1281         return 0;
1282     case 0x1a: /* CTEST2 */
1283         tmp = LSI_CTEST2_DACK | LSI_CTEST2_CM;
1284         if (s->istat0 & LSI_ISTAT0_SIGP) {
1285             s->istat0 &= ~LSI_ISTAT0_SIGP;
1286             tmp |= LSI_CTEST2_SIGP;
1287         }
1288         return tmp;
1289     case 0x1b: /* CTEST3 */
1290         return s->ctest3;
1291     CASE_GET_REG32(temp, 0x1c)
1292     case 0x20: /* DFIFO */
1293         return 0;
1294     case 0x21: /* CTEST4 */
1295         return s->ctest4;
1296     case 0x22: /* CTEST5 */
1297         return s->ctest5;
1298     case 0x23: /* CTEST6 */
1299          return 0;
1300     case 0x24: /* DBC[0:7] */
1301         return s->dbc & 0xff;
1302     case 0x25: /* DBC[8:15] */
1303         return (s->dbc >> 8) & 0xff;
1304     case 0x26: /* DBC[16->23] */
1305         return (s->dbc >> 16) & 0xff;
1306     case 0x27: /* DCMD */
1307         return s->dcmd;
1308     CASE_GET_REG32(dsp, 0x2c)
1309     CASE_GET_REG32(dsps, 0x30)
1310     CASE_GET_REG32(scratch[0], 0x34)
1311     case 0x38: /* DMODE */
1312         return s->dmode;
1313     case 0x39: /* DIEN */
1314         return s->dien;
1315     case 0x3b: /* DCNTL */
1316         return s->dcntl;
1317     case 0x40: /* SIEN0 */
1318         return s->sien0;
1319     case 0x41: /* SIEN1 */
1320         return s->sien1;
1321     case 0x42: /* SIST0 */
1322         tmp = s->sist0;
1323         s->sist0 = 0;
1324         lsi_update_irq(s);
1325         return tmp;
1326     case 0x43: /* SIST1 */
1327         tmp = s->sist1;
1328         s->sist1 = 0;
1329         lsi_update_irq(s);
1330         return tmp;
1331     case 0x47: /* GPCNTL0 */
1332         return 0x0f;
1333     case 0x48: /* STIME0 */
1334         return s->stime0;
1335     case 0x4a: /* RESPID0 */
1336         return s->respid0;
1337     case 0x4b: /* RESPID1 */
1338         return s->respid1;
1339     case 0x4d: /* STEST1 */
1340         return s->stest1;
1341     case 0x4e: /* STEST2 */
1342         return s->stest2;
1343     case 0x4f: /* STEST3 */
1344         return s->stest3;
1345     case 0x50: /* SIDL */
1346         /* This is needed by the linux drivers.  We currently only update it
1347            during the MSG IN phase.  */
1348         return s->sidl;
1349     case 0x52: /* STEST4 */
1350         return 0xe0;
1351     case 0x56: /* CCNTL0 */
1352         return s->ccntl0;
1353     case 0x57: /* CCNTL1 */
1354         return s->ccntl1;
1355     case 0x58: /* SBDL */
1356         /* Some drivers peek at the data bus during the MSG IN phase.  */
1357         if ((s->sstat1 & PHASE_MASK) == PHASE_MI)
1358             return s->msg[0];
1359         return 0;
1360     case 0x59: /* SBDL high */
1361         return 0;
1362     CASE_GET_REG32(mmrs, 0xa0)
1363     CASE_GET_REG32(mmws, 0xa4)
1364     CASE_GET_REG32(sfs, 0xa8)
1365     CASE_GET_REG32(drs, 0xac)
1366     CASE_GET_REG32(sbms, 0xb0)
1367     CASE_GET_REG32(dmbs, 0xb4)
1368     CASE_GET_REG32(dnad64, 0xb8)
1369     CASE_GET_REG32(pmjad1, 0xc0)
1370     CASE_GET_REG32(pmjad2, 0xc4)
1371     CASE_GET_REG32(rbc, 0xc8)
1372     CASE_GET_REG32(ua, 0xcc)
1373     CASE_GET_REG32(ia, 0xd4)
1374     CASE_GET_REG32(sbc, 0xd8)
1375     CASE_GET_REG32(csbc, 0xdc)
1376     }
1377     if (offset >= 0x5c && offset < 0xa0) {
1378         int n;
1379         int shift;
1380         n = (offset - 0x58) >> 2;
1381         shift = (offset & 3) * 8;
1382         return (s->scratch[n] >> shift) & 0xff;
1383     }
1384     BADF("readb 0x%x\n", offset);
1385     exit(1);
1386 #undef CASE_GET_REG32
1387 }
1388
1389 static void lsi_reg_writeb(LSIState *s, int offset, uint8_t val)
1390 {
1391 #define CASE_SET_REG32(name, addr) \
1392     case addr    : s->name &= 0xffffff00; s->name |= val;       break; \
1393     case addr + 1: s->name &= 0xffff00ff; s->name |= val << 8;  break; \
1394     case addr + 2: s->name &= 0xff00ffff; s->name |= val << 16; break; \
1395     case addr + 3: s->name &= 0x00ffffff; s->name |= val << 24; break;
1396
1397 #ifdef DEBUG_LSI_REG
1398     DPRINTF("Write reg %x = %02x\n", offset, val);
1399 #endif
1400     switch (offset) {
1401     case 0x00: /* SCNTL0 */
1402         s->scntl0 = val;
1403         if (val & LSI_SCNTL0_START) {
1404             BADF("Start sequence not implemented\n");
1405         }
1406         break;
1407     case 0x01: /* SCNTL1 */
1408         s->scntl1 = val & ~LSI_SCNTL1_SST;
1409         if (val & LSI_SCNTL1_IARB) {
1410             BADF("Immediate Arbritration not implemented\n");
1411         }
1412         if (val & LSI_SCNTL1_RST) {
1413             s->sstat0 |= LSI_SSTAT0_RST;
1414             lsi_script_scsi_interrupt(s, LSI_SIST0_RST, 0);
1415         } else {
1416             s->sstat0 &= ~LSI_SSTAT0_RST;
1417         }
1418         break;
1419     case 0x02: /* SCNTL2 */
1420         val &= ~(LSI_SCNTL2_WSR | LSI_SCNTL2_WSS);
1421         s->scntl2 = val;
1422         break;
1423     case 0x03: /* SCNTL3 */
1424         s->scntl3 = val;
1425         break;
1426     case 0x04: /* SCID */
1427         s->scid = val;
1428         break;
1429     case 0x05: /* SXFER */
1430         s->sxfer = val;
1431         break;
1432     case 0x06: /* SDID */
1433         if ((val & 0xf) != (s->ssid & 0xf))
1434             BADF("Destination ID does not match SSID\n");
1435         s->sdid = val & 0xf;
1436         break;
1437     case 0x07: /* GPREG0 */
1438         break;
1439     case 0x08: /* SFBR */
1440         /* The CPU is not allowed to write to this register.  However the
1441            SCRIPTS register move instructions are.  */
1442         s->sfbr = val;
1443         break;
1444     case 0x0c: case 0x0d: case 0x0e: case 0x0f:
1445         /* Linux writes to these readonly registers on startup.  */
1446         return;
1447     CASE_SET_REG32(dsa, 0x10)
1448     case 0x14: /* ISTAT0 */
1449         s->istat0 = (s->istat0 & 0x0f) | (val & 0xf0);
1450         if (val & LSI_ISTAT0_ABRT) {
1451             lsi_script_dma_interrupt(s, LSI_DSTAT_ABRT);
1452         }
1453         if (val & LSI_ISTAT0_INTF) {
1454             s->istat0 &= ~LSI_ISTAT0_INTF;
1455             lsi_update_irq(s);
1456         }
1457         if (s->waiting == 1 && val & LSI_ISTAT0_SIGP) {
1458             DPRINTF("Woken by SIGP\n");
1459             s->waiting = 0;
1460             s->dsp = s->dnad;
1461             lsi_execute_script(s);
1462         }
1463         if (val & LSI_ISTAT0_SRST) {
1464             lsi_soft_reset(s);
1465         }
1466         break;
1467     case 0x16: /* MBOX0 */
1468         s->mbox0 = val;
1469         break;
1470     case 0x17: /* MBOX1 */
1471         s->mbox1 = val;
1472         break;
1473     case 0x1b: /* CTEST3 */
1474         s->ctest3 = val & 0x0f;
1475         break;
1476     CASE_SET_REG32(temp, 0x1c)
1477     case 0x21: /* CTEST4 */
1478         if (val & 7) {
1479            BADF("Unimplemented CTEST4-FBL 0x%x\n", val);
1480         }
1481         s->ctest4 = val;
1482         break;
1483     case 0x22: /* CTEST5 */
1484         if (val & (LSI_CTEST5_ADCK | LSI_CTEST5_BBCK)) {
1485             BADF("CTEST5 DMA increment not implemented\n");
1486         }
1487         s->ctest5 = val;
1488         break;
1489     case 0x2c: /* DSP[0:7] */
1490         s->dsp &= 0xffffff00;
1491         s->dsp |= val;
1492         break;
1493     case 0x2d: /* DSP[8:15] */
1494         s->dsp &= 0xffff00ff;
1495         s->dsp |= val << 8;
1496         break;
1497     case 0x2e: /* DSP[16:23] */
1498         s->dsp &= 0xff00ffff;
1499         s->dsp |= val << 16;
1500         break;
1501     case 0x2f: /* DSP[24:31] */
1502         s->dsp &= 0x00ffffff;
1503         s->dsp |= val << 24;
1504         if ((s->dmode & LSI_DMODE_MAN) == 0
1505             && (s->istat1 & LSI_ISTAT1_SRUN) == 0)
1506             lsi_execute_script(s);
1507         break;
1508     CASE_SET_REG32(dsps, 0x30)
1509     CASE_SET_REG32(scratch[0], 0x34)
1510     case 0x38: /* DMODE */
1511         if (val & (LSI_DMODE_SIOM | LSI_DMODE_DIOM)) {
1512             BADF("IO mappings not implemented\n");
1513         }
1514         s->dmode = val;
1515         break;
1516     case 0x39: /* DIEN */
1517         s->dien = val;
1518         lsi_update_irq(s);
1519         break;
1520     case 0x3b: /* DCNTL */
1521         s->dcntl = val & ~(LSI_DCNTL_PFF | LSI_DCNTL_STD);
1522         if ((val & LSI_DCNTL_STD) && (s->istat1 & LSI_ISTAT1_SRUN) == 0)
1523             lsi_execute_script(s);
1524         break;
1525     case 0x40: /* SIEN0 */
1526         s->sien0 = val;
1527         lsi_update_irq(s);
1528         break;
1529     case 0x41: /* SIEN1 */
1530         s->sien1 = val;
1531         lsi_update_irq(s);
1532         break;
1533     case 0x47: /* GPCNTL0 */
1534         break;
1535     case 0x48: /* STIME0 */
1536         s->stime0 = val;
1537         break;
1538     case 0x49: /* STIME1 */
1539         if (val & 0xf) {
1540             DPRINTF("General purpose timer not implemented\n");
1541             /* ??? Raising the interrupt immediately seems to be sufficient
1542                to keep the FreeBSD driver happy.  */
1543             lsi_script_scsi_interrupt(s, 0, LSI_SIST1_GEN);
1544         }
1545         break;
1546     case 0x4a: /* RESPID0 */
1547         s->respid0 = val;
1548         break;
1549     case 0x4b: /* RESPID1 */
1550         s->respid1 = val;
1551         break;
1552     case 0x4d: /* STEST1 */
1553         s->stest1 = val;
1554         break;
1555     case 0x4e: /* STEST2 */
1556         if (val & 1) {
1557             BADF("Low level mode not implemented\n");
1558         }
1559         s->stest2 = val;
1560         break;
1561     case 0x4f: /* STEST3 */
1562         if (val & 0x41) {
1563             BADF("SCSI FIFO test mode not implemented\n");
1564         }
1565         s->stest3 = val;
1566         break;
1567     case 0x56: /* CCNTL0 */
1568         s->ccntl0 = val;
1569         break;
1570     case 0x57: /* CCNTL1 */
1571         s->ccntl1 = val;
1572         break;
1573     CASE_SET_REG32(mmrs, 0xa0)
1574     CASE_SET_REG32(mmws, 0xa4)
1575     CASE_SET_REG32(sfs, 0xa8)
1576     CASE_SET_REG32(drs, 0xac)
1577     CASE_SET_REG32(sbms, 0xb0)
1578     CASE_SET_REG32(dmbs, 0xb4)
1579     CASE_SET_REG32(dnad64, 0xb8)
1580     CASE_SET_REG32(pmjad1, 0xc0)
1581     CASE_SET_REG32(pmjad2, 0xc4)
1582     CASE_SET_REG32(rbc, 0xc8)
1583     CASE_SET_REG32(ua, 0xcc)
1584     CASE_SET_REG32(ia, 0xd4)
1585     CASE_SET_REG32(sbc, 0xd8)
1586     CASE_SET_REG32(csbc, 0xdc)
1587     default:
1588         if (offset >= 0x5c && offset < 0xa0) {
1589             int n;
1590             int shift;
1591             n = (offset - 0x58) >> 2;
1592             shift = (offset & 3) * 8;
1593             s->scratch[n] &= ~(0xff << shift);
1594             s->scratch[n] |= (val & 0xff) << shift;
1595         } else {
1596             BADF("Unhandled writeb 0x%x = 0x%x\n", offset, val);
1597         }
1598     }
1599 #undef CASE_SET_REG32
1600 }
1601
1602 static void lsi_mmio_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1603 {
1604     LSIState *s = (LSIState *)opaque;
1605
1606     lsi_reg_writeb(s, addr & 0xff, val);
1607 }
1608
1609 static void lsi_mmio_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1610 {
1611     LSIState *s = (LSIState *)opaque;
1612
1613     addr &= 0xff;
1614     lsi_reg_writeb(s, addr, val & 0xff);
1615     lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1616 }
1617
1618 static void lsi_mmio_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1619 {
1620     LSIState *s = (LSIState *)opaque;
1621
1622     addr &= 0xff;
1623     lsi_reg_writeb(s, addr, val & 0xff);
1624     lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1625     lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff);
1626     lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
1627 }
1628
1629 static uint32_t lsi_mmio_readb(void *opaque, target_phys_addr_t addr)
1630 {
1631     LSIState *s = (LSIState *)opaque;
1632
1633     return lsi_reg_readb(s, addr & 0xff);
1634 }
1635
1636 static uint32_t lsi_mmio_readw(void *opaque, target_phys_addr_t addr)
1637 {
1638     LSIState *s = (LSIState *)opaque;
1639     uint32_t val;
1640
1641     addr &= 0xff;
1642     val = lsi_reg_readb(s, addr);
1643     val |= lsi_reg_readb(s, addr + 1) << 8;
1644     return val;
1645 }
1646
1647 static uint32_t lsi_mmio_readl(void *opaque, target_phys_addr_t addr)
1648 {
1649     LSIState *s = (LSIState *)opaque;
1650     uint32_t val;
1651     addr &= 0xff;
1652     val = lsi_reg_readb(s, addr);
1653     val |= lsi_reg_readb(s, addr + 1) << 8;
1654     val |= lsi_reg_readb(s, addr + 2) << 16;
1655     val |= lsi_reg_readb(s, addr + 3) << 24;
1656     return val;
1657 }
1658
1659 static CPUReadMemoryFunc *lsi_mmio_readfn[3] = {
1660     lsi_mmio_readb,
1661     lsi_mmio_readw,
1662     lsi_mmio_readl,
1663 };
1664
1665 static CPUWriteMemoryFunc *lsi_mmio_writefn[3] = {
1666     lsi_mmio_writeb,
1667     lsi_mmio_writew,
1668     lsi_mmio_writel,
1669 };
1670
1671 static void lsi_ram_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
1672 {
1673     LSIState *s = (LSIState *)opaque;
1674     uint32_t newval;
1675     int shift;
1676
1677     addr &= 0x1fff;
1678     newval = s->script_ram[addr >> 2];
1679     shift = (addr & 3) * 8;
1680     newval &= ~(0xff << shift);
1681     newval |= val << shift;
1682     s->script_ram[addr >> 2] = newval;
1683 }
1684
1685 static void lsi_ram_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
1686 {
1687     LSIState *s = (LSIState *)opaque;
1688     uint32_t newval;
1689
1690     addr &= 0x1fff;
1691     newval = s->script_ram[addr >> 2];
1692     if (addr & 2) {
1693         newval = (newval & 0xffff) | (val << 16);
1694     } else {
1695         newval = (newval & 0xffff0000) | val;
1696     }
1697     s->script_ram[addr >> 2] = newval;
1698 }
1699
1700
1701 static void lsi_ram_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
1702 {
1703     LSIState *s = (LSIState *)opaque;
1704
1705     addr &= 0x1fff;
1706     s->script_ram[addr >> 2] = val;
1707 }
1708
1709 static uint32_t lsi_ram_readb(void *opaque, target_phys_addr_t addr)
1710 {
1711     LSIState *s = (LSIState *)opaque;
1712     uint32_t val;
1713
1714     addr &= 0x1fff;
1715     val = s->script_ram[addr >> 2];
1716     val >>= (addr & 3) * 8;
1717     return val & 0xff;
1718 }
1719
1720 static uint32_t lsi_ram_readw(void *opaque, target_phys_addr_t addr)
1721 {
1722     LSIState *s = (LSIState *)opaque;
1723     uint32_t val;
1724
1725     addr &= 0x1fff;
1726     val = s->script_ram[addr >> 2];
1727     if (addr & 2)
1728         val >>= 16;
1729     return le16_to_cpu(val);
1730 }
1731
1732 static uint32_t lsi_ram_readl(void *opaque, target_phys_addr_t addr)
1733 {
1734     LSIState *s = (LSIState *)opaque;
1735
1736     addr &= 0x1fff;
1737     return le32_to_cpu(s->script_ram[addr >> 2]);
1738 }
1739
1740 static CPUReadMemoryFunc *lsi_ram_readfn[3] = {
1741     lsi_ram_readb,
1742     lsi_ram_readw,
1743     lsi_ram_readl,
1744 };
1745
1746 static CPUWriteMemoryFunc *lsi_ram_writefn[3] = {
1747     lsi_ram_writeb,
1748     lsi_ram_writew,
1749     lsi_ram_writel,
1750 };
1751
1752 static uint32_t lsi_io_readb(void *opaque, uint32_t addr)
1753 {
1754     LSIState *s = (LSIState *)opaque;
1755     return lsi_reg_readb(s, addr & 0xff);
1756 }
1757
1758 static uint32_t lsi_io_readw(void *opaque, uint32_t addr)
1759 {
1760     LSIState *s = (LSIState *)opaque;
1761     uint32_t val;
1762     addr &= 0xff;
1763     val = lsi_reg_readb(s, addr);
1764     val |= lsi_reg_readb(s, addr + 1) << 8;
1765     return val;
1766 }
1767
1768 static uint32_t lsi_io_readl(void *opaque, uint32_t addr)
1769 {
1770     LSIState *s = (LSIState *)opaque;
1771     uint32_t val;
1772     addr &= 0xff;
1773     val = lsi_reg_readb(s, addr);
1774     val |= lsi_reg_readb(s, addr + 1) << 8;
1775     val |= lsi_reg_readb(s, addr + 2) << 16;
1776     val |= lsi_reg_readb(s, addr + 3) << 24;
1777     return val;
1778 }
1779
1780 static void lsi_io_writeb(void *opaque, uint32_t addr, uint32_t val)
1781 {
1782     LSIState *s = (LSIState *)opaque;
1783     lsi_reg_writeb(s, addr & 0xff, val);
1784 }
1785
1786 static void lsi_io_writew(void *opaque, uint32_t addr, uint32_t val)
1787 {
1788     LSIState *s = (LSIState *)opaque;
1789     addr &= 0xff;
1790     lsi_reg_writeb(s, addr, val & 0xff);
1791     lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1792 }
1793
1794 static void lsi_io_writel(void *opaque, uint32_t addr, uint32_t val)
1795 {
1796     LSIState *s = (LSIState *)opaque;
1797     addr &= 0xff;
1798     lsi_reg_writeb(s, addr, val & 0xff);
1799     lsi_reg_writeb(s, addr + 1, (val >> 8) & 0xff);
1800     lsi_reg_writeb(s, addr + 2, (val >> 16) & 0xff);
1801     lsi_reg_writeb(s, addr + 3, (val >> 24) & 0xff);
1802 }
1803
1804 static void lsi_io_mapfunc(PCIDevice *pci_dev, int region_num,
1805                            uint32_t addr, uint32_t size, int type)
1806 {
1807     LSIState *s = (LSIState *)pci_dev;
1808
1809     DPRINTF("Mapping IO at %08x\n", addr);
1810
1811     register_ioport_write(addr, 256, 1, lsi_io_writeb, s);
1812     register_ioport_read(addr, 256, 1, lsi_io_readb, s);
1813     register_ioport_write(addr, 256, 2, lsi_io_writew, s);
1814     register_ioport_read(addr, 256, 2, lsi_io_readw, s);
1815     register_ioport_write(addr, 256, 4, lsi_io_writel, s);
1816     register_ioport_read(addr, 256, 4, lsi_io_readl, s);
1817 }
1818
1819 static void lsi_ram_mapfunc(PCIDevice *pci_dev, int region_num,
1820                             uint32_t addr, uint32_t size, int type)
1821 {
1822     LSIState *s = (LSIState *)pci_dev;
1823
1824     DPRINTF("Mapping ram at %08x\n", addr);
1825     s->script_ram_base = addr;
1826     cpu_register_physical_memory(addr + 0, 0x2000, s->ram_io_addr);
1827 }
1828
1829 static void lsi_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
1830                              uint32_t addr, uint32_t size, int type)
1831 {
1832     LSIState *s = (LSIState *)pci_dev;
1833
1834     DPRINTF("Mapping registers at %08x\n", addr);
1835     cpu_register_physical_memory(addr + 0, 0x400, s->mmio_io_addr);
1836 }
1837
1838 void lsi_scsi_attach(void *opaque, BlockDriverState *bd, int id)
1839 {
1840     LSIState *s = (LSIState *)opaque;
1841
1842     if (id < 0) {
1843         for (id = 0; id < LSI_MAX_DEVS; id++) {
1844             if (s->scsi_dev[id] == NULL)
1845                 break;
1846         }
1847     }
1848     if (id >= LSI_MAX_DEVS) {
1849         BADF("Bad Device ID %d\n", id);
1850         return;
1851     }
1852     if (s->scsi_dev[id]) {
1853         DPRINTF("Destroying device %d\n", id);
1854         s->scsi_dev[id]->destroy(s->scsi_dev[id]);
1855     }
1856     DPRINTF("Attaching block device %d\n", id);
1857     s->scsi_dev[id] = scsi_generic_init(bd, 1, lsi_command_complete, s);
1858     if (s->scsi_dev[id] == NULL)
1859         s->scsi_dev[id] = scsi_disk_init(bd, 1, lsi_command_complete, s);
1860     bd->devfn = s->pci_dev.devfn;
1861 }
1862
1863 int lsi_scsi_uninit(PCIDevice *d)
1864 {
1865     LSIState *s = (LSIState *) d;
1866
1867     cpu_unregister_io_memory(s->mmio_io_addr);
1868     cpu_unregister_io_memory(s->ram_io_addr);
1869
1870     qemu_free(s->queue);
1871
1872     return 0;
1873 }
1874
1875 void *lsi_scsi_init(PCIBus *bus, int devfn)
1876 {
1877     LSIState *s;
1878
1879     s = (LSIState *)pci_register_device(bus, "LSI53C895A SCSI HBA",
1880                                         sizeof(*s), devfn, NULL, NULL);
1881     if (s == NULL) {
1882         fprintf(stderr, "lsi-scsi: Failed to register PCI device\n");
1883         return NULL;
1884     }
1885
1886     s->pci_dev.config[0x00] = 0x00;
1887     s->pci_dev.config[0x01] = 0x10;
1888     s->pci_dev.config[0x02] = 0x12;
1889     s->pci_dev.config[0x03] = 0x00;
1890     s->pci_dev.config[0x0b] = 0x01;
1891     s->pci_dev.config[0x3d] = 0x01; /* interrupt pin 1 */
1892
1893     s->mmio_io_addr = cpu_register_io_memory(0, lsi_mmio_readfn,
1894                                              lsi_mmio_writefn, s);
1895     s->ram_io_addr = cpu_register_io_memory(0, lsi_ram_readfn,
1896                                             lsi_ram_writefn, s);
1897
1898     pci_register_io_region((struct PCIDevice *)s, 0, 256,
1899                            PCI_ADDRESS_SPACE_IO, lsi_io_mapfunc);
1900     pci_register_io_region((struct PCIDevice *)s, 1, 0x400,
1901                            PCI_ADDRESS_SPACE_MEM, lsi_mmio_mapfunc);
1902     pci_register_io_region((struct PCIDevice *)s, 2, 0x2000,
1903                            PCI_ADDRESS_SPACE_MEM, lsi_ram_mapfunc);
1904     s->queue = qemu_malloc(sizeof(lsi_queue));
1905     s->queue_len = 1;
1906     s->active_commands = 0;
1907     s->pci_dev.unregister = lsi_scsi_uninit;
1908
1909     lsi_soft_reset(s);
1910
1911     return s;
1912 }
1913