hw/ioapic.c

   1 /*
   2  *  ioapic.c IOAPIC emulation logic
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  *  Split the ioapic logic from apic.c
   7  *  Xiantao Zhang <xiantao.zhang@intel.com>
   8  *
   9  * This library is free software; you can redistribute it and/or
  10  * modify it under the terms of the GNU Lesser General Public
  11  * License as published by the Free Software Foundation; either
  12  * version 2 of the License, or (at your option) any later version.
  13  *
  14  * This library is distributed in the hope that it will be useful,
  15  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  17  * Lesser General Public License for more details.
  18  *
  19  * You should have received a copy of the GNU Lesser General Public
  20  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  21  */
  22
  23 #include "hw.h"
  24 #include "pc.h"
  25 #include "apic.h"
  26 #include "sysemu.h"
  27 #include "apic.h"
  28 #include "qemu-timer.h"
  29 #include "host-utils.h"
  30
  31 #include "kvm.h"
  32
  33 //#define DEBUG_IOAPIC
  34
  35 #define IOAPIC_NUM_PINS                 0x18
  36 #define IOAPIC_DEFAULT_BASE_ADDRESS  0xfec00000
  37 #define IOAPIC_LVT_MASKED               (1<<16)
  38
  39 #define IOAPIC_TRIGGER_EDGE             0
  40 #define IOAPIC_TRIGGER_LEVEL            1
  41
  42 /*io{apic,sapic} delivery mode*/
  43 #define IOAPIC_DM_FIXED                 0x0
  44 #define IOAPIC_DM_LOWEST_PRIORITY       0x1
  45 #define IOAPIC_DM_PMI                   0x2
  46 #define IOAPIC_DM_NMI                   0x4
  47 #define IOAPIC_DM_INIT                  0x5
  48 #define IOAPIC_DM_SIPI                  0x5
  49 #define IOAPIC_DM_EXTINT                0x7
  50
  51 struct IOAPICState {
  52     uint8_t id;
  53     uint8_t ioregsel;
  54     uint64_t base_address;
  55
  56     uint32_t irr;
  57     uint64_t ioredtbl[IOAPIC_NUM_PINS];
  58 };
  59
  60 static void ioapic_service(IOAPICState *s)
  61 {
  62     uint8_t i;
  63     uint8_t trig_mode;
  64     uint8_t vector;
  65     uint8_t delivery_mode;
  66     uint32_t mask;
  67     uint64_t entry;
  68     uint8_t dest;
  69     uint8_t dest_mode;
  70     uint8_t polarity;
  71
  72     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
  73         mask = 1 << i;
  74         if (s->irr & mask) {
  75             entry = s->ioredtbl[i];
  76             if (!(entry & IOAPIC_LVT_MASKED)) {
  77                 trig_mode = ((entry >> 15) & 1);
  78                 dest = entry >> 56;
  79                 dest_mode = (entry >> 11) & 1;
  80                 delivery_mode = (entry >> 8) & 7;
  81                 polarity = (entry >> 13) & 1;
  82                 if (trig_mode == IOAPIC_TRIGGER_EDGE)
  83                     s->irr &= ~mask;
  84                 if (delivery_mode == IOAPIC_DM_EXTINT)
  85                     vector = pic_read_irq(isa_pic);
  86                 else
  87                     vector = entry & 0xff;
  88
  89                 apic_deliver_irq(dest, dest_mode, delivery_mode,
  90                                  vector, polarity, trig_mode);
  91             }
  92         }
  93     }
  94 }
  95
  96 void ioapic_set_irq(void *opaque, int vector, int level)
  97 {
  98     IOAPICState *s = opaque;
  99
 100     /* ISA IRQs map to GSI 1-1 except for IRQ0 which maps
 101      * to GSI 2.  GSI maps to ioapic 1-1.  This is not
 102      * the cleanest way of doing it but it should work. */
 103
 104     if (vector == 0 && irq0override) {
 105         vector = 2;
 106     }
 107
 108     if (vector >= 0 && vector < IOAPIC_NUM_PINS) {
 109         uint32_t mask = 1 << vector;
 110         uint64_t entry = s->ioredtbl[vector];
 111
 112         if ((entry >> 15) & 1) {
 113             /* level triggered */
 114             if (level) {
 115                 s->irr |= mask;
 116                 ioapic_service(s);
 117             } else {
 118                 s->irr &= ~mask;
 119             }
 120         } else {
 121             /* edge triggered */
 122             if (level) {
 123                 s->irr |= mask;
 124                 ioapic_service(s);
 125             }
 126         }
 127     }
 128 }
 129
 130 static uint32_t ioapic_mem_readl(void *opaque, target_phys_addr_t addr)
 131 {
 132     IOAPICState *s = opaque;
 133     int index;
 134     uint32_t val = 0;
 135
 136     addr &= 0xff;
 137     if (addr == 0x00) {
 138         val = s->ioregsel;
 139     } else if (addr == 0x10) {
 140         switch (s->ioregsel) {
 141             case 0x00:
 142                 val = s->id << 24;
 143                 break;
 144             case 0x01:
 145                 val = 0x11 | ((IOAPIC_NUM_PINS - 1) << 16); /* version 0x11 */
 146                 break;
 147             case 0x02:
 148                 val = 0;
 149                 break;
 150             default:
 151                 index = (s->ioregsel - 0x10) >> 1;
 152                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
 153                     if (s->ioregsel & 1)
 154                         val = s->ioredtbl[index] >> 32;
 155                     else
 156                         val = s->ioredtbl[index] & 0xffffffff;
 157                 }
 158         }
 159 #ifdef DEBUG_IOAPIC
 160         printf("I/O APIC read: %08x = %08x\n", s->ioregsel, val);
 161 #endif
 162     }
 163     return val;
 164 }
 165
 166 static void ioapic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 167 {
 168     IOAPICState *s = opaque;
 169     int index;
 170
 171     addr &= 0xff;
 172     if (addr == 0x00)  {
 173         s->ioregsel = val;
 174         return;
 175     } else if (addr == 0x10) {
 176 #ifdef DEBUG_IOAPIC
 177         printf("I/O APIC write: %08x = %08x\n", s->ioregsel, val);
 178 #endif
 179         switch (s->ioregsel) {
 180             case 0x00:
 181                 s->id = (val >> 24) & 0xff;
 182                 return;
 183             case 0x01:
 184             case 0x02:
 185                 return;
 186             default:
 187                 index = (s->ioregsel - 0x10) >> 1;
 188                 if (index >= 0 && index < IOAPIC_NUM_PINS) {
 189                     if (s->ioregsel & 1) {
 190                         s->ioredtbl[index] &= 0xffffffff;
 191                         s->ioredtbl[index] |= (uint64_t)val << 32;
 192                     } else {
 193                         s->ioredtbl[index] &= ~0xffffffffULL;
 194                         s->ioredtbl[index] |= val;
 195                     }
 196                     ioapic_service(s);
 197                 }
 198         }
 199     }
 200 }
 201
 202 static void kvm_kernel_ioapic_save_to_user(IOAPICState *s)
 203 {
 204 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
 205     struct kvm_irqchip chip;
 206     struct kvm_ioapic_state *kioapic;
 207     int i;
 208
 209     chip.chip_id = KVM_IRQCHIP_IOAPIC;
 210     kvm_get_irqchip(kvm_context, &chip);
 211     kioapic = &chip.chip.ioapic;
 212
 213     s->id = kioapic->id;
 214     s->ioregsel = kioapic->ioregsel;
 215     s->base_address = kioapic->base_address;
 216     s->irr = kioapic->irr;
 217     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 218         s->ioredtbl[i] = kioapic->redirtbl[i].bits;
 219     }
 220 #endif
 221 }
 222
 223 static void kvm_kernel_ioapic_load_from_user(IOAPICState *s)
 224 {
 225 #if defined(KVM_CAP_IRQCHIP) && defined(TARGET_I386)
 226     struct kvm_irqchip chip;
 227     struct kvm_ioapic_state *kioapic;
 228     int i;
 229
 230     chip.chip_id = KVM_IRQCHIP_IOAPIC;
 231     kioapic = &chip.chip.ioapic;
 232
 233     kioapic->id = s->id;
 234     kioapic->ioregsel = s->ioregsel;
 235     kioapic->base_address = s->base_address;
 236     kioapic->irr = s->irr;
 237     for (i = 0; i < IOAPIC_NUM_PINS; i++) {
 238         kioapic->redirtbl[i].bits = s->ioredtbl[i];
 239     }
 240
 241     kvm_set_irqchip(kvm_context, &chip);
 242 #endif
 243 }
 244
 245 static void ioapic_pre_save(void *opaque)
 246 {
 247     IOAPICState *s = (void *)opaque;
 248
 249     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 250         kvm_kernel_ioapic_save_to_user(s);
 251     }
 252 }
 253
 254 static int ioapic_pre_load(void *opaque)
 255 {
 256     IOAPICState *s = opaque;
 257
 258     /* in case we are doing version 1, we just set these to sane values */
 259     s->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
 260     s->irr = 0;
 261     return 0;
 262 }
 263
 264 static int ioapic_post_load(void *opaque, int version_id)
 265 {
 266     IOAPICState *s = opaque;
 267
 268     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 269         kvm_kernel_ioapic_load_from_user(s);
 270     }
 271     return 0;
 272 }
 273
 274 static const VMStateDescription vmstate_ioapic = {
 275     .name = "ioapic",
 276     .version_id = 2,
 277     .minimum_version_id = 1,
 278     .minimum_version_id_old = 1,
 279     .pre_load = ioapic_pre_load,
 280     .post_load = ioapic_post_load,
 281     .pre_save = ioapic_pre_save,
 282     .fields      = (VMStateField []) {
 283         VMSTATE_UINT8(id, IOAPICState),
 284         VMSTATE_UINT8(ioregsel, IOAPICState),
 285         VMSTATE_UINT64_V(base_address, IOAPICState, 2),
 286         VMSTATE_UINT32_V(irr, IOAPICState, 2),
 287         VMSTATE_UINT64_ARRAY(ioredtbl, IOAPICState, IOAPIC_NUM_PINS),
 288         VMSTATE_END_OF_LIST()
 289     }
 290 };
 291
 292 static void ioapic_reset(void *opaque)
 293 {
 294     IOAPICState *s = opaque;
 295     int i;
 296
 297     memset(s, 0, sizeof(*s));
 298     s->base_address = IOAPIC_DEFAULT_BASE_ADDRESS;
 299     for(i = 0; i < IOAPIC_NUM_PINS; i++)
 300         s->ioredtbl[i] = 1 << 16; /* mask LVT */
 301 #ifdef KVM_CAP_IRQCHIP
 302     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 303         kvm_kernel_ioapic_load_from_user(s);
 304     }
 305 #endif
 306 }
 307
 308 static CPUReadMemoryFunc * const ioapic_mem_read[3] = {
 309     ioapic_mem_readl,
 310     ioapic_mem_readl,
 311     ioapic_mem_readl,
 312 };
 313
 314 static CPUWriteMemoryFunc * const ioapic_mem_write[3] = {
 315     ioapic_mem_writel,
 316     ioapic_mem_writel,
 317     ioapic_mem_writel,
 318 };
 319
 320 qemu_irq *ioapic_init(void)
 321 {
 322     IOAPICState *s;
 323     qemu_irq *irq;
 324     int io_memory;
 325
 326     s = qemu_mallocz(sizeof(IOAPICState));
 327     ioapic_reset(s);
 328
 329     io_memory = cpu_register_io_memory(ioapic_mem_read,
 330                                        ioapic_mem_write, s);
 331     cpu_register_physical_memory(0xfec00000, 0x1000, io_memory);
 332
 333     vmstate_register(0, &vmstate_ioapic, s);
 334     qemu_register_reset(ioapic_reset, s);
 335     irq = qemu_allocate_irqs(ioapic_set_irq, s, IOAPIC_NUM_PINS);
 336
 337     return irq;
 338 }