2 * High Precisition Event Timer emulation
4 * Copyright (c) 2007 Alexander Graf
5 * Copyright (c) 2008 IBM Corporation
7 * Authors: Beth Kon <bkon@us.ibm.com>
9 * This library is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU Lesser General Public
11 * License as published by the Free Software Foundation; either
12 * version 2 of the License, or (at your option) any later version.
14 * This library is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
17 * Lesser General Public License for more details.
19 * You should have received a copy of the GNU Lesser General Public
20 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 * *****************************************************************
24 * This driver attempts to emulate an HPET device in software.
30 #include "qemu-timer.h"
31 #include "hpet_emul.h"
35 #define DPRINTF printf
40 static HPETState
*hpet_statep
;
42 uint32_t hpet_in_legacy_mode(void)
45 return hpet_statep
->config
& HPET_CFG_LEGACY
;
50 static uint32_t timer_int_route(struct HPETTimer
*timer
)
53 route
= (timer
->config
& HPET_TN_INT_ROUTE_MASK
) >> HPET_TN_INT_ROUTE_SHIFT
;
57 static uint32_t hpet_enabled(void)
59 return hpet_statep
->config
& HPET_CFG_ENABLE
;
62 static uint32_t timer_is_periodic(HPETTimer
*t
)
64 return t
->config
& HPET_TN_PERIODIC
;
67 static uint32_t timer_enabled(HPETTimer
*t
)
69 return t
->config
& HPET_TN_ENABLE
;
72 static uint32_t hpet_time_after(uint64_t a
, uint64_t b
)
74 return ((int32_t)(b
) - (int32_t)(a
) < 0);
77 static uint32_t hpet_time_after64(uint64_t a
, uint64_t b
)
79 return ((int64_t)(b
) - (int64_t)(a
) < 0);
82 static uint64_t ticks_to_ns(uint64_t value
)
84 return (muldiv64(value
, HPET_CLK_PERIOD
, FS_PER_NS
));
87 static uint64_t ns_to_ticks(uint64_t value
)
89 return (muldiv64(value
, FS_PER_NS
, HPET_CLK_PERIOD
));
92 static uint64_t hpet_fixup_reg(uint64_t new, uint64_t old
, uint64_t mask
)
99 static int activating_bit(uint64_t old
, uint64_t new, uint64_t mask
)
101 return (!(old
& mask
) && (new & mask
));
104 static int deactivating_bit(uint64_t old
, uint64_t new, uint64_t mask
)
106 return ((old
& mask
) && !(new & mask
));
109 static uint64_t hpet_get_ticks(void)
112 ticks
= ns_to_ticks(qemu_get_clock(vm_clock
) + hpet_statep
->hpet_offset
);
117 * calculate diff between comparator value and current ticks
119 static inline uint64_t hpet_calculate_diff(HPETTimer
*t
, uint64_t current
)
122 if (t
->config
& HPET_TN_32BIT
) {
124 cmp
= (uint32_t)t
->cmp
;
125 diff
= cmp
- (uint32_t)current
;
126 diff
= (int32_t)diff
> 0 ? diff
: (uint32_t)0;
127 return (uint64_t)diff
;
131 diff
= cmp
- current
;
132 diff
= (int64_t)diff
> 0 ? diff
: (uint64_t)0;
137 static void update_irq(struct HPETTimer
*timer
)
142 if (timer
->tn
<= 1 && hpet_in_legacy_mode()) {
143 /* if LegacyReplacementRoute bit is set, HPET specification requires
144 * timer0 be routed to IRQ0 in NON-APIC or IRQ2 in the I/O APIC,
145 * timer1 be routed to IRQ8 in NON-APIC or IRQ8 in the I/O APIC.
147 if (timer
->tn
== 0) {
148 irq
=timer
->state
->irqs
[0];
150 irq
=timer
->state
->irqs
[8];
152 route
=timer_int_route(timer
);
153 irq
=timer
->state
->irqs
[route
];
155 if (timer_enabled(timer
) && hpet_enabled()) {
160 static void hpet_pre_save(void *opaque
)
162 HPETState
*s
= opaque
;
163 /* save current counter value */
164 s
->hpet_counter
= hpet_get_ticks();
167 static int hpet_post_load(void *opaque
, int version_id
)
169 HPETState
*s
= opaque
;
171 /* Recalculate the offset between the main counter and guest time */
172 s
->hpet_offset
= ticks_to_ns(s
->hpet_counter
) - qemu_get_clock(vm_clock
);
174 if (hpet_in_legacy_mode()) {
181 static const VMStateDescription vmstate_hpet_timer
= {
182 .name
= "hpet_timer",
184 .minimum_version_id
= 1,
185 .minimum_version_id_old
= 1,
186 .fields
= (VMStateField
[]) {
187 VMSTATE_UINT8(tn
, HPETTimer
),
188 VMSTATE_UINT64(config
, HPETTimer
),
189 VMSTATE_UINT64(cmp
, HPETTimer
),
190 VMSTATE_UINT64(fsb
, HPETTimer
),
191 VMSTATE_UINT64(period
, HPETTimer
),
192 VMSTATE_UINT8(wrap_flag
, HPETTimer
),
193 VMSTATE_TIMER(qemu_timer
, HPETTimer
),
194 VMSTATE_END_OF_LIST()
198 static const VMStateDescription vmstate_hpet
= {
201 .minimum_version_id
= 1,
202 .minimum_version_id_old
= 1,
203 .pre_save
= hpet_pre_save
,
204 .post_load
= hpet_post_load
,
205 .fields
= (VMStateField
[]) {
206 VMSTATE_UINT64(config
, HPETState
),
207 VMSTATE_UINT64(isr
, HPETState
),
208 VMSTATE_UINT64(hpet_counter
, HPETState
),
209 VMSTATE_STRUCT_ARRAY(timer
, HPETState
, HPET_NUM_TIMERS
, 0,
210 vmstate_hpet_timer
, HPETTimer
),
211 VMSTATE_END_OF_LIST()
216 * timer expiration callback
218 static void hpet_timer(void *opaque
)
220 HPETTimer
*t
= (HPETTimer
*)opaque
;
223 uint64_t period
= t
->period
;
224 uint64_t cur_tick
= hpet_get_ticks();
226 if (timer_is_periodic(t
) && period
!= 0) {
227 if (t
->config
& HPET_TN_32BIT
) {
228 while (hpet_time_after(cur_tick
, t
->cmp
))
229 t
->cmp
= (uint32_t)(t
->cmp
+ t
->period
);
231 while (hpet_time_after64(cur_tick
, t
->cmp
))
234 diff
= hpet_calculate_diff(t
, cur_tick
);
235 qemu_mod_timer(t
->qemu_timer
, qemu_get_clock(vm_clock
)
236 + (int64_t)ticks_to_ns(diff
));
237 } else if (t
->config
& HPET_TN_32BIT
&& !timer_is_periodic(t
)) {
239 diff
= hpet_calculate_diff(t
, cur_tick
);
240 qemu_mod_timer(t
->qemu_timer
, qemu_get_clock(vm_clock
)
241 + (int64_t)ticks_to_ns(diff
));
248 static void hpet_set_timer(HPETTimer
*t
)
251 uint32_t wrap_diff
; /* how many ticks until we wrap? */
252 uint64_t cur_tick
= hpet_get_ticks();
254 /* whenever new timer is being set up, make sure wrap_flag is 0 */
256 diff
= hpet_calculate_diff(t
, cur_tick
);
258 /* hpet spec says in one-shot 32-bit mode, generate an interrupt when
259 * counter wraps in addition to an interrupt with comparator match.
261 if (t
->config
& HPET_TN_32BIT
&& !timer_is_periodic(t
)) {
262 wrap_diff
= 0xffffffff - (uint32_t)cur_tick
;
263 if (wrap_diff
< (uint32_t)diff
) {
268 qemu_mod_timer(t
->qemu_timer
, qemu_get_clock(vm_clock
)
269 + (int64_t)ticks_to_ns(diff
));
272 static void hpet_del_timer(HPETTimer
*t
)
274 qemu_del_timer(t
->qemu_timer
);
278 static uint32_t hpet_ram_readb(void *opaque
, target_phys_addr_t addr
)
280 printf("qemu: hpet_read b at %" PRIx64
"\n", addr
);
284 static uint32_t hpet_ram_readw(void *opaque
, target_phys_addr_t addr
)
286 printf("qemu: hpet_read w at %" PRIx64
"\n", addr
);
291 static uint32_t hpet_ram_readl(void *opaque
, target_phys_addr_t addr
)
293 HPETState
*s
= (HPETState
*)opaque
;
294 uint64_t cur_tick
, index
;
296 DPRINTF("qemu: Enter hpet_ram_readl at %" PRIx64
"\n", addr
);
298 /*address range of all TN regs*/
299 if (index
>= 0x100 && index
<= 0x3ff) {
300 uint8_t timer_id
= (addr
- 0x100) / 0x20;
301 if (timer_id
> HPET_NUM_TIMERS
- 1) {
302 printf("qemu: timer id out of range\n");
305 HPETTimer
*timer
= &s
->timer
[timer_id
];
307 switch ((addr
- 0x100) % 0x20) {
309 return timer
->config
;
310 case HPET_TN_CFG
+ 4: // Interrupt capabilities
311 return timer
->config
>> 32;
312 case HPET_TN_CMP
: // comparator register
314 case HPET_TN_CMP
+ 4:
315 return timer
->cmp
>> 32;
317 return timer
->fsb
>> 32;
319 DPRINTF("qemu: invalid hpet_ram_readl\n");
325 return s
->capability
;
327 return s
->capability
>> 32;
331 DPRINTF("qemu: invalid HPET_CFG + 4 hpet_ram_readl \n");
335 cur_tick
= hpet_get_ticks();
337 cur_tick
= s
->hpet_counter
;
338 DPRINTF("qemu: reading counter = %" PRIx64
"\n", cur_tick
);
340 case HPET_COUNTER
+ 4:
342 cur_tick
= hpet_get_ticks();
344 cur_tick
= s
->hpet_counter
;
345 DPRINTF("qemu: reading counter + 4 = %" PRIx64
"\n", cur_tick
);
346 return cur_tick
>> 32;
350 DPRINTF("qemu: invalid hpet_ram_readl\n");
358 static void hpet_ram_writeb(void *opaque
, target_phys_addr_t addr
,
361 printf("qemu: invalid hpet_write b at %" PRIx64
" = %#x\n",
365 static void hpet_ram_writew(void *opaque
, target_phys_addr_t addr
,
368 printf("qemu: invalid hpet_write w at %" PRIx64
" = %#x\n",
373 static void hpet_ram_writel(void *opaque
, target_phys_addr_t addr
,
377 HPETState
*s
= (HPETState
*)opaque
;
378 uint64_t old_val
, new_val
, val
, index
;
380 DPRINTF("qemu: Enter hpet_ram_writel at %" PRIx64
" = %#x\n", addr
, value
);
382 old_val
= hpet_ram_readl(opaque
, addr
);
385 /*address range of all TN regs*/
386 if (index
>= 0x100 && index
<= 0x3ff) {
387 uint8_t timer_id
= (addr
- 0x100) / 0x20;
388 DPRINTF("qemu: hpet_ram_writel timer_id = %#x \n", timer_id
);
389 HPETTimer
*timer
= &s
->timer
[timer_id
];
391 switch ((addr
- 0x100) % 0x20) {
393 DPRINTF("qemu: hpet_ram_writel HPET_TN_CFG\n");
394 val
= hpet_fixup_reg(new_val
, old_val
, HPET_TN_CFG_WRITE_MASK
);
395 timer
->config
= (timer
->config
& 0xffffffff00000000ULL
) | val
;
396 if (new_val
& HPET_TN_32BIT
) {
397 timer
->cmp
= (uint32_t)timer
->cmp
;
398 timer
->period
= (uint32_t)timer
->period
;
400 if (new_val
& HPET_TIMER_TYPE_LEVEL
) {
401 printf("qemu: level-triggered hpet not supported\n");
406 case HPET_TN_CFG
+ 4: // Interrupt capabilities
407 DPRINTF("qemu: invalid HPET_TN_CFG+4 write\n");
409 case HPET_TN_CMP
: // comparator register
410 DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP \n");
411 if (timer
->config
& HPET_TN_32BIT
)
412 new_val
= (uint32_t)new_val
;
413 if (!timer_is_periodic(timer
) ||
414 (timer
->config
& HPET_TN_SETVAL
))
415 timer
->cmp
= (timer
->cmp
& 0xffffffff00000000ULL
)
417 if (timer_is_periodic(timer
)) {
419 * FIXME: Clamp period to reasonable min value?
420 * Clamp period to reasonable max value
422 new_val
&= (timer
->config
& HPET_TN_32BIT
? ~0u : ~0ull) >> 1;
423 timer
->period
= (timer
->period
& 0xffffffff00000000ULL
)
426 timer
->config
&= ~HPET_TN_SETVAL
;
428 hpet_set_timer(timer
);
430 case HPET_TN_CMP
+ 4: // comparator register high order
431 DPRINTF("qemu: hpet_ram_writel HPET_TN_CMP + 4\n");
432 if (!timer_is_periodic(timer
) ||
433 (timer
->config
& HPET_TN_SETVAL
))
434 timer
->cmp
= (timer
->cmp
& 0xffffffffULL
)
438 * FIXME: Clamp period to reasonable min value?
439 * Clamp period to reasonable max value
441 new_val
&= (timer
->config
442 & HPET_TN_32BIT
? ~0u : ~0ull) >> 1;
443 timer
->period
= (timer
->period
& 0xffffffffULL
)
446 timer
->config
&= ~HPET_TN_SETVAL
;
448 hpet_set_timer(timer
);
450 case HPET_TN_ROUTE
+ 4:
451 DPRINTF("qemu: hpet_ram_writel HPET_TN_ROUTE + 4\n");
454 DPRINTF("qemu: invalid hpet_ram_writel\n");
463 val
= hpet_fixup_reg(new_val
, old_val
, HPET_CFG_WRITE_MASK
);
464 s
->config
= (s
->config
& 0xffffffff00000000ULL
) | val
;
465 if (activating_bit(old_val
, new_val
, HPET_CFG_ENABLE
)) {
466 /* Enable main counter and interrupt generation. */
467 s
->hpet_offset
= ticks_to_ns(s
->hpet_counter
)
468 - qemu_get_clock(vm_clock
);
469 for (i
= 0; i
< HPET_NUM_TIMERS
; i
++)
470 if ((&s
->timer
[i
])->cmp
!= ~0ULL)
471 hpet_set_timer(&s
->timer
[i
]);
473 else if (deactivating_bit(old_val
, new_val
, HPET_CFG_ENABLE
)) {
474 /* Halt main counter and disable interrupt generation. */
475 s
->hpet_counter
= hpet_get_ticks();
476 for (i
= 0; i
< HPET_NUM_TIMERS
; i
++)
477 hpet_del_timer(&s
->timer
[i
]);
479 /* i8254 and RTC are disabled when HPET is in legacy mode */
480 if (activating_bit(old_val
, new_val
, HPET_CFG_LEGACY
)) {
482 DPRINTF("qemu: hpet disabled pit\n");
483 } else if (deactivating_bit(old_val
, new_val
, HPET_CFG_LEGACY
)) {
485 DPRINTF("qemu: hpet enabled pit\n");
489 DPRINTF("qemu: invalid HPET_CFG+4 write \n");
492 /* FIXME: need to handle level-triggered interrupts */
496 printf("qemu: Writing counter while HPET enabled!\n");
497 s
->hpet_counter
= (s
->hpet_counter
& 0xffffffff00000000ULL
)
499 DPRINTF("qemu: HPET counter written. ctr = %#x -> %" PRIx64
"\n",
500 value
, s
->hpet_counter
);
502 case HPET_COUNTER
+ 4:
504 printf("qemu: Writing counter while HPET enabled!\n");
505 s
->hpet_counter
= (s
->hpet_counter
& 0xffffffffULL
)
506 | (((uint64_t)value
) << 32);
507 DPRINTF("qemu: HPET counter + 4 written. ctr = %#x -> %" PRIx64
"\n",
508 value
, s
->hpet_counter
);
511 DPRINTF("qemu: invalid hpet_ram_writel\n");
517 static CPUReadMemoryFunc
* const hpet_ram_read
[] = {
528 static CPUWriteMemoryFunc
* const hpet_ram_write
[] = {
539 static void hpet_reset(void *opaque
) {
540 HPETState
*s
= opaque
;
542 static int count
= 0;
544 for (i
=0; i
<HPET_NUM_TIMERS
; i
++) {
545 HPETTimer
*timer
= &s
->timer
[i
];
546 hpet_del_timer(timer
);
549 timer
->config
= HPET_TN_PERIODIC_CAP
| HPET_TN_SIZE_CAP
;
550 /* advertise availability of ioapic inti2 */
551 timer
->config
|= 0x00000004ULL
<< 32;
553 timer
->period
= 0ULL;
554 timer
->wrap_flag
= 0;
557 s
->hpet_counter
= 0ULL;
558 s
->hpet_offset
= 0ULL;
559 /* 64-bit main counter; 3 timers supported; LegacyReplacementRoute. */
560 s
->capability
= 0x8086a201ULL
;
561 s
->capability
|= ((HPET_CLK_PERIOD
) << 32);
564 /* we don't enable pit when hpet_reset is first called (by hpet_init)
565 * because hpet is taking over for pit here. On subsequent invocations,
566 * hpet_reset is called due to system reset. At this point control must
567 * be returned to pit until SW reenables hpet.
574 void hpet_init(qemu_irq
*irq
) {
578 DPRINTF ("hpet_init\n");
580 s
= qemu_mallocz(sizeof(HPETState
));
583 for (i
=0; i
<HPET_NUM_TIMERS
; i
++) {
584 HPETTimer
*timer
= &s
->timer
[i
];
585 timer
->qemu_timer
= qemu_new_timer(vm_clock
, hpet_timer
, timer
);
587 vmstate_register(-1, &vmstate_hpet
, s
);
588 qemu_register_reset(hpet_reset
, s
);
590 iomemtype
= cpu_register_io_memory(hpet_ram_read
,
592 cpu_register_physical_memory(HPET_BASE
, 0x400, iomemtype
);