hw/acpi.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  */
  18 #include "hw.h"
  19 #include "pc.h"
  20 #include "apm.h"
  21 #include "pm_smbus.h"
  22 #include "pci.h"
  23 #include "qemu-timer.h"
  24 #include "sysemu.h"
  25 #include "i2c.h"
  26 #include "smbus.h"
  27 #include "kvm.h"
  28 #include "qemu-kvm.h"
  29 #include "string.h"
  30
  31 //#define DEBUG
  32
  33 /* i82731AB (PIIX4) compatible power management function */
  34 #define PM_FREQ 3579545
  35
  36 #define ACPI_DBG_IO_ADDR  0xb044
  37
  38 typedef struct PIIX4PMState {
  39     PCIDevice dev;
  40     uint16_t pmsts;
  41     uint16_t pmen;
  42     uint16_t pmcntrl;
  43
  44     APMState apm;
  45
  46     QEMUTimer *tmr_timer;
  47     int64_t tmr_overflow_time;
  48
  49     PMSMBus smb;
  50
  51     qemu_irq irq;
  52     qemu_irq cmos_s3;
  53     qemu_irq smi_irq;
  54     int kvm_enabled;
  55 } PIIX4PMState;
  56
  57 #define RSM_STS (1 << 15)
  58 #define PWRBTN_STS (1 << 8)
  59 #define RTC_EN (1 << 10)
  60 #define PWRBTN_EN (1 << 8)
  61 #define GBL_EN (1 << 5)
  62 #define TMROF_EN (1 << 0)
  63
  64 #define SCI_EN (1 << 0)
  65
  66 #define SUS_EN (1 << 13)
  67
  68 #define ACPI_ENABLE 0xf1
  69 #define ACPI_DISABLE 0xf0
  70
  71 static PIIX4PMState *pm_state;
  72
  73 static uint32_t get_pmtmr(PIIX4PMState *s)
  74 {
  75     uint32_t d;
  76     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, get_ticks_per_sec());
  77     return d & 0xffffff;
  78 }
  79
  80 static int get_pmsts(PIIX4PMState *s)
  81 {
  82     int64_t d;
  83
  84     d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ, get_ticks_per_sec());
  85     if (d >= s->tmr_overflow_time)
  86         s->pmsts |= TMROF_EN;
  87     return s->pmsts;
  88 }
  89
  90 static void pm_update_sci(PIIX4PMState *s)
  91 {
  92     int sci_level, pmsts;
  93     int64_t expire_time;
  94
  95     pmsts = get_pmsts(s);
  96     sci_level = (((pmsts & s->pmen) &
  97                   (RTC_EN | PWRBTN_EN | GBL_EN | TMROF_EN)) != 0);
  98     qemu_set_irq(s->irq, sci_level);
  99     /* schedule a timer interruption if needed */
 100     if ((s->pmen & TMROF_EN) && !(pmsts & TMROF_EN)) {
 101         expire_time = muldiv64(s->tmr_overflow_time, get_ticks_per_sec(), PM_FREQ);
 102         qemu_mod_timer(s->tmr_timer, expire_time);
 103     } else {
 104         qemu_del_timer(s->tmr_timer);
 105     }
 106 }
 107
 108 static void pm_tmr_timer(void *opaque)
 109 {
 110     PIIX4PMState *s = opaque;
 111     pm_update_sci(s);
 112 }
 113
 114 static void pm_ioport_writew(void *opaque, uint32_t addr, uint32_t val)
 115 {
 116     PIIX4PMState *s = opaque;
 117     addr &= 0x3f;
 118     switch(addr) {
 119     case 0x00:
 120         {
 121             int64_t d;
 122             int pmsts;
 123             pmsts = get_pmsts(s);
 124             if (pmsts & val & TMROF_EN) {
 125                 /* if TMRSTS is reset, then compute the new overflow time */
 126                 d = muldiv64(qemu_get_clock(vm_clock), PM_FREQ,
 127                              get_ticks_per_sec());
 128                 s->tmr_overflow_time = (d + 0x800000LL) & ~0x7fffffLL;
 129             }
 130             s->pmsts &= ~val;
 131             pm_update_sci(s);
 132         }
 133         break;
 134     case 0x02:
 135         s->pmen = val;
 136         pm_update_sci(s);
 137         break;
 138     case 0x04:
 139         {
 140             int sus_typ;
 141             s->pmcntrl = val & ~(SUS_EN);
 142             if (val & SUS_EN) {
 143                 /* change suspend type */
 144                 sus_typ = (val >> 10) & 7;
 145                 switch(sus_typ) {
 146                 case 0: /* soft power off */
 147                     qemu_system_shutdown_request();
 148                     break;
 149                 case 1:
 150                     /* RSM_STS should be set on resume. Pretend that resume
 151                        was caused by power button */
 152                     s->pmsts |= (RSM_STS | PWRBTN_STS);
 153                     qemu_system_reset_request();
 154                     if (s->cmos_s3) {
 155                         qemu_irq_raise(s->cmos_s3);
 156                     }
 157                 default:
 158                     break;
 159                 }
 160             }
 161         }
 162         break;
 163     default:
 164         break;
 165     }
 166 #ifdef DEBUG
 167     printf("PM writew port=0x%04x val=0x%04x\n", addr, val);
 168 #endif
 169 }
 170
 171 static uint32_t pm_ioport_readw(void *opaque, uint32_t addr)
 172 {
 173     PIIX4PMState *s = opaque;
 174     uint32_t val;
 175
 176     addr &= 0x3f;
 177     switch(addr) {
 178     case 0x00:
 179         val = get_pmsts(s);
 180         break;
 181     case 0x02:
 182         val = s->pmen;
 183         break;
 184     case 0x04:
 185         val = s->pmcntrl;
 186         break;
 187     default:
 188         val = 0;
 189         break;
 190     }
 191 #ifdef DEBUG
 192     printf("PM readw port=0x%04x val=0x%04x\n", addr, val);
 193 #endif
 194     return val;
 195 }
 196
 197 static void pm_ioport_writel(void *opaque, uint32_t addr, uint32_t val)
 198 {
 199     //    PIIX4PMState *s = opaque;
 200 #ifdef DEBUG
 201     addr &= 0x3f;
 202     printf("PM writel port=0x%04x val=0x%08x\n", addr, val);
 203 #endif
 204 }
 205
 206 static uint32_t pm_ioport_readl(void *opaque, uint32_t addr)
 207 {
 208     PIIX4PMState *s = opaque;
 209     uint32_t val;
 210
 211     addr &= 0x3f;
 212     switch(addr) {
 213     case 0x08:
 214         val = get_pmtmr(s);
 215         break;
 216     default:
 217         val = 0;
 218         break;
 219     }
 220 #ifdef DEBUG
 221     printf("PM readl port=0x%04x val=0x%08x\n", addr, val);
 222 #endif
 223     return val;
 224 }
 225
 226 static void apm_ctrl_changed(uint32_t val, void *arg)
 227 {
 228     PIIX4PMState *s = arg;
 229
 230     /* ACPI specs 3.0, 4.7.2.5 */
 231     if (val == ACPI_ENABLE) {
 232         s->pmcntrl |= SCI_EN;
 233     } else if (val == ACPI_DISABLE) {
 234         s->pmcntrl &= ~SCI_EN;
 235     }
 236
 237     if (s->dev.config[0x5b] & (1 << 1)) {
 238         if (s->smi_irq) {
 239             qemu_irq_raise(s->smi_irq);
 240         }
 241     }
 242 }
 243
 244 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 245 {
 246 #if defined(DEBUG)
 247     printf("ACPI: DBG: 0x%08x\n", val);
 248 #endif
 249 }
 250
 251 static void pm_io_space_update(PIIX4PMState *s)
 252 {
 253     uint32_t pm_io_base;
 254
 255     if (s->dev.config[0x80] & 1) {
 256         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 257         pm_io_base &= 0xffc0;
 258
 259         /* XXX: need to improve memory and ioport allocation */
 260 #if defined(DEBUG)
 261         printf("PM: mapping to 0x%x\n", pm_io_base);
 262 #endif
 263         register_ioport_write(pm_io_base, 64, 2, pm_ioport_writew, s);
 264         register_ioport_read(pm_io_base, 64, 2, pm_ioport_readw, s);
 265         register_ioport_write(pm_io_base, 64, 4, pm_ioport_writel, s);
 266         register_ioport_read(pm_io_base, 64, 4, pm_ioport_readl, s);
 267     }
 268 }
 269
 270 static void pm_write_config(PCIDevice *d,
 271                             uint32_t address, uint32_t val, int len)
 272 {
 273     pci_default_write_config(d, address, val, len);
 274     if (range_covers_byte(address, len, 0x80))
 275         pm_io_space_update((PIIX4PMState *)d);
 276 }
 277
 278 static int vmstate_acpi_post_load(void *opaque, int version_id)
 279 {
 280     PIIX4PMState *s = opaque;
 281
 282     pm_io_space_update(s);
 283     return 0;
 284 }
 285
 286 static const VMStateDescription vmstate_acpi = {
 287     .name = "piix4_pm",
 288     .version_id = 1,
 289     .minimum_version_id = 1,
 290     .minimum_version_id_old = 1,
 291     .post_load = vmstate_acpi_post_load,
 292     .fields      = (VMStateField []) {
 293         VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
 294         VMSTATE_UINT16(pmsts, PIIX4PMState),
 295         VMSTATE_UINT16(pmen, PIIX4PMState),
 296         VMSTATE_UINT16(pmcntrl, PIIX4PMState),
 297         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 298         VMSTATE_TIMER(tmr_timer, PIIX4PMState),
 299         VMSTATE_INT64(tmr_overflow_time, PIIX4PMState),
 300         VMSTATE_END_OF_LIST()
 301     }
 302 };
 303
 304 static void piix4_reset(void *opaque)
 305 {
 306     PIIX4PMState *s = opaque;
 307     uint8_t *pci_conf = s->dev.config;
 308
 309     pci_conf[0x58] = 0;
 310     pci_conf[0x59] = 0;
 311     pci_conf[0x5a] = 0;
 312     pci_conf[0x5b] = 0;
 313
 314     if (s->kvm_enabled) {
 315         /* Mark SMM as already inited (until KVM supports SMM). */
 316         pci_conf[0x5B] = 0x02;
 317     }
 318 }
 319
 320 static void piix4_powerdown(void *opaque, int irq, int power_failing)
 321 {
 322     PIIX4PMState *s = opaque;
 323
 324     if (!s) {
 325         qemu_system_shutdown_request();
 326     } else if (s->pmen & PWRBTN_EN) {
 327         s->pmsts |= PWRBTN_EN;
 328         pm_update_sci(s);
 329     }
 330 }
 331
 332 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 333                        qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
 334                        int kvm_enabled)
 335 {
 336     PIIX4PMState *s;
 337     uint8_t *pci_conf;
 338
 339     s = (PIIX4PMState *)pci_register_device(bus,
 340                                          "PM", sizeof(PIIX4PMState),
 341                                          devfn, NULL, pm_write_config);
 342     pm_state = s;
 343     pci_conf = s->dev.config;
 344     pci_config_set_vendor_id(pci_conf, PCI_VENDOR_ID_INTEL);
 345     pci_config_set_device_id(pci_conf, PCI_DEVICE_ID_INTEL_82371AB_3);
 346     pci_conf[0x06] = 0x80;
 347     pci_conf[0x07] = 0x02;
 348     pci_conf[0x08] = 0x03; // revision number
 349     pci_conf[0x09] = 0x00;
 350     pci_config_set_class(pci_conf, PCI_CLASS_BRIDGE_OTHER);
 351     pci_conf[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 352     pci_conf[0x3d] = 0x01; // interrupt pin 1
 353
 354     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 355
 356 #if defined(TARGET_IA64)
 357     pci_conf[0x40] = 0x41; /* PM io base read only bit */
 358     pci_conf[0x41] = 0x1f;
 359     pm_write_config(s, 0x80, 0x01, 1); /*Set default pm_io_base 0x1f40*/
 360     s->pmcntrl = SCI_EN;
 361 #endif
 362
 363     /* APM */
 364     apm_init(&s->apm, apm_ctrl_changed, s);
 365
 366     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 367
 368     s->kvm_enabled = kvm_enabled;
 369     if (s->kvm_enabled) {
 370         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 371          * support SMM mode. */
 372         pci_conf[0x5B] = 0x02;
 373     }
 374
 375     /* XXX: which specification is used ? The i82731AB has different
 376        mappings */
 377     pci_conf[0x5f] = (parallel_hds[0] != NULL ? 0x80 : 0) | 0x10;
 378     pci_conf[0x63] = 0x60;
 379     pci_conf[0x67] = (serial_hds[0] != NULL ? 0x08 : 0) |
 380         (serial_hds[1] != NULL ? 0x90 : 0);
 381
 382     pci_conf[0x90] = smb_io_base | 1;
 383     pci_conf[0x91] = smb_io_base >> 8;
 384     pci_conf[0xd2] = 0x09;
 385     register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
 386     register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
 387
 388     s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
 389
 390     qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
 391
 392     vmstate_register(0, &vmstate_acpi, s);
 393
 394     pm_smbus_init(NULL, &s->smb);
 395     s->irq = sci_irq;
 396     s->cmos_s3 = cmos_s3;
 397     s->smi_irq = smi_irq;
 398     qemu_register_reset(piix4_reset, s);
 399
 400     return s->smb.smbus;
 401 }
 402
 403 #define GPE_BASE 0xafe0
 404 #define PROC_BASE 0xaf00
 405 #define PCI_BASE 0xae00
 406 #define PCI_EJ_BASE 0xae08
 407
 408 struct gpe_regs {
 409     uint16_t sts; /* status */
 410     uint16_t en;  /* enabled */
 411     uint8_t cpus_sts[32];
 412 };
 413
 414 struct pci_status {
 415     uint32_t up;
 416     uint32_t down;
 417 };
 418
 419 static struct gpe_regs gpe;
 420 static struct pci_status pci0_status;
 421
 422 static uint32_t gpe_read_val(uint16_t val, uint32_t addr)
 423 {
 424     if (addr & 1)
 425         return (val >> 8) & 0xff;
 426     return val & 0xff;
 427 }
 428
 429 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 430 {
 431     uint32_t val = 0;
 432     struct gpe_regs *g = opaque;
 433     switch (addr) {
 434         case PROC_BASE ... PROC_BASE+31:
 435             val = g->cpus_sts[addr - PROC_BASE];
 436             break;
 437
 438         case GPE_BASE:
 439         case GPE_BASE + 1:
 440             val = gpe_read_val(g->sts, addr);
 441             break;
 442         case GPE_BASE + 2:
 443         case GPE_BASE + 3:
 444             val = gpe_read_val(g->en, addr);
 445             break;
 446         default:
 447             break;
 448     }
 449
 450 #if defined(DEBUG)
 451     printf("gpe read %x == %x\n", addr, val);
 452 #endif
 453     return val;
 454 }
 455
 456 static void gpe_write_val(uint16_t *cur, int addr, uint32_t val)
 457 {
 458     if (addr & 1)
 459         *cur = (*cur & 0xff) | (val << 8);
 460     else
 461         *cur = (*cur & 0xff00) | (val & 0xff);
 462 }
 463
 464 static void gpe_reset_val(uint16_t *cur, int addr, uint32_t val)
 465 {
 466     uint16_t x1, x0 = val & 0xff;
 467     int shift = (addr & 1) ? 8 : 0;
 468
 469     x1 = (*cur >> shift) & 0xff;
 470
 471     x1 = x1 & ~x0;
 472
 473     *cur = (*cur & (0xff << (8 - shift))) | (x1 << shift);
 474 }
 475
 476 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 477 {
 478     struct gpe_regs *g = opaque;
 479     switch (addr) {
 480         case PROC_BASE ... PROC_BASE + 31:
 481             /* don't allow to change cpus_sts from inside a guest */
 482             break;
 483
 484         case GPE_BASE:
 485         case GPE_BASE + 1:
 486             gpe_reset_val(&g->sts, addr, val);
 487             break;
 488         case GPE_BASE + 2:
 489         case GPE_BASE + 3:
 490             gpe_write_val(&g->en, addr, val);
 491             break;
 492         default:
 493             break;
 494    }
 495
 496 #if defined(DEBUG)
 497     printf("gpe write %x <== %d\n", addr, val);
 498 #endif
 499 }
 500
 501 static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
 502 {
 503     uint32_t val = 0;
 504     struct pci_status *g = opaque;
 505     switch (addr) {
 506         case PCI_BASE:
 507             val = g->up;
 508             break;
 509         case PCI_BASE + 4:
 510             val = g->down;
 511             break;
 512         default:
 513             break;
 514     }
 515
 516 #if defined(DEBUG)
 517     printf("pcihotplug read %x == %x\n", addr, val);
 518 #endif
 519     return val;
 520 }
 521
 522 static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
 523 {
 524     struct pci_status *g = opaque;
 525     switch (addr) {
 526         case PCI_BASE:
 527             g->up = val;
 528             break;
 529         case PCI_BASE + 4:
 530             g->down = val;
 531             break;
 532    }
 533
 534 #if defined(DEBUG)
 535     printf("pcihotplug write %x <== %d\n", addr, val);
 536 #endif
 537 }
 538
 539 static uint32_t pciej_read(void *opaque, uint32_t addr)
 540 {
 541 #if defined(DEBUG)
 542     printf("pciej read %x\n", addr);
 543 #endif
 544     return 0;
 545 }
 546
 547 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 548 {
 549     BusState *bus = opaque;
 550     DeviceState *qdev, *next;
 551     PCIDevice *dev;
 552     int slot = ffs(val) - 1;
 553
 554     QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
 555         dev = DO_UPCAST(PCIDevice, qdev, qdev);
 556         if (PCI_SLOT(dev->devfn) == slot) {
 557             qdev_free(qdev);
 558         }
 559     }
 560
 561
 562 #if defined(DEBUG)
 563     printf("pciej write %x <== %d\n", addr, val);
 564 #endif
 565 }
 566
 567 static const char *model;
 568
 569 static int piix4_device_hotplug(PCIDevice *dev, int state);
 570
 571 void piix4_acpi_system_hot_add_init(PCIBus *bus, const char *cpu_model)
 572 {
 573     int i = 0, cpus = smp_cpus;
 574
 575     while (cpus > 0) {
 576         gpe.cpus_sts[i++] = (cpus < 8) ? (1 << cpus) - 1 : 0xff;
 577         cpus -= 8;
 578     }
 579     register_ioport_write(GPE_BASE, 4, 1, gpe_writeb, &gpe);
 580     register_ioport_read(GPE_BASE, 4, 1,  gpe_readb, &gpe);
 581
 582     register_ioport_write(PROC_BASE, 32, 1, gpe_writeb, &gpe);
 583     register_ioport_read(PROC_BASE, 32, 1,  gpe_readb, &gpe);
 584
 585     register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, &pci0_status);
 586     register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, &pci0_status);
 587
 588     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
 589     register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, bus);
 590
 591     model = cpu_model;
 592
 593     pci_bus_hotplug(bus, piix4_device_hotplug);
 594 }
 595
 596 #if defined(TARGET_I386)
 597 static void enable_processor(struct gpe_regs *g, int cpu)
 598 {
 599     g->sts |= 4;
 600     g->cpus_sts[cpu/8] |= (1 << (cpu%8));
 601 }
 602
 603 static void disable_processor(struct gpe_regs *g, int cpu)
 604 {
 605     g->sts |= 4;
 606     g->cpus_sts[cpu/8] &= ~(1 << (cpu%8));
 607 }
 608
 609 void qemu_system_cpu_hot_add(int cpu, int state)
 610 {
 611     CPUState *env;
 612
 613     if (state && !qemu_get_cpu(cpu)) {
 614         env = pc_new_cpu(model);
 615         if (!env) {
 616             fprintf(stderr, "cpu %d creation failed\n", cpu);
 617             return;
 618         }
 619         env->cpuid_apic_id = cpu;
 620     }
 621
 622     if (state)
 623         enable_processor(&gpe, cpu);
 624     else
 625         disable_processor(&gpe, cpu);
 626     if (gpe.en & 4) {
 627         qemu_set_irq(pm_state->irq, 1);
 628         qemu_set_irq(pm_state->irq, 0);
 629     }
 630 }
 631 #endif
 632
 633 static void enable_device(struct pci_status *p, struct gpe_regs *g, int slot)
 634 {
 635     g->sts |= 2;
 636     p->up |= (1 << slot);
 637 }
 638
 639 static void disable_device(struct pci_status *p, struct gpe_regs *g, int slot)
 640 {
 641     g->sts |= 2;
 642     p->down |= (1 << slot);
 643 }
 644
 645 static int piix4_device_hotplug(PCIDevice *dev, int state)
 646 {
 647     int slot = PCI_SLOT(dev->devfn);
 648
 649     pci0_status.up = 0;
 650     pci0_status.down = 0;
 651     if (state)
 652         enable_device(&pci0_status, &gpe, slot);
 653     else
 654         disable_device(&pci0_status, &gpe, slot);
 655     if (gpe.en & 2) {
 656         qemu_set_irq(pm_state->irq, 1);
 657         qemu_set_irq(pm_state->irq, 0);
 658     }
 659     return 0;
 660 }
 661
 662 struct acpi_table_header
 663 {
 664     char signature [4];    /* ACPI signature (4 ASCII characters) */
 665     uint32_t length;          /* Length of table, in bytes, including header */
 666     uint8_t revision;         /* ACPI Specification minor version # */
 667     uint8_t checksum;         /* To make sum of entire table == 0 */
 668     char oem_id [6];       /* OEM identification */
 669     char oem_table_id [8]; /* OEM table identification */
 670     uint32_t oem_revision;    /* OEM revision number */
 671     char asl_compiler_id [4]; /* ASL compiler vendor ID */
 672     uint32_t asl_compiler_revision; /* ASL compiler revision number */
 673 } __attribute__((packed));
 674
 675 char *acpi_tables;
 676 size_t acpi_tables_len;
 677
 678 static int acpi_checksum(const uint8_t *data, int len)
 679 {
 680     int sum, i;
 681     sum = 0;
 682     for(i = 0; i < len; i++)
 683         sum += data[i];
 684     return (-sum) & 0xff;
 685 }
 686
 687 int acpi_table_add(const char *t)
 688 {
 689     static const char *dfl_id = "QEMUQEMU";
 690     char buf[1024], *p, *f;
 691     struct acpi_table_header acpi_hdr;
 692     unsigned long val;
 693     size_t off;
 694
 695     memset(&acpi_hdr, 0, sizeof(acpi_hdr));
 696
 697     if (get_param_value(buf, sizeof(buf), "sig", t)) {
 698         strncpy(acpi_hdr.signature, buf, 4);
 699     } else {
 700         strncpy(acpi_hdr.signature, dfl_id, 4);
 701     }
 702     if (get_param_value(buf, sizeof(buf), "rev", t)) {
 703         val = strtoul(buf, &p, 10);
 704         if (val > 255 || *p != '\0')
 705             goto out;
 706     } else {
 707         val = 1;
 708     }
 709     acpi_hdr.revision = (int8_t)val;
 710
 711     if (get_param_value(buf, sizeof(buf), "oem_id", t)) {
 712         strncpy(acpi_hdr.oem_id, buf, 6);
 713     } else {
 714         strncpy(acpi_hdr.oem_id, dfl_id, 6);
 715     }
 716
 717     if (get_param_value(buf, sizeof(buf), "oem_table_id", t)) {
 718         strncpy(acpi_hdr.oem_table_id, buf, 8);
 719     } else {
 720         strncpy(acpi_hdr.oem_table_id, dfl_id, 8);
 721     }
 722
 723     if (get_param_value(buf, sizeof(buf), "oem_rev", t)) {
 724         val = strtol(buf, &p, 10);
 725         if(*p != '\0')
 726             goto out;
 727     } else {
 728         val = 1;
 729     }
 730     acpi_hdr.oem_revision = cpu_to_le32(val);
 731
 732     if (get_param_value(buf, sizeof(buf), "asl_compiler_id", t)) {
 733         strncpy(acpi_hdr.asl_compiler_id, buf, 4);
 734     } else {
 735         strncpy(acpi_hdr.asl_compiler_id, dfl_id, 4);
 736     }
 737
 738     if (get_param_value(buf, sizeof(buf), "asl_compiler_rev", t)) {
 739         val = strtol(buf, &p, 10);
 740         if(*p != '\0')
 741             goto out;
 742     } else {
 743         val = 1;
 744     }
 745     acpi_hdr.asl_compiler_revision = cpu_to_le32(val);
 746
 747     if (!get_param_value(buf, sizeof(buf), "data", t)) {
 748          buf[0] = '\0';
 749     }
 750
 751     acpi_hdr.length = sizeof(acpi_hdr);
 752
 753     f = buf;
 754     while (buf[0]) {
 755         struct stat s;
 756         char *n = strchr(f, ':');
 757         if (n)
 758             *n = '\0';
 759         if(stat(f, &s) < 0) {
 760             fprintf(stderr, "Can't stat file '%s': %s\n", f, strerror(errno));
 761             goto out;
 762         }
 763         acpi_hdr.length += s.st_size;
 764         if (!n)
 765             break;
 766         *n = ':';
 767         f = n + 1;
 768     }
 769
 770     if (!acpi_tables) {
 771         acpi_tables_len = sizeof(uint16_t);
 772         acpi_tables = qemu_mallocz(acpi_tables_len);
 773     }
 774     p = acpi_tables + acpi_tables_len;
 775     acpi_tables_len += sizeof(uint16_t) + acpi_hdr.length;
 776     acpi_tables = qemu_realloc(acpi_tables, acpi_tables_len);
 777
 778     acpi_hdr.length = cpu_to_le32(acpi_hdr.length);
 779     *(uint16_t*)p = acpi_hdr.length;
 780     p += sizeof(uint16_t);
 781     memcpy(p, &acpi_hdr, sizeof(acpi_hdr));
 782     off = sizeof(acpi_hdr);
 783
 784     f = buf;
 785     while (buf[0]) {
 786         struct stat s;
 787         int fd;
 788         char *n = strchr(f, ':');
 789         if (n)
 790             *n = '\0';
 791         fd = open(f, O_RDONLY);
 792
 793         if(fd < 0)
 794             goto out;
 795         if(fstat(fd, &s) < 0) {
 796             close(fd);
 797             goto out;
 798         }
 799
 800         do {
 801             int r;
 802             r = read(fd, p + off, s.st_size);
 803             if (r > 0) {
 804                 off += r;
 805                 s.st_size -= r;
 806             } else if ((r < 0 && errno != EINTR) || r == 0) {
 807                 close(fd);
 808                 goto out;
 809             }
 810         } while(s.st_size);
 811
 812         close(fd);
 813         if (!n)
 814             break;
 815         f = n + 1;
 816     }
 817
 818     ((struct acpi_table_header*)p)->checksum = acpi_checksum((uint8_t*)p, off);
 819     /* increase number of tables */
 820     (*(uint16_t*)acpi_tables) =
 821             cpu_to_le32(le32_to_cpu(*(uint16_t*)acpi_tables) + 1);
 822     return 0;
 823 out:
 824     if (acpi_tables) {
 825         qemu_free(acpi_tables);
 826         acpi_tables = NULL;
 827     }
 828     return -1;
 829 }