kvm-tpr-opt.c

   1 /*
   2  * tpr optimization for qemu/kvm
   3  *
   4  * Copyright (C) 2007-2008 Qumranet Technologies
   5  *
   6  * Licensed under the terms of the GNU GPL version 2 or higher.
   7  */
   8
   9 #include "config.h"
  10 #include "config-host.h"
  11
  12 #include <string.h>
  13
  14 #include "hw/hw.h"
  15 #include "hw/isa.h"
  16 #include "sysemu.h"
  17 #include "kvm.h"
  18 #include "cpu.h"
  19
  20 #include <stdio.h>
  21
  22 static uint64_t map_addr(CPUState *env, target_ulong virt, unsigned *perms)
  23 {
  24     uint64_t mask = ((1ull << 48) - 1) & ~4095ull;
  25     uint64_t p, pp = 7;
  26
  27     p = env->cr[3];
  28     if (env->cr[4] & 0x20) {
  29         p &= ~31ull;
  30         p = ldq_phys(p + 8 * (virt >> 30));
  31         if (!(p & 1))
  32             return -1ull;
  33         p &= mask;
  34         p = ldq_phys(p + 8 * ((virt >> 21) & 511));
  35         if (!(p & 1))
  36             return -1ull;
  37         pp &= p;
  38         if (p & 128) {
  39             p += ((virt >> 12) & 511) << 12;
  40         } else {
  41             p &= mask;
  42             p = ldq_phys(p + 8 * ((virt >> 12) & 511));
  43             if (!(p & 1))
  44                 return -1ull;
  45             pp &= p;
  46         }
  47     } else {
  48         p &= mask;
  49         p = ldl_phys(p + 4 * ((virt >> 22) & 1023));
  50         if (!(p & 1))
  51             return -1ull;
  52         pp &= p;
  53         if (p & 128) {
  54             p += ((virt >> 12) & 1023) << 12;
  55         } else {
  56             p &= mask;
  57             p = ldl_phys(p + 4 * ((virt >> 12) & 1023));
  58             pp &= p;
  59             if (!(p & 1))
  60                 return -1ull;
  61         }
  62     }
  63     if (perms)
  64         *perms = pp >> 1;
  65     p &= mask;
  66     return p + (virt & 4095);
  67 }
  68
  69 static uint8_t read_byte_virt(CPUState *env, target_ulong virt)
  70 {
  71     return ldub_phys(map_addr(env, virt, NULL));
  72 }
  73
  74 static void write_byte_virt(CPUState *env, target_ulong virt, uint8_t b)
  75 {
  76     stb_phys(map_addr(env, virt, NULL), b);
  77 }
  78
  79 struct vapic_bios {
  80     char signature[8];
  81     uint32_t virt_base;
  82     uint32_t fixup_start;
  83     uint32_t fixup_end;
  84     uint32_t vapic;
  85     uint32_t vapic_size;
  86     uint32_t vcpu_shift;
  87     uint32_t real_tpr;
  88     struct vapic_patches {
  89         uint32_t set_tpr;
  90         uint32_t set_tpr_eax;
  91         uint32_t get_tpr[8];
  92         uint32_t get_tpr_stack;
  93     } __attribute__((packed)) up, mp;
  94 } __attribute__((packed));
  95
  96 static struct vapic_bios vapic_bios;
  97
  98 static uint32_t real_tpr;
  99 static uint32_t bios_addr;
 100 static uint32_t vapic_phys;
 101 static uint32_t bios_enabled;
 102 static uint32_t vbios_desc_phys;
 103 static uint32_t vapic_bios_addr;
 104
 105 static void update_vbios_real_tpr(void)
 106 {
 107     cpu_physical_memory_rw(vbios_desc_phys, (void *)&vapic_bios, sizeof vapic_bios, 0);
 108     vapic_bios.real_tpr = real_tpr;
 109     vapic_bios.vcpu_shift = 7;
 110     cpu_physical_memory_rw(vbios_desc_phys, (void *)&vapic_bios, sizeof vapic_bios, 1);
 111 }
 112
 113 static unsigned modrm_reg(uint8_t modrm)
 114 {
 115     return (modrm >> 3) & 7;
 116 }
 117
 118 static int is_abs_modrm(uint8_t modrm)
 119 {
 120     return (modrm & 0xc7) == 0x05;
 121 }
 122
 123 static int instruction_is_ok(CPUState *env, uint64_t rip, int is_write)
 124 {
 125     uint8_t b1, b2;
 126     unsigned addr_offset;
 127     uint32_t addr;
 128     uint64_t p;
 129
 130     if ((rip & 0xf0000000) != 0x80000000 && (rip & 0xf0000000) != 0xe0000000)
 131         return 0;
 132     if (env->regs[R_ESP] == 0)
 133         return 0;
 134     b1 = read_byte_virt(env, rip);
 135     b2 = read_byte_virt(env, rip + 1);
 136     switch (b1) {
 137     case 0xc7: /* mov imm32, r/m32 (c7/0) */
 138         if (modrm_reg(b2) != 0)
 139             return 0;
 140         /* fall through */
 141     case 0x89: /* mov r32 to r/m32 */
 142     case 0x8b: /* mov r/m32 to r32 */
 143         if (!is_abs_modrm(b2))
 144             return 0;
 145         addr_offset = 2;
 146         break;
 147     case 0xa1: /* mov abs to eax */
 148     case 0xa3: /* mov eax to abs */
 149         addr_offset = 1;
 150         break;
 151     case 0xff: /* push r/m32 */
 152         if (modrm_reg(b2) != 6 || !is_abs_modrm(b2))
 153             return 0;
 154         addr_offset = 2;
 155     default:
 156         return 0;
 157     }
 158     p = rip + addr_offset;
 159     addr = read_byte_virt(env, p++);
 160     addr |= read_byte_virt(env, p++) << 8;
 161     addr |= read_byte_virt(env, p++) << 16;
 162     addr |= read_byte_virt(env, p++) << 24;
 163     if ((addr & 0xfff) != 0x80)
 164         return 0;
 165     real_tpr = addr;
 166     update_vbios_real_tpr();
 167     return 1;
 168 }
 169
 170 static int bios_is_mapped(CPUState *env, uint64_t rip)
 171 {
 172     uint32_t probe;
 173     uint64_t phys;
 174     unsigned perms;
 175     uint32_t i;
 176     uint32_t offset, fixup, start = vapic_bios_addr ? : 0xe0000;
 177
 178     if (bios_enabled)
 179         return 1;
 180
 181     probe = (rip & 0xf0000000) + start;
 182     phys = map_addr(env, probe, &perms);
 183     if (phys != start)
 184         return 0;
 185     bios_addr = probe;
 186     for (i = 0; i < 64; ++i) {
 187         cpu_physical_memory_read(phys, (void *)&vapic_bios, sizeof(vapic_bios));
 188         if (memcmp(vapic_bios.signature, "kvm aPiC", 8) == 0)
 189             break;
 190         phys += 1024;
 191         bios_addr += 1024;
 192     }
 193     if (i == 64)
 194         return 0;
 195     if (bios_addr == vapic_bios.virt_base)
 196         return 1;
 197     vbios_desc_phys = phys;
 198     for (i = vapic_bios.fixup_start; i < vapic_bios.fixup_end; i += 4) {
 199         offset = ldl_phys(phys + i - vapic_bios.virt_base);
 200         fixup = phys + offset;
 201         stl_phys(fixup, ldl_phys(fixup) + bios_addr - vapic_bios.virt_base);
 202     }
 203     vapic_phys = vapic_bios.vapic - vapic_bios.virt_base + phys;
 204     return 1;
 205 }
 206
 207 static int get_pcr_cpu(CPUState *env)
 208 {
 209     uint8_t b;
 210
 211     cpu_synchronize_state(env);
 212
 213     if (cpu_memory_rw_debug(env, env->segs[R_FS].base + 0x51, &b, 1, 0) < 0)
 214             return -1;
 215
 216     return (int)b;
 217 }
 218
 219 int kvm_tpr_enable_vapic(CPUState *env)
 220 {
 221     static uint8_t one = 1;
 222     int pcr_cpu = get_pcr_cpu(env);
 223
 224     if (pcr_cpu < 0)
 225             return 0;
 226
 227     kvm_enable_vapic(env, vapic_phys + (pcr_cpu << 7));
 228     cpu_physical_memory_rw(vapic_phys + (pcr_cpu << 7) + 4, &one, 1, 1);
 229     env->kvm_vcpu_update_vapic = 0;
 230     bios_enabled = 1;
 231     return 1;
 232 }
 233
 234 static void patch_call(CPUState *env, uint64_t rip, uint32_t target)
 235 {
 236     uint32_t offset;
 237
 238     offset = target - vapic_bios.virt_base + bios_addr - rip - 5;
 239     write_byte_virt(env, rip, 0xe8); /* call near */
 240     write_byte_virt(env, rip + 1, offset);
 241     write_byte_virt(env, rip + 2, offset >> 8);
 242     write_byte_virt(env, rip + 3, offset >> 16);
 243     write_byte_virt(env, rip + 4, offset >> 24);
 244 }
 245
 246 static void patch_instruction(CPUState *env, uint64_t rip)
 247 {
 248     uint8_t b1, b2;
 249     struct vapic_patches *vp;
 250
 251     vp = smp_cpus == 1 ? &vapic_bios.up : &vapic_bios.mp;
 252     b1 = read_byte_virt(env, rip);
 253     b2 = read_byte_virt(env, rip + 1);
 254     switch (b1) {
 255     case 0x89: /* mov r32 to r/m32 */
 256         write_byte_virt(env, rip, 0x50 + modrm_reg(b2));  /* push reg */
 257         patch_call(env, rip + 1, vp->set_tpr);
 258         break;
 259     case 0x8b: /* mov r/m32 to r32 */
 260         write_byte_virt(env, rip, 0x90);
 261         patch_call(env, rip + 1, vp->get_tpr[modrm_reg(b2)]);
 262         break;
 263     case 0xa1: /* mov abs to eax */
 264         patch_call(env, rip, vp->get_tpr[0]);
 265         break;
 266     case 0xa3: /* mov eax to abs */
 267         patch_call(env, rip, vp->set_tpr_eax);
 268         break;
 269     case 0xc7: /* mov imm32, r/m32 (c7/0) */
 270         write_byte_virt(env, rip, 0x68);  /* push imm32 */
 271         write_byte_virt(env, rip + 1, read_byte_virt(env, rip+6));
 272         write_byte_virt(env, rip + 2, read_byte_virt(env, rip+7));
 273         write_byte_virt(env, rip + 3, read_byte_virt(env, rip+8));
 274         write_byte_virt(env, rip + 4, read_byte_virt(env, rip+9));
 275         patch_call(env, rip + 5, vp->set_tpr);
 276         break;
 277     case 0xff: /* push r/m32 */
 278         printf("patching push\n");
 279         write_byte_virt(env, rip, 0x50); /* push eax */
 280         patch_call(env, rip + 1, vp->get_tpr_stack);
 281         break;
 282     default:
 283         printf("funny insn %02x %02x\n", b1, b2);
 284     }
 285 }
 286
 287 void kvm_tpr_access_report(CPUState *env, uint64_t rip, int is_write)
 288 {
 289     cpu_synchronize_state(env);
 290     if (!instruction_is_ok(env, rip, is_write))
 291         return;
 292     if (!bios_is_mapped(env, rip))
 293         return;
 294     if (!kvm_tpr_enable_vapic(env))
 295         return;
 296     patch_instruction(env, rip);
 297 }
 298
 299 static void tpr_save(QEMUFile *f, void *s)
 300 {
 301     int i;
 302
 303     for (i = 0; i < (sizeof vapic_bios) / 4; ++i)
 304         qemu_put_be32s(f, &((uint32_t *)&vapic_bios)[i]);
 305     qemu_put_be32s(f, &bios_enabled);
 306     qemu_put_be32s(f, &real_tpr);
 307     qemu_put_be32s(f, &bios_addr);
 308     qemu_put_be32s(f, &vapic_phys);
 309     qemu_put_be32s(f, &vbios_desc_phys);
 310 }
 311
 312 static int tpr_load(QEMUFile *f, void *s, int version_id)
 313 {
 314     int i;
 315
 316     if (version_id != 1)
 317         return -EINVAL;
 318
 319     for (i = 0; i < (sizeof vapic_bios) / 4; ++i)
 320         qemu_get_be32s(f, &((uint32_t *)&vapic_bios)[i]);
 321     qemu_get_be32s(f, &bios_enabled);
 322     qemu_get_be32s(f, &real_tpr);
 323     qemu_get_be32s(f, &bios_addr);
 324     qemu_get_be32s(f, &vapic_phys);
 325     qemu_get_be32s(f, &vbios_desc_phys);
 326
 327     if (bios_enabled) {
 328         CPUState *env = first_cpu->next_cpu;
 329
 330         for (env = first_cpu; env != NULL; env = env->next_cpu)
 331             env->kvm_vcpu_update_vapic = 1;
 332     }
 333
 334     return 0;
 335 }
 336
 337 static void vtpr_ioport_write16(void *opaque, uint32_t addr, uint32_t val)
 338 {
 339     CPUState *env = cpu_single_env;
 340
 341     cpu_synchronize_state(env);
 342
 343     vapic_bios_addr = ((env->segs[R_CS].base + env->eip) & ~(512 - 1)) + val;
 344     bios_enabled = 0;
 345 }
 346
 347 static void vtpr_ioport_write(void *opaque, uint32_t addr, uint32_t val)
 348 {
 349     CPUState *env = cpu_single_env;
 350     uint32_t rip;
 351
 352     cpu_synchronize_state(env);
 353
 354     rip = env->eip - 2;
 355     write_byte_virt(env, rip, 0x66);
 356     write_byte_virt(env, rip + 1, 0x90);
 357     if (bios_enabled)
 358         return;
 359     if (!bios_is_mapped(env, rip))
 360         printf("bios not mapped?\n");
 361     for (addr = 0xfffff000u; addr >= 0x80000000u; addr -= 4096)
 362         if (map_addr(env, addr, NULL) == 0xfee00000u) {
 363             real_tpr = addr + 0x80;
 364             break;
 365         }
 366     bios_enabled = 1;
 367     update_vbios_real_tpr();
 368     kvm_tpr_enable_vapic(env);
 369 }
 370
 371 static void kvm_tpr_opt_setup(void)
 372 {
 373     register_savevm("kvm-tpr-opt", 0, 1, tpr_save, tpr_load, NULL);
 374     register_ioport_write(0x7e, 1, 1, vtpr_ioport_write, NULL);
 375     register_ioport_write(0x7e, 2, 2, vtpr_ioport_write16, NULL);
 376 }
 377
 378 device_init(kvm_tpr_opt_setup);