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target-ppc: Fix xxpermdi When T==A or T==B
[qemu-kvm.git] / target-ppc / translate.c
blob655aca656836645d6b52f69438c50432ad765055
1 /*
2 * PowerPC emulation for qemu: main translation routines.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright (C) 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "cpu.h"
22 #include "disas/disas.h"
23 #include "tcg-op.h"
24 #include "qemu/host-utils.h"
25
26 #include "helper.h"
27 #define GEN_HELPER 1
28 #include "helper.h"
29
30 #define CPU_SINGLE_STEP 0x1
31 #define CPU_BRANCH_STEP 0x2
32 #define GDBSTUB_SINGLE_STEP 0x4
33
34 /* Include definitions for instructions classes and implementations flags */
35 //#define PPC_DEBUG_DISAS
36 //#define DO_PPC_STATISTICS
37
38 #ifdef PPC_DEBUG_DISAS
39 # define LOG_DISAS(...) qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__)
40 #else
41 # define LOG_DISAS(...) do { } while (0)
42 #endif
43 /*****************************************************************************/
44 /* Code translation helpers */
45
46 /* global register indexes */
47 static TCGv_ptr cpu_env;
48 static char cpu_reg_names[10*3 + 22*4 /* GPR */
49 #if !defined(TARGET_PPC64)
50 + 10*4 + 22*5 /* SPE GPRh */
51 #endif
52 + 10*4 + 22*5 /* FPR */
53 + 2*(10*6 + 22*7) /* AVRh, AVRl */
54 + 10*5 + 22*6 /* VSR */
55 + 8*5 /* CRF */];
56 static TCGv cpu_gpr[32];
57 #if !defined(TARGET_PPC64)
58 static TCGv cpu_gprh[32];
59 #endif
60 static TCGv_i64 cpu_fpr[32];
61 static TCGv_i64 cpu_avrh[32], cpu_avrl[32];
62 static TCGv_i64 cpu_vsr[32];
63 static TCGv_i32 cpu_crf[8];
64 static TCGv cpu_nip;
65 static TCGv cpu_msr;
66 static TCGv cpu_ctr;
67 static TCGv cpu_lr;
68 #if defined(TARGET_PPC64)
69 static TCGv cpu_cfar;
70 #endif
71 static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca;
72 static TCGv cpu_reserve;
73 static TCGv cpu_fpscr;
74 static TCGv_i32 cpu_access_type;
75
76 #include "exec/gen-icount.h"
77
78 void ppc_translate_init(void)
79 {
80 int i;
81 char* p;
82 size_t cpu_reg_names_size;
83 static int done_init = 0;
84
85 if (done_init)
86 return;
87
88 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
89
90 p = cpu_reg_names;
91 cpu_reg_names_size = sizeof(cpu_reg_names);
92
93 for (i = 0; i < 8; i++) {
94 snprintf(p, cpu_reg_names_size, "crf%d", i);
95 cpu_crf[i] = tcg_global_mem_new_i32(TCG_AREG0,
96 offsetof(CPUPPCState, crf[i]), p);
97 p += 5;
98 cpu_reg_names_size -= 5;
99 }
100
101 for (i = 0; i < 32; i++) {
102 snprintf(p, cpu_reg_names_size, "r%d", i);
103 cpu_gpr[i] = tcg_global_mem_new(TCG_AREG0,
104 offsetof(CPUPPCState, gpr[i]), p);
105 p += (i < 10) ? 3 : 4;
106 cpu_reg_names_size -= (i < 10) ? 3 : 4;
107 #if !defined(TARGET_PPC64)
108 snprintf(p, cpu_reg_names_size, "r%dH", i);
109 cpu_gprh[i] = tcg_global_mem_new_i32(TCG_AREG0,
110 offsetof(CPUPPCState, gprh[i]), p);
111 p += (i < 10) ? 4 : 5;
112 cpu_reg_names_size -= (i < 10) ? 4 : 5;
113 #endif
114
115 snprintf(p, cpu_reg_names_size, "fp%d", i);
116 cpu_fpr[i] = tcg_global_mem_new_i64(TCG_AREG0,
117 offsetof(CPUPPCState, fpr[i]), p);
118 p += (i < 10) ? 4 : 5;
119 cpu_reg_names_size -= (i < 10) ? 4 : 5;
120
121 snprintf(p, cpu_reg_names_size, "avr%dH", i);
122 #ifdef HOST_WORDS_BIGENDIAN
123 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
124 offsetof(CPUPPCState, avr[i].u64[0]), p);
125 #else
126 cpu_avrh[i] = tcg_global_mem_new_i64(TCG_AREG0,
127 offsetof(CPUPPCState, avr[i].u64[1]), p);
128 #endif
129 p += (i < 10) ? 6 : 7;
130 cpu_reg_names_size -= (i < 10) ? 6 : 7;
131
132 snprintf(p, cpu_reg_names_size, "avr%dL", i);
133 #ifdef HOST_WORDS_BIGENDIAN
134 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
135 offsetof(CPUPPCState, avr[i].u64[1]), p);
136 #else
137 cpu_avrl[i] = tcg_global_mem_new_i64(TCG_AREG0,
138 offsetof(CPUPPCState, avr[i].u64[0]), p);
139 #endif
140 p += (i < 10) ? 6 : 7;
141 cpu_reg_names_size -= (i < 10) ? 6 : 7;
142 snprintf(p, cpu_reg_names_size, "vsr%d", i);
143 cpu_vsr[i] = tcg_global_mem_new_i64(TCG_AREG0,
144 offsetof(CPUPPCState, vsr[i]), p);
145 p += (i < 10) ? 5 : 6;
146 cpu_reg_names_size -= (i < 10) ? 5 : 6;
147 }
148
149 cpu_nip = tcg_global_mem_new(TCG_AREG0,
150 offsetof(CPUPPCState, nip), "nip");
151
152 cpu_msr = tcg_global_mem_new(TCG_AREG0,
153 offsetof(CPUPPCState, msr), "msr");
154
155 cpu_ctr = tcg_global_mem_new(TCG_AREG0,
156 offsetof(CPUPPCState, ctr), "ctr");
157
158 cpu_lr = tcg_global_mem_new(TCG_AREG0,
159 offsetof(CPUPPCState, lr), "lr");
160
161 #if defined(TARGET_PPC64)
162 cpu_cfar = tcg_global_mem_new(TCG_AREG0,
163 offsetof(CPUPPCState, cfar), "cfar");
164 #endif
165
166 cpu_xer = tcg_global_mem_new(TCG_AREG0,
167 offsetof(CPUPPCState, xer), "xer");
168 cpu_so = tcg_global_mem_new(TCG_AREG0,
169 offsetof(CPUPPCState, so), "SO");
170 cpu_ov = tcg_global_mem_new(TCG_AREG0,
171 offsetof(CPUPPCState, ov), "OV");
172 cpu_ca = tcg_global_mem_new(TCG_AREG0,
173 offsetof(CPUPPCState, ca), "CA");
174
175 cpu_reserve = tcg_global_mem_new(TCG_AREG0,
176 offsetof(CPUPPCState, reserve_addr),
177 "reserve_addr");
178
179 cpu_fpscr = tcg_global_mem_new(TCG_AREG0,
180 offsetof(CPUPPCState, fpscr), "fpscr");
181
182 cpu_access_type = tcg_global_mem_new_i32(TCG_AREG0,
183 offsetof(CPUPPCState, access_type), "access_type");
184
185 done_init = 1;
186 }
187
188 /* internal defines */
189 typedef struct DisasContext {
190 struct TranslationBlock *tb;
191 target_ulong nip;
192 uint32_t opcode;
193 uint32_t exception;
194 /* Routine used to access memory */
195 int mem_idx;
196 int access_type;
197 /* Translation flags */
198 int le_mode;
199 #if defined(TARGET_PPC64)
200 int sf_mode;
201 int has_cfar;
202 #endif
203 int fpu_enabled;
204 int altivec_enabled;
205 int vsx_enabled;
206 int spe_enabled;
207 ppc_spr_t *spr_cb; /* Needed to check rights for mfspr/mtspr */
208 int singlestep_enabled;
209 uint64_t insns_flags;
210 uint64_t insns_flags2;
211 } DisasContext;
212
213 /* True when active word size < size of target_long. */
214 #ifdef TARGET_PPC64
215 # define NARROW_MODE(C) (!(C)->sf_mode)
216 #else
217 # define NARROW_MODE(C) 0
218 #endif
219
220 struct opc_handler_t {
221 /* invalid bits for instruction 1 (Rc(opcode) == 0) */
222 uint32_t inval1;
223 /* invalid bits for instruction 2 (Rc(opcode) == 1) */
224 uint32_t inval2;
225 /* instruction type */
226 uint64_t type;
227 /* extended instruction type */
228 uint64_t type2;
229 /* handler */
230 void (*handler)(DisasContext *ctx);
231 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
232 const char *oname;
233 #endif
234 #if defined(DO_PPC_STATISTICS)
235 uint64_t count;
236 #endif
237 };
238
239 static inline void gen_reset_fpstatus(void)
240 {
241 gen_helper_reset_fpstatus(cpu_env);
242 }
243
244 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
245 {
246 TCGv_i32 t0 = tcg_temp_new_i32();
247
248 if (set_fprf != 0) {
249 /* This case might be optimized later */
250 tcg_gen_movi_i32(t0, 1);
251 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
252 if (unlikely(set_rc)) {
253 tcg_gen_mov_i32(cpu_crf[1], t0);
254 }
255 gen_helper_float_check_status(cpu_env);
256 } else if (unlikely(set_rc)) {
257 /* We always need to compute fpcc */
258 tcg_gen_movi_i32(t0, 0);
259 gen_helper_compute_fprf(t0, cpu_env, arg, t0);
260 tcg_gen_mov_i32(cpu_crf[1], t0);
261 }
262
263 tcg_temp_free_i32(t0);
264 }
265
266 static inline void gen_set_access_type(DisasContext *ctx, int access_type)
267 {
268 if (ctx->access_type != access_type) {
269 tcg_gen_movi_i32(cpu_access_type, access_type);
270 ctx->access_type = access_type;
271 }
272 }
273
274 static inline void gen_update_nip(DisasContext *ctx, target_ulong nip)
275 {
276 if (NARROW_MODE(ctx)) {
277 nip = (uint32_t)nip;
278 }
279 tcg_gen_movi_tl(cpu_nip, nip);
280 }
281
282 static inline void gen_exception_err(DisasContext *ctx, uint32_t excp, uint32_t error)
283 {
284 TCGv_i32 t0, t1;
285 if (ctx->exception == POWERPC_EXCP_NONE) {
286 gen_update_nip(ctx, ctx->nip);
287 }
288 t0 = tcg_const_i32(excp);
289 t1 = tcg_const_i32(error);
290 gen_helper_raise_exception_err(cpu_env, t0, t1);
291 tcg_temp_free_i32(t0);
292 tcg_temp_free_i32(t1);
293 ctx->exception = (excp);
294 }
295
296 static inline void gen_exception(DisasContext *ctx, uint32_t excp)
297 {
298 TCGv_i32 t0;
299 if (ctx->exception == POWERPC_EXCP_NONE) {
300 gen_update_nip(ctx, ctx->nip);
301 }
302 t0 = tcg_const_i32(excp);
303 gen_helper_raise_exception(cpu_env, t0);
304 tcg_temp_free_i32(t0);
305 ctx->exception = (excp);
306 }
307
308 static inline void gen_debug_exception(DisasContext *ctx)
309 {
310 TCGv_i32 t0;
311
312 if ((ctx->exception != POWERPC_EXCP_BRANCH) &&
313 (ctx->exception != POWERPC_EXCP_SYNC)) {
314 gen_update_nip(ctx, ctx->nip);
315 }
316 t0 = tcg_const_i32(EXCP_DEBUG);
317 gen_helper_raise_exception(cpu_env, t0);
318 tcg_temp_free_i32(t0);
319 }
320
321 static inline void gen_inval_exception(DisasContext *ctx, uint32_t error)
322 {
323 gen_exception_err(ctx, POWERPC_EXCP_PROGRAM, POWERPC_EXCP_INVAL | error);
324 }
325
326 /* Stop translation */
327 static inline void gen_stop_exception(DisasContext *ctx)
328 {
329 gen_update_nip(ctx, ctx->nip);
330 ctx->exception = POWERPC_EXCP_STOP;
331 }
332
333 /* No need to update nip here, as execution flow will change */
334 static inline void gen_sync_exception(DisasContext *ctx)
335 {
336 ctx->exception = POWERPC_EXCP_SYNC;
337 }
338
339 #define GEN_HANDLER(name, opc1, opc2, opc3, inval, type) \
340 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, PPC_NONE)
341
342 #define GEN_HANDLER_E(name, opc1, opc2, opc3, inval, type, type2) \
343 GEN_OPCODE(name, opc1, opc2, opc3, inval, type, type2)
344
345 #define GEN_HANDLER2(name, onam, opc1, opc2, opc3, inval, type) \
346 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, PPC_NONE)
347
348 #define GEN_HANDLER2_E(name, onam, opc1, opc2, opc3, inval, type, type2) \
349 GEN_OPCODE2(name, onam, opc1, opc2, opc3, inval, type, type2)
350
351 typedef struct opcode_t {
352 unsigned char opc1, opc2, opc3;
353 #if HOST_LONG_BITS == 64 /* Explicitly align to 64 bits */
354 unsigned char pad[5];
355 #else
356 unsigned char pad[1];
357 #endif
358 opc_handler_t handler;
359 const char *oname;
360 } opcode_t;
361
362 /*****************************************************************************/
363 /*** Instruction decoding ***/
364 #define EXTRACT_HELPER(name, shift, nb) \
365 static inline uint32_t name(uint32_t opcode) \
366 { \
367 return (opcode >> (shift)) & ((1 << (nb)) - 1); \
368 }
369
370 #define EXTRACT_SHELPER(name, shift, nb) \
371 static inline int32_t name(uint32_t opcode) \
372 { \
373 return (int16_t)((opcode >> (shift)) & ((1 << (nb)) - 1)); \
374 }
375
376 #define EXTRACT_HELPER_SPLIT(name, shift1, nb1, shift2, nb2) \
377 static inline uint32_t name(uint32_t opcode) \
378 { \
379 return (((opcode >> (shift1)) & ((1 << (nb1)) - 1)) << nb2) | \
380 ((opcode >> (shift2)) & ((1 << (nb2)) - 1)); \
381 }
382 /* Opcode part 1 */
383 EXTRACT_HELPER(opc1, 26, 6);
384 /* Opcode part 2 */
385 EXTRACT_HELPER(opc2, 1, 5);
386 /* Opcode part 3 */
387 EXTRACT_HELPER(opc3, 6, 5);
388 /* Update Cr0 flags */
389 EXTRACT_HELPER(Rc, 0, 1);
390 /* Destination */
391 EXTRACT_HELPER(rD, 21, 5);
392 /* Source */
393 EXTRACT_HELPER(rS, 21, 5);
394 /* First operand */
395 EXTRACT_HELPER(rA, 16, 5);
396 /* Second operand */
397 EXTRACT_HELPER(rB, 11, 5);
398 /* Third operand */
399 EXTRACT_HELPER(rC, 6, 5);
400 /*** Get CRn ***/
401 EXTRACT_HELPER(crfD, 23, 3);
402 EXTRACT_HELPER(crfS, 18, 3);
403 EXTRACT_HELPER(crbD, 21, 5);
404 EXTRACT_HELPER(crbA, 16, 5);
405 EXTRACT_HELPER(crbB, 11, 5);
406 /* SPR / TBL */
407 EXTRACT_HELPER(_SPR, 11, 10);
408 static inline uint32_t SPR(uint32_t opcode)
409 {
410 uint32_t sprn = _SPR(opcode);
411
412 return ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
413 }
414 /*** Get constants ***/
415 EXTRACT_HELPER(IMM, 12, 8);
416 /* 16 bits signed immediate value */
417 EXTRACT_SHELPER(SIMM, 0, 16);
418 /* 16 bits unsigned immediate value */
419 EXTRACT_HELPER(UIMM, 0, 16);
420 /* 5 bits signed immediate value */
421 EXTRACT_HELPER(SIMM5, 16, 5);
422 /* 5 bits signed immediate value */
423 EXTRACT_HELPER(UIMM5, 16, 5);
424 /* Bit count */
425 EXTRACT_HELPER(NB, 11, 5);
426 /* Shift count */
427 EXTRACT_HELPER(SH, 11, 5);
428 /* Vector shift count */
429 EXTRACT_HELPER(VSH, 6, 4);
430 /* Mask start */
431 EXTRACT_HELPER(MB, 6, 5);
432 /* Mask end */
433 EXTRACT_HELPER(ME, 1, 5);
434 /* Trap operand */
435 EXTRACT_HELPER(TO, 21, 5);
436
437 EXTRACT_HELPER(CRM, 12, 8);
438 EXTRACT_HELPER(SR, 16, 4);
439
440 /* mtfsf/mtfsfi */
441 EXTRACT_HELPER(FPBF, 23, 3);
442 EXTRACT_HELPER(FPIMM, 12, 4);
443 EXTRACT_HELPER(FPL, 25, 1);
444 EXTRACT_HELPER(FPFLM, 17, 8);
445 EXTRACT_HELPER(FPW, 16, 1);
446
447 /*** Jump target decoding ***/
448 /* Displacement */
449 EXTRACT_SHELPER(d, 0, 16);
450 /* Immediate address */
451 static inline target_ulong LI(uint32_t opcode)
452 {
453 return (opcode >> 0) & 0x03FFFFFC;
454 }
455
456 static inline uint32_t BD(uint32_t opcode)
457 {
458 return (opcode >> 0) & 0xFFFC;
459 }
460
461 EXTRACT_HELPER(BO, 21, 5);
462 EXTRACT_HELPER(BI, 16, 5);
463 /* Absolute/relative address */
464 EXTRACT_HELPER(AA, 1, 1);
465 /* Link */
466 EXTRACT_HELPER(LK, 0, 1);
467
468 /* Create a mask between <start> and <end> bits */
469 static inline target_ulong MASK(uint32_t start, uint32_t end)
470 {
471 target_ulong ret;
472
473 #if defined(TARGET_PPC64)
474 if (likely(start == 0)) {
475 ret = UINT64_MAX << (63 - end);
476 } else if (likely(end == 63)) {
477 ret = UINT64_MAX >> start;
478 }
479 #else
480 if (likely(start == 0)) {
481 ret = UINT32_MAX << (31 - end);
482 } else if (likely(end == 31)) {
483 ret = UINT32_MAX >> start;
484 }
485 #endif
486 else {
487 ret = (((target_ulong)(-1ULL)) >> (start)) ^
488 (((target_ulong)(-1ULL) >> (end)) >> 1);
489 if (unlikely(start > end))
490 return ~ret;
491 }
492
493 return ret;
494 }
495
496 EXTRACT_HELPER_SPLIT(xT, 0, 1, 21, 5);
497 EXTRACT_HELPER_SPLIT(xS, 0, 1, 21, 5);
498 EXTRACT_HELPER_SPLIT(xA, 2, 1, 16, 5);
499 EXTRACT_HELPER_SPLIT(xB, 1, 1, 11, 5);
500 EXTRACT_HELPER_SPLIT(xC, 3, 1, 6, 5);
501 EXTRACT_HELPER(DM, 8, 2);
502 EXTRACT_HELPER(UIM, 16, 2);
503 EXTRACT_HELPER(SHW, 8, 2);
504 /*****************************************************************************/
505 /* PowerPC instructions table */
506
507 #if defined(DO_PPC_STATISTICS)
508 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
509 { \
510 .opc1 = op1, \
511 .opc2 = op2, \
512 .opc3 = op3, \
513 .pad = { 0, }, \
514 .handler = { \
515 .inval1 = invl, \
516 .type = _typ, \
517 .type2 = _typ2, \
518 .handler = &gen_##name, \
519 .oname = stringify(name), \
520 }, \
521 .oname = stringify(name), \
522 }
523 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
524 { \
525 .opc1 = op1, \
526 .opc2 = op2, \
527 .opc3 = op3, \
528 .pad = { 0, }, \
529 .handler = { \
530 .inval1 = invl1, \
531 .inval2 = invl2, \
532 .type = _typ, \
533 .type2 = _typ2, \
534 .handler = &gen_##name, \
535 .oname = stringify(name), \
536 }, \
537 .oname = stringify(name), \
538 }
539 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
540 { \
541 .opc1 = op1, \
542 .opc2 = op2, \
543 .opc3 = op3, \
544 .pad = { 0, }, \
545 .handler = { \
546 .inval1 = invl, \
547 .type = _typ, \
548 .type2 = _typ2, \
549 .handler = &gen_##name, \
550 .oname = onam, \
551 }, \
552 .oname = onam, \
553 }
554 #else
555 #define GEN_OPCODE(name, op1, op2, op3, invl, _typ, _typ2) \
556 { \
557 .opc1 = op1, \
558 .opc2 = op2, \
559 .opc3 = op3, \
560 .pad = { 0, }, \
561 .handler = { \
562 .inval1 = invl, \
563 .type = _typ, \
564 .type2 = _typ2, \
565 .handler = &gen_##name, \
566 }, \
567 .oname = stringify(name), \
568 }
569 #define GEN_OPCODE_DUAL(name, op1, op2, op3, invl1, invl2, _typ, _typ2) \
570 { \
571 .opc1 = op1, \
572 .opc2 = op2, \
573 .opc3 = op3, \
574 .pad = { 0, }, \
575 .handler = { \
576 .inval1 = invl1, \
577 .inval2 = invl2, \
578 .type = _typ, \
579 .type2 = _typ2, \
580 .handler = &gen_##name, \
581 }, \
582 .oname = stringify(name), \
583 }
584 #define GEN_OPCODE2(name, onam, op1, op2, op3, invl, _typ, _typ2) \
585 { \
586 .opc1 = op1, \
587 .opc2 = op2, \
588 .opc3 = op3, \
589 .pad = { 0, }, \
590 .handler = { \
591 .inval1 = invl, \
592 .type = _typ, \
593 .type2 = _typ2, \
594 .handler = &gen_##name, \
595 }, \
596 .oname = onam, \
597 }
598 #endif
599
600 /* SPR load/store helpers */
601 static inline void gen_load_spr(TCGv t, int reg)
602 {
603 tcg_gen_ld_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
604 }
605
606 static inline void gen_store_spr(int reg, TCGv t)
607 {
608 tcg_gen_st_tl(t, cpu_env, offsetof(CPUPPCState, spr[reg]));
609 }
610
611 /* Invalid instruction */
612 static void gen_invalid(DisasContext *ctx)
613 {
614 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
615 }
616
617 static opc_handler_t invalid_handler = {
618 .inval1 = 0xFFFFFFFF,
619 .inval2 = 0xFFFFFFFF,
620 .type = PPC_NONE,
621 .type2 = PPC_NONE,
622 .handler = gen_invalid,
623 };
624
625 /*** Integer comparison ***/
626
627 static inline void gen_op_cmp(TCGv arg0, TCGv arg1, int s, int crf)
628 {
629 TCGv t0 = tcg_temp_new();
630 TCGv_i32 t1 = tcg_temp_new_i32();
631
632 tcg_gen_trunc_tl_i32(cpu_crf[crf], cpu_so);
633
634 tcg_gen_setcond_tl((s ? TCG_COND_LT: TCG_COND_LTU), t0, arg0, arg1);
635 tcg_gen_trunc_tl_i32(t1, t0);
636 tcg_gen_shli_i32(t1, t1, CRF_LT);
637 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
638
639 tcg_gen_setcond_tl((s ? TCG_COND_GT: TCG_COND_GTU), t0, arg0, arg1);
640 tcg_gen_trunc_tl_i32(t1, t0);
641 tcg_gen_shli_i32(t1, t1, CRF_GT);
642 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
643
644 tcg_gen_setcond_tl(TCG_COND_EQ, t0, arg0, arg1);
645 tcg_gen_trunc_tl_i32(t1, t0);
646 tcg_gen_shli_i32(t1, t1, CRF_EQ);
647 tcg_gen_or_i32(cpu_crf[crf], cpu_crf[crf], t1);
648
649 tcg_temp_free(t0);
650 tcg_temp_free_i32(t1);
651 }
652
653 static inline void gen_op_cmpi(TCGv arg0, target_ulong arg1, int s, int crf)
654 {
655 TCGv t0 = tcg_const_tl(arg1);
656 gen_op_cmp(arg0, t0, s, crf);
657 tcg_temp_free(t0);
658 }
659
660 static inline void gen_op_cmp32(TCGv arg0, TCGv arg1, int s, int crf)
661 {
662 TCGv t0, t1;
663 t0 = tcg_temp_new();
664 t1 = tcg_temp_new();
665 if (s) {
666 tcg_gen_ext32s_tl(t0, arg0);
667 tcg_gen_ext32s_tl(t1, arg1);
668 } else {
669 tcg_gen_ext32u_tl(t0, arg0);
670 tcg_gen_ext32u_tl(t1, arg1);
671 }
672 gen_op_cmp(t0, t1, s, crf);
673 tcg_temp_free(t1);
674 tcg_temp_free(t0);
675 }
676
677 static inline void gen_op_cmpi32(TCGv arg0, target_ulong arg1, int s, int crf)
678 {
679 TCGv t0 = tcg_const_tl(arg1);
680 gen_op_cmp32(arg0, t0, s, crf);
681 tcg_temp_free(t0);
682 }
683
684 static inline void gen_set_Rc0(DisasContext *ctx, TCGv reg)
685 {
686 if (NARROW_MODE(ctx)) {
687 gen_op_cmpi32(reg, 0, 1, 0);
688 } else {
689 gen_op_cmpi(reg, 0, 1, 0);
690 }
691 }
692
693 /* cmp */
694 static void gen_cmp(DisasContext *ctx)
695 {
696 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
697 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
698 1, crfD(ctx->opcode));
699 } else {
700 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
701 1, crfD(ctx->opcode));
702 }
703 }
704
705 /* cmpi */
706 static void gen_cmpi(DisasContext *ctx)
707 {
708 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
709 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
710 1, crfD(ctx->opcode));
711 } else {
712 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], SIMM(ctx->opcode),
713 1, crfD(ctx->opcode));
714 }
715 }
716
717 /* cmpl */
718 static void gen_cmpl(DisasContext *ctx)
719 {
720 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
721 gen_op_cmp(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
722 0, crfD(ctx->opcode));
723 } else {
724 gen_op_cmp32(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
725 0, crfD(ctx->opcode));
726 }
727 }
728
729 /* cmpli */
730 static void gen_cmpli(DisasContext *ctx)
731 {
732 if ((ctx->opcode & 0x00200000) && (ctx->insns_flags & PPC_64B)) {
733 gen_op_cmpi(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
734 0, crfD(ctx->opcode));
735 } else {
736 gen_op_cmpi32(cpu_gpr[rA(ctx->opcode)], UIMM(ctx->opcode),
737 0, crfD(ctx->opcode));
738 }
739 }
740
741 /* isel (PowerPC 2.03 specification) */
742 static void gen_isel(DisasContext *ctx)
743 {
744 int l1, l2;
745 uint32_t bi = rC(ctx->opcode);
746 uint32_t mask;
747 TCGv_i32 t0;
748
749 l1 = gen_new_label();
750 l2 = gen_new_label();
751
752 mask = 1 << (3 - (bi & 0x03));
753 t0 = tcg_temp_new_i32();
754 tcg_gen_andi_i32(t0, cpu_crf[bi >> 2], mask);
755 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
756 if (rA(ctx->opcode) == 0)
757 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
758 else
759 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
760 tcg_gen_br(l2);
761 gen_set_label(l1);
762 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
763 gen_set_label(l2);
764 tcg_temp_free_i32(t0);
765 }
766
767 /* cmpb: PowerPC 2.05 specification */
768 static void gen_cmpb(DisasContext *ctx)
769 {
770 gen_helper_cmpb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)],
771 cpu_gpr[rB(ctx->opcode)]);
772 }
773
774 /*** Integer arithmetic ***/
775
776 static inline void gen_op_arith_compute_ov(DisasContext *ctx, TCGv arg0,
777 TCGv arg1, TCGv arg2, int sub)
778 {
779 TCGv t0 = tcg_temp_new();
780
781 tcg_gen_xor_tl(cpu_ov, arg0, arg2);
782 tcg_gen_xor_tl(t0, arg1, arg2);
783 if (sub) {
784 tcg_gen_and_tl(cpu_ov, cpu_ov, t0);
785 } else {
786 tcg_gen_andc_tl(cpu_ov, cpu_ov, t0);
787 }
788 tcg_temp_free(t0);
789 if (NARROW_MODE(ctx)) {
790 tcg_gen_ext32s_tl(cpu_ov, cpu_ov);
791 }
792 tcg_gen_shri_tl(cpu_ov, cpu_ov, TARGET_LONG_BITS - 1);
793 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
794 }
795
796 /* Common add function */
797 static inline void gen_op_arith_add(DisasContext *ctx, TCGv ret, TCGv arg1,
798 TCGv arg2, bool add_ca, bool compute_ca,
799 bool compute_ov, bool compute_rc0)
800 {
801 TCGv t0 = ret;
802
803 if (compute_ca || compute_ov) {
804 t0 = tcg_temp_new();
805 }
806
807 if (compute_ca) {
808 if (NARROW_MODE(ctx)) {
809 /* Caution: a non-obvious corner case of the spec is that we
810 must produce the *entire* 64-bit addition, but produce the
811 carry into bit 32. */
812 TCGv t1 = tcg_temp_new();
813 tcg_gen_xor_tl(t1, arg1, arg2); /* add without carry */
814 tcg_gen_add_tl(t0, arg1, arg2);
815 if (add_ca) {
816 tcg_gen_add_tl(t0, t0, cpu_ca);
817 }
818 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changed w/ carry */
819 tcg_temp_free(t1);
820 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
821 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
822 } else {
823 TCGv zero = tcg_const_tl(0);
824 if (add_ca) {
825 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, cpu_ca, zero);
826 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, arg2, zero);
827 } else {
828 tcg_gen_add2_tl(t0, cpu_ca, arg1, zero, arg2, zero);
829 }
830 tcg_temp_free(zero);
831 }
832 } else {
833 tcg_gen_add_tl(t0, arg1, arg2);
834 if (add_ca) {
835 tcg_gen_add_tl(t0, t0, cpu_ca);
836 }
837 }
838
839 if (compute_ov) {
840 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 0);
841 }
842 if (unlikely(compute_rc0)) {
843 gen_set_Rc0(ctx, t0);
844 }
845
846 if (!TCGV_EQUAL(t0, ret)) {
847 tcg_gen_mov_tl(ret, t0);
848 tcg_temp_free(t0);
849 }
850 }
851 /* Add functions with two operands */
852 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
853 static void glue(gen_, name)(DisasContext *ctx) \
854 { \
855 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
856 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
857 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
858 }
859 /* Add functions with one operand and one immediate */
860 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
861 add_ca, compute_ca, compute_ov) \
862 static void glue(gen_, name)(DisasContext *ctx) \
863 { \
864 TCGv t0 = tcg_const_tl(const_val); \
865 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], \
866 cpu_gpr[rA(ctx->opcode)], t0, \
867 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
868 tcg_temp_free(t0); \
869 }
870
871 /* add add. addo addo. */
872 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
873 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
874 /* addc addc. addco addco. */
875 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
876 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
877 /* adde adde. addeo addeo. */
878 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
879 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
880 /* addme addme. addmeo addmeo. */
881 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
882 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
883 /* addze addze. addzeo addzeo.*/
884 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
885 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
886 /* addi */
887 static void gen_addi(DisasContext *ctx)
888 {
889 target_long simm = SIMM(ctx->opcode);
890
891 if (rA(ctx->opcode) == 0) {
892 /* li case */
893 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm);
894 } else {
895 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
896 cpu_gpr[rA(ctx->opcode)], simm);
897 }
898 }
899 /* addic addic.*/
900 static inline void gen_op_addic(DisasContext *ctx, bool compute_rc0)
901 {
902 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
903 gen_op_arith_add(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
904 c, 0, 1, 0, compute_rc0);
905 tcg_temp_free(c);
906 }
907
908 static void gen_addic(DisasContext *ctx)
909 {
910 gen_op_addic(ctx, 0);
911 }
912
913 static void gen_addic_(DisasContext *ctx)
914 {
915 gen_op_addic(ctx, 1);
916 }
917
918 /* addis */
919 static void gen_addis(DisasContext *ctx)
920 {
921 target_long simm = SIMM(ctx->opcode);
922
923 if (rA(ctx->opcode) == 0) {
924 /* lis case */
925 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], simm << 16);
926 } else {
927 tcg_gen_addi_tl(cpu_gpr[rD(ctx->opcode)],
928 cpu_gpr[rA(ctx->opcode)], simm << 16);
929 }
930 }
931
932 static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, TCGv arg1,
933 TCGv arg2, int sign, int compute_ov)
934 {
935 int l1 = gen_new_label();
936 int l2 = gen_new_label();
937 TCGv_i32 t0 = tcg_temp_local_new_i32();
938 TCGv_i32 t1 = tcg_temp_local_new_i32();
939
940 tcg_gen_trunc_tl_i32(t0, arg1);
941 tcg_gen_trunc_tl_i32(t1, arg2);
942 tcg_gen_brcondi_i32(TCG_COND_EQ, t1, 0, l1);
943 if (sign) {
944 int l3 = gen_new_label();
945 tcg_gen_brcondi_i32(TCG_COND_NE, t1, -1, l3);
946 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, INT32_MIN, l1);
947 gen_set_label(l3);
948 tcg_gen_div_i32(t0, t0, t1);
949 } else {
950 tcg_gen_divu_i32(t0, t0, t1);
951 }
952 if (compute_ov) {
953 tcg_gen_movi_tl(cpu_ov, 0);
954 }
955 tcg_gen_br(l2);
956 gen_set_label(l1);
957 if (sign) {
958 tcg_gen_sari_i32(t0, t0, 31);
959 } else {
960 tcg_gen_movi_i32(t0, 0);
961 }
962 if (compute_ov) {
963 tcg_gen_movi_tl(cpu_ov, 1);
964 tcg_gen_movi_tl(cpu_so, 1);
965 }
966 gen_set_label(l2);
967 tcg_gen_extu_i32_tl(ret, t0);
968 tcg_temp_free_i32(t0);
969 tcg_temp_free_i32(t1);
970 if (unlikely(Rc(ctx->opcode) != 0))
971 gen_set_Rc0(ctx, ret);
972 }
973 /* Div functions */
974 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
975 static void glue(gen_, name)(DisasContext *ctx) \
976 { \
977 gen_op_arith_divw(ctx, cpu_gpr[rD(ctx->opcode)], \
978 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
979 sign, compute_ov); \
980 }
981 /* divwu divwu. divwuo divwuo. */
982 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0);
983 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1);
984 /* divw divw. divwo divwo. */
985 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0);
986 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1);
987
988 /* div[wd]eu[o][.] */
989 #define GEN_DIVE(name, hlpr, compute_ov) \
990 static void gen_##name(DisasContext *ctx) \
991 { \
992 TCGv_i32 t0 = tcg_const_i32(compute_ov); \
993 gen_helper_##hlpr(cpu_gpr[rD(ctx->opcode)], cpu_env, \
994 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0); \
995 tcg_temp_free_i32(t0); \
996 if (unlikely(Rc(ctx->opcode) != 0)) { \
997 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]); \
998 } \
999 }
1000
1001 GEN_DIVE(divweu, divweu, 0);
1002 GEN_DIVE(divweuo, divweu, 1);
1003 GEN_DIVE(divwe, divwe, 0);
1004 GEN_DIVE(divweo, divwe, 1);
1005
1006 #if defined(TARGET_PPC64)
1007 static inline void gen_op_arith_divd(DisasContext *ctx, TCGv ret, TCGv arg1,
1008 TCGv arg2, int sign, int compute_ov)
1009 {
1010 int l1 = gen_new_label();
1011 int l2 = gen_new_label();
1012
1013 tcg_gen_brcondi_i64(TCG_COND_EQ, arg2, 0, l1);
1014 if (sign) {
1015 int l3 = gen_new_label();
1016 tcg_gen_brcondi_i64(TCG_COND_NE, arg2, -1, l3);
1017 tcg_gen_brcondi_i64(TCG_COND_EQ, arg1, INT64_MIN, l1);
1018 gen_set_label(l3);
1019 tcg_gen_div_i64(ret, arg1, arg2);
1020 } else {
1021 tcg_gen_divu_i64(ret, arg1, arg2);
1022 }
1023 if (compute_ov) {
1024 tcg_gen_movi_tl(cpu_ov, 0);
1025 }
1026 tcg_gen_br(l2);
1027 gen_set_label(l1);
1028 if (sign) {
1029 tcg_gen_sari_i64(ret, arg1, 63);
1030 } else {
1031 tcg_gen_movi_i64(ret, 0);
1032 }
1033 if (compute_ov) {
1034 tcg_gen_movi_tl(cpu_ov, 1);
1035 tcg_gen_movi_tl(cpu_so, 1);
1036 }
1037 gen_set_label(l2);
1038 if (unlikely(Rc(ctx->opcode) != 0))
1039 gen_set_Rc0(ctx, ret);
1040 }
1041 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
1042 static void glue(gen_, name)(DisasContext *ctx) \
1043 { \
1044 gen_op_arith_divd(ctx, cpu_gpr[rD(ctx->opcode)], \
1045 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1046 sign, compute_ov); \
1047 }
1048 /* divwu divwu. divwuo divwuo. */
1049 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0);
1050 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1);
1051 /* divw divw. divwo divwo. */
1052 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0);
1053 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1);
1054
1055 GEN_DIVE(divdeu, divdeu, 0);
1056 GEN_DIVE(divdeuo, divdeu, 1);
1057 GEN_DIVE(divde, divde, 0);
1058 GEN_DIVE(divdeo, divde, 1);
1059 #endif
1060
1061 /* mulhw mulhw. */
1062 static void gen_mulhw(DisasContext *ctx)
1063 {
1064 TCGv_i32 t0 = tcg_temp_new_i32();
1065 TCGv_i32 t1 = tcg_temp_new_i32();
1066
1067 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1068 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1069 tcg_gen_muls2_i32(t0, t1, t0, t1);
1070 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1071 tcg_temp_free_i32(t0);
1072 tcg_temp_free_i32(t1);
1073 if (unlikely(Rc(ctx->opcode) != 0))
1074 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1075 }
1076
1077 /* mulhwu mulhwu. */
1078 static void gen_mulhwu(DisasContext *ctx)
1079 {
1080 TCGv_i32 t0 = tcg_temp_new_i32();
1081 TCGv_i32 t1 = tcg_temp_new_i32();
1082
1083 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1084 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1085 tcg_gen_mulu2_i32(t0, t1, t0, t1);
1086 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t1);
1087 tcg_temp_free_i32(t0);
1088 tcg_temp_free_i32(t1);
1089 if (unlikely(Rc(ctx->opcode) != 0))
1090 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1091 }
1092
1093 /* mullw mullw. */
1094 static void gen_mullw(DisasContext *ctx)
1095 {
1096 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1097 cpu_gpr[rB(ctx->opcode)]);
1098 tcg_gen_ext32s_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)]);
1099 if (unlikely(Rc(ctx->opcode) != 0))
1100 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1101 }
1102
1103 /* mullwo mullwo. */
1104 static void gen_mullwo(DisasContext *ctx)
1105 {
1106 TCGv_i32 t0 = tcg_temp_new_i32();
1107 TCGv_i32 t1 = tcg_temp_new_i32();
1108
1109 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]);
1110 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]);
1111 tcg_gen_muls2_i32(t0, t1, t0, t1);
1112 tcg_gen_ext_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
1113
1114 tcg_gen_sari_i32(t0, t0, 31);
1115 tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t1);
1116 tcg_gen_extu_i32_tl(cpu_ov, t0);
1117 tcg_gen_or_tl(cpu_so, cpu_so, cpu_ov);
1118
1119 tcg_temp_free_i32(t0);
1120 tcg_temp_free_i32(t1);
1121 if (unlikely(Rc(ctx->opcode) != 0))
1122 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1123 }
1124
1125 /* mulli */
1126 static void gen_mulli(DisasContext *ctx)
1127 {
1128 tcg_gen_muli_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1129 SIMM(ctx->opcode));
1130 }
1131
1132 #if defined(TARGET_PPC64)
1133 /* mulhd mulhd. */
1134 static void gen_mulhd(DisasContext *ctx)
1135 {
1136 TCGv lo = tcg_temp_new();
1137 tcg_gen_muls2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1138 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1139 tcg_temp_free(lo);
1140 if (unlikely(Rc(ctx->opcode) != 0)) {
1141 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1142 }
1143 }
1144
1145 /* mulhdu mulhdu. */
1146 static void gen_mulhdu(DisasContext *ctx)
1147 {
1148 TCGv lo = tcg_temp_new();
1149 tcg_gen_mulu2_tl(lo, cpu_gpr[rD(ctx->opcode)],
1150 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1151 tcg_temp_free(lo);
1152 if (unlikely(Rc(ctx->opcode) != 0)) {
1153 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1154 }
1155 }
1156
1157 /* mulld mulld. */
1158 static void gen_mulld(DisasContext *ctx)
1159 {
1160 tcg_gen_mul_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1161 cpu_gpr[rB(ctx->opcode)]);
1162 if (unlikely(Rc(ctx->opcode) != 0))
1163 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1164 }
1165
1166 /* mulldo mulldo. */
1167 static void gen_mulldo(DisasContext *ctx)
1168 {
1169 gen_helper_mulldo(cpu_gpr[rD(ctx->opcode)], cpu_env,
1170 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1171 if (unlikely(Rc(ctx->opcode) != 0)) {
1172 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
1173 }
1174 }
1175 #endif
1176
1177 /* Common subf function */
1178 static inline void gen_op_arith_subf(DisasContext *ctx, TCGv ret, TCGv arg1,
1179 TCGv arg2, bool add_ca, bool compute_ca,
1180 bool compute_ov, bool compute_rc0)
1181 {
1182 TCGv t0 = ret;
1183
1184 if (compute_ca || compute_ov) {
1185 t0 = tcg_temp_new();
1186 }
1187
1188 if (compute_ca) {
1189 /* dest = ~arg1 + arg2 [+ ca]. */
1190 if (NARROW_MODE(ctx)) {
1191 /* Caution: a non-obvious corner case of the spec is that we
1192 must produce the *entire* 64-bit addition, but produce the
1193 carry into bit 32. */
1194 TCGv inv1 = tcg_temp_new();
1195 TCGv t1 = tcg_temp_new();
1196 tcg_gen_not_tl(inv1, arg1);
1197 if (add_ca) {
1198 tcg_gen_add_tl(t0, arg2, cpu_ca);
1199 } else {
1200 tcg_gen_addi_tl(t0, arg2, 1);
1201 }
1202 tcg_gen_xor_tl(t1, arg2, inv1); /* add without carry */
1203 tcg_gen_add_tl(t0, t0, inv1);
1204 tcg_gen_xor_tl(cpu_ca, t0, t1); /* bits changes w/ carry */
1205 tcg_temp_free(t1);
1206 tcg_gen_shri_tl(cpu_ca, cpu_ca, 32); /* extract bit 32 */
1207 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
1208 } else if (add_ca) {
1209 TCGv zero, inv1 = tcg_temp_new();
1210 tcg_gen_not_tl(inv1, arg1);
1211 zero = tcg_const_tl(0);
1212 tcg_gen_add2_tl(t0, cpu_ca, arg2, zero, cpu_ca, zero);
1213 tcg_gen_add2_tl(t0, cpu_ca, t0, cpu_ca, inv1, zero);
1214 tcg_temp_free(zero);
1215 tcg_temp_free(inv1);
1216 } else {
1217 tcg_gen_setcond_tl(TCG_COND_GEU, cpu_ca, arg2, arg1);
1218 tcg_gen_sub_tl(t0, arg2, arg1);
1219 }
1220 } else if (add_ca) {
1221 /* Since we're ignoring carry-out, we can simplify the
1222 standard ~arg1 + arg2 + ca to arg2 - arg1 + ca - 1. */
1223 tcg_gen_sub_tl(t0, arg2, arg1);
1224 tcg_gen_add_tl(t0, t0, cpu_ca);
1225 tcg_gen_subi_tl(t0, t0, 1);
1226 } else {
1227 tcg_gen_sub_tl(t0, arg2, arg1);
1228 }
1229
1230 if (compute_ov) {
1231 gen_op_arith_compute_ov(ctx, t0, arg1, arg2, 1);
1232 }
1233 if (unlikely(compute_rc0)) {
1234 gen_set_Rc0(ctx, t0);
1235 }
1236
1237 if (!TCGV_EQUAL(t0, ret)) {
1238 tcg_gen_mov_tl(ret, t0);
1239 tcg_temp_free(t0);
1240 }
1241 }
1242 /* Sub functions with Two operands functions */
1243 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
1244 static void glue(gen_, name)(DisasContext *ctx) \
1245 { \
1246 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1247 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
1248 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1249 }
1250 /* Sub functions with one operand and one immediate */
1251 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
1252 add_ca, compute_ca, compute_ov) \
1253 static void glue(gen_, name)(DisasContext *ctx) \
1254 { \
1255 TCGv t0 = tcg_const_tl(const_val); \
1256 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], \
1257 cpu_gpr[rA(ctx->opcode)], t0, \
1258 add_ca, compute_ca, compute_ov, Rc(ctx->opcode)); \
1259 tcg_temp_free(t0); \
1260 }
1261 /* subf subf. subfo subfo. */
1262 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
1263 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
1264 /* subfc subfc. subfco subfco. */
1265 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
1266 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
1267 /* subfe subfe. subfeo subfo. */
1268 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
1269 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
1270 /* subfme subfme. subfmeo subfmeo. */
1271 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
1272 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
1273 /* subfze subfze. subfzeo subfzeo.*/
1274 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
1275 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
1276
1277 /* subfic */
1278 static void gen_subfic(DisasContext *ctx)
1279 {
1280 TCGv c = tcg_const_tl(SIMM(ctx->opcode));
1281 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1282 c, 0, 1, 0, 0);
1283 tcg_temp_free(c);
1284 }
1285
1286 /* neg neg. nego nego. */
1287 static inline void gen_op_arith_neg(DisasContext *ctx, bool compute_ov)
1288 {
1289 TCGv zero = tcg_const_tl(0);
1290 gen_op_arith_subf(ctx, cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)],
1291 zero, 0, 0, compute_ov, Rc(ctx->opcode));
1292 tcg_temp_free(zero);
1293 }
1294
1295 static void gen_neg(DisasContext *ctx)
1296 {
1297 gen_op_arith_neg(ctx, 0);
1298 }
1299
1300 static void gen_nego(DisasContext *ctx)
1301 {
1302 gen_op_arith_neg(ctx, 1);
1303 }
1304
1305 /*** Integer logical ***/
1306 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
1307 static void glue(gen_, name)(DisasContext *ctx) \
1308 { \
1309 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], \
1310 cpu_gpr[rB(ctx->opcode)]); \
1311 if (unlikely(Rc(ctx->opcode) != 0)) \
1312 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1313 }
1314
1315 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
1316 static void glue(gen_, name)(DisasContext *ctx) \
1317 { \
1318 tcg_op(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]); \
1319 if (unlikely(Rc(ctx->opcode) != 0)) \
1320 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]); \
1321 }
1322
1323 /* and & and. */
1324 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER);
1325 /* andc & andc. */
1326 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER);
1327
1328 /* andi. */
1329 static void gen_andi_(DisasContext *ctx)
1330 {
1331 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode));
1332 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1333 }
1334
1335 /* andis. */
1336 static void gen_andis_(DisasContext *ctx)
1337 {
1338 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], UIMM(ctx->opcode) << 16);
1339 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1340 }
1341
1342 /* cntlzw */
1343 static void gen_cntlzw(DisasContext *ctx)
1344 {
1345 gen_helper_cntlzw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1346 if (unlikely(Rc(ctx->opcode) != 0))
1347 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1348 }
1349 /* eqv & eqv. */
1350 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER);
1351 /* extsb & extsb. */
1352 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER);
1353 /* extsh & extsh. */
1354 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER);
1355 /* nand & nand. */
1356 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER);
1357 /* nor & nor. */
1358 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER);
1359
1360 /* or & or. */
1361 static void gen_or(DisasContext *ctx)
1362 {
1363 int rs, ra, rb;
1364
1365 rs = rS(ctx->opcode);
1366 ra = rA(ctx->opcode);
1367 rb = rB(ctx->opcode);
1368 /* Optimisation for mr. ri case */
1369 if (rs != ra || rs != rb) {
1370 if (rs != rb)
1371 tcg_gen_or_tl(cpu_gpr[ra], cpu_gpr[rs], cpu_gpr[rb]);
1372 else
1373 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rs]);
1374 if (unlikely(Rc(ctx->opcode) != 0))
1375 gen_set_Rc0(ctx, cpu_gpr[ra]);
1376 } else if (unlikely(Rc(ctx->opcode) != 0)) {
1377 gen_set_Rc0(ctx, cpu_gpr[rs]);
1378 #if defined(TARGET_PPC64)
1379 } else {
1380 int prio = 0;
1381
1382 switch (rs) {
1383 case 1:
1384 /* Set process priority to low */
1385 prio = 2;
1386 break;
1387 case 6:
1388 /* Set process priority to medium-low */
1389 prio = 3;
1390 break;
1391 case 2:
1392 /* Set process priority to normal */
1393 prio = 4;
1394 break;
1395 #if !defined(CONFIG_USER_ONLY)
1396 case 31:
1397 if (ctx->mem_idx > 0) {
1398 /* Set process priority to very low */
1399 prio = 1;
1400 }
1401 break;
1402 case 5:
1403 if (ctx->mem_idx > 0) {
1404 /* Set process priority to medium-hight */
1405 prio = 5;
1406 }
1407 break;
1408 case 3:
1409 if (ctx->mem_idx > 0) {
1410 /* Set process priority to high */
1411 prio = 6;
1412 }
1413 break;
1414 case 7:
1415 if (ctx->mem_idx > 1) {
1416 /* Set process priority to very high */
1417 prio = 7;
1418 }
1419 break;
1420 #endif
1421 default:
1422 /* nop */
1423 break;
1424 }
1425 if (prio) {
1426 TCGv t0 = tcg_temp_new();
1427 gen_load_spr(t0, SPR_PPR);
1428 tcg_gen_andi_tl(t0, t0, ~0x001C000000000000ULL);
1429 tcg_gen_ori_tl(t0, t0, ((uint64_t)prio) << 50);
1430 gen_store_spr(SPR_PPR, t0);
1431 tcg_temp_free(t0);
1432 }
1433 #endif
1434 }
1435 }
1436 /* orc & orc. */
1437 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER);
1438
1439 /* xor & xor. */
1440 static void gen_xor(DisasContext *ctx)
1441 {
1442 /* Optimisation for "set to zero" case */
1443 if (rS(ctx->opcode) != rB(ctx->opcode))
1444 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1445 else
1446 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
1447 if (unlikely(Rc(ctx->opcode) != 0))
1448 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1449 }
1450
1451 /* ori */
1452 static void gen_ori(DisasContext *ctx)
1453 {
1454 target_ulong uimm = UIMM(ctx->opcode);
1455
1456 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1457 /* NOP */
1458 /* XXX: should handle special NOPs for POWER series */
1459 return;
1460 }
1461 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1462 }
1463
1464 /* oris */
1465 static void gen_oris(DisasContext *ctx)
1466 {
1467 target_ulong uimm = UIMM(ctx->opcode);
1468
1469 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1470 /* NOP */
1471 return;
1472 }
1473 tcg_gen_ori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1474 }
1475
1476 /* xori */
1477 static void gen_xori(DisasContext *ctx)
1478 {
1479 target_ulong uimm = UIMM(ctx->opcode);
1480
1481 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1482 /* NOP */
1483 return;
1484 }
1485 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm);
1486 }
1487
1488 /* xoris */
1489 static void gen_xoris(DisasContext *ctx)
1490 {
1491 target_ulong uimm = UIMM(ctx->opcode);
1492
1493 if (rS(ctx->opcode) == rA(ctx->opcode) && uimm == 0) {
1494 /* NOP */
1495 return;
1496 }
1497 tcg_gen_xori_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], uimm << 16);
1498 }
1499
1500 /* popcntb : PowerPC 2.03 specification */
1501 static void gen_popcntb(DisasContext *ctx)
1502 {
1503 gen_helper_popcntb(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1504 }
1505
1506 static void gen_popcntw(DisasContext *ctx)
1507 {
1508 gen_helper_popcntw(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1509 }
1510
1511 #if defined(TARGET_PPC64)
1512 /* popcntd: PowerPC 2.06 specification */
1513 static void gen_popcntd(DisasContext *ctx)
1514 {
1515 gen_helper_popcntd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1516 }
1517 #endif
1518
1519 /* prtyw: PowerPC 2.05 specification */
1520 static void gen_prtyw(DisasContext *ctx)
1521 {
1522 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1523 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1524 TCGv t0 = tcg_temp_new();
1525 tcg_gen_shri_tl(t0, rs, 16);
1526 tcg_gen_xor_tl(ra, rs, t0);
1527 tcg_gen_shri_tl(t0, ra, 8);
1528 tcg_gen_xor_tl(ra, ra, t0);
1529 tcg_gen_andi_tl(ra, ra, (target_ulong)0x100000001ULL);
1530 tcg_temp_free(t0);
1531 }
1532
1533 #if defined(TARGET_PPC64)
1534 /* prtyd: PowerPC 2.05 specification */
1535 static void gen_prtyd(DisasContext *ctx)
1536 {
1537 TCGv ra = cpu_gpr[rA(ctx->opcode)];
1538 TCGv rs = cpu_gpr[rS(ctx->opcode)];
1539 TCGv t0 = tcg_temp_new();
1540 tcg_gen_shri_tl(t0, rs, 32);
1541 tcg_gen_xor_tl(ra, rs, t0);
1542 tcg_gen_shri_tl(t0, ra, 16);
1543 tcg_gen_xor_tl(ra, ra, t0);
1544 tcg_gen_shri_tl(t0, ra, 8);
1545 tcg_gen_xor_tl(ra, ra, t0);
1546 tcg_gen_andi_tl(ra, ra, 1);
1547 tcg_temp_free(t0);
1548 }
1549 #endif
1550
1551 #if defined(TARGET_PPC64)
1552 /* bpermd */
1553 static void gen_bpermd(DisasContext *ctx)
1554 {
1555 gen_helper_bpermd(cpu_gpr[rA(ctx->opcode)],
1556 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1557 }
1558 #endif
1559
1560 #if defined(TARGET_PPC64)
1561 /* extsw & extsw. */
1562 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B);
1563
1564 /* cntlzd */
1565 static void gen_cntlzd(DisasContext *ctx)
1566 {
1567 gen_helper_cntlzd(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1568 if (unlikely(Rc(ctx->opcode) != 0))
1569 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1570 }
1571 #endif
1572
1573 /*** Integer rotate ***/
1574
1575 /* rlwimi & rlwimi. */
1576 static void gen_rlwimi(DisasContext *ctx)
1577 {
1578 uint32_t mb, me, sh;
1579
1580 mb = MB(ctx->opcode);
1581 me = ME(ctx->opcode);
1582 sh = SH(ctx->opcode);
1583 if (likely(sh == 0 && mb == 0 && me == 31)) {
1584 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1585 } else {
1586 target_ulong mask;
1587 TCGv t1;
1588 TCGv t0 = tcg_temp_new();
1589 #if defined(TARGET_PPC64)
1590 TCGv_i32 t2 = tcg_temp_new_i32();
1591 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rS(ctx->opcode)]);
1592 tcg_gen_rotli_i32(t2, t2, sh);
1593 tcg_gen_extu_i32_i64(t0, t2);
1594 tcg_temp_free_i32(t2);
1595 #else
1596 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1597 #endif
1598 #if defined(TARGET_PPC64)
1599 mb += 32;
1600 me += 32;
1601 #endif
1602 mask = MASK(mb, me);
1603 t1 = tcg_temp_new();
1604 tcg_gen_andi_tl(t0, t0, mask);
1605 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1606 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1607 tcg_temp_free(t0);
1608 tcg_temp_free(t1);
1609 }
1610 if (unlikely(Rc(ctx->opcode) != 0))
1611 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1612 }
1613
1614 /* rlwinm & rlwinm. */
1615 static void gen_rlwinm(DisasContext *ctx)
1616 {
1617 uint32_t mb, me, sh;
1618
1619 sh = SH(ctx->opcode);
1620 mb = MB(ctx->opcode);
1621 me = ME(ctx->opcode);
1622
1623 if (likely(mb == 0 && me == (31 - sh))) {
1624 if (likely(sh == 0)) {
1625 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1626 } else {
1627 TCGv t0 = tcg_temp_new();
1628 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1629 tcg_gen_shli_tl(t0, t0, sh);
1630 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1631 tcg_temp_free(t0);
1632 }
1633 } else if (likely(sh != 0 && me == 31 && sh == (32 - mb))) {
1634 TCGv t0 = tcg_temp_new();
1635 tcg_gen_ext32u_tl(t0, cpu_gpr[rS(ctx->opcode)]);
1636 tcg_gen_shri_tl(t0, t0, mb);
1637 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], t0);
1638 tcg_temp_free(t0);
1639 } else {
1640 TCGv t0 = tcg_temp_new();
1641 #if defined(TARGET_PPC64)
1642 TCGv_i32 t1 = tcg_temp_new_i32();
1643 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1644 tcg_gen_rotli_i32(t1, t1, sh);
1645 tcg_gen_extu_i32_i64(t0, t1);
1646 tcg_temp_free_i32(t1);
1647 #else
1648 tcg_gen_rotli_i32(t0, cpu_gpr[rS(ctx->opcode)], sh);
1649 #endif
1650 #if defined(TARGET_PPC64)
1651 mb += 32;
1652 me += 32;
1653 #endif
1654 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1655 tcg_temp_free(t0);
1656 }
1657 if (unlikely(Rc(ctx->opcode) != 0))
1658 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1659 }
1660
1661 /* rlwnm & rlwnm. */
1662 static void gen_rlwnm(DisasContext *ctx)
1663 {
1664 uint32_t mb, me;
1665 TCGv t0;
1666 #if defined(TARGET_PPC64)
1667 TCGv_i32 t1, t2;
1668 #endif
1669
1670 mb = MB(ctx->opcode);
1671 me = ME(ctx->opcode);
1672 t0 = tcg_temp_new();
1673 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1f);
1674 #if defined(TARGET_PPC64)
1675 t1 = tcg_temp_new_i32();
1676 t2 = tcg_temp_new_i32();
1677 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rS(ctx->opcode)]);
1678 tcg_gen_trunc_i64_i32(t2, t0);
1679 tcg_gen_rotl_i32(t1, t1, t2);
1680 tcg_gen_extu_i32_i64(t0, t1);
1681 tcg_temp_free_i32(t1);
1682 tcg_temp_free_i32(t2);
1683 #else
1684 tcg_gen_rotl_i32(t0, cpu_gpr[rS(ctx->opcode)], t0);
1685 #endif
1686 if (unlikely(mb != 0 || me != 31)) {
1687 #if defined(TARGET_PPC64)
1688 mb += 32;
1689 me += 32;
1690 #endif
1691 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1692 } else {
1693 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1694 }
1695 tcg_temp_free(t0);
1696 if (unlikely(Rc(ctx->opcode) != 0))
1697 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1698 }
1699
1700 #if defined(TARGET_PPC64)
1701 #define GEN_PPC64_R2(name, opc1, opc2) \
1702 static void glue(gen_, name##0)(DisasContext *ctx) \
1703 { \
1704 gen_##name(ctx, 0); \
1705 } \
1706 \
1707 static void glue(gen_, name##1)(DisasContext *ctx) \
1708 { \
1709 gen_##name(ctx, 1); \
1710 }
1711 #define GEN_PPC64_R4(name, opc1, opc2) \
1712 static void glue(gen_, name##0)(DisasContext *ctx) \
1713 { \
1714 gen_##name(ctx, 0, 0); \
1715 } \
1716 \
1717 static void glue(gen_, name##1)(DisasContext *ctx) \
1718 { \
1719 gen_##name(ctx, 0, 1); \
1720 } \
1721 \
1722 static void glue(gen_, name##2)(DisasContext *ctx) \
1723 { \
1724 gen_##name(ctx, 1, 0); \
1725 } \
1726 \
1727 static void glue(gen_, name##3)(DisasContext *ctx) \
1728 { \
1729 gen_##name(ctx, 1, 1); \
1730 }
1731
1732 static inline void gen_rldinm(DisasContext *ctx, uint32_t mb, uint32_t me,
1733 uint32_t sh)
1734 {
1735 if (likely(sh != 0 && mb == 0 && me == (63 - sh))) {
1736 tcg_gen_shli_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
1737 } else if (likely(sh != 0 && me == 63 && sh == (64 - mb))) {
1738 tcg_gen_shri_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], mb);
1739 } else {
1740 TCGv t0 = tcg_temp_new();
1741 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1742 if (likely(mb == 0 && me == 63)) {
1743 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1744 } else {
1745 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1746 }
1747 tcg_temp_free(t0);
1748 }
1749 if (unlikely(Rc(ctx->opcode) != 0))
1750 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1751 }
1752 /* rldicl - rldicl. */
1753 static inline void gen_rldicl(DisasContext *ctx, int mbn, int shn)
1754 {
1755 uint32_t sh, mb;
1756
1757 sh = SH(ctx->opcode) | (shn << 5);
1758 mb = MB(ctx->opcode) | (mbn << 5);
1759 gen_rldinm(ctx, mb, 63, sh);
1760 }
1761 GEN_PPC64_R4(rldicl, 0x1E, 0x00);
1762 /* rldicr - rldicr. */
1763 static inline void gen_rldicr(DisasContext *ctx, int men, int shn)
1764 {
1765 uint32_t sh, me;
1766
1767 sh = SH(ctx->opcode) | (shn << 5);
1768 me = MB(ctx->opcode) | (men << 5);
1769 gen_rldinm(ctx, 0, me, sh);
1770 }
1771 GEN_PPC64_R4(rldicr, 0x1E, 0x02);
1772 /* rldic - rldic. */
1773 static inline void gen_rldic(DisasContext *ctx, int mbn, int shn)
1774 {
1775 uint32_t sh, mb;
1776
1777 sh = SH(ctx->opcode) | (shn << 5);
1778 mb = MB(ctx->opcode) | (mbn << 5);
1779 gen_rldinm(ctx, mb, 63 - sh, sh);
1780 }
1781 GEN_PPC64_R4(rldic, 0x1E, 0x04);
1782
1783 static inline void gen_rldnm(DisasContext *ctx, uint32_t mb, uint32_t me)
1784 {
1785 TCGv t0;
1786
1787 t0 = tcg_temp_new();
1788 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3f);
1789 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1790 if (unlikely(mb != 0 || me != 63)) {
1791 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], t0, MASK(mb, me));
1792 } else {
1793 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
1794 }
1795 tcg_temp_free(t0);
1796 if (unlikely(Rc(ctx->opcode) != 0))
1797 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1798 }
1799
1800 /* rldcl - rldcl. */
1801 static inline void gen_rldcl(DisasContext *ctx, int mbn)
1802 {
1803 uint32_t mb;
1804
1805 mb = MB(ctx->opcode) | (mbn << 5);
1806 gen_rldnm(ctx, mb, 63);
1807 }
1808 GEN_PPC64_R2(rldcl, 0x1E, 0x08);
1809 /* rldcr - rldcr. */
1810 static inline void gen_rldcr(DisasContext *ctx, int men)
1811 {
1812 uint32_t me;
1813
1814 me = MB(ctx->opcode) | (men << 5);
1815 gen_rldnm(ctx, 0, me);
1816 }
1817 GEN_PPC64_R2(rldcr, 0x1E, 0x09);
1818 /* rldimi - rldimi. */
1819 static inline void gen_rldimi(DisasContext *ctx, int mbn, int shn)
1820 {
1821 uint32_t sh, mb, me;
1822
1823 sh = SH(ctx->opcode) | (shn << 5);
1824 mb = MB(ctx->opcode) | (mbn << 5);
1825 me = 63 - sh;
1826 if (unlikely(sh == 0 && mb == 0)) {
1827 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)]);
1828 } else {
1829 TCGv t0, t1;
1830 target_ulong mask;
1831
1832 t0 = tcg_temp_new();
1833 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
1834 t1 = tcg_temp_new();
1835 mask = MASK(mb, me);
1836 tcg_gen_andi_tl(t0, t0, mask);
1837 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], ~mask);
1838 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1839 tcg_temp_free(t0);
1840 tcg_temp_free(t1);
1841 }
1842 if (unlikely(Rc(ctx->opcode) != 0))
1843 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1844 }
1845 GEN_PPC64_R4(rldimi, 0x1E, 0x06);
1846 #endif
1847
1848 /*** Integer shift ***/
1849
1850 /* slw & slw. */
1851 static void gen_slw(DisasContext *ctx)
1852 {
1853 TCGv t0, t1;
1854
1855 t0 = tcg_temp_new();
1856 /* AND rS with a mask that is 0 when rB >= 0x20 */
1857 #if defined(TARGET_PPC64)
1858 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1859 tcg_gen_sari_tl(t0, t0, 0x3f);
1860 #else
1861 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1862 tcg_gen_sari_tl(t0, t0, 0x1f);
1863 #endif
1864 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1865 t1 = tcg_temp_new();
1866 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1867 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1868 tcg_temp_free(t1);
1869 tcg_temp_free(t0);
1870 tcg_gen_ext32u_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
1871 if (unlikely(Rc(ctx->opcode) != 0))
1872 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1873 }
1874
1875 /* sraw & sraw. */
1876 static void gen_sraw(DisasContext *ctx)
1877 {
1878 gen_helper_sraw(cpu_gpr[rA(ctx->opcode)], cpu_env,
1879 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1880 if (unlikely(Rc(ctx->opcode) != 0))
1881 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1882 }
1883
1884 /* srawi & srawi. */
1885 static void gen_srawi(DisasContext *ctx)
1886 {
1887 int sh = SH(ctx->opcode);
1888 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1889 TCGv src = cpu_gpr[rS(ctx->opcode)];
1890 if (sh == 0) {
1891 tcg_gen_mov_tl(dst, src);
1892 tcg_gen_movi_tl(cpu_ca, 0);
1893 } else {
1894 TCGv t0;
1895 tcg_gen_ext32s_tl(dst, src);
1896 tcg_gen_andi_tl(cpu_ca, dst, (1ULL << sh) - 1);
1897 t0 = tcg_temp_new();
1898 tcg_gen_sari_tl(t0, dst, TARGET_LONG_BITS - 1);
1899 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1900 tcg_temp_free(t0);
1901 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1902 tcg_gen_sari_tl(dst, dst, sh);
1903 }
1904 if (unlikely(Rc(ctx->opcode) != 0)) {
1905 gen_set_Rc0(ctx, dst);
1906 }
1907 }
1908
1909 /* srw & srw. */
1910 static void gen_srw(DisasContext *ctx)
1911 {
1912 TCGv t0, t1;
1913
1914 t0 = tcg_temp_new();
1915 /* AND rS with a mask that is 0 when rB >= 0x20 */
1916 #if defined(TARGET_PPC64)
1917 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x3a);
1918 tcg_gen_sari_tl(t0, t0, 0x3f);
1919 #else
1920 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1a);
1921 tcg_gen_sari_tl(t0, t0, 0x1f);
1922 #endif
1923 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1924 tcg_gen_ext32u_tl(t0, t0);
1925 t1 = tcg_temp_new();
1926 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1f);
1927 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1928 tcg_temp_free(t1);
1929 tcg_temp_free(t0);
1930 if (unlikely(Rc(ctx->opcode) != 0))
1931 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1932 }
1933
1934 #if defined(TARGET_PPC64)
1935 /* sld & sld. */
1936 static void gen_sld(DisasContext *ctx)
1937 {
1938 TCGv t0, t1;
1939
1940 t0 = tcg_temp_new();
1941 /* AND rS with a mask that is 0 when rB >= 0x40 */
1942 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
1943 tcg_gen_sari_tl(t0, t0, 0x3f);
1944 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
1945 t1 = tcg_temp_new();
1946 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
1947 tcg_gen_shl_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
1948 tcg_temp_free(t1);
1949 tcg_temp_free(t0);
1950 if (unlikely(Rc(ctx->opcode) != 0))
1951 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1952 }
1953
1954 /* srad & srad. */
1955 static void gen_srad(DisasContext *ctx)
1956 {
1957 gen_helper_srad(cpu_gpr[rA(ctx->opcode)], cpu_env,
1958 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
1959 if (unlikely(Rc(ctx->opcode) != 0))
1960 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
1961 }
1962 /* sradi & sradi. */
1963 static inline void gen_sradi(DisasContext *ctx, int n)
1964 {
1965 int sh = SH(ctx->opcode) + (n << 5);
1966 TCGv dst = cpu_gpr[rA(ctx->opcode)];
1967 TCGv src = cpu_gpr[rS(ctx->opcode)];
1968 if (sh == 0) {
1969 tcg_gen_mov_tl(dst, src);
1970 tcg_gen_movi_tl(cpu_ca, 0);
1971 } else {
1972 TCGv t0;
1973 tcg_gen_andi_tl(cpu_ca, src, (1ULL << sh) - 1);
1974 t0 = tcg_temp_new();
1975 tcg_gen_sari_tl(t0, src, TARGET_LONG_BITS - 1);
1976 tcg_gen_and_tl(cpu_ca, cpu_ca, t0);
1977 tcg_temp_free(t0);
1978 tcg_gen_setcondi_tl(TCG_COND_NE, cpu_ca, cpu_ca, 0);
1979 tcg_gen_sari_tl(dst, src, sh);
1980 }
1981 if (unlikely(Rc(ctx->opcode) != 0)) {
1982 gen_set_Rc0(ctx, dst);
1983 }
1984 }
1985
1986 static void gen_sradi0(DisasContext *ctx)
1987 {
1988 gen_sradi(ctx, 0);
1989 }
1990
1991 static void gen_sradi1(DisasContext *ctx)
1992 {
1993 gen_sradi(ctx, 1);
1994 }
1995
1996 /* srd & srd. */
1997 static void gen_srd(DisasContext *ctx)
1998 {
1999 TCGv t0, t1;
2000
2001 t0 = tcg_temp_new();
2002 /* AND rS with a mask that is 0 when rB >= 0x40 */
2003 tcg_gen_shli_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x39);
2004 tcg_gen_sari_tl(t0, t0, 0x3f);
2005 tcg_gen_andc_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
2006 t1 = tcg_temp_new();
2007 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x3f);
2008 tcg_gen_shr_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
2009 tcg_temp_free(t1);
2010 tcg_temp_free(t0);
2011 if (unlikely(Rc(ctx->opcode) != 0))
2012 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
2013 }
2014 #endif
2015
2016 /*** Floating-Point arithmetic ***/
2017 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
2018 static void gen_f##name(DisasContext *ctx) \
2019 { \
2020 if (unlikely(!ctx->fpu_enabled)) { \
2021 gen_exception(ctx, POWERPC_EXCP_FPU); \
2022 return; \
2023 } \
2024 /* NIP cannot be restored if the memory exception comes from an helper */ \
2025 gen_update_nip(ctx, ctx->nip - 4); \
2026 gen_reset_fpstatus(); \
2027 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2028 cpu_fpr[rA(ctx->opcode)], \
2029 cpu_fpr[rC(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]); \
2030 if (isfloat) { \
2031 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2032 cpu_fpr[rD(ctx->opcode)]); \
2033 } \
2034 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], set_fprf, \
2035 Rc(ctx->opcode) != 0); \
2036 }
2037
2038 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
2039 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type); \
2040 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type);
2041
2042 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2043 static void gen_f##name(DisasContext *ctx) \
2044 { \
2045 if (unlikely(!ctx->fpu_enabled)) { \
2046 gen_exception(ctx, POWERPC_EXCP_FPU); \
2047 return; \
2048 } \
2049 /* NIP cannot be restored if the memory exception comes from an helper */ \
2050 gen_update_nip(ctx, ctx->nip - 4); \
2051 gen_reset_fpstatus(); \
2052 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2053 cpu_fpr[rA(ctx->opcode)], \
2054 cpu_fpr[rB(ctx->opcode)]); \
2055 if (isfloat) { \
2056 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2057 cpu_fpr[rD(ctx->opcode)]); \
2058 } \
2059 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2060 set_fprf, Rc(ctx->opcode) != 0); \
2061 }
2062 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
2063 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2064 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2065
2066 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
2067 static void gen_f##name(DisasContext *ctx) \
2068 { \
2069 if (unlikely(!ctx->fpu_enabled)) { \
2070 gen_exception(ctx, POWERPC_EXCP_FPU); \
2071 return; \
2072 } \
2073 /* NIP cannot be restored if the memory exception comes from an helper */ \
2074 gen_update_nip(ctx, ctx->nip - 4); \
2075 gen_reset_fpstatus(); \
2076 gen_helper_f##op(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2077 cpu_fpr[rA(ctx->opcode)], \
2078 cpu_fpr[rC(ctx->opcode)]); \
2079 if (isfloat) { \
2080 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2081 cpu_fpr[rD(ctx->opcode)]); \
2082 } \
2083 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2084 set_fprf, Rc(ctx->opcode) != 0); \
2085 }
2086 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
2087 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type); \
2088 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type);
2089
2090 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
2091 static void gen_f##name(DisasContext *ctx) \
2092 { \
2093 if (unlikely(!ctx->fpu_enabled)) { \
2094 gen_exception(ctx, POWERPC_EXCP_FPU); \
2095 return; \
2096 } \
2097 /* NIP cannot be restored if the memory exception comes from an helper */ \
2098 gen_update_nip(ctx, ctx->nip - 4); \
2099 gen_reset_fpstatus(); \
2100 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2101 cpu_fpr[rB(ctx->opcode)]); \
2102 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2103 set_fprf, Rc(ctx->opcode) != 0); \
2104 }
2105
2106 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
2107 static void gen_f##name(DisasContext *ctx) \
2108 { \
2109 if (unlikely(!ctx->fpu_enabled)) { \
2110 gen_exception(ctx, POWERPC_EXCP_FPU); \
2111 return; \
2112 } \
2113 /* NIP cannot be restored if the memory exception comes from an helper */ \
2114 gen_update_nip(ctx, ctx->nip - 4); \
2115 gen_reset_fpstatus(); \
2116 gen_helper_f##name(cpu_fpr[rD(ctx->opcode)], cpu_env, \
2117 cpu_fpr[rB(ctx->opcode)]); \
2118 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], \
2119 set_fprf, Rc(ctx->opcode) != 0); \
2120 }
2121
2122 /* fadd - fadds */
2123 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT);
2124 /* fdiv - fdivs */
2125 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT);
2126 /* fmul - fmuls */
2127 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT);
2128
2129 /* fre */
2130 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT);
2131
2132 /* fres */
2133 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES);
2134
2135 /* frsqrte */
2136 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE);
2137
2138 /* frsqrtes */
2139 static void gen_frsqrtes(DisasContext *ctx)
2140 {
2141 if (unlikely(!ctx->fpu_enabled)) {
2142 gen_exception(ctx, POWERPC_EXCP_FPU);
2143 return;
2144 }
2145 /* NIP cannot be restored if the memory exception comes from an helper */
2146 gen_update_nip(ctx, ctx->nip - 4);
2147 gen_reset_fpstatus();
2148 gen_helper_frsqrte(cpu_fpr[rD(ctx->opcode)], cpu_env,
2149 cpu_fpr[rB(ctx->opcode)]);
2150 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2151 cpu_fpr[rD(ctx->opcode)]);
2152 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2153 }
2154
2155 /* fsel */
2156 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL);
2157 /* fsub - fsubs */
2158 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT);
2159 /* Optional: */
2160
2161 /* fsqrt */
2162 static void gen_fsqrt(DisasContext *ctx)
2163 {
2164 if (unlikely(!ctx->fpu_enabled)) {
2165 gen_exception(ctx, POWERPC_EXCP_FPU);
2166 return;
2167 }
2168 /* NIP cannot be restored if the memory exception comes from an helper */
2169 gen_update_nip(ctx, ctx->nip - 4);
2170 gen_reset_fpstatus();
2171 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2172 cpu_fpr[rB(ctx->opcode)]);
2173 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2174 }
2175
2176 static void gen_fsqrts(DisasContext *ctx)
2177 {
2178 if (unlikely(!ctx->fpu_enabled)) {
2179 gen_exception(ctx, POWERPC_EXCP_FPU);
2180 return;
2181 }
2182 /* NIP cannot be restored if the memory exception comes from an helper */
2183 gen_update_nip(ctx, ctx->nip - 4);
2184 gen_reset_fpstatus();
2185 gen_helper_fsqrt(cpu_fpr[rD(ctx->opcode)], cpu_env,
2186 cpu_fpr[rB(ctx->opcode)]);
2187 gen_helper_frsp(cpu_fpr[rD(ctx->opcode)], cpu_env,
2188 cpu_fpr[rD(ctx->opcode)]);
2189 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 1, Rc(ctx->opcode) != 0);
2190 }
2191
2192 /*** Floating-Point multiply-and-add ***/
2193 /* fmadd - fmadds */
2194 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT);
2195 /* fmsub - fmsubs */
2196 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT);
2197 /* fnmadd - fnmadds */
2198 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT);
2199 /* fnmsub - fnmsubs */
2200 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT);
2201
2202 /*** Floating-Point round & convert ***/
2203 /* fctiw */
2204 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT);
2205 /* fctiwu */
2206 GEN_FLOAT_B(ctiwu, 0x0E, 0x04, 0, PPC2_FP_CVT_ISA206);
2207 /* fctiwz */
2208 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT);
2209 /* fctiwuz */
2210 GEN_FLOAT_B(ctiwuz, 0x0F, 0x04, 0, PPC2_FP_CVT_ISA206);
2211 /* frsp */
2212 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT);
2213 #if defined(TARGET_PPC64)
2214 /* fcfid */
2215 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B);
2216 /* fcfids */
2217 GEN_FLOAT_B(cfids, 0x0E, 0x1A, 0, PPC2_FP_CVT_ISA206);
2218 /* fcfidu */
2219 GEN_FLOAT_B(cfidu, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2220 /* fcfidus */
2221 GEN_FLOAT_B(cfidus, 0x0E, 0x1E, 0, PPC2_FP_CVT_ISA206);
2222 /* fctid */
2223 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B);
2224 /* fctidu */
2225 GEN_FLOAT_B(ctidu, 0x0E, 0x1D, 0, PPC2_FP_CVT_ISA206);
2226 /* fctidz */
2227 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B);
2228 /* fctidu */
2229 GEN_FLOAT_B(ctiduz, 0x0F, 0x1D, 0, PPC2_FP_CVT_ISA206);
2230 #endif
2231
2232 /* frin */
2233 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT);
2234 /* friz */
2235 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT);
2236 /* frip */
2237 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT);
2238 /* frim */
2239 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT);
2240
2241 static void gen_ftdiv(DisasContext *ctx)
2242 {
2243 if (unlikely(!ctx->fpu_enabled)) {
2244 gen_exception(ctx, POWERPC_EXCP_FPU);
2245 return;
2246 }
2247 gen_helper_ftdiv(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2248 cpu_fpr[rB(ctx->opcode)]);
2249 }
2250
2251 static void gen_ftsqrt(DisasContext *ctx)
2252 {
2253 if (unlikely(!ctx->fpu_enabled)) {
2254 gen_exception(ctx, POWERPC_EXCP_FPU);
2255 return;
2256 }
2257 gen_helper_ftsqrt(cpu_crf[crfD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2258 }
2259
2260
2261
2262 /*** Floating-Point compare ***/
2263
2264 /* fcmpo */
2265 static void gen_fcmpo(DisasContext *ctx)
2266 {
2267 TCGv_i32 crf;
2268 if (unlikely(!ctx->fpu_enabled)) {
2269 gen_exception(ctx, POWERPC_EXCP_FPU);
2270 return;
2271 }
2272 /* NIP cannot be restored if the memory exception comes from an helper */
2273 gen_update_nip(ctx, ctx->nip - 4);
2274 gen_reset_fpstatus();
2275 crf = tcg_const_i32(crfD(ctx->opcode));
2276 gen_helper_fcmpo(cpu_env, cpu_fpr[rA(ctx->opcode)],
2277 cpu_fpr[rB(ctx->opcode)], crf);
2278 tcg_temp_free_i32(crf);
2279 gen_helper_float_check_status(cpu_env);
2280 }
2281
2282 /* fcmpu */
2283 static void gen_fcmpu(DisasContext *ctx)
2284 {
2285 TCGv_i32 crf;
2286 if (unlikely(!ctx->fpu_enabled)) {
2287 gen_exception(ctx, POWERPC_EXCP_FPU);
2288 return;
2289 }
2290 /* NIP cannot be restored if the memory exception comes from an helper */
2291 gen_update_nip(ctx, ctx->nip - 4);
2292 gen_reset_fpstatus();
2293 crf = tcg_const_i32(crfD(ctx->opcode));
2294 gen_helper_fcmpu(cpu_env, cpu_fpr[rA(ctx->opcode)],
2295 cpu_fpr[rB(ctx->opcode)], crf);
2296 tcg_temp_free_i32(crf);
2297 gen_helper_float_check_status(cpu_env);
2298 }
2299
2300 /*** Floating-point move ***/
2301 /* fabs */
2302 /* XXX: beware that fabs never checks for NaNs nor update FPSCR */
2303 static void gen_fabs(DisasContext *ctx)
2304 {
2305 if (unlikely(!ctx->fpu_enabled)) {
2306 gen_exception(ctx, POWERPC_EXCP_FPU);
2307 return;
2308 }
2309 tcg_gen_andi_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2310 ~(1ULL << 63));
2311 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2312 }
2313
2314 /* fmr - fmr. */
2315 /* XXX: beware that fmr never checks for NaNs nor update FPSCR */
2316 static void gen_fmr(DisasContext *ctx)
2317 {
2318 if (unlikely(!ctx->fpu_enabled)) {
2319 gen_exception(ctx, POWERPC_EXCP_FPU);
2320 return;
2321 }
2322 tcg_gen_mov_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)]);
2323 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2324 }
2325
2326 /* fnabs */
2327 /* XXX: beware that fnabs never checks for NaNs nor update FPSCR */
2328 static void gen_fnabs(DisasContext *ctx)
2329 {
2330 if (unlikely(!ctx->fpu_enabled)) {
2331 gen_exception(ctx, POWERPC_EXCP_FPU);
2332 return;
2333 }
2334 tcg_gen_ori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2335 1ULL << 63);
2336 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2337 }
2338
2339 /* fneg */
2340 /* XXX: beware that fneg never checks for NaNs nor update FPSCR */
2341 static void gen_fneg(DisasContext *ctx)
2342 {
2343 if (unlikely(!ctx->fpu_enabled)) {
2344 gen_exception(ctx, POWERPC_EXCP_FPU);
2345 return;
2346 }
2347 tcg_gen_xori_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rB(ctx->opcode)],
2348 1ULL << 63);
2349 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2350 }
2351
2352 /* fcpsgn: PowerPC 2.05 specification */
2353 /* XXX: beware that fcpsgn never checks for NaNs nor update FPSCR */
2354 static void gen_fcpsgn(DisasContext *ctx)
2355 {
2356 if (unlikely(!ctx->fpu_enabled)) {
2357 gen_exception(ctx, POWERPC_EXCP_FPU);
2358 return;
2359 }
2360 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2361 cpu_fpr[rB(ctx->opcode)], 0, 63);
2362 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2363 }
2364
2365 static void gen_fmrgew(DisasContext *ctx)
2366 {
2367 TCGv_i64 b0;
2368 if (unlikely(!ctx->fpu_enabled)) {
2369 gen_exception(ctx, POWERPC_EXCP_FPU);
2370 return;
2371 }
2372 b0 = tcg_temp_new_i64();
2373 tcg_gen_shri_i64(b0, cpu_fpr[rB(ctx->opcode)], 32);
2374 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpr[rA(ctx->opcode)],
2375 b0, 0, 32);
2376 tcg_temp_free_i64(b0);
2377 }
2378
2379 static void gen_fmrgow(DisasContext *ctx)
2380 {
2381 if (unlikely(!ctx->fpu_enabled)) {
2382 gen_exception(ctx, POWERPC_EXCP_FPU);
2383 return;
2384 }
2385 tcg_gen_deposit_i64(cpu_fpr[rD(ctx->opcode)],
2386 cpu_fpr[rB(ctx->opcode)],
2387 cpu_fpr[rA(ctx->opcode)],
2388 32, 32);
2389 }
2390
2391 /*** Floating-Point status & ctrl register ***/
2392
2393 /* mcrfs */
2394 static void gen_mcrfs(DisasContext *ctx)
2395 {
2396 TCGv tmp = tcg_temp_new();
2397 int bfa;
2398
2399 if (unlikely(!ctx->fpu_enabled)) {
2400 gen_exception(ctx, POWERPC_EXCP_FPU);
2401 return;
2402 }
2403 bfa = 4 * (7 - crfS(ctx->opcode));
2404 tcg_gen_shri_tl(tmp, cpu_fpscr, bfa);
2405 tcg_gen_trunc_tl_i32(cpu_crf[crfD(ctx->opcode)], tmp);
2406 tcg_temp_free(tmp);
2407 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], 0xf);
2408 tcg_gen_andi_tl(cpu_fpscr, cpu_fpscr, ~(0xF << bfa));
2409 }
2410
2411 /* mffs */
2412 static void gen_mffs(DisasContext *ctx)
2413 {
2414 if (unlikely(!ctx->fpu_enabled)) {
2415 gen_exception(ctx, POWERPC_EXCP_FPU);
2416 return;
2417 }
2418 gen_reset_fpstatus();
2419 tcg_gen_extu_tl_i64(cpu_fpr[rD(ctx->opcode)], cpu_fpscr);
2420 gen_compute_fprf(cpu_fpr[rD(ctx->opcode)], 0, Rc(ctx->opcode) != 0);
2421 }
2422
2423 /* mtfsb0 */
2424 static void gen_mtfsb0(DisasContext *ctx)
2425 {
2426 uint8_t crb;
2427
2428 if (unlikely(!ctx->fpu_enabled)) {
2429 gen_exception(ctx, POWERPC_EXCP_FPU);
2430 return;
2431 }
2432 crb = 31 - crbD(ctx->opcode);
2433 gen_reset_fpstatus();
2434 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX)) {
2435 TCGv_i32 t0;
2436 /* NIP cannot be restored if the memory exception comes from an helper */
2437 gen_update_nip(ctx, ctx->nip - 4);
2438 t0 = tcg_const_i32(crb);
2439 gen_helper_fpscr_clrbit(cpu_env, t0);
2440 tcg_temp_free_i32(t0);
2441 }
2442 if (unlikely(Rc(ctx->opcode) != 0)) {
2443 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2444 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2445 }
2446 }
2447
2448 /* mtfsb1 */
2449 static void gen_mtfsb1(DisasContext *ctx)
2450 {
2451 uint8_t crb;
2452
2453 if (unlikely(!ctx->fpu_enabled)) {
2454 gen_exception(ctx, POWERPC_EXCP_FPU);
2455 return;
2456 }
2457 crb = 31 - crbD(ctx->opcode);
2458 gen_reset_fpstatus();
2459 /* XXX: we pretend we can only do IEEE floating-point computations */
2460 if (likely(crb != FPSCR_FEX && crb != FPSCR_VX && crb != FPSCR_NI)) {
2461 TCGv_i32 t0;
2462 /* NIP cannot be restored if the memory exception comes from an helper */
2463 gen_update_nip(ctx, ctx->nip - 4);
2464 t0 = tcg_const_i32(crb);
2465 gen_helper_fpscr_setbit(cpu_env, t0);
2466 tcg_temp_free_i32(t0);
2467 }
2468 if (unlikely(Rc(ctx->opcode) != 0)) {
2469 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2470 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2471 }
2472 /* We can raise a differed exception */
2473 gen_helper_float_check_status(cpu_env);
2474 }
2475
2476 /* mtfsf */
2477 static void gen_mtfsf(DisasContext *ctx)
2478 {
2479 TCGv_i32 t0;
2480 int flm, l, w;
2481
2482 if (unlikely(!ctx->fpu_enabled)) {
2483 gen_exception(ctx, POWERPC_EXCP_FPU);
2484 return;
2485 }
2486 flm = FPFLM(ctx->opcode);
2487 l = FPL(ctx->opcode);
2488 w = FPW(ctx->opcode);
2489 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2490 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2491 return;
2492 }
2493 /* NIP cannot be restored if the memory exception comes from an helper */
2494 gen_update_nip(ctx, ctx->nip - 4);
2495 gen_reset_fpstatus();
2496 if (l) {
2497 t0 = tcg_const_i32((ctx->insns_flags2 & PPC2_ISA205) ? 0xffff : 0xff);
2498 } else {
2499 t0 = tcg_const_i32(flm << (w * 8));
2500 }
2501 gen_helper_store_fpscr(cpu_env, cpu_fpr[rB(ctx->opcode)], t0);
2502 tcg_temp_free_i32(t0);
2503 if (unlikely(Rc(ctx->opcode) != 0)) {
2504 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2505 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2506 }
2507 /* We can raise a differed exception */
2508 gen_helper_float_check_status(cpu_env);
2509 }
2510
2511 /* mtfsfi */
2512 static void gen_mtfsfi(DisasContext *ctx)
2513 {
2514 int bf, sh, w;
2515 TCGv_i64 t0;
2516 TCGv_i32 t1;
2517
2518 if (unlikely(!ctx->fpu_enabled)) {
2519 gen_exception(ctx, POWERPC_EXCP_FPU);
2520 return;
2521 }
2522 w = FPW(ctx->opcode);
2523 bf = FPBF(ctx->opcode);
2524 if (unlikely(w & !(ctx->insns_flags2 & PPC2_ISA205))) {
2525 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2526 return;
2527 }
2528 sh = (8 * w) + 7 - bf;
2529 /* NIP cannot be restored if the memory exception comes from an helper */
2530 gen_update_nip(ctx, ctx->nip - 4);
2531 gen_reset_fpstatus();
2532 t0 = tcg_const_i64(((uint64_t)FPIMM(ctx->opcode)) << (4 * sh));
2533 t1 = tcg_const_i32(1 << sh);
2534 gen_helper_store_fpscr(cpu_env, t0, t1);
2535 tcg_temp_free_i64(t0);
2536 tcg_temp_free_i32(t1);
2537 if (unlikely(Rc(ctx->opcode) != 0)) {
2538 tcg_gen_trunc_tl_i32(cpu_crf[1], cpu_fpscr);
2539 tcg_gen_shri_i32(cpu_crf[1], cpu_crf[1], FPSCR_OX);
2540 }
2541 /* We can raise a differed exception */
2542 gen_helper_float_check_status(cpu_env);
2543 }
2544
2545 /*** Addressing modes ***/
2546 /* Register indirect with immediate index : EA = (rA|0) + SIMM */
2547 static inline void gen_addr_imm_index(DisasContext *ctx, TCGv EA,
2548 target_long maskl)
2549 {
2550 target_long simm = SIMM(ctx->opcode);
2551
2552 simm &= ~maskl;
2553 if (rA(ctx->opcode) == 0) {
2554 if (NARROW_MODE(ctx)) {
2555 simm = (uint32_t)simm;
2556 }
2557 tcg_gen_movi_tl(EA, simm);
2558 } else if (likely(simm != 0)) {
2559 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], simm);
2560 if (NARROW_MODE(ctx)) {
2561 tcg_gen_ext32u_tl(EA, EA);
2562 }
2563 } else {
2564 if (NARROW_MODE(ctx)) {
2565 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2566 } else {
2567 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2568 }
2569 }
2570 }
2571
2572 static inline void gen_addr_reg_index(DisasContext *ctx, TCGv EA)
2573 {
2574 if (rA(ctx->opcode) == 0) {
2575 if (NARROW_MODE(ctx)) {
2576 tcg_gen_ext32u_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2577 } else {
2578 tcg_gen_mov_tl(EA, cpu_gpr[rB(ctx->opcode)]);
2579 }
2580 } else {
2581 tcg_gen_add_tl(EA, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
2582 if (NARROW_MODE(ctx)) {
2583 tcg_gen_ext32u_tl(EA, EA);
2584 }
2585 }
2586 }
2587
2588 static inline void gen_addr_register(DisasContext *ctx, TCGv EA)
2589 {
2590 if (rA(ctx->opcode) == 0) {
2591 tcg_gen_movi_tl(EA, 0);
2592 } else if (NARROW_MODE(ctx)) {
2593 tcg_gen_ext32u_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2594 } else {
2595 tcg_gen_mov_tl(EA, cpu_gpr[rA(ctx->opcode)]);
2596 }
2597 }
2598
2599 static inline void gen_addr_add(DisasContext *ctx, TCGv ret, TCGv arg1,
2600 target_long val)
2601 {
2602 tcg_gen_addi_tl(ret, arg1, val);
2603 if (NARROW_MODE(ctx)) {
2604 tcg_gen_ext32u_tl(ret, ret);
2605 }
2606 }
2607
2608 static inline void gen_check_align(DisasContext *ctx, TCGv EA, int mask)
2609 {
2610 int l1 = gen_new_label();
2611 TCGv t0 = tcg_temp_new();
2612 TCGv_i32 t1, t2;
2613 /* NIP cannot be restored if the memory exception comes from an helper */
2614 gen_update_nip(ctx, ctx->nip - 4);
2615 tcg_gen_andi_tl(t0, EA, mask);
2616 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
2617 t1 = tcg_const_i32(POWERPC_EXCP_ALIGN);
2618 t2 = tcg_const_i32(0);
2619 gen_helper_raise_exception_err(cpu_env, t1, t2);
2620 tcg_temp_free_i32(t1);
2621 tcg_temp_free_i32(t2);
2622 gen_set_label(l1);
2623 tcg_temp_free(t0);
2624 }
2625
2626 /*** Integer load ***/
2627 static inline void gen_qemu_ld8u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2628 {
2629 tcg_gen_qemu_ld8u(arg1, arg2, ctx->mem_idx);
2630 }
2631
2632 static inline void gen_qemu_ld8s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2633 {
2634 tcg_gen_qemu_ld8s(arg1, arg2, ctx->mem_idx);
2635 }
2636
2637 static inline void gen_qemu_ld16u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2638 {
2639 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2640 if (unlikely(ctx->le_mode)) {
2641 tcg_gen_bswap16_tl(arg1, arg1);
2642 }
2643 }
2644
2645 static inline void gen_qemu_ld16s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2646 {
2647 if (unlikely(ctx->le_mode)) {
2648 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
2649 tcg_gen_bswap16_tl(arg1, arg1);
2650 tcg_gen_ext16s_tl(arg1, arg1);
2651 } else {
2652 tcg_gen_qemu_ld16s(arg1, arg2, ctx->mem_idx);
2653 }
2654 }
2655
2656 static inline void gen_qemu_ld32u(DisasContext *ctx, TCGv arg1, TCGv arg2)
2657 {
2658 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2659 if (unlikely(ctx->le_mode)) {
2660 tcg_gen_bswap32_tl(arg1, arg1);
2661 }
2662 }
2663
2664 static void gen_qemu_ld32u_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2665 {
2666 TCGv tmp = tcg_temp_new();
2667 gen_qemu_ld32u(ctx, tmp, addr);
2668 tcg_gen_extu_tl_i64(val, tmp);
2669 tcg_temp_free(tmp);
2670 }
2671
2672 static inline void gen_qemu_ld32s(DisasContext *ctx, TCGv arg1, TCGv arg2)
2673 {
2674 if (unlikely(ctx->le_mode)) {
2675 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
2676 tcg_gen_bswap32_tl(arg1, arg1);
2677 tcg_gen_ext32s_tl(arg1, arg1);
2678 } else
2679 tcg_gen_qemu_ld32s(arg1, arg2, ctx->mem_idx);
2680 }
2681
2682 static void gen_qemu_ld32s_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2683 {
2684 TCGv tmp = tcg_temp_new();
2685 gen_qemu_ld32s(ctx, tmp, addr);
2686 tcg_gen_ext_tl_i64(val, tmp);
2687 tcg_temp_free(tmp);
2688 }
2689
2690 static inline void gen_qemu_ld64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2691 {
2692 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
2693 if (unlikely(ctx->le_mode)) {
2694 tcg_gen_bswap64_i64(arg1, arg1);
2695 }
2696 }
2697
2698 static inline void gen_qemu_st8(DisasContext *ctx, TCGv arg1, TCGv arg2)
2699 {
2700 tcg_gen_qemu_st8(arg1, arg2, ctx->mem_idx);
2701 }
2702
2703 static inline void gen_qemu_st16(DisasContext *ctx, TCGv arg1, TCGv arg2)
2704 {
2705 if (unlikely(ctx->le_mode)) {
2706 TCGv t0 = tcg_temp_new();
2707 tcg_gen_ext16u_tl(t0, arg1);
2708 tcg_gen_bswap16_tl(t0, t0);
2709 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
2710 tcg_temp_free(t0);
2711 } else {
2712 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
2713 }
2714 }
2715
2716 static inline void gen_qemu_st32(DisasContext *ctx, TCGv arg1, TCGv arg2)
2717 {
2718 if (unlikely(ctx->le_mode)) {
2719 TCGv t0 = tcg_temp_new();
2720 tcg_gen_ext32u_tl(t0, arg1);
2721 tcg_gen_bswap32_tl(t0, t0);
2722 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
2723 tcg_temp_free(t0);
2724 } else {
2725 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
2726 }
2727 }
2728
2729 static void gen_qemu_st32_i64(DisasContext *ctx, TCGv_i64 val, TCGv addr)
2730 {
2731 TCGv tmp = tcg_temp_new();
2732 tcg_gen_trunc_i64_tl(tmp, val);
2733 gen_qemu_st32(ctx, tmp, addr);
2734 tcg_temp_free(tmp);
2735 }
2736
2737 static inline void gen_qemu_st64(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
2738 {
2739 if (unlikely(ctx->le_mode)) {
2740 TCGv_i64 t0 = tcg_temp_new_i64();
2741 tcg_gen_bswap64_i64(t0, arg1);
2742 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
2743 tcg_temp_free_i64(t0);
2744 } else
2745 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
2746 }
2747
2748 #define GEN_LD(name, ldop, opc, type) \
2749 static void glue(gen_, name)(DisasContext *ctx) \
2750 { \
2751 TCGv EA; \
2752 gen_set_access_type(ctx, ACCESS_INT); \
2753 EA = tcg_temp_new(); \
2754 gen_addr_imm_index(ctx, EA, 0); \
2755 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2756 tcg_temp_free(EA); \
2757 }
2758
2759 #define GEN_LDU(name, ldop, opc, type) \
2760 static void glue(gen_, name##u)(DisasContext *ctx) \
2761 { \
2762 TCGv EA; \
2763 if (unlikely(rA(ctx->opcode) == 0 || \
2764 rA(ctx->opcode) == rD(ctx->opcode))) { \
2765 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2766 return; \
2767 } \
2768 gen_set_access_type(ctx, ACCESS_INT); \
2769 EA = tcg_temp_new(); \
2770 if (type == PPC_64B) \
2771 gen_addr_imm_index(ctx, EA, 0x03); \
2772 else \
2773 gen_addr_imm_index(ctx, EA, 0); \
2774 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2775 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2776 tcg_temp_free(EA); \
2777 }
2778
2779 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
2780 static void glue(gen_, name##ux)(DisasContext *ctx) \
2781 { \
2782 TCGv EA; \
2783 if (unlikely(rA(ctx->opcode) == 0 || \
2784 rA(ctx->opcode) == rD(ctx->opcode))) { \
2785 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2786 return; \
2787 } \
2788 gen_set_access_type(ctx, ACCESS_INT); \
2789 EA = tcg_temp_new(); \
2790 gen_addr_reg_index(ctx, EA); \
2791 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2792 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2793 tcg_temp_free(EA); \
2794 }
2795
2796 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
2797 static void glue(gen_, name##x)(DisasContext *ctx) \
2798 { \
2799 TCGv EA; \
2800 gen_set_access_type(ctx, ACCESS_INT); \
2801 EA = tcg_temp_new(); \
2802 gen_addr_reg_index(ctx, EA); \
2803 gen_qemu_##ldop(ctx, cpu_gpr[rD(ctx->opcode)], EA); \
2804 tcg_temp_free(EA); \
2805 }
2806 #define GEN_LDX(name, ldop, opc2, opc3, type) \
2807 GEN_LDX_E(name, ldop, opc2, opc3, type, PPC_NONE)
2808
2809 #define GEN_LDS(name, ldop, op, type) \
2810 GEN_LD(name, ldop, op | 0x20, type); \
2811 GEN_LDU(name, ldop, op | 0x21, type); \
2812 GEN_LDUX(name, ldop, 0x17, op | 0x01, type); \
2813 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
2814
2815 /* lbz lbzu lbzux lbzx */
2816 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER);
2817 /* lha lhau lhaux lhax */
2818 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER);
2819 /* lhz lhzu lhzux lhzx */
2820 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER);
2821 /* lwz lwzu lwzux lwzx */
2822 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER);
2823 #if defined(TARGET_PPC64)
2824 /* lwaux */
2825 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B);
2826 /* lwax */
2827 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B);
2828 /* ldux */
2829 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B);
2830 /* ldx */
2831 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B);
2832
2833 static void gen_ld(DisasContext *ctx)
2834 {
2835 TCGv EA;
2836 if (Rc(ctx->opcode)) {
2837 if (unlikely(rA(ctx->opcode) == 0 ||
2838 rA(ctx->opcode) == rD(ctx->opcode))) {
2839 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2840 return;
2841 }
2842 }
2843 gen_set_access_type(ctx, ACCESS_INT);
2844 EA = tcg_temp_new();
2845 gen_addr_imm_index(ctx, EA, 0x03);
2846 if (ctx->opcode & 0x02) {
2847 /* lwa (lwau is undefined) */
2848 gen_qemu_ld32s(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2849 } else {
2850 /* ld - ldu */
2851 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], EA);
2852 }
2853 if (Rc(ctx->opcode))
2854 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
2855 tcg_temp_free(EA);
2856 }
2857
2858 /* lq */
2859 static void gen_lq(DisasContext *ctx)
2860 {
2861 #if defined(CONFIG_USER_ONLY)
2862 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2863 #else
2864 int ra, rd;
2865 TCGv EA;
2866
2867 /* Restore CPU state */
2868 if (unlikely(ctx->mem_idx == 0)) {
2869 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2870 return;
2871 }
2872 ra = rA(ctx->opcode);
2873 rd = rD(ctx->opcode);
2874 if (unlikely((rd & 1) || rd == ra)) {
2875 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2876 return;
2877 }
2878 if (unlikely(ctx->le_mode)) {
2879 /* Little-endian mode is not handled */
2880 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2881 return;
2882 }
2883 gen_set_access_type(ctx, ACCESS_INT);
2884 EA = tcg_temp_new();
2885 gen_addr_imm_index(ctx, EA, 0x0F);
2886 gen_qemu_ld64(ctx, cpu_gpr[rd], EA);
2887 gen_addr_add(ctx, EA, EA, 8);
2888 gen_qemu_ld64(ctx, cpu_gpr[rd+1], EA);
2889 tcg_temp_free(EA);
2890 #endif
2891 }
2892 #endif
2893
2894 /*** Integer store ***/
2895 #define GEN_ST(name, stop, opc, type) \
2896 static void glue(gen_, name)(DisasContext *ctx) \
2897 { \
2898 TCGv EA; \
2899 gen_set_access_type(ctx, ACCESS_INT); \
2900 EA = tcg_temp_new(); \
2901 gen_addr_imm_index(ctx, EA, 0); \
2902 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2903 tcg_temp_free(EA); \
2904 }
2905
2906 #define GEN_STU(name, stop, opc, type) \
2907 static void glue(gen_, stop##u)(DisasContext *ctx) \
2908 { \
2909 TCGv EA; \
2910 if (unlikely(rA(ctx->opcode) == 0)) { \
2911 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2912 return; \
2913 } \
2914 gen_set_access_type(ctx, ACCESS_INT); \
2915 EA = tcg_temp_new(); \
2916 if (type == PPC_64B) \
2917 gen_addr_imm_index(ctx, EA, 0x03); \
2918 else \
2919 gen_addr_imm_index(ctx, EA, 0); \
2920 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2921 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2922 tcg_temp_free(EA); \
2923 }
2924
2925 #define GEN_STUX(name, stop, opc2, opc3, type) \
2926 static void glue(gen_, name##ux)(DisasContext *ctx) \
2927 { \
2928 TCGv EA; \
2929 if (unlikely(rA(ctx->opcode) == 0)) { \
2930 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
2931 return; \
2932 } \
2933 gen_set_access_type(ctx, ACCESS_INT); \
2934 EA = tcg_temp_new(); \
2935 gen_addr_reg_index(ctx, EA); \
2936 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2937 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
2938 tcg_temp_free(EA); \
2939 }
2940
2941 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
2942 static void glue(gen_, name##x)(DisasContext *ctx) \
2943 { \
2944 TCGv EA; \
2945 gen_set_access_type(ctx, ACCESS_INT); \
2946 EA = tcg_temp_new(); \
2947 gen_addr_reg_index(ctx, EA); \
2948 gen_qemu_##stop(ctx, cpu_gpr[rS(ctx->opcode)], EA); \
2949 tcg_temp_free(EA); \
2950 }
2951 #define GEN_STX(name, stop, opc2, opc3, type) \
2952 GEN_STX_E(name, stop, opc2, opc3, type, PPC_NONE)
2953
2954 #define GEN_STS(name, stop, op, type) \
2955 GEN_ST(name, stop, op | 0x20, type); \
2956 GEN_STU(name, stop, op | 0x21, type); \
2957 GEN_STUX(name, stop, 0x17, op | 0x01, type); \
2958 GEN_STX(name, stop, 0x17, op | 0x00, type)
2959
2960 /* stb stbu stbux stbx */
2961 GEN_STS(stb, st8, 0x06, PPC_INTEGER);
2962 /* sth sthu sthux sthx */
2963 GEN_STS(sth, st16, 0x0C, PPC_INTEGER);
2964 /* stw stwu stwux stwx */
2965 GEN_STS(stw, st32, 0x04, PPC_INTEGER);
2966 #if defined(TARGET_PPC64)
2967 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B);
2968 GEN_STX(std, st64, 0x15, 0x04, PPC_64B);
2969
2970 static void gen_std(DisasContext *ctx)
2971 {
2972 int rs;
2973 TCGv EA;
2974
2975 rs = rS(ctx->opcode);
2976 if ((ctx->opcode & 0x3) == 0x2) {
2977 #if defined(CONFIG_USER_ONLY)
2978 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2979 #else
2980 /* stq */
2981 if (unlikely(ctx->mem_idx == 0)) {
2982 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
2983 return;
2984 }
2985 if (unlikely(rs & 1)) {
2986 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
2987 return;
2988 }
2989 if (unlikely(ctx->le_mode)) {
2990 /* Little-endian mode is not handled */
2991 gen_exception_err(ctx, POWERPC_EXCP_ALIGN, POWERPC_EXCP_ALIGN_LE);
2992 return;
2993 }
2994 gen_set_access_type(ctx, ACCESS_INT);
2995 EA = tcg_temp_new();
2996 gen_addr_imm_index(ctx, EA, 0x03);
2997 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
2998 gen_addr_add(ctx, EA, EA, 8);
2999 gen_qemu_st64(ctx, cpu_gpr[rs+1], EA);
3000 tcg_temp_free(EA);
3001 #endif
3002 } else {
3003 /* std / stdu */
3004 if (Rc(ctx->opcode)) {
3005 if (unlikely(rA(ctx->opcode) == 0)) {
3006 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3007 return;
3008 }
3009 }
3010 gen_set_access_type(ctx, ACCESS_INT);
3011 EA = tcg_temp_new();
3012 gen_addr_imm_index(ctx, EA, 0x03);
3013 gen_qemu_st64(ctx, cpu_gpr[rs], EA);
3014 if (Rc(ctx->opcode))
3015 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA);
3016 tcg_temp_free(EA);
3017 }
3018 }
3019 #endif
3020 /*** Integer load and store with byte reverse ***/
3021 /* lhbrx */
3022 static inline void gen_qemu_ld16ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3023 {
3024 tcg_gen_qemu_ld16u(arg1, arg2, ctx->mem_idx);
3025 if (likely(!ctx->le_mode)) {
3026 tcg_gen_bswap16_tl(arg1, arg1);
3027 }
3028 }
3029 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER);
3030
3031 /* lwbrx */
3032 static inline void gen_qemu_ld32ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3033 {
3034 tcg_gen_qemu_ld32u(arg1, arg2, ctx->mem_idx);
3035 if (likely(!ctx->le_mode)) {
3036 tcg_gen_bswap32_tl(arg1, arg1);
3037 }
3038 }
3039 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER);
3040
3041 #if defined(TARGET_PPC64)
3042 /* ldbrx */
3043 static inline void gen_qemu_ld64ur(DisasContext *ctx, TCGv arg1, TCGv arg2)
3044 {
3045 tcg_gen_qemu_ld64(arg1, arg2, ctx->mem_idx);
3046 if (likely(!ctx->le_mode)) {
3047 tcg_gen_bswap64_tl(arg1, arg1);
3048 }
3049 }
3050 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX);
3051 #endif /* TARGET_PPC64 */
3052
3053 /* sthbrx */
3054 static inline void gen_qemu_st16r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3055 {
3056 if (likely(!ctx->le_mode)) {
3057 TCGv t0 = tcg_temp_new();
3058 tcg_gen_ext16u_tl(t0, arg1);
3059 tcg_gen_bswap16_tl(t0, t0);
3060 tcg_gen_qemu_st16(t0, arg2, ctx->mem_idx);
3061 tcg_temp_free(t0);
3062 } else {
3063 tcg_gen_qemu_st16(arg1, arg2, ctx->mem_idx);
3064 }
3065 }
3066 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER);
3067
3068 /* stwbrx */
3069 static inline void gen_qemu_st32r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3070 {
3071 if (likely(!ctx->le_mode)) {
3072 TCGv t0 = tcg_temp_new();
3073 tcg_gen_ext32u_tl(t0, arg1);
3074 tcg_gen_bswap32_tl(t0, t0);
3075 tcg_gen_qemu_st32(t0, arg2, ctx->mem_idx);
3076 tcg_temp_free(t0);
3077 } else {
3078 tcg_gen_qemu_st32(arg1, arg2, ctx->mem_idx);
3079 }
3080 }
3081 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER);
3082
3083 #if defined(TARGET_PPC64)
3084 /* stdbrx */
3085 static inline void gen_qemu_st64r(DisasContext *ctx, TCGv arg1, TCGv arg2)
3086 {
3087 if (likely(!ctx->le_mode)) {
3088 TCGv t0 = tcg_temp_new();
3089 tcg_gen_bswap64_tl(t0, arg1);
3090 tcg_gen_qemu_st64(t0, arg2, ctx->mem_idx);
3091 tcg_temp_free(t0);
3092 } else {
3093 tcg_gen_qemu_st64(arg1, arg2, ctx->mem_idx);
3094 }
3095 }
3096 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX);
3097 #endif /* TARGET_PPC64 */
3098
3099 /*** Integer load and store multiple ***/
3100
3101 /* lmw */
3102 static void gen_lmw(DisasContext *ctx)
3103 {
3104 TCGv t0;
3105 TCGv_i32 t1;
3106 gen_set_access_type(ctx, ACCESS_INT);
3107 /* NIP cannot be restored if the memory exception comes from an helper */
3108 gen_update_nip(ctx, ctx->nip - 4);
3109 t0 = tcg_temp_new();
3110 t1 = tcg_const_i32(rD(ctx->opcode));
3111 gen_addr_imm_index(ctx, t0, 0);
3112 gen_helper_lmw(cpu_env, t0, t1);
3113 tcg_temp_free(t0);
3114 tcg_temp_free_i32(t1);
3115 }
3116
3117 /* stmw */
3118 static void gen_stmw(DisasContext *ctx)
3119 {
3120 TCGv t0;
3121 TCGv_i32 t1;
3122 gen_set_access_type(ctx, ACCESS_INT);
3123 /* NIP cannot be restored if the memory exception comes from an helper */
3124 gen_update_nip(ctx, ctx->nip - 4);
3125 t0 = tcg_temp_new();
3126 t1 = tcg_const_i32(rS(ctx->opcode));
3127 gen_addr_imm_index(ctx, t0, 0);
3128 gen_helper_stmw(cpu_env, t0, t1);
3129 tcg_temp_free(t0);
3130 tcg_temp_free_i32(t1);
3131 }
3132
3133 /*** Integer load and store strings ***/
3134
3135 /* lswi */
3136 /* PowerPC32 specification says we must generate an exception if
3137 * rA is in the range of registers to be loaded.
3138 * In an other hand, IBM says this is valid, but rA won't be loaded.
3139 * For now, I'll follow the spec...
3140 */
3141 static void gen_lswi(DisasContext *ctx)
3142 {
3143 TCGv t0;
3144 TCGv_i32 t1, t2;
3145 int nb = NB(ctx->opcode);
3146 int start = rD(ctx->opcode);
3147 int ra = rA(ctx->opcode);
3148 int nr;
3149
3150 if (nb == 0)
3151 nb = 32;
3152 nr = nb / 4;
3153 if (unlikely(((start + nr) > 32 &&
3154 start <= ra && (start + nr - 32) > ra) ||
3155 ((start + nr) <= 32 && start <= ra && (start + nr) > ra))) {
3156 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
3157 return;
3158 }
3159 gen_set_access_type(ctx, ACCESS_INT);
3160 /* NIP cannot be restored if the memory exception comes from an helper */
3161 gen_update_nip(ctx, ctx->nip - 4);
3162 t0 = tcg_temp_new();
3163 gen_addr_register(ctx, t0);
3164 t1 = tcg_const_i32(nb);
3165 t2 = tcg_const_i32(start);
3166 gen_helper_lsw(cpu_env, t0, t1, t2);
3167 tcg_temp_free(t0);
3168 tcg_temp_free_i32(t1);
3169 tcg_temp_free_i32(t2);
3170 }
3171
3172 /* lswx */
3173 static void gen_lswx(DisasContext *ctx)
3174 {
3175 TCGv t0;
3176 TCGv_i32 t1, t2, t3;
3177 gen_set_access_type(ctx, ACCESS_INT);
3178 /* NIP cannot be restored if the memory exception comes from an helper */
3179 gen_update_nip(ctx, ctx->nip - 4);
3180 t0 = tcg_temp_new();
3181 gen_addr_reg_index(ctx, t0);
3182 t1 = tcg_const_i32(rD(ctx->opcode));
3183 t2 = tcg_const_i32(rA(ctx->opcode));
3184 t3 = tcg_const_i32(rB(ctx->opcode));
3185 gen_helper_lswx(cpu_env, t0, t1, t2, t3);
3186 tcg_temp_free(t0);
3187 tcg_temp_free_i32(t1);
3188 tcg_temp_free_i32(t2);
3189 tcg_temp_free_i32(t3);
3190 }
3191
3192 /* stswi */
3193 static void gen_stswi(DisasContext *ctx)
3194 {
3195 TCGv t0;
3196 TCGv_i32 t1, t2;
3197 int nb = NB(ctx->opcode);
3198 gen_set_access_type(ctx, ACCESS_INT);
3199 /* NIP cannot be restored if the memory exception comes from an helper */
3200 gen_update_nip(ctx, ctx->nip - 4);
3201 t0 = tcg_temp_new();
3202 gen_addr_register(ctx, t0);
3203 if (nb == 0)
3204 nb = 32;
3205 t1 = tcg_const_i32(nb);
3206 t2 = tcg_const_i32(rS(ctx->opcode));
3207 gen_helper_stsw(cpu_env, t0, t1, t2);
3208 tcg_temp_free(t0);
3209 tcg_temp_free_i32(t1);
3210 tcg_temp_free_i32(t2);
3211 }
3212
3213 /* stswx */
3214 static void gen_stswx(DisasContext *ctx)
3215 {
3216 TCGv t0;
3217 TCGv_i32 t1, t2;
3218 gen_set_access_type(ctx, ACCESS_INT);
3219 /* NIP cannot be restored if the memory exception comes from an helper */
3220 gen_update_nip(ctx, ctx->nip - 4);
3221 t0 = tcg_temp_new();
3222 gen_addr_reg_index(ctx, t0);
3223 t1 = tcg_temp_new_i32();
3224 tcg_gen_trunc_tl_i32(t1, cpu_xer);
3225 tcg_gen_andi_i32(t1, t1, 0x7F);
3226 t2 = tcg_const_i32(rS(ctx->opcode));
3227 gen_helper_stsw(cpu_env, t0, t1, t2);
3228 tcg_temp_free(t0);
3229 tcg_temp_free_i32(t1);
3230 tcg_temp_free_i32(t2);
3231 }
3232
3233 /*** Memory synchronisation ***/
3234 /* eieio */
3235 static void gen_eieio(DisasContext *ctx)
3236 {
3237 }
3238
3239 /* isync */
3240 static void gen_isync(DisasContext *ctx)
3241 {
3242 gen_stop_exception(ctx);
3243 }
3244
3245 #define LARX(name, len, loadop) \
3246 static void gen_##name(DisasContext *ctx) \
3247 { \
3248 TCGv t0; \
3249 TCGv gpr = cpu_gpr[rD(ctx->opcode)]; \
3250 gen_set_access_type(ctx, ACCESS_RES); \
3251 t0 = tcg_temp_local_new(); \
3252 gen_addr_reg_index(ctx, t0); \
3253 if ((len) > 1) { \
3254 gen_check_align(ctx, t0, (len)-1); \
3255 } \
3256 gen_qemu_##loadop(ctx, gpr, t0); \
3257 tcg_gen_mov_tl(cpu_reserve, t0); \
3258 tcg_gen_st_tl(gpr, cpu_env, offsetof(CPUPPCState, reserve_val)); \
3259 tcg_temp_free(t0); \
3260 }
3261
3262 /* lwarx */
3263 LARX(lbarx, 1, ld8u);
3264 LARX(lharx, 2, ld16u);
3265 LARX(lwarx, 4, ld32u);
3266
3267
3268 #if defined(CONFIG_USER_ONLY)
3269 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3270 int reg, int size)
3271 {
3272 TCGv t0 = tcg_temp_new();
3273 uint32_t save_exception = ctx->exception;
3274
3275 tcg_gen_st_tl(EA, cpu_env, offsetof(CPUPPCState, reserve_ea));
3276 tcg_gen_movi_tl(t0, (size << 5) | reg);
3277 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, reserve_info));
3278 tcg_temp_free(t0);
3279 gen_update_nip(ctx, ctx->nip-4);
3280 ctx->exception = POWERPC_EXCP_BRANCH;
3281 gen_exception(ctx, POWERPC_EXCP_STCX);
3282 ctx->exception = save_exception;
3283 }
3284 #else
3285 static void gen_conditional_store(DisasContext *ctx, TCGv EA,
3286 int reg, int size)
3287 {
3288 int l1;
3289
3290 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
3291 l1 = gen_new_label();
3292 tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, l1);
3293 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
3294 #if defined(TARGET_PPC64)
3295 if (size == 8) {
3296 gen_qemu_st64(ctx, cpu_gpr[reg], EA);
3297 } else
3298 #endif
3299 if (size == 4) {
3300 gen_qemu_st32(ctx, cpu_gpr[reg], EA);
3301 } else if (size == 2) {
3302 gen_qemu_st16(ctx, cpu_gpr[reg], EA);
3303 } else {
3304 gen_qemu_st8(ctx, cpu_gpr[reg], EA);
3305 }
3306 gen_set_label(l1);
3307 tcg_gen_movi_tl(cpu_reserve, -1);
3308 }
3309 #endif
3310
3311 #define STCX(name, len) \
3312 static void gen_##name(DisasContext *ctx) \
3313 { \
3314 TCGv t0; \
3315 gen_set_access_type(ctx, ACCESS_RES); \
3316 t0 = tcg_temp_local_new(); \
3317 gen_addr_reg_index(ctx, t0); \
3318 if (len > 1) { \
3319 gen_check_align(ctx, t0, (len)-1); \
3320 } \
3321 gen_conditional_store(ctx, t0, rS(ctx->opcode), len); \
3322 tcg_temp_free(t0); \
3323 }
3324
3325 STCX(stbcx_, 1);
3326 STCX(sthcx_, 2);
3327 STCX(stwcx_, 4);
3328
3329 #if defined(TARGET_PPC64)
3330 /* ldarx */
3331 LARX(ldarx, 8, ld64);
3332
3333 /* stdcx. */
3334 STCX(stdcx_, 8);
3335 #endif /* defined(TARGET_PPC64) */
3336
3337 /* sync */
3338 static void gen_sync(DisasContext *ctx)
3339 {
3340 }
3341
3342 /* wait */
3343 static void gen_wait(DisasContext *ctx)
3344 {
3345 TCGv_i32 t0 = tcg_temp_new_i32();
3346 tcg_gen_st_i32(t0, cpu_env,
3347 -offsetof(PowerPCCPU, env) + offsetof(CPUState, halted));
3348 tcg_temp_free_i32(t0);
3349 /* Stop translation, as the CPU is supposed to sleep from now */
3350 gen_exception_err(ctx, EXCP_HLT, 1);
3351 }
3352
3353 /*** Floating-point load ***/
3354 #define GEN_LDF(name, ldop, opc, type) \
3355 static void glue(gen_, name)(DisasContext *ctx) \
3356 { \
3357 TCGv EA; \
3358 if (unlikely(!ctx->fpu_enabled)) { \
3359 gen_exception(ctx, POWERPC_EXCP_FPU); \
3360 return; \
3361 } \
3362 gen_set_access_type(ctx, ACCESS_FLOAT); \
3363 EA = tcg_temp_new(); \
3364 gen_addr_imm_index(ctx, EA, 0); \
3365 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3366 tcg_temp_free(EA); \
3367 }
3368
3369 #define GEN_LDUF(name, ldop, opc, type) \
3370 static void glue(gen_, name##u)(DisasContext *ctx) \
3371 { \
3372 TCGv EA; \
3373 if (unlikely(!ctx->fpu_enabled)) { \
3374 gen_exception(ctx, POWERPC_EXCP_FPU); \
3375 return; \
3376 } \
3377 if (unlikely(rA(ctx->opcode) == 0)) { \
3378 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3379 return; \
3380 } \
3381 gen_set_access_type(ctx, ACCESS_FLOAT); \
3382 EA = tcg_temp_new(); \
3383 gen_addr_imm_index(ctx, EA, 0); \
3384 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3385 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3386 tcg_temp_free(EA); \
3387 }
3388
3389 #define GEN_LDUXF(name, ldop, opc, type) \
3390 static void glue(gen_, name##ux)(DisasContext *ctx) \
3391 { \
3392 TCGv EA; \
3393 if (unlikely(!ctx->fpu_enabled)) { \
3394 gen_exception(ctx, POWERPC_EXCP_FPU); \
3395 return; \
3396 } \
3397 if (unlikely(rA(ctx->opcode) == 0)) { \
3398 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3399 return; \
3400 } \
3401 gen_set_access_type(ctx, ACCESS_FLOAT); \
3402 EA = tcg_temp_new(); \
3403 gen_addr_reg_index(ctx, EA); \
3404 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3405 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3406 tcg_temp_free(EA); \
3407 }
3408
3409 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
3410 static void glue(gen_, name##x)(DisasContext *ctx) \
3411 { \
3412 TCGv EA; \
3413 if (unlikely(!ctx->fpu_enabled)) { \
3414 gen_exception(ctx, POWERPC_EXCP_FPU); \
3415 return; \
3416 } \
3417 gen_set_access_type(ctx, ACCESS_FLOAT); \
3418 EA = tcg_temp_new(); \
3419 gen_addr_reg_index(ctx, EA); \
3420 gen_qemu_##ldop(ctx, cpu_fpr[rD(ctx->opcode)], EA); \
3421 tcg_temp_free(EA); \
3422 }
3423
3424 #define GEN_LDFS(name, ldop, op, type) \
3425 GEN_LDF(name, ldop, op | 0x20, type); \
3426 GEN_LDUF(name, ldop, op | 0x21, type); \
3427 GEN_LDUXF(name, ldop, op | 0x01, type); \
3428 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
3429
3430 static inline void gen_qemu_ld32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3431 {
3432 TCGv t0 = tcg_temp_new();
3433 TCGv_i32 t1 = tcg_temp_new_i32();
3434 gen_qemu_ld32u(ctx, t0, arg2);
3435 tcg_gen_trunc_tl_i32(t1, t0);
3436 tcg_temp_free(t0);
3437 gen_helper_float32_to_float64(arg1, cpu_env, t1);
3438 tcg_temp_free_i32(t1);
3439 }
3440
3441 /* lfd lfdu lfdux lfdx */
3442 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT);
3443 /* lfs lfsu lfsux lfsx */
3444 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT);
3445
3446 /* lfdp */
3447 static void gen_lfdp(DisasContext *ctx)
3448 {
3449 TCGv EA;
3450 if (unlikely(!ctx->fpu_enabled)) {
3451 gen_exception(ctx, POWERPC_EXCP_FPU);
3452 return;
3453 }
3454 gen_set_access_type(ctx, ACCESS_FLOAT);
3455 EA = tcg_temp_new();
3456 gen_addr_imm_index(ctx, EA, 0); \
3457 if (unlikely(ctx->le_mode)) {
3458 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3459 tcg_gen_addi_tl(EA, EA, 8);
3460 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3461 } else {
3462 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3463 tcg_gen_addi_tl(EA, EA, 8);
3464 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3465 }
3466 tcg_temp_free(EA);
3467 }
3468
3469 /* lfdpx */
3470 static void gen_lfdpx(DisasContext *ctx)
3471 {
3472 TCGv EA;
3473 if (unlikely(!ctx->fpu_enabled)) {
3474 gen_exception(ctx, POWERPC_EXCP_FPU);
3475 return;
3476 }
3477 gen_set_access_type(ctx, ACCESS_FLOAT);
3478 EA = tcg_temp_new();
3479 gen_addr_reg_index(ctx, EA);
3480 if (unlikely(ctx->le_mode)) {
3481 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3482 tcg_gen_addi_tl(EA, EA, 8);
3483 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3484 } else {
3485 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3486 tcg_gen_addi_tl(EA, EA, 8);
3487 gen_qemu_ld64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3488 }
3489 tcg_temp_free(EA);
3490 }
3491
3492 /* lfiwax */
3493 static void gen_lfiwax(DisasContext *ctx)
3494 {
3495 TCGv EA;
3496 TCGv t0;
3497 if (unlikely(!ctx->fpu_enabled)) {
3498 gen_exception(ctx, POWERPC_EXCP_FPU);
3499 return;
3500 }
3501 gen_set_access_type(ctx, ACCESS_FLOAT);
3502 EA = tcg_temp_new();
3503 t0 = tcg_temp_new();
3504 gen_addr_reg_index(ctx, EA);
3505 gen_qemu_ld32s(ctx, t0, EA);
3506 tcg_gen_ext_tl_i64(cpu_fpr[rD(ctx->opcode)], t0);
3507 tcg_temp_free(EA);
3508 tcg_temp_free(t0);
3509 }
3510
3511 /* lfiwzx */
3512 static void gen_lfiwzx(DisasContext *ctx)
3513 {
3514 TCGv EA;
3515 if (unlikely(!ctx->fpu_enabled)) {
3516 gen_exception(ctx, POWERPC_EXCP_FPU);
3517 return;
3518 }
3519 gen_set_access_type(ctx, ACCESS_FLOAT);
3520 EA = tcg_temp_new();
3521 gen_addr_reg_index(ctx, EA);
3522 gen_qemu_ld32u_i64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3523 tcg_temp_free(EA);
3524 }
3525 /*** Floating-point store ***/
3526 #define GEN_STF(name, stop, opc, type) \
3527 static void glue(gen_, name)(DisasContext *ctx) \
3528 { \
3529 TCGv EA; \
3530 if (unlikely(!ctx->fpu_enabled)) { \
3531 gen_exception(ctx, POWERPC_EXCP_FPU); \
3532 return; \
3533 } \
3534 gen_set_access_type(ctx, ACCESS_FLOAT); \
3535 EA = tcg_temp_new(); \
3536 gen_addr_imm_index(ctx, EA, 0); \
3537 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3538 tcg_temp_free(EA); \
3539 }
3540
3541 #define GEN_STUF(name, stop, opc, type) \
3542 static void glue(gen_, name##u)(DisasContext *ctx) \
3543 { \
3544 TCGv EA; \
3545 if (unlikely(!ctx->fpu_enabled)) { \
3546 gen_exception(ctx, POWERPC_EXCP_FPU); \
3547 return; \
3548 } \
3549 if (unlikely(rA(ctx->opcode) == 0)) { \
3550 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3551 return; \
3552 } \
3553 gen_set_access_type(ctx, ACCESS_FLOAT); \
3554 EA = tcg_temp_new(); \
3555 gen_addr_imm_index(ctx, EA, 0); \
3556 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3557 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3558 tcg_temp_free(EA); \
3559 }
3560
3561 #define GEN_STUXF(name, stop, opc, type) \
3562 static void glue(gen_, name##ux)(DisasContext *ctx) \
3563 { \
3564 TCGv EA; \
3565 if (unlikely(!ctx->fpu_enabled)) { \
3566 gen_exception(ctx, POWERPC_EXCP_FPU); \
3567 return; \
3568 } \
3569 if (unlikely(rA(ctx->opcode) == 0)) { \
3570 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL); \
3571 return; \
3572 } \
3573 gen_set_access_type(ctx, ACCESS_FLOAT); \
3574 EA = tcg_temp_new(); \
3575 gen_addr_reg_index(ctx, EA); \
3576 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3577 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], EA); \
3578 tcg_temp_free(EA); \
3579 }
3580
3581 #define GEN_STXF(name, stop, opc2, opc3, type) \
3582 static void glue(gen_, name##x)(DisasContext *ctx) \
3583 { \
3584 TCGv EA; \
3585 if (unlikely(!ctx->fpu_enabled)) { \
3586 gen_exception(ctx, POWERPC_EXCP_FPU); \
3587 return; \
3588 } \
3589 gen_set_access_type(ctx, ACCESS_FLOAT); \
3590 EA = tcg_temp_new(); \
3591 gen_addr_reg_index(ctx, EA); \
3592 gen_qemu_##stop(ctx, cpu_fpr[rS(ctx->opcode)], EA); \
3593 tcg_temp_free(EA); \
3594 }
3595
3596 #define GEN_STFS(name, stop, op, type) \
3597 GEN_STF(name, stop, op | 0x20, type); \
3598 GEN_STUF(name, stop, op | 0x21, type); \
3599 GEN_STUXF(name, stop, op | 0x01, type); \
3600 GEN_STXF(name, stop, 0x17, op | 0x00, type)
3601
3602 static inline void gen_qemu_st32fs(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3603 {
3604 TCGv_i32 t0 = tcg_temp_new_i32();
3605 TCGv t1 = tcg_temp_new();
3606 gen_helper_float64_to_float32(t0, cpu_env, arg1);
3607 tcg_gen_extu_i32_tl(t1, t0);
3608 tcg_temp_free_i32(t0);
3609 gen_qemu_st32(ctx, t1, arg2);
3610 tcg_temp_free(t1);
3611 }
3612
3613 /* stfd stfdu stfdux stfdx */
3614 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT);
3615 /* stfs stfsu stfsux stfsx */
3616 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT);
3617
3618 /* stfdp */
3619 static void gen_stfdp(DisasContext *ctx)
3620 {
3621 TCGv EA;
3622 if (unlikely(!ctx->fpu_enabled)) {
3623 gen_exception(ctx, POWERPC_EXCP_FPU);
3624 return;
3625 }
3626 gen_set_access_type(ctx, ACCESS_FLOAT);
3627 EA = tcg_temp_new();
3628 gen_addr_imm_index(ctx, EA, 0); \
3629 if (unlikely(ctx->le_mode)) {
3630 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3631 tcg_gen_addi_tl(EA, EA, 8);
3632 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3633 } else {
3634 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3635 tcg_gen_addi_tl(EA, EA, 8);
3636 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3637 }
3638 tcg_temp_free(EA);
3639 }
3640
3641 /* stfdpx */
3642 static void gen_stfdpx(DisasContext *ctx)
3643 {
3644 TCGv EA;
3645 if (unlikely(!ctx->fpu_enabled)) {
3646 gen_exception(ctx, POWERPC_EXCP_FPU);
3647 return;
3648 }
3649 gen_set_access_type(ctx, ACCESS_FLOAT);
3650 EA = tcg_temp_new();
3651 gen_addr_reg_index(ctx, EA);
3652 if (unlikely(ctx->le_mode)) {
3653 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3654 tcg_gen_addi_tl(EA, EA, 8);
3655 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3656 } else {
3657 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode)], EA);
3658 tcg_gen_addi_tl(EA, EA, 8);
3659 gen_qemu_st64(ctx, cpu_fpr[rD(ctx->opcode) + 1], EA);
3660 }
3661 tcg_temp_free(EA);
3662 }
3663
3664 /* Optional: */
3665 static inline void gen_qemu_st32fiw(DisasContext *ctx, TCGv_i64 arg1, TCGv arg2)
3666 {
3667 TCGv t0 = tcg_temp_new();
3668 tcg_gen_trunc_i64_tl(t0, arg1),
3669 gen_qemu_st32(ctx, t0, arg2);
3670 tcg_temp_free(t0);
3671 }
3672 /* stfiwx */
3673 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX);
3674
3675 static inline void gen_update_cfar(DisasContext *ctx, target_ulong nip)
3676 {
3677 #if defined(TARGET_PPC64)
3678 if (ctx->has_cfar)
3679 tcg_gen_movi_tl(cpu_cfar, nip);
3680 #endif
3681 }
3682
3683 /*** Branch ***/
3684 static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest)
3685 {
3686 TranslationBlock *tb;
3687 tb = ctx->tb;
3688 if (NARROW_MODE(ctx)) {
3689 dest = (uint32_t) dest;
3690 }
3691 if ((tb->pc & TARGET_PAGE_MASK) == (dest & TARGET_PAGE_MASK) &&
3692 likely(!ctx->singlestep_enabled)) {
3693 tcg_gen_goto_tb(n);
3694 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3695 tcg_gen_exit_tb((uintptr_t)tb + n);
3696 } else {
3697 tcg_gen_movi_tl(cpu_nip, dest & ~3);
3698 if (unlikely(ctx->singlestep_enabled)) {
3699 if ((ctx->singlestep_enabled &
3700 (CPU_BRANCH_STEP | CPU_SINGLE_STEP)) &&
3701 (ctx->exception == POWERPC_EXCP_BRANCH ||
3702 ctx->exception == POWERPC_EXCP_TRACE)) {
3703 target_ulong tmp = ctx->nip;
3704 ctx->nip = dest;
3705 gen_exception(ctx, POWERPC_EXCP_TRACE);
3706 ctx->nip = tmp;
3707 }
3708 if (ctx->singlestep_enabled & GDBSTUB_SINGLE_STEP) {
3709 gen_debug_exception(ctx);
3710 }
3711 }
3712 tcg_gen_exit_tb(0);
3713 }
3714 }
3715
3716 static inline void gen_setlr(DisasContext *ctx, target_ulong nip)
3717 {
3718 if (NARROW_MODE(ctx)) {
3719 nip = (uint32_t)nip;
3720 }
3721 tcg_gen_movi_tl(cpu_lr, nip);
3722 }
3723
3724 /* b ba bl bla */
3725 static void gen_b(DisasContext *ctx)
3726 {
3727 target_ulong li, target;
3728
3729 ctx->exception = POWERPC_EXCP_BRANCH;
3730 /* sign extend LI */
3731 li = LI(ctx->opcode);
3732 li = (li ^ 0x02000000) - 0x02000000;
3733 if (likely(AA(ctx->opcode) == 0)) {
3734 target = ctx->nip + li - 4;
3735 } else {
3736 target = li;
3737 }
3738 if (LK(ctx->opcode)) {
3739 gen_setlr(ctx, ctx->nip);
3740 }
3741 gen_update_cfar(ctx, ctx->nip);
3742 gen_goto_tb(ctx, 0, target);
3743 }
3744
3745 #define BCOND_IM 0
3746 #define BCOND_LR 1
3747 #define BCOND_CTR 2
3748
3749 static inline void gen_bcond(DisasContext *ctx, int type)
3750 {
3751 uint32_t bo = BO(ctx->opcode);
3752 int l1;
3753 TCGv target;
3754
3755 ctx->exception = POWERPC_EXCP_BRANCH;
3756 if (type == BCOND_LR || type == BCOND_CTR) {
3757 target = tcg_temp_local_new();
3758 if (type == BCOND_CTR)
3759 tcg_gen_mov_tl(target, cpu_ctr);
3760 else
3761 tcg_gen_mov_tl(target, cpu_lr);
3762 } else {
3763 TCGV_UNUSED(target);
3764 }
3765 if (LK(ctx->opcode))
3766 gen_setlr(ctx, ctx->nip);
3767 l1 = gen_new_label();
3768 if ((bo & 0x4) == 0) {
3769 /* Decrement and test CTR */
3770 TCGv temp = tcg_temp_new();
3771 if (unlikely(type == BCOND_CTR)) {
3772 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
3773 return;
3774 }
3775 tcg_gen_subi_tl(cpu_ctr, cpu_ctr, 1);
3776 if (NARROW_MODE(ctx)) {
3777 tcg_gen_ext32u_tl(temp, cpu_ctr);
3778 } else {
3779 tcg_gen_mov_tl(temp, cpu_ctr);
3780 }
3781 if (bo & 0x2) {
3782 tcg_gen_brcondi_tl(TCG_COND_NE, temp, 0, l1);
3783 } else {
3784 tcg_gen_brcondi_tl(TCG_COND_EQ, temp, 0, l1);
3785 }
3786 tcg_temp_free(temp);
3787 }
3788 if ((bo & 0x10) == 0) {
3789 /* Test CR */
3790 uint32_t bi = BI(ctx->opcode);
3791 uint32_t mask = 1 << (3 - (bi & 0x03));
3792 TCGv_i32 temp = tcg_temp_new_i32();
3793
3794 if (bo & 0x8) {
3795 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3796 tcg_gen_brcondi_i32(TCG_COND_EQ, temp, 0, l1);
3797 } else {
3798 tcg_gen_andi_i32(temp, cpu_crf[bi >> 2], mask);
3799 tcg_gen_brcondi_i32(TCG_COND_NE, temp, 0, l1);
3800 }
3801 tcg_temp_free_i32(temp);
3802 }
3803 gen_update_cfar(ctx, ctx->nip);
3804 if (type == BCOND_IM) {
3805 target_ulong li = (target_long)((int16_t)(BD(ctx->opcode)));
3806 if (likely(AA(ctx->opcode) == 0)) {
3807 gen_goto_tb(ctx, 0, ctx->nip + li - 4);
3808 } else {
3809 gen_goto_tb(ctx, 0, li);
3810 }
3811 gen_set_label(l1);
3812 gen_goto_tb(ctx, 1, ctx->nip);
3813 } else {
3814 if (NARROW_MODE(ctx)) {
3815 tcg_gen_andi_tl(cpu_nip, target, (uint32_t)~3);
3816 } else {
3817 tcg_gen_andi_tl(cpu_nip, target, ~3);
3818 }
3819 tcg_gen_exit_tb(0);
3820 gen_set_label(l1);
3821 gen_update_nip(ctx, ctx->nip);
3822 tcg_gen_exit_tb(0);
3823 }
3824 }
3825
3826 static void gen_bc(DisasContext *ctx)
3827 {
3828 gen_bcond(ctx, BCOND_IM);
3829 }
3830
3831 static void gen_bcctr(DisasContext *ctx)
3832 {
3833 gen_bcond(ctx, BCOND_CTR);
3834 }
3835
3836 static void gen_bclr(DisasContext *ctx)
3837 {
3838 gen_bcond(ctx, BCOND_LR);
3839 }
3840
3841 /*** Condition register logical ***/
3842 #define GEN_CRLOGIC(name, tcg_op, opc) \
3843 static void glue(gen_, name)(DisasContext *ctx) \
3844 { \
3845 uint8_t bitmask; \
3846 int sh; \
3847 TCGv_i32 t0, t1; \
3848 sh = (crbD(ctx->opcode) & 0x03) - (crbA(ctx->opcode) & 0x03); \
3849 t0 = tcg_temp_new_i32(); \
3850 if (sh > 0) \
3851 tcg_gen_shri_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], sh); \
3852 else if (sh < 0) \
3853 tcg_gen_shli_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2], -sh); \
3854 else \
3855 tcg_gen_mov_i32(t0, cpu_crf[crbA(ctx->opcode) >> 2]); \
3856 t1 = tcg_temp_new_i32(); \
3857 sh = (crbD(ctx->opcode) & 0x03) - (crbB(ctx->opcode) & 0x03); \
3858 if (sh > 0) \
3859 tcg_gen_shri_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], sh); \
3860 else if (sh < 0) \
3861 tcg_gen_shli_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2], -sh); \
3862 else \
3863 tcg_gen_mov_i32(t1, cpu_crf[crbB(ctx->opcode) >> 2]); \
3864 tcg_op(t0, t0, t1); \
3865 bitmask = 1 << (3 - (crbD(ctx->opcode) & 0x03)); \
3866 tcg_gen_andi_i32(t0, t0, bitmask); \
3867 tcg_gen_andi_i32(t1, cpu_crf[crbD(ctx->opcode) >> 2], ~bitmask); \
3868 tcg_gen_or_i32(cpu_crf[crbD(ctx->opcode) >> 2], t0, t1); \
3869 tcg_temp_free_i32(t0); \
3870 tcg_temp_free_i32(t1); \
3871 }
3872
3873 /* crand */
3874 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08);
3875 /* crandc */
3876 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04);
3877 /* creqv */
3878 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09);
3879 /* crnand */
3880 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07);
3881 /* crnor */
3882 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01);
3883 /* cror */
3884 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E);
3885 /* crorc */
3886 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D);
3887 /* crxor */
3888 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06);
3889
3890 /* mcrf */
3891 static void gen_mcrf(DisasContext *ctx)
3892 {
3893 tcg_gen_mov_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfS(ctx->opcode)]);
3894 }
3895
3896 /*** System linkage ***/
3897
3898 /* rfi (mem_idx only) */
3899 static void gen_rfi(DisasContext *ctx)
3900 {
3901 #if defined(CONFIG_USER_ONLY)
3902 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3903 #else
3904 /* Restore CPU state */
3905 if (unlikely(!ctx->mem_idx)) {
3906 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3907 return;
3908 }
3909 gen_update_cfar(ctx, ctx->nip);
3910 gen_helper_rfi(cpu_env);
3911 gen_sync_exception(ctx);
3912 #endif
3913 }
3914
3915 #if defined(TARGET_PPC64)
3916 static void gen_rfid(DisasContext *ctx)
3917 {
3918 #if defined(CONFIG_USER_ONLY)
3919 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3920 #else
3921 /* Restore CPU state */
3922 if (unlikely(!ctx->mem_idx)) {
3923 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3924 return;
3925 }
3926 gen_update_cfar(ctx, ctx->nip);
3927 gen_helper_rfid(cpu_env);
3928 gen_sync_exception(ctx);
3929 #endif
3930 }
3931
3932 static void gen_hrfid(DisasContext *ctx)
3933 {
3934 #if defined(CONFIG_USER_ONLY)
3935 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3936 #else
3937 /* Restore CPU state */
3938 if (unlikely(ctx->mem_idx <= 1)) {
3939 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
3940 return;
3941 }
3942 gen_helper_hrfid(cpu_env);
3943 gen_sync_exception(ctx);
3944 #endif
3945 }
3946 #endif
3947
3948 /* sc */
3949 #if defined(CONFIG_USER_ONLY)
3950 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL_USER
3951 #else
3952 #define POWERPC_SYSCALL POWERPC_EXCP_SYSCALL
3953 #endif
3954 static void gen_sc(DisasContext *ctx)
3955 {
3956 uint32_t lev;
3957
3958 lev = (ctx->opcode >> 5) & 0x7F;
3959 gen_exception_err(ctx, POWERPC_SYSCALL, lev);
3960 }
3961
3962 /*** Trap ***/
3963
3964 /* tw */
3965 static void gen_tw(DisasContext *ctx)
3966 {
3967 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3968 /* Update the nip since this might generate a trap exception */
3969 gen_update_nip(ctx, ctx->nip);
3970 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3971 t0);
3972 tcg_temp_free_i32(t0);
3973 }
3974
3975 /* twi */
3976 static void gen_twi(DisasContext *ctx)
3977 {
3978 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
3979 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
3980 /* Update the nip since this might generate a trap exception */
3981 gen_update_nip(ctx, ctx->nip);
3982 gen_helper_tw(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
3983 tcg_temp_free(t0);
3984 tcg_temp_free_i32(t1);
3985 }
3986
3987 #if defined(TARGET_PPC64)
3988 /* td */
3989 static void gen_td(DisasContext *ctx)
3990 {
3991 TCGv_i32 t0 = tcg_const_i32(TO(ctx->opcode));
3992 /* Update the nip since this might generate a trap exception */
3993 gen_update_nip(ctx, ctx->nip);
3994 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)],
3995 t0);
3996 tcg_temp_free_i32(t0);
3997 }
3998
3999 /* tdi */
4000 static void gen_tdi(DisasContext *ctx)
4001 {
4002 TCGv t0 = tcg_const_tl(SIMM(ctx->opcode));
4003 TCGv_i32 t1 = tcg_const_i32(TO(ctx->opcode));
4004 /* Update the nip since this might generate a trap exception */
4005 gen_update_nip(ctx, ctx->nip);
4006 gen_helper_td(cpu_env, cpu_gpr[rA(ctx->opcode)], t0, t1);
4007 tcg_temp_free(t0);
4008 tcg_temp_free_i32(t1);
4009 }
4010 #endif
4011
4012 /*** Processor control ***/
4013
4014 static void gen_read_xer(TCGv dst)
4015 {
4016 TCGv t0 = tcg_temp_new();
4017 TCGv t1 = tcg_temp_new();
4018 TCGv t2 = tcg_temp_new();
4019 tcg_gen_mov_tl(dst, cpu_xer);
4020 tcg_gen_shli_tl(t0, cpu_so, XER_SO);
4021 tcg_gen_shli_tl(t1, cpu_ov, XER_OV);
4022 tcg_gen_shli_tl(t2, cpu_ca, XER_CA);
4023 tcg_gen_or_tl(t0, t0, t1);
4024 tcg_gen_or_tl(dst, dst, t2);
4025 tcg_gen_or_tl(dst, dst, t0);
4026 tcg_temp_free(t0);
4027 tcg_temp_free(t1);
4028 tcg_temp_free(t2);
4029 }
4030
4031 static void gen_write_xer(TCGv src)
4032 {
4033 tcg_gen_andi_tl(cpu_xer, src,
4034 ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA)));
4035 tcg_gen_shri_tl(cpu_so, src, XER_SO);
4036 tcg_gen_shri_tl(cpu_ov, src, XER_OV);
4037 tcg_gen_shri_tl(cpu_ca, src, XER_CA);
4038 tcg_gen_andi_tl(cpu_so, cpu_so, 1);
4039 tcg_gen_andi_tl(cpu_ov, cpu_ov, 1);
4040 tcg_gen_andi_tl(cpu_ca, cpu_ca, 1);
4041 }
4042
4043 /* mcrxr */
4044 static void gen_mcrxr(DisasContext *ctx)
4045 {
4046 TCGv_i32 t0 = tcg_temp_new_i32();
4047 TCGv_i32 t1 = tcg_temp_new_i32();
4048 TCGv_i32 dst = cpu_crf[crfD(ctx->opcode)];
4049
4050 tcg_gen_trunc_tl_i32(t0, cpu_so);
4051 tcg_gen_trunc_tl_i32(t1, cpu_ov);
4052 tcg_gen_trunc_tl_i32(dst, cpu_ca);
4053 tcg_gen_shri_i32(t0, t0, 2);
4054 tcg_gen_shri_i32(t1, t1, 1);
4055 tcg_gen_or_i32(dst, dst, t0);
4056 tcg_gen_or_i32(dst, dst, t1);
4057 tcg_temp_free_i32(t0);
4058 tcg_temp_free_i32(t1);
4059
4060 tcg_gen_movi_tl(cpu_so, 0);
4061 tcg_gen_movi_tl(cpu_ov, 0);
4062 tcg_gen_movi_tl(cpu_ca, 0);
4063 }
4064
4065 /* mfcr mfocrf */
4066 static void gen_mfcr(DisasContext *ctx)
4067 {
4068 uint32_t crm, crn;
4069
4070 if (likely(ctx->opcode & 0x00100000)) {
4071 crm = CRM(ctx->opcode);
4072 if (likely(crm && ((crm & (crm - 1)) == 0))) {
4073 crn = ctz32 (crm);
4074 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], cpu_crf[7 - crn]);
4075 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)],
4076 cpu_gpr[rD(ctx->opcode)], crn * 4);
4077 }
4078 } else {
4079 TCGv_i32 t0 = tcg_temp_new_i32();
4080 tcg_gen_mov_i32(t0, cpu_crf[0]);
4081 tcg_gen_shli_i32(t0, t0, 4);
4082 tcg_gen_or_i32(t0, t0, cpu_crf[1]);
4083 tcg_gen_shli_i32(t0, t0, 4);
4084 tcg_gen_or_i32(t0, t0, cpu_crf[2]);
4085 tcg_gen_shli_i32(t0, t0, 4);
4086 tcg_gen_or_i32(t0, t0, cpu_crf[3]);
4087 tcg_gen_shli_i32(t0, t0, 4);
4088 tcg_gen_or_i32(t0, t0, cpu_crf[4]);
4089 tcg_gen_shli_i32(t0, t0, 4);
4090 tcg_gen_or_i32(t0, t0, cpu_crf[5]);
4091 tcg_gen_shli_i32(t0, t0, 4);
4092 tcg_gen_or_i32(t0, t0, cpu_crf[6]);
4093 tcg_gen_shli_i32(t0, t0, 4);
4094 tcg_gen_or_i32(t0, t0, cpu_crf[7]);
4095 tcg_gen_extu_i32_tl(cpu_gpr[rD(ctx->opcode)], t0);
4096 tcg_temp_free_i32(t0);
4097 }
4098 }
4099
4100 /* mfmsr */
4101 static void gen_mfmsr(DisasContext *ctx)
4102 {
4103 #if defined(CONFIG_USER_ONLY)
4104 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4105 #else
4106 if (unlikely(!ctx->mem_idx)) {
4107 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4108 return;
4109 }
4110 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_msr);
4111 #endif
4112 }
4113
4114 static void spr_noaccess(void *opaque, int gprn, int sprn)
4115 {
4116 #if 0
4117 sprn = ((sprn >> 5) & 0x1F) | ((sprn & 0x1F) << 5);
4118 printf("ERROR: try to access SPR %d !\n", sprn);
4119 #endif
4120 }
4121 #define SPR_NOACCESS (&spr_noaccess)
4122
4123 /* mfspr */
4124 static inline void gen_op_mfspr(DisasContext *ctx)
4125 {
4126 void (*read_cb)(void *opaque, int gprn, int sprn);
4127 uint32_t sprn = SPR(ctx->opcode);
4128
4129 #if !defined(CONFIG_USER_ONLY)
4130 if (ctx->mem_idx == 2)
4131 read_cb = ctx->spr_cb[sprn].hea_read;
4132 else if (ctx->mem_idx)
4133 read_cb = ctx->spr_cb[sprn].oea_read;
4134 else
4135 #endif
4136 read_cb = ctx->spr_cb[sprn].uea_read;
4137 if (likely(read_cb != NULL)) {
4138 if (likely(read_cb != SPR_NOACCESS)) {
4139 (*read_cb)(ctx, rD(ctx->opcode), sprn);
4140 } else {
4141 /* Privilege exception */
4142 /* This is a hack to avoid warnings when running Linux:
4143 * this OS breaks the PowerPC virtualisation model,
4144 * allowing userland application to read the PVR
4145 */
4146 if (sprn != SPR_PVR) {
4147 qemu_log("Trying to read privileged spr %d (0x%03x) at "
4148 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4149 printf("Trying to read privileged spr %d (0x%03x) at "
4150 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4151 }
4152 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4153 }
4154 } else {
4155 /* Not defined */
4156 qemu_log("Trying to read invalid spr %d (0x%03x) at "
4157 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4158 printf("Trying to read invalid spr %d (0x%03x) at "
4159 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4160 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4161 }
4162 }
4163
4164 static void gen_mfspr(DisasContext *ctx)
4165 {
4166 gen_op_mfspr(ctx);
4167 }
4168
4169 /* mftb */
4170 static void gen_mftb(DisasContext *ctx)
4171 {
4172 gen_op_mfspr(ctx);
4173 }
4174
4175 /* mtcrf mtocrf*/
4176 static void gen_mtcrf(DisasContext *ctx)
4177 {
4178 uint32_t crm, crn;
4179
4180 crm = CRM(ctx->opcode);
4181 if (likely((ctx->opcode & 0x00100000))) {
4182 if (crm && ((crm & (crm - 1)) == 0)) {
4183 TCGv_i32 temp = tcg_temp_new_i32();
4184 crn = ctz32 (crm);
4185 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4186 tcg_gen_shri_i32(temp, temp, crn * 4);
4187 tcg_gen_andi_i32(cpu_crf[7 - crn], temp, 0xf);
4188 tcg_temp_free_i32(temp);
4189 }
4190 } else {
4191 TCGv_i32 temp = tcg_temp_new_i32();
4192 tcg_gen_trunc_tl_i32(temp, cpu_gpr[rS(ctx->opcode)]);
4193 for (crn = 0 ; crn < 8 ; crn++) {
4194 if (crm & (1 << crn)) {
4195 tcg_gen_shri_i32(cpu_crf[7 - crn], temp, crn * 4);
4196 tcg_gen_andi_i32(cpu_crf[7 - crn], cpu_crf[7 - crn], 0xf);
4197 }
4198 }
4199 tcg_temp_free_i32(temp);
4200 }
4201 }
4202
4203 /* mtmsr */
4204 #if defined(TARGET_PPC64)
4205 static void gen_mtmsrd(DisasContext *ctx)
4206 {
4207 #if defined(CONFIG_USER_ONLY)
4208 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4209 #else
4210 if (unlikely(!ctx->mem_idx)) {
4211 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4212 return;
4213 }
4214 if (ctx->opcode & 0x00010000) {
4215 /* Special form that does not need any synchronisation */
4216 TCGv t0 = tcg_temp_new();
4217 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4218 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4219 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4220 tcg_temp_free(t0);
4221 } else {
4222 /* XXX: we need to update nip before the store
4223 * if we enter power saving mode, we will exit the loop
4224 * directly from ppc_store_msr
4225 */
4226 gen_update_nip(ctx, ctx->nip);
4227 gen_helper_store_msr(cpu_env, cpu_gpr[rS(ctx->opcode)]);
4228 /* Must stop the translation as machine state (may have) changed */
4229 /* Note that mtmsr is not always defined as context-synchronizing */
4230 gen_stop_exception(ctx);
4231 }
4232 #endif
4233 }
4234 #endif
4235
4236 static void gen_mtmsr(DisasContext *ctx)
4237 {
4238 #if defined(CONFIG_USER_ONLY)
4239 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4240 #else
4241 if (unlikely(!ctx->mem_idx)) {
4242 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4243 return;
4244 }
4245 if (ctx->opcode & 0x00010000) {
4246 /* Special form that does not need any synchronisation */
4247 TCGv t0 = tcg_temp_new();
4248 tcg_gen_andi_tl(t0, cpu_gpr[rS(ctx->opcode)], (1 << MSR_RI) | (1 << MSR_EE));
4249 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~((1 << MSR_RI) | (1 << MSR_EE)));
4250 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
4251 tcg_temp_free(t0);
4252 } else {
4253 TCGv msr = tcg_temp_new();
4254
4255 /* XXX: we need to update nip before the store
4256 * if we enter power saving mode, we will exit the loop
4257 * directly from ppc_store_msr
4258 */
4259 gen_update_nip(ctx, ctx->nip);
4260 #if defined(TARGET_PPC64)
4261 tcg_gen_deposit_tl(msr, cpu_msr, cpu_gpr[rS(ctx->opcode)], 0, 32);
4262 #else
4263 tcg_gen_mov_tl(msr, cpu_gpr[rS(ctx->opcode)]);
4264 #endif
4265 gen_helper_store_msr(cpu_env, msr);
4266 /* Must stop the translation as machine state (may have) changed */
4267 /* Note that mtmsr is not always defined as context-synchronizing */
4268 gen_stop_exception(ctx);
4269 }
4270 #endif
4271 }
4272
4273 /* mtspr */
4274 static void gen_mtspr(DisasContext *ctx)
4275 {
4276 void (*write_cb)(void *opaque, int sprn, int gprn);
4277 uint32_t sprn = SPR(ctx->opcode);
4278
4279 #if !defined(CONFIG_USER_ONLY)
4280 if (ctx->mem_idx == 2)
4281 write_cb = ctx->spr_cb[sprn].hea_write;
4282 else if (ctx->mem_idx)
4283 write_cb = ctx->spr_cb[sprn].oea_write;
4284 else
4285 #endif
4286 write_cb = ctx->spr_cb[sprn].uea_write;
4287 if (likely(write_cb != NULL)) {
4288 if (likely(write_cb != SPR_NOACCESS)) {
4289 (*write_cb)(ctx, sprn, rS(ctx->opcode));
4290 } else {
4291 /* Privilege exception */
4292 qemu_log("Trying to write privileged spr %d (0x%03x) at "
4293 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4294 printf("Trying to write privileged spr %d (0x%03x) at "
4295 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4296 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4297 }
4298 } else {
4299 /* Not defined */
4300 qemu_log("Trying to write invalid spr %d (0x%03x) at "
4301 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4302 printf("Trying to write invalid spr %d (0x%03x) at "
4303 TARGET_FMT_lx "\n", sprn, sprn, ctx->nip - 4);
4304 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_SPR);
4305 }
4306 }
4307
4308 /*** Cache management ***/
4309
4310 /* dcbf */
4311 static void gen_dcbf(DisasContext *ctx)
4312 {
4313 /* XXX: specification says this is treated as a load by the MMU */
4314 TCGv t0;
4315 gen_set_access_type(ctx, ACCESS_CACHE);
4316 t0 = tcg_temp_new();
4317 gen_addr_reg_index(ctx, t0);
4318 gen_qemu_ld8u(ctx, t0, t0);
4319 tcg_temp_free(t0);
4320 }
4321
4322 /* dcbi (Supervisor only) */
4323 static void gen_dcbi(DisasContext *ctx)
4324 {
4325 #if defined(CONFIG_USER_ONLY)
4326 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4327 #else
4328 TCGv EA, val;
4329 if (unlikely(!ctx->mem_idx)) {
4330 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4331 return;
4332 }
4333 EA = tcg_temp_new();
4334 gen_set_access_type(ctx, ACCESS_CACHE);
4335 gen_addr_reg_index(ctx, EA);
4336 val = tcg_temp_new();
4337 /* XXX: specification says this should be treated as a store by the MMU */
4338 gen_qemu_ld8u(ctx, val, EA);
4339 gen_qemu_st8(ctx, val, EA);
4340 tcg_temp_free(val);
4341 tcg_temp_free(EA);
4342 #endif
4343 }
4344
4345 /* dcdst */
4346 static void gen_dcbst(DisasContext *ctx)
4347 {
4348 /* XXX: specification say this is treated as a load by the MMU */
4349 TCGv t0;
4350 gen_set_access_type(ctx, ACCESS_CACHE);
4351 t0 = tcg_temp_new();
4352 gen_addr_reg_index(ctx, t0);
4353 gen_qemu_ld8u(ctx, t0, t0);
4354 tcg_temp_free(t0);
4355 }
4356
4357 /* dcbt */
4358 static void gen_dcbt(DisasContext *ctx)
4359 {
4360 /* interpreted as no-op */
4361 /* XXX: specification say this is treated as a load by the MMU
4362 * but does not generate any exception
4363 */
4364 }
4365
4366 /* dcbtst */
4367 static void gen_dcbtst(DisasContext *ctx)
4368 {
4369 /* interpreted as no-op */
4370 /* XXX: specification say this is treated as a load by the MMU
4371 * but does not generate any exception
4372 */
4373 }
4374
4375 /* dcbz */
4376 static void gen_dcbz(DisasContext *ctx)
4377 {
4378 TCGv tcgv_addr;
4379 TCGv_i32 tcgv_is_dcbzl;
4380 int is_dcbzl = ctx->opcode & 0x00200000 ? 1 : 0;
4381
4382 gen_set_access_type(ctx, ACCESS_CACHE);
4383 /* NIP cannot be restored if the memory exception comes from an helper */
4384 gen_update_nip(ctx, ctx->nip - 4);
4385 tcgv_addr = tcg_temp_new();
4386 tcgv_is_dcbzl = tcg_const_i32(is_dcbzl);
4387
4388 gen_addr_reg_index(ctx, tcgv_addr);
4389 gen_helper_dcbz(cpu_env, tcgv_addr, tcgv_is_dcbzl);
4390
4391 tcg_temp_free(tcgv_addr);
4392 tcg_temp_free_i32(tcgv_is_dcbzl);
4393 }
4394
4395 /* dst / dstt */
4396 static void gen_dst(DisasContext *ctx)
4397 {
4398 if (rA(ctx->opcode) == 0) {
4399 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4400 } else {
4401 /* interpreted as no-op */
4402 }
4403 }
4404
4405 /* dstst /dststt */
4406 static void gen_dstst(DisasContext *ctx)
4407 {
4408 if (rA(ctx->opcode) == 0) {
4409 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_LSWX);
4410 } else {
4411 /* interpreted as no-op */
4412 }
4413
4414 }
4415
4416 /* dss / dssall */
4417 static void gen_dss(DisasContext *ctx)
4418 {
4419 /* interpreted as no-op */
4420 }
4421
4422 /* icbi */
4423 static void gen_icbi(DisasContext *ctx)
4424 {
4425 TCGv t0;
4426 gen_set_access_type(ctx, ACCESS_CACHE);
4427 /* NIP cannot be restored if the memory exception comes from an helper */
4428 gen_update_nip(ctx, ctx->nip - 4);
4429 t0 = tcg_temp_new();
4430 gen_addr_reg_index(ctx, t0);
4431 gen_helper_icbi(cpu_env, t0);
4432 tcg_temp_free(t0);
4433 }
4434
4435 /* Optional: */
4436 /* dcba */
4437 static void gen_dcba(DisasContext *ctx)
4438 {
4439 /* interpreted as no-op */
4440 /* XXX: specification say this is treated as a store by the MMU
4441 * but does not generate any exception
4442 */
4443 }
4444
4445 /*** Segment register manipulation ***/
4446 /* Supervisor only: */
4447
4448 /* mfsr */
4449 static void gen_mfsr(DisasContext *ctx)
4450 {
4451 #if defined(CONFIG_USER_ONLY)
4452 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4453 #else
4454 TCGv t0;
4455 if (unlikely(!ctx->mem_idx)) {
4456 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4457 return;
4458 }
4459 t0 = tcg_const_tl(SR(ctx->opcode));
4460 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4461 tcg_temp_free(t0);
4462 #endif
4463 }
4464
4465 /* mfsrin */
4466 static void gen_mfsrin(DisasContext *ctx)
4467 {
4468 #if defined(CONFIG_USER_ONLY)
4469 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4470 #else
4471 TCGv t0;
4472 if (unlikely(!ctx->mem_idx)) {
4473 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4474 return;
4475 }
4476 t0 = tcg_temp_new();
4477 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4478 tcg_gen_andi_tl(t0, t0, 0xF);
4479 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4480 tcg_temp_free(t0);
4481 #endif
4482 }
4483
4484 /* mtsr */
4485 static void gen_mtsr(DisasContext *ctx)
4486 {
4487 #if defined(CONFIG_USER_ONLY)
4488 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4489 #else
4490 TCGv t0;
4491 if (unlikely(!ctx->mem_idx)) {
4492 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4493 return;
4494 }
4495 t0 = tcg_const_tl(SR(ctx->opcode));
4496 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4497 tcg_temp_free(t0);
4498 #endif
4499 }
4500
4501 /* mtsrin */
4502 static void gen_mtsrin(DisasContext *ctx)
4503 {
4504 #if defined(CONFIG_USER_ONLY)
4505 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4506 #else
4507 TCGv t0;
4508 if (unlikely(!ctx->mem_idx)) {
4509 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4510 return;
4511 }
4512 t0 = tcg_temp_new();
4513 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4514 tcg_gen_andi_tl(t0, t0, 0xF);
4515 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rD(ctx->opcode)]);
4516 tcg_temp_free(t0);
4517 #endif
4518 }
4519
4520 #if defined(TARGET_PPC64)
4521 /* Specific implementation for PowerPC 64 "bridge" emulation using SLB */
4522
4523 /* mfsr */
4524 static void gen_mfsr_64b(DisasContext *ctx)
4525 {
4526 #if defined(CONFIG_USER_ONLY)
4527 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4528 #else
4529 TCGv t0;
4530 if (unlikely(!ctx->mem_idx)) {
4531 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4532 return;
4533 }
4534 t0 = tcg_const_tl(SR(ctx->opcode));
4535 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4536 tcg_temp_free(t0);
4537 #endif
4538 }
4539
4540 /* mfsrin */
4541 static void gen_mfsrin_64b(DisasContext *ctx)
4542 {
4543 #if defined(CONFIG_USER_ONLY)
4544 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4545 #else
4546 TCGv t0;
4547 if (unlikely(!ctx->mem_idx)) {
4548 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4549 return;
4550 }
4551 t0 = tcg_temp_new();
4552 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4553 tcg_gen_andi_tl(t0, t0, 0xF);
4554 gen_helper_load_sr(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4555 tcg_temp_free(t0);
4556 #endif
4557 }
4558
4559 /* mtsr */
4560 static void gen_mtsr_64b(DisasContext *ctx)
4561 {
4562 #if defined(CONFIG_USER_ONLY)
4563 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4564 #else
4565 TCGv t0;
4566 if (unlikely(!ctx->mem_idx)) {
4567 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4568 return;
4569 }
4570 t0 = tcg_const_tl(SR(ctx->opcode));
4571 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4572 tcg_temp_free(t0);
4573 #endif
4574 }
4575
4576 /* mtsrin */
4577 static void gen_mtsrin_64b(DisasContext *ctx)
4578 {
4579 #if defined(CONFIG_USER_ONLY)
4580 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4581 #else
4582 TCGv t0;
4583 if (unlikely(!ctx->mem_idx)) {
4584 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4585 return;
4586 }
4587 t0 = tcg_temp_new();
4588 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 28);
4589 tcg_gen_andi_tl(t0, t0, 0xF);
4590 gen_helper_store_sr(cpu_env, t0, cpu_gpr[rS(ctx->opcode)]);
4591 tcg_temp_free(t0);
4592 #endif
4593 }
4594
4595 /* slbmte */
4596 static void gen_slbmte(DisasContext *ctx)
4597 {
4598 #if defined(CONFIG_USER_ONLY)
4599 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4600 #else
4601 if (unlikely(!ctx->mem_idx)) {
4602 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4603 return;
4604 }
4605 gen_helper_store_slb(cpu_env, cpu_gpr[rB(ctx->opcode)],
4606 cpu_gpr[rS(ctx->opcode)]);
4607 #endif
4608 }
4609
4610 static void gen_slbmfee(DisasContext *ctx)
4611 {
4612 #if defined(CONFIG_USER_ONLY)
4613 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4614 #else
4615 if (unlikely(!ctx->mem_idx)) {
4616 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4617 return;
4618 }
4619 gen_helper_load_slb_esid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4620 cpu_gpr[rB(ctx->opcode)]);
4621 #endif
4622 }
4623
4624 static void gen_slbmfev(DisasContext *ctx)
4625 {
4626 #if defined(CONFIG_USER_ONLY)
4627 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4628 #else
4629 if (unlikely(!ctx->mem_idx)) {
4630 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
4631 return;
4632 }
4633 gen_helper_load_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
4634 cpu_gpr[rB(ctx->opcode)]);
4635 #endif
4636 }
4637 #endif /* defined(TARGET_PPC64) */
4638
4639 /*** Lookaside buffer management ***/
4640 /* Optional & mem_idx only: */
4641
4642 /* tlbia */
4643 static void gen_tlbia(DisasContext *ctx)
4644 {
4645 #if defined(CONFIG_USER_ONLY)
4646 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4647 #else
4648 if (unlikely(!ctx->mem_idx)) {
4649 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4650 return;
4651 }
4652 gen_helper_tlbia(cpu_env);
4653 #endif
4654 }
4655
4656 /* tlbiel */
4657 static void gen_tlbiel(DisasContext *ctx)
4658 {
4659 #if defined(CONFIG_USER_ONLY)
4660 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4661 #else
4662 if (unlikely(!ctx->mem_idx)) {
4663 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4664 return;
4665 }
4666 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4667 #endif
4668 }
4669
4670 /* tlbie */
4671 static void gen_tlbie(DisasContext *ctx)
4672 {
4673 #if defined(CONFIG_USER_ONLY)
4674 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4675 #else
4676 if (unlikely(!ctx->mem_idx)) {
4677 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4678 return;
4679 }
4680 if (NARROW_MODE(ctx)) {
4681 TCGv t0 = tcg_temp_new();
4682 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
4683 gen_helper_tlbie(cpu_env, t0);
4684 tcg_temp_free(t0);
4685 } else {
4686 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4687 }
4688 #endif
4689 }
4690
4691 /* tlbsync */
4692 static void gen_tlbsync(DisasContext *ctx)
4693 {
4694 #if defined(CONFIG_USER_ONLY)
4695 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4696 #else
4697 if (unlikely(!ctx->mem_idx)) {
4698 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4699 return;
4700 }
4701 /* This has no effect: it should ensure that all previous
4702 * tlbie have completed
4703 */
4704 gen_stop_exception(ctx);
4705 #endif
4706 }
4707
4708 #if defined(TARGET_PPC64)
4709 /* slbia */
4710 static void gen_slbia(DisasContext *ctx)
4711 {
4712 #if defined(CONFIG_USER_ONLY)
4713 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4714 #else
4715 if (unlikely(!ctx->mem_idx)) {
4716 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4717 return;
4718 }
4719 gen_helper_slbia(cpu_env);
4720 #endif
4721 }
4722
4723 /* slbie */
4724 static void gen_slbie(DisasContext *ctx)
4725 {
4726 #if defined(CONFIG_USER_ONLY)
4727 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4728 #else
4729 if (unlikely(!ctx->mem_idx)) {
4730 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
4731 return;
4732 }
4733 gen_helper_slbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
4734 #endif
4735 }
4736 #endif
4737
4738 /*** External control ***/
4739 /* Optional: */
4740
4741 /* eciwx */
4742 static void gen_eciwx(DisasContext *ctx)
4743 {
4744 TCGv t0;
4745 /* Should check EAR[E] ! */
4746 gen_set_access_type(ctx, ACCESS_EXT);
4747 t0 = tcg_temp_new();
4748 gen_addr_reg_index(ctx, t0);
4749 gen_check_align(ctx, t0, 0x03);
4750 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4751 tcg_temp_free(t0);
4752 }
4753
4754 /* ecowx */
4755 static void gen_ecowx(DisasContext *ctx)
4756 {
4757 TCGv t0;
4758 /* Should check EAR[E] ! */
4759 gen_set_access_type(ctx, ACCESS_EXT);
4760 t0 = tcg_temp_new();
4761 gen_addr_reg_index(ctx, t0);
4762 gen_check_align(ctx, t0, 0x03);
4763 gen_qemu_st32(ctx, cpu_gpr[rD(ctx->opcode)], t0);
4764 tcg_temp_free(t0);
4765 }
4766
4767 /* PowerPC 601 specific instructions */
4768
4769 /* abs - abs. */
4770 static void gen_abs(DisasContext *ctx)
4771 {
4772 int l1 = gen_new_label();
4773 int l2 = gen_new_label();
4774 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l1);
4775 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4776 tcg_gen_br(l2);
4777 gen_set_label(l1);
4778 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4779 gen_set_label(l2);
4780 if (unlikely(Rc(ctx->opcode) != 0))
4781 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4782 }
4783
4784 /* abso - abso. */
4785 static void gen_abso(DisasContext *ctx)
4786 {
4787 int l1 = gen_new_label();
4788 int l2 = gen_new_label();
4789 int l3 = gen_new_label();
4790 /* Start with XER OV disabled, the most likely case */
4791 tcg_gen_movi_tl(cpu_ov, 0);
4792 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rA(ctx->opcode)], 0, l2);
4793 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_gpr[rA(ctx->opcode)], 0x80000000, l1);
4794 tcg_gen_movi_tl(cpu_ov, 1);
4795 tcg_gen_movi_tl(cpu_so, 1);
4796 tcg_gen_br(l2);
4797 gen_set_label(l1);
4798 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4799 tcg_gen_br(l3);
4800 gen_set_label(l2);
4801 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4802 gen_set_label(l3);
4803 if (unlikely(Rc(ctx->opcode) != 0))
4804 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4805 }
4806
4807 /* clcs */
4808 static void gen_clcs(DisasContext *ctx)
4809 {
4810 TCGv_i32 t0 = tcg_const_i32(rA(ctx->opcode));
4811 gen_helper_clcs(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
4812 tcg_temp_free_i32(t0);
4813 /* Rc=1 sets CR0 to an undefined state */
4814 }
4815
4816 /* div - div. */
4817 static void gen_div(DisasContext *ctx)
4818 {
4819 gen_helper_div(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4820 cpu_gpr[rB(ctx->opcode)]);
4821 if (unlikely(Rc(ctx->opcode) != 0))
4822 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4823 }
4824
4825 /* divo - divo. */
4826 static void gen_divo(DisasContext *ctx)
4827 {
4828 gen_helper_divo(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4829 cpu_gpr[rB(ctx->opcode)]);
4830 if (unlikely(Rc(ctx->opcode) != 0))
4831 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4832 }
4833
4834 /* divs - divs. */
4835 static void gen_divs(DisasContext *ctx)
4836 {
4837 gen_helper_divs(cpu_gpr[rD(ctx->opcode)], cpu_env, cpu_gpr[rA(ctx->opcode)],
4838 cpu_gpr[rB(ctx->opcode)]);
4839 if (unlikely(Rc(ctx->opcode) != 0))
4840 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4841 }
4842
4843 /* divso - divso. */
4844 static void gen_divso(DisasContext *ctx)
4845 {
4846 gen_helper_divso(cpu_gpr[rD(ctx->opcode)], cpu_env,
4847 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4848 if (unlikely(Rc(ctx->opcode) != 0))
4849 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4850 }
4851
4852 /* doz - doz. */
4853 static void gen_doz(DisasContext *ctx)
4854 {
4855 int l1 = gen_new_label();
4856 int l2 = gen_new_label();
4857 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4858 tcg_gen_sub_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4859 tcg_gen_br(l2);
4860 gen_set_label(l1);
4861 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4862 gen_set_label(l2);
4863 if (unlikely(Rc(ctx->opcode) != 0))
4864 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4865 }
4866
4867 /* dozo - dozo. */
4868 static void gen_dozo(DisasContext *ctx)
4869 {
4870 int l1 = gen_new_label();
4871 int l2 = gen_new_label();
4872 TCGv t0 = tcg_temp_new();
4873 TCGv t1 = tcg_temp_new();
4874 TCGv t2 = tcg_temp_new();
4875 /* Start with XER OV disabled, the most likely case */
4876 tcg_gen_movi_tl(cpu_ov, 0);
4877 tcg_gen_brcond_tl(TCG_COND_GE, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], l1);
4878 tcg_gen_sub_tl(t0, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4879 tcg_gen_xor_tl(t1, cpu_gpr[rB(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4880 tcg_gen_xor_tl(t2, cpu_gpr[rA(ctx->opcode)], t0);
4881 tcg_gen_andc_tl(t1, t1, t2);
4882 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
4883 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
4884 tcg_gen_movi_tl(cpu_ov, 1);
4885 tcg_gen_movi_tl(cpu_so, 1);
4886 tcg_gen_br(l2);
4887 gen_set_label(l1);
4888 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4889 gen_set_label(l2);
4890 tcg_temp_free(t0);
4891 tcg_temp_free(t1);
4892 tcg_temp_free(t2);
4893 if (unlikely(Rc(ctx->opcode) != 0))
4894 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4895 }
4896
4897 /* dozi */
4898 static void gen_dozi(DisasContext *ctx)
4899 {
4900 target_long simm = SIMM(ctx->opcode);
4901 int l1 = gen_new_label();
4902 int l2 = gen_new_label();
4903 tcg_gen_brcondi_tl(TCG_COND_LT, cpu_gpr[rA(ctx->opcode)], simm, l1);
4904 tcg_gen_subfi_tl(cpu_gpr[rD(ctx->opcode)], simm, cpu_gpr[rA(ctx->opcode)]);
4905 tcg_gen_br(l2);
4906 gen_set_label(l1);
4907 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], 0);
4908 gen_set_label(l2);
4909 if (unlikely(Rc(ctx->opcode) != 0))
4910 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4911 }
4912
4913 /* lscbx - lscbx. */
4914 static void gen_lscbx(DisasContext *ctx)
4915 {
4916 TCGv t0 = tcg_temp_new();
4917 TCGv_i32 t1 = tcg_const_i32(rD(ctx->opcode));
4918 TCGv_i32 t2 = tcg_const_i32(rA(ctx->opcode));
4919 TCGv_i32 t3 = tcg_const_i32(rB(ctx->opcode));
4920
4921 gen_addr_reg_index(ctx, t0);
4922 /* NIP cannot be restored if the memory exception comes from an helper */
4923 gen_update_nip(ctx, ctx->nip - 4);
4924 gen_helper_lscbx(t0, cpu_env, t0, t1, t2, t3);
4925 tcg_temp_free_i32(t1);
4926 tcg_temp_free_i32(t2);
4927 tcg_temp_free_i32(t3);
4928 tcg_gen_andi_tl(cpu_xer, cpu_xer, ~0x7F);
4929 tcg_gen_or_tl(cpu_xer, cpu_xer, t0);
4930 if (unlikely(Rc(ctx->opcode) != 0))
4931 gen_set_Rc0(ctx, t0);
4932 tcg_temp_free(t0);
4933 }
4934
4935 /* maskg - maskg. */
4936 static void gen_maskg(DisasContext *ctx)
4937 {
4938 int l1 = gen_new_label();
4939 TCGv t0 = tcg_temp_new();
4940 TCGv t1 = tcg_temp_new();
4941 TCGv t2 = tcg_temp_new();
4942 TCGv t3 = tcg_temp_new();
4943 tcg_gen_movi_tl(t3, 0xFFFFFFFF);
4944 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
4945 tcg_gen_andi_tl(t1, cpu_gpr[rS(ctx->opcode)], 0x1F);
4946 tcg_gen_addi_tl(t2, t0, 1);
4947 tcg_gen_shr_tl(t2, t3, t2);
4948 tcg_gen_shr_tl(t3, t3, t1);
4949 tcg_gen_xor_tl(cpu_gpr[rA(ctx->opcode)], t2, t3);
4950 tcg_gen_brcond_tl(TCG_COND_GE, t0, t1, l1);
4951 tcg_gen_neg_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
4952 gen_set_label(l1);
4953 tcg_temp_free(t0);
4954 tcg_temp_free(t1);
4955 tcg_temp_free(t2);
4956 tcg_temp_free(t3);
4957 if (unlikely(Rc(ctx->opcode) != 0))
4958 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4959 }
4960
4961 /* maskir - maskir. */
4962 static void gen_maskir(DisasContext *ctx)
4963 {
4964 TCGv t0 = tcg_temp_new();
4965 TCGv t1 = tcg_temp_new();
4966 tcg_gen_and_tl(t0, cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4967 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
4968 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
4969 tcg_temp_free(t0);
4970 tcg_temp_free(t1);
4971 if (unlikely(Rc(ctx->opcode) != 0))
4972 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
4973 }
4974
4975 /* mul - mul. */
4976 static void gen_mul(DisasContext *ctx)
4977 {
4978 TCGv_i64 t0 = tcg_temp_new_i64();
4979 TCGv_i64 t1 = tcg_temp_new_i64();
4980 TCGv t2 = tcg_temp_new();
4981 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
4982 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
4983 tcg_gen_mul_i64(t0, t0, t1);
4984 tcg_gen_trunc_i64_tl(t2, t0);
4985 gen_store_spr(SPR_MQ, t2);
4986 tcg_gen_shri_i64(t1, t0, 32);
4987 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
4988 tcg_temp_free_i64(t0);
4989 tcg_temp_free_i64(t1);
4990 tcg_temp_free(t2);
4991 if (unlikely(Rc(ctx->opcode) != 0))
4992 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
4993 }
4994
4995 /* mulo - mulo. */
4996 static void gen_mulo(DisasContext *ctx)
4997 {
4998 int l1 = gen_new_label();
4999 TCGv_i64 t0 = tcg_temp_new_i64();
5000 TCGv_i64 t1 = tcg_temp_new_i64();
5001 TCGv t2 = tcg_temp_new();
5002 /* Start with XER OV disabled, the most likely case */
5003 tcg_gen_movi_tl(cpu_ov, 0);
5004 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
5005 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
5006 tcg_gen_mul_i64(t0, t0, t1);
5007 tcg_gen_trunc_i64_tl(t2, t0);
5008 gen_store_spr(SPR_MQ, t2);
5009 tcg_gen_shri_i64(t1, t0, 32);
5010 tcg_gen_trunc_i64_tl(cpu_gpr[rD(ctx->opcode)], t1);
5011 tcg_gen_ext32s_i64(t1, t0);
5012 tcg_gen_brcond_i64(TCG_COND_EQ, t0, t1, l1);
5013 tcg_gen_movi_tl(cpu_ov, 1);
5014 tcg_gen_movi_tl(cpu_so, 1);
5015 gen_set_label(l1);
5016 tcg_temp_free_i64(t0);
5017 tcg_temp_free_i64(t1);
5018 tcg_temp_free(t2);
5019 if (unlikely(Rc(ctx->opcode) != 0))
5020 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5021 }
5022
5023 /* nabs - nabs. */
5024 static void gen_nabs(DisasContext *ctx)
5025 {
5026 int l1 = gen_new_label();
5027 int l2 = gen_new_label();
5028 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5029 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5030 tcg_gen_br(l2);
5031 gen_set_label(l1);
5032 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5033 gen_set_label(l2);
5034 if (unlikely(Rc(ctx->opcode) != 0))
5035 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5036 }
5037
5038 /* nabso - nabso. */
5039 static void gen_nabso(DisasContext *ctx)
5040 {
5041 int l1 = gen_new_label();
5042 int l2 = gen_new_label();
5043 tcg_gen_brcondi_tl(TCG_COND_GT, cpu_gpr[rA(ctx->opcode)], 0, l1);
5044 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5045 tcg_gen_br(l2);
5046 gen_set_label(l1);
5047 tcg_gen_neg_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5048 gen_set_label(l2);
5049 /* nabs never overflows */
5050 tcg_gen_movi_tl(cpu_ov, 0);
5051 if (unlikely(Rc(ctx->opcode) != 0))
5052 gen_set_Rc0(ctx, cpu_gpr[rD(ctx->opcode)]);
5053 }
5054
5055 /* rlmi - rlmi. */
5056 static void gen_rlmi(DisasContext *ctx)
5057 {
5058 uint32_t mb = MB(ctx->opcode);
5059 uint32_t me = ME(ctx->opcode);
5060 TCGv t0 = tcg_temp_new();
5061 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5062 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5063 tcg_gen_andi_tl(t0, t0, MASK(mb, me));
5064 tcg_gen_andi_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~MASK(mb, me));
5065 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], t0);
5066 tcg_temp_free(t0);
5067 if (unlikely(Rc(ctx->opcode) != 0))
5068 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5069 }
5070
5071 /* rrib - rrib. */
5072 static void gen_rrib(DisasContext *ctx)
5073 {
5074 TCGv t0 = tcg_temp_new();
5075 TCGv t1 = tcg_temp_new();
5076 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5077 tcg_gen_movi_tl(t1, 0x80000000);
5078 tcg_gen_shr_tl(t1, t1, t0);
5079 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5080 tcg_gen_and_tl(t0, t0, t1);
5081 tcg_gen_andc_tl(t1, cpu_gpr[rA(ctx->opcode)], t1);
5082 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5083 tcg_temp_free(t0);
5084 tcg_temp_free(t1);
5085 if (unlikely(Rc(ctx->opcode) != 0))
5086 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5087 }
5088
5089 /* sle - sle. */
5090 static void gen_sle(DisasContext *ctx)
5091 {
5092 TCGv t0 = tcg_temp_new();
5093 TCGv t1 = tcg_temp_new();
5094 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5095 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5096 tcg_gen_subfi_tl(t1, 32, t1);
5097 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5098 tcg_gen_or_tl(t1, t0, t1);
5099 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5100 gen_store_spr(SPR_MQ, t1);
5101 tcg_temp_free(t0);
5102 tcg_temp_free(t1);
5103 if (unlikely(Rc(ctx->opcode) != 0))
5104 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5105 }
5106
5107 /* sleq - sleq. */
5108 static void gen_sleq(DisasContext *ctx)
5109 {
5110 TCGv t0 = tcg_temp_new();
5111 TCGv t1 = tcg_temp_new();
5112 TCGv t2 = tcg_temp_new();
5113 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5114 tcg_gen_movi_tl(t2, 0xFFFFFFFF);
5115 tcg_gen_shl_tl(t2, t2, t0);
5116 tcg_gen_rotl_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5117 gen_load_spr(t1, SPR_MQ);
5118 gen_store_spr(SPR_MQ, t0);
5119 tcg_gen_and_tl(t0, t0, t2);
5120 tcg_gen_andc_tl(t1, t1, t2);
5121 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5122 tcg_temp_free(t0);
5123 tcg_temp_free(t1);
5124 tcg_temp_free(t2);
5125 if (unlikely(Rc(ctx->opcode) != 0))
5126 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5127 }
5128
5129 /* sliq - sliq. */
5130 static void gen_sliq(DisasContext *ctx)
5131 {
5132 int sh = SH(ctx->opcode);
5133 TCGv t0 = tcg_temp_new();
5134 TCGv t1 = tcg_temp_new();
5135 tcg_gen_shli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5136 tcg_gen_shri_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5137 tcg_gen_or_tl(t1, t0, t1);
5138 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5139 gen_store_spr(SPR_MQ, t1);
5140 tcg_temp_free(t0);
5141 tcg_temp_free(t1);
5142 if (unlikely(Rc(ctx->opcode) != 0))
5143 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5144 }
5145
5146 /* slliq - slliq. */
5147 static void gen_slliq(DisasContext *ctx)
5148 {
5149 int sh = SH(ctx->opcode);
5150 TCGv t0 = tcg_temp_new();
5151 TCGv t1 = tcg_temp_new();
5152 tcg_gen_rotli_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5153 gen_load_spr(t1, SPR_MQ);
5154 gen_store_spr(SPR_MQ, t0);
5155 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU << sh));
5156 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU << sh));
5157 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5158 tcg_temp_free(t0);
5159 tcg_temp_free(t1);
5160 if (unlikely(Rc(ctx->opcode) != 0))
5161 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5162 }
5163
5164 /* sllq - sllq. */
5165 static void gen_sllq(DisasContext *ctx)
5166 {
5167 int l1 = gen_new_label();
5168 int l2 = gen_new_label();
5169 TCGv t0 = tcg_temp_local_new();
5170 TCGv t1 = tcg_temp_local_new();
5171 TCGv t2 = tcg_temp_local_new();
5172 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5173 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5174 tcg_gen_shl_tl(t1, t1, t2);
5175 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5176 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5177 gen_load_spr(t0, SPR_MQ);
5178 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5179 tcg_gen_br(l2);
5180 gen_set_label(l1);
5181 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5182 gen_load_spr(t2, SPR_MQ);
5183 tcg_gen_andc_tl(t1, t2, t1);
5184 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5185 gen_set_label(l2);
5186 tcg_temp_free(t0);
5187 tcg_temp_free(t1);
5188 tcg_temp_free(t2);
5189 if (unlikely(Rc(ctx->opcode) != 0))
5190 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5191 }
5192
5193 /* slq - slq. */
5194 static void gen_slq(DisasContext *ctx)
5195 {
5196 int l1 = gen_new_label();
5197 TCGv t0 = tcg_temp_new();
5198 TCGv t1 = tcg_temp_new();
5199 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5200 tcg_gen_shl_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5201 tcg_gen_subfi_tl(t1, 32, t1);
5202 tcg_gen_shr_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5203 tcg_gen_or_tl(t1, t0, t1);
5204 gen_store_spr(SPR_MQ, t1);
5205 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5206 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5207 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5208 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5209 gen_set_label(l1);
5210 tcg_temp_free(t0);
5211 tcg_temp_free(t1);
5212 if (unlikely(Rc(ctx->opcode) != 0))
5213 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5214 }
5215
5216 /* sraiq - sraiq. */
5217 static void gen_sraiq(DisasContext *ctx)
5218 {
5219 int sh = SH(ctx->opcode);
5220 int l1 = gen_new_label();
5221 TCGv t0 = tcg_temp_new();
5222 TCGv t1 = tcg_temp_new();
5223 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5224 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5225 tcg_gen_or_tl(t0, t0, t1);
5226 gen_store_spr(SPR_MQ, t0);
5227 tcg_gen_movi_tl(cpu_ca, 0);
5228 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, l1);
5229 tcg_gen_brcondi_tl(TCG_COND_GE, cpu_gpr[rS(ctx->opcode)], 0, l1);
5230 tcg_gen_movi_tl(cpu_ca, 1);
5231 gen_set_label(l1);
5232 tcg_gen_sari_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], sh);
5233 tcg_temp_free(t0);
5234 tcg_temp_free(t1);
5235 if (unlikely(Rc(ctx->opcode) != 0))
5236 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5237 }
5238
5239 /* sraq - sraq. */
5240 static void gen_sraq(DisasContext *ctx)
5241 {
5242 int l1 = gen_new_label();
5243 int l2 = gen_new_label();
5244 TCGv t0 = tcg_temp_new();
5245 TCGv t1 = tcg_temp_local_new();
5246 TCGv t2 = tcg_temp_local_new();
5247 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5248 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5249 tcg_gen_sar_tl(t1, cpu_gpr[rS(ctx->opcode)], t2);
5250 tcg_gen_subfi_tl(t2, 32, t2);
5251 tcg_gen_shl_tl(t2, cpu_gpr[rS(ctx->opcode)], t2);
5252 tcg_gen_or_tl(t0, t0, t2);
5253 gen_store_spr(SPR_MQ, t0);
5254 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5255 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l1);
5256 tcg_gen_mov_tl(t2, cpu_gpr[rS(ctx->opcode)]);
5257 tcg_gen_sari_tl(t1, cpu_gpr[rS(ctx->opcode)], 31);
5258 gen_set_label(l1);
5259 tcg_temp_free(t0);
5260 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t1);
5261 tcg_gen_movi_tl(cpu_ca, 0);
5262 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l2);
5263 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, l2);
5264 tcg_gen_movi_tl(cpu_ca, 1);
5265 gen_set_label(l2);
5266 tcg_temp_free(t1);
5267 tcg_temp_free(t2);
5268 if (unlikely(Rc(ctx->opcode) != 0))
5269 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5270 }
5271
5272 /* sre - sre. */
5273 static void gen_sre(DisasContext *ctx)
5274 {
5275 TCGv t0 = tcg_temp_new();
5276 TCGv t1 = tcg_temp_new();
5277 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5278 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5279 tcg_gen_subfi_tl(t1, 32, t1);
5280 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5281 tcg_gen_or_tl(t1, t0, t1);
5282 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5283 gen_store_spr(SPR_MQ, t1);
5284 tcg_temp_free(t0);
5285 tcg_temp_free(t1);
5286 if (unlikely(Rc(ctx->opcode) != 0))
5287 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5288 }
5289
5290 /* srea - srea. */
5291 static void gen_srea(DisasContext *ctx)
5292 {
5293 TCGv t0 = tcg_temp_new();
5294 TCGv t1 = tcg_temp_new();
5295 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5296 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5297 gen_store_spr(SPR_MQ, t0);
5298 tcg_gen_sar_tl(cpu_gpr[rA(ctx->opcode)], cpu_gpr[rS(ctx->opcode)], t1);
5299 tcg_temp_free(t0);
5300 tcg_temp_free(t1);
5301 if (unlikely(Rc(ctx->opcode) != 0))
5302 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5303 }
5304
5305 /* sreq */
5306 static void gen_sreq(DisasContext *ctx)
5307 {
5308 TCGv t0 = tcg_temp_new();
5309 TCGv t1 = tcg_temp_new();
5310 TCGv t2 = tcg_temp_new();
5311 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x1F);
5312 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5313 tcg_gen_shr_tl(t1, t1, t0);
5314 tcg_gen_rotr_tl(t0, cpu_gpr[rS(ctx->opcode)], t0);
5315 gen_load_spr(t2, SPR_MQ);
5316 gen_store_spr(SPR_MQ, t0);
5317 tcg_gen_and_tl(t0, t0, t1);
5318 tcg_gen_andc_tl(t2, t2, t1);
5319 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5320 tcg_temp_free(t0);
5321 tcg_temp_free(t1);
5322 tcg_temp_free(t2);
5323 if (unlikely(Rc(ctx->opcode) != 0))
5324 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5325 }
5326
5327 /* sriq */
5328 static void gen_sriq(DisasContext *ctx)
5329 {
5330 int sh = SH(ctx->opcode);
5331 TCGv t0 = tcg_temp_new();
5332 TCGv t1 = tcg_temp_new();
5333 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5334 tcg_gen_shli_tl(t1, cpu_gpr[rS(ctx->opcode)], 32 - sh);
5335 tcg_gen_or_tl(t1, t0, t1);
5336 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5337 gen_store_spr(SPR_MQ, t1);
5338 tcg_temp_free(t0);
5339 tcg_temp_free(t1);
5340 if (unlikely(Rc(ctx->opcode) != 0))
5341 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5342 }
5343
5344 /* srliq */
5345 static void gen_srliq(DisasContext *ctx)
5346 {
5347 int sh = SH(ctx->opcode);
5348 TCGv t0 = tcg_temp_new();
5349 TCGv t1 = tcg_temp_new();
5350 tcg_gen_rotri_tl(t0, cpu_gpr[rS(ctx->opcode)], sh);
5351 gen_load_spr(t1, SPR_MQ);
5352 gen_store_spr(SPR_MQ, t0);
5353 tcg_gen_andi_tl(t0, t0, (0xFFFFFFFFU >> sh));
5354 tcg_gen_andi_tl(t1, t1, ~(0xFFFFFFFFU >> sh));
5355 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5356 tcg_temp_free(t0);
5357 tcg_temp_free(t1);
5358 if (unlikely(Rc(ctx->opcode) != 0))
5359 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5360 }
5361
5362 /* srlq */
5363 static void gen_srlq(DisasContext *ctx)
5364 {
5365 int l1 = gen_new_label();
5366 int l2 = gen_new_label();
5367 TCGv t0 = tcg_temp_local_new();
5368 TCGv t1 = tcg_temp_local_new();
5369 TCGv t2 = tcg_temp_local_new();
5370 tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x1F);
5371 tcg_gen_movi_tl(t1, 0xFFFFFFFF);
5372 tcg_gen_shr_tl(t2, t1, t2);
5373 tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x20);
5374 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5375 gen_load_spr(t0, SPR_MQ);
5376 tcg_gen_and_tl(cpu_gpr[rA(ctx->opcode)], t0, t2);
5377 tcg_gen_br(l2);
5378 gen_set_label(l1);
5379 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t2);
5380 tcg_gen_and_tl(t0, t0, t2);
5381 gen_load_spr(t1, SPR_MQ);
5382 tcg_gen_andc_tl(t1, t1, t2);
5383 tcg_gen_or_tl(cpu_gpr[rA(ctx->opcode)], t0, t1);
5384 gen_set_label(l2);
5385 tcg_temp_free(t0);
5386 tcg_temp_free(t1);
5387 tcg_temp_free(t2);
5388 if (unlikely(Rc(ctx->opcode) != 0))
5389 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5390 }
5391
5392 /* srq */
5393 static void gen_srq(DisasContext *ctx)
5394 {
5395 int l1 = gen_new_label();
5396 TCGv t0 = tcg_temp_new();
5397 TCGv t1 = tcg_temp_new();
5398 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x1F);
5399 tcg_gen_shr_tl(t0, cpu_gpr[rS(ctx->opcode)], t1);
5400 tcg_gen_subfi_tl(t1, 32, t1);
5401 tcg_gen_shl_tl(t1, cpu_gpr[rS(ctx->opcode)], t1);
5402 tcg_gen_or_tl(t1, t0, t1);
5403 gen_store_spr(SPR_MQ, t1);
5404 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0x20);
5405 tcg_gen_mov_tl(cpu_gpr[rA(ctx->opcode)], t0);
5406 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, l1);
5407 tcg_gen_movi_tl(cpu_gpr[rA(ctx->opcode)], 0);
5408 gen_set_label(l1);
5409 tcg_temp_free(t0);
5410 tcg_temp_free(t1);
5411 if (unlikely(Rc(ctx->opcode) != 0))
5412 gen_set_Rc0(ctx, cpu_gpr[rA(ctx->opcode)]);
5413 }
5414
5415 /* PowerPC 602 specific instructions */
5416
5417 /* dsa */
5418 static void gen_dsa(DisasContext *ctx)
5419 {
5420 /* XXX: TODO */
5421 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5422 }
5423
5424 /* esa */
5425 static void gen_esa(DisasContext *ctx)
5426 {
5427 /* XXX: TODO */
5428 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5429 }
5430
5431 /* mfrom */
5432 static void gen_mfrom(DisasContext *ctx)
5433 {
5434 #if defined(CONFIG_USER_ONLY)
5435 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5436 #else
5437 if (unlikely(!ctx->mem_idx)) {
5438 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5439 return;
5440 }
5441 gen_helper_602_mfrom(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
5442 #endif
5443 }
5444
5445 /* 602 - 603 - G2 TLB management */
5446
5447 /* tlbld */
5448 static void gen_tlbld_6xx(DisasContext *ctx)
5449 {
5450 #if defined(CONFIG_USER_ONLY)
5451 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5452 #else
5453 if (unlikely(!ctx->mem_idx)) {
5454 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5455 return;
5456 }
5457 gen_helper_6xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5458 #endif
5459 }
5460
5461 /* tlbli */
5462 static void gen_tlbli_6xx(DisasContext *ctx)
5463 {
5464 #if defined(CONFIG_USER_ONLY)
5465 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5466 #else
5467 if (unlikely(!ctx->mem_idx)) {
5468 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5469 return;
5470 }
5471 gen_helper_6xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5472 #endif
5473 }
5474
5475 /* 74xx TLB management */
5476
5477 /* tlbld */
5478 static void gen_tlbld_74xx(DisasContext *ctx)
5479 {
5480 #if defined(CONFIG_USER_ONLY)
5481 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5482 #else
5483 if (unlikely(!ctx->mem_idx)) {
5484 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5485 return;
5486 }
5487 gen_helper_74xx_tlbd(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5488 #endif
5489 }
5490
5491 /* tlbli */
5492 static void gen_tlbli_74xx(DisasContext *ctx)
5493 {
5494 #if defined(CONFIG_USER_ONLY)
5495 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5496 #else
5497 if (unlikely(!ctx->mem_idx)) {
5498 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5499 return;
5500 }
5501 gen_helper_74xx_tlbi(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5502 #endif
5503 }
5504
5505 /* POWER instructions not in PowerPC 601 */
5506
5507 /* clf */
5508 static void gen_clf(DisasContext *ctx)
5509 {
5510 /* Cache line flush: implemented as no-op */
5511 }
5512
5513 /* cli */
5514 static void gen_cli(DisasContext *ctx)
5515 {
5516 /* Cache line invalidate: privileged and treated as no-op */
5517 #if defined(CONFIG_USER_ONLY)
5518 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5519 #else
5520 if (unlikely(!ctx->mem_idx)) {
5521 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5522 return;
5523 }
5524 #endif
5525 }
5526
5527 /* dclst */
5528 static void gen_dclst(DisasContext *ctx)
5529 {
5530 /* Data cache line store: treated as no-op */
5531 }
5532
5533 static void gen_mfsri(DisasContext *ctx)
5534 {
5535 #if defined(CONFIG_USER_ONLY)
5536 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5537 #else
5538 int ra = rA(ctx->opcode);
5539 int rd = rD(ctx->opcode);
5540 TCGv t0;
5541 if (unlikely(!ctx->mem_idx)) {
5542 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5543 return;
5544 }
5545 t0 = tcg_temp_new();
5546 gen_addr_reg_index(ctx, t0);
5547 tcg_gen_shri_tl(t0, t0, 28);
5548 tcg_gen_andi_tl(t0, t0, 0xF);
5549 gen_helper_load_sr(cpu_gpr[rd], cpu_env, t0);
5550 tcg_temp_free(t0);
5551 if (ra != 0 && ra != rd)
5552 tcg_gen_mov_tl(cpu_gpr[ra], cpu_gpr[rd]);
5553 #endif
5554 }
5555
5556 static void gen_rac(DisasContext *ctx)
5557 {
5558 #if defined(CONFIG_USER_ONLY)
5559 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5560 #else
5561 TCGv t0;
5562 if (unlikely(!ctx->mem_idx)) {
5563 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5564 return;
5565 }
5566 t0 = tcg_temp_new();
5567 gen_addr_reg_index(ctx, t0);
5568 gen_helper_rac(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
5569 tcg_temp_free(t0);
5570 #endif
5571 }
5572
5573 static void gen_rfsvc(DisasContext *ctx)
5574 {
5575 #if defined(CONFIG_USER_ONLY)
5576 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5577 #else
5578 if (unlikely(!ctx->mem_idx)) {
5579 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5580 return;
5581 }
5582 gen_helper_rfsvc(cpu_env);
5583 gen_sync_exception(ctx);
5584 #endif
5585 }
5586
5587 /* svc is not implemented for now */
5588
5589 /* POWER2 specific instructions */
5590 /* Quad manipulation (load/store two floats at a time) */
5591
5592 /* lfq */
5593 static void gen_lfq(DisasContext *ctx)
5594 {
5595 int rd = rD(ctx->opcode);
5596 TCGv t0;
5597 gen_set_access_type(ctx, ACCESS_FLOAT);
5598 t0 = tcg_temp_new();
5599 gen_addr_imm_index(ctx, t0, 0);
5600 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5601 gen_addr_add(ctx, t0, t0, 8);
5602 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5603 tcg_temp_free(t0);
5604 }
5605
5606 /* lfqu */
5607 static void gen_lfqu(DisasContext *ctx)
5608 {
5609 int ra = rA(ctx->opcode);
5610 int rd = rD(ctx->opcode);
5611 TCGv t0, t1;
5612 gen_set_access_type(ctx, ACCESS_FLOAT);
5613 t0 = tcg_temp_new();
5614 t1 = tcg_temp_new();
5615 gen_addr_imm_index(ctx, t0, 0);
5616 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5617 gen_addr_add(ctx, t1, t0, 8);
5618 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5619 if (ra != 0)
5620 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5621 tcg_temp_free(t0);
5622 tcg_temp_free(t1);
5623 }
5624
5625 /* lfqux */
5626 static void gen_lfqux(DisasContext *ctx)
5627 {
5628 int ra = rA(ctx->opcode);
5629 int rd = rD(ctx->opcode);
5630 gen_set_access_type(ctx, ACCESS_FLOAT);
5631 TCGv t0, t1;
5632 t0 = tcg_temp_new();
5633 gen_addr_reg_index(ctx, t0);
5634 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5635 t1 = tcg_temp_new();
5636 gen_addr_add(ctx, t1, t0, 8);
5637 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5638 tcg_temp_free(t1);
5639 if (ra != 0)
5640 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5641 tcg_temp_free(t0);
5642 }
5643
5644 /* lfqx */
5645 static void gen_lfqx(DisasContext *ctx)
5646 {
5647 int rd = rD(ctx->opcode);
5648 TCGv t0;
5649 gen_set_access_type(ctx, ACCESS_FLOAT);
5650 t0 = tcg_temp_new();
5651 gen_addr_reg_index(ctx, t0);
5652 gen_qemu_ld64(ctx, cpu_fpr[rd], t0);
5653 gen_addr_add(ctx, t0, t0, 8);
5654 gen_qemu_ld64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5655 tcg_temp_free(t0);
5656 }
5657
5658 /* stfq */
5659 static void gen_stfq(DisasContext *ctx)
5660 {
5661 int rd = rD(ctx->opcode);
5662 TCGv t0;
5663 gen_set_access_type(ctx, ACCESS_FLOAT);
5664 t0 = tcg_temp_new();
5665 gen_addr_imm_index(ctx, t0, 0);
5666 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5667 gen_addr_add(ctx, t0, t0, 8);
5668 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5669 tcg_temp_free(t0);
5670 }
5671
5672 /* stfqu */
5673 static void gen_stfqu(DisasContext *ctx)
5674 {
5675 int ra = rA(ctx->opcode);
5676 int rd = rD(ctx->opcode);
5677 TCGv t0, t1;
5678 gen_set_access_type(ctx, ACCESS_FLOAT);
5679 t0 = tcg_temp_new();
5680 gen_addr_imm_index(ctx, t0, 0);
5681 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5682 t1 = tcg_temp_new();
5683 gen_addr_add(ctx, t1, t0, 8);
5684 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5685 tcg_temp_free(t1);
5686 if (ra != 0)
5687 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5688 tcg_temp_free(t0);
5689 }
5690
5691 /* stfqux */
5692 static void gen_stfqux(DisasContext *ctx)
5693 {
5694 int ra = rA(ctx->opcode);
5695 int rd = rD(ctx->opcode);
5696 TCGv t0, t1;
5697 gen_set_access_type(ctx, ACCESS_FLOAT);
5698 t0 = tcg_temp_new();
5699 gen_addr_reg_index(ctx, t0);
5700 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5701 t1 = tcg_temp_new();
5702 gen_addr_add(ctx, t1, t0, 8);
5703 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t1);
5704 tcg_temp_free(t1);
5705 if (ra != 0)
5706 tcg_gen_mov_tl(cpu_gpr[ra], t0);
5707 tcg_temp_free(t0);
5708 }
5709
5710 /* stfqx */
5711 static void gen_stfqx(DisasContext *ctx)
5712 {
5713 int rd = rD(ctx->opcode);
5714 TCGv t0;
5715 gen_set_access_type(ctx, ACCESS_FLOAT);
5716 t0 = tcg_temp_new();
5717 gen_addr_reg_index(ctx, t0);
5718 gen_qemu_st64(ctx, cpu_fpr[rd], t0);
5719 gen_addr_add(ctx, t0, t0, 8);
5720 gen_qemu_st64(ctx, cpu_fpr[(rd + 1) % 32], t0);
5721 tcg_temp_free(t0);
5722 }
5723
5724 /* BookE specific instructions */
5725
5726 /* XXX: not implemented on 440 ? */
5727 static void gen_mfapidi(DisasContext *ctx)
5728 {
5729 /* XXX: TODO */
5730 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
5731 }
5732
5733 /* XXX: not implemented on 440 ? */
5734 static void gen_tlbiva(DisasContext *ctx)
5735 {
5736 #if defined(CONFIG_USER_ONLY)
5737 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5738 #else
5739 TCGv t0;
5740 if (unlikely(!ctx->mem_idx)) {
5741 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
5742 return;
5743 }
5744 t0 = tcg_temp_new();
5745 gen_addr_reg_index(ctx, t0);
5746 gen_helper_tlbie(cpu_env, cpu_gpr[rB(ctx->opcode)]);
5747 tcg_temp_free(t0);
5748 #endif
5749 }
5750
5751 /* All 405 MAC instructions are translated here */
5752 static inline void gen_405_mulladd_insn(DisasContext *ctx, int opc2, int opc3,
5753 int ra, int rb, int rt, int Rc)
5754 {
5755 TCGv t0, t1;
5756
5757 t0 = tcg_temp_local_new();
5758 t1 = tcg_temp_local_new();
5759
5760 switch (opc3 & 0x0D) {
5761 case 0x05:
5762 /* macchw - macchw. - macchwo - macchwo. */
5763 /* macchws - macchws. - macchwso - macchwso. */
5764 /* nmacchw - nmacchw. - nmacchwo - nmacchwo. */
5765 /* nmacchws - nmacchws. - nmacchwso - nmacchwso. */
5766 /* mulchw - mulchw. */
5767 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5768 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5769 tcg_gen_ext16s_tl(t1, t1);
5770 break;
5771 case 0x04:
5772 /* macchwu - macchwu. - macchwuo - macchwuo. */
5773 /* macchwsu - macchwsu. - macchwsuo - macchwsuo. */
5774 /* mulchwu - mulchwu. */
5775 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5776 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5777 tcg_gen_ext16u_tl(t1, t1);
5778 break;
5779 case 0x01:
5780 /* machhw - machhw. - machhwo - machhwo. */
5781 /* machhws - machhws. - machhwso - machhwso. */
5782 /* nmachhw - nmachhw. - nmachhwo - nmachhwo. */
5783 /* nmachhws - nmachhws. - nmachhwso - nmachhwso. */
5784 /* mulhhw - mulhhw. */
5785 tcg_gen_sari_tl(t0, cpu_gpr[ra], 16);
5786 tcg_gen_ext16s_tl(t0, t0);
5787 tcg_gen_sari_tl(t1, cpu_gpr[rb], 16);
5788 tcg_gen_ext16s_tl(t1, t1);
5789 break;
5790 case 0x00:
5791 /* machhwu - machhwu. - machhwuo - machhwuo. */
5792 /* machhwsu - machhwsu. - machhwsuo - machhwsuo. */
5793 /* mulhhwu - mulhhwu. */
5794 tcg_gen_shri_tl(t0, cpu_gpr[ra], 16);
5795 tcg_gen_ext16u_tl(t0, t0);
5796 tcg_gen_shri_tl(t1, cpu_gpr[rb], 16);
5797 tcg_gen_ext16u_tl(t1, t1);
5798 break;
5799 case 0x0D:
5800 /* maclhw - maclhw. - maclhwo - maclhwo. */
5801 /* maclhws - maclhws. - maclhwso - maclhwso. */
5802 /* nmaclhw - nmaclhw. - nmaclhwo - nmaclhwo. */
5803 /* nmaclhws - nmaclhws. - nmaclhwso - nmaclhwso. */
5804 /* mullhw - mullhw. */
5805 tcg_gen_ext16s_tl(t0, cpu_gpr[ra]);
5806 tcg_gen_ext16s_tl(t1, cpu_gpr[rb]);
5807 break;
5808 case 0x0C:
5809 /* maclhwu - maclhwu. - maclhwuo - maclhwuo. */
5810 /* maclhwsu - maclhwsu. - maclhwsuo - maclhwsuo. */
5811 /* mullhwu - mullhwu. */
5812 tcg_gen_ext16u_tl(t0, cpu_gpr[ra]);
5813 tcg_gen_ext16u_tl(t1, cpu_gpr[rb]);
5814 break;
5815 }
5816 if (opc2 & 0x04) {
5817 /* (n)multiply-and-accumulate (0x0C / 0x0E) */
5818 tcg_gen_mul_tl(t1, t0, t1);
5819 if (opc2 & 0x02) {
5820 /* nmultiply-and-accumulate (0x0E) */
5821 tcg_gen_sub_tl(t0, cpu_gpr[rt], t1);
5822 } else {
5823 /* multiply-and-accumulate (0x0C) */
5824 tcg_gen_add_tl(t0, cpu_gpr[rt], t1);
5825 }
5826
5827 if (opc3 & 0x12) {
5828 /* Check overflow and/or saturate */
5829 int l1 = gen_new_label();
5830
5831 if (opc3 & 0x10) {
5832 /* Start with XER OV disabled, the most likely case */
5833 tcg_gen_movi_tl(cpu_ov, 0);
5834 }
5835 if (opc3 & 0x01) {
5836 /* Signed */
5837 tcg_gen_xor_tl(t1, cpu_gpr[rt], t1);
5838 tcg_gen_brcondi_tl(TCG_COND_GE, t1, 0, l1);
5839 tcg_gen_xor_tl(t1, cpu_gpr[rt], t0);
5840 tcg_gen_brcondi_tl(TCG_COND_LT, t1, 0, l1);
5841 if (opc3 & 0x02) {
5842 /* Saturate */
5843 tcg_gen_sari_tl(t0, cpu_gpr[rt], 31);
5844 tcg_gen_xori_tl(t0, t0, 0x7fffffff);
5845 }
5846 } else {
5847 /* Unsigned */
5848 tcg_gen_brcond_tl(TCG_COND_GEU, t0, t1, l1);
5849 if (opc3 & 0x02) {
5850 /* Saturate */
5851 tcg_gen_movi_tl(t0, UINT32_MAX);
5852 }
5853 }
5854 if (opc3 & 0x10) {
5855 /* Check overflow */
5856 tcg_gen_movi_tl(cpu_ov, 1);
5857 tcg_gen_movi_tl(cpu_so, 1);
5858 }
5859 gen_set_label(l1);
5860 tcg_gen_mov_tl(cpu_gpr[rt], t0);
5861 }
5862 } else {
5863 tcg_gen_mul_tl(cpu_gpr[rt], t0, t1);
5864 }
5865 tcg_temp_free(t0);
5866 tcg_temp_free(t1);
5867 if (unlikely(Rc) != 0) {
5868 /* Update Rc0 */
5869 gen_set_Rc0(ctx, cpu_gpr[rt]);
5870 }
5871 }
5872
5873 #define GEN_MAC_HANDLER(name, opc2, opc3) \
5874 static void glue(gen_, name)(DisasContext *ctx) \
5875 { \
5876 gen_405_mulladd_insn(ctx, opc2, opc3, rA(ctx->opcode), rB(ctx->opcode), \
5877 rD(ctx->opcode), Rc(ctx->opcode)); \
5878 }
5879
5880 /* macchw - macchw. */
5881 GEN_MAC_HANDLER(macchw, 0x0C, 0x05);
5882 /* macchwo - macchwo. */
5883 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15);
5884 /* macchws - macchws. */
5885 GEN_MAC_HANDLER(macchws, 0x0C, 0x07);
5886 /* macchwso - macchwso. */
5887 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17);
5888 /* macchwsu - macchwsu. */
5889 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06);
5890 /* macchwsuo - macchwsuo. */
5891 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16);
5892 /* macchwu - macchwu. */
5893 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04);
5894 /* macchwuo - macchwuo. */
5895 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14);
5896 /* machhw - machhw. */
5897 GEN_MAC_HANDLER(machhw, 0x0C, 0x01);
5898 /* machhwo - machhwo. */
5899 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11);
5900 /* machhws - machhws. */
5901 GEN_MAC_HANDLER(machhws, 0x0C, 0x03);
5902 /* machhwso - machhwso. */
5903 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13);
5904 /* machhwsu - machhwsu. */
5905 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02);
5906 /* machhwsuo - machhwsuo. */
5907 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12);
5908 /* machhwu - machhwu. */
5909 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00);
5910 /* machhwuo - machhwuo. */
5911 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10);
5912 /* maclhw - maclhw. */
5913 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D);
5914 /* maclhwo - maclhwo. */
5915 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D);
5916 /* maclhws - maclhws. */
5917 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F);
5918 /* maclhwso - maclhwso. */
5919 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F);
5920 /* maclhwu - maclhwu. */
5921 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C);
5922 /* maclhwuo - maclhwuo. */
5923 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C);
5924 /* maclhwsu - maclhwsu. */
5925 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E);
5926 /* maclhwsuo - maclhwsuo. */
5927 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E);
5928 /* nmacchw - nmacchw. */
5929 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05);
5930 /* nmacchwo - nmacchwo. */
5931 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15);
5932 /* nmacchws - nmacchws. */
5933 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07);
5934 /* nmacchwso - nmacchwso. */
5935 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17);
5936 /* nmachhw - nmachhw. */
5937 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01);
5938 /* nmachhwo - nmachhwo. */
5939 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11);
5940 /* nmachhws - nmachhws. */
5941 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03);
5942 /* nmachhwso - nmachhwso. */
5943 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13);
5944 /* nmaclhw - nmaclhw. */
5945 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D);
5946 /* nmaclhwo - nmaclhwo. */
5947 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D);
5948 /* nmaclhws - nmaclhws. */
5949 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F);
5950 /* nmaclhwso - nmaclhwso. */
5951 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F);
5952
5953 /* mulchw - mulchw. */
5954 GEN_MAC_HANDLER(mulchw, 0x08, 0x05);
5955 /* mulchwu - mulchwu. */
5956 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04);
5957 /* mulhhw - mulhhw. */
5958 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01);
5959 /* mulhhwu - mulhhwu. */
5960 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00);
5961 /* mullhw - mullhw. */
5962 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D);
5963 /* mullhwu - mullhwu. */
5964 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C);
5965
5966 /* mfdcr */
5967 static void gen_mfdcr(DisasContext *ctx)
5968 {
5969 #if defined(CONFIG_USER_ONLY)
5970 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5971 #else
5972 TCGv dcrn;
5973 if (unlikely(!ctx->mem_idx)) {
5974 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5975 return;
5976 }
5977 /* NIP cannot be restored if the memory exception comes from an helper */
5978 gen_update_nip(ctx, ctx->nip - 4);
5979 dcrn = tcg_const_tl(SPR(ctx->opcode));
5980 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env, dcrn);
5981 tcg_temp_free(dcrn);
5982 #endif
5983 }
5984
5985 /* mtdcr */
5986 static void gen_mtdcr(DisasContext *ctx)
5987 {
5988 #if defined(CONFIG_USER_ONLY)
5989 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5990 #else
5991 TCGv dcrn;
5992 if (unlikely(!ctx->mem_idx)) {
5993 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
5994 return;
5995 }
5996 /* NIP cannot be restored if the memory exception comes from an helper */
5997 gen_update_nip(ctx, ctx->nip - 4);
5998 dcrn = tcg_const_tl(SPR(ctx->opcode));
5999 gen_helper_store_dcr(cpu_env, dcrn, cpu_gpr[rS(ctx->opcode)]);
6000 tcg_temp_free(dcrn);
6001 #endif
6002 }
6003
6004 /* mfdcrx */
6005 /* XXX: not implemented on 440 ? */
6006 static void gen_mfdcrx(DisasContext *ctx)
6007 {
6008 #if defined(CONFIG_USER_ONLY)
6009 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6010 #else
6011 if (unlikely(!ctx->mem_idx)) {
6012 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6013 return;
6014 }
6015 /* NIP cannot be restored if the memory exception comes from an helper */
6016 gen_update_nip(ctx, ctx->nip - 4);
6017 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6018 cpu_gpr[rA(ctx->opcode)]);
6019 /* Note: Rc update flag set leads to undefined state of Rc0 */
6020 #endif
6021 }
6022
6023 /* mtdcrx */
6024 /* XXX: not implemented on 440 ? */
6025 static void gen_mtdcrx(DisasContext *ctx)
6026 {
6027 #if defined(CONFIG_USER_ONLY)
6028 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6029 #else
6030 if (unlikely(!ctx->mem_idx)) {
6031 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
6032 return;
6033 }
6034 /* NIP cannot be restored if the memory exception comes from an helper */
6035 gen_update_nip(ctx, ctx->nip - 4);
6036 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6037 cpu_gpr[rS(ctx->opcode)]);
6038 /* Note: Rc update flag set leads to undefined state of Rc0 */
6039 #endif
6040 }
6041
6042 /* mfdcrux (PPC 460) : user-mode access to DCR */
6043 static void gen_mfdcrux(DisasContext *ctx)
6044 {
6045 /* NIP cannot be restored if the memory exception comes from an helper */
6046 gen_update_nip(ctx, ctx->nip - 4);
6047 gen_helper_load_dcr(cpu_gpr[rD(ctx->opcode)], cpu_env,
6048 cpu_gpr[rA(ctx->opcode)]);
6049 /* Note: Rc update flag set leads to undefined state of Rc0 */
6050 }
6051
6052 /* mtdcrux (PPC 460) : user-mode access to DCR */
6053 static void gen_mtdcrux(DisasContext *ctx)
6054 {
6055 /* NIP cannot be restored if the memory exception comes from an helper */
6056 gen_update_nip(ctx, ctx->nip - 4);
6057 gen_helper_store_dcr(cpu_env, cpu_gpr[rA(ctx->opcode)],
6058 cpu_gpr[rS(ctx->opcode)]);
6059 /* Note: Rc update flag set leads to undefined state of Rc0 */
6060 }
6061
6062 /* dccci */
6063 static void gen_dccci(DisasContext *ctx)
6064 {
6065 #if defined(CONFIG_USER_ONLY)
6066 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6067 #else
6068 if (unlikely(!ctx->mem_idx)) {
6069 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6070 return;
6071 }
6072 /* interpreted as no-op */
6073 #endif
6074 }
6075
6076 /* dcread */
6077 static void gen_dcread(DisasContext *ctx)
6078 {
6079 #if defined(CONFIG_USER_ONLY)
6080 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6081 #else
6082 TCGv EA, val;
6083 if (unlikely(!ctx->mem_idx)) {
6084 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6085 return;
6086 }
6087 gen_set_access_type(ctx, ACCESS_CACHE);
6088 EA = tcg_temp_new();
6089 gen_addr_reg_index(ctx, EA);
6090 val = tcg_temp_new();
6091 gen_qemu_ld32u(ctx, val, EA);
6092 tcg_temp_free(val);
6093 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], EA);
6094 tcg_temp_free(EA);
6095 #endif
6096 }
6097
6098 /* icbt */
6099 static void gen_icbt_40x(DisasContext *ctx)
6100 {
6101 /* interpreted as no-op */
6102 /* XXX: specification say this is treated as a load by the MMU
6103 * but does not generate any exception
6104 */
6105 }
6106
6107 /* iccci */
6108 static void gen_iccci(DisasContext *ctx)
6109 {
6110 #if defined(CONFIG_USER_ONLY)
6111 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6112 #else
6113 if (unlikely(!ctx->mem_idx)) {
6114 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6115 return;
6116 }
6117 /* interpreted as no-op */
6118 #endif
6119 }
6120
6121 /* icread */
6122 static void gen_icread(DisasContext *ctx)
6123 {
6124 #if defined(CONFIG_USER_ONLY)
6125 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6126 #else
6127 if (unlikely(!ctx->mem_idx)) {
6128 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6129 return;
6130 }
6131 /* interpreted as no-op */
6132 #endif
6133 }
6134
6135 /* rfci (mem_idx only) */
6136 static void gen_rfci_40x(DisasContext *ctx)
6137 {
6138 #if defined(CONFIG_USER_ONLY)
6139 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6140 #else
6141 if (unlikely(!ctx->mem_idx)) {
6142 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6143 return;
6144 }
6145 /* Restore CPU state */
6146 gen_helper_40x_rfci(cpu_env);
6147 gen_sync_exception(ctx);
6148 #endif
6149 }
6150
6151 static void gen_rfci(DisasContext *ctx)
6152 {
6153 #if defined(CONFIG_USER_ONLY)
6154 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6155 #else
6156 if (unlikely(!ctx->mem_idx)) {
6157 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6158 return;
6159 }
6160 /* Restore CPU state */
6161 gen_helper_rfci(cpu_env);
6162 gen_sync_exception(ctx);
6163 #endif
6164 }
6165
6166 /* BookE specific */
6167
6168 /* XXX: not implemented on 440 ? */
6169 static void gen_rfdi(DisasContext *ctx)
6170 {
6171 #if defined(CONFIG_USER_ONLY)
6172 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6173 #else
6174 if (unlikely(!ctx->mem_idx)) {
6175 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6176 return;
6177 }
6178 /* Restore CPU state */
6179 gen_helper_rfdi(cpu_env);
6180 gen_sync_exception(ctx);
6181 #endif
6182 }
6183
6184 /* XXX: not implemented on 440 ? */
6185 static void gen_rfmci(DisasContext *ctx)
6186 {
6187 #if defined(CONFIG_USER_ONLY)
6188 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6189 #else
6190 if (unlikely(!ctx->mem_idx)) {
6191 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6192 return;
6193 }
6194 /* Restore CPU state */
6195 gen_helper_rfmci(cpu_env);
6196 gen_sync_exception(ctx);
6197 #endif
6198 }
6199
6200 /* TLB management - PowerPC 405 implementation */
6201
6202 /* tlbre */
6203 static void gen_tlbre_40x(DisasContext *ctx)
6204 {
6205 #if defined(CONFIG_USER_ONLY)
6206 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6207 #else
6208 if (unlikely(!ctx->mem_idx)) {
6209 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6210 return;
6211 }
6212 switch (rB(ctx->opcode)) {
6213 case 0:
6214 gen_helper_4xx_tlbre_hi(cpu_gpr[rD(ctx->opcode)], cpu_env,
6215 cpu_gpr[rA(ctx->opcode)]);
6216 break;
6217 case 1:
6218 gen_helper_4xx_tlbre_lo(cpu_gpr[rD(ctx->opcode)], cpu_env,
6219 cpu_gpr[rA(ctx->opcode)]);
6220 break;
6221 default:
6222 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6223 break;
6224 }
6225 #endif
6226 }
6227
6228 /* tlbsx - tlbsx. */
6229 static void gen_tlbsx_40x(DisasContext *ctx)
6230 {
6231 #if defined(CONFIG_USER_ONLY)
6232 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6233 #else
6234 TCGv t0;
6235 if (unlikely(!ctx->mem_idx)) {
6236 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6237 return;
6238 }
6239 t0 = tcg_temp_new();
6240 gen_addr_reg_index(ctx, t0);
6241 gen_helper_4xx_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6242 tcg_temp_free(t0);
6243 if (Rc(ctx->opcode)) {
6244 int l1 = gen_new_label();
6245 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6246 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6247 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6248 gen_set_label(l1);
6249 }
6250 #endif
6251 }
6252
6253 /* tlbwe */
6254 static void gen_tlbwe_40x(DisasContext *ctx)
6255 {
6256 #if defined(CONFIG_USER_ONLY)
6257 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6258 #else
6259 if (unlikely(!ctx->mem_idx)) {
6260 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6261 return;
6262 }
6263 switch (rB(ctx->opcode)) {
6264 case 0:
6265 gen_helper_4xx_tlbwe_hi(cpu_env, cpu_gpr[rA(ctx->opcode)],
6266 cpu_gpr[rS(ctx->opcode)]);
6267 break;
6268 case 1:
6269 gen_helper_4xx_tlbwe_lo(cpu_env, cpu_gpr[rA(ctx->opcode)],
6270 cpu_gpr[rS(ctx->opcode)]);
6271 break;
6272 default:
6273 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6274 break;
6275 }
6276 #endif
6277 }
6278
6279 /* TLB management - PowerPC 440 implementation */
6280
6281 /* tlbre */
6282 static void gen_tlbre_440(DisasContext *ctx)
6283 {
6284 #if defined(CONFIG_USER_ONLY)
6285 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6286 #else
6287 if (unlikely(!ctx->mem_idx)) {
6288 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6289 return;
6290 }
6291 switch (rB(ctx->opcode)) {
6292 case 0:
6293 case 1:
6294 case 2:
6295 {
6296 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6297 gen_helper_440_tlbre(cpu_gpr[rD(ctx->opcode)], cpu_env,
6298 t0, cpu_gpr[rA(ctx->opcode)]);
6299 tcg_temp_free_i32(t0);
6300 }
6301 break;
6302 default:
6303 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6304 break;
6305 }
6306 #endif
6307 }
6308
6309 /* tlbsx - tlbsx. */
6310 static void gen_tlbsx_440(DisasContext *ctx)
6311 {
6312 #if defined(CONFIG_USER_ONLY)
6313 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6314 #else
6315 TCGv t0;
6316 if (unlikely(!ctx->mem_idx)) {
6317 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6318 return;
6319 }
6320 t0 = tcg_temp_new();
6321 gen_addr_reg_index(ctx, t0);
6322 gen_helper_440_tlbsx(cpu_gpr[rD(ctx->opcode)], cpu_env, t0);
6323 tcg_temp_free(t0);
6324 if (Rc(ctx->opcode)) {
6325 int l1 = gen_new_label();
6326 tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
6327 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rD(ctx->opcode)], -1, l1);
6328 tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 0x02);
6329 gen_set_label(l1);
6330 }
6331 #endif
6332 }
6333
6334 /* tlbwe */
6335 static void gen_tlbwe_440(DisasContext *ctx)
6336 {
6337 #if defined(CONFIG_USER_ONLY)
6338 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6339 #else
6340 if (unlikely(!ctx->mem_idx)) {
6341 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6342 return;
6343 }
6344 switch (rB(ctx->opcode)) {
6345 case 0:
6346 case 1:
6347 case 2:
6348 {
6349 TCGv_i32 t0 = tcg_const_i32(rB(ctx->opcode));
6350 gen_helper_440_tlbwe(cpu_env, t0, cpu_gpr[rA(ctx->opcode)],
6351 cpu_gpr[rS(ctx->opcode)]);
6352 tcg_temp_free_i32(t0);
6353 }
6354 break;
6355 default:
6356 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6357 break;
6358 }
6359 #endif
6360 }
6361
6362 /* TLB management - PowerPC BookE 2.06 implementation */
6363
6364 /* tlbre */
6365 static void gen_tlbre_booke206(DisasContext *ctx)
6366 {
6367 #if defined(CONFIG_USER_ONLY)
6368 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6369 #else
6370 if (unlikely(!ctx->mem_idx)) {
6371 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6372 return;
6373 }
6374
6375 gen_helper_booke206_tlbre(cpu_env);
6376 #endif
6377 }
6378
6379 /* tlbsx - tlbsx. */
6380 static void gen_tlbsx_booke206(DisasContext *ctx)
6381 {
6382 #if defined(CONFIG_USER_ONLY)
6383 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6384 #else
6385 TCGv t0;
6386 if (unlikely(!ctx->mem_idx)) {
6387 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6388 return;
6389 }
6390
6391 if (rA(ctx->opcode)) {
6392 t0 = tcg_temp_new();
6393 tcg_gen_mov_tl(t0, cpu_gpr[rD(ctx->opcode)]);
6394 } else {
6395 t0 = tcg_const_tl(0);
6396 }
6397
6398 tcg_gen_add_tl(t0, t0, cpu_gpr[rB(ctx->opcode)]);
6399 gen_helper_booke206_tlbsx(cpu_env, t0);
6400 #endif
6401 }
6402
6403 /* tlbwe */
6404 static void gen_tlbwe_booke206(DisasContext *ctx)
6405 {
6406 #if defined(CONFIG_USER_ONLY)
6407 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6408 #else
6409 if (unlikely(!ctx->mem_idx)) {
6410 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6411 return;
6412 }
6413 gen_update_nip(ctx, ctx->nip - 4);
6414 gen_helper_booke206_tlbwe(cpu_env);
6415 #endif
6416 }
6417
6418 static void gen_tlbivax_booke206(DisasContext *ctx)
6419 {
6420 #if defined(CONFIG_USER_ONLY)
6421 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6422 #else
6423 TCGv t0;
6424 if (unlikely(!ctx->mem_idx)) {
6425 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6426 return;
6427 }
6428
6429 t0 = tcg_temp_new();
6430 gen_addr_reg_index(ctx, t0);
6431
6432 gen_helper_booke206_tlbivax(cpu_env, t0);
6433 #endif
6434 }
6435
6436 static void gen_tlbilx_booke206(DisasContext *ctx)
6437 {
6438 #if defined(CONFIG_USER_ONLY)
6439 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6440 #else
6441 TCGv t0;
6442 if (unlikely(!ctx->mem_idx)) {
6443 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6444 return;
6445 }
6446
6447 t0 = tcg_temp_new();
6448 gen_addr_reg_index(ctx, t0);
6449
6450 switch((ctx->opcode >> 21) & 0x3) {
6451 case 0:
6452 gen_helper_booke206_tlbilx0(cpu_env, t0);
6453 break;
6454 case 1:
6455 gen_helper_booke206_tlbilx1(cpu_env, t0);
6456 break;
6457 case 3:
6458 gen_helper_booke206_tlbilx3(cpu_env, t0);
6459 break;
6460 default:
6461 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
6462 break;
6463 }
6464
6465 tcg_temp_free(t0);
6466 #endif
6467 }
6468
6469
6470 /* wrtee */
6471 static void gen_wrtee(DisasContext *ctx)
6472 {
6473 #if defined(CONFIG_USER_ONLY)
6474 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6475 #else
6476 TCGv t0;
6477 if (unlikely(!ctx->mem_idx)) {
6478 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6479 return;
6480 }
6481 t0 = tcg_temp_new();
6482 tcg_gen_andi_tl(t0, cpu_gpr[rD(ctx->opcode)], (1 << MSR_EE));
6483 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6484 tcg_gen_or_tl(cpu_msr, cpu_msr, t0);
6485 tcg_temp_free(t0);
6486 /* Stop translation to have a chance to raise an exception
6487 * if we just set msr_ee to 1
6488 */
6489 gen_stop_exception(ctx);
6490 #endif
6491 }
6492
6493 /* wrteei */
6494 static void gen_wrteei(DisasContext *ctx)
6495 {
6496 #if defined(CONFIG_USER_ONLY)
6497 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6498 #else
6499 if (unlikely(!ctx->mem_idx)) {
6500 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6501 return;
6502 }
6503 if (ctx->opcode & 0x00008000) {
6504 tcg_gen_ori_tl(cpu_msr, cpu_msr, (1 << MSR_EE));
6505 /* Stop translation to have a chance to raise an exception */
6506 gen_stop_exception(ctx);
6507 } else {
6508 tcg_gen_andi_tl(cpu_msr, cpu_msr, ~(1 << MSR_EE));
6509 }
6510 #endif
6511 }
6512
6513 /* PowerPC 440 specific instructions */
6514
6515 /* dlmzb */
6516 static void gen_dlmzb(DisasContext *ctx)
6517 {
6518 TCGv_i32 t0 = tcg_const_i32(Rc(ctx->opcode));
6519 gen_helper_dlmzb(cpu_gpr[rA(ctx->opcode)], cpu_env,
6520 cpu_gpr[rS(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], t0);
6521 tcg_temp_free_i32(t0);
6522 }
6523
6524 /* mbar replaces eieio on 440 */
6525 static void gen_mbar(DisasContext *ctx)
6526 {
6527 /* interpreted as no-op */
6528 }
6529
6530 /* msync replaces sync on 440 */
6531 static void gen_msync_4xx(DisasContext *ctx)
6532 {
6533 /* interpreted as no-op */
6534 }
6535
6536 /* icbt */
6537 static void gen_icbt_440(DisasContext *ctx)
6538 {
6539 /* interpreted as no-op */
6540 /* XXX: specification say this is treated as a load by the MMU
6541 * but does not generate any exception
6542 */
6543 }
6544
6545 /* Embedded.Processor Control */
6546
6547 static void gen_msgclr(DisasContext *ctx)
6548 {
6549 #if defined(CONFIG_USER_ONLY)
6550 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6551 #else
6552 if (unlikely(ctx->mem_idx == 0)) {
6553 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6554 return;
6555 }
6556
6557 gen_helper_msgclr(cpu_env, cpu_gpr[rB(ctx->opcode)]);
6558 #endif
6559 }
6560
6561 static void gen_msgsnd(DisasContext *ctx)
6562 {
6563 #if defined(CONFIG_USER_ONLY)
6564 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6565 #else
6566 if (unlikely(ctx->mem_idx == 0)) {
6567 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_OPC);
6568 return;
6569 }
6570
6571 gen_helper_msgsnd(cpu_gpr[rB(ctx->opcode)]);
6572 #endif
6573 }
6574
6575 /*** Altivec vector extension ***/
6576 /* Altivec registers moves */
6577
6578 static inline TCGv_ptr gen_avr_ptr(int reg)
6579 {
6580 TCGv_ptr r = tcg_temp_new_ptr();
6581 tcg_gen_addi_ptr(r, cpu_env, offsetof(CPUPPCState, avr[reg]));
6582 return r;
6583 }
6584
6585 #define GEN_VR_LDX(name, opc2, opc3) \
6586 static void glue(gen_, name)(DisasContext *ctx) \
6587 { \
6588 TCGv EA; \
6589 if (unlikely(!ctx->altivec_enabled)) { \
6590 gen_exception(ctx, POWERPC_EXCP_VPU); \
6591 return; \
6592 } \
6593 gen_set_access_type(ctx, ACCESS_INT); \
6594 EA = tcg_temp_new(); \
6595 gen_addr_reg_index(ctx, EA); \
6596 tcg_gen_andi_tl(EA, EA, ~0xf); \
6597 if (ctx->le_mode) { \
6598 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6599 tcg_gen_addi_tl(EA, EA, 8); \
6600 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6601 } else { \
6602 gen_qemu_ld64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6603 tcg_gen_addi_tl(EA, EA, 8); \
6604 gen_qemu_ld64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6605 } \
6606 tcg_temp_free(EA); \
6607 }
6608
6609 #define GEN_VR_STX(name, opc2, opc3) \
6610 static void gen_st##name(DisasContext *ctx) \
6611 { \
6612 TCGv EA; \
6613 if (unlikely(!ctx->altivec_enabled)) { \
6614 gen_exception(ctx, POWERPC_EXCP_VPU); \
6615 return; \
6616 } \
6617 gen_set_access_type(ctx, ACCESS_INT); \
6618 EA = tcg_temp_new(); \
6619 gen_addr_reg_index(ctx, EA); \
6620 tcg_gen_andi_tl(EA, EA, ~0xf); \
6621 if (ctx->le_mode) { \
6622 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6623 tcg_gen_addi_tl(EA, EA, 8); \
6624 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6625 } else { \
6626 gen_qemu_st64(ctx, cpu_avrh[rD(ctx->opcode)], EA); \
6627 tcg_gen_addi_tl(EA, EA, 8); \
6628 gen_qemu_st64(ctx, cpu_avrl[rD(ctx->opcode)], EA); \
6629 } \
6630 tcg_temp_free(EA); \
6631 }
6632
6633 #define GEN_VR_LVE(name, opc2, opc3) \
6634 static void gen_lve##name(DisasContext *ctx) \
6635 { \
6636 TCGv EA; \
6637 TCGv_ptr rs; \
6638 if (unlikely(!ctx->altivec_enabled)) { \
6639 gen_exception(ctx, POWERPC_EXCP_VPU); \
6640 return; \
6641 } \
6642 gen_set_access_type(ctx, ACCESS_INT); \
6643 EA = tcg_temp_new(); \
6644 gen_addr_reg_index(ctx, EA); \
6645 rs = gen_avr_ptr(rS(ctx->opcode)); \
6646 gen_helper_lve##name(cpu_env, rs, EA); \
6647 tcg_temp_free(EA); \
6648 tcg_temp_free_ptr(rs); \
6649 }
6650
6651 #define GEN_VR_STVE(name, opc2, opc3) \
6652 static void gen_stve##name(DisasContext *ctx) \
6653 { \
6654 TCGv EA; \
6655 TCGv_ptr rs; \
6656 if (unlikely(!ctx->altivec_enabled)) { \
6657 gen_exception(ctx, POWERPC_EXCP_VPU); \
6658 return; \
6659 } \
6660 gen_set_access_type(ctx, ACCESS_INT); \
6661 EA = tcg_temp_new(); \
6662 gen_addr_reg_index(ctx, EA); \
6663 rs = gen_avr_ptr(rS(ctx->opcode)); \
6664 gen_helper_stve##name(cpu_env, rs, EA); \
6665 tcg_temp_free(EA); \
6666 tcg_temp_free_ptr(rs); \
6667 }
6668
6669 GEN_VR_LDX(lvx, 0x07, 0x03);
6670 /* As we don't emulate the cache, lvxl is stricly equivalent to lvx */
6671 GEN_VR_LDX(lvxl, 0x07, 0x0B);
6672
6673 GEN_VR_LVE(bx, 0x07, 0x00);
6674 GEN_VR_LVE(hx, 0x07, 0x01);
6675 GEN_VR_LVE(wx, 0x07, 0x02);
6676
6677 GEN_VR_STX(svx, 0x07, 0x07);
6678 /* As we don't emulate the cache, stvxl is stricly equivalent to stvx */
6679 GEN_VR_STX(svxl, 0x07, 0x0F);
6680
6681 GEN_VR_STVE(bx, 0x07, 0x04);
6682 GEN_VR_STVE(hx, 0x07, 0x05);
6683 GEN_VR_STVE(wx, 0x07, 0x06);
6684
6685 static void gen_lvsl(DisasContext *ctx)
6686 {
6687 TCGv_ptr rd;
6688 TCGv EA;
6689 if (unlikely(!ctx->altivec_enabled)) {
6690 gen_exception(ctx, POWERPC_EXCP_VPU);
6691 return;
6692 }
6693 EA = tcg_temp_new();
6694 gen_addr_reg_index(ctx, EA);
6695 rd = gen_avr_ptr(rD(ctx->opcode));
6696 gen_helper_lvsl(rd, EA);
6697 tcg_temp_free(EA);
6698 tcg_temp_free_ptr(rd);
6699 }
6700
6701 static void gen_lvsr(DisasContext *ctx)
6702 {
6703 TCGv_ptr rd;
6704 TCGv EA;
6705 if (unlikely(!ctx->altivec_enabled)) {
6706 gen_exception(ctx, POWERPC_EXCP_VPU);
6707 return;
6708 }
6709 EA = tcg_temp_new();
6710 gen_addr_reg_index(ctx, EA);
6711 rd = gen_avr_ptr(rD(ctx->opcode));
6712 gen_helper_lvsr(rd, EA);
6713 tcg_temp_free(EA);
6714 tcg_temp_free_ptr(rd);
6715 }
6716
6717 static void gen_mfvscr(DisasContext *ctx)
6718 {
6719 TCGv_i32 t;
6720 if (unlikely(!ctx->altivec_enabled)) {
6721 gen_exception(ctx, POWERPC_EXCP_VPU);
6722 return;
6723 }
6724 tcg_gen_movi_i64(cpu_avrh[rD(ctx->opcode)], 0);
6725 t = tcg_temp_new_i32();
6726 tcg_gen_ld_i32(t, cpu_env, offsetof(CPUPPCState, vscr));
6727 tcg_gen_extu_i32_i64(cpu_avrl[rD(ctx->opcode)], t);
6728 tcg_temp_free_i32(t);
6729 }
6730
6731 static void gen_mtvscr(DisasContext *ctx)
6732 {
6733 TCGv_ptr p;
6734 if (unlikely(!ctx->altivec_enabled)) {
6735 gen_exception(ctx, POWERPC_EXCP_VPU);
6736 return;
6737 }
6738 p = gen_avr_ptr(rD(ctx->opcode));
6739 gen_helper_mtvscr(cpu_env, p);
6740 tcg_temp_free_ptr(p);
6741 }
6742
6743 /* Logical operations */
6744 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
6745 static void glue(gen_, name)(DisasContext *ctx) \
6746 { \
6747 if (unlikely(!ctx->altivec_enabled)) { \
6748 gen_exception(ctx, POWERPC_EXCP_VPU); \
6749 return; \
6750 } \
6751 tcg_op(cpu_avrh[rD(ctx->opcode)], cpu_avrh[rA(ctx->opcode)], cpu_avrh[rB(ctx->opcode)]); \
6752 tcg_op(cpu_avrl[rD(ctx->opcode)], cpu_avrl[rA(ctx->opcode)], cpu_avrl[rB(ctx->opcode)]); \
6753 }
6754
6755 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16);
6756 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17);
6757 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18);
6758 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19);
6759 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20);
6760
6761 #define GEN_VXFORM(name, opc2, opc3) \
6762 static void glue(gen_, name)(DisasContext *ctx) \
6763 { \
6764 TCGv_ptr ra, rb, rd; \
6765 if (unlikely(!ctx->altivec_enabled)) { \
6766 gen_exception(ctx, POWERPC_EXCP_VPU); \
6767 return; \
6768 } \
6769 ra = gen_avr_ptr(rA(ctx->opcode)); \
6770 rb = gen_avr_ptr(rB(ctx->opcode)); \
6771 rd = gen_avr_ptr(rD(ctx->opcode)); \
6772 gen_helper_##name (rd, ra, rb); \
6773 tcg_temp_free_ptr(ra); \
6774 tcg_temp_free_ptr(rb); \
6775 tcg_temp_free_ptr(rd); \
6776 }
6777
6778 #define GEN_VXFORM_ENV(name, opc2, opc3) \
6779 static void glue(gen_, name)(DisasContext *ctx) \
6780 { \
6781 TCGv_ptr ra, rb, rd; \
6782 if (unlikely(!ctx->altivec_enabled)) { \
6783 gen_exception(ctx, POWERPC_EXCP_VPU); \
6784 return; \
6785 } \
6786 ra = gen_avr_ptr(rA(ctx->opcode)); \
6787 rb = gen_avr_ptr(rB(ctx->opcode)); \
6788 rd = gen_avr_ptr(rD(ctx->opcode)); \
6789 gen_helper_##name(cpu_env, rd, ra, rb); \
6790 tcg_temp_free_ptr(ra); \
6791 tcg_temp_free_ptr(rb); \
6792 tcg_temp_free_ptr(rd); \
6793 }
6794
6795 GEN_VXFORM(vaddubm, 0, 0);
6796 GEN_VXFORM(vadduhm, 0, 1);
6797 GEN_VXFORM(vadduwm, 0, 2);
6798 GEN_VXFORM(vsububm, 0, 16);
6799 GEN_VXFORM(vsubuhm, 0, 17);
6800 GEN_VXFORM(vsubuwm, 0, 18);
6801 GEN_VXFORM(vmaxub, 1, 0);
6802 GEN_VXFORM(vmaxuh, 1, 1);
6803 GEN_VXFORM(vmaxuw, 1, 2);
6804 GEN_VXFORM(vmaxsb, 1, 4);
6805 GEN_VXFORM(vmaxsh, 1, 5);
6806 GEN_VXFORM(vmaxsw, 1, 6);
6807 GEN_VXFORM(vminub, 1, 8);
6808 GEN_VXFORM(vminuh, 1, 9);
6809 GEN_VXFORM(vminuw, 1, 10);
6810 GEN_VXFORM(vminsb, 1, 12);
6811 GEN_VXFORM(vminsh, 1, 13);
6812 GEN_VXFORM(vminsw, 1, 14);
6813 GEN_VXFORM(vavgub, 1, 16);
6814 GEN_VXFORM(vavguh, 1, 17);
6815 GEN_VXFORM(vavguw, 1, 18);
6816 GEN_VXFORM(vavgsb, 1, 20);
6817 GEN_VXFORM(vavgsh, 1, 21);
6818 GEN_VXFORM(vavgsw, 1, 22);
6819 GEN_VXFORM(vmrghb, 6, 0);
6820 GEN_VXFORM(vmrghh, 6, 1);
6821 GEN_VXFORM(vmrghw, 6, 2);
6822 GEN_VXFORM(vmrglb, 6, 4);
6823 GEN_VXFORM(vmrglh, 6, 5);
6824 GEN_VXFORM(vmrglw, 6, 6);
6825 GEN_VXFORM(vmuloub, 4, 0);
6826 GEN_VXFORM(vmulouh, 4, 1);
6827 GEN_VXFORM(vmulosb, 4, 4);
6828 GEN_VXFORM(vmulosh, 4, 5);
6829 GEN_VXFORM(vmuleub, 4, 8);
6830 GEN_VXFORM(vmuleuh, 4, 9);
6831 GEN_VXFORM(vmulesb, 4, 12);
6832 GEN_VXFORM(vmulesh, 4, 13);
6833 GEN_VXFORM(vslb, 2, 4);
6834 GEN_VXFORM(vslh, 2, 5);
6835 GEN_VXFORM(vslw, 2, 6);
6836 GEN_VXFORM(vsrb, 2, 8);
6837 GEN_VXFORM(vsrh, 2, 9);
6838 GEN_VXFORM(vsrw, 2, 10);
6839 GEN_VXFORM(vsrab, 2, 12);
6840 GEN_VXFORM(vsrah, 2, 13);
6841 GEN_VXFORM(vsraw, 2, 14);
6842 GEN_VXFORM(vslo, 6, 16);
6843 GEN_VXFORM(vsro, 6, 17);
6844 GEN_VXFORM(vaddcuw, 0, 6);
6845 GEN_VXFORM(vsubcuw, 0, 22);
6846 GEN_VXFORM_ENV(vaddubs, 0, 8);
6847 GEN_VXFORM_ENV(vadduhs, 0, 9);
6848 GEN_VXFORM_ENV(vadduws, 0, 10);
6849 GEN_VXFORM_ENV(vaddsbs, 0, 12);
6850 GEN_VXFORM_ENV(vaddshs, 0, 13);
6851 GEN_VXFORM_ENV(vaddsws, 0, 14);
6852 GEN_VXFORM_ENV(vsububs, 0, 24);
6853 GEN_VXFORM_ENV(vsubuhs, 0, 25);
6854 GEN_VXFORM_ENV(vsubuws, 0, 26);
6855 GEN_VXFORM_ENV(vsubsbs, 0, 28);
6856 GEN_VXFORM_ENV(vsubshs, 0, 29);
6857 GEN_VXFORM_ENV(vsubsws, 0, 30);
6858 GEN_VXFORM(vrlb, 2, 0);
6859 GEN_VXFORM(vrlh, 2, 1);
6860 GEN_VXFORM(vrlw, 2, 2);
6861 GEN_VXFORM(vsl, 2, 7);
6862 GEN_VXFORM(vsr, 2, 11);
6863 GEN_VXFORM_ENV(vpkuhum, 7, 0);
6864 GEN_VXFORM_ENV(vpkuwum, 7, 1);
6865 GEN_VXFORM_ENV(vpkuhus, 7, 2);
6866 GEN_VXFORM_ENV(vpkuwus, 7, 3);
6867 GEN_VXFORM_ENV(vpkshus, 7, 4);
6868 GEN_VXFORM_ENV(vpkswus, 7, 5);
6869 GEN_VXFORM_ENV(vpkshss, 7, 6);
6870 GEN_VXFORM_ENV(vpkswss, 7, 7);
6871 GEN_VXFORM(vpkpx, 7, 12);
6872 GEN_VXFORM_ENV(vsum4ubs, 4, 24);
6873 GEN_VXFORM_ENV(vsum4sbs, 4, 28);
6874 GEN_VXFORM_ENV(vsum4shs, 4, 25);
6875 GEN_VXFORM_ENV(vsum2sws, 4, 26);
6876 GEN_VXFORM_ENV(vsumsws, 4, 30);
6877 GEN_VXFORM_ENV(vaddfp, 5, 0);
6878 GEN_VXFORM_ENV(vsubfp, 5, 1);
6879 GEN_VXFORM_ENV(vmaxfp, 5, 16);
6880 GEN_VXFORM_ENV(vminfp, 5, 17);
6881
6882 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
6883 static void glue(gen_, name)(DisasContext *ctx) \
6884 { \
6885 TCGv_ptr ra, rb, rd; \
6886 if (unlikely(!ctx->altivec_enabled)) { \
6887 gen_exception(ctx, POWERPC_EXCP_VPU); \
6888 return; \
6889 } \
6890 ra = gen_avr_ptr(rA(ctx->opcode)); \
6891 rb = gen_avr_ptr(rB(ctx->opcode)); \
6892 rd = gen_avr_ptr(rD(ctx->opcode)); \
6893 gen_helper_##opname(cpu_env, rd, ra, rb); \
6894 tcg_temp_free_ptr(ra); \
6895 tcg_temp_free_ptr(rb); \
6896 tcg_temp_free_ptr(rd); \
6897 }
6898
6899 #define GEN_VXRFORM(name, opc2, opc3) \
6900 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
6901 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
6902
6903 GEN_VXRFORM(vcmpequb, 3, 0)
6904 GEN_VXRFORM(vcmpequh, 3, 1)
6905 GEN_VXRFORM(vcmpequw, 3, 2)
6906 GEN_VXRFORM(vcmpgtsb, 3, 12)
6907 GEN_VXRFORM(vcmpgtsh, 3, 13)
6908 GEN_VXRFORM(vcmpgtsw, 3, 14)
6909 GEN_VXRFORM(vcmpgtub, 3, 8)
6910 GEN_VXRFORM(vcmpgtuh, 3, 9)
6911 GEN_VXRFORM(vcmpgtuw, 3, 10)
6912 GEN_VXRFORM(vcmpeqfp, 3, 3)
6913 GEN_VXRFORM(vcmpgefp, 3, 7)
6914 GEN_VXRFORM(vcmpgtfp, 3, 11)
6915 GEN_VXRFORM(vcmpbfp, 3, 15)
6916
6917 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6918 static void glue(gen_, name)(DisasContext *ctx) \
6919 { \
6920 TCGv_ptr rd; \
6921 TCGv_i32 simm; \
6922 if (unlikely(!ctx->altivec_enabled)) { \
6923 gen_exception(ctx, POWERPC_EXCP_VPU); \
6924 return; \
6925 } \
6926 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6927 rd = gen_avr_ptr(rD(ctx->opcode)); \
6928 gen_helper_##name (rd, simm); \
6929 tcg_temp_free_i32(simm); \
6930 tcg_temp_free_ptr(rd); \
6931 }
6932
6933 GEN_VXFORM_SIMM(vspltisb, 6, 12);
6934 GEN_VXFORM_SIMM(vspltish, 6, 13);
6935 GEN_VXFORM_SIMM(vspltisw, 6, 14);
6936
6937 #define GEN_VXFORM_NOA(name, opc2, opc3) \
6938 static void glue(gen_, name)(DisasContext *ctx) \
6939 { \
6940 TCGv_ptr rb, rd; \
6941 if (unlikely(!ctx->altivec_enabled)) { \
6942 gen_exception(ctx, POWERPC_EXCP_VPU); \
6943 return; \
6944 } \
6945 rb = gen_avr_ptr(rB(ctx->opcode)); \
6946 rd = gen_avr_ptr(rD(ctx->opcode)); \
6947 gen_helper_##name (rd, rb); \
6948 tcg_temp_free_ptr(rb); \
6949 tcg_temp_free_ptr(rd); \
6950 }
6951
6952 #define GEN_VXFORM_NOA_ENV(name, opc2, opc3) \
6953 static void glue(gen_, name)(DisasContext *ctx) \
6954 { \
6955 TCGv_ptr rb, rd; \
6956 \
6957 if (unlikely(!ctx->altivec_enabled)) { \
6958 gen_exception(ctx, POWERPC_EXCP_VPU); \
6959 return; \
6960 } \
6961 rb = gen_avr_ptr(rB(ctx->opcode)); \
6962 rd = gen_avr_ptr(rD(ctx->opcode)); \
6963 gen_helper_##name(cpu_env, rd, rb); \
6964 tcg_temp_free_ptr(rb); \
6965 tcg_temp_free_ptr(rd); \
6966 }
6967
6968 GEN_VXFORM_NOA(vupkhsb, 7, 8);
6969 GEN_VXFORM_NOA(vupkhsh, 7, 9);
6970 GEN_VXFORM_NOA(vupklsb, 7, 10);
6971 GEN_VXFORM_NOA(vupklsh, 7, 11);
6972 GEN_VXFORM_NOA(vupkhpx, 7, 13);
6973 GEN_VXFORM_NOA(vupklpx, 7, 15);
6974 GEN_VXFORM_NOA_ENV(vrefp, 5, 4);
6975 GEN_VXFORM_NOA_ENV(vrsqrtefp, 5, 5);
6976 GEN_VXFORM_NOA_ENV(vexptefp, 5, 6);
6977 GEN_VXFORM_NOA_ENV(vlogefp, 5, 7);
6978 GEN_VXFORM_NOA_ENV(vrfim, 5, 8);
6979 GEN_VXFORM_NOA_ENV(vrfin, 5, 9);
6980 GEN_VXFORM_NOA_ENV(vrfip, 5, 10);
6981 GEN_VXFORM_NOA_ENV(vrfiz, 5, 11);
6982
6983 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
6984 static void glue(gen_, name)(DisasContext *ctx) \
6985 { \
6986 TCGv_ptr rd; \
6987 TCGv_i32 simm; \
6988 if (unlikely(!ctx->altivec_enabled)) { \
6989 gen_exception(ctx, POWERPC_EXCP_VPU); \
6990 return; \
6991 } \
6992 simm = tcg_const_i32(SIMM5(ctx->opcode)); \
6993 rd = gen_avr_ptr(rD(ctx->opcode)); \
6994 gen_helper_##name (rd, simm); \
6995 tcg_temp_free_i32(simm); \
6996 tcg_temp_free_ptr(rd); \
6997 }
6998
6999 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
7000 static void glue(gen_, name)(DisasContext *ctx) \
7001 { \
7002 TCGv_ptr rb, rd; \
7003 TCGv_i32 uimm; \
7004 if (unlikely(!ctx->altivec_enabled)) { \
7005 gen_exception(ctx, POWERPC_EXCP_VPU); \
7006 return; \
7007 } \
7008 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7009 rb = gen_avr_ptr(rB(ctx->opcode)); \
7010 rd = gen_avr_ptr(rD(ctx->opcode)); \
7011 gen_helper_##name (rd, rb, uimm); \
7012 tcg_temp_free_i32(uimm); \
7013 tcg_temp_free_ptr(rb); \
7014 tcg_temp_free_ptr(rd); \
7015 }
7016
7017 #define GEN_VXFORM_UIMM_ENV(name, opc2, opc3) \
7018 static void glue(gen_, name)(DisasContext *ctx) \
7019 { \
7020 TCGv_ptr rb, rd; \
7021 TCGv_i32 uimm; \
7022 \
7023 if (unlikely(!ctx->altivec_enabled)) { \
7024 gen_exception(ctx, POWERPC_EXCP_VPU); \
7025 return; \
7026 } \
7027 uimm = tcg_const_i32(UIMM5(ctx->opcode)); \
7028 rb = gen_avr_ptr(rB(ctx->opcode)); \
7029 rd = gen_avr_ptr(rD(ctx->opcode)); \
7030 gen_helper_##name(cpu_env, rd, rb, uimm); \
7031 tcg_temp_free_i32(uimm); \
7032 tcg_temp_free_ptr(rb); \
7033 tcg_temp_free_ptr(rd); \
7034 }
7035
7036 GEN_VXFORM_UIMM(vspltb, 6, 8);
7037 GEN_VXFORM_UIMM(vsplth, 6, 9);
7038 GEN_VXFORM_UIMM(vspltw, 6, 10);
7039 GEN_VXFORM_UIMM_ENV(vcfux, 5, 12);
7040 GEN_VXFORM_UIMM_ENV(vcfsx, 5, 13);
7041 GEN_VXFORM_UIMM_ENV(vctuxs, 5, 14);
7042 GEN_VXFORM_UIMM_ENV(vctsxs, 5, 15);
7043
7044 static void gen_vsldoi(DisasContext *ctx)
7045 {
7046 TCGv_ptr ra, rb, rd;
7047 TCGv_i32 sh;
7048 if (unlikely(!ctx->altivec_enabled)) {
7049 gen_exception(ctx, POWERPC_EXCP_VPU);
7050 return;
7051 }
7052 ra = gen_avr_ptr(rA(ctx->opcode));
7053 rb = gen_avr_ptr(rB(ctx->opcode));
7054 rd = gen_avr_ptr(rD(ctx->opcode));
7055 sh = tcg_const_i32(VSH(ctx->opcode));
7056 gen_helper_vsldoi (rd, ra, rb, sh);
7057 tcg_temp_free_ptr(ra);
7058 tcg_temp_free_ptr(rb);
7059 tcg_temp_free_ptr(rd);
7060 tcg_temp_free_i32(sh);
7061 }
7062
7063 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
7064 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7065 { \
7066 TCGv_ptr ra, rb, rc, rd; \
7067 if (unlikely(!ctx->altivec_enabled)) { \
7068 gen_exception(ctx, POWERPC_EXCP_VPU); \
7069 return; \
7070 } \
7071 ra = gen_avr_ptr(rA(ctx->opcode)); \
7072 rb = gen_avr_ptr(rB(ctx->opcode)); \
7073 rc = gen_avr_ptr(rC(ctx->opcode)); \
7074 rd = gen_avr_ptr(rD(ctx->opcode)); \
7075 if (Rc(ctx->opcode)) { \
7076 gen_helper_##name1(cpu_env, rd, ra, rb, rc); \
7077 } else { \
7078 gen_helper_##name0(cpu_env, rd, ra, rb, rc); \
7079 } \
7080 tcg_temp_free_ptr(ra); \
7081 tcg_temp_free_ptr(rb); \
7082 tcg_temp_free_ptr(rc); \
7083 tcg_temp_free_ptr(rd); \
7084 }
7085
7086 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16)
7087
7088 static void gen_vmladduhm(DisasContext *ctx)
7089 {
7090 TCGv_ptr ra, rb, rc, rd;
7091 if (unlikely(!ctx->altivec_enabled)) {
7092 gen_exception(ctx, POWERPC_EXCP_VPU);
7093 return;
7094 }
7095 ra = gen_avr_ptr(rA(ctx->opcode));
7096 rb = gen_avr_ptr(rB(ctx->opcode));
7097 rc = gen_avr_ptr(rC(ctx->opcode));
7098 rd = gen_avr_ptr(rD(ctx->opcode));
7099 gen_helper_vmladduhm(rd, ra, rb, rc);
7100 tcg_temp_free_ptr(ra);
7101 tcg_temp_free_ptr(rb);
7102 tcg_temp_free_ptr(rc);
7103 tcg_temp_free_ptr(rd);
7104 }
7105
7106 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18)
7107 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19)
7108 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20)
7109 GEN_VAFORM_PAIRED(vsel, vperm, 21)
7110 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23)
7111
7112 /*** VSX extension ***/
7113
7114 static inline TCGv_i64 cpu_vsrh(int n)
7115 {
7116 if (n < 32) {
7117 return cpu_fpr[n];
7118 } else {
7119 return cpu_avrh[n-32];
7120 }
7121 }
7122
7123 static inline TCGv_i64 cpu_vsrl(int n)
7124 {
7125 if (n < 32) {
7126 return cpu_vsr[n];
7127 } else {
7128 return cpu_avrl[n-32];
7129 }
7130 }
7131
7132 #define VSX_LOAD_SCALAR(name, operation) \
7133 static void gen_##name(DisasContext *ctx) \
7134 { \
7135 TCGv EA; \
7136 if (unlikely(!ctx->vsx_enabled)) { \
7137 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7138 return; \
7139 } \
7140 gen_set_access_type(ctx, ACCESS_INT); \
7141 EA = tcg_temp_new(); \
7142 gen_addr_reg_index(ctx, EA); \
7143 gen_qemu_##operation(ctx, cpu_vsrh(xT(ctx->opcode)), EA); \
7144 /* NOTE: cpu_vsrl is undefined */ \
7145 tcg_temp_free(EA); \
7146 }
7147
7148 VSX_LOAD_SCALAR(lxsdx, ld64)
7149 VSX_LOAD_SCALAR(lxsiwax, ld32s_i64)
7150 VSX_LOAD_SCALAR(lxsiwzx, ld32u_i64)
7151 VSX_LOAD_SCALAR(lxsspx, ld32fs)
7152
7153 static void gen_lxvd2x(DisasContext *ctx)
7154 {
7155 TCGv EA;
7156 if (unlikely(!ctx->vsx_enabled)) {
7157 gen_exception(ctx, POWERPC_EXCP_VSXU);
7158 return;
7159 }
7160 gen_set_access_type(ctx, ACCESS_INT);
7161 EA = tcg_temp_new();
7162 gen_addr_reg_index(ctx, EA);
7163 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7164 tcg_gen_addi_tl(EA, EA, 8);
7165 gen_qemu_ld64(ctx, cpu_vsrl(xT(ctx->opcode)), EA);
7166 tcg_temp_free(EA);
7167 }
7168
7169 static void gen_lxvdsx(DisasContext *ctx)
7170 {
7171 TCGv EA;
7172 if (unlikely(!ctx->vsx_enabled)) {
7173 gen_exception(ctx, POWERPC_EXCP_VSXU);
7174 return;
7175 }
7176 gen_set_access_type(ctx, ACCESS_INT);
7177 EA = tcg_temp_new();
7178 gen_addr_reg_index(ctx, EA);
7179 gen_qemu_ld64(ctx, cpu_vsrh(xT(ctx->opcode)), EA);
7180 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7181 tcg_temp_free(EA);
7182 }
7183
7184 static void gen_lxvw4x(DisasContext *ctx)
7185 {
7186 TCGv EA;
7187 TCGv_i64 tmp;
7188 TCGv_i64 xth = cpu_vsrh(xT(ctx->opcode));
7189 TCGv_i64 xtl = cpu_vsrl(xT(ctx->opcode));
7190 if (unlikely(!ctx->vsx_enabled)) {
7191 gen_exception(ctx, POWERPC_EXCP_VSXU);
7192 return;
7193 }
7194 gen_set_access_type(ctx, ACCESS_INT);
7195 EA = tcg_temp_new();
7196 tmp = tcg_temp_new_i64();
7197
7198 gen_addr_reg_index(ctx, EA);
7199 gen_qemu_ld32u_i64(ctx, tmp, EA);
7200 tcg_gen_addi_tl(EA, EA, 4);
7201 gen_qemu_ld32u_i64(ctx, xth, EA);
7202 tcg_gen_deposit_i64(xth, xth, tmp, 32, 32);
7203
7204 tcg_gen_addi_tl(EA, EA, 4);
7205 gen_qemu_ld32u_i64(ctx, tmp, EA);
7206 tcg_gen_addi_tl(EA, EA, 4);
7207 gen_qemu_ld32u_i64(ctx, xtl, EA);
7208 tcg_gen_deposit_i64(xtl, xtl, tmp, 32, 32);
7209
7210 tcg_temp_free(EA);
7211 tcg_temp_free_i64(tmp);
7212 }
7213
7214 #define VSX_STORE_SCALAR(name, operation) \
7215 static void gen_##name(DisasContext *ctx) \
7216 { \
7217 TCGv EA; \
7218 if (unlikely(!ctx->vsx_enabled)) { \
7219 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7220 return; \
7221 } \
7222 gen_set_access_type(ctx, ACCESS_INT); \
7223 EA = tcg_temp_new(); \
7224 gen_addr_reg_index(ctx, EA); \
7225 gen_qemu_##operation(ctx, cpu_vsrh(xS(ctx->opcode)), EA); \
7226 tcg_temp_free(EA); \
7227 }
7228
7229 VSX_STORE_SCALAR(stxsdx, st64)
7230 VSX_STORE_SCALAR(stxsiwx, st32_i64)
7231 VSX_STORE_SCALAR(stxsspx, st32fs)
7232
7233 static void gen_stxvd2x(DisasContext *ctx)
7234 {
7235 TCGv EA;
7236 if (unlikely(!ctx->vsx_enabled)) {
7237 gen_exception(ctx, POWERPC_EXCP_VSXU);
7238 return;
7239 }
7240 gen_set_access_type(ctx, ACCESS_INT);
7241 EA = tcg_temp_new();
7242 gen_addr_reg_index(ctx, EA);
7243 gen_qemu_st64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7244 tcg_gen_addi_tl(EA, EA, 8);
7245 gen_qemu_st64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7246 tcg_temp_free(EA);
7247 }
7248
7249 static void gen_stxvw4x(DisasContext *ctx)
7250 {
7251 TCGv_i64 tmp;
7252 TCGv EA;
7253 if (unlikely(!ctx->vsx_enabled)) {
7254 gen_exception(ctx, POWERPC_EXCP_VSXU);
7255 return;
7256 }
7257 gen_set_access_type(ctx, ACCESS_INT);
7258 EA = tcg_temp_new();
7259 gen_addr_reg_index(ctx, EA);
7260 tmp = tcg_temp_new_i64();
7261
7262 tcg_gen_shri_i64(tmp, cpu_vsrh(xS(ctx->opcode)), 32);
7263 gen_qemu_st32_i64(ctx, tmp, EA);
7264 tcg_gen_addi_tl(EA, EA, 4);
7265 gen_qemu_st32_i64(ctx, cpu_vsrh(xS(ctx->opcode)), EA);
7266
7267 tcg_gen_shri_i64(tmp, cpu_vsrl(xS(ctx->opcode)), 32);
7268 tcg_gen_addi_tl(EA, EA, 4);
7269 gen_qemu_st32_i64(ctx, tmp, EA);
7270 tcg_gen_addi_tl(EA, EA, 4);
7271 gen_qemu_st32_i64(ctx, cpu_vsrl(xS(ctx->opcode)), EA);
7272
7273 tcg_temp_free(EA);
7274 tcg_temp_free_i64(tmp);
7275 }
7276
7277 #define MV_VSRW(name, tcgop1, tcgop2, target, source) \
7278 static void gen_##name(DisasContext *ctx) \
7279 { \
7280 if (xS(ctx->opcode) < 32) { \
7281 if (unlikely(!ctx->fpu_enabled)) { \
7282 gen_exception(ctx, POWERPC_EXCP_FPU); \
7283 return; \
7284 } \
7285 } else { \
7286 if (unlikely(!ctx->altivec_enabled)) { \
7287 gen_exception(ctx, POWERPC_EXCP_VPU); \
7288 return; \
7289 } \
7290 } \
7291 TCGv_i64 tmp = tcg_temp_new_i64(); \
7292 tcg_gen_##tcgop1(tmp, source); \
7293 tcg_gen_##tcgop2(target, tmp); \
7294 tcg_temp_free_i64(tmp); \
7295 }
7296
7297
7298 MV_VSRW(mfvsrwz, ext32u_i64, trunc_i64_tl, cpu_gpr[rA(ctx->opcode)], \
7299 cpu_vsrh(xS(ctx->opcode)))
7300 MV_VSRW(mtvsrwa, extu_tl_i64, ext32s_i64, cpu_vsrh(xT(ctx->opcode)), \
7301 cpu_gpr[rA(ctx->opcode)])
7302 MV_VSRW(mtvsrwz, extu_tl_i64, ext32u_i64, cpu_vsrh(xT(ctx->opcode)), \
7303 cpu_gpr[rA(ctx->opcode)])
7304
7305 #if defined(TARGET_PPC64)
7306 #define MV_VSRD(name, target, source) \
7307 static void gen_##name(DisasContext *ctx) \
7308 { \
7309 if (xS(ctx->opcode) < 32) { \
7310 if (unlikely(!ctx->fpu_enabled)) { \
7311 gen_exception(ctx, POWERPC_EXCP_FPU); \
7312 return; \
7313 } \
7314 } else { \
7315 if (unlikely(!ctx->altivec_enabled)) { \
7316 gen_exception(ctx, POWERPC_EXCP_VPU); \
7317 return; \
7318 } \
7319 } \
7320 tcg_gen_mov_i64(target, source); \
7321 }
7322
7323 MV_VSRD(mfvsrd, cpu_gpr[rA(ctx->opcode)], cpu_vsrh(xS(ctx->opcode)))
7324 MV_VSRD(mtvsrd, cpu_vsrh(xT(ctx->opcode)), cpu_gpr[rA(ctx->opcode)])
7325
7326 #endif
7327
7328 static void gen_xxpermdi(DisasContext *ctx)
7329 {
7330 if (unlikely(!ctx->vsx_enabled)) {
7331 gen_exception(ctx, POWERPC_EXCP_VSXU);
7332 return;
7333 }
7334
7335 if (unlikely((xT(ctx->opcode) == xA(ctx->opcode)) ||
7336 (xT(ctx->opcode) == xB(ctx->opcode)))) {
7337 TCGv_i64 xh, xl;
7338
7339 xh = tcg_temp_new_i64();
7340 xl = tcg_temp_new_i64();
7341
7342 if ((DM(ctx->opcode) & 2) == 0) {
7343 tcg_gen_mov_i64(xh, cpu_vsrh(xA(ctx->opcode)));
7344 } else {
7345 tcg_gen_mov_i64(xh, cpu_vsrl(xA(ctx->opcode)));
7346 }
7347 if ((DM(ctx->opcode) & 1) == 0) {
7348 tcg_gen_mov_i64(xl, cpu_vsrh(xB(ctx->opcode)));
7349 } else {
7350 tcg_gen_mov_i64(xl, cpu_vsrl(xB(ctx->opcode)));
7351 }
7352
7353 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xh);
7354 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xl);
7355
7356 tcg_temp_free_i64(xh);
7357 tcg_temp_free_i64(xl);
7358 } else {
7359 if ((DM(ctx->opcode) & 2) == 0) {
7360 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)));
7361 } else {
7362 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)));
7363 }
7364 if ((DM(ctx->opcode) & 1) == 0) {
7365 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xB(ctx->opcode)));
7366 } else {
7367 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xB(ctx->opcode)));
7368 }
7369 }
7370 }
7371
7372 #define OP_ABS 1
7373 #define OP_NABS 2
7374 #define OP_NEG 3
7375 #define OP_CPSGN 4
7376 #define SGN_MASK_DP 0x8000000000000000ul
7377 #define SGN_MASK_SP 0x8000000080000000ul
7378
7379 #define VSX_SCALAR_MOVE(name, op, sgn_mask) \
7380 static void glue(gen_, name)(DisasContext * ctx) \
7381 { \
7382 TCGv_i64 xb, sgm; \
7383 if (unlikely(!ctx->vsx_enabled)) { \
7384 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7385 return; \
7386 } \
7387 xb = tcg_temp_new_i64(); \
7388 sgm = tcg_temp_new_i64(); \
7389 tcg_gen_mov_i64(xb, cpu_vsrh(xB(ctx->opcode))); \
7390 tcg_gen_movi_i64(sgm, sgn_mask); \
7391 switch (op) { \
7392 case OP_ABS: { \
7393 tcg_gen_andc_i64(xb, xb, sgm); \
7394 break; \
7395 } \
7396 case OP_NABS: { \
7397 tcg_gen_or_i64(xb, xb, sgm); \
7398 break; \
7399 } \
7400 case OP_NEG: { \
7401 tcg_gen_xor_i64(xb, xb, sgm); \
7402 break; \
7403 } \
7404 case OP_CPSGN: { \
7405 TCGv_i64 xa = tcg_temp_new_i64(); \
7406 tcg_gen_mov_i64(xa, cpu_vsrh(xA(ctx->opcode))); \
7407 tcg_gen_and_i64(xa, xa, sgm); \
7408 tcg_gen_andc_i64(xb, xb, sgm); \
7409 tcg_gen_or_i64(xb, xb, xa); \
7410 tcg_temp_free_i64(xa); \
7411 break; \
7412 } \
7413 } \
7414 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xb); \
7415 tcg_temp_free_i64(xb); \
7416 tcg_temp_free_i64(sgm); \
7417 }
7418
7419 VSX_SCALAR_MOVE(xsabsdp, OP_ABS, SGN_MASK_DP)
7420 VSX_SCALAR_MOVE(xsnabsdp, OP_NABS, SGN_MASK_DP)
7421 VSX_SCALAR_MOVE(xsnegdp, OP_NEG, SGN_MASK_DP)
7422 VSX_SCALAR_MOVE(xscpsgndp, OP_CPSGN, SGN_MASK_DP)
7423
7424 #define VSX_VECTOR_MOVE(name, op, sgn_mask) \
7425 static void glue(gen_, name)(DisasContext * ctx) \
7426 { \
7427 TCGv_i64 xbh, xbl, sgm; \
7428 if (unlikely(!ctx->vsx_enabled)) { \
7429 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7430 return; \
7431 } \
7432 xbh = tcg_temp_new_i64(); \
7433 xbl = tcg_temp_new_i64(); \
7434 sgm = tcg_temp_new_i64(); \
7435 tcg_gen_mov_i64(xbh, cpu_vsrh(xB(ctx->opcode))); \
7436 tcg_gen_mov_i64(xbl, cpu_vsrl(xB(ctx->opcode))); \
7437 tcg_gen_movi_i64(sgm, sgn_mask); \
7438 switch (op) { \
7439 case OP_ABS: { \
7440 tcg_gen_andc_i64(xbh, xbh, sgm); \
7441 tcg_gen_andc_i64(xbl, xbl, sgm); \
7442 break; \
7443 } \
7444 case OP_NABS: { \
7445 tcg_gen_or_i64(xbh, xbh, sgm); \
7446 tcg_gen_or_i64(xbl, xbl, sgm); \
7447 break; \
7448 } \
7449 case OP_NEG: { \
7450 tcg_gen_xor_i64(xbh, xbh, sgm); \
7451 tcg_gen_xor_i64(xbl, xbl, sgm); \
7452 break; \
7453 } \
7454 case OP_CPSGN: { \
7455 TCGv_i64 xah = tcg_temp_new_i64(); \
7456 TCGv_i64 xal = tcg_temp_new_i64(); \
7457 tcg_gen_mov_i64(xah, cpu_vsrh(xA(ctx->opcode))); \
7458 tcg_gen_mov_i64(xal, cpu_vsrl(xA(ctx->opcode))); \
7459 tcg_gen_and_i64(xah, xah, sgm); \
7460 tcg_gen_and_i64(xal, xal, sgm); \
7461 tcg_gen_andc_i64(xbh, xbh, sgm); \
7462 tcg_gen_andc_i64(xbl, xbl, sgm); \
7463 tcg_gen_or_i64(xbh, xbh, xah); \
7464 tcg_gen_or_i64(xbl, xbl, xal); \
7465 tcg_temp_free_i64(xah); \
7466 tcg_temp_free_i64(xal); \
7467 break; \
7468 } \
7469 } \
7470 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xbh); \
7471 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xbl); \
7472 tcg_temp_free_i64(xbh); \
7473 tcg_temp_free_i64(xbl); \
7474 tcg_temp_free_i64(sgm); \
7475 }
7476
7477 VSX_VECTOR_MOVE(xvabsdp, OP_ABS, SGN_MASK_DP)
7478 VSX_VECTOR_MOVE(xvnabsdp, OP_NABS, SGN_MASK_DP)
7479 VSX_VECTOR_MOVE(xvnegdp, OP_NEG, SGN_MASK_DP)
7480 VSX_VECTOR_MOVE(xvcpsgndp, OP_CPSGN, SGN_MASK_DP)
7481 VSX_VECTOR_MOVE(xvabssp, OP_ABS, SGN_MASK_SP)
7482 VSX_VECTOR_MOVE(xvnabssp, OP_NABS, SGN_MASK_SP)
7483 VSX_VECTOR_MOVE(xvnegsp, OP_NEG, SGN_MASK_SP)
7484 VSX_VECTOR_MOVE(xvcpsgnsp, OP_CPSGN, SGN_MASK_SP)
7485
7486 #define GEN_VSX_HELPER_2(name, op1, op2, inval, type) \
7487 static void gen_##name(DisasContext * ctx) \
7488 { \
7489 TCGv_i32 opc; \
7490 if (unlikely(!ctx->vsx_enabled)) { \
7491 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7492 return; \
7493 } \
7494 /* NIP cannot be restored if the memory exception comes from an helper */ \
7495 gen_update_nip(ctx, ctx->nip - 4); \
7496 opc = tcg_const_i32(ctx->opcode); \
7497 gen_helper_##name(cpu_env, opc); \
7498 tcg_temp_free_i32(opc); \
7499 }
7500
7501 #define GEN_VSX_HELPER_XT_XB_ENV(name, op1, op2, inval, type) \
7502 static void gen_##name(DisasContext * ctx) \
7503 { \
7504 if (unlikely(!ctx->vsx_enabled)) { \
7505 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7506 return; \
7507 } \
7508 /* NIP cannot be restored if the exception comes */ \
7509 /* from a helper. */ \
7510 gen_update_nip(ctx, ctx->nip - 4); \
7511 \
7512 gen_helper_##name(cpu_vsrh(xT(ctx->opcode)), cpu_env, \
7513 cpu_vsrh(xB(ctx->opcode))); \
7514 }
7515
7516 GEN_VSX_HELPER_2(xsadddp, 0x00, 0x04, 0, PPC2_VSX)
7517 GEN_VSX_HELPER_2(xssubdp, 0x00, 0x05, 0, PPC2_VSX)
7518 GEN_VSX_HELPER_2(xsmuldp, 0x00, 0x06, 0, PPC2_VSX)
7519 GEN_VSX_HELPER_2(xsdivdp, 0x00, 0x07, 0, PPC2_VSX)
7520 GEN_VSX_HELPER_2(xsredp, 0x14, 0x05, 0, PPC2_VSX)
7521 GEN_VSX_HELPER_2(xssqrtdp, 0x16, 0x04, 0, PPC2_VSX)
7522 GEN_VSX_HELPER_2(xsrsqrtedp, 0x14, 0x04, 0, PPC2_VSX)
7523 GEN_VSX_HELPER_2(xstdivdp, 0x14, 0x07, 0, PPC2_VSX)
7524 GEN_VSX_HELPER_2(xstsqrtdp, 0x14, 0x06, 0, PPC2_VSX)
7525 GEN_VSX_HELPER_2(xsmaddadp, 0x04, 0x04, 0, PPC2_VSX)
7526 GEN_VSX_HELPER_2(xsmaddmdp, 0x04, 0x05, 0, PPC2_VSX)
7527 GEN_VSX_HELPER_2(xsmsubadp, 0x04, 0x06, 0, PPC2_VSX)
7528 GEN_VSX_HELPER_2(xsmsubmdp, 0x04, 0x07, 0, PPC2_VSX)
7529 GEN_VSX_HELPER_2(xsnmaddadp, 0x04, 0x14, 0, PPC2_VSX)
7530 GEN_VSX_HELPER_2(xsnmaddmdp, 0x04, 0x15, 0, PPC2_VSX)
7531 GEN_VSX_HELPER_2(xsnmsubadp, 0x04, 0x16, 0, PPC2_VSX)
7532 GEN_VSX_HELPER_2(xsnmsubmdp, 0x04, 0x17, 0, PPC2_VSX)
7533 GEN_VSX_HELPER_2(xscmpodp, 0x0C, 0x05, 0, PPC2_VSX)
7534 GEN_VSX_HELPER_2(xscmpudp, 0x0C, 0x04, 0, PPC2_VSX)
7535 GEN_VSX_HELPER_2(xsmaxdp, 0x00, 0x14, 0, PPC2_VSX)
7536 GEN_VSX_HELPER_2(xsmindp, 0x00, 0x15, 0, PPC2_VSX)
7537 GEN_VSX_HELPER_2(xscvdpsp, 0x12, 0x10, 0, PPC2_VSX)
7538 GEN_VSX_HELPER_XT_XB_ENV(xscvdpspn, 0x16, 0x10, 0, PPC2_VSX207)
7539 GEN_VSX_HELPER_2(xscvspdp, 0x12, 0x14, 0, PPC2_VSX)
7540 GEN_VSX_HELPER_XT_XB_ENV(xscvspdpn, 0x16, 0x14, 0, PPC2_VSX207)
7541 GEN_VSX_HELPER_2(xscvdpsxds, 0x10, 0x15, 0, PPC2_VSX)
7542 GEN_VSX_HELPER_2(xscvdpsxws, 0x10, 0x05, 0, PPC2_VSX)
7543 GEN_VSX_HELPER_2(xscvdpuxds, 0x10, 0x14, 0, PPC2_VSX)
7544 GEN_VSX_HELPER_2(xscvdpuxws, 0x10, 0x04, 0, PPC2_VSX)
7545 GEN_VSX_HELPER_2(xscvsxddp, 0x10, 0x17, 0, PPC2_VSX)
7546 GEN_VSX_HELPER_2(xscvuxddp, 0x10, 0x16, 0, PPC2_VSX)
7547 GEN_VSX_HELPER_2(xsrdpi, 0x12, 0x04, 0, PPC2_VSX)
7548 GEN_VSX_HELPER_2(xsrdpic, 0x16, 0x06, 0, PPC2_VSX)
7549 GEN_VSX_HELPER_2(xsrdpim, 0x12, 0x07, 0, PPC2_VSX)
7550 GEN_VSX_HELPER_2(xsrdpip, 0x12, 0x06, 0, PPC2_VSX)
7551 GEN_VSX_HELPER_2(xsrdpiz, 0x12, 0x05, 0, PPC2_VSX)
7552 GEN_VSX_HELPER_XT_XB_ENV(xsrsp, 0x12, 0x11, 0, PPC2_VSX207)
7553
7554 GEN_VSX_HELPER_2(xsaddsp, 0x00, 0x00, 0, PPC2_VSX207)
7555 GEN_VSX_HELPER_2(xssubsp, 0x00, 0x01, 0, PPC2_VSX207)
7556 GEN_VSX_HELPER_2(xsmulsp, 0x00, 0x02, 0, PPC2_VSX207)
7557 GEN_VSX_HELPER_2(xsdivsp, 0x00, 0x03, 0, PPC2_VSX207)
7558 GEN_VSX_HELPER_2(xsresp, 0x14, 0x01, 0, PPC2_VSX207)
7559 GEN_VSX_HELPER_2(xssqrtsp, 0x16, 0x00, 0, PPC2_VSX207)
7560 GEN_VSX_HELPER_2(xsrsqrtesp, 0x14, 0x00, 0, PPC2_VSX207)
7561 GEN_VSX_HELPER_2(xsmaddasp, 0x04, 0x00, 0, PPC2_VSX207)
7562 GEN_VSX_HELPER_2(xsmaddmsp, 0x04, 0x01, 0, PPC2_VSX207)
7563 GEN_VSX_HELPER_2(xsmsubasp, 0x04, 0x02, 0, PPC2_VSX207)
7564 GEN_VSX_HELPER_2(xsmsubmsp, 0x04, 0x03, 0, PPC2_VSX207)
7565 GEN_VSX_HELPER_2(xsnmaddasp, 0x04, 0x10, 0, PPC2_VSX207)
7566 GEN_VSX_HELPER_2(xsnmaddmsp, 0x04, 0x11, 0, PPC2_VSX207)
7567 GEN_VSX_HELPER_2(xsnmsubasp, 0x04, 0x12, 0, PPC2_VSX207)
7568 GEN_VSX_HELPER_2(xsnmsubmsp, 0x04, 0x13, 0, PPC2_VSX207)
7569 GEN_VSX_HELPER_2(xscvsxdsp, 0x10, 0x13, 0, PPC2_VSX207)
7570 GEN_VSX_HELPER_2(xscvuxdsp, 0x10, 0x12, 0, PPC2_VSX207)
7571
7572 GEN_VSX_HELPER_2(xvadddp, 0x00, 0x0C, 0, PPC2_VSX)
7573 GEN_VSX_HELPER_2(xvsubdp, 0x00, 0x0D, 0, PPC2_VSX)
7574 GEN_VSX_HELPER_2(xvmuldp, 0x00, 0x0E, 0, PPC2_VSX)
7575 GEN_VSX_HELPER_2(xvdivdp, 0x00, 0x0F, 0, PPC2_VSX)
7576 GEN_VSX_HELPER_2(xvredp, 0x14, 0x0D, 0, PPC2_VSX)
7577 GEN_VSX_HELPER_2(xvsqrtdp, 0x16, 0x0C, 0, PPC2_VSX)
7578 GEN_VSX_HELPER_2(xvrsqrtedp, 0x14, 0x0C, 0, PPC2_VSX)
7579 GEN_VSX_HELPER_2(xvtdivdp, 0x14, 0x0F, 0, PPC2_VSX)
7580 GEN_VSX_HELPER_2(xvtsqrtdp, 0x14, 0x0E, 0, PPC2_VSX)
7581 GEN_VSX_HELPER_2(xvmaddadp, 0x04, 0x0C, 0, PPC2_VSX)
7582 GEN_VSX_HELPER_2(xvmaddmdp, 0x04, 0x0D, 0, PPC2_VSX)
7583 GEN_VSX_HELPER_2(xvmsubadp, 0x04, 0x0E, 0, PPC2_VSX)
7584 GEN_VSX_HELPER_2(xvmsubmdp, 0x04, 0x0F, 0, PPC2_VSX)
7585 GEN_VSX_HELPER_2(xvnmaddadp, 0x04, 0x1C, 0, PPC2_VSX)
7586 GEN_VSX_HELPER_2(xvnmaddmdp, 0x04, 0x1D, 0, PPC2_VSX)
7587 GEN_VSX_HELPER_2(xvnmsubadp, 0x04, 0x1E, 0, PPC2_VSX)
7588 GEN_VSX_HELPER_2(xvnmsubmdp, 0x04, 0x1F, 0, PPC2_VSX)
7589 GEN_VSX_HELPER_2(xvmaxdp, 0x00, 0x1C, 0, PPC2_VSX)
7590 GEN_VSX_HELPER_2(xvmindp, 0x00, 0x1D, 0, PPC2_VSX)
7591 GEN_VSX_HELPER_2(xvcmpeqdp, 0x0C, 0x0C, 0, PPC2_VSX)
7592 GEN_VSX_HELPER_2(xvcmpgtdp, 0x0C, 0x0D, 0, PPC2_VSX)
7593 GEN_VSX_HELPER_2(xvcmpgedp, 0x0C, 0x0E, 0, PPC2_VSX)
7594 GEN_VSX_HELPER_2(xvcvdpsp, 0x12, 0x18, 0, PPC2_VSX)
7595 GEN_VSX_HELPER_2(xvcvdpsxds, 0x10, 0x1D, 0, PPC2_VSX)
7596 GEN_VSX_HELPER_2(xvcvdpsxws, 0x10, 0x0D, 0, PPC2_VSX)
7597 GEN_VSX_HELPER_2(xvcvdpuxds, 0x10, 0x1C, 0, PPC2_VSX)
7598 GEN_VSX_HELPER_2(xvcvdpuxws, 0x10, 0x0C, 0, PPC2_VSX)
7599 GEN_VSX_HELPER_2(xvcvsxddp, 0x10, 0x1F, 0, PPC2_VSX)
7600 GEN_VSX_HELPER_2(xvcvuxddp, 0x10, 0x1E, 0, PPC2_VSX)
7601 GEN_VSX_HELPER_2(xvcvsxwdp, 0x10, 0x0F, 0, PPC2_VSX)
7602 GEN_VSX_HELPER_2(xvcvuxwdp, 0x10, 0x0E, 0, PPC2_VSX)
7603 GEN_VSX_HELPER_2(xvrdpi, 0x12, 0x0C, 0, PPC2_VSX)
7604 GEN_VSX_HELPER_2(xvrdpic, 0x16, 0x0E, 0, PPC2_VSX)
7605 GEN_VSX_HELPER_2(xvrdpim, 0x12, 0x0F, 0, PPC2_VSX)
7606 GEN_VSX_HELPER_2(xvrdpip, 0x12, 0x0E, 0, PPC2_VSX)
7607 GEN_VSX_HELPER_2(xvrdpiz, 0x12, 0x0D, 0, PPC2_VSX)
7608
7609 GEN_VSX_HELPER_2(xvaddsp, 0x00, 0x08, 0, PPC2_VSX)
7610 GEN_VSX_HELPER_2(xvsubsp, 0x00, 0x09, 0, PPC2_VSX)
7611 GEN_VSX_HELPER_2(xvmulsp, 0x00, 0x0A, 0, PPC2_VSX)
7612 GEN_VSX_HELPER_2(xvdivsp, 0x00, 0x0B, 0, PPC2_VSX)
7613 GEN_VSX_HELPER_2(xvresp, 0x14, 0x09, 0, PPC2_VSX)
7614 GEN_VSX_HELPER_2(xvsqrtsp, 0x16, 0x08, 0, PPC2_VSX)
7615 GEN_VSX_HELPER_2(xvrsqrtesp, 0x14, 0x08, 0, PPC2_VSX)
7616 GEN_VSX_HELPER_2(xvtdivsp, 0x14, 0x0B, 0, PPC2_VSX)
7617 GEN_VSX_HELPER_2(xvtsqrtsp, 0x14, 0x0A, 0, PPC2_VSX)
7618 GEN_VSX_HELPER_2(xvmaddasp, 0x04, 0x08, 0, PPC2_VSX)
7619 GEN_VSX_HELPER_2(xvmaddmsp, 0x04, 0x09, 0, PPC2_VSX)
7620 GEN_VSX_HELPER_2(xvmsubasp, 0x04, 0x0A, 0, PPC2_VSX)
7621 GEN_VSX_HELPER_2(xvmsubmsp, 0x04, 0x0B, 0, PPC2_VSX)
7622 GEN_VSX_HELPER_2(xvnmaddasp, 0x04, 0x18, 0, PPC2_VSX)
7623 GEN_VSX_HELPER_2(xvnmaddmsp, 0x04, 0x19, 0, PPC2_VSX)
7624 GEN_VSX_HELPER_2(xvnmsubasp, 0x04, 0x1A, 0, PPC2_VSX)
7625 GEN_VSX_HELPER_2(xvnmsubmsp, 0x04, 0x1B, 0, PPC2_VSX)
7626 GEN_VSX_HELPER_2(xvmaxsp, 0x00, 0x18, 0, PPC2_VSX)
7627 GEN_VSX_HELPER_2(xvminsp, 0x00, 0x19, 0, PPC2_VSX)
7628 GEN_VSX_HELPER_2(xvcmpeqsp, 0x0C, 0x08, 0, PPC2_VSX)
7629 GEN_VSX_HELPER_2(xvcmpgtsp, 0x0C, 0x09, 0, PPC2_VSX)
7630 GEN_VSX_HELPER_2(xvcmpgesp, 0x0C, 0x0A, 0, PPC2_VSX)
7631 GEN_VSX_HELPER_2(xvcvspdp, 0x12, 0x1C, 0, PPC2_VSX)
7632 GEN_VSX_HELPER_2(xvcvspsxds, 0x10, 0x19, 0, PPC2_VSX)
7633 GEN_VSX_HELPER_2(xvcvspsxws, 0x10, 0x09, 0, PPC2_VSX)
7634 GEN_VSX_HELPER_2(xvcvspuxds, 0x10, 0x18, 0, PPC2_VSX)
7635 GEN_VSX_HELPER_2(xvcvspuxws, 0x10, 0x08, 0, PPC2_VSX)
7636 GEN_VSX_HELPER_2(xvcvsxdsp, 0x10, 0x1B, 0, PPC2_VSX)
7637 GEN_VSX_HELPER_2(xvcvuxdsp, 0x10, 0x1A, 0, PPC2_VSX)
7638 GEN_VSX_HELPER_2(xvcvsxwsp, 0x10, 0x0B, 0, PPC2_VSX)
7639 GEN_VSX_HELPER_2(xvcvuxwsp, 0x10, 0x0A, 0, PPC2_VSX)
7640 GEN_VSX_HELPER_2(xvrspi, 0x12, 0x08, 0, PPC2_VSX)
7641 GEN_VSX_HELPER_2(xvrspic, 0x16, 0x0A, 0, PPC2_VSX)
7642 GEN_VSX_HELPER_2(xvrspim, 0x12, 0x0B, 0, PPC2_VSX)
7643 GEN_VSX_HELPER_2(xvrspip, 0x12, 0x0A, 0, PPC2_VSX)
7644 GEN_VSX_HELPER_2(xvrspiz, 0x12, 0x09, 0, PPC2_VSX)
7645
7646 #define VSX_LOGICAL(name, tcg_op) \
7647 static void glue(gen_, name)(DisasContext * ctx) \
7648 { \
7649 if (unlikely(!ctx->vsx_enabled)) { \
7650 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7651 return; \
7652 } \
7653 tcg_op(cpu_vsrh(xT(ctx->opcode)), cpu_vsrh(xA(ctx->opcode)), \
7654 cpu_vsrh(xB(ctx->opcode))); \
7655 tcg_op(cpu_vsrl(xT(ctx->opcode)), cpu_vsrl(xA(ctx->opcode)), \
7656 cpu_vsrl(xB(ctx->opcode))); \
7657 }
7658
7659 VSX_LOGICAL(xxland, tcg_gen_and_i64)
7660 VSX_LOGICAL(xxlandc, tcg_gen_andc_i64)
7661 VSX_LOGICAL(xxlor, tcg_gen_or_i64)
7662 VSX_LOGICAL(xxlxor, tcg_gen_xor_i64)
7663 VSX_LOGICAL(xxlnor, tcg_gen_nor_i64)
7664 VSX_LOGICAL(xxleqv, tcg_gen_eqv_i64)
7665 VSX_LOGICAL(xxlnand, tcg_gen_nand_i64)
7666 VSX_LOGICAL(xxlorc, tcg_gen_orc_i64)
7667
7668 #define VSX_XXMRG(name, high) \
7669 static void glue(gen_, name)(DisasContext * ctx) \
7670 { \
7671 TCGv_i64 a0, a1, b0, b1; \
7672 if (unlikely(!ctx->vsx_enabled)) { \
7673 gen_exception(ctx, POWERPC_EXCP_VSXU); \
7674 return; \
7675 } \
7676 a0 = tcg_temp_new_i64(); \
7677 a1 = tcg_temp_new_i64(); \
7678 b0 = tcg_temp_new_i64(); \
7679 b1 = tcg_temp_new_i64(); \
7680 if (high) { \
7681 tcg_gen_mov_i64(a0, cpu_vsrh(xA(ctx->opcode))); \
7682 tcg_gen_mov_i64(a1, cpu_vsrh(xA(ctx->opcode))); \
7683 tcg_gen_mov_i64(b0, cpu_vsrh(xB(ctx->opcode))); \
7684 tcg_gen_mov_i64(b1, cpu_vsrh(xB(ctx->opcode))); \
7685 } else { \
7686 tcg_gen_mov_i64(a0, cpu_vsrl(xA(ctx->opcode))); \
7687 tcg_gen_mov_i64(a1, cpu_vsrl(xA(ctx->opcode))); \
7688 tcg_gen_mov_i64(b0, cpu_vsrl(xB(ctx->opcode))); \
7689 tcg_gen_mov_i64(b1, cpu_vsrl(xB(ctx->opcode))); \
7690 } \
7691 tcg_gen_shri_i64(a0, a0, 32); \
7692 tcg_gen_shri_i64(b0, b0, 32); \
7693 tcg_gen_deposit_i64(cpu_vsrh(xT(ctx->opcode)), \
7694 b0, a0, 32, 32); \
7695 tcg_gen_deposit_i64(cpu_vsrl(xT(ctx->opcode)), \
7696 b1, a1, 32, 32); \
7697 tcg_temp_free_i64(a0); \
7698 tcg_temp_free_i64(a1); \
7699 tcg_temp_free_i64(b0); \
7700 tcg_temp_free_i64(b1); \
7701 }
7702
7703 VSX_XXMRG(xxmrghw, 1)
7704 VSX_XXMRG(xxmrglw, 0)
7705
7706 static void gen_xxsel(DisasContext * ctx)
7707 {
7708 TCGv_i64 a, b, c;
7709 if (unlikely(!ctx->vsx_enabled)) {
7710 gen_exception(ctx, POWERPC_EXCP_VSXU);
7711 return;
7712 }
7713 a = tcg_temp_new_i64();
7714 b = tcg_temp_new_i64();
7715 c = tcg_temp_new_i64();
7716
7717 tcg_gen_mov_i64(a, cpu_vsrh(xA(ctx->opcode)));
7718 tcg_gen_mov_i64(b, cpu_vsrh(xB(ctx->opcode)));
7719 tcg_gen_mov_i64(c, cpu_vsrh(xC(ctx->opcode)));
7720
7721 tcg_gen_and_i64(b, b, c);
7722 tcg_gen_andc_i64(a, a, c);
7723 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), a, b);
7724
7725 tcg_gen_mov_i64(a, cpu_vsrl(xA(ctx->opcode)));
7726 tcg_gen_mov_i64(b, cpu_vsrl(xB(ctx->opcode)));
7727 tcg_gen_mov_i64(c, cpu_vsrl(xC(ctx->opcode)));
7728
7729 tcg_gen_and_i64(b, b, c);
7730 tcg_gen_andc_i64(a, a, c);
7731 tcg_gen_or_i64(cpu_vsrl(xT(ctx->opcode)), a, b);
7732
7733 tcg_temp_free_i64(a);
7734 tcg_temp_free_i64(b);
7735 tcg_temp_free_i64(c);
7736 }
7737
7738 static void gen_xxspltw(DisasContext *ctx)
7739 {
7740 TCGv_i64 b, b2;
7741 TCGv_i64 vsr = (UIM(ctx->opcode) & 2) ?
7742 cpu_vsrl(xB(ctx->opcode)) :
7743 cpu_vsrh(xB(ctx->opcode));
7744
7745 if (unlikely(!ctx->vsx_enabled)) {
7746 gen_exception(ctx, POWERPC_EXCP_VSXU);
7747 return;
7748 }
7749
7750 b = tcg_temp_new_i64();
7751 b2 = tcg_temp_new_i64();
7752
7753 if (UIM(ctx->opcode) & 1) {
7754 tcg_gen_ext32u_i64(b, vsr);
7755 } else {
7756 tcg_gen_shri_i64(b, vsr, 32);
7757 }
7758
7759 tcg_gen_shli_i64(b2, b, 32);
7760 tcg_gen_or_i64(cpu_vsrh(xT(ctx->opcode)), b, b2);
7761 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), cpu_vsrh(xT(ctx->opcode)));
7762
7763 tcg_temp_free_i64(b);
7764 tcg_temp_free_i64(b2);
7765 }
7766
7767 static void gen_xxsldwi(DisasContext *ctx)
7768 {
7769 TCGv_i64 xth, xtl;
7770 if (unlikely(!ctx->vsx_enabled)) {
7771 gen_exception(ctx, POWERPC_EXCP_VSXU);
7772 return;
7773 }
7774 xth = tcg_temp_new_i64();
7775 xtl = tcg_temp_new_i64();
7776
7777 switch (SHW(ctx->opcode)) {
7778 case 0: {
7779 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
7780 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
7781 break;
7782 }
7783 case 1: {
7784 TCGv_i64 t0 = tcg_temp_new_i64();
7785 tcg_gen_mov_i64(xth, cpu_vsrh(xA(ctx->opcode)));
7786 tcg_gen_shli_i64(xth, xth, 32);
7787 tcg_gen_mov_i64(t0, cpu_vsrl(xA(ctx->opcode)));
7788 tcg_gen_shri_i64(t0, t0, 32);
7789 tcg_gen_or_i64(xth, xth, t0);
7790 tcg_gen_mov_i64(xtl, cpu_vsrl(xA(ctx->opcode)));
7791 tcg_gen_shli_i64(xtl, xtl, 32);
7792 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
7793 tcg_gen_shri_i64(t0, t0, 32);
7794 tcg_gen_or_i64(xtl, xtl, t0);
7795 tcg_temp_free_i64(t0);
7796 break;
7797 }
7798 case 2: {
7799 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
7800 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
7801 break;
7802 }
7803 case 3: {
7804 TCGv_i64 t0 = tcg_temp_new_i64();
7805 tcg_gen_mov_i64(xth, cpu_vsrl(xA(ctx->opcode)));
7806 tcg_gen_shli_i64(xth, xth, 32);
7807 tcg_gen_mov_i64(t0, cpu_vsrh(xB(ctx->opcode)));
7808 tcg_gen_shri_i64(t0, t0, 32);
7809 tcg_gen_or_i64(xth, xth, t0);
7810 tcg_gen_mov_i64(xtl, cpu_vsrh(xB(ctx->opcode)));
7811 tcg_gen_shli_i64(xtl, xtl, 32);
7812 tcg_gen_mov_i64(t0, cpu_vsrl(xB(ctx->opcode)));
7813 tcg_gen_shri_i64(t0, t0, 32);
7814 tcg_gen_or_i64(xtl, xtl, t0);
7815 tcg_temp_free_i64(t0);
7816 break;
7817 }
7818 }
7819
7820 tcg_gen_mov_i64(cpu_vsrh(xT(ctx->opcode)), xth);
7821 tcg_gen_mov_i64(cpu_vsrl(xT(ctx->opcode)), xtl);
7822
7823 tcg_temp_free_i64(xth);
7824 tcg_temp_free_i64(xtl);
7825 }
7826
7827
7828 /*** SPE extension ***/
7829 /* Register moves */
7830
7831 static inline void gen_evmra(DisasContext *ctx)
7832 {
7833
7834 if (unlikely(!ctx->spe_enabled)) {
7835 gen_exception(ctx, POWERPC_EXCP_SPEU);
7836 return;
7837 }
7838
7839 #if defined(TARGET_PPC64)
7840 /* rD := rA */
7841 tcg_gen_mov_i64(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7842
7843 /* spe_acc := rA */
7844 tcg_gen_st_i64(cpu_gpr[rA(ctx->opcode)],
7845 cpu_env,
7846 offsetof(CPUPPCState, spe_acc));
7847 #else
7848 TCGv_i64 tmp = tcg_temp_new_i64();
7849
7850 /* tmp := rA_lo + rA_hi << 32 */
7851 tcg_gen_concat_i32_i64(tmp, cpu_gpr[rA(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7852
7853 /* spe_acc := tmp */
7854 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
7855 tcg_temp_free_i64(tmp);
7856
7857 /* rD := rA */
7858 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
7859 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
7860 #endif
7861 }
7862
7863 static inline void gen_load_gpr64(TCGv_i64 t, int reg)
7864 {
7865 #if defined(TARGET_PPC64)
7866 tcg_gen_mov_i64(t, cpu_gpr[reg]);
7867 #else
7868 tcg_gen_concat_i32_i64(t, cpu_gpr[reg], cpu_gprh[reg]);
7869 #endif
7870 }
7871
7872 static inline void gen_store_gpr64(int reg, TCGv_i64 t)
7873 {
7874 #if defined(TARGET_PPC64)
7875 tcg_gen_mov_i64(cpu_gpr[reg], t);
7876 #else
7877 TCGv_i64 tmp = tcg_temp_new_i64();
7878 tcg_gen_trunc_i64_i32(cpu_gpr[reg], t);
7879 tcg_gen_shri_i64(tmp, t, 32);
7880 tcg_gen_trunc_i64_i32(cpu_gprh[reg], tmp);
7881 tcg_temp_free_i64(tmp);
7882 #endif
7883 }
7884
7885 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
7886 static void glue(gen_, name0##_##name1)(DisasContext *ctx) \
7887 { \
7888 if (Rc(ctx->opcode)) \
7889 gen_##name1(ctx); \
7890 else \
7891 gen_##name0(ctx); \
7892 }
7893
7894 /* Handler for undefined SPE opcodes */
7895 static inline void gen_speundef(DisasContext *ctx)
7896 {
7897 gen_inval_exception(ctx, POWERPC_EXCP_INVAL_INVAL);
7898 }
7899
7900 /* SPE logic */
7901 #if defined(TARGET_PPC64)
7902 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
7903 static inline void gen_##name(DisasContext *ctx) \
7904 { \
7905 if (unlikely(!ctx->spe_enabled)) { \
7906 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7907 return; \
7908 } \
7909 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7910 cpu_gpr[rB(ctx->opcode)]); \
7911 }
7912 #else
7913 #define GEN_SPEOP_LOGIC2(name, tcg_op) \
7914 static inline void gen_##name(DisasContext *ctx) \
7915 { \
7916 if (unlikely(!ctx->spe_enabled)) { \
7917 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7918 return; \
7919 } \
7920 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7921 cpu_gpr[rB(ctx->opcode)]); \
7922 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7923 cpu_gprh[rB(ctx->opcode)]); \
7924 }
7925 #endif
7926
7927 GEN_SPEOP_LOGIC2(evand, tcg_gen_and_tl);
7928 GEN_SPEOP_LOGIC2(evandc, tcg_gen_andc_tl);
7929 GEN_SPEOP_LOGIC2(evxor, tcg_gen_xor_tl);
7930 GEN_SPEOP_LOGIC2(evor, tcg_gen_or_tl);
7931 GEN_SPEOP_LOGIC2(evnor, tcg_gen_nor_tl);
7932 GEN_SPEOP_LOGIC2(eveqv, tcg_gen_eqv_tl);
7933 GEN_SPEOP_LOGIC2(evorc, tcg_gen_orc_tl);
7934 GEN_SPEOP_LOGIC2(evnand, tcg_gen_nand_tl);
7935
7936 /* SPE logic immediate */
7937 #if defined(TARGET_PPC64)
7938 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
7939 static inline void gen_##name(DisasContext *ctx) \
7940 { \
7941 if (unlikely(!ctx->spe_enabled)) { \
7942 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7943 return; \
7944 } \
7945 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7946 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7947 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7948 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7949 tcg_opi(t0, t0, rB(ctx->opcode)); \
7950 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7951 tcg_gen_trunc_i64_i32(t1, t2); \
7952 tcg_temp_free_i64(t2); \
7953 tcg_opi(t1, t1, rB(ctx->opcode)); \
7954 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7955 tcg_temp_free_i32(t0); \
7956 tcg_temp_free_i32(t1); \
7957 }
7958 #else
7959 #define GEN_SPEOP_TCG_LOGIC_IMM2(name, tcg_opi) \
7960 static inline void gen_##name(DisasContext *ctx) \
7961 { \
7962 if (unlikely(!ctx->spe_enabled)) { \
7963 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7964 return; \
7965 } \
7966 tcg_opi(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
7967 rB(ctx->opcode)); \
7968 tcg_opi(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
7969 rB(ctx->opcode)); \
7970 }
7971 #endif
7972 GEN_SPEOP_TCG_LOGIC_IMM2(evslwi, tcg_gen_shli_i32);
7973 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwiu, tcg_gen_shri_i32);
7974 GEN_SPEOP_TCG_LOGIC_IMM2(evsrwis, tcg_gen_sari_i32);
7975 GEN_SPEOP_TCG_LOGIC_IMM2(evrlwi, tcg_gen_rotli_i32);
7976
7977 /* SPE arithmetic */
7978 #if defined(TARGET_PPC64)
7979 #define GEN_SPEOP_ARITH1(name, tcg_op) \
7980 static inline void gen_##name(DisasContext *ctx) \
7981 { \
7982 if (unlikely(!ctx->spe_enabled)) { \
7983 gen_exception(ctx, POWERPC_EXCP_SPEU); \
7984 return; \
7985 } \
7986 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
7987 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
7988 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
7989 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
7990 tcg_op(t0, t0); \
7991 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
7992 tcg_gen_trunc_i64_i32(t1, t2); \
7993 tcg_temp_free_i64(t2); \
7994 tcg_op(t1, t1); \
7995 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
7996 tcg_temp_free_i32(t0); \
7997 tcg_temp_free_i32(t1); \
7998 }
7999 #else
8000 #define GEN_SPEOP_ARITH1(name, tcg_op) \
8001 static inline void gen_##name(DisasContext *ctx) \
8002 { \
8003 if (unlikely(!ctx->spe_enabled)) { \
8004 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8005 return; \
8006 } \
8007 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); \
8008 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]); \
8009 }
8010 #endif
8011
8012 static inline void gen_op_evabs(TCGv_i32 ret, TCGv_i32 arg1)
8013 {
8014 int l1 = gen_new_label();
8015 int l2 = gen_new_label();
8016
8017 tcg_gen_brcondi_i32(TCG_COND_GE, arg1, 0, l1);
8018 tcg_gen_neg_i32(ret, arg1);
8019 tcg_gen_br(l2);
8020 gen_set_label(l1);
8021 tcg_gen_mov_i32(ret, arg1);
8022 gen_set_label(l2);
8023 }
8024 GEN_SPEOP_ARITH1(evabs, gen_op_evabs);
8025 GEN_SPEOP_ARITH1(evneg, tcg_gen_neg_i32);
8026 GEN_SPEOP_ARITH1(evextsb, tcg_gen_ext8s_i32);
8027 GEN_SPEOP_ARITH1(evextsh, tcg_gen_ext16s_i32);
8028 static inline void gen_op_evrndw(TCGv_i32 ret, TCGv_i32 arg1)
8029 {
8030 tcg_gen_addi_i32(ret, arg1, 0x8000);
8031 tcg_gen_ext16u_i32(ret, ret);
8032 }
8033 GEN_SPEOP_ARITH1(evrndw, gen_op_evrndw);
8034 GEN_SPEOP_ARITH1(evcntlsw, gen_helper_cntlsw32);
8035 GEN_SPEOP_ARITH1(evcntlzw, gen_helper_cntlzw32);
8036
8037 #if defined(TARGET_PPC64)
8038 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8039 static inline void gen_##name(DisasContext *ctx) \
8040 { \
8041 if (unlikely(!ctx->spe_enabled)) { \
8042 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8043 return; \
8044 } \
8045 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8046 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8047 TCGv_i32 t2 = tcg_temp_local_new_i32(); \
8048 TCGv_i64 t3 = tcg_temp_local_new_i64(); \
8049 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8050 tcg_gen_trunc_i64_i32(t2, cpu_gpr[rB(ctx->opcode)]); \
8051 tcg_op(t0, t0, t2); \
8052 tcg_gen_shri_i64(t3, cpu_gpr[rA(ctx->opcode)], 32); \
8053 tcg_gen_trunc_i64_i32(t1, t3); \
8054 tcg_gen_shri_i64(t3, cpu_gpr[rB(ctx->opcode)], 32); \
8055 tcg_gen_trunc_i64_i32(t2, t3); \
8056 tcg_temp_free_i64(t3); \
8057 tcg_op(t1, t1, t2); \
8058 tcg_temp_free_i32(t2); \
8059 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
8060 tcg_temp_free_i32(t0); \
8061 tcg_temp_free_i32(t1); \
8062 }
8063 #else
8064 #define GEN_SPEOP_ARITH2(name, tcg_op) \
8065 static inline void gen_##name(DisasContext *ctx) \
8066 { \
8067 if (unlikely(!ctx->spe_enabled)) { \
8068 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8069 return; \
8070 } \
8071 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], \
8072 cpu_gpr[rB(ctx->opcode)]); \
8073 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], \
8074 cpu_gprh[rB(ctx->opcode)]); \
8075 }
8076 #endif
8077
8078 static inline void gen_op_evsrwu(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8079 {
8080 TCGv_i32 t0;
8081 int l1, l2;
8082
8083 l1 = gen_new_label();
8084 l2 = gen_new_label();
8085 t0 = tcg_temp_local_new_i32();
8086 /* No error here: 6 bits are used */
8087 tcg_gen_andi_i32(t0, arg2, 0x3F);
8088 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8089 tcg_gen_shr_i32(ret, arg1, t0);
8090 tcg_gen_br(l2);
8091 gen_set_label(l1);
8092 tcg_gen_movi_i32(ret, 0);
8093 gen_set_label(l2);
8094 tcg_temp_free_i32(t0);
8095 }
8096 GEN_SPEOP_ARITH2(evsrwu, gen_op_evsrwu);
8097 static inline void gen_op_evsrws(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8098 {
8099 TCGv_i32 t0;
8100 int l1, l2;
8101
8102 l1 = gen_new_label();
8103 l2 = gen_new_label();
8104 t0 = tcg_temp_local_new_i32();
8105 /* No error here: 6 bits are used */
8106 tcg_gen_andi_i32(t0, arg2, 0x3F);
8107 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8108 tcg_gen_sar_i32(ret, arg1, t0);
8109 tcg_gen_br(l2);
8110 gen_set_label(l1);
8111 tcg_gen_movi_i32(ret, 0);
8112 gen_set_label(l2);
8113 tcg_temp_free_i32(t0);
8114 }
8115 GEN_SPEOP_ARITH2(evsrws, gen_op_evsrws);
8116 static inline void gen_op_evslw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8117 {
8118 TCGv_i32 t0;
8119 int l1, l2;
8120
8121 l1 = gen_new_label();
8122 l2 = gen_new_label();
8123 t0 = tcg_temp_local_new_i32();
8124 /* No error here: 6 bits are used */
8125 tcg_gen_andi_i32(t0, arg2, 0x3F);
8126 tcg_gen_brcondi_i32(TCG_COND_GE, t0, 32, l1);
8127 tcg_gen_shl_i32(ret, arg1, t0);
8128 tcg_gen_br(l2);
8129 gen_set_label(l1);
8130 tcg_gen_movi_i32(ret, 0);
8131 gen_set_label(l2);
8132 tcg_temp_free_i32(t0);
8133 }
8134 GEN_SPEOP_ARITH2(evslw, gen_op_evslw);
8135 static inline void gen_op_evrlw(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8136 {
8137 TCGv_i32 t0 = tcg_temp_new_i32();
8138 tcg_gen_andi_i32(t0, arg2, 0x1F);
8139 tcg_gen_rotl_i32(ret, arg1, t0);
8140 tcg_temp_free_i32(t0);
8141 }
8142 GEN_SPEOP_ARITH2(evrlw, gen_op_evrlw);
8143 static inline void gen_evmergehi(DisasContext *ctx)
8144 {
8145 if (unlikely(!ctx->spe_enabled)) {
8146 gen_exception(ctx, POWERPC_EXCP_SPEU);
8147 return;
8148 }
8149 #if defined(TARGET_PPC64)
8150 TCGv t0 = tcg_temp_new();
8151 TCGv t1 = tcg_temp_new();
8152 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
8153 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
8154 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8155 tcg_temp_free(t0);
8156 tcg_temp_free(t1);
8157 #else
8158 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8159 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8160 #endif
8161 }
8162 GEN_SPEOP_ARITH2(evaddw, tcg_gen_add_i32);
8163 static inline void gen_op_evsubf(TCGv_i32 ret, TCGv_i32 arg1, TCGv_i32 arg2)
8164 {
8165 tcg_gen_sub_i32(ret, arg2, arg1);
8166 }
8167 GEN_SPEOP_ARITH2(evsubfw, gen_op_evsubf);
8168
8169 /* SPE arithmetic immediate */
8170 #if defined(TARGET_PPC64)
8171 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8172 static inline void gen_##name(DisasContext *ctx) \
8173 { \
8174 if (unlikely(!ctx->spe_enabled)) { \
8175 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8176 return; \
8177 } \
8178 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8179 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8180 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
8181 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
8182 tcg_op(t0, t0, rA(ctx->opcode)); \
8183 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
8184 tcg_gen_trunc_i64_i32(t1, t2); \
8185 tcg_temp_free_i64(t2); \
8186 tcg_op(t1, t1, rA(ctx->opcode)); \
8187 tcg_gen_concat_i32_i64(cpu_gpr[rD(ctx->opcode)], t0, t1); \
8188 tcg_temp_free_i32(t0); \
8189 tcg_temp_free_i32(t1); \
8190 }
8191 #else
8192 #define GEN_SPEOP_ARITH_IMM2(name, tcg_op) \
8193 static inline void gen_##name(DisasContext *ctx) \
8194 { \
8195 if (unlikely(!ctx->spe_enabled)) { \
8196 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8197 return; \
8198 } \
8199 tcg_op(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)], \
8200 rA(ctx->opcode)); \
8201 tcg_op(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)], \
8202 rA(ctx->opcode)); \
8203 }
8204 #endif
8205 GEN_SPEOP_ARITH_IMM2(evaddiw, tcg_gen_addi_i32);
8206 GEN_SPEOP_ARITH_IMM2(evsubifw, tcg_gen_subi_i32);
8207
8208 /* SPE comparison */
8209 #if defined(TARGET_PPC64)
8210 #define GEN_SPEOP_COMP(name, tcg_cond) \
8211 static inline void gen_##name(DisasContext *ctx) \
8212 { \
8213 if (unlikely(!ctx->spe_enabled)) { \
8214 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8215 return; \
8216 } \
8217 int l1 = gen_new_label(); \
8218 int l2 = gen_new_label(); \
8219 int l3 = gen_new_label(); \
8220 int l4 = gen_new_label(); \
8221 TCGv_i32 t0 = tcg_temp_local_new_i32(); \
8222 TCGv_i32 t1 = tcg_temp_local_new_i32(); \
8223 TCGv_i64 t2 = tcg_temp_local_new_i64(); \
8224 tcg_gen_trunc_i64_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
8225 tcg_gen_trunc_i64_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
8226 tcg_gen_brcond_i32(tcg_cond, t0, t1, l1); \
8227 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], 0); \
8228 tcg_gen_br(l2); \
8229 gen_set_label(l1); \
8230 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8231 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8232 gen_set_label(l2); \
8233 tcg_gen_shri_i64(t2, cpu_gpr[rA(ctx->opcode)], 32); \
8234 tcg_gen_trunc_i64_i32(t0, t2); \
8235 tcg_gen_shri_i64(t2, cpu_gpr[rB(ctx->opcode)], 32); \
8236 tcg_gen_trunc_i64_i32(t1, t2); \
8237 tcg_temp_free_i64(t2); \
8238 tcg_gen_brcond_i32(tcg_cond, t0, t1, l3); \
8239 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8240 ~(CRF_CH | CRF_CH_AND_CL)); \
8241 tcg_gen_br(l4); \
8242 gen_set_label(l3); \
8243 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8244 CRF_CH | CRF_CH_OR_CL); \
8245 gen_set_label(l4); \
8246 tcg_temp_free_i32(t0); \
8247 tcg_temp_free_i32(t1); \
8248 }
8249 #else
8250 #define GEN_SPEOP_COMP(name, tcg_cond) \
8251 static inline void gen_##name(DisasContext *ctx) \
8252 { \
8253 if (unlikely(!ctx->spe_enabled)) { \
8254 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8255 return; \
8256 } \
8257 int l1 = gen_new_label(); \
8258 int l2 = gen_new_label(); \
8259 int l3 = gen_new_label(); \
8260 int l4 = gen_new_label(); \
8261 \
8262 tcg_gen_brcond_i32(tcg_cond, cpu_gpr[rA(ctx->opcode)], \
8263 cpu_gpr[rB(ctx->opcode)], l1); \
8264 tcg_gen_movi_tl(cpu_crf[crfD(ctx->opcode)], 0); \
8265 tcg_gen_br(l2); \
8266 gen_set_label(l1); \
8267 tcg_gen_movi_i32(cpu_crf[crfD(ctx->opcode)], \
8268 CRF_CL | CRF_CH_OR_CL | CRF_CH_AND_CL); \
8269 gen_set_label(l2); \
8270 tcg_gen_brcond_i32(tcg_cond, cpu_gprh[rA(ctx->opcode)], \
8271 cpu_gprh[rB(ctx->opcode)], l3); \
8272 tcg_gen_andi_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8273 ~(CRF_CH | CRF_CH_AND_CL)); \
8274 tcg_gen_br(l4); \
8275 gen_set_label(l3); \
8276 tcg_gen_ori_i32(cpu_crf[crfD(ctx->opcode)], cpu_crf[crfD(ctx->opcode)], \
8277 CRF_CH | CRF_CH_OR_CL); \
8278 gen_set_label(l4); \
8279 }
8280 #endif
8281 GEN_SPEOP_COMP(evcmpgtu, TCG_COND_GTU);
8282 GEN_SPEOP_COMP(evcmpgts, TCG_COND_GT);
8283 GEN_SPEOP_COMP(evcmpltu, TCG_COND_LTU);
8284 GEN_SPEOP_COMP(evcmplts, TCG_COND_LT);
8285 GEN_SPEOP_COMP(evcmpeq, TCG_COND_EQ);
8286
8287 /* SPE misc */
8288 static inline void gen_brinc(DisasContext *ctx)
8289 {
8290 /* Note: brinc is usable even if SPE is disabled */
8291 gen_helper_brinc(cpu_gpr[rD(ctx->opcode)],
8292 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8293 }
8294 static inline void gen_evmergelo(DisasContext *ctx)
8295 {
8296 if (unlikely(!ctx->spe_enabled)) {
8297 gen_exception(ctx, POWERPC_EXCP_SPEU);
8298 return;
8299 }
8300 #if defined(TARGET_PPC64)
8301 TCGv t0 = tcg_temp_new();
8302 TCGv t1 = tcg_temp_new();
8303 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
8304 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
8305 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8306 tcg_temp_free(t0);
8307 tcg_temp_free(t1);
8308 #else
8309 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8310 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8311 #endif
8312 }
8313 static inline void gen_evmergehilo(DisasContext *ctx)
8314 {
8315 if (unlikely(!ctx->spe_enabled)) {
8316 gen_exception(ctx, POWERPC_EXCP_SPEU);
8317 return;
8318 }
8319 #if defined(TARGET_PPC64)
8320 TCGv t0 = tcg_temp_new();
8321 TCGv t1 = tcg_temp_new();
8322 tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]);
8323 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL);
8324 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8325 tcg_temp_free(t0);
8326 tcg_temp_free(t1);
8327 #else
8328 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8329 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8330 #endif
8331 }
8332 static inline void gen_evmergelohi(DisasContext *ctx)
8333 {
8334 if (unlikely(!ctx->spe_enabled)) {
8335 gen_exception(ctx, POWERPC_EXCP_SPEU);
8336 return;
8337 }
8338 #if defined(TARGET_PPC64)
8339 TCGv t0 = tcg_temp_new();
8340 TCGv t1 = tcg_temp_new();
8341 tcg_gen_shri_tl(t0, cpu_gpr[rB(ctx->opcode)], 32);
8342 tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32);
8343 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1);
8344 tcg_temp_free(t0);
8345 tcg_temp_free(t1);
8346 #else
8347 if (rD(ctx->opcode) == rA(ctx->opcode)) {
8348 TCGv_i32 tmp = tcg_temp_new_i32();
8349 tcg_gen_mov_i32(tmp, cpu_gpr[rA(ctx->opcode)]);
8350 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8351 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], tmp);
8352 tcg_temp_free_i32(tmp);
8353 } else {
8354 tcg_gen_mov_i32(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8355 tcg_gen_mov_i32(cpu_gprh[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8356 }
8357 #endif
8358 }
8359 static inline void gen_evsplati(DisasContext *ctx)
8360 {
8361 uint64_t imm = ((int32_t)(rA(ctx->opcode) << 27)) >> 27;
8362
8363 #if defined(TARGET_PPC64)
8364 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
8365 #else
8366 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
8367 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
8368 #endif
8369 }
8370 static inline void gen_evsplatfi(DisasContext *ctx)
8371 {
8372 uint64_t imm = rA(ctx->opcode) << 27;
8373
8374 #if defined(TARGET_PPC64)
8375 tcg_gen_movi_tl(cpu_gpr[rD(ctx->opcode)], (imm << 32) | imm);
8376 #else
8377 tcg_gen_movi_i32(cpu_gpr[rD(ctx->opcode)], imm);
8378 tcg_gen_movi_i32(cpu_gprh[rD(ctx->opcode)], imm);
8379 #endif
8380 }
8381
8382 static inline void gen_evsel(DisasContext *ctx)
8383 {
8384 int l1 = gen_new_label();
8385 int l2 = gen_new_label();
8386 int l3 = gen_new_label();
8387 int l4 = gen_new_label();
8388 TCGv_i32 t0 = tcg_temp_local_new_i32();
8389 #if defined(TARGET_PPC64)
8390 TCGv t1 = tcg_temp_local_new();
8391 TCGv t2 = tcg_temp_local_new();
8392 #endif
8393 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 3);
8394 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l1);
8395 #if defined(TARGET_PPC64)
8396 tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF00000000ULL);
8397 #else
8398 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)]);
8399 #endif
8400 tcg_gen_br(l2);
8401 gen_set_label(l1);
8402 #if defined(TARGET_PPC64)
8403 tcg_gen_andi_tl(t1, cpu_gpr[rB(ctx->opcode)], 0xFFFFFFFF00000000ULL);
8404 #else
8405 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rB(ctx->opcode)]);
8406 #endif
8407 gen_set_label(l2);
8408 tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2);
8409 tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3);
8410 #if defined(TARGET_PPC64)
8411 tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]);
8412 #else
8413 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
8414 #endif
8415 tcg_gen_br(l4);
8416 gen_set_label(l3);
8417 #if defined(TARGET_PPC64)
8418 tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]);
8419 #else
8420 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]);
8421 #endif
8422 gen_set_label(l4);
8423 tcg_temp_free_i32(t0);
8424 #if defined(TARGET_PPC64)
8425 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t1, t2);
8426 tcg_temp_free(t1);
8427 tcg_temp_free(t2);
8428 #endif
8429 }
8430
8431 static void gen_evsel0(DisasContext *ctx)
8432 {
8433 gen_evsel(ctx);
8434 }
8435
8436 static void gen_evsel1(DisasContext *ctx)
8437 {
8438 gen_evsel(ctx);
8439 }
8440
8441 static void gen_evsel2(DisasContext *ctx)
8442 {
8443 gen_evsel(ctx);
8444 }
8445
8446 static void gen_evsel3(DisasContext *ctx)
8447 {
8448 gen_evsel(ctx);
8449 }
8450
8451 /* Multiply */
8452
8453 static inline void gen_evmwumi(DisasContext *ctx)
8454 {
8455 TCGv_i64 t0, t1;
8456
8457 if (unlikely(!ctx->spe_enabled)) {
8458 gen_exception(ctx, POWERPC_EXCP_SPEU);
8459 return;
8460 }
8461
8462 t0 = tcg_temp_new_i64();
8463 t1 = tcg_temp_new_i64();
8464
8465 /* t0 := rA; t1 := rB */
8466 #if defined(TARGET_PPC64)
8467 tcg_gen_ext32u_tl(t0, cpu_gpr[rA(ctx->opcode)]);
8468 tcg_gen_ext32u_tl(t1, cpu_gpr[rB(ctx->opcode)]);
8469 #else
8470 tcg_gen_extu_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8471 tcg_gen_extu_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8472 #endif
8473
8474 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8475
8476 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8477
8478 tcg_temp_free_i64(t0);
8479 tcg_temp_free_i64(t1);
8480 }
8481
8482 static inline void gen_evmwumia(DisasContext *ctx)
8483 {
8484 TCGv_i64 tmp;
8485
8486 if (unlikely(!ctx->spe_enabled)) {
8487 gen_exception(ctx, POWERPC_EXCP_SPEU);
8488 return;
8489 }
8490
8491 gen_evmwumi(ctx); /* rD := rA * rB */
8492
8493 tmp = tcg_temp_new_i64();
8494
8495 /* acc := rD */
8496 gen_load_gpr64(tmp, rD(ctx->opcode));
8497 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8498 tcg_temp_free_i64(tmp);
8499 }
8500
8501 static inline void gen_evmwumiaa(DisasContext *ctx)
8502 {
8503 TCGv_i64 acc;
8504 TCGv_i64 tmp;
8505
8506 if (unlikely(!ctx->spe_enabled)) {
8507 gen_exception(ctx, POWERPC_EXCP_SPEU);
8508 return;
8509 }
8510
8511 gen_evmwumi(ctx); /* rD := rA * rB */
8512
8513 acc = tcg_temp_new_i64();
8514 tmp = tcg_temp_new_i64();
8515
8516 /* tmp := rD */
8517 gen_load_gpr64(tmp, rD(ctx->opcode));
8518
8519 /* Load acc */
8520 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8521
8522 /* acc := tmp + acc */
8523 tcg_gen_add_i64(acc, acc, tmp);
8524
8525 /* Store acc */
8526 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8527
8528 /* rD := acc */
8529 gen_store_gpr64(rD(ctx->opcode), acc);
8530
8531 tcg_temp_free_i64(acc);
8532 tcg_temp_free_i64(tmp);
8533 }
8534
8535 static inline void gen_evmwsmi(DisasContext *ctx)
8536 {
8537 TCGv_i64 t0, t1;
8538
8539 if (unlikely(!ctx->spe_enabled)) {
8540 gen_exception(ctx, POWERPC_EXCP_SPEU);
8541 return;
8542 }
8543
8544 t0 = tcg_temp_new_i64();
8545 t1 = tcg_temp_new_i64();
8546
8547 /* t0 := rA; t1 := rB */
8548 #if defined(TARGET_PPC64)
8549 tcg_gen_ext32s_tl(t0, cpu_gpr[rA(ctx->opcode)]);
8550 tcg_gen_ext32s_tl(t1, cpu_gpr[rB(ctx->opcode)]);
8551 #else
8552 tcg_gen_ext_tl_i64(t0, cpu_gpr[rA(ctx->opcode)]);
8553 tcg_gen_ext_tl_i64(t1, cpu_gpr[rB(ctx->opcode)]);
8554 #endif
8555
8556 tcg_gen_mul_i64(t0, t0, t1); /* t0 := rA * rB */
8557
8558 gen_store_gpr64(rD(ctx->opcode), t0); /* rD := t0 */
8559
8560 tcg_temp_free_i64(t0);
8561 tcg_temp_free_i64(t1);
8562 }
8563
8564 static inline void gen_evmwsmia(DisasContext *ctx)
8565 {
8566 TCGv_i64 tmp;
8567
8568 gen_evmwsmi(ctx); /* rD := rA * rB */
8569
8570 tmp = tcg_temp_new_i64();
8571
8572 /* acc := rD */
8573 gen_load_gpr64(tmp, rD(ctx->opcode));
8574 tcg_gen_st_i64(tmp, cpu_env, offsetof(CPUPPCState, spe_acc));
8575
8576 tcg_temp_free_i64(tmp);
8577 }
8578
8579 static inline void gen_evmwsmiaa(DisasContext *ctx)
8580 {
8581 TCGv_i64 acc = tcg_temp_new_i64();
8582 TCGv_i64 tmp = tcg_temp_new_i64();
8583
8584 gen_evmwsmi(ctx); /* rD := rA * rB */
8585
8586 acc = tcg_temp_new_i64();
8587 tmp = tcg_temp_new_i64();
8588
8589 /* tmp := rD */
8590 gen_load_gpr64(tmp, rD(ctx->opcode));
8591
8592 /* Load acc */
8593 tcg_gen_ld_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8594
8595 /* acc := tmp + acc */
8596 tcg_gen_add_i64(acc, acc, tmp);
8597
8598 /* Store acc */
8599 tcg_gen_st_i64(acc, cpu_env, offsetof(CPUPPCState, spe_acc));
8600
8601 /* rD := acc */
8602 gen_store_gpr64(rD(ctx->opcode), acc);
8603
8604 tcg_temp_free_i64(acc);
8605 tcg_temp_free_i64(tmp);
8606 }
8607
8608 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8609 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8610 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8611 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8612 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8613 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8614 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE); ////
8615 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE); //
8616 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE);
8617 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
8618 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8619 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8620 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8621 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8622 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE);
8623 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE);
8624 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE); ////
8625 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8626 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8627 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE);
8628 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE); ////
8629 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE);
8630 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE); //
8631 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE);
8632 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8633 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE); ////
8634 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
8635 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE); ////
8636 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE); ////
8637
8638 /* SPE load and stores */
8639 static inline void gen_addr_spe_imm_index(DisasContext *ctx, TCGv EA, int sh)
8640 {
8641 target_ulong uimm = rB(ctx->opcode);
8642
8643 if (rA(ctx->opcode) == 0) {
8644 tcg_gen_movi_tl(EA, uimm << sh);
8645 } else {
8646 tcg_gen_addi_tl(EA, cpu_gpr[rA(ctx->opcode)], uimm << sh);
8647 if (NARROW_MODE(ctx)) {
8648 tcg_gen_ext32u_tl(EA, EA);
8649 }
8650 }
8651 }
8652
8653 static inline void gen_op_evldd(DisasContext *ctx, TCGv addr)
8654 {
8655 #if defined(TARGET_PPC64)
8656 gen_qemu_ld64(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8657 #else
8658 TCGv_i64 t0 = tcg_temp_new_i64();
8659 gen_qemu_ld64(ctx, t0, addr);
8660 tcg_gen_trunc_i64_i32(cpu_gpr[rD(ctx->opcode)], t0);
8661 tcg_gen_shri_i64(t0, t0, 32);
8662 tcg_gen_trunc_i64_i32(cpu_gprh[rD(ctx->opcode)], t0);
8663 tcg_temp_free_i64(t0);
8664 #endif
8665 }
8666
8667 static inline void gen_op_evldw(DisasContext *ctx, TCGv addr)
8668 {
8669 #if defined(TARGET_PPC64)
8670 TCGv t0 = tcg_temp_new();
8671 gen_qemu_ld32u(ctx, t0, addr);
8672 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
8673 gen_addr_add(ctx, addr, addr, 4);
8674 gen_qemu_ld32u(ctx, t0, addr);
8675 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8676 tcg_temp_free(t0);
8677 #else
8678 gen_qemu_ld32u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
8679 gen_addr_add(ctx, addr, addr, 4);
8680 gen_qemu_ld32u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8681 #endif
8682 }
8683
8684 static inline void gen_op_evldh(DisasContext *ctx, TCGv addr)
8685 {
8686 TCGv t0 = tcg_temp_new();
8687 #if defined(TARGET_PPC64)
8688 gen_qemu_ld16u(ctx, t0, addr);
8689 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
8690 gen_addr_add(ctx, addr, addr, 2);
8691 gen_qemu_ld16u(ctx, t0, addr);
8692 tcg_gen_shli_tl(t0, t0, 32);
8693 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8694 gen_addr_add(ctx, addr, addr, 2);
8695 gen_qemu_ld16u(ctx, t0, addr);
8696 tcg_gen_shli_tl(t0, t0, 16);
8697 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8698 gen_addr_add(ctx, addr, addr, 2);
8699 gen_qemu_ld16u(ctx, t0, addr);
8700 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8701 #else
8702 gen_qemu_ld16u(ctx, t0, addr);
8703 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
8704 gen_addr_add(ctx, addr, addr, 2);
8705 gen_qemu_ld16u(ctx, t0, addr);
8706 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
8707 gen_addr_add(ctx, addr, addr, 2);
8708 gen_qemu_ld16u(ctx, t0, addr);
8709 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
8710 gen_addr_add(ctx, addr, addr, 2);
8711 gen_qemu_ld16u(ctx, t0, addr);
8712 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8713 #endif
8714 tcg_temp_free(t0);
8715 }
8716
8717 static inline void gen_op_evlhhesplat(DisasContext *ctx, TCGv addr)
8718 {
8719 TCGv t0 = tcg_temp_new();
8720 gen_qemu_ld16u(ctx, t0, addr);
8721 #if defined(TARGET_PPC64)
8722 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
8723 tcg_gen_shli_tl(t0, t0, 16);
8724 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8725 #else
8726 tcg_gen_shli_tl(t0, t0, 16);
8727 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
8728 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
8729 #endif
8730 tcg_temp_free(t0);
8731 }
8732
8733 static inline void gen_op_evlhhousplat(DisasContext *ctx, TCGv addr)
8734 {
8735 TCGv t0 = tcg_temp_new();
8736 gen_qemu_ld16u(ctx, t0, addr);
8737 #if defined(TARGET_PPC64)
8738 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
8739 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8740 #else
8741 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
8742 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
8743 #endif
8744 tcg_temp_free(t0);
8745 }
8746
8747 static inline void gen_op_evlhhossplat(DisasContext *ctx, TCGv addr)
8748 {
8749 TCGv t0 = tcg_temp_new();
8750 gen_qemu_ld16s(ctx, t0, addr);
8751 #if defined(TARGET_PPC64)
8752 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
8753 tcg_gen_ext32u_tl(t0, t0);
8754 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8755 #else
8756 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
8757 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
8758 #endif
8759 tcg_temp_free(t0);
8760 }
8761
8762 static inline void gen_op_evlwhe(DisasContext *ctx, TCGv addr)
8763 {
8764 TCGv t0 = tcg_temp_new();
8765 #if defined(TARGET_PPC64)
8766 gen_qemu_ld16u(ctx, t0, addr);
8767 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
8768 gen_addr_add(ctx, addr, addr, 2);
8769 gen_qemu_ld16u(ctx, t0, addr);
8770 tcg_gen_shli_tl(t0, t0, 16);
8771 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8772 #else
8773 gen_qemu_ld16u(ctx, t0, addr);
8774 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
8775 gen_addr_add(ctx, addr, addr, 2);
8776 gen_qemu_ld16u(ctx, t0, addr);
8777 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
8778 #endif
8779 tcg_temp_free(t0);
8780 }
8781
8782 static inline void gen_op_evlwhou(DisasContext *ctx, TCGv addr)
8783 {
8784 #if defined(TARGET_PPC64)
8785 TCGv t0 = tcg_temp_new();
8786 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8787 gen_addr_add(ctx, addr, addr, 2);
8788 gen_qemu_ld16u(ctx, t0, addr);
8789 tcg_gen_shli_tl(t0, t0, 32);
8790 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8791 tcg_temp_free(t0);
8792 #else
8793 gen_qemu_ld16u(ctx, cpu_gprh[rD(ctx->opcode)], addr);
8794 gen_addr_add(ctx, addr, addr, 2);
8795 gen_qemu_ld16u(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8796 #endif
8797 }
8798
8799 static inline void gen_op_evlwhos(DisasContext *ctx, TCGv addr)
8800 {
8801 #if defined(TARGET_PPC64)
8802 TCGv t0 = tcg_temp_new();
8803 gen_qemu_ld16s(ctx, t0, addr);
8804 tcg_gen_ext32u_tl(cpu_gpr[rD(ctx->opcode)], t0);
8805 gen_addr_add(ctx, addr, addr, 2);
8806 gen_qemu_ld16s(ctx, t0, addr);
8807 tcg_gen_shli_tl(t0, t0, 32);
8808 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8809 tcg_temp_free(t0);
8810 #else
8811 gen_qemu_ld16s(ctx, cpu_gprh[rD(ctx->opcode)], addr);
8812 gen_addr_add(ctx, addr, addr, 2);
8813 gen_qemu_ld16s(ctx, cpu_gpr[rD(ctx->opcode)], addr);
8814 #endif
8815 }
8816
8817 static inline void gen_op_evlwwsplat(DisasContext *ctx, TCGv addr)
8818 {
8819 TCGv t0 = tcg_temp_new();
8820 gen_qemu_ld32u(ctx, t0, addr);
8821 #if defined(TARGET_PPC64)
8822 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 32);
8823 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8824 #else
8825 tcg_gen_mov_tl(cpu_gprh[rD(ctx->opcode)], t0);
8826 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], t0);
8827 #endif
8828 tcg_temp_free(t0);
8829 }
8830
8831 static inline void gen_op_evlwhsplat(DisasContext *ctx, TCGv addr)
8832 {
8833 TCGv t0 = tcg_temp_new();
8834 #if defined(TARGET_PPC64)
8835 gen_qemu_ld16u(ctx, t0, addr);
8836 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 48);
8837 tcg_gen_shli_tl(t0, t0, 32);
8838 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8839 gen_addr_add(ctx, addr, addr, 2);
8840 gen_qemu_ld16u(ctx, t0, addr);
8841 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8842 tcg_gen_shli_tl(t0, t0, 16);
8843 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t0);
8844 #else
8845 gen_qemu_ld16u(ctx, t0, addr);
8846 tcg_gen_shli_tl(cpu_gprh[rD(ctx->opcode)], t0, 16);
8847 tcg_gen_or_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
8848 gen_addr_add(ctx, addr, addr, 2);
8849 gen_qemu_ld16u(ctx, t0, addr);
8850 tcg_gen_shli_tl(cpu_gpr[rD(ctx->opcode)], t0, 16);
8851 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gprh[rD(ctx->opcode)], t0);
8852 #endif
8853 tcg_temp_free(t0);
8854 }
8855
8856 static inline void gen_op_evstdd(DisasContext *ctx, TCGv addr)
8857 {
8858 #if defined(TARGET_PPC64)
8859 gen_qemu_st64(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8860 #else
8861 TCGv_i64 t0 = tcg_temp_new_i64();
8862 tcg_gen_concat_i32_i64(t0, cpu_gpr[rS(ctx->opcode)], cpu_gprh[rS(ctx->opcode)]);
8863 gen_qemu_st64(ctx, t0, addr);
8864 tcg_temp_free_i64(t0);
8865 #endif
8866 }
8867
8868 static inline void gen_op_evstdw(DisasContext *ctx, TCGv addr)
8869 {
8870 #if defined(TARGET_PPC64)
8871 TCGv t0 = tcg_temp_new();
8872 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8873 gen_qemu_st32(ctx, t0, addr);
8874 tcg_temp_free(t0);
8875 #else
8876 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8877 #endif
8878 gen_addr_add(ctx, addr, addr, 4);
8879 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8880 }
8881
8882 static inline void gen_op_evstdh(DisasContext *ctx, TCGv addr)
8883 {
8884 TCGv t0 = tcg_temp_new();
8885 #if defined(TARGET_PPC64)
8886 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
8887 #else
8888 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
8889 #endif
8890 gen_qemu_st16(ctx, t0, addr);
8891 gen_addr_add(ctx, addr, addr, 2);
8892 #if defined(TARGET_PPC64)
8893 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8894 gen_qemu_st16(ctx, t0, addr);
8895 #else
8896 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8897 #endif
8898 gen_addr_add(ctx, addr, addr, 2);
8899 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
8900 gen_qemu_st16(ctx, t0, addr);
8901 tcg_temp_free(t0);
8902 gen_addr_add(ctx, addr, addr, 2);
8903 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8904 }
8905
8906 static inline void gen_op_evstwhe(DisasContext *ctx, TCGv addr)
8907 {
8908 TCGv t0 = tcg_temp_new();
8909 #if defined(TARGET_PPC64)
8910 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 48);
8911 #else
8912 tcg_gen_shri_tl(t0, cpu_gprh[rS(ctx->opcode)], 16);
8913 #endif
8914 gen_qemu_st16(ctx, t0, addr);
8915 gen_addr_add(ctx, addr, addr, 2);
8916 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 16);
8917 gen_qemu_st16(ctx, t0, addr);
8918 tcg_temp_free(t0);
8919 }
8920
8921 static inline void gen_op_evstwho(DisasContext *ctx, TCGv addr)
8922 {
8923 #if defined(TARGET_PPC64)
8924 TCGv t0 = tcg_temp_new();
8925 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8926 gen_qemu_st16(ctx, t0, addr);
8927 tcg_temp_free(t0);
8928 #else
8929 gen_qemu_st16(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8930 #endif
8931 gen_addr_add(ctx, addr, addr, 2);
8932 gen_qemu_st16(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8933 }
8934
8935 static inline void gen_op_evstwwe(DisasContext *ctx, TCGv addr)
8936 {
8937 #if defined(TARGET_PPC64)
8938 TCGv t0 = tcg_temp_new();
8939 tcg_gen_shri_tl(t0, cpu_gpr[rS(ctx->opcode)], 32);
8940 gen_qemu_st32(ctx, t0, addr);
8941 tcg_temp_free(t0);
8942 #else
8943 gen_qemu_st32(ctx, cpu_gprh[rS(ctx->opcode)], addr);
8944 #endif
8945 }
8946
8947 static inline void gen_op_evstwwo(DisasContext *ctx, TCGv addr)
8948 {
8949 gen_qemu_st32(ctx, cpu_gpr[rS(ctx->opcode)], addr);
8950 }
8951
8952 #define GEN_SPEOP_LDST(name, opc2, sh) \
8953 static void glue(gen_, name)(DisasContext *ctx) \
8954 { \
8955 TCGv t0; \
8956 if (unlikely(!ctx->spe_enabled)) { \
8957 gen_exception(ctx, POWERPC_EXCP_SPEU); \
8958 return; \
8959 } \
8960 gen_set_access_type(ctx, ACCESS_INT); \
8961 t0 = tcg_temp_new(); \
8962 if (Rc(ctx->opcode)) { \
8963 gen_addr_spe_imm_index(ctx, t0, sh); \
8964 } else { \
8965 gen_addr_reg_index(ctx, t0); \
8966 } \
8967 gen_op_##name(ctx, t0); \
8968 tcg_temp_free(t0); \
8969 }
8970
8971 GEN_SPEOP_LDST(evldd, 0x00, 3);
8972 GEN_SPEOP_LDST(evldw, 0x01, 3);
8973 GEN_SPEOP_LDST(evldh, 0x02, 3);
8974 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1);
8975 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1);
8976 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1);
8977 GEN_SPEOP_LDST(evlwhe, 0x08, 2);
8978 GEN_SPEOP_LDST(evlwhou, 0x0A, 2);
8979 GEN_SPEOP_LDST(evlwhos, 0x0B, 2);
8980 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2);
8981 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2);
8982
8983 GEN_SPEOP_LDST(evstdd, 0x10, 3);
8984 GEN_SPEOP_LDST(evstdw, 0x11, 3);
8985 GEN_SPEOP_LDST(evstdh, 0x12, 3);
8986 GEN_SPEOP_LDST(evstwhe, 0x18, 2);
8987 GEN_SPEOP_LDST(evstwho, 0x1A, 2);
8988 GEN_SPEOP_LDST(evstwwe, 0x1C, 2);
8989 GEN_SPEOP_LDST(evstwwo, 0x1E, 2);
8990
8991 /* Multiply and add - TODO */
8992 #if 0
8993 GEN_SPE(speundef, evmhessf, 0x01, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);//
8994 GEN_SPE(speundef, evmhossf, 0x03, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8995 GEN_SPE(evmheumi, evmhesmi, 0x04, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8996 GEN_SPE(speundef, evmhesmf, 0x05, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8997 GEN_SPE(evmhoumi, evmhosmi, 0x06, 0x10, 0x00000000, 0x00000000, PPC_SPE);
8998 GEN_SPE(speundef, evmhosmf, 0x07, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
8999 GEN_SPE(speundef, evmhessfa, 0x11, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9000 GEN_SPE(speundef, evmhossfa, 0x13, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9001 GEN_SPE(evmheumia, evmhesmia, 0x14, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9002 GEN_SPE(speundef, evmhesmfa, 0x15, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9003 GEN_SPE(evmhoumia, evmhosmia, 0x16, 0x10, 0x00000000, 0x00000000, PPC_SPE);
9004 GEN_SPE(speundef, evmhosmfa, 0x17, 0x10, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9005
9006 GEN_SPE(speundef, evmwhssf, 0x03, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9007 GEN_SPE(evmwlumi, speundef, 0x04, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9008 GEN_SPE(evmwhumi, evmwhsmi, 0x06, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9009 GEN_SPE(speundef, evmwhsmf, 0x07, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9010 GEN_SPE(speundef, evmwssf, 0x09, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9011 GEN_SPE(speundef, evmwsmf, 0x0D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9012 GEN_SPE(speundef, evmwhssfa, 0x13, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9013 GEN_SPE(evmwlumia, speundef, 0x14, 0x11, 0x00000000, 0xFFFFFFFF, PPC_SPE);
9014 GEN_SPE(evmwhumia, evmwhsmia, 0x16, 0x11, 0x00000000, 0x00000000, PPC_SPE);
9015 GEN_SPE(speundef, evmwhsmfa, 0x17, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9016 GEN_SPE(speundef, evmwssfa, 0x19, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9017 GEN_SPE(speundef, evmwsmfa, 0x1D, 0x11, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9018
9019 GEN_SPE(evadduiaaw, evaddsiaaw, 0x00, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9020 GEN_SPE(evsubfusiaaw, evsubfssiaaw, 0x01, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9021 GEN_SPE(evaddumiaaw, evaddsmiaaw, 0x04, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9022 GEN_SPE(evsubfumiaaw, evsubfsmiaaw, 0x05, 0x13, 0x0000F800, 0x0000F800, PPC_SPE);
9023 GEN_SPE(evdivws, evdivwu, 0x06, 0x13, 0x00000000, 0x00000000, PPC_SPE);
9024
9025 GEN_SPE(evmheusiaaw, evmhessiaaw, 0x00, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9026 GEN_SPE(speundef, evmhessfaaw, 0x01, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9027 GEN_SPE(evmhousiaaw, evmhossiaaw, 0x02, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9028 GEN_SPE(speundef, evmhossfaaw, 0x03, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9029 GEN_SPE(evmheumiaaw, evmhesmiaaw, 0x04, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9030 GEN_SPE(speundef, evmhesmfaaw, 0x05, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9031 GEN_SPE(evmhoumiaaw, evmhosmiaaw, 0x06, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9032 GEN_SPE(speundef, evmhosmfaaw, 0x07, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9033 GEN_SPE(evmhegumiaa, evmhegsmiaa, 0x14, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9034 GEN_SPE(speundef, evmhegsmfaa, 0x15, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9035 GEN_SPE(evmhogumiaa, evmhogsmiaa, 0x16, 0x14, 0x00000000, 0x00000000, PPC_SPE);
9036 GEN_SPE(speundef, evmhogsmfaa, 0x17, 0x14, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9037
9038 GEN_SPE(evmwlusiaaw, evmwlssiaaw, 0x00, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9039 GEN_SPE(evmwlumiaaw, evmwlsmiaaw, 0x04, 0x15, 0x00000000, 0x00000000, PPC_SPE);
9040 GEN_SPE(speundef, evmwssfaa, 0x09, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9041 GEN_SPE(speundef, evmwsmfaa, 0x0D, 0x15, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9042
9043 GEN_SPE(evmheusianw, evmhessianw, 0x00, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9044 GEN_SPE(speundef, evmhessfanw, 0x01, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9045 GEN_SPE(evmhousianw, evmhossianw, 0x02, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9046 GEN_SPE(speundef, evmhossfanw, 0x03, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9047 GEN_SPE(evmheumianw, evmhesmianw, 0x04, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9048 GEN_SPE(speundef, evmhesmfanw, 0x05, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9049 GEN_SPE(evmhoumianw, evmhosmianw, 0x06, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9050 GEN_SPE(speundef, evmhosmfanw, 0x07, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9051 GEN_SPE(evmhegumian, evmhegsmian, 0x14, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9052 GEN_SPE(speundef, evmhegsmfan, 0x15, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9053 GEN_SPE(evmhigumian, evmhigsmian, 0x16, 0x16, 0x00000000, 0x00000000, PPC_SPE);
9054 GEN_SPE(speundef, evmhogsmfan, 0x17, 0x16, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9055
9056 GEN_SPE(evmwlusianw, evmwlssianw, 0x00, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9057 GEN_SPE(evmwlumianw, evmwlsmianw, 0x04, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9058 GEN_SPE(speundef, evmwssfan, 0x09, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9059 GEN_SPE(evmwumian, evmwsmian, 0x0C, 0x17, 0x00000000, 0x00000000, PPC_SPE);
9060 GEN_SPE(speundef, evmwsmfan, 0x0D, 0x17, 0xFFFFFFFF, 0x00000000, PPC_SPE);
9061 #endif
9062
9063 /*** SPE floating-point extension ***/
9064 #if defined(TARGET_PPC64)
9065 #define GEN_SPEFPUOP_CONV_32_32(name) \
9066 static inline void gen_##name(DisasContext *ctx) \
9067 { \
9068 TCGv_i32 t0; \
9069 TCGv t1; \
9070 t0 = tcg_temp_new_i32(); \
9071 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9072 gen_helper_##name(t0, cpu_env, t0); \
9073 t1 = tcg_temp_new(); \
9074 tcg_gen_extu_i32_tl(t1, t0); \
9075 tcg_temp_free_i32(t0); \
9076 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
9077 0xFFFFFFFF00000000ULL); \
9078 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
9079 tcg_temp_free(t1); \
9080 }
9081 #define GEN_SPEFPUOP_CONV_32_64(name) \
9082 static inline void gen_##name(DisasContext *ctx) \
9083 { \
9084 TCGv_i32 t0; \
9085 TCGv t1; \
9086 t0 = tcg_temp_new_i32(); \
9087 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
9088 t1 = tcg_temp_new(); \
9089 tcg_gen_extu_i32_tl(t1, t0); \
9090 tcg_temp_free_i32(t0); \
9091 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
9092 0xFFFFFFFF00000000ULL); \
9093 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t1); \
9094 tcg_temp_free(t1); \
9095 }
9096 #define GEN_SPEFPUOP_CONV_64_32(name) \
9097 static inline void gen_##name(DisasContext *ctx) \
9098 { \
9099 TCGv_i32 t0 = tcg_temp_new_i32(); \
9100 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rB(ctx->opcode)]); \
9101 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
9102 tcg_temp_free_i32(t0); \
9103 }
9104 #define GEN_SPEFPUOP_CONV_64_64(name) \
9105 static inline void gen_##name(DisasContext *ctx) \
9106 { \
9107 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9108 cpu_gpr[rB(ctx->opcode)]); \
9109 }
9110 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9111 static inline void gen_##name(DisasContext *ctx) \
9112 { \
9113 TCGv_i32 t0, t1; \
9114 TCGv_i64 t2; \
9115 if (unlikely(!ctx->spe_enabled)) { \
9116 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9117 return; \
9118 } \
9119 t0 = tcg_temp_new_i32(); \
9120 t1 = tcg_temp_new_i32(); \
9121 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9122 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9123 gen_helper_##name(t0, cpu_env, t0, t1); \
9124 tcg_temp_free_i32(t1); \
9125 t2 = tcg_temp_new(); \
9126 tcg_gen_extu_i32_tl(t2, t0); \
9127 tcg_temp_free_i32(t0); \
9128 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], \
9129 0xFFFFFFFF00000000ULL); \
9130 tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rD(ctx->opcode)], t2); \
9131 tcg_temp_free(t2); \
9132 }
9133 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9134 static inline void gen_##name(DisasContext *ctx) \
9135 { \
9136 if (unlikely(!ctx->spe_enabled)) { \
9137 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9138 return; \
9139 } \
9140 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9141 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9142 }
9143 #define GEN_SPEFPUOP_COMP_32(name) \
9144 static inline void gen_##name(DisasContext *ctx) \
9145 { \
9146 TCGv_i32 t0, t1; \
9147 if (unlikely(!ctx->spe_enabled)) { \
9148 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9149 return; \
9150 } \
9151 t0 = tcg_temp_new_i32(); \
9152 t1 = tcg_temp_new_i32(); \
9153 tcg_gen_trunc_tl_i32(t0, cpu_gpr[rA(ctx->opcode)]); \
9154 tcg_gen_trunc_tl_i32(t1, cpu_gpr[rB(ctx->opcode)]); \
9155 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9156 tcg_temp_free_i32(t0); \
9157 tcg_temp_free_i32(t1); \
9158 }
9159 #define GEN_SPEFPUOP_COMP_64(name) \
9160 static inline void gen_##name(DisasContext *ctx) \
9161 { \
9162 if (unlikely(!ctx->spe_enabled)) { \
9163 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9164 return; \
9165 } \
9166 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
9167 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9168 }
9169 #else
9170 #define GEN_SPEFPUOP_CONV_32_32(name) \
9171 static inline void gen_##name(DisasContext *ctx) \
9172 { \
9173 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9174 cpu_gpr[rB(ctx->opcode)]); \
9175 }
9176 #define GEN_SPEFPUOP_CONV_32_64(name) \
9177 static inline void gen_##name(DisasContext *ctx) \
9178 { \
9179 TCGv_i64 t0 = tcg_temp_new_i64(); \
9180 gen_load_gpr64(t0, rB(ctx->opcode)); \
9181 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, t0); \
9182 tcg_temp_free_i64(t0); \
9183 }
9184 #define GEN_SPEFPUOP_CONV_64_32(name) \
9185 static inline void gen_##name(DisasContext *ctx) \
9186 { \
9187 TCGv_i64 t0 = tcg_temp_new_i64(); \
9188 gen_helper_##name(t0, cpu_env, cpu_gpr[rB(ctx->opcode)]); \
9189 gen_store_gpr64(rD(ctx->opcode), t0); \
9190 tcg_temp_free_i64(t0); \
9191 }
9192 #define GEN_SPEFPUOP_CONV_64_64(name) \
9193 static inline void gen_##name(DisasContext *ctx) \
9194 { \
9195 TCGv_i64 t0 = tcg_temp_new_i64(); \
9196 gen_load_gpr64(t0, rB(ctx->opcode)); \
9197 gen_helper_##name(t0, cpu_env, t0); \
9198 gen_store_gpr64(rD(ctx->opcode), t0); \
9199 tcg_temp_free_i64(t0); \
9200 }
9201 #define GEN_SPEFPUOP_ARITH2_32_32(name) \
9202 static inline void gen_##name(DisasContext *ctx) \
9203 { \
9204 if (unlikely(!ctx->spe_enabled)) { \
9205 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9206 return; \
9207 } \
9208 gen_helper_##name(cpu_gpr[rD(ctx->opcode)], cpu_env, \
9209 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9210 }
9211 #define GEN_SPEFPUOP_ARITH2_64_64(name) \
9212 static inline void gen_##name(DisasContext *ctx) \
9213 { \
9214 TCGv_i64 t0, t1; \
9215 if (unlikely(!ctx->spe_enabled)) { \
9216 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9217 return; \
9218 } \
9219 t0 = tcg_temp_new_i64(); \
9220 t1 = tcg_temp_new_i64(); \
9221 gen_load_gpr64(t0, rA(ctx->opcode)); \
9222 gen_load_gpr64(t1, rB(ctx->opcode)); \
9223 gen_helper_##name(t0, cpu_env, t0, t1); \
9224 gen_store_gpr64(rD(ctx->opcode), t0); \
9225 tcg_temp_free_i64(t0); \
9226 tcg_temp_free_i64(t1); \
9227 }
9228 #define GEN_SPEFPUOP_COMP_32(name) \
9229 static inline void gen_##name(DisasContext *ctx) \
9230 { \
9231 if (unlikely(!ctx->spe_enabled)) { \
9232 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9233 return; \
9234 } \
9235 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, \
9236 cpu_gpr[rA(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); \
9237 }
9238 #define GEN_SPEFPUOP_COMP_64(name) \
9239 static inline void gen_##name(DisasContext *ctx) \
9240 { \
9241 TCGv_i64 t0, t1; \
9242 if (unlikely(!ctx->spe_enabled)) { \
9243 gen_exception(ctx, POWERPC_EXCP_SPEU); \
9244 return; \
9245 } \
9246 t0 = tcg_temp_new_i64(); \
9247 t1 = tcg_temp_new_i64(); \
9248 gen_load_gpr64(t0, rA(ctx->opcode)); \
9249 gen_load_gpr64(t1, rB(ctx->opcode)); \
9250 gen_helper_##name(cpu_crf[crfD(ctx->opcode)], cpu_env, t0, t1); \
9251 tcg_temp_free_i64(t0); \
9252 tcg_temp_free_i64(t1); \
9253 }
9254 #endif
9255
9256 /* Single precision floating-point vectors operations */
9257 /* Arithmetic */
9258 GEN_SPEFPUOP_ARITH2_64_64(evfsadd);
9259 GEN_SPEFPUOP_ARITH2_64_64(evfssub);
9260 GEN_SPEFPUOP_ARITH2_64_64(evfsmul);
9261 GEN_SPEFPUOP_ARITH2_64_64(evfsdiv);
9262 static inline void gen_evfsabs(DisasContext *ctx)
9263 {
9264 if (unlikely(!ctx->spe_enabled)) {
9265 gen_exception(ctx, POWERPC_EXCP_SPEU);
9266 return;
9267 }
9268 #if defined(TARGET_PPC64)
9269 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000080000000LL);
9270 #else
9271 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x80000000);
9272 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
9273 #endif
9274 }
9275 static inline void gen_evfsnabs(DisasContext *ctx)
9276 {
9277 if (unlikely(!ctx->spe_enabled)) {
9278 gen_exception(ctx, POWERPC_EXCP_SPEU);
9279 return;
9280 }
9281 #if defined(TARGET_PPC64)
9282 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
9283 #else
9284 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9285 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9286 #endif
9287 }
9288 static inline void gen_evfsneg(DisasContext *ctx)
9289 {
9290 if (unlikely(!ctx->spe_enabled)) {
9291 gen_exception(ctx, POWERPC_EXCP_SPEU);
9292 return;
9293 }
9294 #if defined(TARGET_PPC64)
9295 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000080000000LL);
9296 #else
9297 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9298 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9299 #endif
9300 }
9301
9302 /* Conversion */
9303 GEN_SPEFPUOP_CONV_64_64(evfscfui);
9304 GEN_SPEFPUOP_CONV_64_64(evfscfsi);
9305 GEN_SPEFPUOP_CONV_64_64(evfscfuf);
9306 GEN_SPEFPUOP_CONV_64_64(evfscfsf);
9307 GEN_SPEFPUOP_CONV_64_64(evfsctui);
9308 GEN_SPEFPUOP_CONV_64_64(evfsctsi);
9309 GEN_SPEFPUOP_CONV_64_64(evfsctuf);
9310 GEN_SPEFPUOP_CONV_64_64(evfsctsf);
9311 GEN_SPEFPUOP_CONV_64_64(evfsctuiz);
9312 GEN_SPEFPUOP_CONV_64_64(evfsctsiz);
9313
9314 /* Comparison */
9315 GEN_SPEFPUOP_COMP_64(evfscmpgt);
9316 GEN_SPEFPUOP_COMP_64(evfscmplt);
9317 GEN_SPEFPUOP_COMP_64(evfscmpeq);
9318 GEN_SPEFPUOP_COMP_64(evfststgt);
9319 GEN_SPEFPUOP_COMP_64(evfststlt);
9320 GEN_SPEFPUOP_COMP_64(evfststeq);
9321
9322 /* Opcodes definitions */
9323 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9324 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9325 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9326 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9327 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9328 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9329 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9330 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9331 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9332 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9333 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9334 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9335 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9336 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9337
9338 /* Single precision floating-point operations */
9339 /* Arithmetic */
9340 GEN_SPEFPUOP_ARITH2_32_32(efsadd);
9341 GEN_SPEFPUOP_ARITH2_32_32(efssub);
9342 GEN_SPEFPUOP_ARITH2_32_32(efsmul);
9343 GEN_SPEFPUOP_ARITH2_32_32(efsdiv);
9344 static inline void gen_efsabs(DisasContext *ctx)
9345 {
9346 if (unlikely(!ctx->spe_enabled)) {
9347 gen_exception(ctx, POWERPC_EXCP_SPEU);
9348 return;
9349 }
9350 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], (target_long)~0x80000000LL);
9351 }
9352 static inline void gen_efsnabs(DisasContext *ctx)
9353 {
9354 if (unlikely(!ctx->spe_enabled)) {
9355 gen_exception(ctx, POWERPC_EXCP_SPEU);
9356 return;
9357 }
9358 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9359 }
9360 static inline void gen_efsneg(DisasContext *ctx)
9361 {
9362 if (unlikely(!ctx->spe_enabled)) {
9363 gen_exception(ctx, POWERPC_EXCP_SPEU);
9364 return;
9365 }
9366 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x80000000);
9367 }
9368
9369 /* Conversion */
9370 GEN_SPEFPUOP_CONV_32_32(efscfui);
9371 GEN_SPEFPUOP_CONV_32_32(efscfsi);
9372 GEN_SPEFPUOP_CONV_32_32(efscfuf);
9373 GEN_SPEFPUOP_CONV_32_32(efscfsf);
9374 GEN_SPEFPUOP_CONV_32_32(efsctui);
9375 GEN_SPEFPUOP_CONV_32_32(efsctsi);
9376 GEN_SPEFPUOP_CONV_32_32(efsctuf);
9377 GEN_SPEFPUOP_CONV_32_32(efsctsf);
9378 GEN_SPEFPUOP_CONV_32_32(efsctuiz);
9379 GEN_SPEFPUOP_CONV_32_32(efsctsiz);
9380 GEN_SPEFPUOP_CONV_32_64(efscfd);
9381
9382 /* Comparison */
9383 GEN_SPEFPUOP_COMP_32(efscmpgt);
9384 GEN_SPEFPUOP_COMP_32(efscmplt);
9385 GEN_SPEFPUOP_COMP_32(efscmpeq);
9386 GEN_SPEFPUOP_COMP_32(efststgt);
9387 GEN_SPEFPUOP_COMP_32(efststlt);
9388 GEN_SPEFPUOP_COMP_32(efststeq);
9389
9390 /* Opcodes definitions */
9391 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9392 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE); //
9393 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9394 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE); //
9395 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9396 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE); //
9397 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9398 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9399 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9400 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE); //
9401 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9402 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9403 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE); //
9404 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE); //
9405
9406 /* Double precision floating-point operations */
9407 /* Arithmetic */
9408 GEN_SPEFPUOP_ARITH2_64_64(efdadd);
9409 GEN_SPEFPUOP_ARITH2_64_64(efdsub);
9410 GEN_SPEFPUOP_ARITH2_64_64(efdmul);
9411 GEN_SPEFPUOP_ARITH2_64_64(efddiv);
9412 static inline void gen_efdabs(DisasContext *ctx)
9413 {
9414 if (unlikely(!ctx->spe_enabled)) {
9415 gen_exception(ctx, POWERPC_EXCP_SPEU);
9416 return;
9417 }
9418 #if defined(TARGET_PPC64)
9419 tcg_gen_andi_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], ~0x8000000000000000LL);
9420 #else
9421 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9422 tcg_gen_andi_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], ~0x80000000);
9423 #endif
9424 }
9425 static inline void gen_efdnabs(DisasContext *ctx)
9426 {
9427 if (unlikely(!ctx->spe_enabled)) {
9428 gen_exception(ctx, POWERPC_EXCP_SPEU);
9429 return;
9430 }
9431 #if defined(TARGET_PPC64)
9432 tcg_gen_ori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
9433 #else
9434 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9435 tcg_gen_ori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9436 #endif
9437 }
9438 static inline void gen_efdneg(DisasContext *ctx)
9439 {
9440 if (unlikely(!ctx->spe_enabled)) {
9441 gen_exception(ctx, POWERPC_EXCP_SPEU);
9442 return;
9443 }
9444 #if defined(TARGET_PPC64)
9445 tcg_gen_xori_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)], 0x8000000000000000LL);
9446 #else
9447 tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]);
9448 tcg_gen_xori_tl(cpu_gprh[rD(ctx->opcode)], cpu_gprh[rA(ctx->opcode)], 0x80000000);
9449 #endif
9450 }
9451
9452 /* Conversion */
9453 GEN_SPEFPUOP_CONV_64_32(efdcfui);
9454 GEN_SPEFPUOP_CONV_64_32(efdcfsi);
9455 GEN_SPEFPUOP_CONV_64_32(efdcfuf);
9456 GEN_SPEFPUOP_CONV_64_32(efdcfsf);
9457 GEN_SPEFPUOP_CONV_32_64(efdctui);
9458 GEN_SPEFPUOP_CONV_32_64(efdctsi);
9459 GEN_SPEFPUOP_CONV_32_64(efdctuf);
9460 GEN_SPEFPUOP_CONV_32_64(efdctsf);
9461 GEN_SPEFPUOP_CONV_32_64(efdctuiz);
9462 GEN_SPEFPUOP_CONV_32_64(efdctsiz);
9463 GEN_SPEFPUOP_CONV_64_32(efdcfs);
9464 GEN_SPEFPUOP_CONV_64_64(efdcfuid);
9465 GEN_SPEFPUOP_CONV_64_64(efdcfsid);
9466 GEN_SPEFPUOP_CONV_64_64(efdctuidz);
9467 GEN_SPEFPUOP_CONV_64_64(efdctsidz);
9468
9469 /* Comparison */
9470 GEN_SPEFPUOP_COMP_64(efdcmpgt);
9471 GEN_SPEFPUOP_COMP_64(efdcmplt);
9472 GEN_SPEFPUOP_COMP_64(efdcmpeq);
9473 GEN_SPEFPUOP_COMP_64(efdtstgt);
9474 GEN_SPEFPUOP_COMP_64(efdtstlt);
9475 GEN_SPEFPUOP_COMP_64(efdtsteq);
9476
9477 /* Opcodes definitions */
9478 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9479 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9480 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE); //
9481 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9482 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE); //
9483 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9484 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9485 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE); //
9486 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9487 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9488 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9489 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE); //
9490 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9491 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9492 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE); //
9493 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE); //
9494
9495 static opcode_t opcodes[] = {
9496 GEN_HANDLER(invalid, 0x00, 0x00, 0x00, 0xFFFFFFFF, PPC_NONE),
9497 GEN_HANDLER(cmp, 0x1F, 0x00, 0x00, 0x00400000, PPC_INTEGER),
9498 GEN_HANDLER(cmpi, 0x0B, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9499 GEN_HANDLER(cmpl, 0x1F, 0x00, 0x01, 0x00400000, PPC_INTEGER),
9500 GEN_HANDLER(cmpli, 0x0A, 0xFF, 0xFF, 0x00400000, PPC_INTEGER),
9501 GEN_HANDLER_E(cmpb, 0x1F, 0x1C, 0x0F, 0x00000001, PPC_NONE, PPC2_ISA205),
9502 GEN_HANDLER(isel, 0x1F, 0x0F, 0xFF, 0x00000001, PPC_ISEL),
9503 GEN_HANDLER(addi, 0x0E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9504 GEN_HANDLER(addic, 0x0C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9505 GEN_HANDLER2(addic_, "addic.", 0x0D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9506 GEN_HANDLER(addis, 0x0F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9507 GEN_HANDLER(mulhw, 0x1F, 0x0B, 0x02, 0x00000400, PPC_INTEGER),
9508 GEN_HANDLER(mulhwu, 0x1F, 0x0B, 0x00, 0x00000400, PPC_INTEGER),
9509 GEN_HANDLER(mullw, 0x1F, 0x0B, 0x07, 0x00000000, PPC_INTEGER),
9510 GEN_HANDLER(mullwo, 0x1F, 0x0B, 0x17, 0x00000000, PPC_INTEGER),
9511 GEN_HANDLER(mulli, 0x07, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9512 #if defined(TARGET_PPC64)
9513 GEN_HANDLER(mulld, 0x1F, 0x09, 0x07, 0x00000000, PPC_64B),
9514 #endif
9515 GEN_HANDLER(neg, 0x1F, 0x08, 0x03, 0x0000F800, PPC_INTEGER),
9516 GEN_HANDLER(nego, 0x1F, 0x08, 0x13, 0x0000F800, PPC_INTEGER),
9517 GEN_HANDLER(subfic, 0x08, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9518 GEN_HANDLER2(andi_, "andi.", 0x1C, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9519 GEN_HANDLER2(andis_, "andis.", 0x1D, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9520 GEN_HANDLER(cntlzw, 0x1F, 0x1A, 0x00, 0x00000000, PPC_INTEGER),
9521 GEN_HANDLER(or, 0x1F, 0x1C, 0x0D, 0x00000000, PPC_INTEGER),
9522 GEN_HANDLER(xor, 0x1F, 0x1C, 0x09, 0x00000000, PPC_INTEGER),
9523 GEN_HANDLER(ori, 0x18, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9524 GEN_HANDLER(oris, 0x19, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9525 GEN_HANDLER(xori, 0x1A, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9526 GEN_HANDLER(xoris, 0x1B, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9527 GEN_HANDLER(popcntb, 0x1F, 0x03, 0x03, 0x0000F801, PPC_POPCNTB),
9528 GEN_HANDLER(popcntw, 0x1F, 0x1A, 0x0b, 0x0000F801, PPC_POPCNTWD),
9529 GEN_HANDLER_E(prtyw, 0x1F, 0x1A, 0x04, 0x0000F801, PPC_NONE, PPC2_ISA205),
9530 #if defined(TARGET_PPC64)
9531 GEN_HANDLER(popcntd, 0x1F, 0x1A, 0x0F, 0x0000F801, PPC_POPCNTWD),
9532 GEN_HANDLER(cntlzd, 0x1F, 0x1A, 0x01, 0x00000000, PPC_64B),
9533 GEN_HANDLER_E(prtyd, 0x1F, 0x1A, 0x05, 0x0000F801, PPC_NONE, PPC2_ISA205),
9534 GEN_HANDLER_E(bpermd, 0x1F, 0x1C, 0x07, 0x00000001, PPC_NONE, PPC2_PERM_ISA206),
9535 #endif
9536 GEN_HANDLER(rlwimi, 0x14, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9537 GEN_HANDLER(rlwinm, 0x15, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9538 GEN_HANDLER(rlwnm, 0x17, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9539 GEN_HANDLER(slw, 0x1F, 0x18, 0x00, 0x00000000, PPC_INTEGER),
9540 GEN_HANDLER(sraw, 0x1F, 0x18, 0x18, 0x00000000, PPC_INTEGER),
9541 GEN_HANDLER(srawi, 0x1F, 0x18, 0x19, 0x00000000, PPC_INTEGER),
9542 GEN_HANDLER(srw, 0x1F, 0x18, 0x10, 0x00000000, PPC_INTEGER),
9543 #if defined(TARGET_PPC64)
9544 GEN_HANDLER(sld, 0x1F, 0x1B, 0x00, 0x00000000, PPC_64B),
9545 GEN_HANDLER(srad, 0x1F, 0x1A, 0x18, 0x00000000, PPC_64B),
9546 GEN_HANDLER2(sradi0, "sradi", 0x1F, 0x1A, 0x19, 0x00000000, PPC_64B),
9547 GEN_HANDLER2(sradi1, "sradi", 0x1F, 0x1B, 0x19, 0x00000000, PPC_64B),
9548 GEN_HANDLER(srd, 0x1F, 0x1B, 0x10, 0x00000000, PPC_64B),
9549 #endif
9550 GEN_HANDLER(frsqrtes, 0x3B, 0x1A, 0xFF, 0x001F07C0, PPC_FLOAT_FRSQRTES),
9551 GEN_HANDLER(fsqrt, 0x3F, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9552 GEN_HANDLER(fsqrts, 0x3B, 0x16, 0xFF, 0x001F07C0, PPC_FLOAT_FSQRT),
9553 GEN_HANDLER(fcmpo, 0x3F, 0x00, 0x01, 0x00600001, PPC_FLOAT),
9554 GEN_HANDLER(fcmpu, 0x3F, 0x00, 0x00, 0x00600001, PPC_FLOAT),
9555 GEN_HANDLER(fabs, 0x3F, 0x08, 0x08, 0x001F0000, PPC_FLOAT),
9556 GEN_HANDLER(fmr, 0x3F, 0x08, 0x02, 0x001F0000, PPC_FLOAT),
9557 GEN_HANDLER(fnabs, 0x3F, 0x08, 0x04, 0x001F0000, PPC_FLOAT),
9558 GEN_HANDLER(fneg, 0x3F, 0x08, 0x01, 0x001F0000, PPC_FLOAT),
9559 GEN_HANDLER_E(fcpsgn, 0x3F, 0x08, 0x00, 0x00000000, PPC_NONE, PPC2_ISA205),
9560 GEN_HANDLER_E(fmrgew, 0x3F, 0x06, 0x1E, 0x00000001, PPC_NONE, PPC2_VSX207),
9561 GEN_HANDLER_E(fmrgow, 0x3F, 0x06, 0x1A, 0x00000001, PPC_NONE, PPC2_VSX207),
9562 GEN_HANDLER(mcrfs, 0x3F, 0x00, 0x02, 0x0063F801, PPC_FLOAT),
9563 GEN_HANDLER(mffs, 0x3F, 0x07, 0x12, 0x001FF800, PPC_FLOAT),
9564 GEN_HANDLER(mtfsb0, 0x3F, 0x06, 0x02, 0x001FF800, PPC_FLOAT),
9565 GEN_HANDLER(mtfsb1, 0x3F, 0x06, 0x01, 0x001FF800, PPC_FLOAT),
9566 GEN_HANDLER(mtfsf, 0x3F, 0x07, 0x16, 0x00000000, PPC_FLOAT),
9567 GEN_HANDLER(mtfsfi, 0x3F, 0x06, 0x04, 0x006e0800, PPC_FLOAT),
9568 #if defined(TARGET_PPC64)
9569 GEN_HANDLER(ld, 0x3A, 0xFF, 0xFF, 0x00000000, PPC_64B),
9570 GEN_HANDLER(lq, 0x38, 0xFF, 0xFF, 0x00000000, PPC_64BX),
9571 GEN_HANDLER(std, 0x3E, 0xFF, 0xFF, 0x00000000, PPC_64B),
9572 #endif
9573 GEN_HANDLER(lmw, 0x2E, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9574 GEN_HANDLER(stmw, 0x2F, 0xFF, 0xFF, 0x00000000, PPC_INTEGER),
9575 GEN_HANDLER(lswi, 0x1F, 0x15, 0x12, 0x00000001, PPC_STRING),
9576 GEN_HANDLER(lswx, 0x1F, 0x15, 0x10, 0x00000001, PPC_STRING),
9577 GEN_HANDLER(stswi, 0x1F, 0x15, 0x16, 0x00000001, PPC_STRING),
9578 GEN_HANDLER(stswx, 0x1F, 0x15, 0x14, 0x00000001, PPC_STRING),
9579 GEN_HANDLER(eieio, 0x1F, 0x16, 0x1A, 0x03FFF801, PPC_MEM_EIEIO),
9580 GEN_HANDLER(isync, 0x13, 0x16, 0x04, 0x03FFF801, PPC_MEM),
9581 GEN_HANDLER_E(lbarx, 0x1F, 0x14, 0x01, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9582 GEN_HANDLER_E(lharx, 0x1F, 0x14, 0x03, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9583 GEN_HANDLER(lwarx, 0x1F, 0x14, 0x00, 0x00000000, PPC_RES),
9584 GEN_HANDLER_E(stbcx_, 0x1F, 0x16, 0x15, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9585 GEN_HANDLER_E(sthcx_, 0x1F, 0x16, 0x16, 0, PPC_NONE, PPC2_ATOMIC_ISA206),
9586 GEN_HANDLER2(stwcx_, "stwcx.", 0x1F, 0x16, 0x04, 0x00000000, PPC_RES),
9587 #if defined(TARGET_PPC64)
9588 GEN_HANDLER(ldarx, 0x1F, 0x14, 0x02, 0x00000000, PPC_64B),
9589 GEN_HANDLER2(stdcx_, "stdcx.", 0x1F, 0x16, 0x06, 0x00000000, PPC_64B),
9590 #endif
9591 GEN_HANDLER(sync, 0x1F, 0x16, 0x12, 0x039FF801, PPC_MEM_SYNC),
9592 GEN_HANDLER(wait, 0x1F, 0x1E, 0x01, 0x03FFF801, PPC_WAIT),
9593 GEN_HANDLER(b, 0x12, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9594 GEN_HANDLER(bc, 0x10, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9595 GEN_HANDLER(bcctr, 0x13, 0x10, 0x10, 0x00000000, PPC_FLOW),
9596 GEN_HANDLER(bclr, 0x13, 0x10, 0x00, 0x00000000, PPC_FLOW),
9597 GEN_HANDLER(mcrf, 0x13, 0x00, 0xFF, 0x00000001, PPC_INTEGER),
9598 GEN_HANDLER(rfi, 0x13, 0x12, 0x01, 0x03FF8001, PPC_FLOW),
9599 #if defined(TARGET_PPC64)
9600 GEN_HANDLER(rfid, 0x13, 0x12, 0x00, 0x03FF8001, PPC_64B),
9601 GEN_HANDLER(hrfid, 0x13, 0x12, 0x08, 0x03FF8001, PPC_64H),
9602 #endif
9603 GEN_HANDLER(sc, 0x11, 0xFF, 0xFF, 0x03FFF01D, PPC_FLOW),
9604 GEN_HANDLER(tw, 0x1F, 0x04, 0x00, 0x00000001, PPC_FLOW),
9605 GEN_HANDLER(twi, 0x03, 0xFF, 0xFF, 0x00000000, PPC_FLOW),
9606 #if defined(TARGET_PPC64)
9607 GEN_HANDLER(td, 0x1F, 0x04, 0x02, 0x00000001, PPC_64B),
9608 GEN_HANDLER(tdi, 0x02, 0xFF, 0xFF, 0x00000000, PPC_64B),
9609 #endif
9610 GEN_HANDLER(mcrxr, 0x1F, 0x00, 0x10, 0x007FF801, PPC_MISC),
9611 GEN_HANDLER(mfcr, 0x1F, 0x13, 0x00, 0x00000801, PPC_MISC),
9612 GEN_HANDLER(mfmsr, 0x1F, 0x13, 0x02, 0x001FF801, PPC_MISC),
9613 GEN_HANDLER(mfspr, 0x1F, 0x13, 0x0A, 0x00000001, PPC_MISC),
9614 GEN_HANDLER(mftb, 0x1F, 0x13, 0x0B, 0x00000001, PPC_MFTB),
9615 GEN_HANDLER(mtcrf, 0x1F, 0x10, 0x04, 0x00000801, PPC_MISC),
9616 #if defined(TARGET_PPC64)
9617 GEN_HANDLER(mtmsrd, 0x1F, 0x12, 0x05, 0x001EF801, PPC_64B),
9618 #endif
9619 GEN_HANDLER(mtmsr, 0x1F, 0x12, 0x04, 0x001FF801, PPC_MISC),
9620 GEN_HANDLER(mtspr, 0x1F, 0x13, 0x0E, 0x00000001, PPC_MISC),
9621 GEN_HANDLER(dcbf, 0x1F, 0x16, 0x02, 0x03C00001, PPC_CACHE),
9622 GEN_HANDLER(dcbi, 0x1F, 0x16, 0x0E, 0x03E00001, PPC_CACHE),
9623 GEN_HANDLER(dcbst, 0x1F, 0x16, 0x01, 0x03E00001, PPC_CACHE),
9624 GEN_HANDLER(dcbt, 0x1F, 0x16, 0x08, 0x00000001, PPC_CACHE),
9625 GEN_HANDLER(dcbtst, 0x1F, 0x16, 0x07, 0x00000001, PPC_CACHE),
9626 GEN_HANDLER(dcbz, 0x1F, 0x16, 0x1F, 0x03C00001, PPC_CACHE_DCBZ),
9627 GEN_HANDLER(dst, 0x1F, 0x16, 0x0A, 0x01800001, PPC_ALTIVEC),
9628 GEN_HANDLER(dstst, 0x1F, 0x16, 0x0B, 0x02000001, PPC_ALTIVEC),
9629 GEN_HANDLER(dss, 0x1F, 0x16, 0x19, 0x019FF801, PPC_ALTIVEC),
9630 GEN_HANDLER(icbi, 0x1F, 0x16, 0x1E, 0x03E00001, PPC_CACHE_ICBI),
9631 GEN_HANDLER(dcba, 0x1F, 0x16, 0x17, 0x03E00001, PPC_CACHE_DCBA),
9632 GEN_HANDLER(mfsr, 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT),
9633 GEN_HANDLER(mfsrin, 0x1F, 0x13, 0x14, 0x001F0001, PPC_SEGMENT),
9634 GEN_HANDLER(mtsr, 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT),
9635 GEN_HANDLER(mtsrin, 0x1F, 0x12, 0x07, 0x001F0001, PPC_SEGMENT),
9636 #if defined(TARGET_PPC64)
9637 GEN_HANDLER2(mfsr_64b, "mfsr", 0x1F, 0x13, 0x12, 0x0010F801, PPC_SEGMENT_64B),
9638 GEN_HANDLER2(mfsrin_64b, "mfsrin", 0x1F, 0x13, 0x14, 0x001F0001,
9639 PPC_SEGMENT_64B),
9640 GEN_HANDLER2(mtsr_64b, "mtsr", 0x1F, 0x12, 0x06, 0x0010F801, PPC_SEGMENT_64B),
9641 GEN_HANDLER2(mtsrin_64b, "mtsrin", 0x1F, 0x12, 0x07, 0x001F0001,
9642 PPC_SEGMENT_64B),
9643 GEN_HANDLER2(slbmte, "slbmte", 0x1F, 0x12, 0x0C, 0x001F0001, PPC_SEGMENT_64B),
9644 GEN_HANDLER2(slbmfee, "slbmfee", 0x1F, 0x13, 0x1C, 0x001F0001, PPC_SEGMENT_64B),
9645 GEN_HANDLER2(slbmfev, "slbmfev", 0x1F, 0x13, 0x1A, 0x001F0001, PPC_SEGMENT_64B),
9646 #endif
9647 GEN_HANDLER(tlbia, 0x1F, 0x12, 0x0B, 0x03FFFC01, PPC_MEM_TLBIA),
9648 GEN_HANDLER(tlbiel, 0x1F, 0x12, 0x08, 0x03FF0001, PPC_MEM_TLBIE),
9649 GEN_HANDLER(tlbie, 0x1F, 0x12, 0x09, 0x03FF0001, PPC_MEM_TLBIE),
9650 GEN_HANDLER(tlbsync, 0x1F, 0x16, 0x11, 0x03FFF801, PPC_MEM_TLBSYNC),
9651 #if defined(TARGET_PPC64)
9652 GEN_HANDLER(slbia, 0x1F, 0x12, 0x0F, 0x03FFFC01, PPC_SLBI),
9653 GEN_HANDLER(slbie, 0x1F, 0x12, 0x0D, 0x03FF0001, PPC_SLBI),
9654 #endif
9655 GEN_HANDLER(eciwx, 0x1F, 0x16, 0x0D, 0x00000001, PPC_EXTERN),
9656 GEN_HANDLER(ecowx, 0x1F, 0x16, 0x09, 0x00000001, PPC_EXTERN),
9657 GEN_HANDLER(abs, 0x1F, 0x08, 0x0B, 0x0000F800, PPC_POWER_BR),
9658 GEN_HANDLER(abso, 0x1F, 0x08, 0x1B, 0x0000F800, PPC_POWER_BR),
9659 GEN_HANDLER(clcs, 0x1F, 0x10, 0x13, 0x0000F800, PPC_POWER_BR),
9660 GEN_HANDLER(div, 0x1F, 0x0B, 0x0A, 0x00000000, PPC_POWER_BR),
9661 GEN_HANDLER(divo, 0x1F, 0x0B, 0x1A, 0x00000000, PPC_POWER_BR),
9662 GEN_HANDLER(divs, 0x1F, 0x0B, 0x0B, 0x00000000, PPC_POWER_BR),
9663 GEN_HANDLER(divso, 0x1F, 0x0B, 0x1B, 0x00000000, PPC_POWER_BR),
9664 GEN_HANDLER(doz, 0x1F, 0x08, 0x08, 0x00000000, PPC_POWER_BR),
9665 GEN_HANDLER(dozo, 0x1F, 0x08, 0x18, 0x00000000, PPC_POWER_BR),
9666 GEN_HANDLER(dozi, 0x09, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9667 GEN_HANDLER(lscbx, 0x1F, 0x15, 0x08, 0x00000000, PPC_POWER_BR),
9668 GEN_HANDLER(maskg, 0x1F, 0x1D, 0x00, 0x00000000, PPC_POWER_BR),
9669 GEN_HANDLER(maskir, 0x1F, 0x1D, 0x10, 0x00000000, PPC_POWER_BR),
9670 GEN_HANDLER(mul, 0x1F, 0x0B, 0x03, 0x00000000, PPC_POWER_BR),
9671 GEN_HANDLER(mulo, 0x1F, 0x0B, 0x13, 0x00000000, PPC_POWER_BR),
9672 GEN_HANDLER(nabs, 0x1F, 0x08, 0x0F, 0x00000000, PPC_POWER_BR),
9673 GEN_HANDLER(nabso, 0x1F, 0x08, 0x1F, 0x00000000, PPC_POWER_BR),
9674 GEN_HANDLER(rlmi, 0x16, 0xFF, 0xFF, 0x00000000, PPC_POWER_BR),
9675 GEN_HANDLER(rrib, 0x1F, 0x19, 0x10, 0x00000000, PPC_POWER_BR),
9676 GEN_HANDLER(sle, 0x1F, 0x19, 0x04, 0x00000000, PPC_POWER_BR),
9677 GEN_HANDLER(sleq, 0x1F, 0x19, 0x06, 0x00000000, PPC_POWER_BR),
9678 GEN_HANDLER(sliq, 0x1F, 0x18, 0x05, 0x00000000, PPC_POWER_BR),
9679 GEN_HANDLER(slliq, 0x1F, 0x18, 0x07, 0x00000000, PPC_POWER_BR),
9680 GEN_HANDLER(sllq, 0x1F, 0x18, 0x06, 0x00000000, PPC_POWER_BR),
9681 GEN_HANDLER(slq, 0x1F, 0x18, 0x04, 0x00000000, PPC_POWER_BR),
9682 GEN_HANDLER(sraiq, 0x1F, 0x18, 0x1D, 0x00000000, PPC_POWER_BR),
9683 GEN_HANDLER(sraq, 0x1F, 0x18, 0x1C, 0x00000000, PPC_POWER_BR),
9684 GEN_HANDLER(sre, 0x1F, 0x19, 0x14, 0x00000000, PPC_POWER_BR),
9685 GEN_HANDLER(srea, 0x1F, 0x19, 0x1C, 0x00000000, PPC_POWER_BR),
9686 GEN_HANDLER(sreq, 0x1F, 0x19, 0x16, 0x00000000, PPC_POWER_BR),
9687 GEN_HANDLER(sriq, 0x1F, 0x18, 0x15, 0x00000000, PPC_POWER_BR),
9688 GEN_HANDLER(srliq, 0x1F, 0x18, 0x17, 0x00000000, PPC_POWER_BR),
9689 GEN_HANDLER(srlq, 0x1F, 0x18, 0x16, 0x00000000, PPC_POWER_BR),
9690 GEN_HANDLER(srq, 0x1F, 0x18, 0x14, 0x00000000, PPC_POWER_BR),
9691 GEN_HANDLER(dsa, 0x1F, 0x14, 0x13, 0x03FFF801, PPC_602_SPEC),
9692 GEN_HANDLER(esa, 0x1F, 0x14, 0x12, 0x03FFF801, PPC_602_SPEC),
9693 GEN_HANDLER(mfrom, 0x1F, 0x09, 0x08, 0x03E0F801, PPC_602_SPEC),
9694 GEN_HANDLER2(tlbld_6xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_6xx_TLB),
9695 GEN_HANDLER2(tlbli_6xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_6xx_TLB),
9696 GEN_HANDLER2(tlbld_74xx, "tlbld", 0x1F, 0x12, 0x1E, 0x03FF0001, PPC_74xx_TLB),
9697 GEN_HANDLER2(tlbli_74xx, "tlbli", 0x1F, 0x12, 0x1F, 0x03FF0001, PPC_74xx_TLB),
9698 GEN_HANDLER(clf, 0x1F, 0x16, 0x03, 0x03E00000, PPC_POWER),
9699 GEN_HANDLER(cli, 0x1F, 0x16, 0x0F, 0x03E00000, PPC_POWER),
9700 GEN_HANDLER(dclst, 0x1F, 0x16, 0x13, 0x03E00000, PPC_POWER),
9701 GEN_HANDLER(mfsri, 0x1F, 0x13, 0x13, 0x00000001, PPC_POWER),
9702 GEN_HANDLER(rac, 0x1F, 0x12, 0x19, 0x00000001, PPC_POWER),
9703 GEN_HANDLER(rfsvc, 0x13, 0x12, 0x02, 0x03FFF0001, PPC_POWER),
9704 GEN_HANDLER(lfq, 0x38, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9705 GEN_HANDLER(lfqu, 0x39, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9706 GEN_HANDLER(lfqux, 0x1F, 0x17, 0x19, 0x00000001, PPC_POWER2),
9707 GEN_HANDLER(lfqx, 0x1F, 0x17, 0x18, 0x00000001, PPC_POWER2),
9708 GEN_HANDLER(stfq, 0x3C, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9709 GEN_HANDLER(stfqu, 0x3D, 0xFF, 0xFF, 0x00000003, PPC_POWER2),
9710 GEN_HANDLER(stfqux, 0x1F, 0x17, 0x1D, 0x00000001, PPC_POWER2),
9711 GEN_HANDLER(stfqx, 0x1F, 0x17, 0x1C, 0x00000001, PPC_POWER2),
9712 GEN_HANDLER(mfapidi, 0x1F, 0x13, 0x08, 0x0000F801, PPC_MFAPIDI),
9713 GEN_HANDLER(tlbiva, 0x1F, 0x12, 0x18, 0x03FFF801, PPC_TLBIVA),
9714 GEN_HANDLER(mfdcr, 0x1F, 0x03, 0x0A, 0x00000001, PPC_DCR),
9715 GEN_HANDLER(mtdcr, 0x1F, 0x03, 0x0E, 0x00000001, PPC_DCR),
9716 GEN_HANDLER(mfdcrx, 0x1F, 0x03, 0x08, 0x00000000, PPC_DCRX),
9717 GEN_HANDLER(mtdcrx, 0x1F, 0x03, 0x0C, 0x00000000, PPC_DCRX),
9718 GEN_HANDLER(mfdcrux, 0x1F, 0x03, 0x09, 0x00000000, PPC_DCRUX),
9719 GEN_HANDLER(mtdcrux, 0x1F, 0x03, 0x0D, 0x00000000, PPC_DCRUX),
9720 GEN_HANDLER(dccci, 0x1F, 0x06, 0x0E, 0x03E00001, PPC_4xx_COMMON),
9721 GEN_HANDLER(dcread, 0x1F, 0x06, 0x0F, 0x00000001, PPC_4xx_COMMON),
9722 GEN_HANDLER2(icbt_40x, "icbt", 0x1F, 0x06, 0x08, 0x03E00001, PPC_40x_ICBT),
9723 GEN_HANDLER(iccci, 0x1F, 0x06, 0x1E, 0x00000001, PPC_4xx_COMMON),
9724 GEN_HANDLER(icread, 0x1F, 0x06, 0x1F, 0x03E00001, PPC_4xx_COMMON),
9725 GEN_HANDLER2(rfci_40x, "rfci", 0x13, 0x13, 0x01, 0x03FF8001, PPC_40x_EXCP),
9726 GEN_HANDLER_E(rfci, 0x13, 0x13, 0x01, 0x03FF8001, PPC_BOOKE, PPC2_BOOKE206),
9727 GEN_HANDLER(rfdi, 0x13, 0x07, 0x01, 0x03FF8001, PPC_RFDI),
9728 GEN_HANDLER(rfmci, 0x13, 0x06, 0x01, 0x03FF8001, PPC_RFMCI),
9729 GEN_HANDLER2(tlbre_40x, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_40x_TLB),
9730 GEN_HANDLER2(tlbsx_40x, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_40x_TLB),
9731 GEN_HANDLER2(tlbwe_40x, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_40x_TLB),
9732 GEN_HANDLER2(tlbre_440, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001, PPC_BOOKE),
9733 GEN_HANDLER2(tlbsx_440, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000, PPC_BOOKE),
9734 GEN_HANDLER2(tlbwe_440, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001, PPC_BOOKE),
9735 GEN_HANDLER2_E(tlbre_booke206, "tlbre", 0x1F, 0x12, 0x1D, 0x00000001,
9736 PPC_NONE, PPC2_BOOKE206),
9737 GEN_HANDLER2_E(tlbsx_booke206, "tlbsx", 0x1F, 0x12, 0x1C, 0x00000000,
9738 PPC_NONE, PPC2_BOOKE206),
9739 GEN_HANDLER2_E(tlbwe_booke206, "tlbwe", 0x1F, 0x12, 0x1E, 0x00000001,
9740 PPC_NONE, PPC2_BOOKE206),
9741 GEN_HANDLER2_E(tlbivax_booke206, "tlbivax", 0x1F, 0x12, 0x18, 0x00000001,
9742 PPC_NONE, PPC2_BOOKE206),
9743 GEN_HANDLER2_E(tlbilx_booke206, "tlbilx", 0x1F, 0x12, 0x00, 0x03800001,
9744 PPC_NONE, PPC2_BOOKE206),
9745 GEN_HANDLER2_E(msgsnd, "msgsnd", 0x1F, 0x0E, 0x06, 0x03ff0001,
9746 PPC_NONE, PPC2_PRCNTL),
9747 GEN_HANDLER2_E(msgclr, "msgclr", 0x1F, 0x0E, 0x07, 0x03ff0001,
9748 PPC_NONE, PPC2_PRCNTL),
9749 GEN_HANDLER(wrtee, 0x1F, 0x03, 0x04, 0x000FFC01, PPC_WRTEE),
9750 GEN_HANDLER(wrteei, 0x1F, 0x03, 0x05, 0x000E7C01, PPC_WRTEE),
9751 GEN_HANDLER(dlmzb, 0x1F, 0x0E, 0x02, 0x00000000, PPC_440_SPEC),
9752 GEN_HANDLER_E(mbar, 0x1F, 0x16, 0x1a, 0x001FF801,
9753 PPC_BOOKE, PPC2_BOOKE206),
9754 GEN_HANDLER(msync_4xx, 0x1F, 0x16, 0x12, 0x03FFF801, PPC_BOOKE),
9755 GEN_HANDLER2_E(icbt_440, "icbt", 0x1F, 0x16, 0x00, 0x03E00001,
9756 PPC_BOOKE, PPC2_BOOKE206),
9757 GEN_HANDLER(lvsl, 0x1f, 0x06, 0x00, 0x00000001, PPC_ALTIVEC),
9758 GEN_HANDLER(lvsr, 0x1f, 0x06, 0x01, 0x00000001, PPC_ALTIVEC),
9759 GEN_HANDLER(mfvscr, 0x04, 0x2, 0x18, 0x001ff800, PPC_ALTIVEC),
9760 GEN_HANDLER(mtvscr, 0x04, 0x2, 0x19, 0x03ff0000, PPC_ALTIVEC),
9761 GEN_HANDLER(vsldoi, 0x04, 0x16, 0xFF, 0x00000400, PPC_ALTIVEC),
9762 GEN_HANDLER(vmladduhm, 0x04, 0x11, 0xFF, 0x00000000, PPC_ALTIVEC),
9763 GEN_HANDLER2(evsel0, "evsel", 0x04, 0x1c, 0x09, 0x00000000, PPC_SPE),
9764 GEN_HANDLER2(evsel1, "evsel", 0x04, 0x1d, 0x09, 0x00000000, PPC_SPE),
9765 GEN_HANDLER2(evsel2, "evsel", 0x04, 0x1e, 0x09, 0x00000000, PPC_SPE),
9766 GEN_HANDLER2(evsel3, "evsel", 0x04, 0x1f, 0x09, 0x00000000, PPC_SPE),
9767
9768 #undef GEN_INT_ARITH_ADD
9769 #undef GEN_INT_ARITH_ADD_CONST
9770 #define GEN_INT_ARITH_ADD(name, opc3, add_ca, compute_ca, compute_ov) \
9771 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x00000000, PPC_INTEGER),
9772 #define GEN_INT_ARITH_ADD_CONST(name, opc3, const_val, \
9773 add_ca, compute_ca, compute_ov) \
9774 GEN_HANDLER(name, 0x1F, 0x0A, opc3, 0x0000F800, PPC_INTEGER),
9775 GEN_INT_ARITH_ADD(add, 0x08, 0, 0, 0)
9776 GEN_INT_ARITH_ADD(addo, 0x18, 0, 0, 1)
9777 GEN_INT_ARITH_ADD(addc, 0x00, 0, 1, 0)
9778 GEN_INT_ARITH_ADD(addco, 0x10, 0, 1, 1)
9779 GEN_INT_ARITH_ADD(adde, 0x04, 1, 1, 0)
9780 GEN_INT_ARITH_ADD(addeo, 0x14, 1, 1, 1)
9781 GEN_INT_ARITH_ADD_CONST(addme, 0x07, -1LL, 1, 1, 0)
9782 GEN_INT_ARITH_ADD_CONST(addmeo, 0x17, -1LL, 1, 1, 1)
9783 GEN_INT_ARITH_ADD_CONST(addze, 0x06, 0, 1, 1, 0)
9784 GEN_INT_ARITH_ADD_CONST(addzeo, 0x16, 0, 1, 1, 1)
9785
9786 #undef GEN_INT_ARITH_DIVW
9787 #define GEN_INT_ARITH_DIVW(name, opc3, sign, compute_ov) \
9788 GEN_HANDLER(name, 0x1F, 0x0B, opc3, 0x00000000, PPC_INTEGER)
9789 GEN_INT_ARITH_DIVW(divwu, 0x0E, 0, 0),
9790 GEN_INT_ARITH_DIVW(divwuo, 0x1E, 0, 1),
9791 GEN_INT_ARITH_DIVW(divw, 0x0F, 1, 0),
9792 GEN_INT_ARITH_DIVW(divwo, 0x1F, 1, 1),
9793 GEN_HANDLER_E(divwe, 0x1F, 0x0B, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9794 GEN_HANDLER_E(divweo, 0x1F, 0x0B, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9795 GEN_HANDLER_E(divweu, 0x1F, 0x0B, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9796 GEN_HANDLER_E(divweuo, 0x1F, 0x0B, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9797
9798 #if defined(TARGET_PPC64)
9799 #undef GEN_INT_ARITH_DIVD
9800 #define GEN_INT_ARITH_DIVD(name, opc3, sign, compute_ov) \
9801 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
9802 GEN_INT_ARITH_DIVD(divdu, 0x0E, 0, 0),
9803 GEN_INT_ARITH_DIVD(divduo, 0x1E, 0, 1),
9804 GEN_INT_ARITH_DIVD(divd, 0x0F, 1, 0),
9805 GEN_INT_ARITH_DIVD(divdo, 0x1F, 1, 1),
9806
9807 GEN_HANDLER_E(divdeu, 0x1F, 0x09, 0x0C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9808 GEN_HANDLER_E(divdeuo, 0x1F, 0x09, 0x1C, 0, PPC_NONE, PPC2_DIVE_ISA206),
9809 GEN_HANDLER_E(divde, 0x1F, 0x09, 0x0D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9810 GEN_HANDLER_E(divdeo, 0x1F, 0x09, 0x1D, 0, PPC_NONE, PPC2_DIVE_ISA206),
9811
9812 #undef GEN_INT_ARITH_MUL_HELPER
9813 #define GEN_INT_ARITH_MUL_HELPER(name, opc3) \
9814 GEN_HANDLER(name, 0x1F, 0x09, opc3, 0x00000000, PPC_64B)
9815 GEN_INT_ARITH_MUL_HELPER(mulhdu, 0x00),
9816 GEN_INT_ARITH_MUL_HELPER(mulhd, 0x02),
9817 GEN_INT_ARITH_MUL_HELPER(mulldo, 0x17),
9818 #endif
9819
9820 #undef GEN_INT_ARITH_SUBF
9821 #undef GEN_INT_ARITH_SUBF_CONST
9822 #define GEN_INT_ARITH_SUBF(name, opc3, add_ca, compute_ca, compute_ov) \
9823 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x00000000, PPC_INTEGER),
9824 #define GEN_INT_ARITH_SUBF_CONST(name, opc3, const_val, \
9825 add_ca, compute_ca, compute_ov) \
9826 GEN_HANDLER(name, 0x1F, 0x08, opc3, 0x0000F800, PPC_INTEGER),
9827 GEN_INT_ARITH_SUBF(subf, 0x01, 0, 0, 0)
9828 GEN_INT_ARITH_SUBF(subfo, 0x11, 0, 0, 1)
9829 GEN_INT_ARITH_SUBF(subfc, 0x00, 0, 1, 0)
9830 GEN_INT_ARITH_SUBF(subfco, 0x10, 0, 1, 1)
9831 GEN_INT_ARITH_SUBF(subfe, 0x04, 1, 1, 0)
9832 GEN_INT_ARITH_SUBF(subfeo, 0x14, 1, 1, 1)
9833 GEN_INT_ARITH_SUBF_CONST(subfme, 0x07, -1LL, 1, 1, 0)
9834 GEN_INT_ARITH_SUBF_CONST(subfmeo, 0x17, -1LL, 1, 1, 1)
9835 GEN_INT_ARITH_SUBF_CONST(subfze, 0x06, 0, 1, 1, 0)
9836 GEN_INT_ARITH_SUBF_CONST(subfzeo, 0x16, 0, 1, 1, 1)
9837
9838 #undef GEN_LOGICAL1
9839 #undef GEN_LOGICAL2
9840 #define GEN_LOGICAL2(name, tcg_op, opc, type) \
9841 GEN_HANDLER(name, 0x1F, 0x1C, opc, 0x00000000, type)
9842 #define GEN_LOGICAL1(name, tcg_op, opc, type) \
9843 GEN_HANDLER(name, 0x1F, 0x1A, opc, 0x00000000, type)
9844 GEN_LOGICAL2(and, tcg_gen_and_tl, 0x00, PPC_INTEGER),
9845 GEN_LOGICAL2(andc, tcg_gen_andc_tl, 0x01, PPC_INTEGER),
9846 GEN_LOGICAL2(eqv, tcg_gen_eqv_tl, 0x08, PPC_INTEGER),
9847 GEN_LOGICAL1(extsb, tcg_gen_ext8s_tl, 0x1D, PPC_INTEGER),
9848 GEN_LOGICAL1(extsh, tcg_gen_ext16s_tl, 0x1C, PPC_INTEGER),
9849 GEN_LOGICAL2(nand, tcg_gen_nand_tl, 0x0E, PPC_INTEGER),
9850 GEN_LOGICAL2(nor, tcg_gen_nor_tl, 0x03, PPC_INTEGER),
9851 GEN_LOGICAL2(orc, tcg_gen_orc_tl, 0x0C, PPC_INTEGER),
9852 #if defined(TARGET_PPC64)
9853 GEN_LOGICAL1(extsw, tcg_gen_ext32s_tl, 0x1E, PPC_64B),
9854 #endif
9855
9856 #if defined(TARGET_PPC64)
9857 #undef GEN_PPC64_R2
9858 #undef GEN_PPC64_R4
9859 #define GEN_PPC64_R2(name, opc1, opc2) \
9860 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
9861 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
9862 PPC_64B)
9863 #define GEN_PPC64_R4(name, opc1, opc2) \
9864 GEN_HANDLER2(name##0, stringify(name), opc1, opc2, 0xFF, 0x00000000, PPC_64B),\
9865 GEN_HANDLER2(name##1, stringify(name), opc1, opc2 | 0x01, 0xFF, 0x00000000, \
9866 PPC_64B), \
9867 GEN_HANDLER2(name##2, stringify(name), opc1, opc2 | 0x10, 0xFF, 0x00000000, \
9868 PPC_64B), \
9869 GEN_HANDLER2(name##3, stringify(name), opc1, opc2 | 0x11, 0xFF, 0x00000000, \
9870 PPC_64B)
9871 GEN_PPC64_R4(rldicl, 0x1E, 0x00),
9872 GEN_PPC64_R4(rldicr, 0x1E, 0x02),
9873 GEN_PPC64_R4(rldic, 0x1E, 0x04),
9874 GEN_PPC64_R2(rldcl, 0x1E, 0x08),
9875 GEN_PPC64_R2(rldcr, 0x1E, 0x09),
9876 GEN_PPC64_R4(rldimi, 0x1E, 0x06),
9877 #endif
9878
9879 #undef _GEN_FLOAT_ACB
9880 #undef GEN_FLOAT_ACB
9881 #undef _GEN_FLOAT_AB
9882 #undef GEN_FLOAT_AB
9883 #undef _GEN_FLOAT_AC
9884 #undef GEN_FLOAT_AC
9885 #undef GEN_FLOAT_B
9886 #undef GEN_FLOAT_BS
9887 #define _GEN_FLOAT_ACB(name, op, op1, op2, isfloat, set_fprf, type) \
9888 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x00000000, type)
9889 #define GEN_FLOAT_ACB(name, op2, set_fprf, type) \
9890 _GEN_FLOAT_ACB(name, name, 0x3F, op2, 0, set_fprf, type), \
9891 _GEN_FLOAT_ACB(name##s, name, 0x3B, op2, 1, set_fprf, type)
9892 #define _GEN_FLOAT_AB(name, op, op1, op2, inval, isfloat, set_fprf, type) \
9893 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
9894 #define GEN_FLOAT_AB(name, op2, inval, set_fprf, type) \
9895 _GEN_FLOAT_AB(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
9896 _GEN_FLOAT_AB(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
9897 #define _GEN_FLOAT_AC(name, op, op1, op2, inval, isfloat, set_fprf, type) \
9898 GEN_HANDLER(f##name, op1, op2, 0xFF, inval, type)
9899 #define GEN_FLOAT_AC(name, op2, inval, set_fprf, type) \
9900 _GEN_FLOAT_AC(name, name, 0x3F, op2, inval, 0, set_fprf, type), \
9901 _GEN_FLOAT_AC(name##s, name, 0x3B, op2, inval, 1, set_fprf, type)
9902 #define GEN_FLOAT_B(name, op2, op3, set_fprf, type) \
9903 GEN_HANDLER(f##name, 0x3F, op2, op3, 0x001F0000, type)
9904 #define GEN_FLOAT_BS(name, op1, op2, set_fprf, type) \
9905 GEN_HANDLER(f##name, op1, op2, 0xFF, 0x001F07C0, type)
9906
9907 GEN_FLOAT_AB(add, 0x15, 0x000007C0, 1, PPC_FLOAT),
9908 GEN_FLOAT_AB(div, 0x12, 0x000007C0, 1, PPC_FLOAT),
9909 GEN_FLOAT_AC(mul, 0x19, 0x0000F800, 1, PPC_FLOAT),
9910 GEN_FLOAT_BS(re, 0x3F, 0x18, 1, PPC_FLOAT_EXT),
9911 GEN_FLOAT_BS(res, 0x3B, 0x18, 1, PPC_FLOAT_FRES),
9912 GEN_FLOAT_BS(rsqrte, 0x3F, 0x1A, 1, PPC_FLOAT_FRSQRTE),
9913 _GEN_FLOAT_ACB(sel, sel, 0x3F, 0x17, 0, 0, PPC_FLOAT_FSEL),
9914 GEN_FLOAT_AB(sub, 0x14, 0x000007C0, 1, PPC_FLOAT),
9915 GEN_FLOAT_ACB(madd, 0x1D, 1, PPC_FLOAT),
9916 GEN_FLOAT_ACB(msub, 0x1C, 1, PPC_FLOAT),
9917 GEN_FLOAT_ACB(nmadd, 0x1F, 1, PPC_FLOAT),
9918 GEN_FLOAT_ACB(nmsub, 0x1E, 1, PPC_FLOAT),
9919 GEN_HANDLER_E(ftdiv, 0x3F, 0x00, 0x04, 1, PPC_NONE, PPC2_FP_TST_ISA206),
9920 GEN_HANDLER_E(ftsqrt, 0x3F, 0x00, 0x05, 1, PPC_NONE, PPC2_FP_TST_ISA206),
9921 GEN_FLOAT_B(ctiw, 0x0E, 0x00, 0, PPC_FLOAT),
9922 GEN_HANDLER_E(fctiwu, 0x3F, 0x0E, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
9923 GEN_FLOAT_B(ctiwz, 0x0F, 0x00, 0, PPC_FLOAT),
9924 GEN_HANDLER_E(fctiwuz, 0x3F, 0x0F, 0x04, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
9925 GEN_FLOAT_B(rsp, 0x0C, 0x00, 1, PPC_FLOAT),
9926 #if defined(TARGET_PPC64)
9927 GEN_FLOAT_B(cfid, 0x0E, 0x1A, 1, PPC_64B),
9928 GEN_HANDLER_E(fcfids, 0x3B, 0x0E, 0x1A, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
9929 GEN_HANDLER_E(fcfidu, 0x3F, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
9930 GEN_HANDLER_E(fcfidus, 0x3B, 0x0E, 0x1E, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
9931 GEN_FLOAT_B(ctid, 0x0E, 0x19, 0, PPC_64B),
9932 GEN_HANDLER_E(fctidu, 0x3F, 0x0E, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
9933 GEN_FLOAT_B(ctidz, 0x0F, 0x19, 0, PPC_64B),
9934 GEN_HANDLER_E(fctiduz, 0x3F, 0x0F, 0x1D, 0, PPC_NONE, PPC2_FP_CVT_ISA206),
9935 #endif
9936 GEN_FLOAT_B(rin, 0x08, 0x0C, 1, PPC_FLOAT_EXT),
9937 GEN_FLOAT_B(riz, 0x08, 0x0D, 1, PPC_FLOAT_EXT),
9938 GEN_FLOAT_B(rip, 0x08, 0x0E, 1, PPC_FLOAT_EXT),
9939 GEN_FLOAT_B(rim, 0x08, 0x0F, 1, PPC_FLOAT_EXT),
9940
9941 #undef GEN_LD
9942 #undef GEN_LDU
9943 #undef GEN_LDUX
9944 #undef GEN_LDX_E
9945 #undef GEN_LDS
9946 #define GEN_LD(name, ldop, opc, type) \
9947 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9948 #define GEN_LDU(name, ldop, opc, type) \
9949 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
9950 #define GEN_LDUX(name, ldop, opc2, opc3, type) \
9951 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
9952 #define GEN_LDX_E(name, ldop, opc2, opc3, type, type2) \
9953 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
9954 #define GEN_LDS(name, ldop, op, type) \
9955 GEN_LD(name, ldop, op | 0x20, type) \
9956 GEN_LDU(name, ldop, op | 0x21, type) \
9957 GEN_LDUX(name, ldop, 0x17, op | 0x01, type) \
9958 GEN_LDX(name, ldop, 0x17, op | 0x00, type)
9959
9960 GEN_LDS(lbz, ld8u, 0x02, PPC_INTEGER)
9961 GEN_LDS(lha, ld16s, 0x0A, PPC_INTEGER)
9962 GEN_LDS(lhz, ld16u, 0x08, PPC_INTEGER)
9963 GEN_LDS(lwz, ld32u, 0x00, PPC_INTEGER)
9964 #if defined(TARGET_PPC64)
9965 GEN_LDUX(lwa, ld32s, 0x15, 0x0B, PPC_64B)
9966 GEN_LDX(lwa, ld32s, 0x15, 0x0A, PPC_64B)
9967 GEN_LDUX(ld, ld64, 0x15, 0x01, PPC_64B)
9968 GEN_LDX(ld, ld64, 0x15, 0x00, PPC_64B)
9969 GEN_LDX_E(ldbr, ld64ur, 0x14, 0x10, PPC_NONE, PPC2_DBRX)
9970 #endif
9971 GEN_LDX(lhbr, ld16ur, 0x16, 0x18, PPC_INTEGER)
9972 GEN_LDX(lwbr, ld32ur, 0x16, 0x10, PPC_INTEGER)
9973
9974 #undef GEN_ST
9975 #undef GEN_STU
9976 #undef GEN_STUX
9977 #undef GEN_STX_E
9978 #undef GEN_STS
9979 #define GEN_ST(name, stop, opc, type) \
9980 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
9981 #define GEN_STU(name, stop, opc, type) \
9982 GEN_HANDLER(stop##u, opc, 0xFF, 0xFF, 0x00000000, type),
9983 #define GEN_STUX(name, stop, opc2, opc3, type) \
9984 GEN_HANDLER(name##ux, 0x1F, opc2, opc3, 0x00000001, type),
9985 #define GEN_STX_E(name, stop, opc2, opc3, type, type2) \
9986 GEN_HANDLER_E(name##x, 0x1F, opc2, opc3, 0x00000001, type, type2),
9987 #define GEN_STS(name, stop, op, type) \
9988 GEN_ST(name, stop, op | 0x20, type) \
9989 GEN_STU(name, stop, op | 0x21, type) \
9990 GEN_STUX(name, stop, 0x17, op | 0x01, type) \
9991 GEN_STX(name, stop, 0x17, op | 0x00, type)
9992
9993 GEN_STS(stb, st8, 0x06, PPC_INTEGER)
9994 GEN_STS(sth, st16, 0x0C, PPC_INTEGER)
9995 GEN_STS(stw, st32, 0x04, PPC_INTEGER)
9996 #if defined(TARGET_PPC64)
9997 GEN_STUX(std, st64, 0x15, 0x05, PPC_64B)
9998 GEN_STX(std, st64, 0x15, 0x04, PPC_64B)
9999 GEN_STX_E(stdbr, st64r, 0x14, 0x14, PPC_NONE, PPC2_DBRX)
10000 #endif
10001 GEN_STX(sthbr, st16r, 0x16, 0x1C, PPC_INTEGER)
10002 GEN_STX(stwbr, st32r, 0x16, 0x14, PPC_INTEGER)
10003
10004 #undef GEN_LDF
10005 #undef GEN_LDUF
10006 #undef GEN_LDUXF
10007 #undef GEN_LDXF
10008 #undef GEN_LDFS
10009 #define GEN_LDF(name, ldop, opc, type) \
10010 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10011 #define GEN_LDUF(name, ldop, opc, type) \
10012 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10013 #define GEN_LDUXF(name, ldop, opc, type) \
10014 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10015 #define GEN_LDXF(name, ldop, opc2, opc3, type) \
10016 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10017 #define GEN_LDFS(name, ldop, op, type) \
10018 GEN_LDF(name, ldop, op | 0x20, type) \
10019 GEN_LDUF(name, ldop, op | 0x21, type) \
10020 GEN_LDUXF(name, ldop, op | 0x01, type) \
10021 GEN_LDXF(name, ldop, 0x17, op | 0x00, type)
10022
10023 GEN_LDFS(lfd, ld64, 0x12, PPC_FLOAT)
10024 GEN_LDFS(lfs, ld32fs, 0x10, PPC_FLOAT)
10025 GEN_HANDLER_E(lfiwax, 0x1f, 0x17, 0x1a, 0x00000001, PPC_NONE, PPC2_ISA205),
10026 GEN_HANDLER_E(lfiwzx, 0x1f, 0x17, 0x1b, 0x1, PPC_NONE, PPC2_FP_CVT_ISA206),
10027 GEN_HANDLER_E(lfdp, 0x39, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10028 GEN_HANDLER_E(lfdpx, 0x1F, 0x17, 0x18, 0x00200001, PPC_NONE, PPC2_ISA205),
10029
10030 #undef GEN_STF
10031 #undef GEN_STUF
10032 #undef GEN_STUXF
10033 #undef GEN_STXF
10034 #undef GEN_STFS
10035 #define GEN_STF(name, stop, opc, type) \
10036 GEN_HANDLER(name, opc, 0xFF, 0xFF, 0x00000000, type),
10037 #define GEN_STUF(name, stop, opc, type) \
10038 GEN_HANDLER(name##u, opc, 0xFF, 0xFF, 0x00000000, type),
10039 #define GEN_STUXF(name, stop, opc, type) \
10040 GEN_HANDLER(name##ux, 0x1F, 0x17, opc, 0x00000001, type),
10041 #define GEN_STXF(name, stop, opc2, opc3, type) \
10042 GEN_HANDLER(name##x, 0x1F, opc2, opc3, 0x00000001, type),
10043 #define GEN_STFS(name, stop, op, type) \
10044 GEN_STF(name, stop, op | 0x20, type) \
10045 GEN_STUF(name, stop, op | 0x21, type) \
10046 GEN_STUXF(name, stop, op | 0x01, type) \
10047 GEN_STXF(name, stop, 0x17, op | 0x00, type)
10048
10049 GEN_STFS(stfd, st64, 0x16, PPC_FLOAT)
10050 GEN_STFS(stfs, st32fs, 0x14, PPC_FLOAT)
10051 GEN_STXF(stfiw, st32fiw, 0x17, 0x1E, PPC_FLOAT_STFIWX)
10052 GEN_HANDLER_E(stfdp, 0x3D, 0xFF, 0xFF, 0x00200003, PPC_NONE, PPC2_ISA205),
10053 GEN_HANDLER_E(stfdpx, 0x1F, 0x17, 0x1C, 0x00200001, PPC_NONE, PPC2_ISA205),
10054
10055 #undef GEN_CRLOGIC
10056 #define GEN_CRLOGIC(name, tcg_op, opc) \
10057 GEN_HANDLER(name, 0x13, 0x01, opc, 0x00000001, PPC_INTEGER)
10058 GEN_CRLOGIC(crand, tcg_gen_and_i32, 0x08),
10059 GEN_CRLOGIC(crandc, tcg_gen_andc_i32, 0x04),
10060 GEN_CRLOGIC(creqv, tcg_gen_eqv_i32, 0x09),
10061 GEN_CRLOGIC(crnand, tcg_gen_nand_i32, 0x07),
10062 GEN_CRLOGIC(crnor, tcg_gen_nor_i32, 0x01),
10063 GEN_CRLOGIC(cror, tcg_gen_or_i32, 0x0E),
10064 GEN_CRLOGIC(crorc, tcg_gen_orc_i32, 0x0D),
10065 GEN_CRLOGIC(crxor, tcg_gen_xor_i32, 0x06),
10066
10067 #undef GEN_MAC_HANDLER
10068 #define GEN_MAC_HANDLER(name, opc2, opc3) \
10069 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_405_MAC)
10070 GEN_MAC_HANDLER(macchw, 0x0C, 0x05),
10071 GEN_MAC_HANDLER(macchwo, 0x0C, 0x15),
10072 GEN_MAC_HANDLER(macchws, 0x0C, 0x07),
10073 GEN_MAC_HANDLER(macchwso, 0x0C, 0x17),
10074 GEN_MAC_HANDLER(macchwsu, 0x0C, 0x06),
10075 GEN_MAC_HANDLER(macchwsuo, 0x0C, 0x16),
10076 GEN_MAC_HANDLER(macchwu, 0x0C, 0x04),
10077 GEN_MAC_HANDLER(macchwuo, 0x0C, 0x14),
10078 GEN_MAC_HANDLER(machhw, 0x0C, 0x01),
10079 GEN_MAC_HANDLER(machhwo, 0x0C, 0x11),
10080 GEN_MAC_HANDLER(machhws, 0x0C, 0x03),
10081 GEN_MAC_HANDLER(machhwso, 0x0C, 0x13),
10082 GEN_MAC_HANDLER(machhwsu, 0x0C, 0x02),
10083 GEN_MAC_HANDLER(machhwsuo, 0x0C, 0x12),
10084 GEN_MAC_HANDLER(machhwu, 0x0C, 0x00),
10085 GEN_MAC_HANDLER(machhwuo, 0x0C, 0x10),
10086 GEN_MAC_HANDLER(maclhw, 0x0C, 0x0D),
10087 GEN_MAC_HANDLER(maclhwo, 0x0C, 0x1D),
10088 GEN_MAC_HANDLER(maclhws, 0x0C, 0x0F),
10089 GEN_MAC_HANDLER(maclhwso, 0x0C, 0x1F),
10090 GEN_MAC_HANDLER(maclhwu, 0x0C, 0x0C),
10091 GEN_MAC_HANDLER(maclhwuo, 0x0C, 0x1C),
10092 GEN_MAC_HANDLER(maclhwsu, 0x0C, 0x0E),
10093 GEN_MAC_HANDLER(maclhwsuo, 0x0C, 0x1E),
10094 GEN_MAC_HANDLER(nmacchw, 0x0E, 0x05),
10095 GEN_MAC_HANDLER(nmacchwo, 0x0E, 0x15),
10096 GEN_MAC_HANDLER(nmacchws, 0x0E, 0x07),
10097 GEN_MAC_HANDLER(nmacchwso, 0x0E, 0x17),
10098 GEN_MAC_HANDLER(nmachhw, 0x0E, 0x01),
10099 GEN_MAC_HANDLER(nmachhwo, 0x0E, 0x11),
10100 GEN_MAC_HANDLER(nmachhws, 0x0E, 0x03),
10101 GEN_MAC_HANDLER(nmachhwso, 0x0E, 0x13),
10102 GEN_MAC_HANDLER(nmaclhw, 0x0E, 0x0D),
10103 GEN_MAC_HANDLER(nmaclhwo, 0x0E, 0x1D),
10104 GEN_MAC_HANDLER(nmaclhws, 0x0E, 0x0F),
10105 GEN_MAC_HANDLER(nmaclhwso, 0x0E, 0x1F),
10106 GEN_MAC_HANDLER(mulchw, 0x08, 0x05),
10107 GEN_MAC_HANDLER(mulchwu, 0x08, 0x04),
10108 GEN_MAC_HANDLER(mulhhw, 0x08, 0x01),
10109 GEN_MAC_HANDLER(mulhhwu, 0x08, 0x00),
10110 GEN_MAC_HANDLER(mullhw, 0x08, 0x0D),
10111 GEN_MAC_HANDLER(mullhwu, 0x08, 0x0C),
10112
10113 #undef GEN_VR_LDX
10114 #undef GEN_VR_STX
10115 #undef GEN_VR_LVE
10116 #undef GEN_VR_STVE
10117 #define GEN_VR_LDX(name, opc2, opc3) \
10118 GEN_HANDLER(name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10119 #define GEN_VR_STX(name, opc2, opc3) \
10120 GEN_HANDLER(st##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10121 #define GEN_VR_LVE(name, opc2, opc3) \
10122 GEN_HANDLER(lve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10123 #define GEN_VR_STVE(name, opc2, opc3) \
10124 GEN_HANDLER(stve##name, 0x1F, opc2, opc3, 0x00000001, PPC_ALTIVEC)
10125 GEN_VR_LDX(lvx, 0x07, 0x03),
10126 GEN_VR_LDX(lvxl, 0x07, 0x0B),
10127 GEN_VR_LVE(bx, 0x07, 0x00),
10128 GEN_VR_LVE(hx, 0x07, 0x01),
10129 GEN_VR_LVE(wx, 0x07, 0x02),
10130 GEN_VR_STX(svx, 0x07, 0x07),
10131 GEN_VR_STX(svxl, 0x07, 0x0F),
10132 GEN_VR_STVE(bx, 0x07, 0x04),
10133 GEN_VR_STVE(hx, 0x07, 0x05),
10134 GEN_VR_STVE(wx, 0x07, 0x06),
10135
10136 #undef GEN_VX_LOGICAL
10137 #define GEN_VX_LOGICAL(name, tcg_op, opc2, opc3) \
10138 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10139 GEN_VX_LOGICAL(vand, tcg_gen_and_i64, 2, 16),
10140 GEN_VX_LOGICAL(vandc, tcg_gen_andc_i64, 2, 17),
10141 GEN_VX_LOGICAL(vor, tcg_gen_or_i64, 2, 18),
10142 GEN_VX_LOGICAL(vxor, tcg_gen_xor_i64, 2, 19),
10143 GEN_VX_LOGICAL(vnor, tcg_gen_nor_i64, 2, 20),
10144
10145 #undef GEN_VXFORM
10146 #define GEN_VXFORM(name, opc2, opc3) \
10147 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10148 GEN_VXFORM(vaddubm, 0, 0),
10149 GEN_VXFORM(vadduhm, 0, 1),
10150 GEN_VXFORM(vadduwm, 0, 2),
10151 GEN_VXFORM(vsububm, 0, 16),
10152 GEN_VXFORM(vsubuhm, 0, 17),
10153 GEN_VXFORM(vsubuwm, 0, 18),
10154 GEN_VXFORM(vmaxub, 1, 0),
10155 GEN_VXFORM(vmaxuh, 1, 1),
10156 GEN_VXFORM(vmaxuw, 1, 2),
10157 GEN_VXFORM(vmaxsb, 1, 4),
10158 GEN_VXFORM(vmaxsh, 1, 5),
10159 GEN_VXFORM(vmaxsw, 1, 6),
10160 GEN_VXFORM(vminub, 1, 8),
10161 GEN_VXFORM(vminuh, 1, 9),
10162 GEN_VXFORM(vminuw, 1, 10),
10163 GEN_VXFORM(vminsb, 1, 12),
10164 GEN_VXFORM(vminsh, 1, 13),
10165 GEN_VXFORM(vminsw, 1, 14),
10166 GEN_VXFORM(vavgub, 1, 16),
10167 GEN_VXFORM(vavguh, 1, 17),
10168 GEN_VXFORM(vavguw, 1, 18),
10169 GEN_VXFORM(vavgsb, 1, 20),
10170 GEN_VXFORM(vavgsh, 1, 21),
10171 GEN_VXFORM(vavgsw, 1, 22),
10172 GEN_VXFORM(vmrghb, 6, 0),
10173 GEN_VXFORM(vmrghh, 6, 1),
10174 GEN_VXFORM(vmrghw, 6, 2),
10175 GEN_VXFORM(vmrglb, 6, 4),
10176 GEN_VXFORM(vmrglh, 6, 5),
10177 GEN_VXFORM(vmrglw, 6, 6),
10178 GEN_VXFORM(vmuloub, 4, 0),
10179 GEN_VXFORM(vmulouh, 4, 1),
10180 GEN_VXFORM(vmulosb, 4, 4),
10181 GEN_VXFORM(vmulosh, 4, 5),
10182 GEN_VXFORM(vmuleub, 4, 8),
10183 GEN_VXFORM(vmuleuh, 4, 9),
10184 GEN_VXFORM(vmulesb, 4, 12),
10185 GEN_VXFORM(vmulesh, 4, 13),
10186 GEN_VXFORM(vslb, 2, 4),
10187 GEN_VXFORM(vslh, 2, 5),
10188 GEN_VXFORM(vslw, 2, 6),
10189 GEN_VXFORM(vsrb, 2, 8),
10190 GEN_VXFORM(vsrh, 2, 9),
10191 GEN_VXFORM(vsrw, 2, 10),
10192 GEN_VXFORM(vsrab, 2, 12),
10193 GEN_VXFORM(vsrah, 2, 13),
10194 GEN_VXFORM(vsraw, 2, 14),
10195 GEN_VXFORM(vslo, 6, 16),
10196 GEN_VXFORM(vsro, 6, 17),
10197 GEN_VXFORM(vaddcuw, 0, 6),
10198 GEN_VXFORM(vsubcuw, 0, 22),
10199 GEN_VXFORM(vaddubs, 0, 8),
10200 GEN_VXFORM(vadduhs, 0, 9),
10201 GEN_VXFORM(vadduws, 0, 10),
10202 GEN_VXFORM(vaddsbs, 0, 12),
10203 GEN_VXFORM(vaddshs, 0, 13),
10204 GEN_VXFORM(vaddsws, 0, 14),
10205 GEN_VXFORM(vsububs, 0, 24),
10206 GEN_VXFORM(vsubuhs, 0, 25),
10207 GEN_VXFORM(vsubuws, 0, 26),
10208 GEN_VXFORM(vsubsbs, 0, 28),
10209 GEN_VXFORM(vsubshs, 0, 29),
10210 GEN_VXFORM(vsubsws, 0, 30),
10211 GEN_VXFORM(vrlb, 2, 0),
10212 GEN_VXFORM(vrlh, 2, 1),
10213 GEN_VXFORM(vrlw, 2, 2),
10214 GEN_VXFORM(vsl, 2, 7),
10215 GEN_VXFORM(vsr, 2, 11),
10216 GEN_VXFORM(vpkuhum, 7, 0),
10217 GEN_VXFORM(vpkuwum, 7, 1),
10218 GEN_VXFORM(vpkuhus, 7, 2),
10219 GEN_VXFORM(vpkuwus, 7, 3),
10220 GEN_VXFORM(vpkshus, 7, 4),
10221 GEN_VXFORM(vpkswus, 7, 5),
10222 GEN_VXFORM(vpkshss, 7, 6),
10223 GEN_VXFORM(vpkswss, 7, 7),
10224 GEN_VXFORM(vpkpx, 7, 12),
10225 GEN_VXFORM(vsum4ubs, 4, 24),
10226 GEN_VXFORM(vsum4sbs, 4, 28),
10227 GEN_VXFORM(vsum4shs, 4, 25),
10228 GEN_VXFORM(vsum2sws, 4, 26),
10229 GEN_VXFORM(vsumsws, 4, 30),
10230 GEN_VXFORM(vaddfp, 5, 0),
10231 GEN_VXFORM(vsubfp, 5, 1),
10232 GEN_VXFORM(vmaxfp, 5, 16),
10233 GEN_VXFORM(vminfp, 5, 17),
10234
10235 #undef GEN_VXRFORM1
10236 #undef GEN_VXRFORM
10237 #define GEN_VXRFORM1(opname, name, str, opc2, opc3) \
10238 GEN_HANDLER2(name, str, 0x4, opc2, opc3, 0x00000000, PPC_ALTIVEC),
10239 #define GEN_VXRFORM(name, opc2, opc3) \
10240 GEN_VXRFORM1(name, name, #name, opc2, opc3) \
10241 GEN_VXRFORM1(name##_dot, name##_, #name ".", opc2, (opc3 | (0x1 << 4)))
10242 GEN_VXRFORM(vcmpequb, 3, 0)
10243 GEN_VXRFORM(vcmpequh, 3, 1)
10244 GEN_VXRFORM(vcmpequw, 3, 2)
10245 GEN_VXRFORM(vcmpgtsb, 3, 12)
10246 GEN_VXRFORM(vcmpgtsh, 3, 13)
10247 GEN_VXRFORM(vcmpgtsw, 3, 14)
10248 GEN_VXRFORM(vcmpgtub, 3, 8)
10249 GEN_VXRFORM(vcmpgtuh, 3, 9)
10250 GEN_VXRFORM(vcmpgtuw, 3, 10)
10251 GEN_VXRFORM(vcmpeqfp, 3, 3)
10252 GEN_VXRFORM(vcmpgefp, 3, 7)
10253 GEN_VXRFORM(vcmpgtfp, 3, 11)
10254 GEN_VXRFORM(vcmpbfp, 3, 15)
10255
10256 #undef GEN_VXFORM_SIMM
10257 #define GEN_VXFORM_SIMM(name, opc2, opc3) \
10258 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10259 GEN_VXFORM_SIMM(vspltisb, 6, 12),
10260 GEN_VXFORM_SIMM(vspltish, 6, 13),
10261 GEN_VXFORM_SIMM(vspltisw, 6, 14),
10262
10263 #undef GEN_VXFORM_NOA
10264 #define GEN_VXFORM_NOA(name, opc2, opc3) \
10265 GEN_HANDLER(name, 0x04, opc2, opc3, 0x001f0000, PPC_ALTIVEC)
10266 GEN_VXFORM_NOA(vupkhsb, 7, 8),
10267 GEN_VXFORM_NOA(vupkhsh, 7, 9),
10268 GEN_VXFORM_NOA(vupklsb, 7, 10),
10269 GEN_VXFORM_NOA(vupklsh, 7, 11),
10270 GEN_VXFORM_NOA(vupkhpx, 7, 13),
10271 GEN_VXFORM_NOA(vupklpx, 7, 15),
10272 GEN_VXFORM_NOA(vrefp, 5, 4),
10273 GEN_VXFORM_NOA(vrsqrtefp, 5, 5),
10274 GEN_VXFORM_NOA(vexptefp, 5, 6),
10275 GEN_VXFORM_NOA(vlogefp, 5, 7),
10276 GEN_VXFORM_NOA(vrfim, 5, 8),
10277 GEN_VXFORM_NOA(vrfin, 5, 9),
10278 GEN_VXFORM_NOA(vrfip, 5, 10),
10279 GEN_VXFORM_NOA(vrfiz, 5, 11),
10280
10281 #undef GEN_VXFORM_UIMM
10282 #define GEN_VXFORM_UIMM(name, opc2, opc3) \
10283 GEN_HANDLER(name, 0x04, opc2, opc3, 0x00000000, PPC_ALTIVEC)
10284 GEN_VXFORM_UIMM(vspltb, 6, 8),
10285 GEN_VXFORM_UIMM(vsplth, 6, 9),
10286 GEN_VXFORM_UIMM(vspltw, 6, 10),
10287 GEN_VXFORM_UIMM(vcfux, 5, 12),
10288 GEN_VXFORM_UIMM(vcfsx, 5, 13),
10289 GEN_VXFORM_UIMM(vctuxs, 5, 14),
10290 GEN_VXFORM_UIMM(vctsxs, 5, 15),
10291
10292 #undef GEN_VAFORM_PAIRED
10293 #define GEN_VAFORM_PAIRED(name0, name1, opc2) \
10294 GEN_HANDLER(name0##_##name1, 0x04, opc2, 0xFF, 0x00000000, PPC_ALTIVEC)
10295 GEN_VAFORM_PAIRED(vmhaddshs, vmhraddshs, 16),
10296 GEN_VAFORM_PAIRED(vmsumubm, vmsummbm, 18),
10297 GEN_VAFORM_PAIRED(vmsumuhm, vmsumuhs, 19),
10298 GEN_VAFORM_PAIRED(vmsumshm, vmsumshs, 20),
10299 GEN_VAFORM_PAIRED(vsel, vperm, 21),
10300 GEN_VAFORM_PAIRED(vmaddfp, vnmsubfp, 23),
10301
10302 GEN_HANDLER_E(lxsdx, 0x1F, 0x0C, 0x12, 0, PPC_NONE, PPC2_VSX),
10303 GEN_HANDLER_E(lxsiwax, 0x1F, 0x0C, 0x02, 0, PPC_NONE, PPC2_VSX207),
10304 GEN_HANDLER_E(lxsiwzx, 0x1F, 0x0C, 0x00, 0, PPC_NONE, PPC2_VSX207),
10305 GEN_HANDLER_E(lxsspx, 0x1F, 0x0C, 0x10, 0, PPC_NONE, PPC2_VSX207),
10306 GEN_HANDLER_E(lxvd2x, 0x1F, 0x0C, 0x1A, 0, PPC_NONE, PPC2_VSX),
10307 GEN_HANDLER_E(lxvdsx, 0x1F, 0x0C, 0x0A, 0, PPC_NONE, PPC2_VSX),
10308 GEN_HANDLER_E(lxvw4x, 0x1F, 0x0C, 0x18, 0, PPC_NONE, PPC2_VSX),
10309
10310 GEN_HANDLER_E(stxsdx, 0x1F, 0xC, 0x16, 0, PPC_NONE, PPC2_VSX),
10311 GEN_HANDLER_E(stxsiwx, 0x1F, 0xC, 0x04, 0, PPC_NONE, PPC2_VSX207),
10312 GEN_HANDLER_E(stxsspx, 0x1F, 0xC, 0x14, 0, PPC_NONE, PPC2_VSX207),
10313 GEN_HANDLER_E(stxvd2x, 0x1F, 0xC, 0x1E, 0, PPC_NONE, PPC2_VSX),
10314 GEN_HANDLER_E(stxvw4x, 0x1F, 0xC, 0x1C, 0, PPC_NONE, PPC2_VSX),
10315
10316 GEN_HANDLER_E(mfvsrwz, 0x1F, 0x13, 0x03, 0x0000F800, PPC_NONE, PPC2_VSX207),
10317 GEN_HANDLER_E(mtvsrwa, 0x1F, 0x13, 0x06, 0x0000F800, PPC_NONE, PPC2_VSX207),
10318 GEN_HANDLER_E(mtvsrwz, 0x1F, 0x13, 0x07, 0x0000F800, PPC_NONE, PPC2_VSX207),
10319 #if defined(TARGET_PPC64)
10320 GEN_HANDLER_E(mfvsrd, 0x1F, 0x13, 0x01, 0x0000F800, PPC_NONE, PPC2_VSX207),
10321 GEN_HANDLER_E(mtvsrd, 0x1F, 0x13, 0x05, 0x0000F800, PPC_NONE, PPC2_VSX207),
10322 #endif
10323
10324 #undef GEN_XX2FORM
10325 #define GEN_XX2FORM(name, opc2, opc3, fl2) \
10326 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10327 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2)
10328
10329 #undef GEN_XX3FORM
10330 #define GEN_XX3FORM(name, opc2, opc3, fl2) \
10331 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0, opc3, 0, PPC_NONE, fl2), \
10332 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 1, opc3, 0, PPC_NONE, fl2), \
10333 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 2, opc3, 0, PPC_NONE, fl2), \
10334 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 3, opc3, 0, PPC_NONE, fl2)
10335
10336 #undef GEN_XX3_RC_FORM
10337 #define GEN_XX3_RC_FORM(name, opc2, opc3, fl2) \
10338 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x00, 0, PPC_NONE, fl2), \
10339 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x00, 0, PPC_NONE, fl2), \
10340 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x00, 0, PPC_NONE, fl2), \
10341 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x00, 0, PPC_NONE, fl2), \
10342 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x00, opc3 | 0x10, 0, PPC_NONE, fl2), \
10343 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x01, opc3 | 0x10, 0, PPC_NONE, fl2), \
10344 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x02, opc3 | 0x10, 0, PPC_NONE, fl2), \
10345 GEN_HANDLER2_E(name, #name, 0x3C, opc2 | 0x03, opc3 | 0x10, 0, PPC_NONE, fl2)
10346
10347 #undef GEN_XX3FORM_DM
10348 #define GEN_XX3FORM_DM(name, opc2, opc3) \
10349 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10350 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10351 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10352 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x00, 0, PPC_NONE, PPC2_VSX),\
10353 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10354 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10355 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10356 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x04, 0, PPC_NONE, PPC2_VSX),\
10357 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10358 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10359 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10360 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x08, 0, PPC_NONE, PPC2_VSX),\
10361 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x00, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10362 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x01, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10363 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x02, opc3|0x0C, 0, PPC_NONE, PPC2_VSX),\
10364 GEN_HANDLER2_E(name, #name, 0x3C, opc2|0x03, opc3|0x0C, 0, PPC_NONE, PPC2_VSX)
10365
10366 GEN_XX2FORM(xsabsdp, 0x12, 0x15, PPC2_VSX),
10367 GEN_XX2FORM(xsnabsdp, 0x12, 0x16, PPC2_VSX),
10368 GEN_XX2FORM(xsnegdp, 0x12, 0x17, PPC2_VSX),
10369 GEN_XX3FORM(xscpsgndp, 0x00, 0x16, PPC2_VSX),
10370
10371 GEN_XX2FORM(xvabsdp, 0x12, 0x1D, PPC2_VSX),
10372 GEN_XX2FORM(xvnabsdp, 0x12, 0x1E, PPC2_VSX),
10373 GEN_XX2FORM(xvnegdp, 0x12, 0x1F, PPC2_VSX),
10374 GEN_XX3FORM(xvcpsgndp, 0x00, 0x1E, PPC2_VSX),
10375 GEN_XX2FORM(xvabssp, 0x12, 0x19, PPC2_VSX),
10376 GEN_XX2FORM(xvnabssp, 0x12, 0x1A, PPC2_VSX),
10377 GEN_XX2FORM(xvnegsp, 0x12, 0x1B, PPC2_VSX),
10378 GEN_XX3FORM(xvcpsgnsp, 0x00, 0x1A, PPC2_VSX),
10379
10380 GEN_XX3FORM(xsadddp, 0x00, 0x04, PPC2_VSX),
10381 GEN_XX3FORM(xssubdp, 0x00, 0x05, PPC2_VSX),
10382 GEN_XX3FORM(xsmuldp, 0x00, 0x06, PPC2_VSX),
10383 GEN_XX3FORM(xsdivdp, 0x00, 0x07, PPC2_VSX),
10384 GEN_XX2FORM(xsredp, 0x14, 0x05, PPC2_VSX),
10385 GEN_XX2FORM(xssqrtdp, 0x16, 0x04, PPC2_VSX),
10386 GEN_XX2FORM(xsrsqrtedp, 0x14, 0x04, PPC2_VSX),
10387 GEN_XX3FORM(xstdivdp, 0x14, 0x07, PPC2_VSX),
10388 GEN_XX2FORM(xstsqrtdp, 0x14, 0x06, PPC2_VSX),
10389 GEN_XX3FORM(xsmaddadp, 0x04, 0x04, PPC2_VSX),
10390 GEN_XX3FORM(xsmaddmdp, 0x04, 0x05, PPC2_VSX),
10391 GEN_XX3FORM(xsmsubadp, 0x04, 0x06, PPC2_VSX),
10392 GEN_XX3FORM(xsmsubmdp, 0x04, 0x07, PPC2_VSX),
10393 GEN_XX3FORM(xsnmaddadp, 0x04, 0x14, PPC2_VSX),
10394 GEN_XX3FORM(xsnmaddmdp, 0x04, 0x15, PPC2_VSX),
10395 GEN_XX3FORM(xsnmsubadp, 0x04, 0x16, PPC2_VSX),
10396 GEN_XX3FORM(xsnmsubmdp, 0x04, 0x17, PPC2_VSX),
10397 GEN_XX2FORM(xscmpodp, 0x0C, 0x05, PPC2_VSX),
10398 GEN_XX2FORM(xscmpudp, 0x0C, 0x04, PPC2_VSX),
10399 GEN_XX3FORM(xsmaxdp, 0x00, 0x14, PPC2_VSX),
10400 GEN_XX3FORM(xsmindp, 0x00, 0x15, PPC2_VSX),
10401 GEN_XX2FORM(xscvdpsp, 0x12, 0x10, PPC2_VSX),
10402 GEN_XX2FORM(xscvdpspn, 0x16, 0x10, PPC2_VSX207),
10403 GEN_XX2FORM(xscvspdp, 0x12, 0x14, PPC2_VSX),
10404 GEN_XX2FORM(xscvspdpn, 0x16, 0x14, PPC2_VSX207),
10405 GEN_XX2FORM(xscvdpsxds, 0x10, 0x15, PPC2_VSX),
10406 GEN_XX2FORM(xscvdpsxws, 0x10, 0x05, PPC2_VSX),
10407 GEN_XX2FORM(xscvdpuxds, 0x10, 0x14, PPC2_VSX),
10408 GEN_XX2FORM(xscvdpuxws, 0x10, 0x04, PPC2_VSX),
10409 GEN_XX2FORM(xscvsxddp, 0x10, 0x17, PPC2_VSX),
10410 GEN_XX2FORM(xscvuxddp, 0x10, 0x16, PPC2_VSX),
10411 GEN_XX2FORM(xsrdpi, 0x12, 0x04, PPC2_VSX),
10412 GEN_XX2FORM(xsrdpic, 0x16, 0x06, PPC2_VSX),
10413 GEN_XX2FORM(xsrdpim, 0x12, 0x07, PPC2_VSX),
10414 GEN_XX2FORM(xsrdpip, 0x12, 0x06, PPC2_VSX),
10415 GEN_XX2FORM(xsrdpiz, 0x12, 0x05, PPC2_VSX),
10416
10417 GEN_XX3FORM(xsaddsp, 0x00, 0x00, PPC2_VSX207),
10418 GEN_XX3FORM(xssubsp, 0x00, 0x01, PPC2_VSX207),
10419 GEN_XX3FORM(xsmulsp, 0x00, 0x02, PPC2_VSX207),
10420 GEN_XX3FORM(xsdivsp, 0x00, 0x03, PPC2_VSX207),
10421 GEN_XX2FORM(xsresp, 0x14, 0x01, PPC2_VSX207),
10422 GEN_XX2FORM(xsrsp, 0x12, 0x11, PPC2_VSX207),
10423 GEN_XX2FORM(xssqrtsp, 0x16, 0x00, PPC2_VSX207),
10424 GEN_XX2FORM(xsrsqrtesp, 0x14, 0x00, PPC2_VSX207),
10425 GEN_XX3FORM(xsmaddasp, 0x04, 0x00, PPC2_VSX207),
10426 GEN_XX3FORM(xsmaddmsp, 0x04, 0x01, PPC2_VSX207),
10427 GEN_XX3FORM(xsmsubasp, 0x04, 0x02, PPC2_VSX207),
10428 GEN_XX3FORM(xsmsubmsp, 0x04, 0x03, PPC2_VSX207),
10429 GEN_XX3FORM(xsnmaddasp, 0x04, 0x10, PPC2_VSX207),
10430 GEN_XX3FORM(xsnmaddmsp, 0x04, 0x11, PPC2_VSX207),
10431 GEN_XX3FORM(xsnmsubasp, 0x04, 0x12, PPC2_VSX207),
10432 GEN_XX3FORM(xsnmsubmsp, 0x04, 0x13, PPC2_VSX207),
10433 GEN_XX2FORM(xscvsxdsp, 0x10, 0x13, PPC2_VSX207),
10434 GEN_XX2FORM(xscvuxdsp, 0x10, 0x12, PPC2_VSX207),
10435
10436 GEN_XX3FORM(xvadddp, 0x00, 0x0C, PPC2_VSX),
10437 GEN_XX3FORM(xvsubdp, 0x00, 0x0D, PPC2_VSX),
10438 GEN_XX3FORM(xvmuldp, 0x00, 0x0E, PPC2_VSX),
10439 GEN_XX3FORM(xvdivdp, 0x00, 0x0F, PPC2_VSX),
10440 GEN_XX2FORM(xvredp, 0x14, 0x0D, PPC2_VSX),
10441 GEN_XX2FORM(xvsqrtdp, 0x16, 0x0C, PPC2_VSX),
10442 GEN_XX2FORM(xvrsqrtedp, 0x14, 0x0C, PPC2_VSX),
10443 GEN_XX3FORM(xvtdivdp, 0x14, 0x0F, PPC2_VSX),
10444 GEN_XX2FORM(xvtsqrtdp, 0x14, 0x0E, PPC2_VSX),
10445 GEN_XX3FORM(xvmaddadp, 0x04, 0x0C, PPC2_VSX),
10446 GEN_XX3FORM(xvmaddmdp, 0x04, 0x0D, PPC2_VSX),
10447 GEN_XX3FORM(xvmsubadp, 0x04, 0x0E, PPC2_VSX),
10448 GEN_XX3FORM(xvmsubmdp, 0x04, 0x0F, PPC2_VSX),
10449 GEN_XX3FORM(xvnmaddadp, 0x04, 0x1C, PPC2_VSX),
10450 GEN_XX3FORM(xvnmaddmdp, 0x04, 0x1D, PPC2_VSX),
10451 GEN_XX3FORM(xvnmsubadp, 0x04, 0x1E, PPC2_VSX),
10452 GEN_XX3FORM(xvnmsubmdp, 0x04, 0x1F, PPC2_VSX),
10453 GEN_XX3FORM(xvmaxdp, 0x00, 0x1C, PPC2_VSX),
10454 GEN_XX3FORM(xvmindp, 0x00, 0x1D, PPC2_VSX),
10455 GEN_XX3_RC_FORM(xvcmpeqdp, 0x0C, 0x0C, PPC2_VSX),
10456 GEN_XX3_RC_FORM(xvcmpgtdp, 0x0C, 0x0D, PPC2_VSX),
10457 GEN_XX3_RC_FORM(xvcmpgedp, 0x0C, 0x0E, PPC2_VSX),
10458 GEN_XX2FORM(xvcvdpsp, 0x12, 0x18, PPC2_VSX),
10459 GEN_XX2FORM(xvcvdpsxds, 0x10, 0x1D, PPC2_VSX),
10460 GEN_XX2FORM(xvcvdpsxws, 0x10, 0x0D, PPC2_VSX),
10461 GEN_XX2FORM(xvcvdpuxds, 0x10, 0x1C, PPC2_VSX),
10462 GEN_XX2FORM(xvcvdpuxws, 0x10, 0x0C, PPC2_VSX),
10463 GEN_XX2FORM(xvcvsxddp, 0x10, 0x1F, PPC2_VSX),
10464 GEN_XX2FORM(xvcvuxddp, 0x10, 0x1E, PPC2_VSX),
10465 GEN_XX2FORM(xvcvsxwdp, 0x10, 0x0F, PPC2_VSX),
10466 GEN_XX2FORM(xvcvuxwdp, 0x10, 0x0E, PPC2_VSX),
10467 GEN_XX2FORM(xvrdpi, 0x12, 0x0C, PPC2_VSX),
10468 GEN_XX2FORM(xvrdpic, 0x16, 0x0E, PPC2_VSX),
10469 GEN_XX2FORM(xvrdpim, 0x12, 0x0F, PPC2_VSX),
10470 GEN_XX2FORM(xvrdpip, 0x12, 0x0E, PPC2_VSX),
10471 GEN_XX2FORM(xvrdpiz, 0x12, 0x0D, PPC2_VSX),
10472
10473 GEN_XX3FORM(xvaddsp, 0x00, 0x08, PPC2_VSX),
10474 GEN_XX3FORM(xvsubsp, 0x00, 0x09, PPC2_VSX),
10475 GEN_XX3FORM(xvmulsp, 0x00, 0x0A, PPC2_VSX),
10476 GEN_XX3FORM(xvdivsp, 0x00, 0x0B, PPC2_VSX),
10477 GEN_XX2FORM(xvresp, 0x14, 0x09, PPC2_VSX),
10478 GEN_XX2FORM(xvsqrtsp, 0x16, 0x08, PPC2_VSX),
10479 GEN_XX2FORM(xvrsqrtesp, 0x14, 0x08, PPC2_VSX),
10480 GEN_XX3FORM(xvtdivsp, 0x14, 0x0B, PPC2_VSX),
10481 GEN_XX2FORM(xvtsqrtsp, 0x14, 0x0A, PPC2_VSX),
10482 GEN_XX3FORM(xvmaddasp, 0x04, 0x08, PPC2_VSX),
10483 GEN_XX3FORM(xvmaddmsp, 0x04, 0x09, PPC2_VSX),
10484 GEN_XX3FORM(xvmsubasp, 0x04, 0x0A, PPC2_VSX),
10485 GEN_XX3FORM(xvmsubmsp, 0x04, 0x0B, PPC2_VSX),
10486 GEN_XX3FORM(xvnmaddasp, 0x04, 0x18, PPC2_VSX),
10487 GEN_XX3FORM(xvnmaddmsp, 0x04, 0x19, PPC2_VSX),
10488 GEN_XX3FORM(xvnmsubasp, 0x04, 0x1A, PPC2_VSX),
10489 GEN_XX3FORM(xvnmsubmsp, 0x04, 0x1B, PPC2_VSX),
10490 GEN_XX3FORM(xvmaxsp, 0x00, 0x18, PPC2_VSX),
10491 GEN_XX3FORM(xvminsp, 0x00, 0x19, PPC2_VSX),
10492 GEN_XX3_RC_FORM(xvcmpeqsp, 0x0C, 0x08, PPC2_VSX),
10493 GEN_XX3_RC_FORM(xvcmpgtsp, 0x0C, 0x09, PPC2_VSX),
10494 GEN_XX3_RC_FORM(xvcmpgesp, 0x0C, 0x0A, PPC2_VSX),
10495 GEN_XX2FORM(xvcvspdp, 0x12, 0x1C, PPC2_VSX),
10496 GEN_XX2FORM(xvcvspsxds, 0x10, 0x19, PPC2_VSX),
10497 GEN_XX2FORM(xvcvspsxws, 0x10, 0x09, PPC2_VSX),
10498 GEN_XX2FORM(xvcvspuxds, 0x10, 0x18, PPC2_VSX),
10499 GEN_XX2FORM(xvcvspuxws, 0x10, 0x08, PPC2_VSX),
10500 GEN_XX2FORM(xvcvsxdsp, 0x10, 0x1B, PPC2_VSX),
10501 GEN_XX2FORM(xvcvuxdsp, 0x10, 0x1A, PPC2_VSX),
10502 GEN_XX2FORM(xvcvsxwsp, 0x10, 0x0B, PPC2_VSX),
10503 GEN_XX2FORM(xvcvuxwsp, 0x10, 0x0A, PPC2_VSX),
10504 GEN_XX2FORM(xvrspi, 0x12, 0x08, PPC2_VSX),
10505 GEN_XX2FORM(xvrspic, 0x16, 0x0A, PPC2_VSX),
10506 GEN_XX2FORM(xvrspim, 0x12, 0x0B, PPC2_VSX),
10507 GEN_XX2FORM(xvrspip, 0x12, 0x0A, PPC2_VSX),
10508 GEN_XX2FORM(xvrspiz, 0x12, 0x09, PPC2_VSX),
10509
10510 #undef VSX_LOGICAL
10511 #define VSX_LOGICAL(name, opc2, opc3, fl2) \
10512 GEN_XX3FORM(name, opc2, opc3, fl2)
10513
10514 VSX_LOGICAL(xxland, 0x8, 0x10, PPC2_VSX),
10515 VSX_LOGICAL(xxlandc, 0x8, 0x11, PPC2_VSX),
10516 VSX_LOGICAL(xxlor, 0x8, 0x12, PPC2_VSX),
10517 VSX_LOGICAL(xxlxor, 0x8, 0x13, PPC2_VSX),
10518 VSX_LOGICAL(xxlnor, 0x8, 0x14, PPC2_VSX),
10519 VSX_LOGICAL(xxleqv, 0x8, 0x17, PPC2_VSX207),
10520 VSX_LOGICAL(xxlnand, 0x8, 0x16, PPC2_VSX207),
10521 VSX_LOGICAL(xxlorc, 0x8, 0x15, PPC2_VSX207),
10522 GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX),
10523 GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX),
10524 GEN_XX2FORM(xxspltw, 0x08, 0x0A, PPC2_VSX),
10525 GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00),
10526
10527 #define GEN_XXSEL_ROW(opc3) \
10528 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x18, opc3, 0, PPC_NONE, PPC2_VSX), \
10529 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x19, opc3, 0, PPC_NONE, PPC2_VSX), \
10530 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1A, opc3, 0, PPC_NONE, PPC2_VSX), \
10531 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1B, opc3, 0, PPC_NONE, PPC2_VSX), \
10532 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1C, opc3, 0, PPC_NONE, PPC2_VSX), \
10533 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1D, opc3, 0, PPC_NONE, PPC2_VSX), \
10534 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1E, opc3, 0, PPC_NONE, PPC2_VSX), \
10535 GEN_HANDLER2_E(xxsel, "xxsel", 0x3C, 0x1F, opc3, 0, PPC_NONE, PPC2_VSX), \
10536
10537 GEN_XXSEL_ROW(0x00)
10538 GEN_XXSEL_ROW(0x01)
10539 GEN_XXSEL_ROW(0x02)
10540 GEN_XXSEL_ROW(0x03)
10541 GEN_XXSEL_ROW(0x04)
10542 GEN_XXSEL_ROW(0x05)
10543 GEN_XXSEL_ROW(0x06)
10544 GEN_XXSEL_ROW(0x07)
10545 GEN_XXSEL_ROW(0x08)
10546 GEN_XXSEL_ROW(0x09)
10547 GEN_XXSEL_ROW(0x0A)
10548 GEN_XXSEL_ROW(0x0B)
10549 GEN_XXSEL_ROW(0x0C)
10550 GEN_XXSEL_ROW(0x0D)
10551 GEN_XXSEL_ROW(0x0E)
10552 GEN_XXSEL_ROW(0x0F)
10553 GEN_XXSEL_ROW(0x10)
10554 GEN_XXSEL_ROW(0x11)
10555 GEN_XXSEL_ROW(0x12)
10556 GEN_XXSEL_ROW(0x13)
10557 GEN_XXSEL_ROW(0x14)
10558 GEN_XXSEL_ROW(0x15)
10559 GEN_XXSEL_ROW(0x16)
10560 GEN_XXSEL_ROW(0x17)
10561 GEN_XXSEL_ROW(0x18)
10562 GEN_XXSEL_ROW(0x19)
10563 GEN_XXSEL_ROW(0x1A)
10564 GEN_XXSEL_ROW(0x1B)
10565 GEN_XXSEL_ROW(0x1C)
10566 GEN_XXSEL_ROW(0x1D)
10567 GEN_XXSEL_ROW(0x1E)
10568 GEN_XXSEL_ROW(0x1F)
10569
10570 GEN_XX3FORM_DM(xxpermdi, 0x08, 0x01),
10571
10572 #undef GEN_SPE
10573 #define GEN_SPE(name0, name1, opc2, opc3, inval0, inval1, type) \
10574 GEN_OPCODE_DUAL(name0##_##name1, 0x04, opc2, opc3, inval0, inval1, type, PPC_NONE)
10575 GEN_SPE(evaddw, speundef, 0x00, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10576 GEN_SPE(evaddiw, speundef, 0x01, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10577 GEN_SPE(evsubfw, speundef, 0x02, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10578 GEN_SPE(evsubifw, speundef, 0x03, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10579 GEN_SPE(evabs, evneg, 0x04, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10580 GEN_SPE(evextsb, evextsh, 0x05, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10581 GEN_SPE(evrndw, evcntlzw, 0x06, 0x08, 0x0000F800, 0x0000F800, PPC_SPE),
10582 GEN_SPE(evcntlsw, brinc, 0x07, 0x08, 0x0000F800, 0x00000000, PPC_SPE),
10583 GEN_SPE(evmra, speundef, 0x02, 0x13, 0x0000F800, 0xFFFFFFFF, PPC_SPE),
10584 GEN_SPE(speundef, evand, 0x08, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
10585 GEN_SPE(evandc, speundef, 0x09, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10586 GEN_SPE(evxor, evor, 0x0B, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10587 GEN_SPE(evnor, eveqv, 0x0C, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10588 GEN_SPE(evmwumi, evmwsmi, 0x0C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
10589 GEN_SPE(evmwumia, evmwsmia, 0x1C, 0x11, 0x00000000, 0x00000000, PPC_SPE),
10590 GEN_SPE(evmwumiaa, evmwsmiaa, 0x0C, 0x15, 0x00000000, 0x00000000, PPC_SPE),
10591 GEN_SPE(speundef, evorc, 0x0D, 0x08, 0xFFFFFFFF, 0x00000000, PPC_SPE),
10592 GEN_SPE(evnand, speundef, 0x0F, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10593 GEN_SPE(evsrwu, evsrws, 0x10, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10594 GEN_SPE(evsrwiu, evsrwis, 0x11, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10595 GEN_SPE(evslw, speundef, 0x12, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10596 GEN_SPE(evslwi, speundef, 0x13, 0x08, 0x00000000, 0xFFFFFFFF, PPC_SPE),
10597 GEN_SPE(evrlw, evsplati, 0x14, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
10598 GEN_SPE(evrlwi, evsplatfi, 0x15, 0x08, 0x00000000, 0x0000F800, PPC_SPE),
10599 GEN_SPE(evmergehi, evmergelo, 0x16, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10600 GEN_SPE(evmergehilo, evmergelohi, 0x17, 0x08, 0x00000000, 0x00000000, PPC_SPE),
10601 GEN_SPE(evcmpgtu, evcmpgts, 0x18, 0x08, 0x00600000, 0x00600000, PPC_SPE),
10602 GEN_SPE(evcmpltu, evcmplts, 0x19, 0x08, 0x00600000, 0x00600000, PPC_SPE),
10603 GEN_SPE(evcmpeq, speundef, 0x1A, 0x08, 0x00600000, 0xFFFFFFFF, PPC_SPE),
10604
10605 GEN_SPE(evfsadd, evfssub, 0x00, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10606 GEN_SPE(evfsabs, evfsnabs, 0x02, 0x0A, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
10607 GEN_SPE(evfsneg, speundef, 0x03, 0x0A, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
10608 GEN_SPE(evfsmul, evfsdiv, 0x04, 0x0A, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10609 GEN_SPE(evfscmpgt, evfscmplt, 0x06, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10610 GEN_SPE(evfscmpeq, speundef, 0x07, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10611 GEN_SPE(evfscfui, evfscfsi, 0x08, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10612 GEN_SPE(evfscfuf, evfscfsf, 0x09, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10613 GEN_SPE(evfsctui, evfsctsi, 0x0A, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10614 GEN_SPE(evfsctuf, evfsctsf, 0x0B, 0x0A, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10615 GEN_SPE(evfsctuiz, speundef, 0x0C, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10616 GEN_SPE(evfsctsiz, speundef, 0x0D, 0x0A, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10617 GEN_SPE(evfststgt, evfststlt, 0x0E, 0x0A, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10618 GEN_SPE(evfststeq, speundef, 0x0F, 0x0A, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10619
10620 GEN_SPE(efsadd, efssub, 0x00, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10621 GEN_SPE(efsabs, efsnabs, 0x02, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_SINGLE),
10622 GEN_SPE(efsneg, speundef, 0x03, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_SINGLE),
10623 GEN_SPE(efsmul, efsdiv, 0x04, 0x0B, 0x00000000, 0x00000000, PPC_SPE_SINGLE),
10624 GEN_SPE(efscmpgt, efscmplt, 0x06, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10625 GEN_SPE(efscmpeq, efscfd, 0x07, 0x0B, 0x00600000, 0x00180000, PPC_SPE_SINGLE),
10626 GEN_SPE(efscfui, efscfsi, 0x08, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10627 GEN_SPE(efscfuf, efscfsf, 0x09, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10628 GEN_SPE(efsctui, efsctsi, 0x0A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10629 GEN_SPE(efsctuf, efsctsf, 0x0B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_SINGLE),
10630 GEN_SPE(efsctuiz, speundef, 0x0C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10631 GEN_SPE(efsctsiz, speundef, 0x0D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10632 GEN_SPE(efststgt, efststlt, 0x0E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_SINGLE),
10633 GEN_SPE(efststeq, speundef, 0x0F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_SINGLE),
10634
10635 GEN_SPE(efdadd, efdsub, 0x10, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
10636 GEN_SPE(efdcfuid, efdcfsid, 0x11, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10637 GEN_SPE(efdabs, efdnabs, 0x12, 0x0B, 0x0000F800, 0x0000F800, PPC_SPE_DOUBLE),
10638 GEN_SPE(efdneg, speundef, 0x13, 0x0B, 0x0000F800, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10639 GEN_SPE(efdmul, efddiv, 0x14, 0x0B, 0x00000000, 0x00000000, PPC_SPE_DOUBLE),
10640 GEN_SPE(efdctuidz, efdctsidz, 0x15, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10641 GEN_SPE(efdcmpgt, efdcmplt, 0x16, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
10642 GEN_SPE(efdcmpeq, efdcfs, 0x17, 0x0B, 0x00600000, 0x00180000, PPC_SPE_DOUBLE),
10643 GEN_SPE(efdcfui, efdcfsi, 0x18, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10644 GEN_SPE(efdcfuf, efdcfsf, 0x19, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10645 GEN_SPE(efdctui, efdctsi, 0x1A, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10646 GEN_SPE(efdctuf, efdctsf, 0x1B, 0x0B, 0x00180000, 0x00180000, PPC_SPE_DOUBLE),
10647 GEN_SPE(efdctuiz, speundef, 0x1C, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10648 GEN_SPE(efdctsiz, speundef, 0x1D, 0x0B, 0x00180000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10649 GEN_SPE(efdtstgt, efdtstlt, 0x1E, 0x0B, 0x00600000, 0x00600000, PPC_SPE_DOUBLE),
10650 GEN_SPE(efdtsteq, speundef, 0x1F, 0x0B, 0x00600000, 0xFFFFFFFF, PPC_SPE_DOUBLE),
10651
10652 #undef GEN_SPEOP_LDST
10653 #define GEN_SPEOP_LDST(name, opc2, sh) \
10654 GEN_HANDLER(name, 0x04, opc2, 0x0C, 0x00000000, PPC_SPE)
10655 GEN_SPEOP_LDST(evldd, 0x00, 3),
10656 GEN_SPEOP_LDST(evldw, 0x01, 3),
10657 GEN_SPEOP_LDST(evldh, 0x02, 3),
10658 GEN_SPEOP_LDST(evlhhesplat, 0x04, 1),
10659 GEN_SPEOP_LDST(evlhhousplat, 0x06, 1),
10660 GEN_SPEOP_LDST(evlhhossplat, 0x07, 1),
10661 GEN_SPEOP_LDST(evlwhe, 0x08, 2),
10662 GEN_SPEOP_LDST(evlwhou, 0x0A, 2),
10663 GEN_SPEOP_LDST(evlwhos, 0x0B, 2),
10664 GEN_SPEOP_LDST(evlwwsplat, 0x0C, 2),
10665 GEN_SPEOP_LDST(evlwhsplat, 0x0E, 2),
10666
10667 GEN_SPEOP_LDST(evstdd, 0x10, 3),
10668 GEN_SPEOP_LDST(evstdw, 0x11, 3),
10669 GEN_SPEOP_LDST(evstdh, 0x12, 3),
10670 GEN_SPEOP_LDST(evstwhe, 0x18, 2),
10671 GEN_SPEOP_LDST(evstwho, 0x1A, 2),
10672 GEN_SPEOP_LDST(evstwwe, 0x1C, 2),
10673 GEN_SPEOP_LDST(evstwwo, 0x1E, 2),
10674 };
10675
10676 #include "helper_regs.h"
10677 #include "translate_init.c"
10678
10679 /*****************************************************************************/
10680 /* Misc PowerPC helpers */
10681 void ppc_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf,
10682 int flags)
10683 {
10684 #define RGPL 4
10685 #define RFPL 4
10686
10687 PowerPCCPU *cpu = POWERPC_CPU(cs);
10688 CPUPPCState *env = &cpu->env;
10689 int i;
10690
10691 cpu_fprintf(f, "NIP " TARGET_FMT_lx " LR " TARGET_FMT_lx " CTR "
10692 TARGET_FMT_lx " XER " TARGET_FMT_lx "\n",
10693 env->nip, env->lr, env->ctr, cpu_read_xer(env));
10694 cpu_fprintf(f, "MSR " TARGET_FMT_lx " HID0 " TARGET_FMT_lx " HF "
10695 TARGET_FMT_lx " idx %d\n", env->msr, env->spr[SPR_HID0],
10696 env->hflags, env->mmu_idx);
10697 #if !defined(NO_TIMER_DUMP)
10698 cpu_fprintf(f, "TB %08" PRIu32 " %08" PRIu64
10699 #if !defined(CONFIG_USER_ONLY)
10700 " DECR %08" PRIu32
10701 #endif
10702 "\n",
10703 cpu_ppc_load_tbu(env), cpu_ppc_load_tbl(env)
10704 #if !defined(CONFIG_USER_ONLY)
10705 , cpu_ppc_load_decr(env)
10706 #endif
10707 );
10708 #endif
10709 for (i = 0; i < 32; i++) {
10710 if ((i & (RGPL - 1)) == 0)
10711 cpu_fprintf(f, "GPR%02d", i);
10712 cpu_fprintf(f, " %016" PRIx64, ppc_dump_gpr(env, i));
10713 if ((i & (RGPL - 1)) == (RGPL - 1))
10714 cpu_fprintf(f, "\n");
10715 }
10716 cpu_fprintf(f, "CR ");
10717 for (i = 0; i < 8; i++)
10718 cpu_fprintf(f, "%01x", env->crf[i]);
10719 cpu_fprintf(f, " [");
10720 for (i = 0; i < 8; i++) {
10721 char a = '-';
10722 if (env->crf[i] & 0x08)
10723 a = 'L';
10724 else if (env->crf[i] & 0x04)
10725 a = 'G';
10726 else if (env->crf[i] & 0x02)
10727 a = 'E';
10728 cpu_fprintf(f, " %c%c", a, env->crf[i] & 0x01 ? 'O' : ' ');
10729 }
10730 cpu_fprintf(f, " ] RES " TARGET_FMT_lx "\n",
10731 env->reserve_addr);
10732 for (i = 0; i < 32; i++) {
10733 if ((i & (RFPL - 1)) == 0)
10734 cpu_fprintf(f, "FPR%02d", i);
10735 cpu_fprintf(f, " %016" PRIx64, *((uint64_t *)&env->fpr[i]));
10736 if ((i & (RFPL - 1)) == (RFPL - 1))
10737 cpu_fprintf(f, "\n");
10738 }
10739 cpu_fprintf(f, "FPSCR " TARGET_FMT_lx "\n", env->fpscr);
10740 #if !defined(CONFIG_USER_ONLY)
10741 cpu_fprintf(f, " SRR0 " TARGET_FMT_lx " SRR1 " TARGET_FMT_lx
10742 " PVR " TARGET_FMT_lx " VRSAVE " TARGET_FMT_lx "\n",
10743 env->spr[SPR_SRR0], env->spr[SPR_SRR1],
10744 env->spr[SPR_PVR], env->spr[SPR_VRSAVE]);
10745
10746 cpu_fprintf(f, "SPRG0 " TARGET_FMT_lx " SPRG1 " TARGET_FMT_lx
10747 " SPRG2 " TARGET_FMT_lx " SPRG3 " TARGET_FMT_lx "\n",
10748 env->spr[SPR_SPRG0], env->spr[SPR_SPRG1],
10749 env->spr[SPR_SPRG2], env->spr[SPR_SPRG3]);
10750
10751 cpu_fprintf(f, "SPRG4 " TARGET_FMT_lx " SPRG5 " TARGET_FMT_lx
10752 " SPRG6 " TARGET_FMT_lx " SPRG7 " TARGET_FMT_lx "\n",
10753 env->spr[SPR_SPRG4], env->spr[SPR_SPRG5],
10754 env->spr[SPR_SPRG6], env->spr[SPR_SPRG7]);
10755
10756 if (env->excp_model == POWERPC_EXCP_BOOKE) {
10757 cpu_fprintf(f, "CSRR0 " TARGET_FMT_lx " CSRR1 " TARGET_FMT_lx
10758 " MCSRR0 " TARGET_FMT_lx " MCSRR1 " TARGET_FMT_lx "\n",
10759 env->spr[SPR_BOOKE_CSRR0], env->spr[SPR_BOOKE_CSRR1],
10760 env->spr[SPR_BOOKE_MCSRR0], env->spr[SPR_BOOKE_MCSRR1]);
10761
10762 cpu_fprintf(f, " TCR " TARGET_FMT_lx " TSR " TARGET_FMT_lx
10763 " ESR " TARGET_FMT_lx " DEAR " TARGET_FMT_lx "\n",
10764 env->spr[SPR_BOOKE_TCR], env->spr[SPR_BOOKE_TSR],
10765 env->spr[SPR_BOOKE_ESR], env->spr[SPR_BOOKE_DEAR]);
10766
10767 cpu_fprintf(f, " PIR " TARGET_FMT_lx " DECAR " TARGET_FMT_lx
10768 " IVPR " TARGET_FMT_lx " EPCR " TARGET_FMT_lx "\n",
10769 env->spr[SPR_BOOKE_PIR], env->spr[SPR_BOOKE_DECAR],
10770 env->spr[SPR_BOOKE_IVPR], env->spr[SPR_BOOKE_EPCR]);
10771
10772 cpu_fprintf(f, " MCSR " TARGET_FMT_lx " SPRG8 " TARGET_FMT_lx
10773 " EPR " TARGET_FMT_lx "\n",
10774 env->spr[SPR_BOOKE_MCSR], env->spr[SPR_BOOKE_SPRG8],
10775 env->spr[SPR_BOOKE_EPR]);
10776
10777 /* FSL-specific */
10778 cpu_fprintf(f, " MCAR " TARGET_FMT_lx " PID1 " TARGET_FMT_lx
10779 " PID2 " TARGET_FMT_lx " SVR " TARGET_FMT_lx "\n",
10780 env->spr[SPR_Exxx_MCAR], env->spr[SPR_BOOKE_PID1],
10781 env->spr[SPR_BOOKE_PID2], env->spr[SPR_E500_SVR]);
10782
10783 /*
10784 * IVORs are left out as they are large and do not change often --
10785 * they can be read with "p $ivor0", "p $ivor1", etc.
10786 */
10787 }
10788
10789 #if defined(TARGET_PPC64)
10790 if (env->flags & POWERPC_FLAG_CFAR) {
10791 cpu_fprintf(f, " CFAR " TARGET_FMT_lx"\n", env->cfar);
10792 }
10793 #endif
10794
10795 switch (env->mmu_model) {
10796 case POWERPC_MMU_32B:
10797 case POWERPC_MMU_601:
10798 case POWERPC_MMU_SOFT_6xx:
10799 case POWERPC_MMU_SOFT_74xx:
10800 #if defined(TARGET_PPC64)
10801 case POWERPC_MMU_64B:
10802 case POWERPC_MMU_2_06:
10803 case POWERPC_MMU_2_06a:
10804 case POWERPC_MMU_2_06d:
10805 #endif
10806 cpu_fprintf(f, " SDR1 " TARGET_FMT_lx " DAR " TARGET_FMT_lx
10807 " DSISR " TARGET_FMT_lx "\n", env->spr[SPR_SDR1],
10808 env->spr[SPR_DAR], env->spr[SPR_DSISR]);
10809 break;
10810 case POWERPC_MMU_BOOKE206:
10811 cpu_fprintf(f, " MAS0 " TARGET_FMT_lx " MAS1 " TARGET_FMT_lx
10812 " MAS2 " TARGET_FMT_lx " MAS3 " TARGET_FMT_lx "\n",
10813 env->spr[SPR_BOOKE_MAS0], env->spr[SPR_BOOKE_MAS1],
10814 env->spr[SPR_BOOKE_MAS2], env->spr[SPR_BOOKE_MAS3]);
10815
10816 cpu_fprintf(f, " MAS4 " TARGET_FMT_lx " MAS6 " TARGET_FMT_lx
10817 " MAS7 " TARGET_FMT_lx " PID " TARGET_FMT_lx "\n",
10818 env->spr[SPR_BOOKE_MAS4], env->spr[SPR_BOOKE_MAS6],
10819 env->spr[SPR_BOOKE_MAS7], env->spr[SPR_BOOKE_PID]);
10820
10821 cpu_fprintf(f, "MMUCFG " TARGET_FMT_lx " TLB0CFG " TARGET_FMT_lx
10822 " TLB1CFG " TARGET_FMT_lx "\n",
10823 env->spr[SPR_MMUCFG], env->spr[SPR_BOOKE_TLB0CFG],
10824 env->spr[SPR_BOOKE_TLB1CFG]);
10825 break;
10826 default:
10827 break;
10828 }
10829 #endif
10830
10831 #undef RGPL
10832 #undef RFPL
10833 }
10834
10835 void ppc_cpu_dump_statistics(CPUState *cs, FILE*f,
10836 fprintf_function cpu_fprintf, int flags)
10837 {
10838 #if defined(DO_PPC_STATISTICS)
10839 PowerPCCPU *cpu = POWERPC_CPU(cs);
10840 opc_handler_t **t1, **t2, **t3, *handler;
10841 int op1, op2, op3;
10842
10843 t1 = cpu->env.opcodes;
10844 for (op1 = 0; op1 < 64; op1++) {
10845 handler = t1[op1];
10846 if (is_indirect_opcode(handler)) {
10847 t2 = ind_table(handler);
10848 for (op2 = 0; op2 < 32; op2++) {
10849 handler = t2[op2];
10850 if (is_indirect_opcode(handler)) {
10851 t3 = ind_table(handler);
10852 for (op3 = 0; op3 < 32; op3++) {
10853 handler = t3[op3];
10854 if (handler->count == 0)
10855 continue;
10856 cpu_fprintf(f, "%02x %02x %02x (%02x %04d) %16s: "
10857 "%016" PRIx64 " %" PRId64 "\n",
10858 op1, op2, op3, op1, (op3 << 5) | op2,
10859 handler->oname,
10860 handler->count, handler->count);
10861 }
10862 } else {
10863 if (handler->count == 0)
10864 continue;
10865 cpu_fprintf(f, "%02x %02x (%02x %04d) %16s: "
10866 "%016" PRIx64 " %" PRId64 "\n",
10867 op1, op2, op1, op2, handler->oname,
10868 handler->count, handler->count);
10869 }
10870 }
10871 } else {
10872 if (handler->count == 0)
10873 continue;
10874 cpu_fprintf(f, "%02x (%02x ) %16s: %016" PRIx64
10875 " %" PRId64 "\n",
10876 op1, op1, handler->oname,
10877 handler->count, handler->count);
10878 }
10879 }
10880 #endif
10881 }
10882
10883 /*****************************************************************************/
10884 static inline void gen_intermediate_code_internal(PowerPCCPU *cpu,
10885 TranslationBlock *tb,
10886 bool search_pc)
10887 {
10888 CPUState *cs = CPU(cpu);
10889 CPUPPCState *env = &cpu->env;
10890 DisasContext ctx, *ctxp = &ctx;
10891 opc_handler_t **table, *handler;
10892 target_ulong pc_start;
10893 uint16_t *gen_opc_end;
10894 CPUBreakpoint *bp;
10895 int j, lj = -1;
10896 int num_insns;
10897 int max_insns;
10898
10899 pc_start = tb->pc;
10900 gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
10901 ctx.nip = pc_start;
10902 ctx.tb = tb;
10903 ctx.exception = POWERPC_EXCP_NONE;
10904 ctx.spr_cb = env->spr_cb;
10905 ctx.mem_idx = env->mmu_idx;
10906 ctx.insns_flags = env->insns_flags;
10907 ctx.insns_flags2 = env->insns_flags2;
10908 ctx.access_type = -1;
10909 ctx.le_mode = env->hflags & (1 << MSR_LE) ? 1 : 0;
10910 #if defined(TARGET_PPC64)
10911 ctx.sf_mode = msr_is_64bit(env, env->msr);
10912 ctx.has_cfar = !!(env->flags & POWERPC_FLAG_CFAR);
10913 #endif
10914 ctx.fpu_enabled = msr_fp;
10915 if ((env->flags & POWERPC_FLAG_SPE) && msr_spe)
10916 ctx.spe_enabled = msr_spe;
10917 else
10918 ctx.spe_enabled = 0;
10919 if ((env->flags & POWERPC_FLAG_VRE) && msr_vr)
10920 ctx.altivec_enabled = msr_vr;
10921 else
10922 ctx.altivec_enabled = 0;
10923 if ((env->flags & POWERPC_FLAG_VSX) && msr_vsx) {
10924 ctx.vsx_enabled = msr_vsx;
10925 } else {
10926 ctx.vsx_enabled = 0;
10927 }
10928 if ((env->flags & POWERPC_FLAG_SE) && msr_se)
10929 ctx.singlestep_enabled = CPU_SINGLE_STEP;
10930 else
10931 ctx.singlestep_enabled = 0;
10932 if ((env->flags & POWERPC_FLAG_BE) && msr_be)
10933 ctx.singlestep_enabled |= CPU_BRANCH_STEP;
10934 if (unlikely(cs->singlestep_enabled)) {
10935 ctx.singlestep_enabled |= GDBSTUB_SINGLE_STEP;
10936 }
10937 #if defined (DO_SINGLE_STEP) && 0
10938 /* Single step trace mode */
10939 msr_se = 1;
10940 #endif
10941 num_insns = 0;
10942 max_insns = tb->cflags & CF_COUNT_MASK;
10943 if (max_insns == 0)
10944 max_insns = CF_COUNT_MASK;
10945
10946 gen_tb_start();
10947 /* Set env in case of segfault during code fetch */
10948 while (ctx.exception == POWERPC_EXCP_NONE
10949 && tcg_ctx.gen_opc_ptr < gen_opc_end) {
10950 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
10951 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
10952 if (bp->pc == ctx.nip) {
10953 gen_debug_exception(ctxp);
10954 break;
10955 }
10956 }
10957 }
10958 if (unlikely(search_pc)) {
10959 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
10960 if (lj < j) {
10961 lj++;
10962 while (lj < j)
10963 tcg_ctx.gen_opc_instr_start[lj++] = 0;
10964 }
10965 tcg_ctx.gen_opc_pc[lj] = ctx.nip;
10966 tcg_ctx.gen_opc_instr_start[lj] = 1;
10967 tcg_ctx.gen_opc_icount[lj] = num_insns;
10968 }
10969 LOG_DISAS("----------------\n");
10970 LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n",
10971 ctx.nip, ctx.mem_idx, (int)msr_ir);
10972 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
10973 gen_io_start();
10974 if (unlikely(ctx.le_mode)) {
10975 ctx.opcode = bswap32(cpu_ldl_code(env, ctx.nip));
10976 } else {
10977 ctx.opcode = cpu_ldl_code(env, ctx.nip);
10978 }
10979 LOG_DISAS("translate opcode %08x (%02x %02x %02x) (%s)\n",
10980 ctx.opcode, opc1(ctx.opcode), opc2(ctx.opcode),
10981 opc3(ctx.opcode), ctx.le_mode ? "little" : "big");
10982 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) {
10983 tcg_gen_debug_insn_start(ctx.nip);
10984 }
10985 ctx.nip += 4;
10986 table = env->opcodes;
10987 num_insns++;
10988 handler = table[opc1(ctx.opcode)];
10989 if (is_indirect_opcode(handler)) {
10990 table = ind_table(handler);
10991 handler = table[opc2(ctx.opcode)];
10992 if (is_indirect_opcode(handler)) {
10993 table = ind_table(handler);
10994 handler = table[opc3(ctx.opcode)];
10995 }
10996 }
10997 /* Is opcode *REALLY* valid ? */
10998 if (unlikely(handler->handler == &gen_invalid)) {
10999 if (qemu_log_enabled()) {
11000 qemu_log("invalid/unsupported opcode: "
11001 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx " %d\n",
11002 opc1(ctx.opcode), opc2(ctx.opcode),
11003 opc3(ctx.opcode), ctx.opcode, ctx.nip - 4, (int)msr_ir);
11004 }
11005 } else {
11006 uint32_t inval;
11007
11008 if (unlikely(handler->type & (PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE) && Rc(ctx.opcode))) {
11009 inval = handler->inval2;
11010 } else {
11011 inval = handler->inval1;
11012 }
11013
11014 if (unlikely((ctx.opcode & inval) != 0)) {
11015 if (qemu_log_enabled()) {
11016 qemu_log("invalid bits: %08x for opcode: "
11017 "%02x - %02x - %02x (%08x) " TARGET_FMT_lx "\n",
11018 ctx.opcode & inval, opc1(ctx.opcode),
11019 opc2(ctx.opcode), opc3(ctx.opcode),
11020 ctx.opcode, ctx.nip - 4);
11021 }
11022 gen_inval_exception(ctxp, POWERPC_EXCP_INVAL_INVAL);
11023 break;
11024 }
11025 }
11026 (*(handler->handler))(&ctx);
11027 #if defined(DO_PPC_STATISTICS)
11028 handler->count++;
11029 #endif
11030 /* Check trace mode exceptions */
11031 if (unlikely(ctx.singlestep_enabled & CPU_SINGLE_STEP &&
11032 (ctx.nip <= 0x100 || ctx.nip > 0xF00) &&
11033 ctx.exception != POWERPC_SYSCALL &&
11034 ctx.exception != POWERPC_EXCP_TRAP &&
11035 ctx.exception != POWERPC_EXCP_BRANCH)) {
11036 gen_exception(ctxp, POWERPC_EXCP_TRACE);
11037 } else if (unlikely(((ctx.nip & (TARGET_PAGE_SIZE - 1)) == 0) ||
11038 (cs->singlestep_enabled) ||
11039 singlestep ||
11040 num_insns >= max_insns)) {
11041 /* if we reach a page boundary or are single stepping, stop
11042 * generation
11043 */
11044 break;
11045 }
11046 }
11047 if (tb->cflags & CF_LAST_IO)
11048 gen_io_end();
11049 if (ctx.exception == POWERPC_EXCP_NONE) {
11050 gen_goto_tb(&ctx, 0, ctx.nip);
11051 } else if (ctx.exception != POWERPC_EXCP_BRANCH) {
11052 if (unlikely(cs->singlestep_enabled)) {
11053 gen_debug_exception(ctxp);
11054 }
11055 /* Generate the return instruction */
11056 tcg_gen_exit_tb(0);
11057 }
11058 gen_tb_end(tb, num_insns);
11059 *tcg_ctx.gen_opc_ptr = INDEX_op_end;
11060 if (unlikely(search_pc)) {
11061 j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf;
11062 lj++;
11063 while (lj <= j)
11064 tcg_ctx.gen_opc_instr_start[lj++] = 0;
11065 } else {
11066 tb->size = ctx.nip - pc_start;
11067 tb->icount = num_insns;
11068 }
11069 #if defined(DEBUG_DISAS)
11070 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
11071 int flags;
11072 flags = env->bfd_mach;
11073 flags |= ctx.le_mode << 16;
11074 qemu_log("IN: %s\n", lookup_symbol(pc_start));
11075 log_target_disas(env, pc_start, ctx.nip - pc_start, flags);
11076 qemu_log("\n");
11077 }
11078 #endif
11079 }
11080
11081 void gen_intermediate_code (CPUPPCState *env, struct TranslationBlock *tb)
11082 {
11083 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, false);
11084 }
11085
11086 void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb)
11087 {
11088 gen_intermediate_code_internal(ppc_env_get_cpu(env), tb, true);
11089 }
11090
11091 void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos)
11092 {
11093 env->nip = tcg_ctx.gen_opc_pc[pc_pos];
11094 }
QEMU modified to work with kvm