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xhci: add sanity checks to xhci_lookup_uport
[qemu-kvm.git] / target-mips / translate_init.c
blob148b394cf054543eb733a5c602c235bc8d8631f6
1 /*
2 * MIPS emulation for qemu: CPU initialisation routines.
3 *
4 * Copyright (c) 2004-2005 Jocelyn Mayer
5 * Copyright (c) 2007 Herve Poussineau
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 /* CPU / CPU family specific config register values. */
22
23 /* Have config1, uncached coherency */
24 #define MIPS_CONFIG0 \
25 ((1U << CP0C0_M) | (0x2 << CP0C0_K0))
26
27 /* Have config2, no coprocessor2 attached, no MDMX support attached,
28 no performance counters, watch registers present,
29 no code compression, EJTAG present, no FPU */
30 #define MIPS_CONFIG1 \
31 ((1U << CP0C1_M) | \
32 (0 << CP0C1_C2) | (0 << CP0C1_MD) | (0 << CP0C1_PC) | \
33 (1 << CP0C1_WR) | (0 << CP0C1_CA) | (1 << CP0C1_EP) | \
34 (0 << CP0C1_FP))
35
36 /* Have config3, no tertiary/secondary caches implemented */
37 #define MIPS_CONFIG2 \
38 ((1U << CP0C2_M))
39
40 /* No config4, no DSP ASE, no large physaddr (PABITS),
41 no external interrupt controller, no vectored interrupts,
42 no 1kb pages, no SmartMIPS ASE, no trace logic */
43 #define MIPS_CONFIG3 \
44 ((0 << CP0C3_M) | (0 << CP0C3_DSPP) | (0 << CP0C3_LPA) | \
45 (0 << CP0C3_VEIC) | (0 << CP0C3_VInt) | (0 << CP0C3_SP) | \
46 (0 << CP0C3_SM) | (0 << CP0C3_TL))
47
48 #define MIPS_CONFIG4 \
49 ((0 << CP0C4_M))
50
51 #define MIPS_CONFIG5 \
52 ((0 << CP0C5_M))
53
54 /* MMU types, the first four entries have the same layout as the
55 CP0C0_MT field. */
56 enum mips_mmu_types {
57 MMU_TYPE_NONE,
58 MMU_TYPE_R4000,
59 MMU_TYPE_RESERVED,
60 MMU_TYPE_FMT,
61 MMU_TYPE_R3000,
62 MMU_TYPE_R6000,
63 MMU_TYPE_R8000
64 };
65
66 struct mips_def_t {
67 const char *name;
68 int32_t CP0_PRid;
69 int32_t CP0_Config0;
70 int32_t CP0_Config1;
71 int32_t CP0_Config2;
72 int32_t CP0_Config3;
73 int32_t CP0_Config4;
74 int32_t CP0_Config4_rw_bitmask;
75 int32_t CP0_Config5;
76 int32_t CP0_Config5_rw_bitmask;
77 int32_t CP0_Config6;
78 int32_t CP0_Config7;
79 target_ulong CP0_LLAddr_rw_bitmask;
80 int CP0_LLAddr_shift;
81 int32_t SYNCI_Step;
82 int32_t CCRes;
83 int32_t CP0_Status_rw_bitmask;
84 int32_t CP0_TCStatus_rw_bitmask;
85 int32_t CP0_SRSCtl;
86 int32_t CP1_fcr0;
87 int32_t MSAIR;
88 int32_t SEGBITS;
89 int32_t PABITS;
90 int32_t CP0_SRSConf0_rw_bitmask;
91 int32_t CP0_SRSConf0;
92 int32_t CP0_SRSConf1_rw_bitmask;
93 int32_t CP0_SRSConf1;
94 int32_t CP0_SRSConf2_rw_bitmask;
95 int32_t CP0_SRSConf2;
96 int32_t CP0_SRSConf3_rw_bitmask;
97 int32_t CP0_SRSConf3;
98 int32_t CP0_SRSConf4_rw_bitmask;
99 int32_t CP0_SRSConf4;
100 int32_t CP0_PageGrain_rw_bitmask;
101 int32_t CP0_PageGrain;
102 int insn_flags;
103 enum mips_mmu_types mmu_type;
104 };
105
106 /*****************************************************************************/
107 /* MIPS CPU definitions */
108 static const mips_def_t mips_defs[] =
109 {
110 {
111 .name = "4Kc",
112 .CP0_PRid = 0x00018000,
113 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
114 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
115 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
116 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
117 (0 << CP0C1_CA),
118 .CP0_Config2 = MIPS_CONFIG2,
119 .CP0_Config3 = MIPS_CONFIG3,
120 .CP0_LLAddr_rw_bitmask = 0,
121 .CP0_LLAddr_shift = 4,
122 .SYNCI_Step = 32,
123 .CCRes = 2,
124 .CP0_Status_rw_bitmask = 0x1278FF17,
125 .SEGBITS = 32,
126 .PABITS = 32,
127 .insn_flags = CPU_MIPS32,
128 .mmu_type = MMU_TYPE_R4000,
129 },
130 {
131 .name = "4Km",
132 .CP0_PRid = 0x00018300,
133 /* Config1 implemented, fixed mapping MMU,
134 no virtual icache, uncached coherency. */
135 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
136 .CP0_Config1 = MIPS_CONFIG1 |
137 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
138 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
139 (1 << CP0C1_CA),
140 .CP0_Config2 = MIPS_CONFIG2,
141 .CP0_Config3 = MIPS_CONFIG3,
142 .CP0_LLAddr_rw_bitmask = 0,
143 .CP0_LLAddr_shift = 4,
144 .SYNCI_Step = 32,
145 .CCRes = 2,
146 .CP0_Status_rw_bitmask = 0x1258FF17,
147 .SEGBITS = 32,
148 .PABITS = 32,
149 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
150 .mmu_type = MMU_TYPE_FMT,
151 },
152 {
153 .name = "4KEcR1",
154 .CP0_PRid = 0x00018400,
155 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_R4000 << CP0C0_MT),
156 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
157 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
158 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
159 (0 << CP0C1_CA),
160 .CP0_Config2 = MIPS_CONFIG2,
161 .CP0_Config3 = MIPS_CONFIG3,
162 .CP0_LLAddr_rw_bitmask = 0,
163 .CP0_LLAddr_shift = 4,
164 .SYNCI_Step = 32,
165 .CCRes = 2,
166 .CP0_Status_rw_bitmask = 0x1278FF17,
167 .SEGBITS = 32,
168 .PABITS = 32,
169 .insn_flags = CPU_MIPS32,
170 .mmu_type = MMU_TYPE_R4000,
171 },
172 {
173 .name = "4KEmR1",
174 .CP0_PRid = 0x00018500,
175 .CP0_Config0 = MIPS_CONFIG0 | (MMU_TYPE_FMT << CP0C0_MT),
176 .CP0_Config1 = MIPS_CONFIG1 |
177 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
178 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
179 (1 << CP0C1_CA),
180 .CP0_Config2 = MIPS_CONFIG2,
181 .CP0_Config3 = MIPS_CONFIG3,
182 .CP0_LLAddr_rw_bitmask = 0,
183 .CP0_LLAddr_shift = 4,
184 .SYNCI_Step = 32,
185 .CCRes = 2,
186 .CP0_Status_rw_bitmask = 0x1258FF17,
187 .SEGBITS = 32,
188 .PABITS = 32,
189 .insn_flags = CPU_MIPS32 | ASE_MIPS16,
190 .mmu_type = MMU_TYPE_FMT,
191 },
192 {
193 .name = "4KEc",
194 .CP0_PRid = 0x00019000,
195 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
196 (MMU_TYPE_R4000 << CP0C0_MT),
197 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
198 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
199 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
200 (0 << CP0C1_CA),
201 .CP0_Config2 = MIPS_CONFIG2,
202 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
203 .CP0_LLAddr_rw_bitmask = 0,
204 .CP0_LLAddr_shift = 4,
205 .SYNCI_Step = 32,
206 .CCRes = 2,
207 .CP0_Status_rw_bitmask = 0x1278FF17,
208 .SEGBITS = 32,
209 .PABITS = 32,
210 .insn_flags = CPU_MIPS32R2,
211 .mmu_type = MMU_TYPE_R4000,
212 },
213 {
214 .name = "4KEm",
215 .CP0_PRid = 0x00019100,
216 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
217 (MMU_TYPE_FMT << CP0C0_MT),
218 .CP0_Config1 = MIPS_CONFIG1 |
219 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
220 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
221 (1 << CP0C1_CA),
222 .CP0_Config2 = MIPS_CONFIG2,
223 .CP0_Config3 = MIPS_CONFIG3,
224 .CP0_LLAddr_rw_bitmask = 0,
225 .CP0_LLAddr_shift = 4,
226 .SYNCI_Step = 32,
227 .CCRes = 2,
228 .CP0_Status_rw_bitmask = 0x1258FF17,
229 .SEGBITS = 32,
230 .PABITS = 32,
231 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
232 .mmu_type = MMU_TYPE_FMT,
233 },
234 {
235 .name = "24Kc",
236 .CP0_PRid = 0x00019300,
237 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
238 (MMU_TYPE_R4000 << CP0C0_MT),
239 .CP0_Config1 = MIPS_CONFIG1 | (15 << CP0C1_MMU) |
240 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
241 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
242 (1 << CP0C1_CA),
243 .CP0_Config2 = MIPS_CONFIG2,
244 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
245 .CP0_LLAddr_rw_bitmask = 0,
246 .CP0_LLAddr_shift = 4,
247 .SYNCI_Step = 32,
248 .CCRes = 2,
249 /* No DSP implemented. */
250 .CP0_Status_rw_bitmask = 0x1278FF1F,
251 .SEGBITS = 32,
252 .PABITS = 32,
253 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
254 .mmu_type = MMU_TYPE_R4000,
255 },
256 {
257 .name = "24Kf",
258 .CP0_PRid = 0x00019300,
259 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
260 (MMU_TYPE_R4000 << CP0C0_MT),
261 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
262 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
263 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
264 (1 << CP0C1_CA),
265 .CP0_Config2 = MIPS_CONFIG2,
266 .CP0_Config3 = MIPS_CONFIG3 | (0 << CP0C3_VInt),
267 .CP0_LLAddr_rw_bitmask = 0,
268 .CP0_LLAddr_shift = 4,
269 .SYNCI_Step = 32,
270 .CCRes = 2,
271 /* No DSP implemented. */
272 .CP0_Status_rw_bitmask = 0x3678FF1F,
273 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
274 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
275 .SEGBITS = 32,
276 .PABITS = 32,
277 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16,
278 .mmu_type = MMU_TYPE_R4000,
279 },
280 {
281 .name = "34Kf",
282 .CP0_PRid = 0x00019500,
283 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
284 (MMU_TYPE_R4000 << CP0C0_MT),
285 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
286 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
287 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
288 (1 << CP0C1_CA),
289 .CP0_Config2 = MIPS_CONFIG2,
290 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_VInt) | (1 << CP0C3_MT) |
291 (1 << CP0C3_DSPP),
292 .CP0_LLAddr_rw_bitmask = 0,
293 .CP0_LLAddr_shift = 0,
294 .SYNCI_Step = 32,
295 .CCRes = 2,
296 .CP0_Status_rw_bitmask = 0x3778FF1F,
297 .CP0_TCStatus_rw_bitmask = (0 << CP0TCSt_TCU3) | (0 << CP0TCSt_TCU2) |
298 (1 << CP0TCSt_TCU1) | (1 << CP0TCSt_TCU0) |
299 (0 << CP0TCSt_TMX) | (1 << CP0TCSt_DT) |
300 (1 << CP0TCSt_DA) | (1 << CP0TCSt_A) |
301 (0x3 << CP0TCSt_TKSU) | (1 << CP0TCSt_IXMT) |
302 (0xff << CP0TCSt_TASID),
303 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
304 (1 << FCR0_D) | (1 << FCR0_S) | (0x95 << FCR0_PRID),
305 .CP0_SRSCtl = (0xf << CP0SRSCtl_HSS),
306 .CP0_SRSConf0_rw_bitmask = 0x3fffffff,
307 .CP0_SRSConf0 = (1U << CP0SRSC0_M) | (0x3fe << CP0SRSC0_SRS3) |
308 (0x3fe << CP0SRSC0_SRS2) | (0x3fe << CP0SRSC0_SRS1),
309 .CP0_SRSConf1_rw_bitmask = 0x3fffffff,
310 .CP0_SRSConf1 = (1U << CP0SRSC1_M) | (0x3fe << CP0SRSC1_SRS6) |
311 (0x3fe << CP0SRSC1_SRS5) | (0x3fe << CP0SRSC1_SRS4),
312 .CP0_SRSConf2_rw_bitmask = 0x3fffffff,
313 .CP0_SRSConf2 = (1U << CP0SRSC2_M) | (0x3fe << CP0SRSC2_SRS9) |
314 (0x3fe << CP0SRSC2_SRS8) | (0x3fe << CP0SRSC2_SRS7),
315 .CP0_SRSConf3_rw_bitmask = 0x3fffffff,
316 .CP0_SRSConf3 = (1U << CP0SRSC3_M) | (0x3fe << CP0SRSC3_SRS12) |
317 (0x3fe << CP0SRSC3_SRS11) | (0x3fe << CP0SRSC3_SRS10),
318 .CP0_SRSConf4_rw_bitmask = 0x3fffffff,
319 .CP0_SRSConf4 = (0x3fe << CP0SRSC4_SRS15) |
320 (0x3fe << CP0SRSC4_SRS14) | (0x3fe << CP0SRSC4_SRS13),
321 .SEGBITS = 32,
322 .PABITS = 32,
323 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_MT,
324 .mmu_type = MMU_TYPE_R4000,
325 },
326 {
327 .name = "74Kf",
328 .CP0_PRid = 0x00019700,
329 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
330 (MMU_TYPE_R4000 << CP0C0_MT),
331 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
332 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
333 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
334 (1 << CP0C1_CA),
335 .CP0_Config2 = MIPS_CONFIG2,
336 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_DSP2P) | (1 << CP0C3_DSPP) |
337 (0 << CP0C3_VInt),
338 .CP0_LLAddr_rw_bitmask = 0,
339 .CP0_LLAddr_shift = 4,
340 .SYNCI_Step = 32,
341 .CCRes = 2,
342 .CP0_Status_rw_bitmask = 0x3778FF1F,
343 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
344 (1 << FCR0_D) | (1 << FCR0_S) | (0x93 << FCR0_PRID),
345 .SEGBITS = 32,
346 .PABITS = 32,
347 .insn_flags = CPU_MIPS32R2 | ASE_MIPS16 | ASE_DSP | ASE_DSPR2,
348 .mmu_type = MMU_TYPE_R4000,
349 },
350 {
351 /* A generic CPU providing MIPS32 Release 5 features.
352 FIXME: Eventually this should be replaced by a real CPU model. */
353 .name = "mips32r5-generic",
354 .CP0_PRid = 0x00019700,
355 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) |
356 (MMU_TYPE_R4000 << CP0C0_MT),
357 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (15 << CP0C1_MMU) |
358 (0 << CP0C1_IS) | (3 << CP0C1_IL) | (1 << CP0C1_IA) |
359 (0 << CP0C1_DS) | (3 << CP0C1_DL) | (1 << CP0C1_DA) |
360 (1 << CP0C1_CA),
361 .CP0_Config2 = MIPS_CONFIG2,
362 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_MSAP),
363 .CP0_Config4 = MIPS_CONFIG4 | (1U << CP0C4_M),
364 .CP0_Config4_rw_bitmask = 0,
365 .CP0_Config5 = MIPS_CONFIG5 | (1 << CP0C5_UFR),
366 .CP0_Config5_rw_bitmask = (0 << CP0C5_M) | (1 << CP0C5_K) |
367 (1 << CP0C5_CV) | (0 << CP0C5_EVA) |
368 (1 << CP0C5_MSAEn) | (1 << CP0C5_UFR) |
369 (0 << CP0C5_NFExists),
370 .CP0_LLAddr_rw_bitmask = 0,
371 .CP0_LLAddr_shift = 4,
372 .SYNCI_Step = 32,
373 .CCRes = 2,
374 .CP0_Status_rw_bitmask = 0x3778FF1F,
375 .CP1_fcr0 = (1 << FCR0_UFRP) | (1 << FCR0_F64) | (1 << FCR0_L) |
376 (1 << FCR0_W) | (1 << FCR0_D) | (1 << FCR0_S) |
377 (0x93 << FCR0_PRID),
378 .SEGBITS = 32,
379 .PABITS = 32,
380 .insn_flags = CPU_MIPS32R5 | ASE_MIPS16 | ASE_MSA,
381 .mmu_type = MMU_TYPE_R4000,
382 },
383 #if defined(TARGET_MIPS64)
384 {
385 .name = "R4000",
386 .CP0_PRid = 0x00000400,
387 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
388 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
389 /* Note: Config1 is only used internally, the R4000 has only Config0. */
390 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
391 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFF,
392 .CP0_LLAddr_shift = 4,
393 .SYNCI_Step = 16,
394 .CCRes = 2,
395 .CP0_Status_rw_bitmask = 0x3678FFFF,
396 /* The R4000 has a full 64bit FPU but doesn't use the fcr0 bits. */
397 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x0 << FCR0_REV),
398 .SEGBITS = 40,
399 .PABITS = 36,
400 .insn_flags = CPU_MIPS3,
401 .mmu_type = MMU_TYPE_R4000,
402 },
403 {
404 .name = "VR5432",
405 .CP0_PRid = 0x00005400,
406 /* No L2 cache, icache size 8k, dcache size 8k, uncached coherency. */
407 .CP0_Config0 = (1 << 17) | (0x1 << 9) | (0x1 << 6) | (0x2 << CP0C0_K0),
408 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
409 .CP0_LLAddr_rw_bitmask = 0xFFFFFFFFL,
410 .CP0_LLAddr_shift = 4,
411 .SYNCI_Step = 16,
412 .CCRes = 2,
413 .CP0_Status_rw_bitmask = 0x3678FFFF,
414 /* The VR5432 has a full 64bit FPU but doesn't use the fcr0 bits. */
415 .CP1_fcr0 = (0x54 << FCR0_PRID) | (0x0 << FCR0_REV),
416 .SEGBITS = 40,
417 .PABITS = 32,
418 .insn_flags = CPU_VR54XX,
419 .mmu_type = MMU_TYPE_R4000,
420 },
421 {
422 .name = "5Kc",
423 .CP0_PRid = 0x00018100,
424 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
425 (MMU_TYPE_R4000 << CP0C0_MT),
426 .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
427 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
428 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
429 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
430 .CP0_Config2 = MIPS_CONFIG2,
431 .CP0_Config3 = MIPS_CONFIG3,
432 .CP0_LLAddr_rw_bitmask = 0,
433 .CP0_LLAddr_shift = 4,
434 .SYNCI_Step = 32,
435 .CCRes = 2,
436 .CP0_Status_rw_bitmask = 0x32F8FFFF,
437 .SEGBITS = 42,
438 .PABITS = 36,
439 .insn_flags = CPU_MIPS64,
440 .mmu_type = MMU_TYPE_R4000,
441 },
442 {
443 .name = "5Kf",
444 .CP0_PRid = 0x00018100,
445 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
446 (MMU_TYPE_R4000 << CP0C0_MT),
447 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
448 (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
449 (1 << CP0C1_DS) | (4 << CP0C1_DL) | (1 << CP0C1_DA) |
450 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
451 .CP0_Config2 = MIPS_CONFIG2,
452 .CP0_Config3 = MIPS_CONFIG3,
453 .CP0_LLAddr_rw_bitmask = 0,
454 .CP0_LLAddr_shift = 4,
455 .SYNCI_Step = 32,
456 .CCRes = 2,
457 .CP0_Status_rw_bitmask = 0x36F8FFFF,
458 /* The 5Kf has F64 / L / W but doesn't use the fcr0 bits. */
459 .CP1_fcr0 = (1 << FCR0_D) | (1 << FCR0_S) |
460 (0x81 << FCR0_PRID) | (0x0 << FCR0_REV),
461 .SEGBITS = 42,
462 .PABITS = 36,
463 .insn_flags = CPU_MIPS64,
464 .mmu_type = MMU_TYPE_R4000,
465 },
466 {
467 .name = "20Kc",
468 /* We emulate a later version of the 20Kc, earlier ones had a broken
469 WAIT instruction. */
470 .CP0_PRid = 0x000182a0,
471 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
472 (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
473 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
474 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
475 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
476 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
477 .CP0_Config2 = MIPS_CONFIG2,
478 .CP0_Config3 = MIPS_CONFIG3,
479 .CP0_LLAddr_rw_bitmask = 0,
480 .CP0_LLAddr_shift = 0,
481 .SYNCI_Step = 32,
482 .CCRes = 1,
483 .CP0_Status_rw_bitmask = 0x36FBFFFF,
484 /* The 20Kc has F64 / L / W but doesn't use the fcr0 bits. */
485 .CP1_fcr0 = (1 << FCR0_3D) | (1 << FCR0_PS) |
486 (1 << FCR0_D) | (1 << FCR0_S) |
487 (0x82 << FCR0_PRID) | (0x0 << FCR0_REV),
488 .SEGBITS = 40,
489 .PABITS = 36,
490 .insn_flags = CPU_MIPS64 | ASE_MIPS3D,
491 .mmu_type = MMU_TYPE_R4000,
492 },
493 {
494 /* A generic CPU providing MIPS64 Release 2 features.
495 FIXME: Eventually this should be replaced by a real CPU model. */
496 .name = "MIPS64R2-generic",
497 .CP0_PRid = 0x00010000,
498 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
499 (MMU_TYPE_R4000 << CP0C0_MT),
500 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
501 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
502 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
503 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
504 .CP0_Config2 = MIPS_CONFIG2,
505 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_LPA),
506 .CP0_LLAddr_rw_bitmask = 0,
507 .CP0_LLAddr_shift = 0,
508 .SYNCI_Step = 32,
509 .CCRes = 2,
510 .CP0_Status_rw_bitmask = 0x36FBFFFF,
511 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
512 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
513 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
514 .SEGBITS = 42,
515 /* The architectural limit is 59, but we have hardcoded 36 bit
516 in some places...
517 .PABITS = 59, */ /* the architectural limit */
518 .PABITS = 36,
519 .insn_flags = CPU_MIPS64R2 | ASE_MIPS3D,
520 .mmu_type = MMU_TYPE_R4000,
521 },
522 {
523 /* A generic CPU supporting MIPS64 Release 6 ISA.
524 FIXME: Support IEEE 754-2008 FP and misaligned memory accesses.
525 Eventually this should be replaced by a real CPU model. */
526 .name = "MIPS64R6-generic",
527 .CP0_PRid = 0x00010000,
528 .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AR) | (0x2 << CP0C0_AT) |
529 (MMU_TYPE_R4000 << CP0C0_MT),
530 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
531 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
532 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
533 (0 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
534 .CP0_Config2 = MIPS_CONFIG2,
535 .CP0_Config3 = MIPS_CONFIG3 | (1 << CP0C3_RXI) | (1 << CP0C3_BP) |
536 (1 << CP0C3_BI) | (1 << CP0C3_ULRI) | (1U << CP0C3_M),
537 .CP0_Config4 = MIPS_CONFIG4 | (0xfc << CP0C4_KScrExist) |
538 (3 << CP0C4_IE) | (1 << CP0C4_M),
539 .CP0_Config5_rw_bitmask = (1 << CP0C5_SBRI),
540 .CP0_LLAddr_rw_bitmask = 0,
541 .CP0_LLAddr_shift = 0,
542 .SYNCI_Step = 32,
543 .CCRes = 2,
544 .CP0_Status_rw_bitmask = 0x30D8FFFF,
545 .CP0_PageGrain = (1 << CP0PG_IEC) | (1 << CP0PG_XIE) |
546 (1U << CP0PG_RIE),
547 .CP0_PageGrain_rw_bitmask = 0,
548 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_L) | (1 << FCR0_W) |
549 (1 << FCR0_D) | (1 << FCR0_S) | (0x00 << FCR0_PRID) |
550 (0x0 << FCR0_REV),
551 .SEGBITS = 42,
552 /* The architectural limit is 59, but we have hardcoded 36 bit
553 in some places...
554 .PABITS = 59, */ /* the architectural limit */
555 .PABITS = 36,
556 .insn_flags = CPU_MIPS64R6,
557 .mmu_type = MMU_TYPE_R4000,
558 },
559 {
560 .name = "Loongson-2E",
561 .CP0_PRid = 0x6302,
562 /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/
563 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) |
564 (0x1<<4) | (0x1<<1),
565 /* Note: Config1 is only used internally, Loongson-2E has only Config0. */
566 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
567 .SYNCI_Step = 16,
568 .CCRes = 2,
569 .CP0_Status_rw_bitmask = 0x35D0FFFF,
570 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
571 .SEGBITS = 40,
572 .PABITS = 40,
573 .insn_flags = CPU_LOONGSON2E,
574 .mmu_type = MMU_TYPE_R4000,
575 },
576 {
577 .name = "Loongson-2F",
578 .CP0_PRid = 0x6303,
579 /*64KB I-cache and d-cache. 4 way with 32 bit cache line size*/
580 .CP0_Config0 = (0x1<<17) | (0x1<<16) | (0x1<<11) | (0x1<<8) | (0x1<<5) |
581 (0x1<<4) | (0x1<<1),
582 /* Note: Config1 is only used internally, Loongson-2F has only Config0. */
583 .CP0_Config1 = (1 << CP0C1_FP) | (47 << CP0C1_MMU),
584 .SYNCI_Step = 16,
585 .CCRes = 2,
586 .CP0_Status_rw_bitmask = 0xF5D0FF1F, /*bit5:7 not writable*/
587 .CP1_fcr0 = (0x5 << FCR0_PRID) | (0x1 << FCR0_REV),
588 .SEGBITS = 40,
589 .PABITS = 40,
590 .insn_flags = CPU_LOONGSON2F,
591 .mmu_type = MMU_TYPE_R4000,
592 },
593 {
594 /* A generic CPU providing MIPS64 ASE DSP 2 features.
595 FIXME: Eventually this should be replaced by a real CPU model. */
596 .name = "mips64dspr2",
597 .CP0_PRid = 0x00010000,
598 .CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) |
599 (MMU_TYPE_R4000 << CP0C0_MT),
600 .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (63 << CP0C1_MMU) |
601 (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |
602 (2 << CP0C1_DS) | (4 << CP0C1_DL) | (3 << CP0C1_DA) |
603 (1 << CP0C1_PC) | (1 << CP0C1_WR) | (1 << CP0C1_EP),
604 .CP0_Config2 = MIPS_CONFIG2,
605 .CP0_Config3 = MIPS_CONFIG3 | (1U << CP0C3_M) | (1 << CP0C3_DSP2P) |
606 (1 << CP0C3_DSPP) | (1 << CP0C3_LPA),
607 .CP0_LLAddr_rw_bitmask = 0,
608 .CP0_LLAddr_shift = 0,
609 .SYNCI_Step = 32,
610 .CCRes = 2,
611 .CP0_Status_rw_bitmask = 0x37FBFFFF,
612 .CP1_fcr0 = (1 << FCR0_F64) | (1 << FCR0_3D) | (1 << FCR0_PS) |
613 (1 << FCR0_L) | (1 << FCR0_W) | (1 << FCR0_D) |
614 (1 << FCR0_S) | (0x00 << FCR0_PRID) | (0x0 << FCR0_REV),
615 .SEGBITS = 42,
616 /* The architectural limit is 59, but we have hardcoded 36 bit
617 in some places...
618 .PABITS = 59, */ /* the architectural limit */
619 .PABITS = 36,
620 .insn_flags = CPU_MIPS64R2 | ASE_DSP | ASE_DSPR2,
621 .mmu_type = MMU_TYPE_R4000,
622 },
623
624 #endif
625 };
626
627 static const mips_def_t *cpu_mips_find_by_name (const char *name)
628 {
629 int i;
630
631 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
632 if (strcasecmp(name, mips_defs[i].name) == 0) {
633 return &mips_defs[i];
634 }
635 }
636 return NULL;
637 }
638
639 void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf)
640 {
641 int i;
642
643 for (i = 0; i < ARRAY_SIZE(mips_defs); i++) {
644 (*cpu_fprintf)(f, "MIPS '%s'\n",
645 mips_defs[i].name);
646 }
647 }
648
649 #ifndef CONFIG_USER_ONLY
650 static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
651 {
652 env->tlb->nb_tlb = 1;
653 env->tlb->map_address = &no_mmu_map_address;
654 }
655
656 static void fixed_mmu_init (CPUMIPSState *env, const mips_def_t *def)
657 {
658 env->tlb->nb_tlb = 1;
659 env->tlb->map_address = &fixed_mmu_map_address;
660 }
661
662 static void r4k_mmu_init (CPUMIPSState *env, const mips_def_t *def)
663 {
664 env->tlb->nb_tlb = 1 + ((def->CP0_Config1 >> CP0C1_MMU) & 63);
665 env->tlb->map_address = &r4k_map_address;
666 env->tlb->helper_tlbwi = r4k_helper_tlbwi;
667 env->tlb->helper_tlbwr = r4k_helper_tlbwr;
668 env->tlb->helper_tlbp = r4k_helper_tlbp;
669 env->tlb->helper_tlbr = r4k_helper_tlbr;
670 env->tlb->helper_tlbinv = r4k_helper_tlbinv;
671 env->tlb->helper_tlbinvf = r4k_helper_tlbinvf;
672 }
673
674 static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
675 {
676 MIPSCPU *cpu = mips_env_get_cpu(env);
677
678 env->tlb = g_malloc0(sizeof(CPUMIPSTLBContext));
679
680 switch (def->mmu_type) {
681 case MMU_TYPE_NONE:
682 no_mmu_init(env, def);
683 break;
684 case MMU_TYPE_R4000:
685 r4k_mmu_init(env, def);
686 break;
687 case MMU_TYPE_FMT:
688 fixed_mmu_init(env, def);
689 break;
690 case MMU_TYPE_R3000:
691 case MMU_TYPE_R6000:
692 case MMU_TYPE_R8000:
693 default:
694 cpu_abort(CPU(cpu), "MMU type not supported\n");
695 }
696 }
697 #endif /* CONFIG_USER_ONLY */
698
699 static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
700 {
701 int i;
702
703 for (i = 0; i < MIPS_FPU_MAX; i++)
704 env->fpus[i].fcr0 = def->CP1_fcr0;
705
706 memcpy(&env->active_fpu, &env->fpus[0], sizeof(env->active_fpu));
707 }
708
709 static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
710 {
711 env->mvp = g_malloc0(sizeof(CPUMIPSMVPContext));
712
713 /* MVPConf1 implemented, TLB sharable, no gating storage support,
714 programmable cache partitioning implemented, number of allocatable
715 and sharable TLB entries, MVP has allocatable TCs, 2 VPEs
716 implemented, 5 TCs implemented. */
717 env->mvp->CP0_MVPConf0 = (1U << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
718 (0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
719 // TODO: actually do 2 VPEs.
720 // (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
721 // (0x04 << CP0MVPC0_PTC);
722 (1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
723 (0x00 << CP0MVPC0_PTC);
724 #if !defined(CONFIG_USER_ONLY)
725 /* Usermode has no TLB support */
726 env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
727 #endif
728
729 /* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
730 no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
731 env->mvp->CP0_MVPConf1 = (1U << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
732 (0x0 << CP0MVPC1_PCX) | (0x0 << CP0MVPC1_PCP2) |
733 (0x1 << CP0MVPC1_PCP1);
734 }
735
736 static void msa_reset(CPUMIPSState *env)
737 {
738 #ifdef CONFIG_USER_ONLY
739 /* MSA access enabled */
740 env->CP0_Config5 |= 1 << CP0C5_MSAEn;
741 env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR);
742 #endif
743
744 /* MSA CSR:
745 - non-signaling floating point exception mode off (NX bit is 0)
746 - Cause, Enables, and Flags are all 0
747 - round to nearest / ties to even (RM bits are 0) */
748 env->active_tc.msacsr = 0;
749
750 /* tininess detected after rounding.*/
751 set_float_detect_tininess(float_tininess_after_rounding,
752 &env->active_tc.msa_fp_status);
753
754 /* clear float_status exception flags */
755 set_float_exception_flags(0, &env->active_tc.msa_fp_status);
756
757 /* set float_status rounding mode */
758 set_float_rounding_mode(float_round_nearest_even,
759 &env->active_tc.msa_fp_status);
760
761 /* set float_status flush modes */
762 set_flush_to_zero(0, &env->active_tc.msa_fp_status);
763 set_flush_inputs_to_zero(0, &env->active_tc.msa_fp_status);
764
765 /* clear float_status nan mode */
766 set_default_nan_mode(0, &env->active_tc.msa_fp_status);
767 }
QEMU modified to work with kvm