?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
ppc: memory: Replace memory_region_init_ram with memory_region_allocate_system_memory
[qemu-kvm.git] / hw / ppc / ppc405_boards.c
blob6b566cd8e582c6590608bdcc7c6009be8899672a
1 /*
2 * QEMU PowerPC 405 evaluation boards emulation
3 *
4 * Copyright (c) 2007 Jocelyn Mayer
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "hw/hw.h"
25 #include "hw/ppc/ppc.h"
26 #include "ppc405.h"
27 #include "hw/timer/m48t59.h"
28 #include "hw/block/flash.h"
29 #include "sysemu/sysemu.h"
30 #include "sysemu/qtest.h"
31 #include "block/block.h"
32 #include "hw/boards.h"
33 #include "qemu/log.h"
34 #include "qemu/error-report.h"
35 #include "hw/loader.h"
36 #include "sysemu/blockdev.h"
37 #include "exec/address-spaces.h"
38
39 #define BIOS_FILENAME "ppc405_rom.bin"
40 #define BIOS_SIZE (2048 * 1024)
41
42 #define KERNEL_LOAD_ADDR 0x00000000
43 #define INITRD_LOAD_ADDR 0x01800000
44
45 #define USE_FLASH_BIOS
46
47 //#define DEBUG_BOARD_INIT
48
49 /*****************************************************************************/
50 /* PPC405EP reference board (IBM) */
51 /* Standalone board with:
52 * - PowerPC 405EP CPU
53 * - SDRAM (0x00000000)
54 * - Flash (0xFFF80000)
55 * - SRAM (0xFFF00000)
56 * - NVRAM (0xF0000000)
57 * - FPGA (0xF0300000)
58 */
59 typedef struct ref405ep_fpga_t ref405ep_fpga_t;
60 struct ref405ep_fpga_t {
61 uint8_t reg0;
62 uint8_t reg1;
63 };
64
65 static uint32_t ref405ep_fpga_readb (void *opaque, hwaddr addr)
66 {
67 ref405ep_fpga_t *fpga;
68 uint32_t ret;
69
70 fpga = opaque;
71 switch (addr) {
72 case 0x0:
73 ret = fpga->reg0;
74 break;
75 case 0x1:
76 ret = fpga->reg1;
77 break;
78 default:
79 ret = 0;
80 break;
81 }
82
83 return ret;
84 }
85
86 static void ref405ep_fpga_writeb (void *opaque,
87 hwaddr addr, uint32_t value)
88 {
89 ref405ep_fpga_t *fpga;
90
91 fpga = opaque;
92 switch (addr) {
93 case 0x0:
94 /* Read only */
95 break;
96 case 0x1:
97 fpga->reg1 = value;
98 break;
99 default:
100 break;
101 }
102 }
103
104 static uint32_t ref405ep_fpga_readw (void *opaque, hwaddr addr)
105 {
106 uint32_t ret;
107
108 ret = ref405ep_fpga_readb(opaque, addr) << 8;
109 ret |= ref405ep_fpga_readb(opaque, addr + 1);
110
111 return ret;
112 }
113
114 static void ref405ep_fpga_writew (void *opaque,
115 hwaddr addr, uint32_t value)
116 {
117 ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
118 ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
119 }
120
121 static uint32_t ref405ep_fpga_readl (void *opaque, hwaddr addr)
122 {
123 uint32_t ret;
124
125 ret = ref405ep_fpga_readb(opaque, addr) << 24;
126 ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
127 ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
128 ret |= ref405ep_fpga_readb(opaque, addr + 3);
129
130 return ret;
131 }
132
133 static void ref405ep_fpga_writel (void *opaque,
134 hwaddr addr, uint32_t value)
135 {
136 ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
137 ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
138 ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF);
139 ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
140 }
141
142 static const MemoryRegionOps ref405ep_fpga_ops = {
143 .old_mmio = {
144 .read = {
145 ref405ep_fpga_readb, ref405ep_fpga_readw, ref405ep_fpga_readl,
146 },
147 .write = {
148 ref405ep_fpga_writeb, ref405ep_fpga_writew, ref405ep_fpga_writel,
149 },
150 },
151 .endianness = DEVICE_NATIVE_ENDIAN,
152 };
153
154 static void ref405ep_fpga_reset (void *opaque)
155 {
156 ref405ep_fpga_t *fpga;
157
158 fpga = opaque;
159 fpga->reg0 = 0x00;
160 fpga->reg1 = 0x0F;
161 }
162
163 static void ref405ep_fpga_init(MemoryRegion *sysmem, uint32_t base)
164 {
165 ref405ep_fpga_t *fpga;
166 MemoryRegion *fpga_memory = g_new(MemoryRegion, 1);
167
168 fpga = g_malloc0(sizeof(ref405ep_fpga_t));
169 memory_region_init_io(fpga_memory, NULL, &ref405ep_fpga_ops, fpga,
170 "fpga", 0x00000100);
171 memory_region_add_subregion(sysmem, base, fpga_memory);
172 qemu_register_reset(&ref405ep_fpga_reset, fpga);
173 }
174
175 static void ref405ep_init(MachineState *machine)
176 {
177 ram_addr_t ram_size = machine->ram_size;
178 const char *kernel_filename = machine->kernel_filename;
179 const char *kernel_cmdline = machine->kernel_cmdline;
180 const char *initrd_filename = machine->initrd_filename;
181 char *filename;
182 ppc4xx_bd_info_t bd;
183 CPUPPCState *env;
184 qemu_irq *pic;
185 MemoryRegion *bios;
186 MemoryRegion *sram = g_new(MemoryRegion, 1);
187 ram_addr_t bdloc;
188 MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
189 hwaddr ram_bases[2], ram_sizes[2];
190 target_ulong sram_size;
191 long bios_size;
192 //int phy_addr = 0;
193 //static int phy_addr = 1;
194 target_ulong kernel_base, initrd_base;
195 long kernel_size, initrd_size;
196 int linux_boot;
197 int fl_idx, fl_sectors, len;
198 DriveInfo *dinfo;
199 MemoryRegion *sysmem = get_system_memory();
200
201 /* XXX: fix this */
202 memory_region_allocate_system_memory(&ram_memories[0], NULL, "ef405ep.ram",
203 0x08000000);
204 ram_bases[0] = 0;
205 ram_sizes[0] = 0x08000000;
206 memory_region_init(&ram_memories[1], NULL, "ef405ep.ram1", 0);
207 ram_bases[1] = 0x00000000;
208 ram_sizes[1] = 0x00000000;
209 ram_size = 128 * 1024 * 1024;
210 #ifdef DEBUG_BOARD_INIT
211 printf("%s: register cpu\n", __func__);
212 #endif
213 env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
214 33333333, &pic, kernel_filename == NULL ? 0 : 1);
215 /* allocate SRAM */
216 sram_size = 512 * 1024;
217 memory_region_allocate_system_memory(sram, NULL, "ef405ep.sram", sram_size);
218 memory_region_add_subregion(sysmem, 0xFFF00000, sram);
219 /* allocate and load BIOS */
220 #ifdef DEBUG_BOARD_INIT
221 printf("%s: register BIOS\n", __func__);
222 #endif
223 fl_idx = 0;
224 #ifdef USE_FLASH_BIOS
225 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
226 if (dinfo) {
227 bios_size = bdrv_getlength(dinfo->bdrv);
228 fl_sectors = (bios_size + 65535) >> 16;
229 #ifdef DEBUG_BOARD_INIT
230 printf("Register parallel flash %d size %lx"
231 " at addr %lx '%s' %d\n",
232 fl_idx, bios_size, -bios_size,
233 bdrv_get_device_name(dinfo->bdrv), fl_sectors);
234 #endif
235 pflash_cfi02_register((uint32_t)(-bios_size),
236 NULL, "ef405ep.bios", bios_size,
237 dinfo->bdrv, 65536, fl_sectors, 1,
238 2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
239 1);
240 fl_idx++;
241 } else
242 #endif
243 {
244 #ifdef DEBUG_BOARD_INIT
245 printf("Load BIOS from file\n");
246 #endif
247 bios = g_new(MemoryRegion, 1);
248 memory_region_allocate_system_memory(bios, NULL, "ef405ep.bios",
249 BIOS_SIZE);
250 if (bios_name == NULL)
251 bios_name = BIOS_FILENAME;
252 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
253 if (filename) {
254 bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
255 g_free(filename);
256 if (bios_size < 0 || bios_size > BIOS_SIZE) {
257 error_report("Could not load PowerPC BIOS '%s'", bios_name);
258 exit(1);
259 }
260 bios_size = (bios_size + 0xfff) & ~0xfff;
261 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
262 } else if (!qtest_enabled() || kernel_filename != NULL) {
263 error_report("Could not load PowerPC BIOS '%s'", bios_name);
264 exit(1);
265 } else {
266 /* Avoid an uninitialized variable warning */
267 bios_size = -1;
268 }
269 memory_region_set_readonly(bios, true);
270 }
271 /* Register FPGA */
272 #ifdef DEBUG_BOARD_INIT
273 printf("%s: register FPGA\n", __func__);
274 #endif
275 ref405ep_fpga_init(sysmem, 0xF0300000);
276 /* Register NVRAM */
277 #ifdef DEBUG_BOARD_INIT
278 printf("%s: register NVRAM\n", __func__);
279 #endif
280 m48t59_init(NULL, 0xF0000000, 0, 8192, 8);
281 /* Load kernel */
282 linux_boot = (kernel_filename != NULL);
283 if (linux_boot) {
284 #ifdef DEBUG_BOARD_INIT
285 printf("%s: load kernel\n", __func__);
286 #endif
287 memset(&bd, 0, sizeof(bd));
288 bd.bi_memstart = 0x00000000;
289 bd.bi_memsize = ram_size;
290 bd.bi_flashstart = -bios_size;
291 bd.bi_flashsize = -bios_size;
292 bd.bi_flashoffset = 0;
293 bd.bi_sramstart = 0xFFF00000;
294 bd.bi_sramsize = sram_size;
295 bd.bi_bootflags = 0;
296 bd.bi_intfreq = 133333333;
297 bd.bi_busfreq = 33333333;
298 bd.bi_baudrate = 115200;
299 bd.bi_s_version[0] = 'Q';
300 bd.bi_s_version[1] = 'M';
301 bd.bi_s_version[2] = 'U';
302 bd.bi_s_version[3] = '\0';
303 bd.bi_r_version[0] = 'Q';
304 bd.bi_r_version[1] = 'E';
305 bd.bi_r_version[2] = 'M';
306 bd.bi_r_version[3] = 'U';
307 bd.bi_r_version[4] = '\0';
308 bd.bi_procfreq = 133333333;
309 bd.bi_plb_busfreq = 33333333;
310 bd.bi_pci_busfreq = 33333333;
311 bd.bi_opbfreq = 33333333;
312 bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
313 env->gpr[3] = bdloc;
314 kernel_base = KERNEL_LOAD_ADDR;
315 /* now we can load the kernel */
316 kernel_size = load_image_targphys(kernel_filename, kernel_base,
317 ram_size - kernel_base);
318 if (kernel_size < 0) {
319 fprintf(stderr, "qemu: could not load kernel '%s'\n",
320 kernel_filename);
321 exit(1);
322 }
323 printf("Load kernel size %ld at " TARGET_FMT_lx,
324 kernel_size, kernel_base);
325 /* load initrd */
326 if (initrd_filename) {
327 initrd_base = INITRD_LOAD_ADDR;
328 initrd_size = load_image_targphys(initrd_filename, initrd_base,
329 ram_size - initrd_base);
330 if (initrd_size < 0) {
331 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
332 initrd_filename);
333 exit(1);
334 }
335 } else {
336 initrd_base = 0;
337 initrd_size = 0;
338 }
339 env->gpr[4] = initrd_base;
340 env->gpr[5] = initrd_size;
341 if (kernel_cmdline != NULL) {
342 len = strlen(kernel_cmdline);
343 bdloc -= ((len + 255) & ~255);
344 cpu_physical_memory_write(bdloc, kernel_cmdline, len + 1);
345 env->gpr[6] = bdloc;
346 env->gpr[7] = bdloc + len;
347 } else {
348 env->gpr[6] = 0;
349 env->gpr[7] = 0;
350 }
351 env->nip = KERNEL_LOAD_ADDR;
352 } else {
353 kernel_base = 0;
354 kernel_size = 0;
355 initrd_base = 0;
356 initrd_size = 0;
357 bdloc = 0;
358 }
359 #ifdef DEBUG_BOARD_INIT
360 printf("bdloc " RAM_ADDR_FMT "\n", bdloc);
361 printf("%s: Done\n", __func__);
362 #endif
363 }
364
365 static QEMUMachine ref405ep_machine = {
366 .name = "ref405ep",
367 .desc = "ref405ep",
368 .init = ref405ep_init,
369 };
370
371 /*****************************************************************************/
372 /* AMCC Taihu evaluation board */
373 /* - PowerPC 405EP processor
374 * - SDRAM 128 MB at 0x00000000
375 * - Boot flash 2 MB at 0xFFE00000
376 * - Application flash 32 MB at 0xFC000000
377 * - 2 serial ports
378 * - 2 ethernet PHY
379 * - 1 USB 1.1 device 0x50000000
380 * - 1 LCD display 0x50100000
381 * - 1 CPLD 0x50100000
382 * - 1 I2C EEPROM
383 * - 1 I2C thermal sensor
384 * - a set of LEDs
385 * - bit-bang SPI port using GPIOs
386 * - 1 EBC interface connector 0 0x50200000
387 * - 1 cardbus controller + expansion slot.
388 * - 1 PCI expansion slot.
389 */
390 typedef struct taihu_cpld_t taihu_cpld_t;
391 struct taihu_cpld_t {
392 uint8_t reg0;
393 uint8_t reg1;
394 };
395
396 static uint32_t taihu_cpld_readb (void *opaque, hwaddr addr)
397 {
398 taihu_cpld_t *cpld;
399 uint32_t ret;
400
401 cpld = opaque;
402 switch (addr) {
403 case 0x0:
404 ret = cpld->reg0;
405 break;
406 case 0x1:
407 ret = cpld->reg1;
408 break;
409 default:
410 ret = 0;
411 break;
412 }
413
414 return ret;
415 }
416
417 static void taihu_cpld_writeb (void *opaque,
418 hwaddr addr, uint32_t value)
419 {
420 taihu_cpld_t *cpld;
421
422 cpld = opaque;
423 switch (addr) {
424 case 0x0:
425 /* Read only */
426 break;
427 case 0x1:
428 cpld->reg1 = value;
429 break;
430 default:
431 break;
432 }
433 }
434
435 static uint32_t taihu_cpld_readw (void *opaque, hwaddr addr)
436 {
437 uint32_t ret;
438
439 ret = taihu_cpld_readb(opaque, addr) << 8;
440 ret |= taihu_cpld_readb(opaque, addr + 1);
441
442 return ret;
443 }
444
445 static void taihu_cpld_writew (void *opaque,
446 hwaddr addr, uint32_t value)
447 {
448 taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
449 taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
450 }
451
452 static uint32_t taihu_cpld_readl (void *opaque, hwaddr addr)
453 {
454 uint32_t ret;
455
456 ret = taihu_cpld_readb(opaque, addr) << 24;
457 ret |= taihu_cpld_readb(opaque, addr + 1) << 16;
458 ret |= taihu_cpld_readb(opaque, addr + 2) << 8;
459 ret |= taihu_cpld_readb(opaque, addr + 3);
460
461 return ret;
462 }
463
464 static void taihu_cpld_writel (void *opaque,
465 hwaddr addr, uint32_t value)
466 {
467 taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
468 taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
469 taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF);
470 taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
471 }
472
473 static const MemoryRegionOps taihu_cpld_ops = {
474 .old_mmio = {
475 .read = { taihu_cpld_readb, taihu_cpld_readw, taihu_cpld_readl, },
476 .write = { taihu_cpld_writeb, taihu_cpld_writew, taihu_cpld_writel, },
477 },
478 .endianness = DEVICE_NATIVE_ENDIAN,
479 };
480
481 static void taihu_cpld_reset (void *opaque)
482 {
483 taihu_cpld_t *cpld;
484
485 cpld = opaque;
486 cpld->reg0 = 0x01;
487 cpld->reg1 = 0x80;
488 }
489
490 static void taihu_cpld_init(MemoryRegion *sysmem, uint32_t base)
491 {
492 taihu_cpld_t *cpld;
493 MemoryRegion *cpld_memory = g_new(MemoryRegion, 1);
494
495 cpld = g_malloc0(sizeof(taihu_cpld_t));
496 memory_region_init_io(cpld_memory, NULL, &taihu_cpld_ops, cpld, "cpld", 0x100);
497 memory_region_add_subregion(sysmem, base, cpld_memory);
498 qemu_register_reset(&taihu_cpld_reset, cpld);
499 }
500
501 static void taihu_405ep_init(MachineState *machine)
502 {
503 ram_addr_t ram_size = machine->ram_size;
504 const char *kernel_filename = machine->kernel_filename;
505 const char *initrd_filename = machine->initrd_filename;
506 char *filename;
507 qemu_irq *pic;
508 MemoryRegion *sysmem = get_system_memory();
509 MemoryRegion *bios;
510 MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
511 hwaddr ram_bases[2], ram_sizes[2];
512 long bios_size;
513 target_ulong kernel_base, initrd_base;
514 long kernel_size, initrd_size;
515 int linux_boot;
516 int fl_idx, fl_sectors;
517 DriveInfo *dinfo;
518
519 /* RAM is soldered to the board so the size cannot be changed */
520 memory_region_allocate_system_memory(&ram_memories[0], NULL,
521 "taihu_405ep.ram-0", 0x04000000);
522 ram_bases[0] = 0;
523 ram_sizes[0] = 0x04000000;
524 memory_region_allocate_system_memory(&ram_memories[1], NULL,
525 "taihu_405ep.ram-1", 0x04000000);
526 ram_bases[1] = 0x04000000;
527 ram_sizes[1] = 0x04000000;
528 ram_size = 0x08000000;
529 #ifdef DEBUG_BOARD_INIT
530 printf("%s: register cpu\n", __func__);
531 #endif
532 ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
533 33333333, &pic, kernel_filename == NULL ? 0 : 1);
534 /* allocate and load BIOS */
535 #ifdef DEBUG_BOARD_INIT
536 printf("%s: register BIOS\n", __func__);
537 #endif
538 fl_idx = 0;
539 #if defined(USE_FLASH_BIOS)
540 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
541 if (dinfo) {
542 bios_size = bdrv_getlength(dinfo->bdrv);
543 /* XXX: should check that size is 2MB */
544 // bios_size = 2 * 1024 * 1024;
545 fl_sectors = (bios_size + 65535) >> 16;
546 #ifdef DEBUG_BOARD_INIT
547 printf("Register parallel flash %d size %lx"
548 " at addr %lx '%s' %d\n",
549 fl_idx, bios_size, -bios_size,
550 bdrv_get_device_name(dinfo->bdrv), fl_sectors);
551 #endif
552 pflash_cfi02_register((uint32_t)(-bios_size),
553 NULL, "taihu_405ep.bios", bios_size,
554 dinfo->bdrv, 65536, fl_sectors, 1,
555 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
556 1);
557 fl_idx++;
558 } else
559 #endif
560 {
561 #ifdef DEBUG_BOARD_INIT
562 printf("Load BIOS from file\n");
563 #endif
564 if (bios_name == NULL)
565 bios_name = BIOS_FILENAME;
566 bios = g_new(MemoryRegion, 1);
567 memory_region_allocate_system_memory(bios, NULL, "taihu_405ep.bios",
568 BIOS_SIZE);
569 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
570 if (filename) {
571 bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
572 g_free(filename);
573 if (bios_size < 0 || bios_size > BIOS_SIZE) {
574 error_report("Could not load PowerPC BIOS '%s'", bios_name);
575 exit(1);
576 }
577 bios_size = (bios_size + 0xfff) & ~0xfff;
578 memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
579 } else if (!qtest_enabled()) {
580 error_report("Could not load PowerPC BIOS '%s'", bios_name);
581 exit(1);
582 }
583 memory_region_set_readonly(bios, true);
584 }
585 /* Register Linux flash */
586 dinfo = drive_get(IF_PFLASH, 0, fl_idx);
587 if (dinfo) {
588 bios_size = bdrv_getlength(dinfo->bdrv);
589 /* XXX: should check that size is 32MB */
590 bios_size = 32 * 1024 * 1024;
591 fl_sectors = (bios_size + 65535) >> 16;
592 #ifdef DEBUG_BOARD_INIT
593 printf("Register parallel flash %d size %lx"
594 " at addr " TARGET_FMT_lx " '%s'\n",
595 fl_idx, bios_size, (target_ulong)0xfc000000,
596 bdrv_get_device_name(dinfo->bdrv));
597 #endif
598 pflash_cfi02_register(0xfc000000, NULL, "taihu_405ep.flash", bios_size,
599 dinfo->bdrv, 65536, fl_sectors, 1,
600 4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
601 1);
602 fl_idx++;
603 }
604 /* Register CLPD & LCD display */
605 #ifdef DEBUG_BOARD_INIT
606 printf("%s: register CPLD\n", __func__);
607 #endif
608 taihu_cpld_init(sysmem, 0x50100000);
609 /* Load kernel */
610 linux_boot = (kernel_filename != NULL);
611 if (linux_boot) {
612 #ifdef DEBUG_BOARD_INIT
613 printf("%s: load kernel\n", __func__);
614 #endif
615 kernel_base = KERNEL_LOAD_ADDR;
616 /* now we can load the kernel */
617 kernel_size = load_image_targphys(kernel_filename, kernel_base,
618 ram_size - kernel_base);
619 if (kernel_size < 0) {
620 fprintf(stderr, "qemu: could not load kernel '%s'\n",
621 kernel_filename);
622 exit(1);
623 }
624 /* load initrd */
625 if (initrd_filename) {
626 initrd_base = INITRD_LOAD_ADDR;
627 initrd_size = load_image_targphys(initrd_filename, initrd_base,
628 ram_size - initrd_base);
629 if (initrd_size < 0) {
630 fprintf(stderr,
631 "qemu: could not load initial ram disk '%s'\n",
632 initrd_filename);
633 exit(1);
634 }
635 } else {
636 initrd_base = 0;
637 initrd_size = 0;
638 }
639 } else {
640 kernel_base = 0;
641 kernel_size = 0;
642 initrd_base = 0;
643 initrd_size = 0;
644 }
645 #ifdef DEBUG_BOARD_INIT
646 printf("%s: Done\n", __func__);
647 #endif
648 }
649
650 static QEMUMachine taihu_machine = {
651 .name = "taihu",
652 .desc = "taihu",
653 .init = taihu_405ep_init,
654 };
655
656 static void ppc405_machine_init(void)
657 {
658 qemu_register_machine(&ref405ep_machine);
659 qemu_register_machine(&taihu_machine);
660 }
661
662 machine_init(ppc405_machine_init);
QEMU modified to work with kvm