target-arm/helper.c

   1 #include "cpu.h"
   2 #include "internals.h"
   3 #include "exec/gdbstub.h"
   4 #include "helper.h"
   5 #include "qemu/host-utils.h"
   6 #include "sysemu/arch_init.h"
   7 #include "sysemu/sysemu.h"
   8 #include "qemu/bitops.h"
   9 #include "qemu/crc32c.h"
  10 #include <zlib.h> /* For crc32 */
  11
  12 #ifndef CONFIG_USER_ONLY
  13 #include "exec/softmmu_exec.h"
  14
  15 static inline int get_phys_addr(CPUARMState *env, target_ulong address,
  16                                 int access_type, int is_user,
  17                                 hwaddr *phys_ptr, int *prot,
  18                                 target_ulong *page_size);
  19
  20 /* Definitions for the PMCCNTR and PMCR registers */
  21 #define PMCRD   0x8
  22 #define PMCRC   0x4
  23 #define PMCRE   0x1
  24 #endif
  25
  26 static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  27 {
  28     int nregs;
  29
  30     /* VFP data registers are always little-endian.  */
  31     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  32     if (reg < nregs) {
  33         stfq_le_p(buf, env->vfp.regs[reg]);
  34         return 8;
  35     }
  36     if (arm_feature(env, ARM_FEATURE_NEON)) {
  37         /* Aliases for Q regs.  */
  38         nregs += 16;
  39         if (reg < nregs) {
  40             stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]);
  41             stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]);
  42             return 16;
  43         }
  44     }
  45     switch (reg - nregs) {
  46     case 0: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSID]); return 4;
  47     case 1: stl_p(buf, env->vfp.xregs[ARM_VFP_FPSCR]); return 4;
  48     case 2: stl_p(buf, env->vfp.xregs[ARM_VFP_FPEXC]); return 4;
  49     }
  50     return 0;
  51 }
  52
  53 static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
  54 {
  55     int nregs;
  56
  57     nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16;
  58     if (reg < nregs) {
  59         env->vfp.regs[reg] = ldfq_le_p(buf);
  60         return 8;
  61     }
  62     if (arm_feature(env, ARM_FEATURE_NEON)) {
  63         nregs += 16;
  64         if (reg < nregs) {
  65             env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf);
  66             env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8);
  67             return 16;
  68         }
  69     }
  70     switch (reg - nregs) {
  71     case 0: env->vfp.xregs[ARM_VFP_FPSID] = ldl_p(buf); return 4;
  72     case 1: env->vfp.xregs[ARM_VFP_FPSCR] = ldl_p(buf); return 4;
  73     case 2: env->vfp.xregs[ARM_VFP_FPEXC] = ldl_p(buf) & (1 << 30); return 4;
  74     }
  75     return 0;
  76 }
  77
  78 static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
  79 {
  80     switch (reg) {
  81     case 0 ... 31:
  82         /* 128 bit FP register */
  83         stfq_le_p(buf, env->vfp.regs[reg * 2]);
  84         stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]);
  85         return 16;
  86     case 32:
  87         /* FPSR */
  88         stl_p(buf, vfp_get_fpsr(env));
  89         return 4;
  90     case 33:
  91         /* FPCR */
  92         stl_p(buf, vfp_get_fpcr(env));
  93         return 4;
  94     default:
  95         return 0;
  96     }
  97 }
  98
  99 static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
 100 {
 101     switch (reg) {
 102     case 0 ... 31:
 103         /* 128 bit FP register */
 104         env->vfp.regs[reg * 2] = ldfq_le_p(buf);
 105         env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8);
 106         return 16;
 107     case 32:
 108         /* FPSR */
 109         vfp_set_fpsr(env, ldl_p(buf));
 110         return 4;
 111     case 33:
 112         /* FPCR */
 113         vfp_set_fpcr(env, ldl_p(buf));
 114         return 4;
 115     default:
 116         return 0;
 117     }
 118 }
 119
 120 static uint64_t raw_read(CPUARMState *env, const ARMCPRegInfo *ri)
 121 {
 122     if (cpreg_field_is_64bit(ri)) {
 123         return CPREG_FIELD64(env, ri);
 124     } else {
 125         return CPREG_FIELD32(env, ri);
 126     }
 127 }
 128
 129 static void raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
 130                       uint64_t value)
 131 {
 132     if (cpreg_field_is_64bit(ri)) {
 133         CPREG_FIELD64(env, ri) = value;
 134     } else {
 135         CPREG_FIELD32(env, ri) = value;
 136     }
 137 }
 138
 139 static uint64_t read_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri)
 140 {
 141     /* Raw read of a coprocessor register (as needed for migration, etc). */
 142     if (ri->type & ARM_CP_CONST) {
 143         return ri->resetvalue;
 144     } else if (ri->raw_readfn) {
 145         return ri->raw_readfn(env, ri);
 146     } else if (ri->readfn) {
 147         return ri->readfn(env, ri);
 148     } else {
 149         return raw_read(env, ri);
 150     }
 151 }
 152
 153 static void write_raw_cp_reg(CPUARMState *env, const ARMCPRegInfo *ri,
 154                              uint64_t v)
 155 {
 156     /* Raw write of a coprocessor register (as needed for migration, etc).
 157      * Note that constant registers are treated as write-ignored; the
 158      * caller should check for success by whether a readback gives the
 159      * value written.
 160      */
 161     if (ri->type & ARM_CP_CONST) {
 162         return;
 163     } else if (ri->raw_writefn) {
 164         ri->raw_writefn(env, ri, v);
 165     } else if (ri->writefn) {
 166         ri->writefn(env, ri, v);
 167     } else {
 168         raw_write(env, ri, v);
 169     }
 170 }
 171
 172 bool write_cpustate_to_list(ARMCPU *cpu)
 173 {
 174     /* Write the coprocessor state from cpu->env to the (index,value) list. */
 175     int i;
 176     bool ok = true;
 177
 178     for (i = 0; i < cpu->cpreg_array_len; i++) {
 179         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 180         const ARMCPRegInfo *ri;
 181
 182         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 183         if (!ri) {
 184             ok = false;
 185             continue;
 186         }
 187         if (ri->type & ARM_CP_NO_MIGRATE) {
 188             continue;
 189         }
 190         cpu->cpreg_values[i] = read_raw_cp_reg(&cpu->env, ri);
 191     }
 192     return ok;
 193 }
 194
 195 bool write_list_to_cpustate(ARMCPU *cpu)
 196 {
 197     int i;
 198     bool ok = true;
 199
 200     for (i = 0; i < cpu->cpreg_array_len; i++) {
 201         uint32_t regidx = kvm_to_cpreg_id(cpu->cpreg_indexes[i]);
 202         uint64_t v = cpu->cpreg_values[i];
 203         const ARMCPRegInfo *ri;
 204
 205         ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 206         if (!ri) {
 207             ok = false;
 208             continue;
 209         }
 210         if (ri->type & ARM_CP_NO_MIGRATE) {
 211             continue;
 212         }
 213         /* Write value and confirm it reads back as written
 214          * (to catch read-only registers and partially read-only
 215          * registers where the incoming migration value doesn't match)
 216          */
 217         write_raw_cp_reg(&cpu->env, ri, v);
 218         if (read_raw_cp_reg(&cpu->env, ri) != v) {
 219             ok = false;
 220         }
 221     }
 222     return ok;
 223 }
 224
 225 static void add_cpreg_to_list(gpointer key, gpointer opaque)
 226 {
 227     ARMCPU *cpu = opaque;
 228     uint64_t regidx;
 229     const ARMCPRegInfo *ri;
 230
 231     regidx = *(uint32_t *)key;
 232     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 233
 234     if (!(ri->type & ARM_CP_NO_MIGRATE)) {
 235         cpu->cpreg_indexes[cpu->cpreg_array_len] = cpreg_to_kvm_id(regidx);
 236         /* The value array need not be initialized at this point */
 237         cpu->cpreg_array_len++;
 238     }
 239 }
 240
 241 static void count_cpreg(gpointer key, gpointer opaque)
 242 {
 243     ARMCPU *cpu = opaque;
 244     uint64_t regidx;
 245     const ARMCPRegInfo *ri;
 246
 247     regidx = *(uint32_t *)key;
 248     ri = get_arm_cp_reginfo(cpu->cp_regs, regidx);
 249
 250     if (!(ri->type & ARM_CP_NO_MIGRATE)) {
 251         cpu->cpreg_array_len++;
 252     }
 253 }
 254
 255 static gint cpreg_key_compare(gconstpointer a, gconstpointer b)
 256 {
 257     uint64_t aidx = cpreg_to_kvm_id(*(uint32_t *)a);
 258     uint64_t bidx = cpreg_to_kvm_id(*(uint32_t *)b);
 259
 260     if (aidx > bidx) {
 261         return 1;
 262     }
 263     if (aidx < bidx) {
 264         return -1;
 265     }
 266     return 0;
 267 }
 268
 269 static void cpreg_make_keylist(gpointer key, gpointer value, gpointer udata)
 270 {
 271     GList **plist = udata;
 272
 273     *plist = g_list_prepend(*plist, key);
 274 }
 275
 276 void init_cpreg_list(ARMCPU *cpu)
 277 {
 278     /* Initialise the cpreg_tuples[] array based on the cp_regs hash.
 279      * Note that we require cpreg_tuples[] to be sorted by key ID.
 280      */
 281     GList *keys = NULL;
 282     int arraylen;
 283
 284     g_hash_table_foreach(cpu->cp_regs, cpreg_make_keylist, &keys);
 285
 286     keys = g_list_sort(keys, cpreg_key_compare);
 287
 288     cpu->cpreg_array_len = 0;
 289
 290     g_list_foreach(keys, count_cpreg, cpu);
 291
 292     arraylen = cpu->cpreg_array_len;
 293     cpu->cpreg_indexes = g_new(uint64_t, arraylen);
 294     cpu->cpreg_values = g_new(uint64_t, arraylen);
 295     cpu->cpreg_vmstate_indexes = g_new(uint64_t, arraylen);
 296     cpu->cpreg_vmstate_values = g_new(uint64_t, arraylen);
 297     cpu->cpreg_vmstate_array_len = cpu->cpreg_array_len;
 298     cpu->cpreg_array_len = 0;
 299
 300     g_list_foreach(keys, add_cpreg_to_list, cpu);
 301
 302     assert(cpu->cpreg_array_len == arraylen);
 303
 304     g_list_free(keys);
 305 }
 306
 307 /* Return true if extended addresses are enabled.
 308  * This is always the case if our translation regime is 64 bit,
 309  * but depends on TTBCR.EAE for 32 bit.
 310  */
 311 static inline bool extended_addresses_enabled(CPUARMState *env)
 312 {
 313     return arm_el_is_aa64(env, 1)
 314         || ((arm_feature(env, ARM_FEATURE_LPAE)
 315              && (env->cp15.c2_control & (1U << 31))));
 316 }
 317
 318 static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 319 {
 320     ARMCPU *cpu = arm_env_get_cpu(env);
 321
 322     env->cp15.c3 = value;
 323     tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
 324 }
 325
 326 static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
 327 {
 328     ARMCPU *cpu = arm_env_get_cpu(env);
 329
 330     if (env->cp15.c13_fcse != value) {
 331         /* Unlike real hardware the qemu TLB uses virtual addresses,
 332          * not modified virtual addresses, so this causes a TLB flush.
 333          */
 334         tlb_flush(CPU(cpu), 1);
 335         env->cp15.c13_fcse = value;
 336     }
 337 }
 338
 339 static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 340                              uint64_t value)
 341 {
 342     ARMCPU *cpu = arm_env_get_cpu(env);
 343
 344     if (env->cp15.contextidr_el1 != value && !arm_feature(env, ARM_FEATURE_MPU)
 345         && !extended_addresses_enabled(env)) {
 346         /* For VMSA (when not using the LPAE long descriptor page table
 347          * format) this register includes the ASID, so do a TLB flush.
 348          * For PMSA it is purely a process ID and no action is needed.
 349          */
 350         tlb_flush(CPU(cpu), 1);
 351     }
 352     env->cp15.contextidr_el1 = value;
 353 }
 354
 355 static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
 356                           uint64_t value)
 357 {
 358     /* Invalidate all (TLBIALL) */
 359     ARMCPU *cpu = arm_env_get_cpu(env);
 360
 361     tlb_flush(CPU(cpu), 1);
 362 }
 363
 364 static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
 365                           uint64_t value)
 366 {
 367     /* Invalidate single TLB entry by MVA and ASID (TLBIMVA) */
 368     ARMCPU *cpu = arm_env_get_cpu(env);
 369
 370     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 371 }
 372
 373 static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
 374                            uint64_t value)
 375 {
 376     /* Invalidate by ASID (TLBIASID) */
 377     ARMCPU *cpu = arm_env_get_cpu(env);
 378
 379     tlb_flush(CPU(cpu), value == 0);
 380 }
 381
 382 static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
 383                            uint64_t value)
 384 {
 385     /* Invalidate single entry by MVA, all ASIDs (TLBIMVAA) */
 386     ARMCPU *cpu = arm_env_get_cpu(env);
 387
 388     tlb_flush_page(CPU(cpu), value & TARGET_PAGE_MASK);
 389 }
 390
 391 static const ARMCPRegInfo cp_reginfo[] = {
 392     /* DBGDIDR: just RAZ. In particular this means the "debug architecture
 393      * version" bits will read as a reserved value, which should cause
 394      * Linux to not try to use the debug hardware.
 395      */
 396     { .name = "DBGDIDR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 0,
 397       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 398     { .name = "FCSEIDR", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 0,
 399       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c13_fcse),
 400       .resetvalue = 0, .writefn = fcse_write, .raw_writefn = raw_write, },
 401     { .name = "CONTEXTIDR", .state = ARM_CP_STATE_BOTH,
 402       .opc0 = 3, .opc1 = 0, .crn = 13, .crm = 0, .opc2 = 1,
 403       .access = PL1_RW,
 404       .fieldoffset = offsetof(CPUARMState, cp15.contextidr_el1),
 405       .resetvalue = 0, .writefn = contextidr_write, .raw_writefn = raw_write, },
 406     REGINFO_SENTINEL
 407 };
 408
 409 static const ARMCPRegInfo not_v8_cp_reginfo[] = {
 410     /* NB: Some of these registers exist in v8 but with more precise
 411      * definitions that don't use CP_ANY wildcards (mostly in v8_cp_reginfo[]).
 412      */
 413     /* MMU Domain access control / MPU write buffer control */
 414     { .name = "DACR", .cp = 15,
 415       .crn = 3, .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
 416       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
 417       .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
 418     /* ??? This covers not just the impdef TLB lockdown registers but also
 419      * some v7VMSA registers relating to TEX remap, so it is overly broad.
 420      */
 421     { .name = "TLB_LOCKDOWN", .cp = 15, .crn = 10, .crm = CP_ANY,
 422       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_NOP },
 423     /* MMU TLB control. Note that the wildcarding means we cover not just
 424      * the unified TLB ops but also the dside/iside/inner-shareable variants.
 425      */
 426     { .name = "TLBIALL", .cp = 15, .crn = 8, .crm = CP_ANY,
 427       .opc1 = CP_ANY, .opc2 = 0, .access = PL1_W, .writefn = tlbiall_write,
 428       .type = ARM_CP_NO_MIGRATE },
 429     { .name = "TLBIMVA", .cp = 15, .crn = 8, .crm = CP_ANY,
 430       .opc1 = CP_ANY, .opc2 = 1, .access = PL1_W, .writefn = tlbimva_write,
 431       .type = ARM_CP_NO_MIGRATE },
 432     { .name = "TLBIASID", .cp = 15, .crn = 8, .crm = CP_ANY,
 433       .opc1 = CP_ANY, .opc2 = 2, .access = PL1_W, .writefn = tlbiasid_write,
 434       .type = ARM_CP_NO_MIGRATE },
 435     { .name = "TLBIMVAA", .cp = 15, .crn = 8, .crm = CP_ANY,
 436       .opc1 = CP_ANY, .opc2 = 3, .access = PL1_W, .writefn = tlbimvaa_write,
 437       .type = ARM_CP_NO_MIGRATE },
 438     /* Cache maintenance ops; some of this space may be overridden later. */
 439     { .name = "CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
 440       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
 441       .type = ARM_CP_NOP | ARM_CP_OVERRIDE },
 442     REGINFO_SENTINEL
 443 };
 444
 445 static const ARMCPRegInfo not_v6_cp_reginfo[] = {
 446     /* Not all pre-v6 cores implemented this WFI, so this is slightly
 447      * over-broad.
 448      */
 449     { .name = "WFI_v5", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = 2,
 450       .access = PL1_W, .type = ARM_CP_WFI },
 451     REGINFO_SENTINEL
 452 };
 453
 454 static const ARMCPRegInfo not_v7_cp_reginfo[] = {
 455     /* Standard v6 WFI (also used in some pre-v6 cores); not in v7 (which
 456      * is UNPREDICTABLE; we choose to NOP as most implementations do).
 457      */
 458     { .name = "WFI_v6", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 459       .access = PL1_W, .type = ARM_CP_WFI },
 460     /* L1 cache lockdown. Not architectural in v6 and earlier but in practice
 461      * implemented in 926, 946, 1026, 1136, 1176 and 11MPCore. StrongARM and
 462      * OMAPCP will override this space.
 463      */
 464     { .name = "DLOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 0,
 465       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_data),
 466       .resetvalue = 0 },
 467     { .name = "ILOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 0, .opc2 = 1,
 468       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_insn),
 469       .resetvalue = 0 },
 470     /* v6 doesn't have the cache ID registers but Linux reads them anyway */
 471     { .name = "DUMMY", .cp = 15, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = CP_ANY,
 472       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
 473       .resetvalue = 0 },
 474     REGINFO_SENTINEL
 475 };
 476
 477 static void cpacr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 478                         uint64_t value)
 479 {
 480     if (env->cp15.c1_coproc != value) {
 481         env->cp15.c1_coproc = value;
 482         /* ??? Is this safe when called from within a TB?  */
 483         tb_flush(env);
 484     }
 485 }
 486
 487 static const ARMCPRegInfo v6_cp_reginfo[] = {
 488     /* prefetch by MVA in v6, NOP in v7 */
 489     { .name = "MVA_prefetch",
 490       .cp = 15, .crn = 7, .crm = 13, .opc1 = 0, .opc2 = 1,
 491       .access = PL1_W, .type = ARM_CP_NOP },
 492     { .name = "ISB", .cp = 15, .crn = 7, .crm = 5, .opc1 = 0, .opc2 = 4,
 493       .access = PL0_W, .type = ARM_CP_NOP },
 494     { .name = "DSB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 4,
 495       .access = PL0_W, .type = ARM_CP_NOP },
 496     { .name = "DMB", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 5,
 497       .access = PL0_W, .type = ARM_CP_NOP },
 498     { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 2,
 499       .access = PL1_RW,
 500       .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el1),
 501       .resetvalue = 0, },
 502     /* Watchpoint Fault Address Register : should actually only be present
 503      * for 1136, 1176, 11MPCore.
 504      */
 505     { .name = "WFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 506       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0, },
 507     { .name = "CPACR", .state = ARM_CP_STATE_BOTH, .opc0 = 3,
 508       .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 2,
 509       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_coproc),
 510       .resetvalue = 0, .writefn = cpacr_write },
 511     REGINFO_SENTINEL
 512 };
 513
 514 static CPAccessResult pmreg_access(CPUARMState *env, const ARMCPRegInfo *ri)
 515 {
 516     /* Performance monitor registers user accessibility is controlled
 517      * by PMUSERENR.
 518      */
 519     if (arm_current_pl(env) == 0 && !env->cp15.c9_pmuserenr) {
 520         return CP_ACCESS_TRAP;
 521     }
 522     return CP_ACCESS_OK;
 523 }
 524
 525 #ifndef CONFIG_USER_ONLY
 526 static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 527                        uint64_t value)
 528 {
 529     /* Don't computer the number of ticks in user mode */
 530     uint32_t temp_ticks;
 531
 532     temp_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
 533                   get_ticks_per_sec() / 1000000;
 534
 535     if (env->cp15.c9_pmcr & PMCRE) {
 536         /* If the counter is enabled */
 537         if (env->cp15.c9_pmcr & PMCRD) {
 538             /* Increment once every 64 processor clock cycles */
 539             env->cp15.c15_ccnt = (temp_ticks/64) - env->cp15.c15_ccnt;
 540         } else {
 541             env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
 542         }
 543     }
 544
 545     if (value & PMCRC) {
 546         /* The counter has been reset */
 547         env->cp15.c15_ccnt = 0;
 548     }
 549
 550     /* only the DP, X, D and E bits are writable */
 551     env->cp15.c9_pmcr &= ~0x39;
 552     env->cp15.c9_pmcr |= (value & 0x39);
 553
 554     if (env->cp15.c9_pmcr & PMCRE) {
 555         if (env->cp15.c9_pmcr & PMCRD) {
 556             /* Increment once every 64 processor clock cycles */
 557             temp_ticks /= 64;
 558         }
 559         env->cp15.c15_ccnt = temp_ticks - env->cp15.c15_ccnt;
 560     }
 561 }
 562
 563 static uint64_t pmccntr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 564 {
 565     uint32_t total_ticks;
 566
 567     if (!(env->cp15.c9_pmcr & PMCRE)) {
 568         /* Counter is disabled, do not change value */
 569         return env->cp15.c15_ccnt;
 570     }
 571
 572     total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
 573                   get_ticks_per_sec() / 1000000;
 574
 575     if (env->cp15.c9_pmcr & PMCRD) {
 576         /* Increment once every 64 processor clock cycles */
 577         total_ticks /= 64;
 578     }
 579     return total_ticks - env->cp15.c15_ccnt;
 580 }
 581
 582 static void pmccntr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 583                         uint64_t value)
 584 {
 585     uint32_t total_ticks;
 586
 587     if (!(env->cp15.c9_pmcr & PMCRE)) {
 588         /* Counter is disabled, set the absolute value */
 589         env->cp15.c15_ccnt = value;
 590         return;
 591     }
 592
 593     total_ticks = qemu_clock_get_us(QEMU_CLOCK_VIRTUAL) *
 594                   get_ticks_per_sec() / 1000000;
 595
 596     if (env->cp15.c9_pmcr & PMCRD) {
 597         /* Increment once every 64 processor clock cycles */
 598         total_ticks /= 64;
 599     }
 600     env->cp15.c15_ccnt = total_ticks - value;
 601 }
 602 #endif
 603
 604 static void pmcntenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 605                             uint64_t value)
 606 {
 607     value &= (1 << 31);
 608     env->cp15.c9_pmcnten |= value;
 609 }
 610
 611 static void pmcntenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 612                              uint64_t value)
 613 {
 614     value &= (1 << 31);
 615     env->cp15.c9_pmcnten &= ~value;
 616 }
 617
 618 static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 619                          uint64_t value)
 620 {
 621     env->cp15.c9_pmovsr &= ~value;
 622 }
 623
 624 static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
 625                              uint64_t value)
 626 {
 627     env->cp15.c9_pmxevtyper = value & 0xff;
 628 }
 629
 630 static void pmuserenr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 631                             uint64_t value)
 632 {
 633     env->cp15.c9_pmuserenr = value & 1;
 634 }
 635
 636 static void pmintenset_write(CPUARMState *env, const ARMCPRegInfo *ri,
 637                              uint64_t value)
 638 {
 639     /* We have no event counters so only the C bit can be changed */
 640     value &= (1 << 31);
 641     env->cp15.c9_pminten |= value;
 642 }
 643
 644 static void pmintenclr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 645                              uint64_t value)
 646 {
 647     value &= (1 << 31);
 648     env->cp15.c9_pminten &= ~value;
 649 }
 650
 651 static void vbar_write(CPUARMState *env, const ARMCPRegInfo *ri,
 652                        uint64_t value)
 653 {
 654     /* Note that even though the AArch64 view of this register has bits
 655      * [10:0] all RES0 we can only mask the bottom 5, to comply with the
 656      * architectural requirements for bits which are RES0 only in some
 657      * contexts. (ARMv8 would permit us to do no masking at all, but ARMv7
 658      * requires the bottom five bits to be RAZ/WI because they're UNK/SBZP.)
 659      */
 660     env->cp15.c12_vbar = value & ~0x1FULL;
 661 }
 662
 663 static uint64_t ccsidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 664 {
 665     ARMCPU *cpu = arm_env_get_cpu(env);
 666     return cpu->ccsidr[env->cp15.c0_cssel];
 667 }
 668
 669 static void csselr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 670                          uint64_t value)
 671 {
 672     env->cp15.c0_cssel = value & 0xf;
 673 }
 674
 675 static uint64_t isr_read(CPUARMState *env, const ARMCPRegInfo *ri)
 676 {
 677     CPUState *cs = ENV_GET_CPU(env);
 678     uint64_t ret = 0;
 679
 680     if (cs->interrupt_request & CPU_INTERRUPT_HARD) {
 681         ret |= CPSR_I;
 682     }
 683     if (cs->interrupt_request & CPU_INTERRUPT_FIQ) {
 684         ret |= CPSR_F;
 685     }
 686     /* External aborts are not possible in QEMU so A bit is always clear */
 687     return ret;
 688 }
 689
 690 static const ARMCPRegInfo v7_cp_reginfo[] = {
 691     /* DBGDRAR, DBGDSAR: always RAZ since we don't implement memory mapped
 692      * debug components
 693      */
 694     { .name = "DBGDRAR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
 695       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 696     { .name = "DBGDSAR", .cp = 14, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
 697       .access = PL0_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 698     /* the old v6 WFI, UNPREDICTABLE in v7 but we choose to NOP */
 699     { .name = "NOP", .cp = 15, .crn = 7, .crm = 0, .opc1 = 0, .opc2 = 4,
 700       .access = PL1_W, .type = ARM_CP_NOP },
 701     /* Performance monitors are implementation defined in v7,
 702      * but with an ARM recommended set of registers, which we
 703      * follow (although we don't actually implement any counters)
 704      *
 705      * Performance registers fall into three categories:
 706      *  (a) always UNDEF in PL0, RW in PL1 (PMINTENSET, PMINTENCLR)
 707      *  (b) RO in PL0 (ie UNDEF on write), RW in PL1 (PMUSERENR)
 708      *  (c) UNDEF in PL0 if PMUSERENR.EN==0, otherwise accessible (all others)
 709      * For the cases controlled by PMUSERENR we must set .access to PL0_RW
 710      * or PL0_RO as appropriate and then check PMUSERENR in the helper fn.
 711      */
 712     { .name = "PMCNTENSET", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 1,
 713       .access = PL0_RW, .resetvalue = 0,
 714       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
 715       .writefn = pmcntenset_write,
 716       .accessfn = pmreg_access,
 717       .raw_writefn = raw_write },
 718     { .name = "PMCNTENCLR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 2,
 719       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcnten),
 720       .accessfn = pmreg_access,
 721       .writefn = pmcntenclr_write,
 722       .type = ARM_CP_NO_MIGRATE },
 723     { .name = "PMOVSR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 3,
 724       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
 725       .accessfn = pmreg_access,
 726       .writefn = pmovsr_write,
 727       .raw_writefn = raw_write },
 728     /* Unimplemented so WI. */
 729     { .name = "PMSWINC", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 4,
 730       .access = PL0_W, .accessfn = pmreg_access, .type = ARM_CP_NOP },
 731     /* Since we don't implement any events, writing to PMSELR is UNPREDICTABLE.
 732      * We choose to RAZ/WI.
 733      */
 734     { .name = "PMSELR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 5,
 735       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 736       .accessfn = pmreg_access },
 737 #ifndef CONFIG_USER_ONLY
 738     { .name = "PMCCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 0,
 739       .access = PL0_RW, .resetvalue = 0, .type = ARM_CP_IO,
 740       .readfn = pmccntr_read, .writefn = pmccntr_write,
 741       .accessfn = pmreg_access },
 742 #endif
 743     { .name = "PMXEVTYPER", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 1,
 744       .access = PL0_RW,
 745       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmxevtyper),
 746       .accessfn = pmreg_access, .writefn = pmxevtyper_write,
 747       .raw_writefn = raw_write },
 748     /* Unimplemented, RAZ/WI. */
 749     { .name = "PMXEVCNTR", .cp = 15, .crn = 9, .crm = 13, .opc1 = 0, .opc2 = 2,
 750       .access = PL0_RW, .type = ARM_CP_CONST, .resetvalue = 0,
 751       .accessfn = pmreg_access },
 752     { .name = "PMUSERENR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 0,
 753       .access = PL0_R | PL1_RW,
 754       .fieldoffset = offsetof(CPUARMState, cp15.c9_pmuserenr),
 755       .resetvalue = 0,
 756       .writefn = pmuserenr_write, .raw_writefn = raw_write },
 757     { .name = "PMINTENSET", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 1,
 758       .access = PL1_RW,
 759       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
 760       .resetvalue = 0,
 761       .writefn = pmintenset_write, .raw_writefn = raw_write },
 762     { .name = "PMINTENCLR", .cp = 15, .crn = 9, .crm = 14, .opc1 = 0, .opc2 = 2,
 763       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
 764       .fieldoffset = offsetof(CPUARMState, cp15.c9_pminten),
 765       .resetvalue = 0, .writefn = pmintenclr_write, },
 766     { .name = "VBAR", .state = ARM_CP_STATE_BOTH,
 767       .opc0 = 3, .crn = 12, .crm = 0, .opc1 = 0, .opc2 = 0,
 768       .access = PL1_RW, .writefn = vbar_write,
 769       .fieldoffset = offsetof(CPUARMState, cp15.c12_vbar),
 770       .resetvalue = 0 },
 771     { .name = "SCR", .cp = 15, .crn = 1, .crm = 1, .opc1 = 0, .opc2 = 0,
 772       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_scr),
 773       .resetvalue = 0, },
 774     { .name = "CCSIDR", .state = ARM_CP_STATE_BOTH,
 775       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 0,
 776       .access = PL1_R, .readfn = ccsidr_read, .type = ARM_CP_NO_MIGRATE },
 777     { .name = "CSSELR", .state = ARM_CP_STATE_BOTH,
 778       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 2, .opc2 = 0,
 779       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c0_cssel),
 780       .writefn = csselr_write, .resetvalue = 0 },
 781     /* Auxiliary ID register: this actually has an IMPDEF value but for now
 782      * just RAZ for all cores:
 783      */
 784     { .name = "AIDR", .state = ARM_CP_STATE_BOTH,
 785       .opc0 = 3, .opc1 = 1, .crn = 0, .crm = 0, .opc2 = 7,
 786       .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
 787     /* Auxiliary fault status registers: these also are IMPDEF, and we
 788      * choose to RAZ/WI for all cores.
 789      */
 790     { .name = "AFSR0_EL1", .state = ARM_CP_STATE_BOTH,
 791       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 0,
 792       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 793     { .name = "AFSR1_EL1", .state = ARM_CP_STATE_BOTH,
 794       .opc0 = 3, .opc1 = 0, .crn = 5, .crm = 1, .opc2 = 1,
 795       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 796     /* MAIR can just read-as-written because we don't implement caches
 797      * and so don't need to care about memory attributes.
 798      */
 799     { .name = "MAIR_EL1", .state = ARM_CP_STATE_AA64,
 800       .opc0 = 3, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0,
 801       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.mair_el1),
 802       .resetvalue = 0 },
 803     /* For non-long-descriptor page tables these are PRRR and NMRR;
 804      * regardless they still act as reads-as-written for QEMU.
 805      * The override is necessary because of the overly-broad TLB_LOCKDOWN
 806      * definition.
 807      */
 808     { .name = "MAIR0", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
 809       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 0, .access = PL1_RW,
 810       .fieldoffset = offsetoflow32(CPUARMState, cp15.mair_el1),
 811       .resetfn = arm_cp_reset_ignore },
 812     { .name = "MAIR1", .state = ARM_CP_STATE_AA32, .type = ARM_CP_OVERRIDE,
 813       .cp = 15, .opc1 = 0, .crn = 10, .crm = 2, .opc2 = 1, .access = PL1_RW,
 814       .fieldoffset = offsetofhigh32(CPUARMState, cp15.mair_el1),
 815       .resetfn = arm_cp_reset_ignore },
 816     { .name = "ISR_EL1", .state = ARM_CP_STATE_BOTH,
 817       .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 1, .opc2 = 0,
 818       .type = ARM_CP_NO_MIGRATE, .access = PL1_R, .readfn = isr_read },
 819     REGINFO_SENTINEL
 820 };
 821
 822 static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
 823                         uint64_t value)
 824 {
 825     value &= 1;
 826     env->teecr = value;
 827 }
 828
 829 static CPAccessResult teehbr_access(CPUARMState *env, const ARMCPRegInfo *ri)
 830 {
 831     if (arm_current_pl(env) == 0 && (env->teecr & 1)) {
 832         return CP_ACCESS_TRAP;
 833     }
 834     return CP_ACCESS_OK;
 835 }
 836
 837 static const ARMCPRegInfo t2ee_cp_reginfo[] = {
 838     { .name = "TEECR", .cp = 14, .crn = 0, .crm = 0, .opc1 = 6, .opc2 = 0,
 839       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, teecr),
 840       .resetvalue = 0,
 841       .writefn = teecr_write },
 842     { .name = "TEEHBR", .cp = 14, .crn = 1, .crm = 0, .opc1 = 6, .opc2 = 0,
 843       .access = PL0_RW, .fieldoffset = offsetof(CPUARMState, teehbr),
 844       .accessfn = teehbr_access, .resetvalue = 0 },
 845     REGINFO_SENTINEL
 846 };
 847
 848 static const ARMCPRegInfo v6k_cp_reginfo[] = {
 849     { .name = "TPIDR_EL0", .state = ARM_CP_STATE_AA64,
 850       .opc0 = 3, .opc1 = 3, .opc2 = 2, .crn = 13, .crm = 0,
 851       .access = PL0_RW,
 852       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el0), .resetvalue = 0 },
 853     { .name = "TPIDRURW", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 2,
 854       .access = PL0_RW,
 855       .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidr_el0),
 856       .resetfn = arm_cp_reset_ignore },
 857     { .name = "TPIDRRO_EL0", .state = ARM_CP_STATE_AA64,
 858       .opc0 = 3, .opc1 = 3, .opc2 = 3, .crn = 13, .crm = 0,
 859       .access = PL0_R|PL1_W,
 860       .fieldoffset = offsetof(CPUARMState, cp15.tpidrro_el0), .resetvalue = 0 },
 861     { .name = "TPIDRURO", .cp = 15, .crn = 13, .crm = 0, .opc1 = 0, .opc2 = 3,
 862       .access = PL0_R|PL1_W,
 863       .fieldoffset = offsetoflow32(CPUARMState, cp15.tpidrro_el0),
 864       .resetfn = arm_cp_reset_ignore },
 865     { .name = "TPIDR_EL1", .state = ARM_CP_STATE_BOTH,
 866       .opc0 = 3, .opc1 = 0, .opc2 = 4, .crn = 13, .crm = 0,
 867       .access = PL1_RW,
 868       .fieldoffset = offsetof(CPUARMState, cp15.tpidr_el1), .resetvalue = 0 },
 869     REGINFO_SENTINEL
 870 };
 871
 872 #ifndef CONFIG_USER_ONLY
 873
 874 static CPAccessResult gt_cntfrq_access(CPUARMState *env, const ARMCPRegInfo *ri)
 875 {
 876     /* CNTFRQ: not visible from PL0 if both PL0PCTEN and PL0VCTEN are zero */
 877     if (arm_current_pl(env) == 0 && !extract32(env->cp15.c14_cntkctl, 0, 2)) {
 878         return CP_ACCESS_TRAP;
 879     }
 880     return CP_ACCESS_OK;
 881 }
 882
 883 static CPAccessResult gt_counter_access(CPUARMState *env, int timeridx)
 884 {
 885     /* CNT[PV]CT: not visible from PL0 if ELO[PV]CTEN is zero */
 886     if (arm_current_pl(env) == 0 &&
 887         !extract32(env->cp15.c14_cntkctl, timeridx, 1)) {
 888         return CP_ACCESS_TRAP;
 889     }
 890     return CP_ACCESS_OK;
 891 }
 892
 893 static CPAccessResult gt_timer_access(CPUARMState *env, int timeridx)
 894 {
 895     /* CNT[PV]_CVAL, CNT[PV]_CTL, CNT[PV]_TVAL: not visible from PL0 if
 896      * EL0[PV]TEN is zero.
 897      */
 898     if (arm_current_pl(env) == 0 &&
 899         !extract32(env->cp15.c14_cntkctl, 9 - timeridx, 1)) {
 900         return CP_ACCESS_TRAP;
 901     }
 902     return CP_ACCESS_OK;
 903 }
 904
 905 static CPAccessResult gt_pct_access(CPUARMState *env,
 906                                          const ARMCPRegInfo *ri)
 907 {
 908     return gt_counter_access(env, GTIMER_PHYS);
 909 }
 910
 911 static CPAccessResult gt_vct_access(CPUARMState *env,
 912                                          const ARMCPRegInfo *ri)
 913 {
 914     return gt_counter_access(env, GTIMER_VIRT);
 915 }
 916
 917 static CPAccessResult gt_ptimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
 918 {
 919     return gt_timer_access(env, GTIMER_PHYS);
 920 }
 921
 922 static CPAccessResult gt_vtimer_access(CPUARMState *env, const ARMCPRegInfo *ri)
 923 {
 924     return gt_timer_access(env, GTIMER_VIRT);
 925 }
 926
 927 static uint64_t gt_get_countervalue(CPUARMState *env)
 928 {
 929     return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / GTIMER_SCALE;
 930 }
 931
 932 static void gt_recalc_timer(ARMCPU *cpu, int timeridx)
 933 {
 934     ARMGenericTimer *gt = &cpu->env.cp15.c14_timer[timeridx];
 935
 936     if (gt->ctl & 1) {
 937         /* Timer enabled: calculate and set current ISTATUS, irq, and
 938          * reset timer to when ISTATUS next has to change
 939          */
 940         uint64_t count = gt_get_countervalue(&cpu->env);
 941         /* Note that this must be unsigned 64 bit arithmetic: */
 942         int istatus = count >= gt->cval;
 943         uint64_t nexttick;
 944
 945         gt->ctl = deposit32(gt->ctl, 2, 1, istatus);
 946         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
 947                      (istatus && !(gt->ctl & 2)));
 948         if (istatus) {
 949             /* Next transition is when count rolls back over to zero */
 950             nexttick = UINT64_MAX;
 951         } else {
 952             /* Next transition is when we hit cval */
 953             nexttick = gt->cval;
 954         }
 955         /* Note that the desired next expiry time might be beyond the
 956          * signed-64-bit range of a QEMUTimer -- in this case we just
 957          * set the timer for as far in the future as possible. When the
 958          * timer expires we will reset the timer for any remaining period.
 959          */
 960         if (nexttick > INT64_MAX / GTIMER_SCALE) {
 961             nexttick = INT64_MAX / GTIMER_SCALE;
 962         }
 963         timer_mod(cpu->gt_timer[timeridx], nexttick);
 964     } else {
 965         /* Timer disabled: ISTATUS and timer output always clear */
 966         gt->ctl &= ~4;
 967         qemu_set_irq(cpu->gt_timer_outputs[timeridx], 0);
 968         timer_del(cpu->gt_timer[timeridx]);
 969     }
 970 }
 971
 972 static void gt_cnt_reset(CPUARMState *env, const ARMCPRegInfo *ri)
 973 {
 974     ARMCPU *cpu = arm_env_get_cpu(env);
 975     int timeridx = ri->opc1 & 1;
 976
 977     timer_del(cpu->gt_timer[timeridx]);
 978 }
 979
 980 static uint64_t gt_cnt_read(CPUARMState *env, const ARMCPRegInfo *ri)
 981 {
 982     return gt_get_countervalue(env);
 983 }
 984
 985 static void gt_cval_write(CPUARMState *env, const ARMCPRegInfo *ri,
 986                           uint64_t value)
 987 {
 988     int timeridx = ri->opc1 & 1;
 989
 990     env->cp15.c14_timer[timeridx].cval = value;
 991     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
 992 }
 993
 994 static uint64_t gt_tval_read(CPUARMState *env, const ARMCPRegInfo *ri)
 995 {
 996     int timeridx = ri->crm & 1;
 997
 998     return (uint32_t)(env->cp15.c14_timer[timeridx].cval -
 999                       gt_get_countervalue(env));
1000 }
1001
1002 static void gt_tval_write(CPUARMState *env, const ARMCPRegInfo *ri,
1003                           uint64_t value)
1004 {
1005     int timeridx = ri->crm & 1;
1006
1007     env->cp15.c14_timer[timeridx].cval = gt_get_countervalue(env) +
1008         + sextract64(value, 0, 32);
1009     gt_recalc_timer(arm_env_get_cpu(env), timeridx);
1010 }
1011
1012 static void gt_ctl_write(CPUARMState *env, const ARMCPRegInfo *ri,
1013                          uint64_t value)
1014 {
1015     ARMCPU *cpu = arm_env_get_cpu(env);
1016     int timeridx = ri->crm & 1;
1017     uint32_t oldval = env->cp15.c14_timer[timeridx].ctl;
1018
1019     env->cp15.c14_timer[timeridx].ctl = value & 3;
1020     if ((oldval ^ value) & 1) {
1021         /* Enable toggled */
1022         gt_recalc_timer(cpu, timeridx);
1023     } else if ((oldval & value) & 2) {
1024         /* IMASK toggled: don't need to recalculate,
1025          * just set the interrupt line based on ISTATUS
1026          */
1027         qemu_set_irq(cpu->gt_timer_outputs[timeridx],
1028                      (oldval & 4) && (value & 2));
1029     }
1030 }
1031
1032 void arm_gt_ptimer_cb(void *opaque)
1033 {
1034     ARMCPU *cpu = opaque;
1035
1036     gt_recalc_timer(cpu, GTIMER_PHYS);
1037 }
1038
1039 void arm_gt_vtimer_cb(void *opaque)
1040 {
1041     ARMCPU *cpu = opaque;
1042
1043     gt_recalc_timer(cpu, GTIMER_VIRT);
1044 }
1045
1046 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1047     /* Note that CNTFRQ is purely reads-as-written for the benefit
1048      * of software; writing it doesn't actually change the timer frequency.
1049      * Our reset value matches the fixed frequency we implement the timer at.
1050      */
1051     { .name = "CNTFRQ", .cp = 15, .crn = 14, .crm = 0, .opc1 = 0, .opc2 = 0,
1052       .type = ARM_CP_NO_MIGRATE,
1053       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1054       .fieldoffset = offsetoflow32(CPUARMState, cp15.c14_cntfrq),
1055       .resetfn = arm_cp_reset_ignore,
1056     },
1057     { .name = "CNTFRQ_EL0", .state = ARM_CP_STATE_AA64,
1058       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 0,
1059       .access = PL1_RW | PL0_R, .accessfn = gt_cntfrq_access,
1060       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntfrq),
1061       .resetvalue = (1000 * 1000 * 1000) / GTIMER_SCALE,
1062     },
1063     /* overall control: mostly access permissions */
1064     { .name = "CNTKCTL", .state = ARM_CP_STATE_BOTH,
1065       .opc0 = 3, .opc1 = 0, .crn = 14, .crm = 1, .opc2 = 0,
1066       .access = PL1_RW,
1067       .fieldoffset = offsetof(CPUARMState, cp15.c14_cntkctl),
1068       .resetvalue = 0,
1069     },
1070     /* per-timer control */
1071     { .name = "CNTP_CTL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 1,
1072       .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1073       .accessfn = gt_ptimer_access,
1074       .fieldoffset = offsetoflow32(CPUARMState,
1075                                    cp15.c14_timer[GTIMER_PHYS].ctl),
1076       .resetfn = arm_cp_reset_ignore,
1077       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1078     },
1079     { .name = "CNTP_CTL_EL0", .state = ARM_CP_STATE_AA64,
1080       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 1,
1081       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1082       .accessfn = gt_ptimer_access,
1083       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].ctl),
1084       .resetvalue = 0,
1085       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1086     },
1087     { .name = "CNTV_CTL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 1,
1088       .type = ARM_CP_IO | ARM_CP_NO_MIGRATE, .access = PL1_RW | PL0_R,
1089       .accessfn = gt_vtimer_access,
1090       .fieldoffset = offsetoflow32(CPUARMState,
1091                                    cp15.c14_timer[GTIMER_VIRT].ctl),
1092       .resetfn = arm_cp_reset_ignore,
1093       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1094     },
1095     { .name = "CNTV_CTL_EL0", .state = ARM_CP_STATE_AA64,
1096       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 1,
1097       .type = ARM_CP_IO, .access = PL1_RW | PL0_R,
1098       .accessfn = gt_vtimer_access,
1099       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].ctl),
1100       .resetvalue = 0,
1101       .writefn = gt_ctl_write, .raw_writefn = raw_write,
1102     },
1103     /* TimerValue views: a 32 bit downcounting view of the underlying state */
1104     { .name = "CNTP_TVAL", .cp = 15, .crn = 14, .crm = 2, .opc1 = 0, .opc2 = 0,
1105       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1106       .accessfn = gt_ptimer_access,
1107       .readfn = gt_tval_read, .writefn = gt_tval_write,
1108     },
1109     { .name = "CNTP_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1110       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 0,
1111       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1112       .readfn = gt_tval_read, .writefn = gt_tval_write,
1113     },
1114     { .name = "CNTV_TVAL", .cp = 15, .crn = 14, .crm = 3, .opc1 = 0, .opc2 = 0,
1115       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1116       .accessfn = gt_vtimer_access,
1117       .readfn = gt_tval_read, .writefn = gt_tval_write,
1118     },
1119     { .name = "CNTV_TVAL_EL0", .state = ARM_CP_STATE_AA64,
1120       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 0,
1121       .type = ARM_CP_NO_MIGRATE | ARM_CP_IO, .access = PL1_RW | PL0_R,
1122       .readfn = gt_tval_read, .writefn = gt_tval_write,
1123     },
1124     /* The counter itself */
1125     { .name = "CNTPCT", .cp = 15, .crm = 14, .opc1 = 0,
1126       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1127       .accessfn = gt_pct_access,
1128       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1129     },
1130     { .name = "CNTPCT_EL0", .state = ARM_CP_STATE_AA64,
1131       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 1,
1132       .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1133       .accessfn = gt_pct_access,
1134       .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1135     },
1136     { .name = "CNTVCT", .cp = 15, .crm = 14, .opc1 = 1,
1137       .access = PL0_R, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE | ARM_CP_IO,
1138       .accessfn = gt_vct_access,
1139       .readfn = gt_cnt_read, .resetfn = arm_cp_reset_ignore,
1140     },
1141     { .name = "CNTVCT_EL0", .state = ARM_CP_STATE_AA64,
1142       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 0, .opc2 = 2,
1143       .access = PL0_R, .type = ARM_CP_NO_MIGRATE | ARM_CP_IO,
1144       .accessfn = gt_vct_access,
1145       .readfn = gt_cnt_read, .resetfn = gt_cnt_reset,
1146     },
1147     /* Comparison value, indicating when the timer goes off */
1148     { .name = "CNTP_CVAL", .cp = 15, .crm = 14, .opc1 = 2,
1149       .access = PL1_RW | PL0_R,
1150       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1151       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1152       .accessfn = gt_ptimer_access, .resetfn = arm_cp_reset_ignore,
1153       .writefn = gt_cval_write, .raw_writefn = raw_write,
1154     },
1155     { .name = "CNTP_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1156       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 2, .opc2 = 2,
1157       .access = PL1_RW | PL0_R,
1158       .type = ARM_CP_IO,
1159       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_PHYS].cval),
1160       .resetvalue = 0, .accessfn = gt_vtimer_access,
1161       .writefn = gt_cval_write, .raw_writefn = raw_write,
1162     },
1163     { .name = "CNTV_CVAL", .cp = 15, .crm = 14, .opc1 = 3,
1164       .access = PL1_RW | PL0_R,
1165       .type = ARM_CP_64BIT | ARM_CP_IO | ARM_CP_NO_MIGRATE,
1166       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1167       .accessfn = gt_vtimer_access, .resetfn = arm_cp_reset_ignore,
1168       .writefn = gt_cval_write, .raw_writefn = raw_write,
1169     },
1170     { .name = "CNTV_CVAL_EL0", .state = ARM_CP_STATE_AA64,
1171       .opc0 = 3, .opc1 = 3, .crn = 14, .crm = 3, .opc2 = 2,
1172       .access = PL1_RW | PL0_R,
1173       .type = ARM_CP_IO,
1174       .fieldoffset = offsetof(CPUARMState, cp15.c14_timer[GTIMER_VIRT].cval),
1175       .resetvalue = 0, .accessfn = gt_vtimer_access,
1176       .writefn = gt_cval_write, .raw_writefn = raw_write,
1177     },
1178     REGINFO_SENTINEL
1179 };
1180
1181 #else
1182 /* In user-mode none of the generic timer registers are accessible,
1183  * and their implementation depends on QEMU_CLOCK_VIRTUAL and qdev gpio outputs,
1184  * so instead just don't register any of them.
1185  */
1186 static const ARMCPRegInfo generic_timer_cp_reginfo[] = {
1187     REGINFO_SENTINEL
1188 };
1189
1190 #endif
1191
1192 static void par_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1193 {
1194     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1195         env->cp15.par_el1 = value;
1196     } else if (arm_feature(env, ARM_FEATURE_V7)) {
1197         env->cp15.par_el1 = value & 0xfffff6ff;
1198     } else {
1199         env->cp15.par_el1 = value & 0xfffff1ff;
1200     }
1201 }
1202
1203 #ifndef CONFIG_USER_ONLY
1204 /* get_phys_addr() isn't present for user-mode-only targets */
1205
1206 static CPAccessResult ats_access(CPUARMState *env, const ARMCPRegInfo *ri)
1207 {
1208     if (ri->opc2 & 4) {
1209         /* Other states are only available with TrustZone; in
1210          * a non-TZ implementation these registers don't exist
1211          * at all, which is an Uncategorized trap. This underdecoding
1212          * is safe because the reginfo is NO_MIGRATE.
1213          */
1214         return CP_ACCESS_TRAP_UNCATEGORIZED;
1215     }
1216     return CP_ACCESS_OK;
1217 }
1218
1219 static void ats_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
1220 {
1221     hwaddr phys_addr;
1222     target_ulong page_size;
1223     int prot;
1224     int ret, is_user = ri->opc2 & 2;
1225     int access_type = ri->opc2 & 1;
1226
1227     ret = get_phys_addr(env, value, access_type, is_user,
1228                         &phys_addr, &prot, &page_size);
1229     if (extended_addresses_enabled(env)) {
1230         /* ret is a DFSR/IFSR value for the long descriptor
1231          * translation table format, but with WnR always clear.
1232          * Convert it to a 64-bit PAR.
1233          */
1234         uint64_t par64 = (1 << 11); /* LPAE bit always set */
1235         if (ret == 0) {
1236             par64 |= phys_addr & ~0xfffULL;
1237             /* We don't set the ATTR or SH fields in the PAR. */
1238         } else {
1239             par64 |= 1; /* F */
1240             par64 |= (ret & 0x3f) << 1; /* FS */
1241             /* Note that S2WLK and FSTAGE are always zero, because we don't
1242              * implement virtualization and therefore there can't be a stage 2
1243              * fault.
1244              */
1245         }
1246         env->cp15.par_el1 = par64;
1247     } else {
1248         /* ret is a DFSR/IFSR value for the short descriptor
1249          * translation table format (with WnR always clear).
1250          * Convert it to a 32-bit PAR.
1251          */
1252         if (ret == 0) {
1253             /* We do not set any attribute bits in the PAR */
1254             if (page_size == (1 << 24)
1255                 && arm_feature(env, ARM_FEATURE_V7)) {
1256                 env->cp15.par_el1 = (phys_addr & 0xff000000) | 1 << 1;
1257             } else {
1258                 env->cp15.par_el1 = phys_addr & 0xfffff000;
1259             }
1260         } else {
1261             env->cp15.par_el1 = ((ret & (1 << 10)) >> 5) |
1262                 ((ret & (1 << 12)) >> 6) |
1263                 ((ret & 0xf) << 1) | 1;
1264         }
1265     }
1266 }
1267 #endif
1268
1269 static const ARMCPRegInfo vapa_cp_reginfo[] = {
1270     { .name = "PAR", .cp = 15, .crn = 7, .crm = 4, .opc1 = 0, .opc2 = 0,
1271       .access = PL1_RW, .resetvalue = 0,
1272       .fieldoffset = offsetoflow32(CPUARMState, cp15.par_el1),
1273       .writefn = par_write },
1274 #ifndef CONFIG_USER_ONLY
1275     { .name = "ATS", .cp = 15, .crn = 7, .crm = 8, .opc1 = 0, .opc2 = CP_ANY,
1276       .access = PL1_W, .accessfn = ats_access,
1277       .writefn = ats_write, .type = ARM_CP_NO_MIGRATE },
1278 #endif
1279     REGINFO_SENTINEL
1280 };
1281
1282 /* Return basic MPU access permission bits.  */
1283 static uint32_t simple_mpu_ap_bits(uint32_t val)
1284 {
1285     uint32_t ret;
1286     uint32_t mask;
1287     int i;
1288     ret = 0;
1289     mask = 3;
1290     for (i = 0; i < 16; i += 2) {
1291         ret |= (val >> i) & mask;
1292         mask <<= 2;
1293     }
1294     return ret;
1295 }
1296
1297 /* Pad basic MPU access permission bits to extended format.  */
1298 static uint32_t extended_mpu_ap_bits(uint32_t val)
1299 {
1300     uint32_t ret;
1301     uint32_t mask;
1302     int i;
1303     ret = 0;
1304     mask = 3;
1305     for (i = 0; i < 16; i += 2) {
1306         ret |= (val & mask) << i;
1307         mask <<= 2;
1308     }
1309     return ret;
1310 }
1311
1312 static void pmsav5_data_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1313                                  uint64_t value)
1314 {
1315     env->cp15.pmsav5_data_ap = extended_mpu_ap_bits(value);
1316 }
1317
1318 static uint64_t pmsav5_data_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1319 {
1320     return simple_mpu_ap_bits(env->cp15.pmsav5_data_ap);
1321 }
1322
1323 static void pmsav5_insn_ap_write(CPUARMState *env, const ARMCPRegInfo *ri,
1324                                  uint64_t value)
1325 {
1326     env->cp15.pmsav5_insn_ap = extended_mpu_ap_bits(value);
1327 }
1328
1329 static uint64_t pmsav5_insn_ap_read(CPUARMState *env, const ARMCPRegInfo *ri)
1330 {
1331     return simple_mpu_ap_bits(env->cp15.pmsav5_insn_ap);
1332 }
1333
1334 static const ARMCPRegInfo pmsav5_cp_reginfo[] = {
1335     { .name = "DATA_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1336       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1337       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1338       .resetvalue = 0,
1339       .readfn = pmsav5_data_ap_read, .writefn = pmsav5_data_ap_write, },
1340     { .name = "INSN_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1341       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1342       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1343       .resetvalue = 0,
1344       .readfn = pmsav5_insn_ap_read, .writefn = pmsav5_insn_ap_write, },
1345     { .name = "DATA_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 2,
1346       .access = PL1_RW,
1347       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_data_ap),
1348       .resetvalue = 0, },
1349     { .name = "INSN_EXT_AP", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 3,
1350       .access = PL1_RW,
1351       .fieldoffset = offsetof(CPUARMState, cp15.pmsav5_insn_ap),
1352       .resetvalue = 0, },
1353     { .name = "DCACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1354       .access = PL1_RW,
1355       .fieldoffset = offsetof(CPUARMState, cp15.c2_data), .resetvalue = 0, },
1356     { .name = "ICACHE_CFG", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1357       .access = PL1_RW,
1358       .fieldoffset = offsetof(CPUARMState, cp15.c2_insn), .resetvalue = 0, },
1359     /* Protection region base and size registers */
1360     { .name = "946_PRBS0", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
1361       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1362       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[0]) },
1363     { .name = "946_PRBS1", .cp = 15, .crn = 6, .crm = 1, .opc1 = 0,
1364       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1365       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[1]) },
1366     { .name = "946_PRBS2", .cp = 15, .crn = 6, .crm = 2, .opc1 = 0,
1367       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1368       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[2]) },
1369     { .name = "946_PRBS3", .cp = 15, .crn = 6, .crm = 3, .opc1 = 0,
1370       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1371       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[3]) },
1372     { .name = "946_PRBS4", .cp = 15, .crn = 6, .crm = 4, .opc1 = 0,
1373       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1374       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[4]) },
1375     { .name = "946_PRBS5", .cp = 15, .crn = 6, .crm = 5, .opc1 = 0,
1376       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1377       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[5]) },
1378     { .name = "946_PRBS6", .cp = 15, .crn = 6, .crm = 6, .opc1 = 0,
1379       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1380       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[6]) },
1381     { .name = "946_PRBS7", .cp = 15, .crn = 6, .crm = 7, .opc1 = 0,
1382       .opc2 = CP_ANY, .access = PL1_RW, .resetvalue = 0,
1383       .fieldoffset = offsetof(CPUARMState, cp15.c6_region[7]) },
1384     REGINFO_SENTINEL
1385 };
1386
1387 static void vmsa_ttbcr_raw_write(CPUARMState *env, const ARMCPRegInfo *ri,
1388                                  uint64_t value)
1389 {
1390     int maskshift = extract32(value, 0, 3);
1391
1392     if (arm_feature(env, ARM_FEATURE_LPAE) && (value & (1 << 31))) {
1393         value &= ~((7 << 19) | (3 << 14) | (0xf << 3));
1394     } else {
1395         value &= 7;
1396     }
1397     /* Note that we always calculate c2_mask and c2_base_mask, but
1398      * they are only used for short-descriptor tables (ie if EAE is 0);
1399      * for long-descriptor tables the TTBCR fields are used differently
1400      * and the c2_mask and c2_base_mask values are meaningless.
1401      */
1402     env->cp15.c2_control = value;
1403     env->cp15.c2_mask = ~(((uint32_t)0xffffffffu) >> maskshift);
1404     env->cp15.c2_base_mask = ~((uint32_t)0x3fffu >> maskshift);
1405 }
1406
1407 static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1408                              uint64_t value)
1409 {
1410     ARMCPU *cpu = arm_env_get_cpu(env);
1411
1412     if (arm_feature(env, ARM_FEATURE_LPAE)) {
1413         /* With LPAE the TTBCR could result in a change of ASID
1414          * via the TTBCR.A1 bit, so do a TLB flush.
1415          */
1416         tlb_flush(CPU(cpu), 1);
1417     }
1418     vmsa_ttbcr_raw_write(env, ri, value);
1419 }
1420
1421 static void vmsa_ttbcr_reset(CPUARMState *env, const ARMCPRegInfo *ri)
1422 {
1423     env->cp15.c2_base_mask = 0xffffc000u;
1424     env->cp15.c2_control = 0;
1425     env->cp15.c2_mask = 0;
1426 }
1427
1428 static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
1429                                uint64_t value)
1430 {
1431     ARMCPU *cpu = arm_env_get_cpu(env);
1432
1433     /* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
1434     tlb_flush(CPU(cpu), 1);
1435     env->cp15.c2_control = value;
1436 }
1437
1438 static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1439                             uint64_t value)
1440 {
1441     /* 64 bit accesses to the TTBRs can change the ASID and so we
1442      * must flush the TLB.
1443      */
1444     if (cpreg_field_is_64bit(ri)) {
1445         ARMCPU *cpu = arm_env_get_cpu(env);
1446
1447         tlb_flush(CPU(cpu), 1);
1448     }
1449     raw_write(env, ri, value);
1450 }
1451
1452 static const ARMCPRegInfo vmsa_cp_reginfo[] = {
1453     { .name = "DFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 0,
1454       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE,
1455       .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el1),
1456       .resetfn = arm_cp_reset_ignore, },
1457     { .name = "IFSR", .cp = 15, .crn = 5, .crm = 0, .opc1 = 0, .opc2 = 1,
1458       .access = PL1_RW,
1459       .fieldoffset = offsetof(CPUARMState, cp15.ifsr_el2), .resetvalue = 0, },
1460     { .name = "ESR_EL1", .state = ARM_CP_STATE_AA64,
1461       .opc0 = 3, .crn = 5, .crm = 2, .opc1 = 0, .opc2 = 0,
1462       .access = PL1_RW,
1463       .fieldoffset = offsetof(CPUARMState, cp15.esr_el1), .resetvalue = 0, },
1464     { .name = "TTBR0_EL1", .state = ARM_CP_STATE_BOTH,
1465       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 0,
1466       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1467       .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1468     { .name = "TTBR1_EL1", .state = ARM_CP_STATE_BOTH,
1469       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 1,
1470       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1471       .writefn = vmsa_ttbr_write, .resetvalue = 0 },
1472     { .name = "TCR_EL1", .state = ARM_CP_STATE_AA64,
1473       .opc0 = 3, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1474       .access = PL1_RW, .writefn = vmsa_tcr_el1_write,
1475       .resetfn = vmsa_ttbcr_reset, .raw_writefn = raw_write,
1476       .fieldoffset = offsetof(CPUARMState, cp15.c2_control) },
1477     { .name = "TTBCR", .cp = 15, .crn = 2, .crm = 0, .opc1 = 0, .opc2 = 2,
1478       .access = PL1_RW, .type = ARM_CP_NO_MIGRATE, .writefn = vmsa_ttbcr_write,
1479       .resetfn = arm_cp_reset_ignore, .raw_writefn = vmsa_ttbcr_raw_write,
1480       .fieldoffset = offsetoflow32(CPUARMState, cp15.c2_control) },
1481     /* 64-bit FAR; this entry also gives us the AArch32 DFAR */
1482     { .name = "FAR_EL1", .state = ARM_CP_STATE_BOTH,
1483       .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
1484       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.far_el1),
1485       .resetvalue = 0, },
1486     REGINFO_SENTINEL
1487 };
1488
1489 static void omap_ticonfig_write(CPUARMState *env, const ARMCPRegInfo *ri,
1490                                 uint64_t value)
1491 {
1492     env->cp15.c15_ticonfig = value & 0xe7;
1493     /* The OS_TYPE bit in this register changes the reported CPUID! */
1494     env->cp15.c0_cpuid = (value & (1 << 5)) ?
1495         ARM_CPUID_TI915T : ARM_CPUID_TI925T;
1496 }
1497
1498 static void omap_threadid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1499                                 uint64_t value)
1500 {
1501     env->cp15.c15_threadid = value & 0xffff;
1502 }
1503
1504 static void omap_wfi_write(CPUARMState *env, const ARMCPRegInfo *ri,
1505                            uint64_t value)
1506 {
1507     /* Wait-for-interrupt (deprecated) */
1508     cpu_interrupt(CPU(arm_env_get_cpu(env)), CPU_INTERRUPT_HALT);
1509 }
1510
1511 static void omap_cachemaint_write(CPUARMState *env, const ARMCPRegInfo *ri,
1512                                   uint64_t value)
1513 {
1514     /* On OMAP there are registers indicating the max/min index of dcache lines
1515      * containing a dirty line; cache flush operations have to reset these.
1516      */
1517     env->cp15.c15_i_max = 0x000;
1518     env->cp15.c15_i_min = 0xff0;
1519 }
1520
1521 static const ARMCPRegInfo omap_cp_reginfo[] = {
1522     { .name = "DFSR", .cp = 15, .crn = 5, .crm = CP_ANY,
1523       .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW, .type = ARM_CP_OVERRIDE,
1524       .fieldoffset = offsetoflow32(CPUARMState, cp15.esr_el1),
1525       .resetvalue = 0, },
1526     { .name = "", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
1527       .access = PL1_RW, .type = ARM_CP_NOP },
1528     { .name = "TICONFIG", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
1529       .access = PL1_RW,
1530       .fieldoffset = offsetof(CPUARMState, cp15.c15_ticonfig), .resetvalue = 0,
1531       .writefn = omap_ticonfig_write },
1532     { .name = "IMAX", .cp = 15, .crn = 15, .crm = 2, .opc1 = 0, .opc2 = 0,
1533       .access = PL1_RW,
1534       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_max), .resetvalue = 0, },
1535     { .name = "IMIN", .cp = 15, .crn = 15, .crm = 3, .opc1 = 0, .opc2 = 0,
1536       .access = PL1_RW, .resetvalue = 0xff0,
1537       .fieldoffset = offsetof(CPUARMState, cp15.c15_i_min) },
1538     { .name = "THREADID", .cp = 15, .crn = 15, .crm = 4, .opc1 = 0, .opc2 = 0,
1539       .access = PL1_RW,
1540       .fieldoffset = offsetof(CPUARMState, cp15.c15_threadid), .resetvalue = 0,
1541       .writefn = omap_threadid_write },
1542     { .name = "TI925T_STATUS", .cp = 15, .crn = 15,
1543       .crm = 8, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1544       .type = ARM_CP_NO_MIGRATE,
1545       .readfn = arm_cp_read_zero, .writefn = omap_wfi_write, },
1546     /* TODO: Peripheral port remap register:
1547      * On OMAP2 mcr p15, 0, rn, c15, c2, 4 sets up the interrupt controller
1548      * base address at $rn & ~0xfff and map size of 0x200 << ($rn & 0xfff),
1549      * when MMU is off.
1550      */
1551     { .name = "OMAP_CACHEMAINT", .cp = 15, .crn = 7, .crm = CP_ANY,
1552       .opc1 = 0, .opc2 = CP_ANY, .access = PL1_W,
1553       .type = ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE,
1554       .writefn = omap_cachemaint_write },
1555     { .name = "C9", .cp = 15, .crn = 9,
1556       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_RW,
1557       .type = ARM_CP_CONST | ARM_CP_OVERRIDE, .resetvalue = 0 },
1558     REGINFO_SENTINEL
1559 };
1560
1561 static void xscale_cpar_write(CPUARMState *env, const ARMCPRegInfo *ri,
1562                               uint64_t value)
1563 {
1564     value &= 0x3fff;
1565     if (env->cp15.c15_cpar != value) {
1566         /* Changes cp0 to cp13 behavior, so needs a TB flush.  */
1567         tb_flush(env);
1568         env->cp15.c15_cpar = value;
1569     }
1570 }
1571
1572 static const ARMCPRegInfo xscale_cp_reginfo[] = {
1573     { .name = "XSCALE_CPAR",
1574       .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0, .access = PL1_RW,
1575       .fieldoffset = offsetof(CPUARMState, cp15.c15_cpar), .resetvalue = 0,
1576       .writefn = xscale_cpar_write, },
1577     { .name = "XSCALE_AUXCR",
1578       .cp = 15, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 1, .access = PL1_RW,
1579       .fieldoffset = offsetof(CPUARMState, cp15.c1_xscaleauxcr),
1580       .resetvalue = 0, },
1581     /* XScale specific cache-lockdown: since we have no cache we NOP these
1582      * and hope the guest does not really rely on cache behaviour.
1583      */
1584     { .name = "XSCALE_LOCK_ICACHE_LINE",
1585       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
1586       .access = PL1_W, .type = ARM_CP_NOP },
1587     { .name = "XSCALE_UNLOCK_ICACHE",
1588       .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
1589       .access = PL1_W, .type = ARM_CP_NOP },
1590     { .name = "XSCALE_DCACHE_LOCK",
1591       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 0,
1592       .access = PL1_RW, .type = ARM_CP_NOP },
1593     { .name = "XSCALE_UNLOCK_DCACHE",
1594       .cp = 15, .opc1 = 0, .crn = 9, .crm = 2, .opc2 = 1,
1595       .access = PL1_W, .type = ARM_CP_NOP },
1596     REGINFO_SENTINEL
1597 };
1598
1599 static const ARMCPRegInfo dummy_c15_cp_reginfo[] = {
1600     /* RAZ/WI the whole crn=15 space, when we don't have a more specific
1601      * implementation of this implementation-defined space.
1602      * Ideally this should eventually disappear in favour of actually
1603      * implementing the correct behaviour for all cores.
1604      */
1605     { .name = "C15_IMPDEF", .cp = 15, .crn = 15,
1606       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1607       .access = PL1_RW,
1608       .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE | ARM_CP_OVERRIDE,
1609       .resetvalue = 0 },
1610     REGINFO_SENTINEL
1611 };
1612
1613 static const ARMCPRegInfo cache_dirty_status_cp_reginfo[] = {
1614     /* Cache status: RAZ because we have no cache so it's always clean */
1615     { .name = "CDSR", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 6,
1616       .access = PL1_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1617       .resetvalue = 0 },
1618     REGINFO_SENTINEL
1619 };
1620
1621 static const ARMCPRegInfo cache_block_ops_cp_reginfo[] = {
1622     /* We never have a a block transfer operation in progress */
1623     { .name = "BXSR", .cp = 15, .crn = 7, .crm = 12, .opc1 = 0, .opc2 = 4,
1624       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1625       .resetvalue = 0 },
1626     /* The cache ops themselves: these all NOP for QEMU */
1627     { .name = "IICR", .cp = 15, .crm = 5, .opc1 = 0,
1628       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1629     { .name = "IDCR", .cp = 15, .crm = 6, .opc1 = 0,
1630       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1631     { .name = "CDCR", .cp = 15, .crm = 12, .opc1 = 0,
1632       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1633     { .name = "PIR", .cp = 15, .crm = 12, .opc1 = 1,
1634       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1635     { .name = "PDR", .cp = 15, .crm = 12, .opc1 = 2,
1636       .access = PL0_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1637     { .name = "CIDCR", .cp = 15, .crm = 14, .opc1 = 0,
1638       .access = PL1_W, .type = ARM_CP_NOP|ARM_CP_64BIT },
1639     REGINFO_SENTINEL
1640 };
1641
1642 static const ARMCPRegInfo cache_test_clean_cp_reginfo[] = {
1643     /* The cache test-and-clean instructions always return (1 << 30)
1644      * to indicate that there are no dirty cache lines.
1645      */
1646     { .name = "TC_DCACHE", .cp = 15, .crn = 7, .crm = 10, .opc1 = 0, .opc2 = 3,
1647       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1648       .resetvalue = (1 << 30) },
1649     { .name = "TCI_DCACHE", .cp = 15, .crn = 7, .crm = 14, .opc1 = 0, .opc2 = 3,
1650       .access = PL0_R, .type = ARM_CP_CONST | ARM_CP_NO_MIGRATE,
1651       .resetvalue = (1 << 30) },
1652     REGINFO_SENTINEL
1653 };
1654
1655 static const ARMCPRegInfo strongarm_cp_reginfo[] = {
1656     /* Ignore ReadBuffer accesses */
1657     { .name = "C9_READBUFFER", .cp = 15, .crn = 9,
1658       .crm = CP_ANY, .opc1 = CP_ANY, .opc2 = CP_ANY,
1659       .access = PL1_RW, .resetvalue = 0,
1660       .type = ARM_CP_CONST | ARM_CP_OVERRIDE | ARM_CP_NO_MIGRATE },
1661     REGINFO_SENTINEL
1662 };
1663
1664 static uint64_t mpidr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1665 {
1666     CPUState *cs = CPU(arm_env_get_cpu(env));
1667     uint32_t mpidr = cs->cpu_index;
1668     /* We don't support setting cluster ID ([8..11]) (known as Aff1
1669      * in later ARM ARM versions), or any of the higher affinity level fields,
1670      * so these bits always RAZ.
1671      */
1672     if (arm_feature(env, ARM_FEATURE_V7MP)) {
1673         mpidr |= (1U << 31);
1674         /* Cores which are uniprocessor (non-coherent)
1675          * but still implement the MP extensions set
1676          * bit 30. (For instance, A9UP.) However we do
1677          * not currently model any of those cores.
1678          */
1679     }
1680     return mpidr;
1681 }
1682
1683 static const ARMCPRegInfo mpidr_cp_reginfo[] = {
1684     { .name = "MPIDR", .state = ARM_CP_STATE_BOTH,
1685       .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 5,
1686       .access = PL1_R, .readfn = mpidr_read, .type = ARM_CP_NO_MIGRATE },
1687     REGINFO_SENTINEL
1688 };
1689
1690 static const ARMCPRegInfo lpae_cp_reginfo[] = {
1691     /* NOP AMAIR0/1: the override is because these clash with the rather
1692      * broadly specified TLB_LOCKDOWN entry in the generic cp_reginfo.
1693      */
1694     { .name = "AMAIR0", .state = ARM_CP_STATE_BOTH,
1695       .opc0 = 3, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 0,
1696       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1697       .resetvalue = 0 },
1698     /* AMAIR1 is mapped to AMAIR_EL1[63:32] */
1699     { .name = "AMAIR1", .cp = 15, .crn = 10, .crm = 3, .opc1 = 0, .opc2 = 1,
1700       .access = PL1_RW, .type = ARM_CP_CONST | ARM_CP_OVERRIDE,
1701       .resetvalue = 0 },
1702     /* 64 bit access versions of the (dummy) debug registers */
1703     { .name = "DBGDRAR", .cp = 14, .crm = 1, .opc1 = 0,
1704       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1705     { .name = "DBGDSAR", .cp = 14, .crm = 2, .opc1 = 0,
1706       .access = PL0_R, .type = ARM_CP_CONST|ARM_CP_64BIT, .resetvalue = 0 },
1707     { .name = "PAR", .cp = 15, .crm = 7, .opc1 = 0,
1708       .access = PL1_RW, .type = ARM_CP_64BIT,
1709       .fieldoffset = offsetof(CPUARMState, cp15.par_el1), .resetvalue = 0 },
1710     { .name = "TTBR0", .cp = 15, .crm = 2, .opc1 = 0,
1711       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1712       .fieldoffset = offsetof(CPUARMState, cp15.ttbr0_el1),
1713       .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1714     { .name = "TTBR1", .cp = 15, .crm = 2, .opc1 = 1,
1715       .access = PL1_RW, .type = ARM_CP_64BIT | ARM_CP_NO_MIGRATE,
1716       .fieldoffset = offsetof(CPUARMState, cp15.ttbr1_el1),
1717       .writefn = vmsa_ttbr_write, .resetfn = arm_cp_reset_ignore },
1718     REGINFO_SENTINEL
1719 };
1720
1721 static uint64_t aa64_fpcr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1722 {
1723     return vfp_get_fpcr(env);
1724 }
1725
1726 static void aa64_fpcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1727                             uint64_t value)
1728 {
1729     vfp_set_fpcr(env, value);
1730 }
1731
1732 static uint64_t aa64_fpsr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1733 {
1734     return vfp_get_fpsr(env);
1735 }
1736
1737 static void aa64_fpsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
1738                             uint64_t value)
1739 {
1740     vfp_set_fpsr(env, value);
1741 }
1742
1743 static CPAccessResult aa64_daif_access(CPUARMState *env, const ARMCPRegInfo *ri)
1744 {
1745     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UMA)) {
1746         return CP_ACCESS_TRAP;
1747     }
1748     return CP_ACCESS_OK;
1749 }
1750
1751 static void aa64_daif_write(CPUARMState *env, const ARMCPRegInfo *ri,
1752                             uint64_t value)
1753 {
1754     env->daif = value & PSTATE_DAIF;
1755 }
1756
1757 static CPAccessResult aa64_cacheop_access(CPUARMState *env,
1758                                           const ARMCPRegInfo *ri)
1759 {
1760     /* Cache invalidate/clean: NOP, but EL0 must UNDEF unless
1761      * SCTLR_EL1.UCI is set.
1762      */
1763     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCI)) {
1764         return CP_ACCESS_TRAP;
1765     }
1766     return CP_ACCESS_OK;
1767 }
1768
1769 static void tlbi_aa64_va_write(CPUARMState *env, const ARMCPRegInfo *ri,
1770                                uint64_t value)
1771 {
1772     /* Invalidate by VA (AArch64 version) */
1773     ARMCPU *cpu = arm_env_get_cpu(env);
1774     uint64_t pageaddr = value << 12;
1775     tlb_flush_page(CPU(cpu), pageaddr);
1776 }
1777
1778 static void tlbi_aa64_vaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
1779                                 uint64_t value)
1780 {
1781     /* Invalidate by VA, all ASIDs (AArch64 version) */
1782     ARMCPU *cpu = arm_env_get_cpu(env);
1783     uint64_t pageaddr = value << 12;
1784     tlb_flush_page(CPU(cpu), pageaddr);
1785 }
1786
1787 static void tlbi_aa64_asid_write(CPUARMState *env, const ARMCPRegInfo *ri,
1788                                  uint64_t value)
1789 {
1790     /* Invalidate by ASID (AArch64 version) */
1791     ARMCPU *cpu = arm_env_get_cpu(env);
1792     int asid = extract64(value, 48, 16);
1793     tlb_flush(CPU(cpu), asid == 0);
1794 }
1795
1796 static CPAccessResult aa64_zva_access(CPUARMState *env, const ARMCPRegInfo *ri)
1797 {
1798     /* We don't implement EL2, so the only control on DC ZVA is the
1799      * bit in the SCTLR which can prohibit access for EL0.
1800      */
1801     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_DZE)) {
1802         return CP_ACCESS_TRAP;
1803     }
1804     return CP_ACCESS_OK;
1805 }
1806
1807 static uint64_t aa64_dczid_read(CPUARMState *env, const ARMCPRegInfo *ri)
1808 {
1809     ARMCPU *cpu = arm_env_get_cpu(env);
1810     int dzp_bit = 1 << 4;
1811
1812     /* DZP indicates whether DC ZVA access is allowed */
1813     if (aa64_zva_access(env, NULL) != CP_ACCESS_OK) {
1814         dzp_bit = 0;
1815     }
1816     return cpu->dcz_blocksize | dzp_bit;
1817 }
1818
1819 static CPAccessResult sp_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
1820 {
1821     if (!env->pstate & PSTATE_SP) {
1822         /* Access to SP_EL0 is undefined if it's being used as
1823          * the stack pointer.
1824          */
1825         return CP_ACCESS_TRAP_UNCATEGORIZED;
1826     }
1827     return CP_ACCESS_OK;
1828 }
1829
1830 static uint64_t spsel_read(CPUARMState *env, const ARMCPRegInfo *ri)
1831 {
1832     return env->pstate & PSTATE_SP;
1833 }
1834
1835 static void spsel_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t val)
1836 {
1837     update_spsel(env, val);
1838 }
1839
1840 static const ARMCPRegInfo v8_cp_reginfo[] = {
1841     /* Minimal set of EL0-visible registers. This will need to be expanded
1842      * significantly for system emulation of AArch64 CPUs.
1843      */
1844     { .name = "NZCV", .state = ARM_CP_STATE_AA64,
1845       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 2,
1846       .access = PL0_RW, .type = ARM_CP_NZCV },
1847     { .name = "DAIF", .state = ARM_CP_STATE_AA64,
1848       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 2,
1849       .type = ARM_CP_NO_MIGRATE,
1850       .access = PL0_RW, .accessfn = aa64_daif_access,
1851       .fieldoffset = offsetof(CPUARMState, daif),
1852       .writefn = aa64_daif_write, .resetfn = arm_cp_reset_ignore },
1853     { .name = "FPCR", .state = ARM_CP_STATE_AA64,
1854       .opc0 = 3, .opc1 = 3, .opc2 = 0, .crn = 4, .crm = 4,
1855       .access = PL0_RW, .readfn = aa64_fpcr_read, .writefn = aa64_fpcr_write },
1856     { .name = "FPSR", .state = ARM_CP_STATE_AA64,
1857       .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 4, .crm = 4,
1858       .access = PL0_RW, .readfn = aa64_fpsr_read, .writefn = aa64_fpsr_write },
1859     { .name = "DCZID_EL0", .state = ARM_CP_STATE_AA64,
1860       .opc0 = 3, .opc1 = 3, .opc2 = 7, .crn = 0, .crm = 0,
1861       .access = PL0_R, .type = ARM_CP_NO_MIGRATE,
1862       .readfn = aa64_dczid_read },
1863     { .name = "DC_ZVA", .state = ARM_CP_STATE_AA64,
1864       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 4, .opc2 = 1,
1865       .access = PL0_W, .type = ARM_CP_DC_ZVA,
1866 #ifndef CONFIG_USER_ONLY
1867       /* Avoid overhead of an access check that always passes in user-mode */
1868       .accessfn = aa64_zva_access,
1869 #endif
1870     },
1871     { .name = "CURRENTEL", .state = ARM_CP_STATE_AA64,
1872       .opc0 = 3, .opc1 = 0, .opc2 = 2, .crn = 4, .crm = 2,
1873       .access = PL1_R, .type = ARM_CP_CURRENTEL },
1874     /* Cache ops: all NOPs since we don't emulate caches */
1875     { .name = "IC_IALLUIS", .state = ARM_CP_STATE_AA64,
1876       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
1877       .access = PL1_W, .type = ARM_CP_NOP },
1878     { .name = "IC_IALLU", .state = ARM_CP_STATE_AA64,
1879       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
1880       .access = PL1_W, .type = ARM_CP_NOP },
1881     { .name = "IC_IVAU", .state = ARM_CP_STATE_AA64,
1882       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 5, .opc2 = 1,
1883       .access = PL0_W, .type = ARM_CP_NOP,
1884       .accessfn = aa64_cacheop_access },
1885     { .name = "DC_IVAC", .state = ARM_CP_STATE_AA64,
1886       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
1887       .access = PL1_W, .type = ARM_CP_NOP },
1888     { .name = "DC_ISW", .state = ARM_CP_STATE_AA64,
1889       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
1890       .access = PL1_W, .type = ARM_CP_NOP },
1891     { .name = "DC_CVAC", .state = ARM_CP_STATE_AA64,
1892       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 10, .opc2 = 1,
1893       .access = PL0_W, .type = ARM_CP_NOP,
1894       .accessfn = aa64_cacheop_access },
1895     { .name = "DC_CSW", .state = ARM_CP_STATE_AA64,
1896       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
1897       .access = PL1_W, .type = ARM_CP_NOP },
1898     { .name = "DC_CVAU", .state = ARM_CP_STATE_AA64,
1899       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 11, .opc2 = 1,
1900       .access = PL0_W, .type = ARM_CP_NOP,
1901       .accessfn = aa64_cacheop_access },
1902     { .name = "DC_CIVAC", .state = ARM_CP_STATE_AA64,
1903       .opc0 = 1, .opc1 = 3, .crn = 7, .crm = 14, .opc2 = 1,
1904       .access = PL0_W, .type = ARM_CP_NOP,
1905       .accessfn = aa64_cacheop_access },
1906     { .name = "DC_CISW", .state = ARM_CP_STATE_AA64,
1907       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
1908       .access = PL1_W, .type = ARM_CP_NOP },
1909     /* TLBI operations */
1910     { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
1911       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1912       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1913       .writefn = tlbiall_write },
1914     { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
1915       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1916       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1917       .writefn = tlbi_aa64_va_write },
1918     { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
1919       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1920       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1921       .writefn = tlbi_aa64_asid_write },
1922     { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
1923       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1924       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1925       .writefn = tlbi_aa64_vaa_write },
1926     { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
1927       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
1928       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1929       .writefn = tlbi_aa64_va_write },
1930     { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
1931       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
1932       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1933       .writefn = tlbi_aa64_vaa_write },
1934     { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
1935       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
1936       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1937       .writefn = tlbiall_write },
1938     { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
1939       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
1940       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1941       .writefn = tlbi_aa64_va_write },
1942     { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
1943       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
1944       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1945       .writefn = tlbi_aa64_asid_write },
1946     { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
1947       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
1948       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1949       .writefn = tlbi_aa64_vaa_write },
1950     { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
1951       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
1952       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1953       .writefn = tlbi_aa64_va_write },
1954     { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
1955       .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
1956       .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
1957       .writefn = tlbi_aa64_vaa_write },
1958 #ifndef CONFIG_USER_ONLY
1959     /* 64 bit address translation operations */
1960     { .name = "AT_S1E1R", .state = ARM_CP_STATE_AA64,
1961       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 0,
1962       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
1963     { .name = "AT_S1E1W", .state = ARM_CP_STATE_AA64,
1964       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 1,
1965       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
1966     { .name = "AT_S1E0R", .state = ARM_CP_STATE_AA64,
1967       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 2,
1968       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
1969     { .name = "AT_S1E0W", .state = ARM_CP_STATE_AA64,
1970       .opc0 = 1, .opc1 = 0, .crn = 7, .crm = 8, .opc2 = 3,
1971       .access = PL1_W, .type = ARM_CP_NO_MIGRATE, .writefn = ats_write },
1972 #endif
1973     /* 32 bit TLB invalidates, Inner Shareable */
1974     { .name = "TLBIALLIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
1975       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
1976     { .name = "TLBIMVAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
1977       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
1978     { .name = "TLBIASIDIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
1979       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
1980     { .name = "TLBIMVAAIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
1981       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
1982     { .name = "TLBIMVALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
1983       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
1984     { .name = "TLBIMVAALIS", .cp = 15, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
1985       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
1986     /* 32 bit ITLB invalidates */
1987     { .name = "ITLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 0,
1988       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
1989     { .name = "ITLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 1,
1990       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
1991     { .name = "ITLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 5, .opc2 = 2,
1992       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
1993     /* 32 bit DTLB invalidates */
1994     { .name = "DTLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 0,
1995       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
1996     { .name = "DTLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 1,
1997       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
1998     { .name = "DTLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 6, .opc2 = 2,
1999       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
2000     /* 32 bit TLB invalidates */
2001     { .name = "TLBIALL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
2002       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiall_write },
2003     { .name = "TLBIMVA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
2004       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2005     { .name = "TLBIASID", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
2006       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbiasid_write },
2007     { .name = "TLBIMVAA", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
2008       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2009     { .name = "TLBIMVAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
2010       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimva_write },
2011     { .name = "TLBIMVAAL", .cp = 15, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
2012       .type = ARM_CP_NO_MIGRATE, .access = PL1_W, .writefn = tlbimvaa_write },
2013     /* 32 bit cache operations */
2014     { .name = "ICIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 0,
2015       .type = ARM_CP_NOP, .access = PL1_W },
2016     { .name = "BPIALLUIS", .cp = 15, .opc1 = 0, .crn = 7, .crm = 1, .opc2 = 6,
2017       .type = ARM_CP_NOP, .access = PL1_W },
2018     { .name = "ICIALLU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 0,
2019       .type = ARM_CP_NOP, .access = PL1_W },
2020     { .name = "ICIMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 1,
2021       .type = ARM_CP_NOP, .access = PL1_W },
2022     { .name = "BPIALL", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 6,
2023       .type = ARM_CP_NOP, .access = PL1_W },
2024     { .name = "BPIMVA", .cp = 15, .opc1 = 0, .crn = 7, .crm = 5, .opc2 = 7,
2025       .type = ARM_CP_NOP, .access = PL1_W },
2026     { .name = "DCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 1,
2027       .type = ARM_CP_NOP, .access = PL1_W },
2028     { .name = "DCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 6, .opc2 = 2,
2029       .type = ARM_CP_NOP, .access = PL1_W },
2030     { .name = "DCCMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 1,
2031       .type = ARM_CP_NOP, .access = PL1_W },
2032     { .name = "DCCSW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 10, .opc2 = 2,
2033       .type = ARM_CP_NOP, .access = PL1_W },
2034     { .name = "DCCMVAU", .cp = 15, .opc1 = 0, .crn = 7, .crm = 11, .opc2 = 1,
2035       .type = ARM_CP_NOP, .access = PL1_W },
2036     { .name = "DCCIMVAC", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 1,
2037       .type = ARM_CP_NOP, .access = PL1_W },
2038     { .name = "DCCISW", .cp = 15, .opc1 = 0, .crn = 7, .crm = 14, .opc2 = 2,
2039       .type = ARM_CP_NOP, .access = PL1_W },
2040     /* MMU Domain access control / MPU write buffer control */
2041     { .name = "DACR", .cp = 15,
2042       .opc1 = 0, .crn = 3, .crm = 0, .opc2 = 0,
2043       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c3),
2044       .resetvalue = 0, .writefn = dacr_write, .raw_writefn = raw_write, },
2045     /* Dummy implementation of monitor debug system control register:
2046      * we don't support debug.
2047      */
2048     { .name = "MDSCR_EL1", .state = ARM_CP_STATE_AA64,
2049       .opc0 = 2, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
2050       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
2051     /* We define a dummy WI OSLAR_EL1, because Linux writes to it. */
2052     { .name = "OSLAR_EL1", .state = ARM_CP_STATE_AA64,
2053       .opc0 = 2, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 4,
2054       .access = PL1_W, .type = ARM_CP_NOP },
2055     { .name = "ELR_EL1", .state = ARM_CP_STATE_AA64,
2056       .type = ARM_CP_NO_MIGRATE,
2057       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 1,
2058       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, elr_el1) },
2059     { .name = "SPSR_EL1", .state = ARM_CP_STATE_AA64,
2060       .type = ARM_CP_NO_MIGRATE,
2061       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 0, .opc2 = 0,
2062       .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, banked_spsr[0]) },
2063     /* We rely on the access checks not allowing the guest to write to the
2064      * state field when SPSel indicates that it's being used as the stack
2065      * pointer.
2066      */
2067     { .name = "SP_EL0", .state = ARM_CP_STATE_AA64,
2068       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 1, .opc2 = 0,
2069       .access = PL1_RW, .accessfn = sp_el0_access,
2070       .type = ARM_CP_NO_MIGRATE,
2071       .fieldoffset = offsetof(CPUARMState, sp_el[0]) },
2072     { .name = "SPSel", .state = ARM_CP_STATE_AA64,
2073       .opc0 = 3, .opc1 = 0, .crn = 4, .crm = 2, .opc2 = 0,
2074       .type = ARM_CP_NO_MIGRATE,
2075       .access = PL1_RW, .readfn = spsel_read, .writefn = spsel_write },
2076     REGINFO_SENTINEL
2077 };
2078
2079 static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
2080                         uint64_t value)
2081 {
2082     ARMCPU *cpu = arm_env_get_cpu(env);
2083
2084     if (env->cp15.c1_sys == value) {
2085         /* Skip the TLB flush if nothing actually changed; Linux likes
2086          * to do a lot of pointless SCTLR writes.
2087          */
2088         return;
2089     }
2090
2091     env->cp15.c1_sys = value;
2092     /* ??? Lots of these bits are not implemented.  */
2093     /* This may enable/disable the MMU, so do a TLB flush.  */
2094     tlb_flush(CPU(cpu), 1);
2095 }
2096
2097 static CPAccessResult ctr_el0_access(CPUARMState *env, const ARMCPRegInfo *ri)
2098 {
2099     /* Only accessible in EL0 if SCTLR.UCT is set (and only in AArch64,
2100      * but the AArch32 CTR has its own reginfo struct)
2101      */
2102     if (arm_current_pl(env) == 0 && !(env->cp15.c1_sys & SCTLR_UCT)) {
2103         return CP_ACCESS_TRAP;
2104     }
2105     return CP_ACCESS_OK;
2106 }
2107
2108 static void define_aarch64_debug_regs(ARMCPU *cpu)
2109 {
2110     /* Define breakpoint and watchpoint registers. These do nothing
2111      * but read as written, for now.
2112      */
2113     int i;
2114
2115     for (i = 0; i < 16; i++) {
2116         ARMCPRegInfo dbgregs[] = {
2117             { .name = "DBGBVR", .state = ARM_CP_STATE_AA64,
2118               .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 4,
2119               .access = PL1_RW,
2120               .fieldoffset = offsetof(CPUARMState, cp15.dbgbvr[i]) },
2121             { .name = "DBGBCR", .state = ARM_CP_STATE_AA64,
2122               .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 5,
2123               .access = PL1_RW,
2124               .fieldoffset = offsetof(CPUARMState, cp15.dbgbcr[i]) },
2125             { .name = "DBGWVR", .state = ARM_CP_STATE_AA64,
2126               .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 6,
2127               .access = PL1_RW,
2128               .fieldoffset = offsetof(CPUARMState, cp15.dbgwvr[i]) },
2129             { .name = "DBGWCR", .state = ARM_CP_STATE_AA64,
2130               .opc0 = 2, .opc1 = 0, .crn = 0, .crm = i, .opc2 = 7,
2131               .access = PL1_RW,
2132               .fieldoffset = offsetof(CPUARMState, cp15.dbgwcr[i]) },
2133                REGINFO_SENTINEL
2134         };
2135         define_arm_cp_regs(cpu, dbgregs);
2136     }
2137 }
2138
2139 void register_cp_regs_for_features(ARMCPU *cpu)
2140 {
2141     /* Register all the coprocessor registers based on feature bits */
2142     CPUARMState *env = &cpu->env;
2143     if (arm_feature(env, ARM_FEATURE_M)) {
2144         /* M profile has no coprocessor registers */
2145         return;
2146     }
2147
2148     define_arm_cp_regs(cpu, cp_reginfo);
2149     if (!arm_feature(env, ARM_FEATURE_V8)) {
2150         /* Must go early as it is full of wildcards that may be
2151          * overridden by later definitions.
2152          */
2153         define_arm_cp_regs(cpu, not_v8_cp_reginfo);
2154     }
2155
2156     if (arm_feature(env, ARM_FEATURE_V6)) {
2157         /* The ID registers all have impdef reset values */
2158         ARMCPRegInfo v6_idregs[] = {
2159             { .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
2160               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
2161               .access = PL1_R, .type = ARM_CP_CONST,
2162               .resetvalue = cpu->id_pfr0 },
2163             { .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
2164               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
2165               .access = PL1_R, .type = ARM_CP_CONST,
2166               .resetvalue = cpu->id_pfr1 },
2167             { .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
2168               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
2169               .access = PL1_R, .type = ARM_CP_CONST,
2170               .resetvalue = cpu->id_dfr0 },
2171             { .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
2172               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
2173               .access = PL1_R, .type = ARM_CP_CONST,
2174               .resetvalue = cpu->id_afr0 },
2175             { .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
2176               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
2177               .access = PL1_R, .type = ARM_CP_CONST,
2178               .resetvalue = cpu->id_mmfr0 },
2179             { .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
2180               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
2181               .access = PL1_R, .type = ARM_CP_CONST,
2182               .resetvalue = cpu->id_mmfr1 },
2183             { .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
2184               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
2185               .access = PL1_R, .type = ARM_CP_CONST,
2186               .resetvalue = cpu->id_mmfr2 },
2187             { .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
2188               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
2189               .access = PL1_R, .type = ARM_CP_CONST,
2190               .resetvalue = cpu->id_mmfr3 },
2191             { .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
2192               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
2193               .access = PL1_R, .type = ARM_CP_CONST,
2194               .resetvalue = cpu->id_isar0 },
2195             { .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
2196               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
2197               .access = PL1_R, .type = ARM_CP_CONST,
2198               .resetvalue = cpu->id_isar1 },
2199             { .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
2200               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
2201               .access = PL1_R, .type = ARM_CP_CONST,
2202               .resetvalue = cpu->id_isar2 },
2203             { .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
2204               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
2205               .access = PL1_R, .type = ARM_CP_CONST,
2206               .resetvalue = cpu->id_isar3 },
2207             { .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
2208               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
2209               .access = PL1_R, .type = ARM_CP_CONST,
2210               .resetvalue = cpu->id_isar4 },
2211             { .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
2212               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
2213               .access = PL1_R, .type = ARM_CP_CONST,
2214               .resetvalue = cpu->id_isar5 },
2215             /* 6..7 are as yet unallocated and must RAZ */
2216             { .name = "ID_ISAR6", .cp = 15, .crn = 0, .crm = 2,
2217               .opc1 = 0, .opc2 = 6, .access = PL1_R, .type = ARM_CP_CONST,
2218               .resetvalue = 0 },
2219             { .name = "ID_ISAR7", .cp = 15, .crn = 0, .crm = 2,
2220               .opc1 = 0, .opc2 = 7, .access = PL1_R, .type = ARM_CP_CONST,
2221               .resetvalue = 0 },
2222             REGINFO_SENTINEL
2223         };
2224         define_arm_cp_regs(cpu, v6_idregs);
2225         define_arm_cp_regs(cpu, v6_cp_reginfo);
2226     } else {
2227         define_arm_cp_regs(cpu, not_v6_cp_reginfo);
2228     }
2229     if (arm_feature(env, ARM_FEATURE_V6K)) {
2230         define_arm_cp_regs(cpu, v6k_cp_reginfo);
2231     }
2232     if (arm_feature(env, ARM_FEATURE_V7)) {
2233         /* v7 performance monitor control register: same implementor
2234          * field as main ID register, and we implement only the cycle
2235          * count register.
2236          */
2237 #ifndef CONFIG_USER_ONLY
2238         ARMCPRegInfo pmcr = {
2239             .name = "PMCR", .cp = 15, .crn = 9, .crm = 12, .opc1 = 0, .opc2 = 0,
2240             .access = PL0_RW, .resetvalue = cpu->midr & 0xff000000,
2241             .type = ARM_CP_IO,
2242             .fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
2243             .accessfn = pmreg_access, .writefn = pmcr_write,
2244             .raw_writefn = raw_write,
2245         };
2246         define_one_arm_cp_reg(cpu, &pmcr);
2247 #endif
2248         ARMCPRegInfo clidr = {
2249             .name = "CLIDR", .state = ARM_CP_STATE_BOTH,
2250             .opc0 = 3, .crn = 0, .crm = 0, .opc1 = 1, .opc2 = 1,
2251             .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->clidr
2252         };
2253         define_one_arm_cp_reg(cpu, &clidr);
2254         define_arm_cp_regs(cpu, v7_cp_reginfo);
2255     } else {
2256         define_arm_cp_regs(cpu, not_v7_cp_reginfo);
2257     }
2258     if (arm_feature(env, ARM_FEATURE_V8)) {
2259         /* AArch64 ID registers, which all have impdef reset values */
2260         ARMCPRegInfo v8_idregs[] = {
2261             { .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
2262               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
2263               .access = PL1_R, .type = ARM_CP_CONST,
2264               .resetvalue = cpu->id_aa64pfr0 },
2265             { .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
2266               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
2267               .access = PL1_R, .type = ARM_CP_CONST,
2268               .resetvalue = cpu->id_aa64pfr1},
2269             { .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
2270               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
2271               .access = PL1_R, .type = ARM_CP_CONST,
2272               /* We mask out the PMUVer field, beacuse we don't currently
2273                * implement the PMU. Not advertising it prevents the guest
2274                * from trying to use it and getting UNDEFs on registers we
2275                * don't implement.
2276                */
2277               .resetvalue = cpu->id_aa64dfr0 & ~0xf00 },
2278             { .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
2279               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
2280               .access = PL1_R, .type = ARM_CP_CONST,
2281               .resetvalue = cpu->id_aa64dfr1 },
2282             { .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
2283               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
2284               .access = PL1_R, .type = ARM_CP_CONST,
2285               .resetvalue = cpu->id_aa64afr0 },
2286             { .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
2287               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
2288               .access = PL1_R, .type = ARM_CP_CONST,
2289               .resetvalue = cpu->id_aa64afr1 },
2290             { .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
2291               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
2292               .access = PL1_R, .type = ARM_CP_CONST,
2293               .resetvalue = cpu->id_aa64isar0 },
2294             { .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
2295               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
2296               .access = PL1_R, .type = ARM_CP_CONST,
2297               .resetvalue = cpu->id_aa64isar1 },
2298             { .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
2299               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
2300               .access = PL1_R, .type = ARM_CP_CONST,
2301               .resetvalue = cpu->id_aa64mmfr0 },
2302             { .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
2303               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
2304               .access = PL1_R, .type = ARM_CP_CONST,
2305               .resetvalue = cpu->id_aa64mmfr1 },
2306             { .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
2307               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
2308               .access = PL1_R, .type = ARM_CP_CONST,
2309               .resetvalue = cpu->mvfr0 },
2310             { .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
2311               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
2312               .access = PL1_R, .type = ARM_CP_CONST,
2313               .resetvalue = cpu->mvfr1 },
2314             { .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
2315               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
2316               .access = PL1_R, .type = ARM_CP_CONST,
2317               .resetvalue = cpu->mvfr2 },
2318             REGINFO_SENTINEL
2319         };
2320         ARMCPRegInfo rvbar = {
2321             .name = "RVBAR_EL1", .state = ARM_CP_STATE_AA64,
2322             .opc0 = 3, .opc1 = 0, .crn = 12, .crm = 0, .opc2 = 2,
2323             .type = ARM_CP_CONST, .access = PL1_R, .resetvalue = cpu->rvbar
2324         };
2325         define_one_arm_cp_reg(cpu, &rvbar);
2326         define_arm_cp_regs(cpu, v8_idregs);
2327         define_arm_cp_regs(cpu, v8_cp_reginfo);
2328         define_aarch64_debug_regs(cpu);
2329     }
2330     if (arm_feature(env, ARM_FEATURE_MPU)) {
2331         /* These are the MPU registers prior to PMSAv6. Any new
2332          * PMSA core later than the ARM946 will require that we
2333          * implement the PMSAv6 or PMSAv7 registers, which are
2334          * completely different.
2335          */
2336         assert(!arm_feature(env, ARM_FEATURE_V6));
2337         define_arm_cp_regs(cpu, pmsav5_cp_reginfo);
2338     } else {
2339         define_arm_cp_regs(cpu, vmsa_cp_reginfo);
2340     }
2341     if (arm_feature(env, ARM_FEATURE_THUMB2EE)) {
2342         define_arm_cp_regs(cpu, t2ee_cp_reginfo);
2343     }
2344     if (arm_feature(env, ARM_FEATURE_GENERIC_TIMER)) {
2345         define_arm_cp_regs(cpu, generic_timer_cp_reginfo);
2346     }
2347     if (arm_feature(env, ARM_FEATURE_VAPA)) {
2348         define_arm_cp_regs(cpu, vapa_cp_reginfo);
2349     }
2350     if (arm_feature(env, ARM_FEATURE_CACHE_TEST_CLEAN)) {
2351         define_arm_cp_regs(cpu, cache_test_clean_cp_reginfo);
2352     }
2353     if (arm_feature(env, ARM_FEATURE_CACHE_DIRTY_REG)) {
2354         define_arm_cp_regs(cpu, cache_dirty_status_cp_reginfo);
2355     }
2356     if (arm_feature(env, ARM_FEATURE_CACHE_BLOCK_OPS)) {
2357         define_arm_cp_regs(cpu, cache_block_ops_cp_reginfo);
2358     }
2359     if (arm_feature(env, ARM_FEATURE_OMAPCP)) {
2360         define_arm_cp_regs(cpu, omap_cp_reginfo);
2361     }
2362     if (arm_feature(env, ARM_FEATURE_STRONGARM)) {
2363         define_arm_cp_regs(cpu, strongarm_cp_reginfo);
2364     }
2365     if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2366         define_arm_cp_regs(cpu, xscale_cp_reginfo);
2367     }
2368     if (arm_feature(env, ARM_FEATURE_DUMMY_C15_REGS)) {
2369         define_arm_cp_regs(cpu, dummy_c15_cp_reginfo);
2370     }
2371     if (arm_feature(env, ARM_FEATURE_LPAE)) {
2372         define_arm_cp_regs(cpu, lpae_cp_reginfo);
2373     }
2374     /* Slightly awkwardly, the OMAP and StrongARM cores need all of
2375      * cp15 crn=0 to be writes-ignored, whereas for other cores they should
2376      * be read-only (ie write causes UNDEF exception).
2377      */
2378     {
2379         ARMCPRegInfo id_pre_v8_midr_cp_reginfo[] = {
2380             /* Pre-v8 MIDR space.
2381              * Note that the MIDR isn't a simple constant register because
2382              * of the TI925 behaviour where writes to another register can
2383              * cause the MIDR value to change.
2384              *
2385              * Unimplemented registers in the c15 0 0 0 space default to
2386              * MIDR. Define MIDR first as this entire space, then CTR, TCMTR
2387              * and friends override accordingly.
2388              */
2389             { .name = "MIDR",
2390               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = CP_ANY,
2391               .access = PL1_R, .resetvalue = cpu->midr,
2392               .writefn = arm_cp_write_ignore, .raw_writefn = raw_write,
2393               .fieldoffset = offsetof(CPUARMState, cp15.c0_cpuid),
2394               .type = ARM_CP_OVERRIDE },
2395             /* crn = 0 op1 = 0 crm = 3..7 : currently unassigned; we RAZ. */
2396             { .name = "DUMMY",
2397               .cp = 15, .crn = 0, .crm = 3, .opc1 = 0, .opc2 = CP_ANY,
2398               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2399             { .name = "DUMMY",
2400               .cp = 15, .crn = 0, .crm = 4, .opc1 = 0, .opc2 = CP_ANY,
2401               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2402             { .name = "DUMMY",
2403               .cp = 15, .crn = 0, .crm = 5, .opc1 = 0, .opc2 = CP_ANY,
2404               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2405             { .name = "DUMMY",
2406               .cp = 15, .crn = 0, .crm = 6, .opc1 = 0, .opc2 = CP_ANY,
2407               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2408             { .name = "DUMMY",
2409               .cp = 15, .crn = 0, .crm = 7, .opc1 = 0, .opc2 = CP_ANY,
2410               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2411             REGINFO_SENTINEL
2412         };
2413         ARMCPRegInfo id_v8_midr_cp_reginfo[] = {
2414             /* v8 MIDR -- the wildcard isn't necessary, and nor is the
2415              * variable-MIDR TI925 behaviour. Instead we have a single
2416              * (strictly speaking IMPDEF) alias of the MIDR, REVIDR.
2417              */
2418             { .name = "MIDR_EL1", .state = ARM_CP_STATE_BOTH,
2419               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 0,
2420               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
2421             { .name = "REVIDR_EL1", .state = ARM_CP_STATE_BOTH,
2422               .opc0 = 3, .opc1 = 0, .crn = 0, .crm = 0, .opc2 = 6,
2423               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->midr },
2424             REGINFO_SENTINEL
2425         };
2426         ARMCPRegInfo id_cp_reginfo[] = {
2427             /* These are common to v8 and pre-v8 */
2428             { .name = "CTR",
2429               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 1,
2430               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
2431             { .name = "CTR_EL0", .state = ARM_CP_STATE_AA64,
2432               .opc0 = 3, .opc1 = 3, .opc2 = 1, .crn = 0, .crm = 0,
2433               .access = PL0_R, .accessfn = ctr_el0_access,
2434               .type = ARM_CP_CONST, .resetvalue = cpu->ctr },
2435             /* TCMTR and TLBTR exist in v8 but have no 64-bit versions */
2436             { .name = "TCMTR",
2437               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 2,
2438               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2439             { .name = "TLBTR",
2440               .cp = 15, .crn = 0, .crm = 0, .opc1 = 0, .opc2 = 3,
2441               .access = PL1_R, .type = ARM_CP_CONST, .resetvalue = 0 },
2442             REGINFO_SENTINEL
2443         };
2444         ARMCPRegInfo crn0_wi_reginfo = {
2445             .name = "CRN0_WI", .cp = 15, .crn = 0, .crm = CP_ANY,
2446             .opc1 = CP_ANY, .opc2 = CP_ANY, .access = PL1_W,
2447             .type = ARM_CP_NOP | ARM_CP_OVERRIDE
2448         };
2449         if (arm_feature(env, ARM_FEATURE_OMAPCP) ||
2450             arm_feature(env, ARM_FEATURE_STRONGARM)) {
2451             ARMCPRegInfo *r;
2452             /* Register the blanket "writes ignored" value first to cover the
2453              * whole space. Then update the specific ID registers to allow write
2454              * access, so that they ignore writes rather than causing them to
2455              * UNDEF.
2456              */
2457             define_one_arm_cp_reg(cpu, &crn0_wi_reginfo);
2458             for (r = id_pre_v8_midr_cp_reginfo;
2459                  r->type != ARM_CP_SENTINEL; r++) {
2460                 r->access = PL1_RW;
2461             }
2462             for (r = id_cp_reginfo; r->type != ARM_CP_SENTINEL; r++) {
2463                 r->access = PL1_RW;
2464             }
2465         }
2466         if (arm_feature(env, ARM_FEATURE_V8)) {
2467             define_arm_cp_regs(cpu, id_v8_midr_cp_reginfo);
2468         } else {
2469             define_arm_cp_regs(cpu, id_pre_v8_midr_cp_reginfo);
2470         }
2471         define_arm_cp_regs(cpu, id_cp_reginfo);
2472     }
2473
2474     if (arm_feature(env, ARM_FEATURE_MPIDR)) {
2475         define_arm_cp_regs(cpu, mpidr_cp_reginfo);
2476     }
2477
2478     if (arm_feature(env, ARM_FEATURE_AUXCR)) {
2479         ARMCPRegInfo auxcr = {
2480             .name = "ACTLR_EL1", .state = ARM_CP_STATE_BOTH,
2481             .opc0 = 3, .opc1 = 0, .crn = 1, .crm = 0, .opc2 = 1,
2482             .access = PL1_RW, .type = ARM_CP_CONST,
2483             .resetvalue = cpu->reset_auxcr
2484         };
2485         define_one_arm_cp_reg(cpu, &auxcr);
2486     }
2487
2488     if (arm_feature(env, ARM_FEATURE_CBAR)) {
2489         if (arm_feature(env, ARM_FEATURE_AARCH64)) {
2490             /* 32 bit view is [31:18] 0...0 [43:32]. */
2491             uint32_t cbar32 = (extract64(cpu->reset_cbar, 18, 14) << 18)
2492                 | extract64(cpu->reset_cbar, 32, 12);
2493             ARMCPRegInfo cbar_reginfo[] = {
2494                 { .name = "CBAR",
2495                   .type = ARM_CP_CONST,
2496                   .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
2497                   .access = PL1_R, .resetvalue = cpu->reset_cbar },
2498                 { .name = "CBAR_EL1", .state = ARM_CP_STATE_AA64,
2499                   .type = ARM_CP_CONST,
2500                   .opc0 = 3, .opc1 = 1, .crn = 15, .crm = 3, .opc2 = 0,
2501                   .access = PL1_R, .resetvalue = cbar32 },
2502                 REGINFO_SENTINEL
2503             };
2504             /* We don't implement a r/w 64 bit CBAR currently */
2505             assert(arm_feature(env, ARM_FEATURE_CBAR_RO));
2506             define_arm_cp_regs(cpu, cbar_reginfo);
2507         } else {
2508             ARMCPRegInfo cbar = {
2509                 .name = "CBAR",
2510                 .cp = 15, .crn = 15, .crm = 0, .opc1 = 4, .opc2 = 0,
2511                 .access = PL1_R|PL3_W, .resetvalue = cpu->reset_cbar,
2512                 .fieldoffset = offsetof(CPUARMState,
2513                                         cp15.c15_config_base_address)
2514             };
2515             if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
2516                 cbar.access = PL1_R;
2517                 cbar.fieldoffset = 0;
2518                 cbar.type = ARM_CP_CONST;
2519             }
2520             define_one_arm_cp_reg(cpu, &cbar);
2521         }
2522     }
2523
2524     /* Generic registers whose values depend on the implementation */
2525     {
2526         ARMCPRegInfo sctlr = {
2527             .name = "SCTLR", .state = ARM_CP_STATE_BOTH,
2528             .opc0 = 3, .crn = 1, .crm = 0, .opc1 = 0, .opc2 = 0,
2529             .access = PL1_RW, .fieldoffset = offsetof(CPUARMState, cp15.c1_sys),
2530             .writefn = sctlr_write, .resetvalue = cpu->reset_sctlr,
2531             .raw_writefn = raw_write,
2532         };
2533         if (arm_feature(env, ARM_FEATURE_XSCALE)) {
2534             /* Normally we would always end the TB on an SCTLR write, but Linux
2535              * arch/arm/mach-pxa/sleep.S expects two instructions following
2536              * an MMU enable to execute from cache.  Imitate this behaviour.
2537              */
2538             sctlr.type |= ARM_CP_SUPPRESS_TB_END;
2539         }
2540         define_one_arm_cp_reg(cpu, &sctlr);
2541     }
2542 }
2543
2544 ARMCPU *cpu_arm_init(const char *cpu_model)
2545 {
2546     return ARM_CPU(cpu_generic_init(TYPE_ARM_CPU, cpu_model));
2547 }
2548
2549 void arm_cpu_register_gdb_regs_for_features(ARMCPU *cpu)
2550 {
2551     CPUState *cs = CPU(cpu);
2552     CPUARMState *env = &cpu->env;
2553
2554     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
2555         gdb_register_coprocessor(cs, aarch64_fpu_gdb_get_reg,
2556                                  aarch64_fpu_gdb_set_reg,
2557                                  34, "aarch64-fpu.xml", 0);
2558     } else if (arm_feature(env, ARM_FEATURE_NEON)) {
2559         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2560                                  51, "arm-neon.xml", 0);
2561     } else if (arm_feature(env, ARM_FEATURE_VFP3)) {
2562         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2563                                  35, "arm-vfp3.xml", 0);
2564     } else if (arm_feature(env, ARM_FEATURE_VFP)) {
2565         gdb_register_coprocessor(cs, vfp_gdb_get_reg, vfp_gdb_set_reg,
2566                                  19, "arm-vfp.xml", 0);
2567     }
2568 }
2569
2570 /* Sort alphabetically by type name, except for "any". */
2571 static gint arm_cpu_list_compare(gconstpointer a, gconstpointer b)
2572 {
2573     ObjectClass *class_a = (ObjectClass *)a;
2574     ObjectClass *class_b = (ObjectClass *)b;
2575     const char *name_a, *name_b;
2576
2577     name_a = object_class_get_name(class_a);
2578     name_b = object_class_get_name(class_b);
2579     if (strcmp(name_a, "any-" TYPE_ARM_CPU) == 0) {
2580         return 1;
2581     } else if (strcmp(name_b, "any-" TYPE_ARM_CPU) == 0) {
2582         return -1;
2583     } else {
2584         return strcmp(name_a, name_b);
2585     }
2586 }
2587
2588 static void arm_cpu_list_entry(gpointer data, gpointer user_data)
2589 {
2590     ObjectClass *oc = data;
2591     CPUListState *s = user_data;
2592     const char *typename;
2593     char *name;
2594
2595     typename = object_class_get_name(oc);
2596     name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_ARM_CPU));
2597     (*s->cpu_fprintf)(s->file, "  %s\n",
2598                       name);
2599     g_free(name);
2600 }
2601
2602 void arm_cpu_list(FILE *f, fprintf_function cpu_fprintf)
2603 {
2604     CPUListState s = {
2605         .file = f,
2606         .cpu_fprintf = cpu_fprintf,
2607     };
2608     GSList *list;
2609
2610     list = object_class_get_list(TYPE_ARM_CPU, false);
2611     list = g_slist_sort(list, arm_cpu_list_compare);
2612     (*cpu_fprintf)(f, "Available CPUs:\n");
2613     g_slist_foreach(list, arm_cpu_list_entry, &s);
2614     g_slist_free(list);
2615 #ifdef CONFIG_KVM
2616     /* The 'host' CPU type is dynamically registered only if KVM is
2617      * enabled, so we have to special-case it here:
2618      */
2619     (*cpu_fprintf)(f, "  host (only available in KVM mode)\n");
2620 #endif
2621 }
2622
2623 static void arm_cpu_add_definition(gpointer data, gpointer user_data)
2624 {
2625     ObjectClass *oc = data;
2626     CpuDefinitionInfoList **cpu_list = user_data;
2627     CpuDefinitionInfoList *entry;
2628     CpuDefinitionInfo *info;
2629     const char *typename;
2630
2631     typename = object_class_get_name(oc);
2632     info = g_malloc0(sizeof(*info));
2633     info->name = g_strndup(typename,
2634                            strlen(typename) - strlen("-" TYPE_ARM_CPU));
2635
2636     entry = g_malloc0(sizeof(*entry));
2637     entry->value = info;
2638     entry->next = *cpu_list;
2639     *cpu_list = entry;
2640 }
2641
2642 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
2643 {
2644     CpuDefinitionInfoList *cpu_list = NULL;
2645     GSList *list;
2646
2647     list = object_class_get_list(TYPE_ARM_CPU, false);
2648     g_slist_foreach(list, arm_cpu_add_definition, &cpu_list);
2649     g_slist_free(list);
2650
2651     return cpu_list;
2652 }
2653
2654 static void add_cpreg_to_hashtable(ARMCPU *cpu, const ARMCPRegInfo *r,
2655                                    void *opaque, int state,
2656                                    int crm, int opc1, int opc2)
2657 {
2658     /* Private utility function for define_one_arm_cp_reg_with_opaque():
2659      * add a single reginfo struct to the hash table.
2660      */
2661     uint32_t *key = g_new(uint32_t, 1);
2662     ARMCPRegInfo *r2 = g_memdup(r, sizeof(ARMCPRegInfo));
2663     int is64 = (r->type & ARM_CP_64BIT) ? 1 : 0;
2664     if (r->state == ARM_CP_STATE_BOTH && state == ARM_CP_STATE_AA32) {
2665         /* The AArch32 view of a shared register sees the lower 32 bits
2666          * of a 64 bit backing field. It is not migratable as the AArch64
2667          * view handles that. AArch64 also handles reset.
2668          * We assume it is a cp15 register.
2669          */
2670         r2->cp = 15;
2671         r2->type |= ARM_CP_NO_MIGRATE;
2672         r2->resetfn = arm_cp_reset_ignore;
2673 #ifdef HOST_WORDS_BIGENDIAN
2674         if (r2->fieldoffset) {
2675             r2->fieldoffset += sizeof(uint32_t);
2676         }
2677 #endif
2678     }
2679     if (state == ARM_CP_STATE_AA64) {
2680         /* To allow abbreviation of ARMCPRegInfo
2681          * definitions, we treat cp == 0 as equivalent to
2682          * the value for "standard guest-visible sysreg".
2683          */
2684         if (r->cp == 0) {
2685             r2->cp = CP_REG_ARM64_SYSREG_CP;
2686         }
2687         *key = ENCODE_AA64_CP_REG(r2->cp, r2->crn, crm,
2688                                   r2->opc0, opc1, opc2);
2689     } else {
2690         *key = ENCODE_CP_REG(r2->cp, is64, r2->crn, crm, opc1, opc2);
2691     }
2692     if (opaque) {
2693         r2->opaque = opaque;
2694     }
2695     /* reginfo passed to helpers is correct for the actual access,
2696      * and is never ARM_CP_STATE_BOTH:
2697      */
2698     r2->state = state;
2699     /* Make sure reginfo passed to helpers for wildcarded regs
2700      * has the correct crm/opc1/opc2 for this reg, not CP_ANY:
2701      */
2702     r2->crm = crm;
2703     r2->opc1 = opc1;
2704     r2->opc2 = opc2;
2705     /* By convention, for wildcarded registers only the first
2706      * entry is used for migration; the others are marked as
2707      * NO_MIGRATE so we don't try to transfer the register
2708      * multiple times. Special registers (ie NOP/WFI) are
2709      * never migratable.
2710      */
2711     if ((r->type & ARM_CP_SPECIAL) ||
2712         ((r->crm == CP_ANY) && crm != 0) ||
2713         ((r->opc1 == CP_ANY) && opc1 != 0) ||
2714         ((r->opc2 == CP_ANY) && opc2 != 0)) {
2715         r2->type |= ARM_CP_NO_MIGRATE;
2716     }
2717
2718     /* Overriding of an existing definition must be explicitly
2719      * requested.
2720      */
2721     if (!(r->type & ARM_CP_OVERRIDE)) {
2722         ARMCPRegInfo *oldreg;
2723         oldreg = g_hash_table_lookup(cpu->cp_regs, key);
2724         if (oldreg && !(oldreg->type & ARM_CP_OVERRIDE)) {
2725             fprintf(stderr, "Register redefined: cp=%d %d bit "
2726                     "crn=%d crm=%d opc1=%d opc2=%d, "
2727                     "was %s, now %s\n", r2->cp, 32 + 32 * is64,
2728                     r2->crn, r2->crm, r2->opc1, r2->opc2,
2729                     oldreg->name, r2->name);
2730             g_assert_not_reached();
2731         }
2732     }
2733     g_hash_table_insert(cpu->cp_regs, key, r2);
2734 }
2735
2736
2737 void define_one_arm_cp_reg_with_opaque(ARMCPU *cpu,
2738                                        const ARMCPRegInfo *r, void *opaque)
2739 {
2740     /* Define implementations of coprocessor registers.
2741      * We store these in a hashtable because typically
2742      * there are less than 150 registers in a space which
2743      * is 16*16*16*8*8 = 262144 in size.
2744      * Wildcarding is supported for the crm, opc1 and opc2 fields.
2745      * If a register is defined twice then the second definition is
2746      * used, so this can be used to define some generic registers and
2747      * then override them with implementation specific variations.
2748      * At least one of the original and the second definition should
2749      * include ARM_CP_OVERRIDE in its type bits -- this is just a guard
2750      * against accidental use.
2751      *
2752      * The state field defines whether the register is to be
2753      * visible in the AArch32 or AArch64 execution state. If the
2754      * state is set to ARM_CP_STATE_BOTH then we synthesise a
2755      * reginfo structure for the AArch32 view, which sees the lower
2756      * 32 bits of the 64 bit register.
2757      *
2758      * Only registers visible in AArch64 may set r->opc0; opc0 cannot
2759      * be wildcarded. AArch64 registers are always considered to be 64
2760      * bits; the ARM_CP_64BIT* flag applies only to the AArch32 view of
2761      * the register, if any.
2762      */
2763     int crm, opc1, opc2, state;
2764     int crmmin = (r->crm == CP_ANY) ? 0 : r->crm;
2765     int crmmax = (r->crm == CP_ANY) ? 15 : r->crm;
2766     int opc1min = (r->opc1 == CP_ANY) ? 0 : r->opc1;
2767     int opc1max = (r->opc1 == CP_ANY) ? 7 : r->opc1;
2768     int opc2min = (r->opc2 == CP_ANY) ? 0 : r->opc2;
2769     int opc2max = (r->opc2 == CP_ANY) ? 7 : r->opc2;
2770     /* 64 bit registers have only CRm and Opc1 fields */
2771     assert(!((r->type & ARM_CP_64BIT) && (r->opc2 || r->crn)));
2772     /* op0 only exists in the AArch64 encodings */
2773     assert((r->state != ARM_CP_STATE_AA32) || (r->opc0 == 0));
2774     /* AArch64 regs are all 64 bit so ARM_CP_64BIT is meaningless */
2775     assert((r->state != ARM_CP_STATE_AA64) || !(r->type & ARM_CP_64BIT));
2776     /* The AArch64 pseudocode CheckSystemAccess() specifies that op1
2777      * encodes a minimum access level for the register. We roll this
2778      * runtime check into our general permission check code, so check
2779      * here that the reginfo's specified permissions are strict enough
2780      * to encompass the generic architectural permission check.
2781      */
2782     if (r->state != ARM_CP_STATE_AA32) {
2783         int mask = 0;
2784         switch (r->opc1) {
2785         case 0: case 1: case 2:
2786             /* min_EL EL1 */
2787             mask = PL1_RW;
2788             break;
2789         case 3:
2790             /* min_EL EL0 */
2791             mask = PL0_RW;
2792             break;
2793         case 4:
2794             /* min_EL EL2 */
2795             mask = PL2_RW;
2796             break;
2797         case 5:
2798             /* unallocated encoding, so not possible */
2799             assert(false);
2800             break;
2801         case 6:
2802             /* min_EL EL3 */
2803             mask = PL3_RW;
2804             break;
2805         case 7:
2806             /* min_EL EL1, secure mode only (we don't check the latter) */
2807             mask = PL1_RW;
2808             break;
2809         default:
2810             /* broken reginfo with out-of-range opc1 */
2811             assert(false);
2812             break;
2813         }
2814         /* assert our permissions are not too lax (stricter is fine) */
2815         assert((r->access & ~mask) == 0);
2816     }
2817
2818     /* Check that the register definition has enough info to handle
2819      * reads and writes if they are permitted.
2820      */
2821     if (!(r->type & (ARM_CP_SPECIAL|ARM_CP_CONST))) {
2822         if (r->access & PL3_R) {
2823             assert(r->fieldoffset || r->readfn);
2824         }
2825         if (r->access & PL3_W) {
2826             assert(r->fieldoffset || r->writefn);
2827         }
2828     }
2829     /* Bad type field probably means missing sentinel at end of reg list */
2830     assert(cptype_valid(r->type));
2831     for (crm = crmmin; crm <= crmmax; crm++) {
2832         for (opc1 = opc1min; opc1 <= opc1max; opc1++) {
2833             for (opc2 = opc2min; opc2 <= opc2max; opc2++) {
2834                 for (state = ARM_CP_STATE_AA32;
2835                      state <= ARM_CP_STATE_AA64; state++) {
2836                     if (r->state != state && r->state != ARM_CP_STATE_BOTH) {
2837                         continue;
2838                     }
2839                     add_cpreg_to_hashtable(cpu, r, opaque, state,
2840                                            crm, opc1, opc2);
2841                 }
2842             }
2843         }
2844     }
2845 }
2846
2847 void define_arm_cp_regs_with_opaque(ARMCPU *cpu,
2848                                     const ARMCPRegInfo *regs, void *opaque)
2849 {
2850     /* Define a whole list of registers */
2851     const ARMCPRegInfo *r;
2852     for (r = regs; r->type != ARM_CP_SENTINEL; r++) {
2853         define_one_arm_cp_reg_with_opaque(cpu, r, opaque);
2854     }
2855 }
2856
2857 const ARMCPRegInfo *get_arm_cp_reginfo(GHashTable *cpregs, uint32_t encoded_cp)
2858 {
2859     return g_hash_table_lookup(cpregs, &encoded_cp);
2860 }
2861
2862 void arm_cp_write_ignore(CPUARMState *env, const ARMCPRegInfo *ri,
2863                          uint64_t value)
2864 {
2865     /* Helper coprocessor write function for write-ignore registers */
2866 }
2867
2868 uint64_t arm_cp_read_zero(CPUARMState *env, const ARMCPRegInfo *ri)
2869 {
2870     /* Helper coprocessor write function for read-as-zero registers */
2871     return 0;
2872 }
2873
2874 void arm_cp_reset_ignore(CPUARMState *env, const ARMCPRegInfo *opaque)
2875 {
2876     /* Helper coprocessor reset function for do-nothing-on-reset registers */
2877 }
2878
2879 static int bad_mode_switch(CPUARMState *env, int mode)
2880 {
2881     /* Return true if it is not valid for us to switch to
2882      * this CPU mode (ie all the UNPREDICTABLE cases in
2883      * the ARM ARM CPSRWriteByInstr pseudocode).
2884      */
2885     switch (mode) {
2886     case ARM_CPU_MODE_USR:
2887     case ARM_CPU_MODE_SYS:
2888     case ARM_CPU_MODE_SVC:
2889     case ARM_CPU_MODE_ABT:
2890     case ARM_CPU_MODE_UND:
2891     case ARM_CPU_MODE_IRQ:
2892     case ARM_CPU_MODE_FIQ:
2893         return 0;
2894     default:
2895         return 1;
2896     }
2897 }
2898
2899 uint32_t cpsr_read(CPUARMState *env)
2900 {
2901     int ZF;
2902     ZF = (env->ZF == 0);
2903     return env->uncached_cpsr | (env->NF & 0x80000000) | (ZF << 30) |
2904         (env->CF << 29) | ((env->VF & 0x80000000) >> 3) | (env->QF << 27)
2905         | (env->thumb << 5) | ((env->condexec_bits & 3) << 25)
2906         | ((env->condexec_bits & 0xfc) << 8)
2907         | (env->GE << 16) | (env->daif & CPSR_AIF);
2908 }
2909
2910 void cpsr_write(CPUARMState *env, uint32_t val, uint32_t mask)
2911 {
2912     if (mask & CPSR_NZCV) {
2913         env->ZF = (~val) & CPSR_Z;
2914         env->NF = val;
2915         env->CF = (val >> 29) & 1;
2916         env->VF = (val << 3) & 0x80000000;
2917     }
2918     if (mask & CPSR_Q)
2919         env->QF = ((val & CPSR_Q) != 0);
2920     if (mask & CPSR_T)
2921         env->thumb = ((val & CPSR_T) != 0);
2922     if (mask & CPSR_IT_0_1) {
2923         env->condexec_bits &= ~3;
2924         env->condexec_bits |= (val >> 25) & 3;
2925     }
2926     if (mask & CPSR_IT_2_7) {
2927         env->condexec_bits &= 3;
2928         env->condexec_bits |= (val >> 8) & 0xfc;
2929     }
2930     if (mask & CPSR_GE) {
2931         env->GE = (val >> 16) & 0xf;
2932     }
2933
2934     env->daif &= ~(CPSR_AIF & mask);
2935     env->daif |= val & CPSR_AIF & mask;
2936
2937     if ((env->uncached_cpsr ^ val) & mask & CPSR_M) {
2938         if (bad_mode_switch(env, val & CPSR_M)) {
2939             /* Attempt to switch to an invalid mode: this is UNPREDICTABLE.
2940              * We choose to ignore the attempt and leave the CPSR M field
2941              * untouched.
2942              */
2943             mask &= ~CPSR_M;
2944         } else {
2945             switch_mode(env, val & CPSR_M);
2946         }
2947     }
2948     mask &= ~CACHED_CPSR_BITS;
2949     env->uncached_cpsr = (env->uncached_cpsr & ~mask) | (val & mask);
2950 }
2951
2952 /* Sign/zero extend */
2953 uint32_t HELPER(sxtb16)(uint32_t x)
2954 {
2955     uint32_t res;
2956     res = (uint16_t)(int8_t)x;
2957     res |= (uint32_t)(int8_t)(x >> 16) << 16;
2958     return res;
2959 }
2960
2961 uint32_t HELPER(uxtb16)(uint32_t x)
2962 {
2963     uint32_t res;
2964     res = (uint16_t)(uint8_t)x;
2965     res |= (uint32_t)(uint8_t)(x >> 16) << 16;
2966     return res;
2967 }
2968
2969 uint32_t HELPER(clz)(uint32_t x)
2970 {
2971     return clz32(x);
2972 }
2973
2974 int32_t HELPER(sdiv)(int32_t num, int32_t den)
2975 {
2976     if (den == 0)
2977       return 0;
2978     if (num == INT_MIN && den == -1)
2979       return INT_MIN;
2980     return num / den;
2981 }
2982
2983 uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
2984 {
2985     if (den == 0)
2986       return 0;
2987     return num / den;
2988 }
2989
2990 uint32_t HELPER(rbit)(uint32_t x)
2991 {
2992     x =  ((x & 0xff000000) >> 24)
2993        | ((x & 0x00ff0000) >> 8)
2994        | ((x & 0x0000ff00) << 8)
2995        | ((x & 0x000000ff) << 24);
2996     x =  ((x & 0xf0f0f0f0) >> 4)
2997        | ((x & 0x0f0f0f0f) << 4);
2998     x =  ((x & 0x88888888) >> 3)
2999        | ((x & 0x44444444) >> 1)
3000        | ((x & 0x22222222) << 1)
3001        | ((x & 0x11111111) << 3);
3002     return x;
3003 }
3004
3005 #if defined(CONFIG_USER_ONLY)
3006
3007 void arm_cpu_do_interrupt(CPUState *cs)
3008 {
3009     cs->exception_index = -1;
3010 }
3011
3012 int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
3013                              int mmu_idx)
3014 {
3015     ARMCPU *cpu = ARM_CPU(cs);
3016     CPUARMState *env = &cpu->env;
3017
3018     env->exception.vaddress = address;
3019     if (rw == 2) {
3020         cs->exception_index = EXCP_PREFETCH_ABORT;
3021     } else {
3022         cs->exception_index = EXCP_DATA_ABORT;
3023     }
3024     return 1;
3025 }
3026
3027 /* These should probably raise undefined insn exceptions.  */
3028 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
3029 {
3030     ARMCPU *cpu = arm_env_get_cpu(env);
3031
3032     cpu_abort(CPU(cpu), "v7m_msr %d\n", reg);
3033 }
3034
3035 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
3036 {
3037     ARMCPU *cpu = arm_env_get_cpu(env);
3038
3039     cpu_abort(CPU(cpu), "v7m_mrs %d\n", reg);
3040     return 0;
3041 }
3042
3043 void switch_mode(CPUARMState *env, int mode)
3044 {
3045     ARMCPU *cpu = arm_env_get_cpu(env);
3046
3047     if (mode != ARM_CPU_MODE_USR) {
3048         cpu_abort(CPU(cpu), "Tried to switch out of user mode\n");
3049     }
3050 }
3051
3052 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
3053 {
3054     ARMCPU *cpu = arm_env_get_cpu(env);
3055
3056     cpu_abort(CPU(cpu), "banked r13 write\n");
3057 }
3058
3059 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
3060 {
3061     ARMCPU *cpu = arm_env_get_cpu(env);
3062
3063     cpu_abort(CPU(cpu), "banked r13 read\n");
3064     return 0;
3065 }
3066
3067 #else
3068
3069 /* Map CPU modes onto saved register banks.  */
3070 int bank_number(int mode)
3071 {
3072     switch (mode) {
3073     case ARM_CPU_MODE_USR:
3074     case ARM_CPU_MODE_SYS:
3075         return 0;
3076     case ARM_CPU_MODE_SVC:
3077         return 1;
3078     case ARM_CPU_MODE_ABT:
3079         return 2;
3080     case ARM_CPU_MODE_UND:
3081         return 3;
3082     case ARM_CPU_MODE_IRQ:
3083         return 4;
3084     case ARM_CPU_MODE_FIQ:
3085         return 5;
3086     }
3087     hw_error("bank number requested for bad CPSR mode value 0x%x\n", mode);
3088 }
3089
3090 void switch_mode(CPUARMState *env, int mode)
3091 {
3092     int old_mode;
3093     int i;
3094
3095     old_mode = env->uncached_cpsr & CPSR_M;
3096     if (mode == old_mode)
3097         return;
3098
3099     if (old_mode == ARM_CPU_MODE_FIQ) {
3100         memcpy (env->fiq_regs, env->regs + 8, 5 * sizeof(uint32_t));
3101         memcpy (env->regs + 8, env->usr_regs, 5 * sizeof(uint32_t));
3102     } else if (mode == ARM_CPU_MODE_FIQ) {
3103         memcpy (env->usr_regs, env->regs + 8, 5 * sizeof(uint32_t));
3104         memcpy (env->regs + 8, env->fiq_regs, 5 * sizeof(uint32_t));
3105     }
3106
3107     i = bank_number(old_mode);
3108     env->banked_r13[i] = env->regs[13];
3109     env->banked_r14[i] = env->regs[14];
3110     env->banked_spsr[i] = env->spsr;
3111
3112     i = bank_number(mode);
3113     env->regs[13] = env->banked_r13[i];
3114     env->regs[14] = env->banked_r14[i];
3115     env->spsr = env->banked_spsr[i];
3116 }
3117
3118 static void v7m_push(CPUARMState *env, uint32_t val)
3119 {
3120     CPUState *cs = CPU(arm_env_get_cpu(env));
3121
3122     env->regs[13] -= 4;
3123     stl_phys(cs->as, env->regs[13], val);
3124 }
3125
3126 static uint32_t v7m_pop(CPUARMState *env)
3127 {
3128     CPUState *cs = CPU(arm_env_get_cpu(env));
3129     uint32_t val;
3130
3131     val = ldl_phys(cs->as, env->regs[13]);
3132     env->regs[13] += 4;
3133     return val;
3134 }
3135
3136 /* Switch to V7M main or process stack pointer.  */
3137 static void switch_v7m_sp(CPUARMState *env, int process)
3138 {
3139     uint32_t tmp;
3140     if (env->v7m.current_sp != process) {
3141         tmp = env->v7m.other_sp;
3142         env->v7m.other_sp = env->regs[13];
3143         env->regs[13] = tmp;
3144         env->v7m.current_sp = process;
3145     }
3146 }
3147
3148 static void do_v7m_exception_exit(CPUARMState *env)
3149 {
3150     uint32_t type;
3151     uint32_t xpsr;
3152
3153     type = env->regs[15];
3154     if (env->v7m.exception != 0)
3155         armv7m_nvic_complete_irq(env->nvic, env->v7m.exception);
3156
3157     /* Switch to the target stack.  */
3158     switch_v7m_sp(env, (type & 4) != 0);
3159     /* Pop registers.  */
3160     env->regs[0] = v7m_pop(env);
3161     env->regs[1] = v7m_pop(env);
3162     env->regs[2] = v7m_pop(env);
3163     env->regs[3] = v7m_pop(env);
3164     env->regs[12] = v7m_pop(env);
3165     env->regs[14] = v7m_pop(env);
3166     env->regs[15] = v7m_pop(env);
3167     xpsr = v7m_pop(env);
3168     xpsr_write(env, xpsr, 0xfffffdff);
3169     /* Undo stack alignment.  */
3170     if (xpsr & 0x200)
3171         env->regs[13] |= 4;
3172     /* ??? The exception return type specifies Thread/Handler mode.  However
3173        this is also implied by the xPSR value. Not sure what to do
3174        if there is a mismatch.  */
3175     /* ??? Likewise for mismatches between the CONTROL register and the stack
3176        pointer.  */
3177 }
3178
3179 void arm_v7m_cpu_do_interrupt(CPUState *cs)
3180 {
3181     ARMCPU *cpu = ARM_CPU(cs);
3182     CPUARMState *env = &cpu->env;
3183     uint32_t xpsr = xpsr_read(env);
3184     uint32_t lr;
3185     uint32_t addr;
3186
3187     arm_log_exception(cs->exception_index);
3188
3189     lr = 0xfffffff1;
3190     if (env->v7m.current_sp)
3191         lr |= 4;
3192     if (env->v7m.exception == 0)
3193         lr |= 8;
3194
3195     /* For exceptions we just mark as pending on the NVIC, and let that
3196        handle it.  */
3197     /* TODO: Need to escalate if the current priority is higher than the
3198        one we're raising.  */
3199     switch (cs->exception_index) {
3200     case EXCP_UDEF:
3201         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_USAGE);
3202         return;
3203     case EXCP_SWI:
3204         /* The PC already points to the next instruction.  */
3205         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_SVC);
3206         return;
3207     case EXCP_PREFETCH_ABORT:
3208     case EXCP_DATA_ABORT:
3209         /* TODO: if we implemented the MPU registers, this is where we
3210          * should set the MMFAR, etc from exception.fsr and exception.vaddress.
3211          */
3212         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_MEM);
3213         return;
3214     case EXCP_BKPT:
3215         if (semihosting_enabled) {
3216             int nr;
3217             nr = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
3218             if (nr == 0xab) {
3219                 env->regs[15] += 2;
3220                 env->regs[0] = do_arm_semihosting(env);
3221                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3222                 return;
3223             }
3224         }
3225         armv7m_nvic_set_pending(env->nvic, ARMV7M_EXCP_DEBUG);
3226         return;
3227     case EXCP_IRQ:
3228         env->v7m.exception = armv7m_nvic_acknowledge_irq(env->nvic);
3229         break;
3230     case EXCP_EXCEPTION_EXIT:
3231         do_v7m_exception_exit(env);
3232         return;
3233     default:
3234         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
3235         return; /* Never happens.  Keep compiler happy.  */
3236     }
3237
3238     /* Align stack pointer.  */
3239     /* ??? Should only do this if Configuration Control Register
3240        STACKALIGN bit is set.  */
3241     if (env->regs[13] & 4) {
3242         env->regs[13] -= 4;
3243         xpsr |= 0x200;
3244     }
3245     /* Switch to the handler mode.  */
3246     v7m_push(env, xpsr);
3247     v7m_push(env, env->regs[15]);
3248     v7m_push(env, env->regs[14]);
3249     v7m_push(env, env->regs[12]);
3250     v7m_push(env, env->regs[3]);
3251     v7m_push(env, env->regs[2]);
3252     v7m_push(env, env->regs[1]);
3253     v7m_push(env, env->regs[0]);
3254     switch_v7m_sp(env, 0);
3255     /* Clear IT bits */
3256     env->condexec_bits = 0;
3257     env->regs[14] = lr;
3258     addr = ldl_phys(cs->as, env->v7m.vecbase + env->v7m.exception * 4);
3259     env->regs[15] = addr & 0xfffffffe;
3260     env->thumb = addr & 1;
3261 }
3262
3263 /* Handle a CPU exception.  */
3264 void arm_cpu_do_interrupt(CPUState *cs)
3265 {
3266     ARMCPU *cpu = ARM_CPU(cs);
3267     CPUARMState *env = &cpu->env;
3268     uint32_t addr;
3269     uint32_t mask;
3270     int new_mode;
3271     uint32_t offset;
3272
3273     assert(!IS_M(env));
3274
3275     arm_log_exception(cs->exception_index);
3276
3277     /* TODO: Vectored interrupt controller.  */
3278     switch (cs->exception_index) {
3279     case EXCP_UDEF:
3280         new_mode = ARM_CPU_MODE_UND;
3281         addr = 0x04;
3282         mask = CPSR_I;
3283         if (env->thumb)
3284             offset = 2;
3285         else
3286             offset = 4;
3287         break;
3288     case EXCP_SWI:
3289         if (semihosting_enabled) {
3290             /* Check for semihosting interrupt.  */
3291             if (env->thumb) {
3292                 mask = arm_lduw_code(env, env->regs[15] - 2, env->bswap_code)
3293                     & 0xff;
3294             } else {
3295                 mask = arm_ldl_code(env, env->regs[15] - 4, env->bswap_code)
3296                     & 0xffffff;
3297             }
3298             /* Only intercept calls from privileged modes, to provide some
3299                semblance of security.  */
3300             if (((mask == 0x123456 && !env->thumb)
3301                     || (mask == 0xab && env->thumb))
3302                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
3303                 env->regs[0] = do_arm_semihosting(env);
3304                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3305                 return;
3306             }
3307         }
3308         new_mode = ARM_CPU_MODE_SVC;
3309         addr = 0x08;
3310         mask = CPSR_I;
3311         /* The PC already points to the next instruction.  */
3312         offset = 0;
3313         break;
3314     case EXCP_BKPT:
3315         /* See if this is a semihosting syscall.  */
3316         if (env->thumb && semihosting_enabled) {
3317             mask = arm_lduw_code(env, env->regs[15], env->bswap_code) & 0xff;
3318             if (mask == 0xab
3319                   && (env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) {
3320                 env->regs[15] += 2;
3321                 env->regs[0] = do_arm_semihosting(env);
3322                 qemu_log_mask(CPU_LOG_INT, "...handled as semihosting call\n");
3323                 return;
3324             }
3325         }
3326         env->exception.fsr = 2;
3327         /* Fall through to prefetch abort.  */
3328     case EXCP_PREFETCH_ABORT:
3329         env->cp15.ifsr_el2 = env->exception.fsr;
3330         env->cp15.far_el1 = deposit64(env->cp15.far_el1, 32, 32,
3331                                       env->exception.vaddress);
3332         qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
3333                       env->cp15.ifsr_el2, (uint32_t)env->exception.vaddress);
3334         new_mode = ARM_CPU_MODE_ABT;
3335         addr = 0x0c;
3336         mask = CPSR_A | CPSR_I;
3337         offset = 4;
3338         break;
3339     case EXCP_DATA_ABORT:
3340         env->cp15.esr_el1 = env->exception.fsr;
3341         env->cp15.far_el1 = deposit64(env->cp15.far_el1, 0, 32,
3342                                       env->exception.vaddress);
3343         qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
3344                       (uint32_t)env->cp15.esr_el1,
3345                       (uint32_t)env->exception.vaddress);
3346         new_mode = ARM_CPU_MODE_ABT;
3347         addr = 0x10;
3348         mask = CPSR_A | CPSR_I;
3349         offset = 8;
3350         break;
3351     case EXCP_IRQ:
3352         new_mode = ARM_CPU_MODE_IRQ;
3353         addr = 0x18;
3354         /* Disable IRQ and imprecise data aborts.  */
3355         mask = CPSR_A | CPSR_I;
3356         offset = 4;
3357         break;
3358     case EXCP_FIQ:
3359         new_mode = ARM_CPU_MODE_FIQ;
3360         addr = 0x1c;
3361         /* Disable FIQ, IRQ and imprecise data aborts.  */
3362         mask = CPSR_A | CPSR_I | CPSR_F;
3363         offset = 4;
3364         break;
3365     default:
3366         cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
3367         return; /* Never happens.  Keep compiler happy.  */
3368     }
3369     /* High vectors.  */
3370     if (env->cp15.c1_sys & SCTLR_V) {
3371         /* when enabled, base address cannot be remapped.  */
3372         addr += 0xffff0000;
3373     } else {
3374         /* ARM v7 architectures provide a vector base address register to remap
3375          * the interrupt vector table.
3376          * This register is only followed in non-monitor mode, and has a secure
3377          * and un-secure copy. Since the cpu is always in a un-secure operation
3378          * and is never in monitor mode this feature is always active.
3379          * Note: only bits 31:5 are valid.
3380          */
3381         addr += env->cp15.c12_vbar;
3382     }
3383     switch_mode (env, new_mode);
3384     env->spsr = cpsr_read(env);
3385     /* Clear IT bits.  */
3386     env->condexec_bits = 0;
3387     /* Switch to the new mode, and to the correct instruction set.  */
3388     env->uncached_cpsr = (env->uncached_cpsr & ~CPSR_M) | new_mode;
3389     env->daif |= mask;
3390     /* this is a lie, as the was no c1_sys on V4T/V5, but who cares
3391      * and we should just guard the thumb mode on V4 */
3392     if (arm_feature(env, ARM_FEATURE_V4T)) {
3393         env->thumb = (env->cp15.c1_sys & SCTLR_TE) != 0;
3394     }
3395     env->regs[14] = env->regs[15] + offset;
3396     env->regs[15] = addr;
3397     cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
3398 }
3399
3400 /* Check section/page access permissions.
3401    Returns the page protection flags, or zero if the access is not
3402    permitted.  */
3403 static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
3404                            int access_type, int is_user)
3405 {
3406   int prot_ro;
3407
3408   if (domain_prot == 3) {
3409     return PAGE_READ | PAGE_WRITE;
3410   }
3411
3412   if (access_type == 1)
3413       prot_ro = 0;
3414   else
3415       prot_ro = PAGE_READ;
3416
3417   switch (ap) {
3418   case 0:
3419       if (arm_feature(env, ARM_FEATURE_V7)) {
3420           return 0;
3421       }
3422       if (access_type == 1)
3423           return 0;
3424       switch (env->cp15.c1_sys & (SCTLR_S | SCTLR_R)) {
3425       case SCTLR_S:
3426           return is_user ? 0 : PAGE_READ;
3427       case SCTLR_R:
3428           return PAGE_READ;
3429       default:
3430           return 0;
3431       }
3432   case 1:
3433       return is_user ? 0 : PAGE_READ | PAGE_WRITE;
3434   case 2:
3435       if (is_user)
3436           return prot_ro;
3437       else
3438           return PAGE_READ | PAGE_WRITE;
3439   case 3:
3440       return PAGE_READ | PAGE_WRITE;
3441   case 4: /* Reserved.  */
3442       return 0;
3443   case 5:
3444       return is_user ? 0 : prot_ro;
3445   case 6:
3446       return prot_ro;
3447   case 7:
3448       if (!arm_feature (env, ARM_FEATURE_V6K))
3449           return 0;
3450       return prot_ro;
3451   default:
3452       abort();
3453   }
3454 }
3455
3456 static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
3457 {
3458     uint32_t table;
3459
3460     if (address & env->cp15.c2_mask)
3461         table = env->cp15.ttbr1_el1 & 0xffffc000;
3462     else
3463         table = env->cp15.ttbr0_el1 & env->cp15.c2_base_mask;
3464
3465     table |= (address >> 18) & 0x3ffc;
3466     return table;
3467 }
3468
3469 static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
3470                             int is_user, hwaddr *phys_ptr,
3471                             int *prot, target_ulong *page_size)
3472 {
3473     CPUState *cs = CPU(arm_env_get_cpu(env));
3474     int code;
3475     uint32_t table;
3476     uint32_t desc;
3477     int type;
3478     int ap;
3479     int domain;
3480     int domain_prot;
3481     hwaddr phys_addr;
3482
3483     /* Pagetable walk.  */
3484     /* Lookup l1 descriptor.  */
3485     table = get_level1_table_address(env, address);
3486     desc = ldl_phys(cs->as, table);
3487     type = (desc & 3);
3488     domain = (desc >> 5) & 0x0f;
3489     domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
3490     if (type == 0) {
3491         /* Section translation fault.  */
3492         code = 5;
3493         goto do_fault;
3494     }
3495     if (domain_prot == 0 || domain_prot == 2) {
3496         if (type == 2)
3497             code = 9; /* Section domain fault.  */
3498         else
3499             code = 11; /* Page domain fault.  */
3500         goto do_fault;
3501     }
3502     if (type == 2) {
3503         /* 1Mb section.  */
3504         phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
3505         ap = (desc >> 10) & 3;
3506         code = 13;
3507         *page_size = 1024 * 1024;
3508     } else {
3509         /* Lookup l2 entry.  */
3510         if (type == 1) {
3511             /* Coarse pagetable.  */
3512             table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
3513         } else {
3514             /* Fine pagetable.  */
3515             table = (desc & 0xfffff000) | ((address >> 8) & 0xffc);
3516         }
3517         desc = ldl_phys(cs->as, table);
3518         switch (desc & 3) {
3519         case 0: /* Page translation fault.  */
3520             code = 7;
3521             goto do_fault;
3522         case 1: /* 64k page.  */
3523             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
3524             ap = (desc >> (4 + ((address >> 13) & 6))) & 3;
3525             *page_size = 0x10000;
3526             break;
3527         case 2: /* 4k page.  */
3528             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3529             ap = (desc >> (4 + ((address >> 9) & 6))) & 3;
3530             *page_size = 0x1000;
3531             break;
3532         case 3: /* 1k page.  */
3533             if (type == 1) {
3534                 if (arm_feature(env, ARM_FEATURE_XSCALE)) {
3535                     phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3536                 } else {
3537                     /* Page translation fault.  */
3538                     code = 7;
3539                     goto do_fault;
3540                 }
3541             } else {
3542                 phys_addr = (desc & 0xfffffc00) | (address & 0x3ff);
3543             }
3544             ap = (desc >> 4) & 3;
3545             *page_size = 0x400;
3546             break;
3547         default:
3548             /* Never happens, but compiler isn't smart enough to tell.  */
3549             abort();
3550         }
3551         code = 15;
3552     }
3553     *prot = check_ap(env, ap, domain_prot, access_type, is_user);
3554     if (!*prot) {
3555         /* Access permission fault.  */
3556         goto do_fault;
3557     }
3558     *prot |= PAGE_EXEC;
3559     *phys_ptr = phys_addr;
3560     return 0;
3561 do_fault:
3562     return code | (domain << 4);
3563 }
3564
3565 static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
3566                             int is_user, hwaddr *phys_ptr,
3567                             int *prot, target_ulong *page_size)
3568 {
3569     CPUState *cs = CPU(arm_env_get_cpu(env));
3570     int code;
3571     uint32_t table;
3572     uint32_t desc;
3573     uint32_t xn;
3574     uint32_t pxn = 0;
3575     int type;
3576     int ap;
3577     int domain = 0;
3578     int domain_prot;
3579     hwaddr phys_addr;
3580
3581     /* Pagetable walk.  */
3582     /* Lookup l1 descriptor.  */
3583     table = get_level1_table_address(env, address);
3584     desc = ldl_phys(cs->as, table);
3585     type = (desc & 3);
3586     if (type == 0 || (type == 3 && !arm_feature(env, ARM_FEATURE_PXN))) {
3587         /* Section translation fault, or attempt to use the encoding
3588          * which is Reserved on implementations without PXN.
3589          */
3590         code = 5;
3591         goto do_fault;
3592     }
3593     if ((type == 1) || !(desc & (1 << 18))) {
3594         /* Page or Section.  */
3595         domain = (desc >> 5) & 0x0f;
3596     }
3597     domain_prot = (env->cp15.c3 >> (domain * 2)) & 3;
3598     if (domain_prot == 0 || domain_prot == 2) {
3599         if (type != 1) {
3600             code = 9; /* Section domain fault.  */
3601         } else {
3602             code = 11; /* Page domain fault.  */
3603         }
3604         goto do_fault;
3605     }
3606     if (type != 1) {
3607         if (desc & (1 << 18)) {
3608             /* Supersection.  */
3609             phys_addr = (desc & 0xff000000) | (address & 0x00ffffff);
3610             *page_size = 0x1000000;
3611         } else {
3612             /* Section.  */
3613             phys_addr = (desc & 0xfff00000) | (address & 0x000fffff);
3614             *page_size = 0x100000;
3615         }
3616         ap = ((desc >> 10) & 3) | ((desc >> 13) & 4);
3617         xn = desc & (1 << 4);
3618         pxn = desc & 1;
3619         code = 13;
3620     } else {
3621         if (arm_feature(env, ARM_FEATURE_PXN)) {
3622             pxn = (desc >> 2) & 1;
3623         }
3624         /* Lookup l2 entry.  */
3625         table = (desc & 0xfffffc00) | ((address >> 10) & 0x3fc);
3626         desc = ldl_phys(cs->as, table);
3627         ap = ((desc >> 4) & 3) | ((desc >> 7) & 4);
3628         switch (desc & 3) {
3629         case 0: /* Page translation fault.  */
3630             code = 7;
3631             goto do_fault;
3632         case 1: /* 64k page.  */
3633             phys_addr = (desc & 0xffff0000) | (address & 0xffff);
3634             xn = desc & (1 << 15);
3635             *page_size = 0x10000;
3636             break;
3637         case 2: case 3: /* 4k page.  */
3638             phys_addr = (desc & 0xfffff000) | (address & 0xfff);
3639             xn = desc & 1;
3640             *page_size = 0x1000;
3641             break;
3642         default:
3643             /* Never happens, but compiler isn't smart enough to tell.  */
3644             abort();
3645         }
3646         code = 15;
3647     }
3648     if (domain_prot == 3) {
3649         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3650     } else {
3651         if (pxn && !is_user) {
3652             xn = 1;
3653         }
3654         if (xn && access_type == 2)
3655             goto do_fault;
3656
3657         /* The simplified model uses AP[0] as an access control bit.  */
3658         if ((env->cp15.c1_sys & SCTLR_AFE) && (ap & 1) == 0) {
3659             /* Access flag fault.  */
3660             code = (code == 15) ? 6 : 3;
3661             goto do_fault;
3662         }
3663         *prot = check_ap(env, ap, domain_prot, access_type, is_user);
3664         if (!*prot) {
3665             /* Access permission fault.  */
3666             goto do_fault;
3667         }
3668         if (!xn) {
3669             *prot |= PAGE_EXEC;
3670         }
3671     }
3672     *phys_ptr = phys_addr;
3673     return 0;
3674 do_fault:
3675     return code | (domain << 4);
3676 }
3677
3678 /* Fault type for long-descriptor MMU fault reporting; this corresponds
3679  * to bits [5..2] in the STATUS field in long-format DFSR/IFSR.
3680  */
3681 typedef enum {
3682     translation_fault = 1,
3683     access_fault = 2,
3684     permission_fault = 3,
3685 } MMUFaultType;
3686
3687 static int get_phys_addr_lpae(CPUARMState *env, target_ulong address,
3688                               int access_type, int is_user,
3689                               hwaddr *phys_ptr, int *prot,
3690                               target_ulong *page_size_ptr)
3691 {
3692     CPUState *cs = CPU(arm_env_get_cpu(env));
3693     /* Read an LPAE long-descriptor translation table. */
3694     MMUFaultType fault_type = translation_fault;
3695     uint32_t level = 1;
3696     uint32_t epd;
3697     int32_t tsz;
3698     uint32_t tg;
3699     uint64_t ttbr;
3700     int ttbr_select;
3701     hwaddr descaddr, descmask;
3702     uint32_t tableattrs;
3703     target_ulong page_size;
3704     uint32_t attrs;
3705     int32_t granule_sz = 9;
3706     int32_t va_size = 32;
3707     int32_t tbi = 0;
3708
3709     if (arm_el_is_aa64(env, 1)) {
3710         va_size = 64;
3711         if (extract64(address, 55, 1))
3712             tbi = extract64(env->cp15.c2_control, 38, 1);
3713         else
3714             tbi = extract64(env->cp15.c2_control, 37, 1);
3715         tbi *= 8;
3716     }
3717
3718     /* Determine whether this address is in the region controlled by
3719      * TTBR0 or TTBR1 (or if it is in neither region and should fault).
3720      * This is a Non-secure PL0/1 stage 1 translation, so controlled by
3721      * TTBCR/TTBR0/TTBR1 in accordance with ARM ARM DDI0406C table B-32:
3722      */
3723     uint32_t t0sz = extract32(env->cp15.c2_control, 0, 6);
3724     if (arm_el_is_aa64(env, 1)) {
3725         t0sz = MIN(t0sz, 39);
3726         t0sz = MAX(t0sz, 16);
3727     }
3728     uint32_t t1sz = extract32(env->cp15.c2_control, 16, 6);
3729     if (arm_el_is_aa64(env, 1)) {
3730         t1sz = MIN(t1sz, 39);
3731         t1sz = MAX(t1sz, 16);
3732     }
3733     if (t0sz && !extract64(address, va_size - t0sz, t0sz - tbi)) {
3734         /* there is a ttbr0 region and we are in it (high bits all zero) */
3735         ttbr_select = 0;
3736     } else if (t1sz && !extract64(~address, va_size - t1sz, t1sz - tbi)) {
3737         /* there is a ttbr1 region and we are in it (high bits all one) */
3738         ttbr_select = 1;
3739     } else if (!t0sz) {
3740         /* ttbr0 region is "everything not in the ttbr1 region" */
3741         ttbr_select = 0;
3742     } else if (!t1sz) {
3743         /* ttbr1 region is "everything not in the ttbr0 region" */
3744         ttbr_select = 1;
3745     } else {
3746         /* in the gap between the two regions, this is a Translation fault */
3747         fault_type = translation_fault;
3748         goto do_fault;
3749     }
3750
3751     /* Note that QEMU ignores shareability and cacheability attributes,
3752      * so we don't need to do anything with the SH, ORGN, IRGN fields
3753      * in the TTBCR.  Similarly, TTBCR:A1 selects whether we get the
3754      * ASID from TTBR0 or TTBR1, but QEMU's TLB doesn't currently
3755      * implement any ASID-like capability so we can ignore it (instead
3756      * we will always flush the TLB any time the ASID is changed).
3757      */
3758     if (ttbr_select == 0) {
3759         ttbr = env->cp15.ttbr0_el1;
3760         epd = extract32(env->cp15.c2_control, 7, 1);
3761         tsz = t0sz;
3762
3763         tg = extract32(env->cp15.c2_control, 14, 2);
3764         if (tg == 1) { /* 64KB pages */
3765             granule_sz = 13;
3766         }
3767         if (tg == 2) { /* 16KB pages */
3768             granule_sz = 11;
3769         }
3770     } else {
3771         ttbr = env->cp15.ttbr1_el1;
3772         epd = extract32(env->cp15.c2_control, 23, 1);
3773         tsz = t1sz;
3774
3775         tg = extract32(env->cp15.c2_control, 30, 2);
3776         if (tg == 3)  { /* 64KB pages */
3777             granule_sz = 13;
3778         }
3779         if (tg == 1) { /* 16KB pages */
3780             granule_sz = 11;
3781         }
3782     }
3783
3784     if (epd) {
3785         /* Translation table walk disabled => Translation fault on TLB miss */
3786         goto do_fault;
3787     }
3788
3789     /* The starting level depends on the virtual address size which can be
3790      * up to 48-bits and the translation granule size.
3791      */
3792     if ((va_size - tsz) > (granule_sz * 4 + 3)) {
3793         level = 0;
3794     } else if ((va_size - tsz) > (granule_sz * 3 + 3)) {
3795         level = 1;
3796     } else {
3797         level = 2;
3798     }
3799
3800     /* Clear the vaddr bits which aren't part of the within-region address,
3801      * so that we don't have to special case things when calculating the
3802      * first descriptor address.
3803      */
3804     if (tsz) {
3805         address &= (1ULL << (va_size - tsz)) - 1;
3806     }
3807
3808     descmask = (1ULL << (granule_sz + 3)) - 1;
3809
3810     /* Now we can extract the actual base address from the TTBR */
3811     descaddr = extract64(ttbr, 0, 48);
3812     descaddr &= ~((1ULL << (va_size - tsz - (granule_sz * (4 - level)))) - 1);
3813
3814     tableattrs = 0;
3815     for (;;) {
3816         uint64_t descriptor;
3817
3818         descaddr |= (address >> (granule_sz * (4 - level))) & descmask;
3819         descaddr &= ~7ULL;
3820         descriptor = ldq_phys(cs->as, descaddr);
3821         if (!(descriptor & 1) ||
3822             (!(descriptor & 2) && (level == 3))) {
3823             /* Invalid, or the Reserved level 3 encoding */
3824             goto do_fault;
3825         }
3826         descaddr = descriptor & 0xfffffff000ULL;
3827
3828         if ((descriptor & 2) && (level < 3)) {
3829             /* Table entry. The top five bits are attributes which  may
3830              * propagate down through lower levels of the table (and
3831              * which are all arranged so that 0 means "no effect", so
3832              * we can gather them up by ORing in the bits at each level).
3833              */
3834             tableattrs |= extract64(descriptor, 59, 5);
3835             level++;
3836             continue;
3837         }
3838         /* Block entry at level 1 or 2, or page entry at level 3.
3839          * These are basically the same thing, although the number
3840          * of bits we pull in from the vaddr varies.
3841          */
3842         page_size = (1 << ((granule_sz * (4 - level)) + 3));
3843         descaddr |= (address & (page_size - 1));
3844         /* Extract attributes from the descriptor and merge with table attrs */
3845         if (arm_feature(env, ARM_FEATURE_V8)) {
3846             attrs = extract64(descriptor, 2, 10)
3847                 | (extract64(descriptor, 53, 11) << 10);
3848         } else {
3849             attrs = extract64(descriptor, 2, 10)
3850                 | (extract64(descriptor, 52, 12) << 10);
3851         }
3852         attrs |= extract32(tableattrs, 0, 2) << 11; /* XN, PXN */
3853         attrs |= extract32(tableattrs, 3, 1) << 5; /* APTable[1] => AP[2] */
3854         /* The sense of AP[1] vs APTable[0] is reversed, as APTable[0] == 1
3855          * means "force PL1 access only", which means forcing AP[1] to 0.
3856          */
3857         if (extract32(tableattrs, 2, 1)) {
3858             attrs &= ~(1 << 4);
3859         }
3860         /* Since we're always in the Non-secure state, NSTable is ignored. */
3861         break;
3862     }
3863     /* Here descaddr is the final physical address, and attributes
3864      * are all in attrs.
3865      */
3866     fault_type = access_fault;
3867     if ((attrs & (1 << 8)) == 0) {
3868         /* Access flag */
3869         goto do_fault;
3870     }
3871     fault_type = permission_fault;
3872     if (is_user && !(attrs & (1 << 4))) {
3873         /* Unprivileged access not enabled */
3874         goto do_fault;
3875     }
3876     *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3877     if (attrs & (1 << 12) || (!is_user && (attrs & (1 << 11)))) {
3878         /* XN or PXN */
3879         if (access_type == 2) {
3880             goto do_fault;
3881         }
3882         *prot &= ~PAGE_EXEC;
3883     }
3884     if (attrs & (1 << 5)) {
3885         /* Write access forbidden */
3886         if (access_type == 1) {
3887             goto do_fault;
3888         }
3889         *prot &= ~PAGE_WRITE;
3890     }
3891
3892     *phys_ptr = descaddr;
3893     *page_size_ptr = page_size;
3894     return 0;
3895
3896 do_fault:
3897     /* Long-descriptor format IFSR/DFSR value */
3898     return (1 << 9) | (fault_type << 2) | level;
3899 }
3900
3901 static int get_phys_addr_mpu(CPUARMState *env, uint32_t address,
3902                              int access_type, int is_user,
3903                              hwaddr *phys_ptr, int *prot)
3904 {
3905     int n;
3906     uint32_t mask;
3907     uint32_t base;
3908
3909     *phys_ptr = address;
3910     for (n = 7; n >= 0; n--) {
3911         base = env->cp15.c6_region[n];
3912         if ((base & 1) == 0)
3913             continue;
3914         mask = 1 << ((base >> 1) & 0x1f);
3915         /* Keep this shift separate from the above to avoid an
3916            (undefined) << 32.  */
3917         mask = (mask << 1) - 1;
3918         if (((base ^ address) & ~mask) == 0)
3919             break;
3920     }
3921     if (n < 0)
3922         return 2;
3923
3924     if (access_type == 2) {
3925         mask = env->cp15.pmsav5_insn_ap;
3926     } else {
3927         mask = env->cp15.pmsav5_data_ap;
3928     }
3929     mask = (mask >> (n * 4)) & 0xf;
3930     switch (mask) {
3931     case 0:
3932         return 1;
3933     case 1:
3934         if (is_user)
3935           return 1;
3936         *prot = PAGE_READ | PAGE_WRITE;
3937         break;
3938     case 2:
3939         *prot = PAGE_READ;
3940         if (!is_user)
3941             *prot |= PAGE_WRITE;
3942         break;
3943     case 3:
3944         *prot = PAGE_READ | PAGE_WRITE;
3945         break;
3946     case 5:
3947         if (is_user)
3948             return 1;
3949         *prot = PAGE_READ;
3950         break;
3951     case 6:
3952         *prot = PAGE_READ;
3953         break;
3954     default:
3955         /* Bad permission.  */
3956         return 1;
3957     }
3958     *prot |= PAGE_EXEC;
3959     return 0;
3960 }
3961
3962 /* get_phys_addr - get the physical address for this virtual address
3963  *
3964  * Find the physical address corresponding to the given virtual address,
3965  * by doing a translation table walk on MMU based systems or using the
3966  * MPU state on MPU based systems.
3967  *
3968  * Returns 0 if the translation was successful. Otherwise, phys_ptr,
3969  * prot and page_size are not filled in, and the return value provides
3970  * information on why the translation aborted, in the format of a
3971  * DFSR/IFSR fault register, with the following caveats:
3972  *  * we honour the short vs long DFSR format differences.
3973  *  * the WnR bit is never set (the caller must do this).
3974  *  * for MPU based systems we don't bother to return a full FSR format
3975  *    value.
3976  *
3977  * @env: CPUARMState
3978  * @address: virtual address to get physical address for
3979  * @access_type: 0 for read, 1 for write, 2 for execute
3980  * @is_user: 0 for privileged access, 1 for user
3981  * @phys_ptr: set to the physical address corresponding to the virtual address
3982  * @prot: set to the permissions for the page containing phys_ptr
3983  * @page_size: set to the size of the page containing phys_ptr
3984  */
3985 static inline int get_phys_addr(CPUARMState *env, target_ulong address,
3986                                 int access_type, int is_user,
3987                                 hwaddr *phys_ptr, int *prot,
3988                                 target_ulong *page_size)
3989 {
3990     /* Fast Context Switch Extension.  */
3991     if (address < 0x02000000)
3992         address += env->cp15.c13_fcse;
3993
3994     if ((env->cp15.c1_sys & SCTLR_M) == 0) {
3995         /* MMU/MPU disabled.  */
3996         *phys_ptr = address;
3997         *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
3998         *page_size = TARGET_PAGE_SIZE;
3999         return 0;
4000     } else if (arm_feature(env, ARM_FEATURE_MPU)) {
4001         *page_size = TARGET_PAGE_SIZE;
4002         return get_phys_addr_mpu(env, address, access_type, is_user, phys_ptr,
4003                                  prot);
4004     } else if (extended_addresses_enabled(env)) {
4005         return get_phys_addr_lpae(env, address, access_type, is_user, phys_ptr,
4006                                   prot, page_size);
4007     } else if (env->cp15.c1_sys & SCTLR_XP) {
4008         return get_phys_addr_v6(env, address, access_type, is_user, phys_ptr,
4009                                 prot, page_size);
4010     } else {
4011         return get_phys_addr_v5(env, address, access_type, is_user, phys_ptr,
4012                                 prot, page_size);
4013     }
4014 }
4015
4016 int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address,
4017                              int access_type, int mmu_idx)
4018 {
4019     ARMCPU *cpu = ARM_CPU(cs);
4020     CPUARMState *env = &cpu->env;
4021     hwaddr phys_addr;
4022     target_ulong page_size;
4023     int prot;
4024     int ret, is_user;
4025     uint32_t syn;
4026     bool same_el = (arm_current_pl(env) != 0);
4027
4028     is_user = mmu_idx == MMU_USER_IDX;
4029     ret = get_phys_addr(env, address, access_type, is_user, &phys_addr, &prot,
4030                         &page_size);
4031     if (ret == 0) {
4032         /* Map a single [sub]page.  */
4033         phys_addr &= ~(hwaddr)0x3ff;
4034         address &= ~(target_ulong)0x3ff;
4035         tlb_set_page(cs, address, phys_addr, prot, mmu_idx, page_size);
4036         return 0;
4037     }
4038
4039     /* AArch64 syndrome does not have an LPAE bit */
4040     syn = ret & ~(1 << 9);
4041
4042     /* For insn and data aborts we assume there is no instruction syndrome
4043      * information; this is always true for exceptions reported to EL1.
4044      */
4045     if (access_type == 2) {
4046         syn = syn_insn_abort(same_el, 0, 0, syn);
4047         cs->exception_index = EXCP_PREFETCH_ABORT;
4048     } else {
4049         syn = syn_data_abort(same_el, 0, 0, 0, access_type == 1, syn);
4050         if (access_type == 1 && arm_feature(env, ARM_FEATURE_V6)) {
4051             ret |= (1 << 11);
4052         }
4053         cs->exception_index = EXCP_DATA_ABORT;
4054     }
4055
4056     env->exception.syndrome = syn;
4057     env->exception.vaddress = address;
4058     env->exception.fsr = ret;
4059     return 1;
4060 }
4061
4062 hwaddr arm_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
4063 {
4064     ARMCPU *cpu = ARM_CPU(cs);
4065     hwaddr phys_addr;
4066     target_ulong page_size;
4067     int prot;
4068     int ret;
4069
4070     ret = get_phys_addr(&cpu->env, addr, 0, 0, &phys_addr, &prot, &page_size);
4071
4072     if (ret != 0) {
4073         return -1;
4074     }
4075
4076     return phys_addr;
4077 }
4078
4079 void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
4080 {
4081     if ((env->uncached_cpsr & CPSR_M) == mode) {
4082         env->regs[13] = val;
4083     } else {
4084         env->banked_r13[bank_number(mode)] = val;
4085     }
4086 }
4087
4088 uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
4089 {
4090     if ((env->uncached_cpsr & CPSR_M) == mode) {
4091         return env->regs[13];
4092     } else {
4093         return env->banked_r13[bank_number(mode)];
4094     }
4095 }
4096
4097 uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
4098 {
4099     ARMCPU *cpu = arm_env_get_cpu(env);
4100
4101     switch (reg) {
4102     case 0: /* APSR */
4103         return xpsr_read(env) & 0xf8000000;
4104     case 1: /* IAPSR */
4105         return xpsr_read(env) & 0xf80001ff;
4106     case 2: /* EAPSR */
4107         return xpsr_read(env) & 0xff00fc00;
4108     case 3: /* xPSR */
4109         return xpsr_read(env) & 0xff00fdff;
4110     case 5: /* IPSR */
4111         return xpsr_read(env) & 0x000001ff;
4112     case 6: /* EPSR */
4113         return xpsr_read(env) & 0x0700fc00;
4114     case 7: /* IEPSR */
4115         return xpsr_read(env) & 0x0700edff;
4116     case 8: /* MSP */
4117         return env->v7m.current_sp ? env->v7m.other_sp : env->regs[13];
4118     case 9: /* PSP */
4119         return env->v7m.current_sp ? env->regs[13] : env->v7m.other_sp;
4120     case 16: /* PRIMASK */
4121         return (env->daif & PSTATE_I) != 0;
4122     case 17: /* BASEPRI */
4123     case 18: /* BASEPRI_MAX */
4124         return env->v7m.basepri;
4125     case 19: /* FAULTMASK */
4126         return (env->daif & PSTATE_F) != 0;
4127     case 20: /* CONTROL */
4128         return env->v7m.control;
4129     default:
4130         /* ??? For debugging only.  */
4131         cpu_abort(CPU(cpu), "Unimplemented system register read (%d)\n", reg);
4132         return 0;
4133     }
4134 }
4135
4136 void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
4137 {
4138     ARMCPU *cpu = arm_env_get_cpu(env);
4139
4140     switch (reg) {
4141     case 0: /* APSR */
4142         xpsr_write(env, val, 0xf8000000);
4143         break;
4144     case 1: /* IAPSR */
4145         xpsr_write(env, val, 0xf8000000);
4146         break;
4147     case 2: /* EAPSR */
4148         xpsr_write(env, val, 0xfe00fc00);
4149         break;
4150     case 3: /* xPSR */
4151         xpsr_write(env, val, 0xfe00fc00);
4152         break;
4153     case 5: /* IPSR */
4154         /* IPSR bits are readonly.  */
4155         break;
4156     case 6: /* EPSR */
4157         xpsr_write(env, val, 0x0600fc00);
4158         break;
4159     case 7: /* IEPSR */
4160         xpsr_write(env, val, 0x0600fc00);
4161         break;
4162     case 8: /* MSP */
4163         if (env->v7m.current_sp)
4164             env->v7m.other_sp = val;
4165         else
4166             env->regs[13] = val;
4167         break;
4168     case 9: /* PSP */
4169         if (env->v7m.current_sp)
4170             env->regs[13] = val;
4171         else
4172             env->v7m.other_sp = val;
4173         break;
4174     case 16: /* PRIMASK */
4175         if (val & 1) {
4176             env->daif |= PSTATE_I;
4177         } else {
4178             env->daif &= ~PSTATE_I;
4179         }
4180         break;
4181     case 17: /* BASEPRI */
4182         env->v7m.basepri = val & 0xff;
4183         break;
4184     case 18: /* BASEPRI_MAX */
4185         val &= 0xff;
4186         if (val != 0 && (val < env->v7m.basepri || env->v7m.basepri == 0))
4187             env->v7m.basepri = val;
4188         break;
4189     case 19: /* FAULTMASK */
4190         if (val & 1) {
4191             env->daif |= PSTATE_F;
4192         } else {
4193             env->daif &= ~PSTATE_F;
4194         }
4195         break;
4196     case 20: /* CONTROL */
4197         env->v7m.control = val & 3;
4198         switch_v7m_sp(env, (val & 2) != 0);
4199         break;
4200     default:
4201         /* ??? For debugging only.  */
4202         cpu_abort(CPU(cpu), "Unimplemented system register write (%d)\n", reg);
4203         return;
4204     }
4205 }
4206
4207 #endif
4208
4209 void HELPER(dc_zva)(CPUARMState *env, uint64_t vaddr_in)
4210 {
4211     /* Implement DC ZVA, which zeroes a fixed-length block of memory.
4212      * Note that we do not implement the (architecturally mandated)
4213      * alignment fault for attempts to use this on Device memory
4214      * (which matches the usual QEMU behaviour of not implementing either
4215      * alignment faults or any memory attribute handling).
4216      */
4217
4218     ARMCPU *cpu = arm_env_get_cpu(env);
4219     uint64_t blocklen = 4 << cpu->dcz_blocksize;
4220     uint64_t vaddr = vaddr_in & ~(blocklen - 1);
4221
4222 #ifndef CONFIG_USER_ONLY
4223     {
4224         /* Slightly awkwardly, QEMU's TARGET_PAGE_SIZE may be less than
4225          * the block size so we might have to do more than one TLB lookup.
4226          * We know that in fact for any v8 CPU the page size is at least 4K
4227          * and the block size must be 2K or less, but TARGET_PAGE_SIZE is only
4228          * 1K as an artefact of legacy v5 subpage support being present in the
4229          * same QEMU executable.
4230          */
4231         int maxidx = DIV_ROUND_UP(blocklen, TARGET_PAGE_SIZE);
4232         void *hostaddr[maxidx];
4233         int try, i;
4234
4235         for (try = 0; try < 2; try++) {
4236
4237             for (i = 0; i < maxidx; i++) {
4238                 hostaddr[i] = tlb_vaddr_to_host(env,
4239                                                 vaddr + TARGET_PAGE_SIZE * i,
4240                                                 1, cpu_mmu_index(env));
4241                 if (!hostaddr[i]) {
4242                     break;
4243                 }
4244             }
4245             if (i == maxidx) {
4246                 /* If it's all in the TLB it's fair game for just writing to;
4247                  * we know we don't need to update dirty status, etc.
4248                  */
4249                 for (i = 0; i < maxidx - 1; i++) {
4250                     memset(hostaddr[i], 0, TARGET_PAGE_SIZE);
4251                 }
4252                 memset(hostaddr[i], 0, blocklen - (i * TARGET_PAGE_SIZE));
4253                 return;
4254             }
4255             /* OK, try a store and see if we can populate the tlb. This
4256              * might cause an exception if the memory isn't writable,
4257              * in which case we will longjmp out of here. We must for
4258              * this purpose use the actual register value passed to us
4259              * so that we get the fault address right.
4260              */
4261             helper_ret_stb_mmu(env, vaddr_in, 0, cpu_mmu_index(env), GETRA());
4262             /* Now we can populate the other TLB entries, if any */
4263             for (i = 0; i < maxidx; i++) {
4264                 uint64_t va = vaddr + TARGET_PAGE_SIZE * i;
4265                 if (va != (vaddr_in & TARGET_PAGE_MASK)) {
4266                     helper_ret_stb_mmu(env, va, 0, cpu_mmu_index(env), GETRA());
4267                 }
4268             }
4269         }
4270
4271         /* Slow path (probably attempt to do this to an I/O device or
4272          * similar, or clearing of a block of code we have translations
4273          * cached for). Just do a series of byte writes as the architecture
4274          * demands. It's not worth trying to use a cpu_physical_memory_map(),
4275          * memset(), unmap() sequence here because:
4276          *  + we'd need to account for the blocksize being larger than a page
4277          *  + the direct-RAM access case is almost always going to be dealt
4278          *    with in the fastpath code above, so there's no speed benefit
4279          *  + we would have to deal with the map returning NULL because the
4280          *    bounce buffer was in use
4281          */
4282         for (i = 0; i < blocklen; i++) {
4283             helper_ret_stb_mmu(env, vaddr + i, 0, cpu_mmu_index(env), GETRA());
4284         }
4285     }
4286 #else
4287     memset(g2h(vaddr), 0, blocklen);
4288 #endif
4289 }
4290
4291 /* Note that signed overflow is undefined in C.  The following routines are
4292    careful to use unsigned types where modulo arithmetic is required.
4293    Failure to do so _will_ break on newer gcc.  */
4294
4295 /* Signed saturating arithmetic.  */
4296
4297 /* Perform 16-bit signed saturating addition.  */
4298 static inline uint16_t add16_sat(uint16_t a, uint16_t b)
4299 {
4300     uint16_t res;
4301
4302     res = a + b;
4303     if (((res ^ a) & 0x8000) && !((a ^ b) & 0x8000)) {
4304         if (a & 0x8000)
4305             res = 0x8000;
4306         else
4307             res = 0x7fff;
4308     }
4309     return res;
4310 }
4311
4312 /* Perform 8-bit signed saturating addition.  */
4313 static inline uint8_t add8_sat(uint8_t a, uint8_t b)
4314 {
4315     uint8_t res;
4316
4317     res = a + b;
4318     if (((res ^ a) & 0x80) && !((a ^ b) & 0x80)) {
4319         if (a & 0x80)
4320             res = 0x80;
4321         else
4322             res = 0x7f;
4323     }
4324     return res;
4325 }
4326
4327 /* Perform 16-bit signed saturating subtraction.  */
4328 static inline uint16_t sub16_sat(uint16_t a, uint16_t b)
4329 {
4330     uint16_t res;
4331
4332     res = a - b;
4333     if (((res ^ a) & 0x8000) && ((a ^ b) & 0x8000)) {
4334         if (a & 0x8000)
4335             res = 0x8000;
4336         else
4337             res = 0x7fff;
4338     }
4339     return res;
4340 }
4341
4342 /* Perform 8-bit signed saturating subtraction.  */
4343 static inline uint8_t sub8_sat(uint8_t a, uint8_t b)
4344 {
4345     uint8_t res;
4346
4347     res = a - b;
4348     if (((res ^ a) & 0x80) && ((a ^ b) & 0x80)) {
4349         if (a & 0x80)
4350             res = 0x80;
4351         else
4352             res = 0x7f;
4353     }
4354     return res;
4355 }
4356
4357 #define ADD16(a, b, n) RESULT(add16_sat(a, b), n, 16);
4358 #define SUB16(a, b, n) RESULT(sub16_sat(a, b), n, 16);
4359 #define ADD8(a, b, n)  RESULT(add8_sat(a, b), n, 8);
4360 #define SUB8(a, b, n)  RESULT(sub8_sat(a, b), n, 8);
4361 #define PFX q
4362
4363 #include "op_addsub.h"
4364
4365 /* Unsigned saturating arithmetic.  */
4366 static inline uint16_t add16_usat(uint16_t a, uint16_t b)
4367 {
4368     uint16_t res;
4369     res = a + b;
4370     if (res < a)
4371         res = 0xffff;
4372     return res;
4373 }
4374
4375 static inline uint16_t sub16_usat(uint16_t a, uint16_t b)
4376 {
4377     if (a > b)
4378         return a - b;
4379     else
4380         return 0;
4381 }
4382
4383 static inline uint8_t add8_usat(uint8_t a, uint8_t b)
4384 {
4385     uint8_t res;
4386     res = a + b;
4387     if (res < a)
4388         res = 0xff;
4389     return res;
4390 }
4391
4392 static inline uint8_t sub8_usat(uint8_t a, uint8_t b)
4393 {
4394     if (a > b)
4395         return a - b;
4396     else
4397         return 0;
4398 }
4399
4400 #define ADD16(a, b, n) RESULT(add16_usat(a, b), n, 16);
4401 #define SUB16(a, b, n) RESULT(sub16_usat(a, b), n, 16);
4402 #define ADD8(a, b, n)  RESULT(add8_usat(a, b), n, 8);
4403 #define SUB8(a, b, n)  RESULT(sub8_usat(a, b), n, 8);
4404 #define PFX uq
4405
4406 #include "op_addsub.h"
4407
4408 /* Signed modulo arithmetic.  */
4409 #define SARITH16(a, b, n, op) do { \
4410     int32_t sum; \
4411     sum = (int32_t)(int16_t)(a) op (int32_t)(int16_t)(b); \
4412     RESULT(sum, n, 16); \
4413     if (sum >= 0) \
4414         ge |= 3 << (n * 2); \
4415     } while(0)
4416
4417 #define SARITH8(a, b, n, op) do { \
4418     int32_t sum; \
4419     sum = (int32_t)(int8_t)(a) op (int32_t)(int8_t)(b); \
4420     RESULT(sum, n, 8); \
4421     if (sum >= 0) \
4422         ge |= 1 << n; \
4423     } while(0)
4424
4425
4426 #define ADD16(a, b, n) SARITH16(a, b, n, +)
4427 #define SUB16(a, b, n) SARITH16(a, b, n, -)
4428 #define ADD8(a, b, n)  SARITH8(a, b, n, +)
4429 #define SUB8(a, b, n)  SARITH8(a, b, n, -)
4430 #define PFX s
4431 #define ARITH_GE
4432
4433 #include "op_addsub.h"
4434
4435 /* Unsigned modulo arithmetic.  */
4436 #define ADD16(a, b, n) do { \
4437     uint32_t sum; \
4438     sum = (uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b); \
4439     RESULT(sum, n, 16); \
4440     if ((sum >> 16) == 1) \
4441         ge |= 3 << (n * 2); \
4442     } while(0)
4443
4444 #define ADD8(a, b, n) do { \
4445     uint32_t sum; \
4446     sum = (uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b); \
4447     RESULT(sum, n, 8); \
4448     if ((sum >> 8) == 1) \
4449         ge |= 1 << n; \
4450     } while(0)
4451
4452 #define SUB16(a, b, n) do { \
4453     uint32_t sum; \
4454     sum = (uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b); \
4455     RESULT(sum, n, 16); \
4456     if ((sum >> 16) == 0) \
4457         ge |= 3 << (n * 2); \
4458     } while(0)
4459
4460 #define SUB8(a, b, n) do { \
4461     uint32_t sum; \
4462     sum = (uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b); \
4463     RESULT(sum, n, 8); \
4464     if ((sum >> 8) == 0) \
4465         ge |= 1 << n; \
4466     } while(0)
4467
4468 #define PFX u
4469 #define ARITH_GE
4470
4471 #include "op_addsub.h"
4472
4473 /* Halved signed arithmetic.  */
4474 #define ADD16(a, b, n) \
4475   RESULT(((int32_t)(int16_t)(a) + (int32_t)(int16_t)(b)) >> 1, n, 16)
4476 #define SUB16(a, b, n) \
4477   RESULT(((int32_t)(int16_t)(a) - (int32_t)(int16_t)(b)) >> 1, n, 16)
4478 #define ADD8(a, b, n) \
4479   RESULT(((int32_t)(int8_t)(a) + (int32_t)(int8_t)(b)) >> 1, n, 8)
4480 #define SUB8(a, b, n) \
4481   RESULT(((int32_t)(int8_t)(a) - (int32_t)(int8_t)(b)) >> 1, n, 8)
4482 #define PFX sh
4483
4484 #include "op_addsub.h"
4485
4486 /* Halved unsigned arithmetic.  */
4487 #define ADD16(a, b, n) \
4488   RESULT(((uint32_t)(uint16_t)(a) + (uint32_t)(uint16_t)(b)) >> 1, n, 16)
4489 #define SUB16(a, b, n) \
4490   RESULT(((uint32_t)(uint16_t)(a) - (uint32_t)(uint16_t)(b)) >> 1, n, 16)
4491 #define ADD8(a, b, n) \
4492   RESULT(((uint32_t)(uint8_t)(a) + (uint32_t)(uint8_t)(b)) >> 1, n, 8)
4493 #define SUB8(a, b, n) \
4494   RESULT(((uint32_t)(uint8_t)(a) - (uint32_t)(uint8_t)(b)) >> 1, n, 8)
4495 #define PFX uh
4496
4497 #include "op_addsub.h"
4498
4499 static inline uint8_t do_usad(uint8_t a, uint8_t b)
4500 {
4501     if (a > b)
4502         return a - b;
4503     else
4504         return b - a;
4505 }
4506
4507 /* Unsigned sum of absolute byte differences.  */
4508 uint32_t HELPER(usad8)(uint32_t a, uint32_t b)
4509 {
4510     uint32_t sum;
4511     sum = do_usad(a, b);
4512     sum += do_usad(a >> 8, b >> 8);
4513     sum += do_usad(a >> 16, b >>16);
4514     sum += do_usad(a >> 24, b >> 24);
4515     return sum;
4516 }
4517
4518 /* For ARMv6 SEL instruction.  */
4519 uint32_t HELPER(sel_flags)(uint32_t flags, uint32_t a, uint32_t b)
4520 {
4521     uint32_t mask;
4522
4523     mask = 0;
4524     if (flags & 1)
4525         mask |= 0xff;
4526     if (flags & 2)
4527         mask |= 0xff00;
4528     if (flags & 4)
4529         mask |= 0xff0000;
4530     if (flags & 8)
4531         mask |= 0xff000000;
4532     return (a & mask) | (b & ~mask);
4533 }
4534
4535 /* VFP support.  We follow the convention used for VFP instructions:
4536    Single precision routines have a "s" suffix, double precision a
4537    "d" suffix.  */
4538
4539 /* Convert host exception flags to vfp form.  */
4540 static inline int vfp_exceptbits_from_host(int host_bits)
4541 {
4542     int target_bits = 0;
4543
4544     if (host_bits & float_flag_invalid)
4545         target_bits |= 1;
4546     if (host_bits & float_flag_divbyzero)
4547         target_bits |= 2;
4548     if (host_bits & float_flag_overflow)
4549         target_bits |= 4;
4550     if (host_bits & (float_flag_underflow | float_flag_output_denormal))
4551         target_bits |= 8;
4552     if (host_bits & float_flag_inexact)
4553         target_bits |= 0x10;
4554     if (host_bits & float_flag_input_denormal)
4555         target_bits |= 0x80;
4556     return target_bits;
4557 }
4558
4559 uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
4560 {
4561     int i;
4562     uint32_t fpscr;
4563
4564     fpscr = (env->vfp.xregs[ARM_VFP_FPSCR] & 0xffc8ffff)
4565             | (env->vfp.vec_len << 16)
4566             | (env->vfp.vec_stride << 20);
4567     i = get_float_exception_flags(&env->vfp.fp_status);
4568     i |= get_float_exception_flags(&env->vfp.standard_fp_status);
4569     fpscr |= vfp_exceptbits_from_host(i);
4570     return fpscr;
4571 }
4572
4573 uint32_t vfp_get_fpscr(CPUARMState *env)
4574 {
4575     return HELPER(vfp_get_fpscr)(env);
4576 }
4577
4578 /* Convert vfp exception flags to target form.  */
4579 static inline int vfp_exceptbits_to_host(int target_bits)
4580 {
4581     int host_bits = 0;
4582
4583     if (target_bits & 1)
4584         host_bits |= float_flag_invalid;
4585     if (target_bits & 2)
4586         host_bits |= float_flag_divbyzero;
4587     if (target_bits & 4)
4588         host_bits |= float_flag_overflow;
4589     if (target_bits & 8)
4590         host_bits |= float_flag_underflow;
4591     if (target_bits & 0x10)
4592         host_bits |= float_flag_inexact;
4593     if (target_bits & 0x80)
4594         host_bits |= float_flag_input_denormal;
4595     return host_bits;
4596 }
4597
4598 void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
4599 {
4600     int i;
4601     uint32_t changed;
4602
4603     changed = env->vfp.xregs[ARM_VFP_FPSCR];
4604     env->vfp.xregs[ARM_VFP_FPSCR] = (val & 0xffc8ffff);
4605     env->vfp.vec_len = (val >> 16) & 7;
4606     env->vfp.vec_stride = (val >> 20) & 3;
4607
4608     changed ^= val;
4609     if (changed & (3 << 22)) {
4610         i = (val >> 22) & 3;
4611         switch (i) {
4612         case FPROUNDING_TIEEVEN:
4613             i = float_round_nearest_even;
4614             break;
4615         case FPROUNDING_POSINF:
4616             i = float_round_up;
4617             break;
4618         case FPROUNDING_NEGINF:
4619             i = float_round_down;
4620             break;
4621         case FPROUNDING_ZERO:
4622             i = float_round_to_zero;
4623             break;
4624         }
4625         set_float_rounding_mode(i, &env->vfp.fp_status);
4626     }
4627     if (changed & (1 << 24)) {
4628         set_flush_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
4629         set_flush_inputs_to_zero((val & (1 << 24)) != 0, &env->vfp.fp_status);
4630     }
4631     if (changed & (1 << 25))
4632         set_default_nan_mode((val & (1 << 25)) != 0, &env->vfp.fp_status);
4633
4634     i = vfp_exceptbits_to_host(val);
4635     set_float_exception_flags(i, &env->vfp.fp_status);
4636     set_float_exception_flags(0, &env->vfp.standard_fp_status);
4637 }
4638
4639 void vfp_set_fpscr(CPUARMState *env, uint32_t val)
4640 {
4641     HELPER(vfp_set_fpscr)(env, val);
4642 }
4643
4644 #define VFP_HELPER(name, p) HELPER(glue(glue(vfp_,name),p))
4645
4646 #define VFP_BINOP(name) \
4647 float32 VFP_HELPER(name, s)(float32 a, float32 b, void *fpstp) \
4648 { \
4649     float_status *fpst = fpstp; \
4650     return float32_ ## name(a, b, fpst); \
4651 } \
4652 float64 VFP_HELPER(name, d)(float64 a, float64 b, void *fpstp) \
4653 { \
4654     float_status *fpst = fpstp; \
4655     return float64_ ## name(a, b, fpst); \
4656 }
4657 VFP_BINOP(add)
4658 VFP_BINOP(sub)
4659 VFP_BINOP(mul)
4660 VFP_BINOP(div)
4661 VFP_BINOP(min)
4662 VFP_BINOP(max)
4663 VFP_BINOP(minnum)
4664 VFP_BINOP(maxnum)
4665 #undef VFP_BINOP
4666
4667 float32 VFP_HELPER(neg, s)(float32 a)
4668 {
4669     return float32_chs(a);
4670 }
4671
4672 float64 VFP_HELPER(neg, d)(float64 a)
4673 {
4674     return float64_chs(a);
4675 }
4676
4677 float32 VFP_HELPER(abs, s)(float32 a)
4678 {
4679     return float32_abs(a);
4680 }
4681
4682 float64 VFP_HELPER(abs, d)(float64 a)
4683 {
4684     return float64_abs(a);
4685 }
4686
4687 float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
4688 {
4689     return float32_sqrt(a, &env->vfp.fp_status);
4690 }
4691
4692 float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
4693 {
4694     return float64_sqrt(a, &env->vfp.fp_status);
4695 }
4696
4697 /* XXX: check quiet/signaling case */
4698 #define DO_VFP_cmp(p, type) \
4699 void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env)  \
4700 { \
4701     uint32_t flags; \
4702     switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
4703     case 0: flags = 0x6; break; \
4704     case -1: flags = 0x8; break; \
4705     case 1: flags = 0x2; break; \
4706     default: case 2: flags = 0x3; break; \
4707     } \
4708     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
4709         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
4710 } \
4711 void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
4712 { \
4713     uint32_t flags; \
4714     switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
4715     case 0: flags = 0x6; break; \
4716     case -1: flags = 0x8; break; \
4717     case 1: flags = 0x2; break; \
4718     default: case 2: flags = 0x3; break; \
4719     } \
4720     env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
4721         | (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
4722 }
4723 DO_VFP_cmp(s, float32)
4724 DO_VFP_cmp(d, float64)
4725 #undef DO_VFP_cmp
4726
4727 /* Integer to float and float to integer conversions */
4728
4729 #define CONV_ITOF(name, fsz, sign) \
4730     float##fsz HELPER(name)(uint32_t x, void *fpstp) \
4731 { \
4732     float_status *fpst = fpstp; \
4733     return sign##int32_to_##float##fsz((sign##int32_t)x, fpst); \
4734 }
4735
4736 #define CONV_FTOI(name, fsz, sign, round) \
4737 uint32_t HELPER(name)(float##fsz x, void *fpstp) \
4738 { \
4739     float_status *fpst = fpstp; \
4740     if (float##fsz##_is_any_nan(x)) { \
4741         float_raise(float_flag_invalid, fpst); \
4742         return 0; \
4743     } \
4744     return float##fsz##_to_##sign##int32##round(x, fpst); \
4745 }
4746
4747 #define FLOAT_CONVS(name, p, fsz, sign) \
4748 CONV_ITOF(vfp_##name##to##p, fsz, sign) \
4749 CONV_FTOI(vfp_to##name##p, fsz, sign, ) \
4750 CONV_FTOI(vfp_to##name##z##p, fsz, sign, _round_to_zero)
4751
4752 FLOAT_CONVS(si, s, 32, )
4753 FLOAT_CONVS(si, d, 64, )
4754 FLOAT_CONVS(ui, s, 32, u)
4755 FLOAT_CONVS(ui, d, 64, u)
4756
4757 #undef CONV_ITOF
4758 #undef CONV_FTOI
4759 #undef FLOAT_CONVS
4760
4761 /* floating point conversion */
4762 float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
4763 {
4764     float64 r = float32_to_float64(x, &env->vfp.fp_status);
4765     /* ARM requires that S<->D conversion of any kind of NaN generates
4766      * a quiet NaN by forcing the most significant frac bit to 1.
4767      */
4768     return float64_maybe_silence_nan(r);
4769 }
4770
4771 float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
4772 {
4773     float32 r =  float64_to_float32(x, &env->vfp.fp_status);
4774     /* ARM requires that S<->D conversion of any kind of NaN generates
4775      * a quiet NaN by forcing the most significant frac bit to 1.
4776      */
4777     return float32_maybe_silence_nan(r);
4778 }
4779
4780 /* VFP3 fixed point conversion.  */
4781 #define VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype) \
4782 float##fsz HELPER(vfp_##name##to##p)(uint##isz##_t  x, uint32_t shift, \
4783                                      void *fpstp) \
4784 { \
4785     float_status *fpst = fpstp; \
4786     float##fsz tmp; \
4787     tmp = itype##_to_##float##fsz(x, fpst); \
4788     return float##fsz##_scalbn(tmp, -(int)shift, fpst); \
4789 }
4790
4791 /* Notice that we want only input-denormal exception flags from the
4792  * scalbn operation: the other possible flags (overflow+inexact if
4793  * we overflow to infinity, output-denormal) aren't correct for the
4794  * complete scale-and-convert operation.
4795  */
4796 #define VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, round) \
4797 uint##isz##_t HELPER(vfp_to##name##p##round)(float##fsz x, \
4798                                              uint32_t shift, \
4799                                              void *fpstp) \
4800 { \
4801     float_status *fpst = fpstp; \
4802     int old_exc_flags = get_float_exception_flags(fpst); \
4803     float##fsz tmp; \
4804     if (float##fsz##_is_any_nan(x)) { \
4805         float_raise(float_flag_invalid, fpst); \
4806         return 0; \
4807     } \
4808     tmp = float##fsz##_scalbn(x, shift, fpst); \
4809     old_exc_flags |= get_float_exception_flags(fpst) \
4810         & float_flag_input_denormal; \
4811     set_float_exception_flags(old_exc_flags, fpst); \
4812     return float##fsz##_to_##itype##round(tmp, fpst); \
4813 }
4814
4815 #define VFP_CONV_FIX(name, p, fsz, isz, itype)                   \
4816 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
4817 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, _round_to_zero) \
4818 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
4819
4820 #define VFP_CONV_FIX_A64(name, p, fsz, isz, itype)               \
4821 VFP_CONV_FIX_FLOAT(name, p, fsz, isz, itype)                     \
4822 VFP_CONV_FLOAT_FIX_ROUND(name, p, fsz, isz, itype, )
4823
4824 VFP_CONV_FIX(sh, d, 64, 64, int16)
4825 VFP_CONV_FIX(sl, d, 64, 64, int32)
4826 VFP_CONV_FIX_A64(sq, d, 64, 64, int64)
4827 VFP_CONV_FIX(uh, d, 64, 64, uint16)
4828 VFP_CONV_FIX(ul, d, 64, 64, uint32)
4829 VFP_CONV_FIX_A64(uq, d, 64, 64, uint64)
4830 VFP_CONV_FIX(sh, s, 32, 32, int16)
4831 VFP_CONV_FIX(sl, s, 32, 32, int32)
4832 VFP_CONV_FIX_A64(sq, s, 32, 64, int64)
4833 VFP_CONV_FIX(uh, s, 32, 32, uint16)
4834 VFP_CONV_FIX(ul, s, 32, 32, uint32)
4835 VFP_CONV_FIX_A64(uq, s, 32, 64, uint64)
4836 #undef VFP_CONV_FIX
4837 #undef VFP_CONV_FIX_FLOAT
4838 #undef VFP_CONV_FLOAT_FIX_ROUND
4839
4840 /* Set the current fp rounding mode and return the old one.
4841  * The argument is a softfloat float_round_ value.
4842  */
4843 uint32_t HELPER(set_rmode)(uint32_t rmode, CPUARMState *env)
4844 {
4845     float_status *fp_status = &env->vfp.fp_status;
4846
4847     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
4848     set_float_rounding_mode(rmode, fp_status);
4849
4850     return prev_rmode;
4851 }
4852
4853 /* Set the current fp rounding mode in the standard fp status and return
4854  * the old one. This is for NEON instructions that need to change the
4855  * rounding mode but wish to use the standard FPSCR values for everything
4856  * else. Always set the rounding mode back to the correct value after
4857  * modifying it.
4858  * The argument is a softfloat float_round_ value.
4859  */
4860 uint32_t HELPER(set_neon_rmode)(uint32_t rmode, CPUARMState *env)
4861 {
4862     float_status *fp_status = &env->vfp.standard_fp_status;
4863
4864     uint32_t prev_rmode = get_float_rounding_mode(fp_status);
4865     set_float_rounding_mode(rmode, fp_status);
4866
4867     return prev_rmode;
4868 }
4869
4870 /* Half precision conversions.  */
4871 static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
4872 {
4873     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4874     float32 r = float16_to_float32(make_float16(a), ieee, s);
4875     if (ieee) {
4876         return float32_maybe_silence_nan(r);
4877     }
4878     return r;
4879 }
4880
4881 static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
4882 {
4883     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4884     float16 r = float32_to_float16(a, ieee, s);
4885     if (ieee) {
4886         r = float16_maybe_silence_nan(r);
4887     }
4888     return float16_val(r);
4889 }
4890
4891 float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
4892 {
4893     return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
4894 }
4895
4896 uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
4897 {
4898     return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
4899 }
4900
4901 float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
4902 {
4903     return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
4904 }
4905
4906 uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
4907 {
4908     return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
4909 }
4910
4911 float64 HELPER(vfp_fcvt_f16_to_f64)(uint32_t a, CPUARMState *env)
4912 {
4913     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4914     float64 r = float16_to_float64(make_float16(a), ieee, &env->vfp.fp_status);
4915     if (ieee) {
4916         return float64_maybe_silence_nan(r);
4917     }
4918     return r;
4919 }
4920
4921 uint32_t HELPER(vfp_fcvt_f64_to_f16)(float64 a, CPUARMState *env)
4922 {
4923     int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
4924     float16 r = float64_to_float16(a, ieee, &env->vfp.fp_status);
4925     if (ieee) {
4926         r = float16_maybe_silence_nan(r);
4927     }
4928     return float16_val(r);
4929 }
4930
4931 #define float32_two make_float32(0x40000000)
4932 #define float32_three make_float32(0x40400000)
4933 #define float32_one_point_five make_float32(0x3fc00000)
4934
4935 float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
4936 {
4937     float_status *s = &env->vfp.standard_fp_status;
4938     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
4939         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
4940         if (!(float32_is_zero(a) || float32_is_zero(b))) {
4941             float_raise(float_flag_input_denormal, s);
4942         }
4943         return float32_two;
4944     }
4945     return float32_sub(float32_two, float32_mul(a, b, s), s);
4946 }
4947
4948 float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
4949 {
4950     float_status *s = &env->vfp.standard_fp_status;
4951     float32 product;
4952     if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
4953         (float32_is_infinity(b) && float32_is_zero_or_denormal(a))) {
4954         if (!(float32_is_zero(a) || float32_is_zero(b))) {
4955             float_raise(float_flag_input_denormal, s);
4956         }
4957         return float32_one_point_five;
4958     }
4959     product = float32_mul(a, b, s);
4960     return float32_div(float32_sub(float32_three, product, s), float32_two, s);
4961 }
4962
4963 /* NEON helpers.  */
4964
4965 /* Constants 256 and 512 are used in some helpers; we avoid relying on
4966  * int->float conversions at run-time.  */
4967 #define float64_256 make_float64(0x4070000000000000LL)
4968 #define float64_512 make_float64(0x4080000000000000LL)
4969 #define float32_maxnorm make_float32(0x7f7fffff)
4970 #define float64_maxnorm make_float64(0x7fefffffffffffffLL)
4971
4972 /* Reciprocal functions
4973  *
4974  * The algorithm that must be used to calculate the estimate
4975  * is specified by the ARM ARM, see FPRecipEstimate()
4976  */
4977
4978 static float64 recip_estimate(float64 a, float_status *real_fp_status)
4979 {
4980     /* These calculations mustn't set any fp exception flags,
4981      * so we use a local copy of the fp_status.
4982      */
4983     float_status dummy_status = *real_fp_status;
4984     float_status *s = &dummy_status;
4985     /* q = (int)(a * 512.0) */
4986     float64 q = float64_mul(float64_512, a, s);
4987     int64_t q_int = float64_to_int64_round_to_zero(q, s);
4988
4989     /* r = 1.0 / (((double)q + 0.5) / 512.0) */
4990     q = int64_to_float64(q_int, s);
4991     q = float64_add(q, float64_half, s);
4992     q = float64_div(q, float64_512, s);
4993     q = float64_div(float64_one, q, s);
4994
4995     /* s = (int)(256.0 * r + 0.5) */
4996     q = float64_mul(q, float64_256, s);
4997     q = float64_add(q, float64_half, s);
4998     q_int = float64_to_int64_round_to_zero(q, s);
4999
5000     /* return (double)s / 256.0 */
5001     return float64_div(int64_to_float64(q_int, s), float64_256, s);
5002 }
5003
5004 /* Common wrapper to call recip_estimate */
5005 static float64 call_recip_estimate(float64 num, int off, float_status *fpst)
5006 {
5007     uint64_t val64 = float64_val(num);
5008     uint64_t frac = extract64(val64, 0, 52);
5009     int64_t exp = extract64(val64, 52, 11);
5010     uint64_t sbit;
5011     float64 scaled, estimate;
5012
5013     /* Generate the scaled number for the estimate function */
5014     if (exp == 0) {
5015         if (extract64(frac, 51, 1) == 0) {
5016             exp = -1;
5017             frac = extract64(frac, 0, 50) << 2;
5018         } else {
5019             frac = extract64(frac, 0, 51) << 1;
5020         }
5021     }
5022
5023     /* scaled = '0' : '01111111110' : fraction<51:44> : Zeros(44); */
5024     scaled = make_float64((0x3feULL << 52)
5025                           | extract64(frac, 44, 8) << 44);
5026
5027     estimate = recip_estimate(scaled, fpst);
5028
5029     /* Build new result */
5030     val64 = float64_val(estimate);
5031     sbit = 0x8000000000000000ULL & val64;
5032     exp = off - exp;
5033     frac = extract64(val64, 0, 52);
5034
5035     if (exp == 0) {
5036         frac = 1ULL << 51 | extract64(frac, 1, 51);
5037     } else if (exp == -1) {
5038         frac = 1ULL << 50 | extract64(frac, 2, 50);
5039         exp = 0;
5040     }
5041
5042     return make_float64(sbit | (exp << 52) | frac);
5043 }
5044
5045 static bool round_to_inf(float_status *fpst, bool sign_bit)
5046 {
5047     switch (fpst->float_rounding_mode) {
5048     case float_round_nearest_even: /* Round to Nearest */
5049         return true;
5050     case float_round_up: /* Round to +Inf */
5051         return !sign_bit;
5052     case float_round_down: /* Round to -Inf */
5053         return sign_bit;
5054     case float_round_to_zero: /* Round to Zero */
5055         return false;
5056     }
5057
5058     g_assert_not_reached();
5059 }
5060
5061 float32 HELPER(recpe_f32)(float32 input, void *fpstp)
5062 {
5063     float_status *fpst = fpstp;
5064     float32 f32 = float32_squash_input_denormal(input, fpst);
5065     uint32_t f32_val = float32_val(f32);
5066     uint32_t f32_sbit = 0x80000000ULL & f32_val;
5067     int32_t f32_exp = extract32(f32_val, 23, 8);
5068     uint32_t f32_frac = extract32(f32_val, 0, 23);
5069     float64 f64, r64;
5070     uint64_t r64_val;
5071     int64_t r64_exp;
5072     uint64_t r64_frac;
5073
5074     if (float32_is_any_nan(f32)) {
5075         float32 nan = f32;
5076         if (float32_is_signaling_nan(f32)) {
5077             float_raise(float_flag_invalid, fpst);
5078             nan = float32_maybe_silence_nan(f32);
5079         }
5080         if (fpst->default_nan_mode) {
5081             nan =  float32_default_nan;
5082         }
5083         return nan;
5084     } else if (float32_is_infinity(f32)) {
5085         return float32_set_sign(float32_zero, float32_is_neg(f32));
5086     } else if (float32_is_zero(f32)) {
5087         float_raise(float_flag_divbyzero, fpst);
5088         return float32_set_sign(float32_infinity, float32_is_neg(f32));
5089     } else if ((f32_val & ~(1ULL << 31)) < (1ULL << 21)) {
5090         /* Abs(value) < 2.0^-128 */
5091         float_raise(float_flag_overflow | float_flag_inexact, fpst);
5092         if (round_to_inf(fpst, f32_sbit)) {
5093             return float32_set_sign(float32_infinity, float32_is_neg(f32));
5094         } else {
5095             return float32_set_sign(float32_maxnorm, float32_is_neg(f32));
5096         }
5097     } else if (f32_exp >= 253 && fpst->flush_to_zero) {
5098         float_raise(float_flag_underflow, fpst);
5099         return float32_set_sign(float32_zero, float32_is_neg(f32));
5100     }
5101
5102
5103     f64 = make_float64(((int64_t)(f32_exp) << 52) | (int64_t)(f32_frac) << 29);
5104     r64 = call_recip_estimate(f64, 253, fpst);
5105     r64_val = float64_val(r64);
5106     r64_exp = extract64(r64_val, 52, 11);
5107     r64_frac = extract64(r64_val, 0, 52);
5108
5109     /* result = sign : result_exp<7:0> : fraction<51:29>; */
5110     return make_float32(f32_sbit |
5111                         (r64_exp & 0xff) << 23 |
5112                         extract64(r64_frac, 29, 24));
5113 }
5114
5115 float64 HELPER(recpe_f64)(float64 input, void *fpstp)
5116 {
5117     float_status *fpst = fpstp;
5118     float64 f64 = float64_squash_input_denormal(input, fpst);
5119     uint64_t f64_val = float64_val(f64);
5120     uint64_t f64_sbit = 0x8000000000000000ULL & f64_val;
5121     int64_t f64_exp = extract64(f64_val, 52, 11);
5122     float64 r64;
5123     uint64_t r64_val;
5124     int64_t r64_exp;
5125     uint64_t r64_frac;
5126
5127     /* Deal with any special cases */
5128     if (float64_is_any_nan(f64)) {
5129         float64 nan = f64;
5130         if (float64_is_signaling_nan(f64)) {
5131             float_raise(float_flag_invalid, fpst);
5132             nan = float64_maybe_silence_nan(f64);
5133         }
5134         if (fpst->default_nan_mode) {
5135             nan =  float64_default_nan;
5136         }
5137         return nan;
5138     } else if (float64_is_infinity(f64)) {
5139         return float64_set_sign(float64_zero, float64_is_neg(f64));
5140     } else if (float64_is_zero(f64)) {
5141         float_raise(float_flag_divbyzero, fpst);
5142         return float64_set_sign(float64_infinity, float64_is_neg(f64));
5143     } else if ((f64_val & ~(1ULL << 63)) < (1ULL << 50)) {
5144         /* Abs(value) < 2.0^-1024 */
5145         float_raise(float_flag_overflow | float_flag_inexact, fpst);
5146         if (round_to_inf(fpst, f64_sbit)) {
5147             return float64_set_sign(float64_infinity, float64_is_neg(f64));
5148         } else {
5149             return float64_set_sign(float64_maxnorm, float64_is_neg(f64));
5150         }
5151     } else if (f64_exp >= 1023 && fpst->flush_to_zero) {
5152         float_raise(float_flag_underflow, fpst);
5153         return float64_set_sign(float64_zero, float64_is_neg(f64));
5154     }
5155
5156     r64 = call_recip_estimate(f64, 2045, fpst);
5157     r64_val = float64_val(r64);
5158     r64_exp = extract64(r64_val, 52, 11);
5159     r64_frac = extract64(r64_val, 0, 52);
5160
5161     /* result = sign : result_exp<10:0> : fraction<51:0> */
5162     return make_float64(f64_sbit |
5163                         ((r64_exp & 0x7ff) << 52) |
5164                         r64_frac);
5165 }
5166
5167 /* The algorithm that must be used to calculate the estimate
5168  * is specified by the ARM ARM.
5169  */
5170 static float64 recip_sqrt_estimate(float64 a, float_status *real_fp_status)
5171 {
5172     /* These calculations mustn't set any fp exception flags,
5173      * so we use a local copy of the fp_status.
5174      */
5175     float_status dummy_status = *real_fp_status;
5176     float_status *s = &dummy_status;
5177     float64 q;
5178     int64_t q_int;
5179
5180     if (float64_lt(a, float64_half, s)) {
5181         /* range 0.25 <= a < 0.5 */
5182
5183         /* a in units of 1/512 rounded down */
5184         /* q0 = (int)(a * 512.0);  */
5185         q = float64_mul(float64_512, a, s);
5186         q_int = float64_to_int64_round_to_zero(q, s);
5187
5188         /* reciprocal root r */
5189         /* r = 1.0 / sqrt(((double)q0 + 0.5) / 512.0);  */
5190         q = int64_to_float64(q_int, s);
5191         q = float64_add(q, float64_half, s);
5192         q = float64_div(q, float64_512, s);
5193         q = float64_sqrt(q, s);
5194         q = float64_div(float64_one, q, s);
5195     } else {
5196         /* range 0.5 <= a < 1.0 */
5197
5198         /* a in units of 1/256 rounded down */
5199         /* q1 = (int)(a * 256.0); */
5200         q = float64_mul(float64_256, a, s);
5201         int64_t q_int = float64_to_int64_round_to_zero(q, s);
5202
5203         /* reciprocal root r */
5204         /* r = 1.0 /sqrt(((double)q1 + 0.5) / 256); */
5205         q = int64_to_float64(q_int, s);
5206         q = float64_add(q, float64_half, s);
5207         q = float64_div(q, float64_256, s);
5208         q = float64_sqrt(q, s);
5209         q = float64_div(float64_one, q, s);
5210     }
5211     /* r in units of 1/256 rounded to nearest */
5212     /* s = (int)(256.0 * r + 0.5); */
5213
5214     q = float64_mul(q, float64_256,s );
5215     q = float64_add(q, float64_half, s);
5216     q_int = float64_to_int64_round_to_zero(q, s);
5217
5218     /* return (double)s / 256.0;*/
5219     return float64_div(int64_to_float64(q_int, s), float64_256, s);
5220 }
5221
5222 float32 HELPER(rsqrte_f32)(float32 input, void *fpstp)
5223 {
5224     float_status *s = fpstp;
5225     float32 f32 = float32_squash_input_denormal(input, s);
5226     uint32_t val = float32_val(f32);
5227     uint32_t f32_sbit = 0x80000000 & val;
5228     int32_t f32_exp = extract32(val, 23, 8);
5229     uint32_t f32_frac = extract32(val, 0, 23);
5230     uint64_t f64_frac;
5231     uint64_t val64;
5232     int result_exp;
5233     float64 f64;
5234
5235     if (float32_is_any_nan(f32)) {
5236         float32 nan = f32;
5237         if (float32_is_signaling_nan(f32)) {
5238             float_raise(float_flag_invalid, s);
5239             nan = float32_maybe_silence_nan(f32);
5240         }
5241         if (s->default_nan_mode) {
5242             nan =  float32_default_nan;
5243         }
5244         return nan;
5245     } else if (float32_is_zero(f32)) {
5246         float_raise(float_flag_divbyzero, s);
5247         return float32_set_sign(float32_infinity, float32_is_neg(f32));
5248     } else if (float32_is_neg(f32)) {
5249         float_raise(float_flag_invalid, s);
5250         return float32_default_nan;
5251     } else if (float32_is_infinity(f32)) {
5252         return float32_zero;
5253     }
5254
5255     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
5256      * preserving the parity of the exponent.  */
5257
5258     f64_frac = ((uint64_t) f32_frac) << 29;
5259     if (f32_exp == 0) {
5260         while (extract64(f64_frac, 51, 1) == 0) {
5261             f64_frac = f64_frac << 1;
5262             f32_exp = f32_exp-1;
5263         }
5264         f64_frac = extract64(f64_frac, 0, 51) << 1;
5265     }
5266
5267     if (extract64(f32_exp, 0, 1) == 0) {
5268         f64 = make_float64(((uint64_t) f32_sbit) << 32
5269                            | (0x3feULL << 52)
5270                            | f64_frac);
5271     } else {
5272         f64 = make_float64(((uint64_t) f32_sbit) << 32
5273                            | (0x3fdULL << 52)
5274                            | f64_frac);
5275     }
5276
5277     result_exp = (380 - f32_exp) / 2;
5278
5279     f64 = recip_sqrt_estimate(f64, s);
5280
5281     val64 = float64_val(f64);
5282
5283     val = ((result_exp & 0xff) << 23)
5284         | ((val64 >> 29)  & 0x7fffff);
5285     return make_float32(val);
5286 }
5287
5288 float64 HELPER(rsqrte_f64)(float64 input, void *fpstp)
5289 {
5290     float_status *s = fpstp;
5291     float64 f64 = float64_squash_input_denormal(input, s);
5292     uint64_t val = float64_val(f64);
5293     uint64_t f64_sbit = 0x8000000000000000ULL & val;
5294     int64_t f64_exp = extract64(val, 52, 11);
5295     uint64_t f64_frac = extract64(val, 0, 52);
5296     int64_t result_exp;
5297     uint64_t result_frac;
5298
5299     if (float64_is_any_nan(f64)) {
5300         float64 nan = f64;
5301         if (float64_is_signaling_nan(f64)) {
5302             float_raise(float_flag_invalid, s);
5303             nan = float64_maybe_silence_nan(f64);
5304         }
5305         if (s->default_nan_mode) {
5306             nan =  float64_default_nan;
5307         }
5308         return nan;
5309     } else if (float64_is_zero(f64)) {
5310         float_raise(float_flag_divbyzero, s);
5311         return float64_set_sign(float64_infinity, float64_is_neg(f64));
5312     } else if (float64_is_neg(f64)) {
5313         float_raise(float_flag_invalid, s);
5314         return float64_default_nan;
5315     } else if (float64_is_infinity(f64)) {
5316         return float64_zero;
5317     }
5318
5319     /* Scale and normalize to a double-precision value between 0.25 and 1.0,
5320      * preserving the parity of the exponent.  */
5321
5322     if (f64_exp == 0) {
5323         while (extract64(f64_frac, 51, 1) == 0) {
5324             f64_frac = f64_frac << 1;
5325             f64_exp = f64_exp - 1;
5326         }
5327         f64_frac = extract64(f64_frac, 0, 51) << 1;
5328     }
5329
5330     if (extract64(f64_exp, 0, 1) == 0) {
5331         f64 = make_float64(f64_sbit
5332                            | (0x3feULL << 52)
5333                            | f64_frac);
5334     } else {
5335         f64 = make_float64(f64_sbit
5336                            | (0x3fdULL << 52)
5337                            | f64_frac);
5338     }
5339
5340     result_exp = (3068 - f64_exp) / 2;
5341
5342     f64 = recip_sqrt_estimate(f64, s);
5343
5344     result_frac = extract64(float64_val(f64), 0, 52);
5345
5346     return make_float64(f64_sbit |
5347                         ((result_exp & 0x7ff) << 52) |
5348                         result_frac);
5349 }
5350
5351 uint32_t HELPER(recpe_u32)(uint32_t a, void *fpstp)
5352 {
5353     float_status *s = fpstp;
5354     float64 f64;
5355
5356     if ((a & 0x80000000) == 0) {
5357         return 0xffffffff;
5358     }
5359
5360     f64 = make_float64((0x3feULL << 52)
5361                        | ((int64_t)(a & 0x7fffffff) << 21));
5362
5363     f64 = recip_estimate(f64, s);
5364
5365     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
5366 }
5367
5368 uint32_t HELPER(rsqrte_u32)(uint32_t a, void *fpstp)
5369 {
5370     float_status *fpst = fpstp;
5371     float64 f64;
5372
5373     if ((a & 0xc0000000) == 0) {
5374         return 0xffffffff;
5375     }
5376
5377     if (a & 0x80000000) {
5378         f64 = make_float64((0x3feULL << 52)
5379                            | ((uint64_t)(a & 0x7fffffff) << 21));
5380     } else { /* bits 31-30 == '01' */
5381         f64 = make_float64((0x3fdULL << 52)
5382                            | ((uint64_t)(a & 0x3fffffff) << 22));
5383     }
5384
5385     f64 = recip_sqrt_estimate(f64, fpst);
5386
5387     return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
5388 }
5389
5390 /* VFPv4 fused multiply-accumulate */
5391 float32 VFP_HELPER(muladd, s)(float32 a, float32 b, float32 c, void *fpstp)
5392 {
5393     float_status *fpst = fpstp;
5394     return float32_muladd(a, b, c, 0, fpst);
5395 }
5396
5397 float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
5398 {
5399     float_status *fpst = fpstp;
5400     return float64_muladd(a, b, c, 0, fpst);
5401 }
5402
5403 /* ARMv8 round to integral */
5404 float32 HELPER(rints_exact)(float32 x, void *fp_status)
5405 {
5406     return float32_round_to_int(x, fp_status);
5407 }
5408
5409 float64 HELPER(rintd_exact)(float64 x, void *fp_status)
5410 {
5411     return float64_round_to_int(x, fp_status);
5412 }
5413
5414 float32 HELPER(rints)(float32 x, void *fp_status)
5415 {
5416     int old_flags = get_float_exception_flags(fp_status), new_flags;
5417     float32 ret;
5418
5419     ret = float32_round_to_int(x, fp_status);
5420
5421     /* Suppress any inexact exceptions the conversion produced */
5422     if (!(old_flags & float_flag_inexact)) {
5423         new_flags = get_float_exception_flags(fp_status);
5424         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
5425     }
5426
5427     return ret;
5428 }
5429
5430 float64 HELPER(rintd)(float64 x, void *fp_status)
5431 {
5432     int old_flags = get_float_exception_flags(fp_status), new_flags;
5433     float64 ret;
5434
5435     ret = float64_round_to_int(x, fp_status);
5436
5437     new_flags = get_float_exception_flags(fp_status);
5438
5439     /* Suppress any inexact exceptions the conversion produced */
5440     if (!(old_flags & float_flag_inexact)) {
5441         new_flags = get_float_exception_flags(fp_status);
5442         set_float_exception_flags(new_flags & ~float_flag_inexact, fp_status);
5443     }
5444
5445     return ret;
5446 }
5447
5448 /* Convert ARM rounding mode to softfloat */
5449 int arm_rmode_to_sf(int rmode)
5450 {
5451     switch (rmode) {
5452     case FPROUNDING_TIEAWAY:
5453         rmode = float_round_ties_away;
5454         break;
5455     case FPROUNDING_ODD:
5456         /* FIXME: add support for TIEAWAY and ODD */
5457         qemu_log_mask(LOG_UNIMP, "arm: unimplemented rounding mode: %d\n",
5458                       rmode);
5459     case FPROUNDING_TIEEVEN:
5460     default:
5461         rmode = float_round_nearest_even;
5462         break;
5463     case FPROUNDING_POSINF:
5464         rmode = float_round_up;
5465         break;
5466     case FPROUNDING_NEGINF:
5467         rmode = float_round_down;
5468         break;
5469     case FPROUNDING_ZERO:
5470         rmode = float_round_to_zero;
5471         break;
5472     }
5473     return rmode;
5474 }
5475
5476 static void crc_init_buffer(uint8_t *buf, uint32_t val, uint32_t bytes)
5477 {
5478     memset(buf, 0, 4);
5479
5480     if (bytes == 1) {
5481         buf[0] = val & 0xff;
5482     } else if (bytes == 2) {
5483         buf[0] = val & 0xff;
5484         buf[1] = (val >> 8) & 0xff;
5485     } else {
5486         buf[0] = val & 0xff;
5487         buf[1] = (val >> 8) & 0xff;
5488         buf[2] = (val >> 16) & 0xff;
5489         buf[3] = (val >> 24) & 0xff;
5490     }
5491 }
5492
5493 uint32_t HELPER(crc32)(uint32_t acc, uint32_t val, uint32_t bytes)
5494 {
5495     uint8_t buf[4];
5496
5497     crc_init_buffer(buf, val, bytes);
5498
5499     /* zlib crc32 converts the accumulator and output to one's complement.  */
5500     return crc32(acc ^ 0xffffffff, buf, bytes) ^ 0xffffffff;
5501 }
5502
5503 uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes)
5504 {
5505     uint8_t buf[4];
5506
5507     crc_init_buffer(buf, val, bytes);
5508
5509     /* Linux crc32c converts the output to one's complement.  */
5510     return crc32c(acc, buf, bytes) ^ 0xffffffff;
5511 }