hw/arm/highbank.c

   1 /*
   2  * Calxeda Highbank SoC emulation
   3  *
   4  * Copyright (c) 2010-2012 Calxeda
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms and conditions of the GNU General Public License,
   8  * version 2 or later, as published by the Free Software Foundation.
   9  *
  10  * This program is distributed in the hope it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
  13  * more details.
  14  *
  15  * You should have received a copy of the GNU General Public License along with
  16  * this program.  If not, see <http://www.gnu.org/licenses/>.
  17  *
  18  */
  19
  20 #include "hw/sysbus.h"
  21 #include "hw/arm/arm.h"
  22 #include "hw/devices.h"
  23 #include "hw/loader.h"
  24 #include "net/net.h"
  25 #include "sysemu/sysemu.h"
  26 #include "hw/boards.h"
  27 #include "sysemu/blockdev.h"
  28 #include "exec/address-spaces.h"
  29
  30 #define SMP_BOOT_ADDR 0x100
  31 #define SMP_BOOT_REG  0x40
  32 #define GIC_BASE_ADDR 0xfff10000
  33
  34 #define NIRQ_GIC      160
  35
  36 /* Board init.  */
  37
  38 static void hb_write_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
  39 {
  40     int n;
  41     uint32_t smpboot[] = {
  42         0xee100fb0, /* mrc p15, 0, r0, c0, c0, 5 - read current core id */
  43         0xe210000f, /* ands r0, r0, #0x0f */
  44         0xe3a03040, /* mov r3, #0x40 - jump address is 0x40 + 0x10 * core id */
  45         0xe0830200, /* add r0, r3, r0, lsl #4 */
  46         0xe59f2024, /* ldr r2, privbase */
  47         0xe3a01001, /* mov r1, #1 */
  48         0xe5821100, /* str r1, [r2, #256] - set GICC_CTLR.Enable */
  49         0xe3a010ff, /* mov r1, #0xff */
  50         0xe5821104, /* str r1, [r2, #260] - set GICC_PMR.Priority to 0xff */
  51         0xf57ff04f, /* dsb */
  52         0xe320f003, /* wfi */
  53         0xe5901000, /* ldr     r1, [r0] */
  54         0xe1110001, /* tst     r1, r1 */
  55         0x0afffffb, /* beq     <wfi> */
  56         0xe12fff11, /* bx      r1 */
  57         GIC_BASE_ADDR      /* privbase: gic address.  */
  58     };
  59     for (n = 0; n < ARRAY_SIZE(smpboot); n++) {
  60         smpboot[n] = tswap32(smpboot[n]);
  61     }
  62     rom_add_blob_fixed("smpboot", smpboot, sizeof(smpboot), SMP_BOOT_ADDR);
  63 }
  64
  65 static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info)
  66 {
  67     CPUARMState *env = &cpu->env;
  68
  69     switch (info->nb_cpus) {
  70     case 4:
  71         stl_phys_notdirty(SMP_BOOT_REG + 0x30, 0);
  72     case 3:
  73         stl_phys_notdirty(SMP_BOOT_REG + 0x20, 0);
  74     case 2:
  75         stl_phys_notdirty(SMP_BOOT_REG + 0x10, 0);
  76         env->regs[15] = SMP_BOOT_ADDR;
  77         break;
  78     default:
  79         break;
  80     }
  81 }
  82
  83 #define NUM_REGS      0x200
  84 static void hb_regs_write(void *opaque, hwaddr offset,
  85                           uint64_t value, unsigned size)
  86 {
  87     uint32_t *regs = opaque;
  88
  89     if (offset == 0xf00) {
  90         if (value == 1 || value == 2) {
  91             qemu_system_reset_request();
  92         } else if (value == 3) {
  93             qemu_system_shutdown_request();
  94         }
  95     }
  96
  97     regs[offset/4] = value;
  98 }
  99
 100 static uint64_t hb_regs_read(void *opaque, hwaddr offset,
 101                              unsigned size)
 102 {
 103     uint32_t *regs = opaque;
 104     uint32_t value = regs[offset/4];
 105
 106     if ((offset == 0x100) || (offset == 0x108) || (offset == 0x10C)) {
 107         value |= 0x30000000;
 108     }
 109
 110     return value;
 111 }
 112
 113 static const MemoryRegionOps hb_mem_ops = {
 114     .read = hb_regs_read,
 115     .write = hb_regs_write,
 116     .endianness = DEVICE_NATIVE_ENDIAN,
 117 };
 118
 119 #define TYPE_HIGHBANK_REGISTERS "highbank-regs"
 120 #define HIGHBANK_REGISTERS(obj) \
 121     OBJECT_CHECK(HighbankRegsState, (obj), TYPE_HIGHBANK_REGISTERS)
 122
 123 typedef struct {
 124     /*< private >*/
 125     SysBusDevice parent_obj;
 126     /*< public >*/
 127
 128     MemoryRegion *iomem;
 129     uint32_t regs[NUM_REGS];
 130 } HighbankRegsState;
 131
 132 static VMStateDescription vmstate_highbank_regs = {
 133     .name = "highbank-regs",
 134     .version_id = 0,
 135     .minimum_version_id = 0,
 136     .minimum_version_id_old = 0,
 137     .fields = (VMStateField[]) {
 138         VMSTATE_UINT32_ARRAY(regs, HighbankRegsState, NUM_REGS),
 139         VMSTATE_END_OF_LIST(),
 140     },
 141 };
 142
 143 static void highbank_regs_reset(DeviceState *dev)
 144 {
 145     HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
 146
 147     s->regs[0x40] = 0x05F20121;
 148     s->regs[0x41] = 0x2;
 149     s->regs[0x42] = 0x05F30121;
 150     s->regs[0x43] = 0x05F40121;
 151 }
 152
 153 static int highbank_regs_init(SysBusDevice *dev)
 154 {
 155     HighbankRegsState *s = HIGHBANK_REGISTERS(dev);
 156
 157     s->iomem = g_new(MemoryRegion, 1);
 158     memory_region_init_io(s->iomem, OBJECT(s), &hb_mem_ops, s->regs,
 159                           "highbank_regs", 0x1000);
 160     sysbus_init_mmio(dev, s->iomem);
 161
 162     return 0;
 163 }
 164
 165 static void highbank_regs_class_init(ObjectClass *klass, void *data)
 166 {
 167     SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass);
 168     DeviceClass *dc = DEVICE_CLASS(klass);
 169
 170     sbc->init = highbank_regs_init;
 171     dc->desc = "Calxeda Highbank registers";
 172     dc->vmsd = &vmstate_highbank_regs;
 173     dc->reset = highbank_regs_reset;
 174 }
 175
 176 static const TypeInfo highbank_regs_info = {
 177     .name          = TYPE_HIGHBANK_REGISTERS,
 178     .parent        = TYPE_SYS_BUS_DEVICE,
 179     .instance_size = sizeof(HighbankRegsState),
 180     .class_init    = highbank_regs_class_init,
 181 };
 182
 183 static void highbank_regs_register_types(void)
 184 {
 185     type_register_static(&highbank_regs_info);
 186 }
 187
 188 type_init(highbank_regs_register_types)
 189
 190 static struct arm_boot_info highbank_binfo;
 191
 192 enum cxmachines {
 193     CALXEDA_HIGHBANK,
 194     CALXEDA_MIDWAY,
 195 };
 196
 197 /* ram_size must be set to match the upper bound of memory in the
 198  * device tree (linux/arch/arm/boot/dts/highbank.dts), which is
 199  * normally 0xff900000 or -m 4089. When running this board on a
 200  * 32-bit host, set the reg value of memory to 0xf7ff00000 in the
 201  * device tree and pass -m 2047 to QEMU.
 202  */
 203 static void calxeda_init(QEMUMachineInitArgs *args, enum cxmachines machine)
 204 {
 205     ram_addr_t ram_size = args->ram_size;
 206     const char *cpu_model = args->cpu_model;
 207     const char *kernel_filename = args->kernel_filename;
 208     const char *kernel_cmdline = args->kernel_cmdline;
 209     const char *initrd_filename = args->initrd_filename;
 210     DeviceState *dev = NULL;
 211     SysBusDevice *busdev;
 212     qemu_irq *irqp;
 213     qemu_irq pic[128];
 214     int n;
 215     qemu_irq cpu_irq[4];
 216     MemoryRegion *sysram;
 217     MemoryRegion *dram;
 218     MemoryRegion *sysmem;
 219     char *sysboot_filename;
 220
 221     if (!cpu_model) {
 222         switch (machine) {
 223         case CALXEDA_HIGHBANK:
 224             cpu_model = "cortex-a9";
 225             break;
 226         case CALXEDA_MIDWAY:
 227             cpu_model = "cortex-a15";
 228             break;
 229         }
 230     }
 231
 232     for (n = 0; n < smp_cpus; n++) {
 233         ARMCPU *cpu;
 234         cpu = cpu_arm_init(cpu_model);
 235         if (cpu == NULL) {
 236             fprintf(stderr, "Unable to find CPU definition\n");
 237             exit(1);
 238         }
 239
 240         /* This will become a QOM property eventually */
 241         cpu->reset_cbar = GIC_BASE_ADDR;
 242         irqp = arm_pic_init_cpu(cpu);
 243         cpu_irq[n] = irqp[ARM_PIC_CPU_IRQ];
 244     }
 245
 246     sysmem = get_system_memory();
 247     dram = g_new(MemoryRegion, 1);
 248     memory_region_init_ram(dram, NULL, "highbank.dram", ram_size);
 249     /* SDRAM at address zero.  */
 250     memory_region_add_subregion(sysmem, 0, dram);
 251
 252     sysram = g_new(MemoryRegion, 1);
 253     memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000);
 254     memory_region_add_subregion(sysmem, 0xfff88000, sysram);
 255     if (bios_name != NULL) {
 256         sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 257         if (sysboot_filename != NULL) {
 258             uint32_t filesize = get_image_size(sysboot_filename);
 259             if (load_image_targphys("sysram.bin", 0xfff88000, filesize) < 0) {
 260                 hw_error("Unable to load %s\n", bios_name);
 261             }
 262         } else {
 263            hw_error("Unable to find %s\n", bios_name);
 264         }
 265     }
 266
 267     switch (machine) {
 268     case CALXEDA_HIGHBANK:
 269         dev = qdev_create(NULL, "l2x0");
 270         qdev_init_nofail(dev);
 271         busdev = SYS_BUS_DEVICE(dev);
 272         sysbus_mmio_map(busdev, 0, 0xfff12000);
 273
 274         dev = qdev_create(NULL, "a9mpcore_priv");
 275         break;
 276     case CALXEDA_MIDWAY:
 277         dev = qdev_create(NULL, "a15mpcore_priv");
 278         break;
 279     }
 280     qdev_prop_set_uint32(dev, "num-cpu", smp_cpus);
 281     qdev_prop_set_uint32(dev, "num-irq", NIRQ_GIC);
 282     qdev_init_nofail(dev);
 283     busdev = SYS_BUS_DEVICE(dev);
 284     sysbus_mmio_map(busdev, 0, GIC_BASE_ADDR);
 285     for (n = 0; n < smp_cpus; n++) {
 286         sysbus_connect_irq(busdev, n, cpu_irq[n]);
 287     }
 288
 289     for (n = 0; n < 128; n++) {
 290         pic[n] = qdev_get_gpio_in(dev, n);
 291     }
 292
 293     dev = qdev_create(NULL, "sp804");
 294     qdev_prop_set_uint32(dev, "freq0", 150000000);
 295     qdev_prop_set_uint32(dev, "freq1", 150000000);
 296     qdev_init_nofail(dev);
 297     busdev = SYS_BUS_DEVICE(dev);
 298     sysbus_mmio_map(busdev, 0, 0xfff34000);
 299     sysbus_connect_irq(busdev, 0, pic[18]);
 300     sysbus_create_simple("pl011", 0xfff36000, pic[20]);
 301
 302     dev = qdev_create(NULL, "highbank-regs");
 303     qdev_init_nofail(dev);
 304     busdev = SYS_BUS_DEVICE(dev);
 305     sysbus_mmio_map(busdev, 0, 0xfff3c000);
 306
 307     sysbus_create_simple("pl061", 0xfff30000, pic[14]);
 308     sysbus_create_simple("pl061", 0xfff31000, pic[15]);
 309     sysbus_create_simple("pl061", 0xfff32000, pic[16]);
 310     sysbus_create_simple("pl061", 0xfff33000, pic[17]);
 311     sysbus_create_simple("pl031", 0xfff35000, pic[19]);
 312     sysbus_create_simple("pl022", 0xfff39000, pic[23]);
 313
 314     sysbus_create_simple("sysbus-ahci", 0xffe08000, pic[83]);
 315
 316     if (nd_table[0].used) {
 317         qemu_check_nic_model(&nd_table[0], "xgmac");
 318         dev = qdev_create(NULL, "xgmac");
 319         qdev_set_nic_properties(dev, &nd_table[0]);
 320         qdev_init_nofail(dev);
 321         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff50000);
 322         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[77]);
 323         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[78]);
 324         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[79]);
 325
 326         qemu_check_nic_model(&nd_table[1], "xgmac");
 327         dev = qdev_create(NULL, "xgmac");
 328         qdev_set_nic_properties(dev, &nd_table[1]);
 329         qdev_init_nofail(dev);
 330         sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, 0xfff51000);
 331         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, pic[80]);
 332         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 1, pic[81]);
 333         sysbus_connect_irq(SYS_BUS_DEVICE(dev), 2, pic[82]);
 334     }
 335
 336     highbank_binfo.ram_size = ram_size;
 337     highbank_binfo.kernel_filename = kernel_filename;
 338     highbank_binfo.kernel_cmdline = kernel_cmdline;
 339     highbank_binfo.initrd_filename = initrd_filename;
 340     /* highbank requires a dtb in order to boot, and the dtb will override
 341      * the board ID. The following value is ignored, so set it to -1 to be
 342      * clear that the value is meaningless.
 343      */
 344     highbank_binfo.board_id = -1;
 345     highbank_binfo.nb_cpus = smp_cpus;
 346     highbank_binfo.loader_start = 0;
 347     highbank_binfo.write_secondary_boot = hb_write_secondary;
 348     highbank_binfo.secondary_cpu_reset_hook = hb_reset_secondary;
 349     arm_load_kernel(ARM_CPU(first_cpu), &highbank_binfo);
 350 }
 351
 352 static void highbank_init(QEMUMachineInitArgs *args)
 353 {
 354     calxeda_init(args, CALXEDA_HIGHBANK);
 355 }
 356
 357 static void midway_init(QEMUMachineInitArgs *args)
 358 {
 359     calxeda_init(args, CALXEDA_MIDWAY);
 360 }
 361
 362 static QEMUMachine highbank_machine = {
 363     .name = "highbank",
 364     .desc = "Calxeda Highbank (ECX-1000)",
 365     .init = highbank_init,
 366     .block_default_type = IF_SCSI,
 367     .max_cpus = 4,
 368     DEFAULT_MACHINE_OPTIONS,
 369 };
 370
 371 static QEMUMachine midway_machine = {
 372     .name = "midway",
 373     .desc = "Calxeda Midway (ECX-2000)",
 374     .init = midway_init,
 375     .block_default_type = IF_SCSI,
 376     .max_cpus = 4,
 377     DEFAULT_MACHINE_OPTIONS,
 378 };
 379
 380 static void calxeda_machines_init(void)
 381 {
 382     qemu_register_machine(&highbank_machine);
 383     qemu_register_machine(&midway_machine);
 384 }
 385
 386 machine_init(calxeda_machines_init);