2 * i386 CPUID helper functions
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
27 #include "qemu-option.h"
28 #include "qemu-config.h"
30 #include "qapi/qapi-visit-core.h"
34 /* feature flags taken from "Intel Processor Identification and the CPUID
35 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
36 * between feature naming conventions, aliases may be added.
38 static const char *feature_name
[] = {
39 "fpu", "vme", "de", "pse",
40 "tsc", "msr", "pae", "mce",
41 "cx8", "apic", NULL
, "sep",
42 "mtrr", "pge", "mca", "cmov",
43 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
44 NULL
, "ds" /* Intel dts */, "acpi", "mmx",
45 "fxsr", "sse", "sse2", "ss",
46 "ht" /* Intel htt */, "tm", "ia64", "pbe",
48 static const char *ext_feature_name
[] = {
49 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
50 "ds_cpl", "vmx", "smx", "est",
51 "tm2", "ssse3", "cid", NULL
,
52 "fma", "cx16", "xtpr", "pdcm",
53 NULL
, "pcid", "dca", "sse4.1|sse4_1",
54 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
55 "tsc-deadline", "aes", "xsave", "osxsave",
56 "avx", NULL
, NULL
, "hypervisor",
58 static const char *ext2_feature_name
[] = {
59 "fpu", "vme", "de", "pse",
60 "tsc", "msr", "pae", "mce",
61 "cx8" /* AMD CMPXCHG8B */, "apic", NULL
, "syscall",
62 "mtrr", "pge", "mca", "cmov",
63 "pat", "pse36", NULL
, NULL
/* Linux mp */,
64 "nx|xd", NULL
, "mmxext", "mmx",
65 "fxsr", "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
66 NULL
, "lm|i64", "3dnowext", "3dnow",
68 static const char *ext3_feature_name
[] = {
69 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
70 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
71 "3dnowprefetch", "osvw", "ibs", "xop",
72 "skinit", "wdt", NULL
, NULL
,
73 "fma4", NULL
, "cvt16", "nodeid_msr",
74 NULL
, NULL
, NULL
, NULL
,
75 NULL
, NULL
, NULL
, NULL
,
76 NULL
, NULL
, NULL
, NULL
,
79 static const char *kvm_feature_name
[] = {
80 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock", "kvm_asyncpf", NULL
, "kvm_pv_eoi", NULL
,
81 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
82 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
83 NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
, NULL
,
86 static const char *svm_feature_name
[] = {
87 "npt", "lbrv", "svm_lock", "nrip_save",
88 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
89 NULL
, NULL
, "pause_filter", NULL
,
90 "pfthreshold", NULL
, NULL
, NULL
,
91 NULL
, NULL
, NULL
, NULL
,
92 NULL
, NULL
, NULL
, NULL
,
93 NULL
, NULL
, NULL
, NULL
,
94 NULL
, NULL
, NULL
, NULL
,
97 /* collects per-function cpuid data
99 typedef struct model_features_t
{
100 uint32_t *guest_feat
;
103 const char **flag_names
;
108 int enforce_cpuid
= 0;
110 void host_cpuid(uint32_t function
, uint32_t count
,
111 uint32_t *eax
, uint32_t *ebx
, uint32_t *ecx
, uint32_t *edx
)
113 #if defined(CONFIG_KVM)
118 : "=a"(vec
[0]), "=b"(vec
[1]),
119 "=c"(vec
[2]), "=d"(vec
[3])
120 : "0"(function
), "c"(count
) : "cc");
122 asm volatile("pusha \n\t"
124 "mov %%eax, 0(%2) \n\t"
125 "mov %%ebx, 4(%2) \n\t"
126 "mov %%ecx, 8(%2) \n\t"
127 "mov %%edx, 12(%2) \n\t"
129 : : "a"(function
), "c"(count
), "S"(vec
)
144 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
146 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
147 * a substring. ex if !NULL points to the first char after a substring,
148 * otherwise the string is assumed to sized by a terminating nul.
149 * Return lexical ordering of *s1:*s2.
151 static int sstrcmp(const char *s1
, const char *e1
, const char *s2
,
155 if (!*s1
|| !*s2
|| *s1
!= *s2
)
158 if (s1
== e1
&& s2
== e2
)
167 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
168 * '|' delimited (possibly empty) strings in which case search for a match
169 * within the alternatives proceeds left to right. Return 0 for success,
170 * non-zero otherwise.
172 static int altcmp(const char *s
, const char *e
, const char *altstr
)
176 for (q
= p
= altstr
; ; ) {
177 while (*p
&& *p
!= '|')
179 if ((q
== p
&& !*s
) || (q
!= p
&& !sstrcmp(s
, e
, q
, p
)))
188 /* search featureset for flag *[s..e), if found set corresponding bit in
189 * *pval and return true, otherwise return false
191 static bool lookup_feature(uint32_t *pval
, const char *s
, const char *e
,
192 const char **featureset
)
198 for (mask
= 1, ppc
= featureset
; mask
; mask
<<= 1, ++ppc
) {
199 if (*ppc
&& !altcmp(s
, e
, *ppc
)) {
207 static void add_flagname_to_bitmaps(const char *flagname
, uint32_t *features
,
208 uint32_t *ext_features
,
209 uint32_t *ext2_features
,
210 uint32_t *ext3_features
,
211 uint32_t *kvm_features
,
212 uint32_t *svm_features
)
214 if (!lookup_feature(features
, flagname
, NULL
, feature_name
) &&
215 !lookup_feature(ext_features
, flagname
, NULL
, ext_feature_name
) &&
216 !lookup_feature(ext2_features
, flagname
, NULL
, ext2_feature_name
) &&
217 !lookup_feature(ext3_features
, flagname
, NULL
, ext3_feature_name
) &&
218 !lookup_feature(kvm_features
, flagname
, NULL
, kvm_feature_name
) &&
219 !lookup_feature(svm_features
, flagname
, NULL
, svm_feature_name
))
220 fprintf(stderr
, "CPU feature %s not found\n", flagname
);
223 typedef struct x86_def_t
{
224 struct x86_def_t
*next
;
227 uint32_t vendor1
, vendor2
, vendor3
;
232 uint32_t features
, ext_features
, ext2_features
, ext3_features
;
233 uint32_t kvm_features
, svm_features
;
238 /* Store the results of Centaur's CPUID instructions */
239 uint32_t ext4_features
;
241 /* The feature bits on CPUID[EAX=7,ECX=0].EBX */
242 uint32_t cpuid_7_0_ebx_features
;
245 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
246 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
247 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
248 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
249 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
250 CPUID_PSE36 | CPUID_FXSR)
251 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
252 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
253 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
254 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
255 CPUID_PAE | CPUID_SEP | CPUID_APIC)
256 #define EXT2_FEATURE_MASK 0x0183F3FF
258 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
259 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
260 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
261 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
262 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
263 /* partly implemented:
264 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64)
265 CPUID_PSE36 (needed for Solaris) */
267 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
268 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | \
269 CPUID_EXT_CX16 | CPUID_EXT_POPCNT | \
270 CPUID_EXT_HYPERVISOR)
272 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_EST,
273 CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_XSAVE */
274 #define TCG_EXT2_FEATURES ((TCG_FEATURES & EXT2_FEATURE_MASK) | \
275 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
276 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT)
278 CPUID_EXT2_PDPE1GB */
279 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
280 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
281 #define TCG_SVM_FEATURES 0
283 /* maintains list of cpu model definitions
285 static x86_def_t
*x86_defs
= {NULL
};
287 /* built-in cpu model definitions (deprecated)
289 static x86_def_t builtin_x86_defs
[] = {
293 .vendor1
= CPUID_VENDOR_AMD_1
,
294 .vendor2
= CPUID_VENDOR_AMD_2
,
295 .vendor3
= CPUID_VENDOR_AMD_3
,
299 .features
= PPRO_FEATURES
|
300 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
302 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_CX16
| CPUID_EXT_POPCNT
,
303 .ext2_features
= (PPRO_FEATURES
& EXT2_FEATURE_MASK
) |
304 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
305 .ext3_features
= CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
306 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
307 .xlevel
= 0x8000000A,
312 .vendor1
= CPUID_VENDOR_AMD_1
,
313 .vendor2
= CPUID_VENDOR_AMD_2
,
314 .vendor3
= CPUID_VENDOR_AMD_3
,
318 .features
= PPRO_FEATURES
|
319 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
320 CPUID_PSE36
| CPUID_VME
| CPUID_HT
,
321 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_CX16
|
323 .ext2_features
= (PPRO_FEATURES
& EXT2_FEATURE_MASK
) |
324 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
|
325 CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
| CPUID_EXT2_MMXEXT
|
326 CPUID_EXT2_FFXSR
| CPUID_EXT2_PDPE1GB
| CPUID_EXT2_RDTSCP
,
327 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
329 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
330 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
331 .ext3_features
= CPUID_EXT3_LAHF_LM
| CPUID_EXT3_SVM
|
332 CPUID_EXT3_ABM
| CPUID_EXT3_SSE4A
,
333 .svm_features
= CPUID_SVM_NPT
| CPUID_SVM_LBRV
,
334 .xlevel
= 0x8000001A,
335 .model_id
= "AMD Phenom(tm) 9550 Quad-Core Processor"
343 .features
= PPRO_FEATURES
|
344 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
345 CPUID_PSE36
| CPUID_VME
| CPUID_DTS
| CPUID_ACPI
| CPUID_SS
|
346 CPUID_HT
| CPUID_TM
| CPUID_PBE
,
347 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
348 CPUID_EXT_DTES64
| CPUID_EXT_DSCPL
| CPUID_EXT_VMX
| CPUID_EXT_EST
|
349 CPUID_EXT_TM2
| CPUID_EXT_CX16
| CPUID_EXT_XTPR
| CPUID_EXT_PDCM
,
350 .ext2_features
= CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
351 .ext3_features
= CPUID_EXT3_LAHF_LM
,
352 .xlevel
= 0x80000008,
353 .model_id
= "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
358 .vendor1
= CPUID_VENDOR_INTEL_1
,
359 .vendor2
= CPUID_VENDOR_INTEL_2
,
360 .vendor3
= CPUID_VENDOR_INTEL_3
,
364 /* Missing: CPUID_VME, CPUID_HT */
365 .features
= PPRO_FEATURES
|
366 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
|
368 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
369 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_CX16
,
370 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
371 .ext2_features
= (PPRO_FEATURES
& EXT2_FEATURE_MASK
) |
372 CPUID_EXT2_LM
| CPUID_EXT2_SYSCALL
| CPUID_EXT2_NX
,
373 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
374 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
375 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
376 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
378 .xlevel
= 0x80000008,
379 .model_id
= "Common KVM processor"
387 .features
= PPRO_FEATURES
,
388 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_POPCNT
,
389 .xlevel
= 0x80000004,
397 .features
= PPRO_FEATURES
|
398 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_PSE36
,
399 .ext_features
= CPUID_EXT_SSE3
,
400 .ext2_features
= PPRO_FEATURES
& EXT2_FEATURE_MASK
,
402 .xlevel
= 0x80000008,
403 .model_id
= "Common 32-bit KVM processor"
411 .features
= PPRO_FEATURES
| CPUID_VME
|
412 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_DTS
| CPUID_ACPI
|
413 CPUID_SS
| CPUID_HT
| CPUID_TM
| CPUID_PBE
,
414 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_VMX
|
415 CPUID_EXT_EST
| CPUID_EXT_TM2
| CPUID_EXT_XTPR
| CPUID_EXT_PDCM
,
416 .ext2_features
= CPUID_EXT2_NX
,
417 .xlevel
= 0x80000008,
418 .model_id
= "Genuine Intel(R) CPU T2600 @ 2.16GHz",
426 .features
= I486_FEATURES
,
435 .features
= PENTIUM_FEATURES
,
444 .features
= PENTIUM2_FEATURES
,
453 .features
= PENTIUM3_FEATURES
,
459 .vendor1
= CPUID_VENDOR_AMD_1
,
460 .vendor2
= CPUID_VENDOR_AMD_2
,
461 .vendor3
= CPUID_VENDOR_AMD_3
,
465 .features
= PPRO_FEATURES
| CPUID_PSE36
| CPUID_VME
| CPUID_MTRR
| CPUID_MCA
,
466 .ext2_features
= (PPRO_FEATURES
& EXT2_FEATURE_MASK
) | CPUID_EXT2_MMXEXT
| CPUID_EXT2_3DNOW
| CPUID_EXT2_3DNOWEXT
,
467 .xlevel
= 0x80000008,
471 /* original is on level 10 */
476 .features
= PPRO_FEATURES
|
477 CPUID_MTRR
| CPUID_CLFLUSH
| CPUID_MCA
| CPUID_VME
| CPUID_DTS
|
478 CPUID_ACPI
| CPUID_SS
| CPUID_HT
| CPUID_TM
| CPUID_PBE
,
479 /* Some CPUs got no CPUID_SEP */
480 .ext_features
= CPUID_EXT_SSE3
| CPUID_EXT_MONITOR
| CPUID_EXT_SSSE3
|
481 CPUID_EXT_DSCPL
| CPUID_EXT_EST
| CPUID_EXT_TM2
| CPUID_EXT_XTPR
,
482 .ext2_features
= (PPRO_FEATURES
& EXT2_FEATURE_MASK
) | CPUID_EXT2_NX
,
483 .ext3_features
= CPUID_EXT3_LAHF_LM
,
484 .xlevel
= 0x8000000A,
485 .model_id
= "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
489 static int cpu_x86_fill_model_id(char *str
)
491 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
494 for (i
= 0; i
< 3; i
++) {
495 host_cpuid(0x80000002 + i
, 0, &eax
, &ebx
, &ecx
, &edx
);
496 memcpy(str
+ i
* 16 + 0, &eax
, 4);
497 memcpy(str
+ i
* 16 + 4, &ebx
, 4);
498 memcpy(str
+ i
* 16 + 8, &ecx
, 4);
499 memcpy(str
+ i
* 16 + 12, &edx
, 4);
504 static int cpu_x86_fill_host(x86_def_t
*x86_cpu_def
)
506 uint32_t eax
= 0, ebx
= 0, ecx
= 0, edx
= 0;
508 x86_cpu_def
->name
= "host";
509 host_cpuid(0x0, 0, &eax
, &ebx
, &ecx
, &edx
);
510 x86_cpu_def
->level
= eax
;
511 x86_cpu_def
->vendor1
= ebx
;
512 x86_cpu_def
->vendor2
= edx
;
513 x86_cpu_def
->vendor3
= ecx
;
515 host_cpuid(0x1, 0, &eax
, &ebx
, &ecx
, &edx
);
516 x86_cpu_def
->family
= ((eax
>> 8) & 0x0F) + ((eax
>> 20) & 0xFF);
517 x86_cpu_def
->model
= ((eax
>> 4) & 0x0F) | ((eax
& 0xF0000) >> 12);
518 x86_cpu_def
->stepping
= eax
& 0x0F;
519 x86_cpu_def
->ext_features
= ecx
;
520 x86_cpu_def
->features
= edx
;
522 if (kvm_enabled() && x86_cpu_def
->level
>= 7) {
523 x86_cpu_def
->cpuid_7_0_ebx_features
= kvm_arch_get_supported_cpuid(kvm_state
, 0x7, 0, R_EBX
);
525 x86_cpu_def
->cpuid_7_0_ebx_features
= 0;
528 host_cpuid(0x80000000, 0, &eax
, &ebx
, &ecx
, &edx
);
529 x86_cpu_def
->xlevel
= eax
;
531 host_cpuid(0x80000001, 0, &eax
, &ebx
, &ecx
, &edx
);
532 x86_cpu_def
->ext2_features
= edx
;
533 x86_cpu_def
->ext3_features
= ecx
;
534 cpu_x86_fill_model_id(x86_cpu_def
->model_id
);
535 x86_cpu_def
->vendor_override
= 0;
537 /* Call Centaur's CPUID instruction. */
538 if (x86_cpu_def
->vendor1
== CPUID_VENDOR_VIA_1
&&
539 x86_cpu_def
->vendor2
== CPUID_VENDOR_VIA_2
&&
540 x86_cpu_def
->vendor3
== CPUID_VENDOR_VIA_3
) {
541 host_cpuid(0xC0000000, 0, &eax
, &ebx
, &ecx
, &edx
);
542 if (eax
>= 0xC0000001) {
543 /* Support VIA max extended level */
544 x86_cpu_def
->xlevel2
= eax
;
545 host_cpuid(0xC0000001, 0, &eax
, &ebx
, &ecx
, &edx
);
546 x86_cpu_def
->ext4_features
= edx
;
551 * Every SVM feature requires emulation support in KVM - so we can't just
552 * read the host features here. KVM might even support SVM features not
553 * available on the host hardware. Just set all bits and mask out the
554 * unsupported ones later.
556 x86_cpu_def
->svm_features
= -1;
561 static int unavailable_host_feature(struct model_features_t
*f
, uint32_t mask
)
565 for (i
= 0; i
< 32; ++i
)
567 fprintf(stderr
, "warning: host cpuid %04x_%04x lacks requested"
568 " flag '%s' [0x%08x]\n",
569 f
->cpuid
>> 16, f
->cpuid
& 0xffff,
570 f
->flag_names
[i
] ? f
->flag_names
[i
] : "[reserved]", mask
);
576 /* best effort attempt to inform user requested cpu flags aren't making
577 * their way to the guest. Note: ft[].check_feat ideally should be
578 * specified via a guest_def field to suppress report of extraneous flags.
580 static int check_features_against_host(x86_def_t
*guest_def
)
585 struct model_features_t ft
[] = {
586 {&guest_def
->features
, &host_def
.features
,
587 ~0, feature_name
, 0x00000000},
588 {&guest_def
->ext_features
, &host_def
.ext_features
,
589 ~CPUID_EXT_HYPERVISOR
, ext_feature_name
, 0x00000001},
590 {&guest_def
->ext2_features
, &host_def
.ext2_features
,
591 ~PPRO_FEATURES
, ext2_feature_name
, 0x80000000},
592 {&guest_def
->ext3_features
, &host_def
.ext3_features
,
593 ~CPUID_EXT3_SVM
, ext3_feature_name
, 0x80000001}};
595 cpu_x86_fill_host(&host_def
);
596 for (rv
= 0, i
= 0; i
< ARRAY_SIZE(ft
); ++i
)
597 for (mask
= 1; mask
; mask
<<= 1)
598 if (ft
[i
].check_feat
& mask
&& *ft
[i
].guest_feat
& mask
&&
599 !(*ft
[i
].host_feat
& mask
)) {
600 unavailable_host_feature(&ft
[i
], mask
);
606 static void x86_cpuid_version_get_family(Object
*obj
, Visitor
*v
, void *opaque
,
607 const char *name
, Error
**errp
)
609 X86CPU
*cpu
= X86_CPU(obj
);
610 CPUX86State
*env
= &cpu
->env
;
613 value
= (env
->cpuid_version
>> 8) & 0xf;
615 value
+= (env
->cpuid_version
>> 20) & 0xff;
617 visit_type_int(v
, &value
, name
, errp
);
620 static void x86_cpuid_version_set_family(Object
*obj
, Visitor
*v
, void *opaque
,
621 const char *name
, Error
**errp
)
623 X86CPU
*cpu
= X86_CPU(obj
);
624 CPUX86State
*env
= &cpu
->env
;
625 const int64_t min
= 0;
626 const int64_t max
= 0xff + 0xf;
629 visit_type_int(v
, &value
, name
, errp
);
630 if (error_is_set(errp
)) {
633 if (value
< min
|| value
> max
) {
634 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
635 name
? name
: "null", value
, min
, max
);
639 env
->cpuid_version
&= ~0xff00f00;
641 env
->cpuid_version
|= 0xf00 | ((value
- 0x0f) << 20);
643 env
->cpuid_version
|= value
<< 8;
647 static void x86_cpuid_version_get_model(Object
*obj
, Visitor
*v
, void *opaque
,
648 const char *name
, Error
**errp
)
650 X86CPU
*cpu
= X86_CPU(obj
);
651 CPUX86State
*env
= &cpu
->env
;
654 value
= (env
->cpuid_version
>> 4) & 0xf;
655 value
|= ((env
->cpuid_version
>> 16) & 0xf) << 4;
656 visit_type_int(v
, &value
, name
, errp
);
659 static void x86_cpuid_version_set_model(Object
*obj
, Visitor
*v
, void *opaque
,
660 const char *name
, Error
**errp
)
662 X86CPU
*cpu
= X86_CPU(obj
);
663 CPUX86State
*env
= &cpu
->env
;
664 const int64_t min
= 0;
665 const int64_t max
= 0xff;
668 visit_type_int(v
, &value
, name
, errp
);
669 if (error_is_set(errp
)) {
672 if (value
< min
|| value
> max
) {
673 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
674 name
? name
: "null", value
, min
, max
);
678 env
->cpuid_version
&= ~0xf00f0;
679 env
->cpuid_version
|= ((value
& 0xf) << 4) | ((value
>> 4) << 16);
682 static void x86_cpuid_version_get_stepping(Object
*obj
, Visitor
*v
,
683 void *opaque
, const char *name
,
686 X86CPU
*cpu
= X86_CPU(obj
);
687 CPUX86State
*env
= &cpu
->env
;
690 value
= env
->cpuid_version
& 0xf;
691 visit_type_int(v
, &value
, name
, errp
);
694 static void x86_cpuid_version_set_stepping(Object
*obj
, Visitor
*v
,
695 void *opaque
, const char *name
,
698 X86CPU
*cpu
= X86_CPU(obj
);
699 CPUX86State
*env
= &cpu
->env
;
700 const int64_t min
= 0;
701 const int64_t max
= 0xf;
704 visit_type_int(v
, &value
, name
, errp
);
705 if (error_is_set(errp
)) {
708 if (value
< min
|| value
> max
) {
709 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
710 name
? name
: "null", value
, min
, max
);
714 env
->cpuid_version
&= ~0xf;
715 env
->cpuid_version
|= value
& 0xf;
718 static void x86_cpuid_get_level(Object
*obj
, Visitor
*v
, void *opaque
,
719 const char *name
, Error
**errp
)
721 X86CPU
*cpu
= X86_CPU(obj
);
723 visit_type_uint32(v
, &cpu
->env
.cpuid_level
, name
, errp
);
726 static void x86_cpuid_set_level(Object
*obj
, Visitor
*v
, void *opaque
,
727 const char *name
, Error
**errp
)
729 X86CPU
*cpu
= X86_CPU(obj
);
731 visit_type_uint32(v
, &cpu
->env
.cpuid_level
, name
, errp
);
734 static void x86_cpuid_get_xlevel(Object
*obj
, Visitor
*v
, void *opaque
,
735 const char *name
, Error
**errp
)
737 X86CPU
*cpu
= X86_CPU(obj
);
739 visit_type_uint32(v
, &cpu
->env
.cpuid_xlevel
, name
, errp
);
742 static void x86_cpuid_set_xlevel(Object
*obj
, Visitor
*v
, void *opaque
,
743 const char *name
, Error
**errp
)
745 X86CPU
*cpu
= X86_CPU(obj
);
747 visit_type_uint32(v
, &cpu
->env
.cpuid_xlevel
, name
, errp
);
750 static char *x86_cpuid_get_vendor(Object
*obj
, Error
**errp
)
752 X86CPU
*cpu
= X86_CPU(obj
);
753 CPUX86State
*env
= &cpu
->env
;
757 value
= (char *)g_malloc(12 + 1);
758 for (i
= 0; i
< 4; i
++) {
759 value
[i
] = env
->cpuid_vendor1
>> (8 * i
);
760 value
[i
+ 4] = env
->cpuid_vendor2
>> (8 * i
);
761 value
[i
+ 8] = env
->cpuid_vendor3
>> (8 * i
);
767 static void x86_cpuid_set_vendor(Object
*obj
, const char *value
,
770 X86CPU
*cpu
= X86_CPU(obj
);
771 CPUX86State
*env
= &cpu
->env
;
774 if (strlen(value
) != 12) {
775 error_set(errp
, QERR_PROPERTY_VALUE_BAD
, "",
780 env
->cpuid_vendor1
= 0;
781 env
->cpuid_vendor2
= 0;
782 env
->cpuid_vendor3
= 0;
783 for (i
= 0; i
< 4; i
++) {
784 env
->cpuid_vendor1
|= ((uint8_t)value
[i
]) << (8 * i
);
785 env
->cpuid_vendor2
|= ((uint8_t)value
[i
+ 4]) << (8 * i
);
786 env
->cpuid_vendor3
|= ((uint8_t)value
[i
+ 8]) << (8 * i
);
788 env
->cpuid_vendor_override
= 1;
791 static char *x86_cpuid_get_model_id(Object
*obj
, Error
**errp
)
793 X86CPU
*cpu
= X86_CPU(obj
);
794 CPUX86State
*env
= &cpu
->env
;
798 value
= g_malloc(48 + 1);
799 for (i
= 0; i
< 48; i
++) {
800 value
[i
] = env
->cpuid_model
[i
>> 2] >> (8 * (i
& 3));
806 static void x86_cpuid_set_model_id(Object
*obj
, const char *model_id
,
809 X86CPU
*cpu
= X86_CPU(obj
);
810 CPUX86State
*env
= &cpu
->env
;
813 if (model_id
== NULL
) {
816 len
= strlen(model_id
);
817 memset(env
->cpuid_model
, 0, 48);
818 for (i
= 0; i
< 48; i
++) {
822 c
= (uint8_t)model_id
[i
];
824 env
->cpuid_model
[i
>> 2] |= c
<< (8 * (i
& 3));
828 static void x86_cpuid_get_tsc_freq(Object
*obj
, Visitor
*v
, void *opaque
,
829 const char *name
, Error
**errp
)
831 X86CPU
*cpu
= X86_CPU(obj
);
834 value
= cpu
->env
.tsc_khz
* 1000;
835 visit_type_int(v
, &value
, name
, errp
);
838 static void x86_cpuid_set_tsc_freq(Object
*obj
, Visitor
*v
, void *opaque
,
839 const char *name
, Error
**errp
)
841 X86CPU
*cpu
= X86_CPU(obj
);
842 const int64_t min
= 0;
843 const int64_t max
= INT_MAX
;
846 visit_type_int(v
, &value
, name
, errp
);
847 if (error_is_set(errp
)) {
850 if (value
< min
|| value
> max
) {
851 error_set(errp
, QERR_PROPERTY_VALUE_OUT_OF_RANGE
, "",
852 name
? name
: "null", value
, min
, max
);
856 cpu
->env
.tsc_khz
= value
/ 1000;
859 static int cpu_x86_find_by_name(x86_def_t
*x86_cpu_def
, const char *cpu_model
)
864 char *s
= g_strdup(cpu_model
);
865 char *featurestr
, *name
= strtok(s
, ",");
866 /* Features to be added*/
867 uint32_t plus_features
= 0, plus_ext_features
= 0;
868 uint32_t plus_ext2_features
= 0, plus_ext3_features
= 0;
869 uint32_t plus_kvm_features
= 0, plus_svm_features
= 0;
870 /* Features to be removed */
871 uint32_t minus_features
= 0, minus_ext_features
= 0;
872 uint32_t minus_ext2_features
= 0, minus_ext3_features
= 0;
873 uint32_t minus_kvm_features
= 0, minus_svm_features
= 0;
876 for (def
= x86_defs
; def
; def
= def
->next
)
877 if (name
&& !strcmp(name
, def
->name
))
879 if (kvm_enabled() && name
&& strcmp(name
, "host") == 0) {
880 cpu_x86_fill_host(x86_cpu_def
);
884 memcpy(x86_cpu_def
, def
, sizeof(*def
));
887 plus_kvm_features
= ~0; /* not supported bits will be filtered out later */
889 add_flagname_to_bitmaps("hypervisor", &plus_features
,
890 &plus_ext_features
, &plus_ext2_features
, &plus_ext3_features
,
891 &plus_kvm_features
, &plus_svm_features
);
893 featurestr
= strtok(NULL
, ",");
897 if (featurestr
[0] == '+') {
898 add_flagname_to_bitmaps(featurestr
+ 1, &plus_features
,
899 &plus_ext_features
, &plus_ext2_features
,
900 &plus_ext3_features
, &plus_kvm_features
,
902 } else if (featurestr
[0] == '-') {
903 add_flagname_to_bitmaps(featurestr
+ 1, &minus_features
,
904 &minus_ext_features
, &minus_ext2_features
,
905 &minus_ext3_features
, &minus_kvm_features
,
906 &minus_svm_features
);
907 } else if ((val
= strchr(featurestr
, '='))) {
909 if (!strcmp(featurestr
, "family")) {
911 numvalue
= strtoul(val
, &err
, 0);
912 if (!*val
|| *err
|| numvalue
> 0xff + 0xf) {
913 fprintf(stderr
, "bad numerical value %s\n", val
);
916 x86_cpu_def
->family
= numvalue
;
917 } else if (!strcmp(featurestr
, "model")) {
919 numvalue
= strtoul(val
, &err
, 0);
920 if (!*val
|| *err
|| numvalue
> 0xff) {
921 fprintf(stderr
, "bad numerical value %s\n", val
);
924 x86_cpu_def
->model
= numvalue
;
925 } else if (!strcmp(featurestr
, "stepping")) {
927 numvalue
= strtoul(val
, &err
, 0);
928 if (!*val
|| *err
|| numvalue
> 0xf) {
929 fprintf(stderr
, "bad numerical value %s\n", val
);
932 x86_cpu_def
->stepping
= numvalue
;
933 } else if (!strcmp(featurestr
, "level")) {
935 numvalue
= strtoul(val
, &err
, 0);
937 fprintf(stderr
, "bad numerical value %s\n", val
);
940 x86_cpu_def
->level
= numvalue
;
941 } else if (!strcmp(featurestr
, "xlevel")) {
943 numvalue
= strtoul(val
, &err
, 0);
945 fprintf(stderr
, "bad numerical value %s\n", val
);
948 if (numvalue
< 0x80000000) {
949 numvalue
+= 0x80000000;
951 x86_cpu_def
->xlevel
= numvalue
;
952 } else if (!strcmp(featurestr
, "vendor")) {
953 if (strlen(val
) != 12) {
954 fprintf(stderr
, "vendor string must be 12 chars long\n");
957 x86_cpu_def
->vendor1
= 0;
958 x86_cpu_def
->vendor2
= 0;
959 x86_cpu_def
->vendor3
= 0;
960 for(i
= 0; i
< 4; i
++) {
961 x86_cpu_def
->vendor1
|= ((uint8_t)val
[i
]) << (8 * i
);
962 x86_cpu_def
->vendor2
|= ((uint8_t)val
[i
+ 4]) << (8 * i
);
963 x86_cpu_def
->vendor3
|= ((uint8_t)val
[i
+ 8]) << (8 * i
);
965 x86_cpu_def
->vendor_override
= 1;
966 } else if (!strcmp(featurestr
, "model_id")) {
967 pstrcpy(x86_cpu_def
->model_id
, sizeof(x86_cpu_def
->model_id
),
969 } else if (!strcmp(featurestr
, "tsc_freq")) {
973 tsc_freq
= strtosz_suffix_unit(val
, &err
,
974 STRTOSZ_DEFSUFFIX_B
, 1000);
975 if (tsc_freq
< 0 || *err
) {
976 fprintf(stderr
, "bad numerical value %s\n", val
);
979 x86_cpu_def
->tsc_khz
= tsc_freq
/ 1000;
980 } else if (!strcmp(featurestr
, "hv_spinlocks")) {
982 numvalue
= strtoul(val
, &err
, 0);
984 fprintf(stderr
, "bad numerical value %s\n", val
);
987 hyperv_set_spinlock_retries(numvalue
);
989 fprintf(stderr
, "unrecognized feature %s\n", featurestr
);
992 } else if (!strcmp(featurestr
, "check")) {
994 } else if (!strcmp(featurestr
, "enforce")) {
995 check_cpuid
= enforce_cpuid
= 1;
996 } else if (!strcmp(featurestr
, "hv_relaxed")) {
997 hyperv_enable_relaxed_timing(true);
998 } else if (!strcmp(featurestr
, "hv_vapic")) {
999 hyperv_enable_vapic_recommended(true);
1001 fprintf(stderr
, "feature string `%s' not in format (+feature|-feature|feature=xyz)\n", featurestr
);
1004 featurestr
= strtok(NULL
, ",");
1006 x86_cpu_def
->features
|= plus_features
;
1007 x86_cpu_def
->ext_features
|= plus_ext_features
;
1008 x86_cpu_def
->ext2_features
|= plus_ext2_features
;
1009 x86_cpu_def
->ext3_features
|= plus_ext3_features
;
1010 x86_cpu_def
->kvm_features
|= plus_kvm_features
;
1011 x86_cpu_def
->svm_features
|= plus_svm_features
;
1012 x86_cpu_def
->features
&= ~minus_features
;
1013 x86_cpu_def
->ext_features
&= ~minus_ext_features
;
1014 x86_cpu_def
->ext2_features
&= ~minus_ext2_features
;
1015 x86_cpu_def
->ext3_features
&= ~minus_ext3_features
;
1016 x86_cpu_def
->kvm_features
&= ~minus_kvm_features
;
1017 x86_cpu_def
->svm_features
&= ~minus_svm_features
;
1019 if (check_features_against_host(x86_cpu_def
) && enforce_cpuid
)
1030 /* generate a composite string into buf of all cpuid names in featureset
1031 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1032 * if flags, suppress names undefined in featureset.
1034 static void listflags(char *buf
, int bufsize
, uint32_t fbits
,
1035 const char **featureset
, uint32_t flags
)
1037 const char **p
= &featureset
[31];
1041 b
= 4 <= bufsize
? buf
+ (bufsize
-= 3) - 1 : NULL
;
1043 for (q
= buf
, bit
= 31; fbits
&& bufsize
; --p
, fbits
&= ~(1 << bit
), --bit
)
1044 if (fbits
& 1 << bit
&& (*p
|| !flags
)) {
1046 nc
= snprintf(q
, bufsize
, "%s%s", q
== buf
? "" : " ", *p
);
1048 nc
= snprintf(q
, bufsize
, "%s[%d]", q
== buf
? "" : " ", bit
);
1049 if (bufsize
<= nc
) {
1051 memcpy(b
, "...", sizeof("..."));
1060 /* generate CPU information:
1061 * -? list model names
1062 * -?model list model names/IDs
1063 * -?dump output all model (x86_def_t) data
1064 * -?cpuid list all recognized cpuid flag names
1066 void x86_cpu_list(FILE *f
, fprintf_function cpu_fprintf
, const char *optarg
)
1068 unsigned char model
= !strcmp("?model", optarg
);
1069 unsigned char dump
= !strcmp("?dump", optarg
);
1070 unsigned char cpuid
= !strcmp("?cpuid", optarg
);
1075 (*cpu_fprintf
)(f
, "Recognized CPUID flags:\n");
1076 listflags(buf
, sizeof (buf
), (uint32_t)~0, feature_name
, 1);
1077 (*cpu_fprintf
)(f
, " f_edx: %s\n", buf
);
1078 listflags(buf
, sizeof (buf
), (uint32_t)~0, ext_feature_name
, 1);
1079 (*cpu_fprintf
)(f
, " f_ecx: %s\n", buf
);
1080 listflags(buf
, sizeof (buf
), (uint32_t)~0, ext2_feature_name
, 1);
1081 (*cpu_fprintf
)(f
, " extf_edx: %s\n", buf
);
1082 listflags(buf
, sizeof (buf
), (uint32_t)~0, ext3_feature_name
, 1);
1083 (*cpu_fprintf
)(f
, " extf_ecx: %s\n", buf
);
1086 for (def
= x86_defs
; def
; def
= def
->next
) {
1087 snprintf(buf
, sizeof (buf
), def
->flags
? "[%s]": "%s", def
->name
);
1088 if (model
|| dump
) {
1089 (*cpu_fprintf
)(f
, "x86 %16s %-48s\n", buf
, def
->model_id
);
1091 (*cpu_fprintf
)(f
, "x86 %16s\n", buf
);
1094 memcpy(buf
, &def
->vendor1
, sizeof (def
->vendor1
));
1095 memcpy(buf
+ 4, &def
->vendor2
, sizeof (def
->vendor2
));
1096 memcpy(buf
+ 8, &def
->vendor3
, sizeof (def
->vendor3
));
1099 " family %d model %d stepping %d level %d xlevel 0x%x"
1101 def
->family
, def
->model
, def
->stepping
, def
->level
,
1103 listflags(buf
, sizeof (buf
), def
->features
, feature_name
, 0);
1104 (*cpu_fprintf
)(f
, " feature_edx %08x (%s)\n", def
->features
,
1106 listflags(buf
, sizeof (buf
), def
->ext_features
, ext_feature_name
,
1108 (*cpu_fprintf
)(f
, " feature_ecx %08x (%s)\n", def
->ext_features
,
1110 listflags(buf
, sizeof (buf
), def
->ext2_features
, ext2_feature_name
,
1112 (*cpu_fprintf
)(f
, " extfeature_edx %08x (%s)\n",
1113 def
->ext2_features
, buf
);
1114 listflags(buf
, sizeof (buf
), def
->ext3_features
, ext3_feature_name
,
1116 (*cpu_fprintf
)(f
, " extfeature_ecx %08x (%s)\n",
1117 def
->ext3_features
, buf
);
1118 (*cpu_fprintf
)(f
, "\n");
1121 if (kvm_enabled()) {
1122 (*cpu_fprintf
)(f
, "x86 %16s\n", "[host]");
1126 int cpu_x86_register(X86CPU
*cpu
, const char *cpu_model
)
1128 CPUX86State
*env
= &cpu
->env
;
1129 x86_def_t def1
, *def
= &def1
;
1130 Error
*error
= NULL
;
1132 memset(def
, 0, sizeof(*def
));
1134 if (cpu_x86_find_by_name(def
, cpu_model
) < 0)
1137 env
->cpuid_vendor1
= def
->vendor1
;
1138 env
->cpuid_vendor2
= def
->vendor2
;
1139 env
->cpuid_vendor3
= def
->vendor3
;
1141 env
->cpuid_vendor1
= CPUID_VENDOR_INTEL_1
;
1142 env
->cpuid_vendor2
= CPUID_VENDOR_INTEL_2
;
1143 env
->cpuid_vendor3
= CPUID_VENDOR_INTEL_3
;
1145 env
->cpuid_vendor_override
= def
->vendor_override
;
1146 object_property_set_int(OBJECT(cpu
), def
->level
, "level", &error
);
1147 object_property_set_int(OBJECT(cpu
), def
->family
, "family", &error
);
1148 object_property_set_int(OBJECT(cpu
), def
->model
, "model", &error
);
1149 object_property_set_int(OBJECT(cpu
), def
->stepping
, "stepping", &error
);
1150 env
->cpuid_features
= def
->features
;
1151 env
->cpuid_ext_features
= def
->ext_features
;
1152 env
->cpuid_ext2_features
= def
->ext2_features
;
1153 env
->cpuid_ext3_features
= def
->ext3_features
;
1154 object_property_set_int(OBJECT(cpu
), def
->xlevel
, "xlevel", &error
);
1155 env
->cpuid_kvm_features
= def
->kvm_features
;
1156 env
->cpuid_svm_features
= def
->svm_features
;
1157 env
->cpuid_ext4_features
= def
->ext4_features
;
1158 env
->cpuid_7_0_ebx
= def
->cpuid_7_0_ebx_features
;
1159 env
->cpuid_xlevel2
= def
->xlevel2
;
1160 object_property_set_int(OBJECT(cpu
), (int64_t)def
->tsc_khz
* 1000,
1161 "tsc-frequency", &error
);
1162 if (!kvm_enabled()) {
1163 env
->cpuid_features
&= TCG_FEATURES
;
1164 env
->cpuid_ext_features
&= TCG_EXT_FEATURES
;
1165 env
->cpuid_ext2_features
&= (TCG_EXT2_FEATURES
1166 #ifdef TARGET_X86_64
1167 | CPUID_EXT2_SYSCALL
| CPUID_EXT2_LM
1170 env
->cpuid_ext3_features
&= TCG_EXT3_FEATURES
;
1171 env
->cpuid_svm_features
&= TCG_SVM_FEATURES
;
1173 object_property_set_str(OBJECT(cpu
), def
->model_id
, "model-id", &error
);
1174 if (error_is_set(&error
)) {
1181 #if !defined(CONFIG_USER_ONLY)
1182 /* copy vendor id string to 32 bit register, nul pad as needed
1184 static void cpyid(const char *s
, uint32_t *id
)
1186 char *d
= (char *)id
;
1189 for (i
= sizeof (*id
); i
--; )
1190 *d
++ = *s
? *s
++ : '\0';
1193 /* interpret radix and convert from string to arbitrary scalar,
1194 * otherwise flag failure
1196 #define setscalar(pval, str, perr) \
1201 ul = strtoul(str, &pend, 0); \
1202 *str && !*pend ? (*pval = ul) : (*perr = 1); \
1205 /* map cpuid options to feature bits, otherwise return failure
1206 * (option tags in *str are delimited by whitespace)
1208 static void setfeatures(uint32_t *pval
, const char *str
,
1209 const char **featureset
, int *perr
)
1213 for (q
= p
= str
; *p
|| *q
; q
= p
) {
1216 while (*p
&& !iswhite(*p
))
1220 if (!lookup_feature(pval
, q
, p
, featureset
)) {
1221 fprintf(stderr
, "error: feature \"%.*s\" not available in set\n",
1229 /* map config file options to x86_def_t form
1231 static int cpudef_setfield(const char *name
, const char *str
, void *opaque
)
1233 x86_def_t
*def
= opaque
;
1236 if (!strcmp(name
, "name")) {
1237 g_free((void *)def
->name
);
1238 def
->name
= g_strdup(str
);
1239 } else if (!strcmp(name
, "model_id")) {
1240 strncpy(def
->model_id
, str
, sizeof (def
->model_id
));
1241 } else if (!strcmp(name
, "level")) {
1242 setscalar(&def
->level
, str
, &err
)
1243 } else if (!strcmp(name
, "vendor")) {
1244 cpyid(&str
[0], &def
->vendor1
);
1245 cpyid(&str
[4], &def
->vendor2
);
1246 cpyid(&str
[8], &def
->vendor3
);
1247 } else if (!strcmp(name
, "family")) {
1248 setscalar(&def
->family
, str
, &err
)
1249 } else if (!strcmp(name
, "model")) {
1250 setscalar(&def
->model
, str
, &err
)
1251 } else if (!strcmp(name
, "stepping")) {
1252 setscalar(&def
->stepping
, str
, &err
)
1253 } else if (!strcmp(name
, "feature_edx")) {
1254 setfeatures(&def
->features
, str
, feature_name
, &err
);
1255 } else if (!strcmp(name
, "feature_ecx")) {
1256 setfeatures(&def
->ext_features
, str
, ext_feature_name
, &err
);
1257 } else if (!strcmp(name
, "extfeature_edx")) {
1258 setfeatures(&def
->ext2_features
, str
, ext2_feature_name
, &err
);
1259 } else if (!strcmp(name
, "extfeature_ecx")) {
1260 setfeatures(&def
->ext3_features
, str
, ext3_feature_name
, &err
);
1261 } else if (!strcmp(name
, "xlevel")) {
1262 setscalar(&def
->xlevel
, str
, &err
)
1264 fprintf(stderr
, "error: unknown option [%s = %s]\n", name
, str
);
1268 fprintf(stderr
, "error: bad option value [%s = %s]\n", name
, str
);
1274 /* register config file entry as x86_def_t
1276 static int cpudef_register(QemuOpts
*opts
, void *opaque
)
1278 x86_def_t
*def
= g_malloc0(sizeof (x86_def_t
));
1280 qemu_opt_foreach(opts
, cpudef_setfield
, def
, 1);
1281 def
->next
= x86_defs
;
1286 void cpu_clear_apic_feature(CPUX86State
*env
)
1288 env
->cpuid_features
&= ~CPUID_APIC
;
1291 #endif /* !CONFIG_USER_ONLY */
1293 /* register "cpudef" models defined in configuration file. Here we first
1294 * preload any built-in definitions
1296 void x86_cpudef_setup(void)
1299 static const char *model_with_versions
[] = { "qemu32", "qemu64", "athlon" };
1301 for (i
= 0; i
< ARRAY_SIZE(builtin_x86_defs
); ++i
) {
1302 builtin_x86_defs
[i
].next
= x86_defs
;
1303 builtin_x86_defs
[i
].flags
= 1;
1305 /* Look for specific "cpudef" models that */
1306 /* have the QEMU version in .model_id */
1307 for (j
= 0; j
< ARRAY_SIZE(model_with_versions
); j
++) {
1308 if (strcmp(model_with_versions
[j
], builtin_x86_defs
[i
].name
) == 0) {
1309 pstrcpy(builtin_x86_defs
[i
].model_id
, sizeof(builtin_x86_defs
[i
].model_id
), "QEMU Virtual CPU version ");
1310 pstrcat(builtin_x86_defs
[i
].model_id
, sizeof(builtin_x86_defs
[i
].model_id
), qemu_get_version());
1315 x86_defs
= &builtin_x86_defs
[i
];
1317 #if !defined(CONFIG_USER_ONLY)
1318 qemu_opts_foreach(qemu_find_opts("cpudef"), cpudef_register
, NULL
, 0);
1322 static void get_cpuid_vendor(CPUX86State
*env
, uint32_t *ebx
,
1323 uint32_t *ecx
, uint32_t *edx
)
1325 *ebx
= env
->cpuid_vendor1
;
1326 *edx
= env
->cpuid_vendor2
;
1327 *ecx
= env
->cpuid_vendor3
;
1329 /* sysenter isn't supported on compatibility mode on AMD, syscall
1330 * isn't supported in compatibility mode on Intel.
1331 * Normally we advertise the actual cpu vendor, but you can override
1332 * this if you want to use KVM's sysenter/syscall emulation
1333 * in compatibility mode and when doing cross vendor migration
1335 if (kvm_enabled() && ! env
->cpuid_vendor_override
) {
1336 host_cpuid(0, 0, NULL
, ebx
, ecx
, edx
);
1340 void cpu_x86_cpuid(CPUX86State
*env
, uint32_t index
, uint32_t count
,
1341 uint32_t *eax
, uint32_t *ebx
,
1342 uint32_t *ecx
, uint32_t *edx
)
1344 /* test if maximum index reached */
1345 if (index
& 0x80000000) {
1346 if (index
> env
->cpuid_xlevel
) {
1347 if (env
->cpuid_xlevel2
> 0) {
1348 /* Handle the Centaur's CPUID instruction. */
1349 if (index
> env
->cpuid_xlevel2
) {
1350 index
= env
->cpuid_xlevel2
;
1351 } else if (index
< 0xC0000000) {
1352 index
= env
->cpuid_xlevel
;
1355 index
= env
->cpuid_xlevel
;
1359 if (index
> env
->cpuid_level
)
1360 index
= env
->cpuid_level
;
1365 *eax
= env
->cpuid_level
;
1366 get_cpuid_vendor(env
, ebx
, ecx
, edx
);
1369 *eax
= env
->cpuid_version
;
1370 *ebx
= (env
->cpuid_apic_id
<< 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
1371 *ecx
= env
->cpuid_ext_features
;
1372 *edx
= env
->cpuid_features
;
1373 if (env
->nr_cores
* env
->nr_threads
> 1) {
1374 *ebx
|= (env
->nr_cores
* env
->nr_threads
) << 16;
1375 *edx
|= 1 << 28; /* HTT bit */
1379 /* cache info: needed for Pentium Pro compatibility */
1386 /* cache info: needed for Core compatibility */
1387 if (env
->nr_cores
> 1) {
1388 *eax
= (env
->nr_cores
- 1) << 26;
1393 case 0: /* L1 dcache info */
1399 case 1: /* L1 icache info */
1405 case 2: /* L2 cache info */
1407 if (env
->nr_threads
> 1) {
1408 *eax
|= (env
->nr_threads
- 1) << 14;
1414 default: /* end of info */
1423 /* mwait info: needed for Core compatibility */
1424 *eax
= 0; /* Smallest monitor-line size in bytes */
1425 *ebx
= 0; /* Largest monitor-line size in bytes */
1426 *ecx
= CPUID_MWAIT_EMX
| CPUID_MWAIT_IBE
;
1430 /* Thermal and Power Leaf */
1437 /* Structured Extended Feature Flags Enumeration Leaf */
1439 *eax
= 0; /* Maximum ECX value for sub-leaves */
1440 *ebx
= env
->cpuid_7_0_ebx
; /* Feature flags */
1441 *ecx
= 0; /* Reserved */
1442 *edx
= 0; /* Reserved */
1451 /* Direct Cache Access Information Leaf */
1452 *eax
= 0; /* Bits 0-31 in DCA_CAP MSR */
1458 /* Architectural Performance Monitoring Leaf */
1459 if (kvm_enabled()) {
1460 KVMState
*s
= env
->kvm_state
;
1462 *eax
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EAX
);
1463 *ebx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EBX
);
1464 *ecx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_ECX
);
1465 *edx
= kvm_arch_get_supported_cpuid(s
, 0xA, count
, R_EDX
);
1474 /* Processor Extended State */
1475 if (!(env
->cpuid_ext_features
& CPUID_EXT_XSAVE
)) {
1482 if (kvm_enabled()) {
1483 KVMState
*s
= env
->kvm_state
;
1485 *eax
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_EAX
);
1486 *ebx
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_EBX
);
1487 *ecx
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_ECX
);
1488 *edx
= kvm_arch_get_supported_cpuid(s
, 0xd, count
, R_EDX
);
1497 *eax
= env
->cpuid_xlevel
;
1498 *ebx
= env
->cpuid_vendor1
;
1499 *edx
= env
->cpuid_vendor2
;
1500 *ecx
= env
->cpuid_vendor3
;
1503 *eax
= env
->cpuid_version
;
1505 *ecx
= env
->cpuid_ext3_features
;
1506 *edx
= env
->cpuid_ext2_features
;
1508 /* The Linux kernel checks for the CMPLegacy bit and
1509 * discards multiple thread information if it is set.
1510 * So dont set it here for Intel to make Linux guests happy.
1512 if (env
->nr_cores
* env
->nr_threads
> 1) {
1513 uint32_t tebx
, tecx
, tedx
;
1514 get_cpuid_vendor(env
, &tebx
, &tecx
, &tedx
);
1515 if (tebx
!= CPUID_VENDOR_INTEL_1
||
1516 tedx
!= CPUID_VENDOR_INTEL_2
||
1517 tecx
!= CPUID_VENDOR_INTEL_3
) {
1518 *ecx
|= 1 << 1; /* CmpLegacy bit */
1525 *eax
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 0];
1526 *ebx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 1];
1527 *ecx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 2];
1528 *edx
= env
->cpuid_model
[(index
- 0x80000002) * 4 + 3];
1531 /* cache info (L1 cache) */
1538 /* cache info (L2 cache) */
1545 /* virtual & phys address size in low 2 bytes. */
1546 /* XXX: This value must match the one used in the MMU code. */
1547 if (env
->cpuid_ext2_features
& CPUID_EXT2_LM
) {
1548 /* 64 bit processor */
1549 /* XXX: The physical address space is limited to 42 bits in exec.c. */
1550 *eax
= 0x00003028; /* 48 bits virtual, 40 bits physical */
1552 if (env
->cpuid_features
& CPUID_PSE36
)
1553 *eax
= 0x00000024; /* 36 bits physical */
1555 *eax
= 0x00000020; /* 32 bits physical */
1560 if (env
->nr_cores
* env
->nr_threads
> 1) {
1561 *ecx
|= (env
->nr_cores
* env
->nr_threads
) - 1;
1565 if (env
->cpuid_ext3_features
& CPUID_EXT3_SVM
) {
1566 *eax
= 0x00000001; /* SVM Revision */
1567 *ebx
= 0x00000010; /* nr of ASIDs */
1569 *edx
= env
->cpuid_svm_features
; /* optional features */
1578 *eax
= env
->cpuid_xlevel2
;
1584 /* Support for VIA CPU's CPUID instruction */
1585 *eax
= env
->cpuid_version
;
1588 *edx
= env
->cpuid_ext4_features
;
1593 /* Reserved for the future, and now filled with zero */
1600 /* reserved values: zero */
1609 /* CPUClass::reset() */
1610 static void x86_cpu_reset(CPUState
*s
)
1612 X86CPU
*cpu
= X86_CPU(s
);
1613 X86CPUClass
*xcc
= X86_CPU_GET_CLASS(cpu
);
1614 CPUX86State
*env
= &cpu
->env
;
1617 if (qemu_loglevel_mask(CPU_LOG_RESET
)) {
1618 qemu_log("CPU Reset (CPU %d)\n", env
->cpu_index
);
1619 log_cpu_state(env
, X86_DUMP_FPU
| X86_DUMP_CCOP
);
1622 xcc
->parent_reset(s
);
1625 memset(env
, 0, offsetof(CPUX86State
, breakpoints
));
1629 env
->old_exception
= -1;
1631 /* init to reset state */
1633 #ifdef CONFIG_SOFTMMU
1634 env
->hflags
|= HF_SOFTMMU_MASK
;
1636 env
->hflags2
|= HF2_GIF_MASK
;
1638 cpu_x86_update_cr0(env
, 0x60000010);
1639 env
->a20_mask
= ~0x0;
1640 env
->smbase
= 0x30000;
1642 env
->idt
.limit
= 0xffff;
1643 env
->gdt
.limit
= 0xffff;
1644 env
->ldt
.limit
= 0xffff;
1645 env
->ldt
.flags
= DESC_P_MASK
| (2 << DESC_TYPE_SHIFT
);
1646 env
->tr
.limit
= 0xffff;
1647 env
->tr
.flags
= DESC_P_MASK
| (11 << DESC_TYPE_SHIFT
);
1649 cpu_x86_load_seg_cache(env
, R_CS
, 0xf000, 0xffff0000, 0xffff,
1650 DESC_P_MASK
| DESC_S_MASK
| DESC_CS_MASK
|
1651 DESC_R_MASK
| DESC_A_MASK
);
1652 cpu_x86_load_seg_cache(env
, R_DS
, 0, 0, 0xffff,
1653 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
1655 cpu_x86_load_seg_cache(env
, R_ES
, 0, 0, 0xffff,
1656 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
1658 cpu_x86_load_seg_cache(env
, R_SS
, 0, 0, 0xffff,
1659 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
1661 cpu_x86_load_seg_cache(env
, R_FS
, 0, 0, 0xffff,
1662 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
1664 cpu_x86_load_seg_cache(env
, R_GS
, 0, 0, 0xffff,
1665 DESC_P_MASK
| DESC_S_MASK
| DESC_W_MASK
|
1669 env
->regs
[R_EDX
] = env
->cpuid_version
;
1674 for (i
= 0; i
< 8; i
++) {
1679 env
->mxcsr
= 0x1f80;
1681 env
->pat
= 0x0007040600070406ULL
;
1682 env
->msr_ia32_misc_enable
= MSR_IA32_MISC_ENABLE_DEFAULT
;
1684 memset(env
->dr
, 0, sizeof(env
->dr
));
1685 env
->dr
[6] = DR6_FIXED_1
;
1686 env
->dr
[7] = DR7_FIXED_1
;
1687 cpu_breakpoint_remove_all(env
, BP_CPU
);
1688 cpu_watchpoint_remove_all(env
, BP_CPU
);
1691 static void mce_init(X86CPU
*cpu
)
1693 CPUX86State
*cenv
= &cpu
->env
;
1696 if (((cenv
->cpuid_version
>> 8) & 0xf) >= 6
1697 && (cenv
->cpuid_features
& (CPUID_MCE
| CPUID_MCA
)) ==
1698 (CPUID_MCE
| CPUID_MCA
)) {
1699 cenv
->mcg_cap
= MCE_CAP_DEF
| MCE_BANKS_DEF
;
1700 cenv
->mcg_ctl
= ~(uint64_t)0;
1701 for (bank
= 0; bank
< MCE_BANKS_DEF
; bank
++) {
1702 cenv
->mce_banks
[bank
* 4] = ~(uint64_t)0;
1707 void x86_cpu_realize(Object
*obj
, Error
**errp
)
1709 X86CPU
*cpu
= X86_CPU(obj
);
1712 qemu_init_vcpu(&cpu
->env
);
1715 static void x86_cpu_initfn(Object
*obj
)
1717 X86CPU
*cpu
= X86_CPU(obj
);
1718 CPUX86State
*env
= &cpu
->env
;
1722 object_property_add(obj
, "family", "int",
1723 x86_cpuid_version_get_family
,
1724 x86_cpuid_version_set_family
, NULL
, NULL
, NULL
);
1725 object_property_add(obj
, "model", "int",
1726 x86_cpuid_version_get_model
,
1727 x86_cpuid_version_set_model
, NULL
, NULL
, NULL
);
1728 object_property_add(obj
, "stepping", "int",
1729 x86_cpuid_version_get_stepping
,
1730 x86_cpuid_version_set_stepping
, NULL
, NULL
, NULL
);
1731 object_property_add(obj
, "level", "int",
1732 x86_cpuid_get_level
,
1733 x86_cpuid_set_level
, NULL
, NULL
, NULL
);
1734 object_property_add(obj
, "xlevel", "int",
1735 x86_cpuid_get_xlevel
,
1736 x86_cpuid_set_xlevel
, NULL
, NULL
, NULL
);
1737 object_property_add_str(obj
, "vendor",
1738 x86_cpuid_get_vendor
,
1739 x86_cpuid_set_vendor
, NULL
);
1740 object_property_add_str(obj
, "model-id",
1741 x86_cpuid_get_model_id
,
1742 x86_cpuid_set_model_id
, NULL
);
1743 object_property_add(obj
, "tsc-frequency", "int",
1744 x86_cpuid_get_tsc_freq
,
1745 x86_cpuid_set_tsc_freq
, NULL
, NULL
, NULL
);
1747 env
->cpuid_apic_id
= env
->cpu_index
;
1750 static void x86_cpu_common_class_init(ObjectClass
*oc
, void *data
)
1752 X86CPUClass
*xcc
= X86_CPU_CLASS(oc
);
1753 CPUClass
*cc
= CPU_CLASS(oc
);
1755 xcc
->parent_reset
= cc
->reset
;
1756 cc
->reset
= x86_cpu_reset
;
1759 static const TypeInfo x86_cpu_type_info
= {
1760 .name
= TYPE_X86_CPU
,
1762 .instance_size
= sizeof(X86CPU
),
1763 .instance_init
= x86_cpu_initfn
,
1765 .class_size
= sizeof(X86CPUClass
),
1766 .class_init
= x86_cpu_common_class_init
,
1769 static void x86_cpu_register_types(void)
1771 type_register_static(&x86_cpu_type_info
);
1774 type_init(x86_cpu_register_types
)