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PPC: Fix SPR access control of L1CFG0
[qemu-kvm.git] / target-i386 / cpu.c
blob8983457e237bbab262f1aa1739fda0d10be6ab4a
1 /*
2 * i386 CPUID helper functions
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdlib.h>
20 #include <stdio.h>
21 #include <string.h>
22 #include <inttypes.h>
23
24 #include "cpu.h"
25 #include "sysemu/kvm.h"
26 #include "sysemu/cpus.h"
27 #include "kvm_i386.h"
28 #include "topology.h"
29
30 #include "qemu/option.h"
31 #include "qemu/config-file.h"
32 #include "qapi/qmp/qerror.h"
33
34 #include "qapi-types.h"
35 #include "qapi-visit.h"
36 #include "qapi/visitor.h"
37 #include "sysemu/arch_init.h"
38
39 #include "hw/hw.h"
40 #if defined(CONFIG_KVM)
41 #include <linux/kvm_para.h>
42 #endif
43
44 #include "sysemu/sysemu.h"
45 #include "hw/qdev-properties.h"
46 #include "hw/cpu/icc_bus.h"
47 #ifndef CONFIG_USER_ONLY
48 #include "hw/xen/xen.h"
49 #include "hw/i386/apic_internal.h"
50 #endif
51
52
53 /* Cache topology CPUID constants: */
54
55 /* CPUID Leaf 2 Descriptors */
56
57 #define CPUID_2_L1D_32KB_8WAY_64B 0x2c
58 #define CPUID_2_L1I_32KB_8WAY_64B 0x30
59 #define CPUID_2_L2_2MB_8WAY_64B 0x7d
60
61
62 /* CPUID Leaf 4 constants: */
63
64 /* EAX: */
65 #define CPUID_4_TYPE_DCACHE 1
66 #define CPUID_4_TYPE_ICACHE 2
67 #define CPUID_4_TYPE_UNIFIED 3
68
69 #define CPUID_4_LEVEL(l) ((l) << 5)
70
71 #define CPUID_4_SELF_INIT_LEVEL (1 << 8)
72 #define CPUID_4_FULLY_ASSOC (1 << 9)
73
74 /* EDX: */
75 #define CPUID_4_NO_INVD_SHARING (1 << 0)
76 #define CPUID_4_INCLUSIVE (1 << 1)
77 #define CPUID_4_COMPLEX_IDX (1 << 2)
78
79 #define ASSOC_FULL 0xFF
80
81 /* AMD associativity encoding used on CPUID Leaf 0x80000006: */
82 #define AMD_ENC_ASSOC(a) (a <= 1 ? a : \
83 a == 2 ? 0x2 : \
84 a == 4 ? 0x4 : \
85 a == 8 ? 0x6 : \
86 a == 16 ? 0x8 : \
87 a == 32 ? 0xA : \
88 a == 48 ? 0xB : \
89 a == 64 ? 0xC : \
90 a == 96 ? 0xD : \
91 a == 128 ? 0xE : \
92 a == ASSOC_FULL ? 0xF : \
93 0 /* invalid value */)
94
95
96 /* Definitions of the hardcoded cache entries we expose: */
97
98 /* L1 data cache: */
99 #define L1D_LINE_SIZE 64
100 #define L1D_ASSOCIATIVITY 8
101 #define L1D_SETS 64
102 #define L1D_PARTITIONS 1
103 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
104 #define L1D_DESCRIPTOR CPUID_2_L1D_32KB_8WAY_64B
105 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
106 #define L1D_LINES_PER_TAG 1
107 #define L1D_SIZE_KB_AMD 64
108 #define L1D_ASSOCIATIVITY_AMD 2
109
110 /* L1 instruction cache: */
111 #define L1I_LINE_SIZE 64
112 #define L1I_ASSOCIATIVITY 8
113 #define L1I_SETS 64
114 #define L1I_PARTITIONS 1
115 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 32KiB */
116 #define L1I_DESCRIPTOR CPUID_2_L1I_32KB_8WAY_64B
117 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
118 #define L1I_LINES_PER_TAG 1
119 #define L1I_SIZE_KB_AMD 64
120 #define L1I_ASSOCIATIVITY_AMD 2
121
122 /* Level 2 unified cache: */
123 #define L2_LINE_SIZE 64
124 #define L2_ASSOCIATIVITY 16
125 #define L2_SETS 4096
126 #define L2_PARTITIONS 1
127 /* Size = LINE_SIZE*ASSOCIATIVITY*SETS*PARTITIONS = 4MiB */
128 /*FIXME: CPUID leaf 2 descriptor is inconsistent with CPUID leaf 4 */
129 #define L2_DESCRIPTOR CPUID_2_L2_2MB_8WAY_64B
130 /*FIXME: CPUID leaf 0x80000006 is inconsistent with leaves 2 & 4 */
131 #define L2_LINES_PER_TAG 1
132 #define L2_SIZE_KB_AMD 512
133
134 /* No L3 cache: */
135 #define L3_SIZE_KB 0 /* disabled */
136 #define L3_ASSOCIATIVITY 0 /* disabled */
137 #define L3_LINES_PER_TAG 0 /* disabled */
138 #define L3_LINE_SIZE 0 /* disabled */
139
140 /* TLB definitions: */
141
142 #define L1_DTLB_2M_ASSOC 1
143 #define L1_DTLB_2M_ENTRIES 255
144 #define L1_DTLB_4K_ASSOC 1
145 #define L1_DTLB_4K_ENTRIES 255
146
147 #define L1_ITLB_2M_ASSOC 1
148 #define L1_ITLB_2M_ENTRIES 255
149 #define L1_ITLB_4K_ASSOC 1
150 #define L1_ITLB_4K_ENTRIES 255
151
152 #define L2_DTLB_2M_ASSOC 0 /* disabled */
153 #define L2_DTLB_2M_ENTRIES 0 /* disabled */
154 #define L2_DTLB_4K_ASSOC 4
155 #define L2_DTLB_4K_ENTRIES 512
156
157 #define L2_ITLB_2M_ASSOC 0 /* disabled */
158 #define L2_ITLB_2M_ENTRIES 0 /* disabled */
159 #define L2_ITLB_4K_ASSOC 4
160 #define L2_ITLB_4K_ENTRIES 512
161
162
163
164 static void x86_cpu_vendor_words2str(char *dst, uint32_t vendor1,
165 uint32_t vendor2, uint32_t vendor3)
166 {
167 int i;
168 for (i = 0; i < 4; i++) {
169 dst[i] = vendor1 >> (8 * i);
170 dst[i + 4] = vendor2 >> (8 * i);
171 dst[i + 8] = vendor3 >> (8 * i);
172 }
173 dst[CPUID_VENDOR_SZ] = '\0';
174 }
175
176 /* feature flags taken from "Intel Processor Identification and the CPUID
177 * Instruction" and AMD's "CPUID Specification". In cases of disagreement
178 * between feature naming conventions, aliases may be added.
179 */
180 static const char *feature_name[] = {
181 "fpu", "vme", "de", "pse",
182 "tsc", "msr", "pae", "mce",
183 "cx8", "apic", NULL, "sep",
184 "mtrr", "pge", "mca", "cmov",
185 "pat", "pse36", "pn" /* Intel psn */, "clflush" /* Intel clfsh */,
186 NULL, "ds" /* Intel dts */, "acpi", "mmx",
187 "fxsr", "sse", "sse2", "ss",
188 "ht" /* Intel htt */, "tm", "ia64", "pbe",
189 };
190 static const char *ext_feature_name[] = {
191 "pni|sse3" /* Intel,AMD sse3 */, "pclmulqdq|pclmuldq", "dtes64", "monitor",
192 "ds_cpl", "vmx", "smx", "est",
193 "tm2", "ssse3", "cid", NULL,
194 "fma", "cx16", "xtpr", "pdcm",
195 NULL, "pcid", "dca", "sse4.1|sse4_1",
196 "sse4.2|sse4_2", "x2apic", "movbe", "popcnt",
197 "tsc-deadline", "aes", "xsave", "osxsave",
198 "avx", "f16c", "rdrand", "hypervisor",
199 };
200 /* Feature names that are already defined on feature_name[] but are set on
201 * CPUID[8000_0001].EDX on AMD CPUs don't have their names on
202 * ext2_feature_name[]. They are copied automatically to cpuid_ext2_features
203 * if and only if CPU vendor is AMD.
204 */
205 static const char *ext2_feature_name[] = {
206 NULL /* fpu */, NULL /* vme */, NULL /* de */, NULL /* pse */,
207 NULL /* tsc */, NULL /* msr */, NULL /* pae */, NULL /* mce */,
208 NULL /* cx8 */ /* AMD CMPXCHG8B */, NULL /* apic */, NULL, "syscall",
209 NULL /* mtrr */, NULL /* pge */, NULL /* mca */, NULL /* cmov */,
210 NULL /* pat */, NULL /* pse36 */, NULL, NULL /* Linux mp */,
211 "nx|xd", NULL, "mmxext", NULL /* mmx */,
212 NULL /* fxsr */, "fxsr_opt|ffxsr", "pdpe1gb" /* AMD Page1GB */, "rdtscp",
213 NULL, "lm|i64", "3dnowext", "3dnow",
214 };
215 static const char *ext3_feature_name[] = {
216 "lahf_lm" /* AMD LahfSahf */, "cmp_legacy", "svm", "extapic" /* AMD ExtApicSpace */,
217 "cr8legacy" /* AMD AltMovCr8 */, "abm", "sse4a", "misalignsse",
218 "3dnowprefetch", "osvw", "ibs", "xop",
219 "skinit", "wdt", NULL, "lwp",
220 "fma4", "tce", NULL, "nodeid_msr",
221 NULL, "tbm", "topoext", "perfctr_core",
222 "perfctr_nb", NULL, NULL, NULL,
223 NULL, NULL, NULL, NULL,
224 };
225
226 static const char *ext4_feature_name[] = {
227 NULL, NULL, "xstore", "xstore-en",
228 NULL, NULL, "xcrypt", "xcrypt-en",
229 "ace2", "ace2-en", "phe", "phe-en",
230 "pmm", "pmm-en", NULL, NULL,
231 NULL, NULL, NULL, NULL,
232 NULL, NULL, NULL, NULL,
233 NULL, NULL, NULL, NULL,
234 NULL, NULL, NULL, NULL,
235 };
236
237 static const char *kvm_feature_name[] = {
238 "kvmclock", "kvm_nopiodelay", "kvm_mmu", "kvmclock",
239 "kvm_asyncpf", "kvm_steal_time", "kvm_pv_eoi", "kvm_pv_unhalt",
240 NULL, NULL, NULL, NULL,
241 NULL, NULL, NULL, NULL,
242 NULL, NULL, NULL, NULL,
243 NULL, NULL, NULL, NULL,
244 NULL, NULL, NULL, NULL,
245 NULL, NULL, NULL, NULL,
246 };
247
248 static const char *svm_feature_name[] = {
249 "npt", "lbrv", "svm_lock", "nrip_save",
250 "tsc_scale", "vmcb_clean", "flushbyasid", "decodeassists",
251 NULL, NULL, "pause_filter", NULL,
252 "pfthreshold", NULL, NULL, NULL,
253 NULL, NULL, NULL, NULL,
254 NULL, NULL, NULL, NULL,
255 NULL, NULL, NULL, NULL,
256 NULL, NULL, NULL, NULL,
257 };
258
259 static const char *cpuid_7_0_ebx_feature_name[] = {
260 "fsgsbase", NULL, NULL, "bmi1", "hle", "avx2", NULL, "smep",
261 "bmi2", "erms", "invpcid", "rtm", NULL, NULL, NULL, NULL,
262 NULL, NULL, "rdseed", "adx", "smap", NULL, NULL, NULL,
263 NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
264 };
265
266 typedef struct FeatureWordInfo {
267 const char **feat_names;
268 uint32_t cpuid_eax; /* Input EAX for CPUID */
269 bool cpuid_needs_ecx; /* CPUID instruction uses ECX as input */
270 uint32_t cpuid_ecx; /* Input ECX value for CPUID */
271 int cpuid_reg; /* output register (R_* constant) */
272 } FeatureWordInfo;
273
274 static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
275 [FEAT_1_EDX] = {
276 .feat_names = feature_name,
277 .cpuid_eax = 1, .cpuid_reg = R_EDX,
278 },
279 [FEAT_1_ECX] = {
280 .feat_names = ext_feature_name,
281 .cpuid_eax = 1, .cpuid_reg = R_ECX,
282 },
283 [FEAT_8000_0001_EDX] = {
284 .feat_names = ext2_feature_name,
285 .cpuid_eax = 0x80000001, .cpuid_reg = R_EDX,
286 },
287 [FEAT_8000_0001_ECX] = {
288 .feat_names = ext3_feature_name,
289 .cpuid_eax = 0x80000001, .cpuid_reg = R_ECX,
290 },
291 [FEAT_C000_0001_EDX] = {
292 .feat_names = ext4_feature_name,
293 .cpuid_eax = 0xC0000001, .cpuid_reg = R_EDX,
294 },
295 [FEAT_KVM] = {
296 .feat_names = kvm_feature_name,
297 .cpuid_eax = KVM_CPUID_FEATURES, .cpuid_reg = R_EAX,
298 },
299 [FEAT_SVM] = {
300 .feat_names = svm_feature_name,
301 .cpuid_eax = 0x8000000A, .cpuid_reg = R_EDX,
302 },
303 [FEAT_7_0_EBX] = {
304 .feat_names = cpuid_7_0_ebx_feature_name,
305 .cpuid_eax = 7,
306 .cpuid_needs_ecx = true, .cpuid_ecx = 0,
307 .cpuid_reg = R_EBX,
308 },
309 };
310
311 typedef struct X86RegisterInfo32 {
312 /* Name of register */
313 const char *name;
314 /* QAPI enum value register */
315 X86CPURegister32 qapi_enum;
316 } X86RegisterInfo32;
317
318 #define REGISTER(reg) \
319 [R_##reg] = { .name = #reg, .qapi_enum = X86_CPU_REGISTER32_##reg }
320 static const X86RegisterInfo32 x86_reg_info_32[CPU_NB_REGS32] = {
321 REGISTER(EAX),
322 REGISTER(ECX),
323 REGISTER(EDX),
324 REGISTER(EBX),
325 REGISTER(ESP),
326 REGISTER(EBP),
327 REGISTER(ESI),
328 REGISTER(EDI),
329 };
330 #undef REGISTER
331
332 typedef struct ExtSaveArea {
333 uint32_t feature, bits;
334 uint32_t offset, size;
335 } ExtSaveArea;
336
337 static const ExtSaveArea ext_save_areas[] = {
338 [2] = { .feature = FEAT_1_ECX, .bits = CPUID_EXT_AVX,
339 .offset = 0x240, .size = 0x100 },
340 [3] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
341 .offset = 0x3c0, .size = 0x40 },
342 [4] = { .feature = FEAT_7_0_EBX, .bits = CPUID_7_0_EBX_MPX,
343 .offset = 0x400, .size = 0x40 },
344 };
345
346 const char *get_register_name_32(unsigned int reg)
347 {
348 if (reg >= CPU_NB_REGS32) {
349 return NULL;
350 }
351 return x86_reg_info_32[reg].name;
352 }
353
354 /* collects per-function cpuid data
355 */
356 typedef struct model_features_t {
357 uint32_t *guest_feat;
358 uint32_t *host_feat;
359 FeatureWord feat_word;
360 } model_features_t;
361
362 /* KVM-specific features that are automatically added to all CPU models
363 * when KVM is enabled.
364 */
365 static uint32_t kvm_default_features[FEATURE_WORDS] = {
366 [FEAT_KVM] = (1 << KVM_FEATURE_CLOCKSOURCE) |
367 (1 << KVM_FEATURE_NOP_IO_DELAY) |
368 (1 << KVM_FEATURE_CLOCKSOURCE2) |
369 (1 << KVM_FEATURE_ASYNC_PF) |
370 (1 << KVM_FEATURE_STEAL_TIME) |
371 (1 << KVM_FEATURE_PV_EOI) |
372 (1 << KVM_FEATURE_CLOCKSOURCE_STABLE_BIT),
373 [FEAT_1_ECX] = CPUID_EXT_X2APIC,
374 };
375
376 void x86_cpu_compat_disable_kvm_features(FeatureWord w, uint32_t features)
377 {
378 kvm_default_features[w] &= ~features;
379 }
380
381 void host_cpuid(uint32_t function, uint32_t count,
382 uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx)
383 {
384 uint32_t vec[4];
385
386 #ifdef __x86_64__
387 asm volatile("cpuid"
388 : "=a"(vec[0]), "=b"(vec[1]),
389 "=c"(vec[2]), "=d"(vec[3])
390 : "0"(function), "c"(count) : "cc");
391 #elif defined(__i386__)
392 asm volatile("pusha \n\t"
393 "cpuid \n\t"
394 "mov %%eax, 0(%2) \n\t"
395 "mov %%ebx, 4(%2) \n\t"
396 "mov %%ecx, 8(%2) \n\t"
397 "mov %%edx, 12(%2) \n\t"
398 "popa"
399 : : "a"(function), "c"(count), "S"(vec)
400 : "memory", "cc");
401 #else
402 abort();
403 #endif
404
405 if (eax)
406 *eax = vec[0];
407 if (ebx)
408 *ebx = vec[1];
409 if (ecx)
410 *ecx = vec[2];
411 if (edx)
412 *edx = vec[3];
413 }
414
415 #define iswhite(c) ((c) && ((c) <= ' ' || '~' < (c)))
416
417 /* general substring compare of *[s1..e1) and *[s2..e2). sx is start of
418 * a substring. ex if !NULL points to the first char after a substring,
419 * otherwise the string is assumed to sized by a terminating nul.
420 * Return lexical ordering of *s1:*s2.
421 */
422 static int sstrcmp(const char *s1, const char *e1, const char *s2,
423 const char *e2)
424 {
425 for (;;) {
426 if (!*s1 || !*s2 || *s1 != *s2)
427 return (*s1 - *s2);
428 ++s1, ++s2;
429 if (s1 == e1 && s2 == e2)
430 return (0);
431 else if (s1 == e1)
432 return (*s2);
433 else if (s2 == e2)
434 return (*s1);
435 }
436 }
437
438 /* compare *[s..e) to *altstr. *altstr may be a simple string or multiple
439 * '|' delimited (possibly empty) strings in which case search for a match
440 * within the alternatives proceeds left to right. Return 0 for success,
441 * non-zero otherwise.
442 */
443 static int altcmp(const char *s, const char *e, const char *altstr)
444 {
445 const char *p, *q;
446
447 for (q = p = altstr; ; ) {
448 while (*p && *p != '|')
449 ++p;
450 if ((q == p && !*s) || (q != p && !sstrcmp(s, e, q, p)))
451 return (0);
452 if (!*p)
453 return (1);
454 else
455 q = ++p;
456 }
457 }
458
459 /* search featureset for flag *[s..e), if found set corresponding bit in
460 * *pval and return true, otherwise return false
461 */
462 static bool lookup_feature(uint32_t *pval, const char *s, const char *e,
463 const char **featureset)
464 {
465 uint32_t mask;
466 const char **ppc;
467 bool found = false;
468
469 for (mask = 1, ppc = featureset; mask; mask <<= 1, ++ppc) {
470 if (*ppc && !altcmp(s, e, *ppc)) {
471 *pval |= mask;
472 found = true;
473 }
474 }
475 return found;
476 }
477
478 static void add_flagname_to_bitmaps(const char *flagname,
479 FeatureWordArray words)
480 {
481 FeatureWord w;
482 for (w = 0; w < FEATURE_WORDS; w++) {
483 FeatureWordInfo *wi = &feature_word_info[w];
484 if (wi->feat_names &&
485 lookup_feature(&words[w], flagname, NULL, wi->feat_names)) {
486 break;
487 }
488 }
489 if (w == FEATURE_WORDS) {
490 fprintf(stderr, "CPU feature %s not found\n", flagname);
491 }
492 }
493
494 /* CPU class name definitions: */
495
496 #define X86_CPU_TYPE_SUFFIX "-" TYPE_X86_CPU
497 #define X86_CPU_TYPE_NAME(name) (name X86_CPU_TYPE_SUFFIX)
498
499 /* Return type name for a given CPU model name
500 * Caller is responsible for freeing the returned string.
501 */
502 static char *x86_cpu_type_name(const char *model_name)
503 {
504 return g_strdup_printf(X86_CPU_TYPE_NAME("%s"), model_name);
505 }
506
507 static ObjectClass *x86_cpu_class_by_name(const char *cpu_model)
508 {
509 ObjectClass *oc;
510 char *typename;
511
512 if (cpu_model == NULL) {
513 return NULL;
514 }
515
516 typename = x86_cpu_type_name(cpu_model);
517 oc = object_class_by_name(typename);
518 g_free(typename);
519 return oc;
520 }
521
522 struct X86CPUDefinition {
523 const char *name;
524 uint32_t level;
525 uint32_t xlevel;
526 uint32_t xlevel2;
527 /* vendor is zero-terminated, 12 character ASCII string */
528 char vendor[CPUID_VENDOR_SZ + 1];
529 int family;
530 int model;
531 int stepping;
532 FeatureWordArray features;
533 char model_id[48];
534 bool cache_info_passthrough;
535 };
536
537 #define I486_FEATURES (CPUID_FP87 | CPUID_VME | CPUID_PSE)
538 #define PENTIUM_FEATURES (I486_FEATURES | CPUID_DE | CPUID_TSC | \
539 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_MMX | CPUID_APIC)
540 #define PENTIUM2_FEATURES (PENTIUM_FEATURES | CPUID_PAE | CPUID_SEP | \
541 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
542 CPUID_PSE36 | CPUID_FXSR)
543 #define PENTIUM3_FEATURES (PENTIUM2_FEATURES | CPUID_SSE)
544 #define PPRO_FEATURES (CPUID_FP87 | CPUID_DE | CPUID_PSE | CPUID_TSC | \
545 CPUID_MSR | CPUID_MCE | CPUID_CX8 | CPUID_PGE | CPUID_CMOV | \
546 CPUID_PAT | CPUID_FXSR | CPUID_MMX | CPUID_SSE | CPUID_SSE2 | \
547 CPUID_PAE | CPUID_SEP | CPUID_APIC)
548
549 #define TCG_FEATURES (CPUID_FP87 | CPUID_PSE | CPUID_TSC | CPUID_MSR | \
550 CPUID_PAE | CPUID_MCE | CPUID_CX8 | CPUID_APIC | CPUID_SEP | \
551 CPUID_MTRR | CPUID_PGE | CPUID_MCA | CPUID_CMOV | CPUID_PAT | \
552 CPUID_PSE36 | CPUID_CLFLUSH | CPUID_ACPI | CPUID_MMX | \
553 CPUID_FXSR | CPUID_SSE | CPUID_SSE2 | CPUID_SS)
554 /* partly implemented:
555 CPUID_MTRR, CPUID_MCA, CPUID_CLFLUSH (needed for Win64) */
556 /* missing:
557 CPUID_VME, CPUID_DTS, CPUID_SS, CPUID_HT, CPUID_TM, CPUID_PBE */
558 #define TCG_EXT_FEATURES (CPUID_EXT_SSE3 | CPUID_EXT_PCLMULQDQ | \
559 CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | CPUID_EXT_CX16 | \
560 CPUID_EXT_SSE41 | CPUID_EXT_SSE42 | CPUID_EXT_POPCNT | \
561 CPUID_EXT_MOVBE | CPUID_EXT_AES | CPUID_EXT_HYPERVISOR)
562 /* missing:
563 CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_VMX, CPUID_EXT_SMX,
564 CPUID_EXT_EST, CPUID_EXT_TM2, CPUID_EXT_CID, CPUID_EXT_FMA,
565 CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_PCID, CPUID_EXT_DCA,
566 CPUID_EXT_X2APIC, CPUID_EXT_TSC_DEADLINE_TIMER, CPUID_EXT_XSAVE,
567 CPUID_EXT_OSXSAVE, CPUID_EXT_AVX, CPUID_EXT_F16C,
568 CPUID_EXT_RDRAND */
569 #define TCG_EXT2_FEATURES ((TCG_FEATURES & CPUID_EXT2_AMD_ALIASES) | \
570 CPUID_EXT2_NX | CPUID_EXT2_MMXEXT | CPUID_EXT2_RDTSCP | \
571 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_PDPE1GB)
572 #define TCG_EXT3_FEATURES (CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | \
573 CPUID_EXT3_CR8LEG | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A)
574 #define TCG_SVM_FEATURES 0
575 #define TCG_7_0_EBX_FEATURES (CPUID_7_0_EBX_SMEP | CPUID_7_0_EBX_SMAP \
576 CPUID_7_0_EBX_BMI1 | CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ADX)
577 /* missing:
578 CPUID_7_0_EBX_FSGSBASE, CPUID_7_0_EBX_HLE, CPUID_7_0_EBX_AVX2,
579 CPUID_7_0_EBX_ERMS, CPUID_7_0_EBX_INVPCID, CPUID_7_0_EBX_RTM,
580 CPUID_7_0_EBX_RDSEED */
581
582 static X86CPUDefinition builtin_x86_defs[] = {
583 {
584 .name = "qemu64",
585 .level = 4,
586 .vendor = CPUID_VENDOR_AMD,
587 .family = 6,
588 .model = 6,
589 .stepping = 3,
590 .features[FEAT_1_EDX] =
591 PPRO_FEATURES |
592 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
593 CPUID_PSE36,
594 .features[FEAT_1_ECX] =
595 CPUID_EXT_SSE3 | CPUID_EXT_CX16 | CPUID_EXT_POPCNT,
596 .features[FEAT_8000_0001_EDX] =
597 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
598 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
599 .features[FEAT_8000_0001_ECX] =
600 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
601 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
602 .xlevel = 0x8000000A,
603 },
604 {
605 .name = "phenom",
606 .level = 5,
607 .vendor = CPUID_VENDOR_AMD,
608 .family = 16,
609 .model = 2,
610 .stepping = 3,
611 .features[FEAT_1_EDX] =
612 PPRO_FEATURES |
613 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
614 CPUID_PSE36 | CPUID_VME | CPUID_HT,
615 .features[FEAT_1_ECX] =
616 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 |
617 CPUID_EXT_POPCNT,
618 .features[FEAT_8000_0001_EDX] =
619 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
620 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX |
621 CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT | CPUID_EXT2_MMXEXT |
622 CPUID_EXT2_FFXSR | CPUID_EXT2_PDPE1GB | CPUID_EXT2_RDTSCP,
623 /* Missing: CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
624 CPUID_EXT3_CR8LEG,
625 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
626 CPUID_EXT3_OSVW, CPUID_EXT3_IBS */
627 .features[FEAT_8000_0001_ECX] =
628 CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM |
629 CPUID_EXT3_ABM | CPUID_EXT3_SSE4A,
630 .features[FEAT_SVM] =
631 CPUID_SVM_NPT | CPUID_SVM_LBRV,
632 .xlevel = 0x8000001A,
633 .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor"
634 },
635 {
636 .name = "core2duo",
637 .level = 10,
638 .vendor = CPUID_VENDOR_INTEL,
639 .family = 6,
640 .model = 15,
641 .stepping = 11,
642 .features[FEAT_1_EDX] =
643 PPRO_FEATURES |
644 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
645 CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS |
646 CPUID_HT | CPUID_TM | CPUID_PBE,
647 .features[FEAT_1_ECX] =
648 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
649 CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST |
650 CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
651 .features[FEAT_8000_0001_EDX] =
652 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
653 .features[FEAT_8000_0001_ECX] =
654 CPUID_EXT3_LAHF_LM,
655 .xlevel = 0x80000008,
656 .model_id = "Intel(R) Core(TM)2 Duo CPU T7700 @ 2.40GHz",
657 },
658 {
659 .name = "kvm64",
660 .level = 5,
661 .vendor = CPUID_VENDOR_INTEL,
662 .family = 15,
663 .model = 6,
664 .stepping = 1,
665 /* Missing: CPUID_VME, CPUID_HT */
666 .features[FEAT_1_EDX] =
667 PPRO_FEATURES |
668 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA |
669 CPUID_PSE36,
670 /* Missing: CPUID_EXT_POPCNT, CPUID_EXT_MONITOR */
671 .features[FEAT_1_ECX] =
672 CPUID_EXT_SSE3 | CPUID_EXT_CX16,
673 /* Missing: CPUID_EXT2_PDPE1GB, CPUID_EXT2_RDTSCP */
674 .features[FEAT_8000_0001_EDX] =
675 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
676 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
677 /* Missing: CPUID_EXT3_LAHF_LM, CPUID_EXT3_CMP_LEG, CPUID_EXT3_EXTAPIC,
678 CPUID_EXT3_CR8LEG, CPUID_EXT3_ABM, CPUID_EXT3_SSE4A,
679 CPUID_EXT3_MISALIGNSSE, CPUID_EXT3_3DNOWPREFETCH,
680 CPUID_EXT3_OSVW, CPUID_EXT3_IBS, CPUID_EXT3_SVM */
681 .features[FEAT_8000_0001_ECX] =
682 0,
683 .xlevel = 0x80000008,
684 .model_id = "Common KVM processor"
685 },
686 {
687 .name = "qemu32",
688 .level = 4,
689 .vendor = CPUID_VENDOR_INTEL,
690 .family = 6,
691 .model = 6,
692 .stepping = 3,
693 .features[FEAT_1_EDX] =
694 PPRO_FEATURES,
695 .features[FEAT_1_ECX] =
696 CPUID_EXT_SSE3 | CPUID_EXT_POPCNT,
697 .xlevel = 0x80000004,
698 },
699 {
700 .name = "kvm32",
701 .level = 5,
702 .vendor = CPUID_VENDOR_INTEL,
703 .family = 15,
704 .model = 6,
705 .stepping = 1,
706 .features[FEAT_1_EDX] =
707 PPRO_FEATURES |
708 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36,
709 .features[FEAT_1_ECX] =
710 CPUID_EXT_SSE3,
711 .features[FEAT_8000_0001_EDX] =
712 PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES,
713 .features[FEAT_8000_0001_ECX] =
714 0,
715 .xlevel = 0x80000008,
716 .model_id = "Common 32-bit KVM processor"
717 },
718 {
719 .name = "coreduo",
720 .level = 10,
721 .vendor = CPUID_VENDOR_INTEL,
722 .family = 6,
723 .model = 14,
724 .stepping = 8,
725 .features[FEAT_1_EDX] =
726 PPRO_FEATURES | CPUID_VME |
727 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI |
728 CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
729 .features[FEAT_1_ECX] =
730 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX |
731 CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM,
732 .features[FEAT_8000_0001_EDX] =
733 CPUID_EXT2_NX,
734 .xlevel = 0x80000008,
735 .model_id = "Genuine Intel(R) CPU T2600 @ 2.16GHz",
736 },
737 {
738 .name = "486",
739 .level = 1,
740 .vendor = CPUID_VENDOR_INTEL,
741 .family = 4,
742 .model = 8,
743 .stepping = 0,
744 .features[FEAT_1_EDX] =
745 I486_FEATURES,
746 .xlevel = 0,
747 },
748 {
749 .name = "pentium",
750 .level = 1,
751 .vendor = CPUID_VENDOR_INTEL,
752 .family = 5,
753 .model = 4,
754 .stepping = 3,
755 .features[FEAT_1_EDX] =
756 PENTIUM_FEATURES,
757 .xlevel = 0,
758 },
759 {
760 .name = "pentium2",
761 .level = 2,
762 .vendor = CPUID_VENDOR_INTEL,
763 .family = 6,
764 .model = 5,
765 .stepping = 2,
766 .features[FEAT_1_EDX] =
767 PENTIUM2_FEATURES,
768 .xlevel = 0,
769 },
770 {
771 .name = "pentium3",
772 .level = 2,
773 .vendor = CPUID_VENDOR_INTEL,
774 .family = 6,
775 .model = 7,
776 .stepping = 3,
777 .features[FEAT_1_EDX] =
778 PENTIUM3_FEATURES,
779 .xlevel = 0,
780 },
781 {
782 .name = "athlon",
783 .level = 2,
784 .vendor = CPUID_VENDOR_AMD,
785 .family = 6,
786 .model = 2,
787 .stepping = 3,
788 .features[FEAT_1_EDX] =
789 PPRO_FEATURES | CPUID_PSE36 | CPUID_VME | CPUID_MTRR |
790 CPUID_MCA,
791 .features[FEAT_8000_0001_EDX] =
792 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
793 CPUID_EXT2_MMXEXT | CPUID_EXT2_3DNOW | CPUID_EXT2_3DNOWEXT,
794 .xlevel = 0x80000008,
795 },
796 {
797 .name = "n270",
798 /* original is on level 10 */
799 .level = 5,
800 .vendor = CPUID_VENDOR_INTEL,
801 .family = 6,
802 .model = 28,
803 .stepping = 2,
804 .features[FEAT_1_EDX] =
805 PPRO_FEATURES |
806 CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS |
807 CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE,
808 /* Some CPUs got no CPUID_SEP */
809 .features[FEAT_1_ECX] =
810 CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 |
811 CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR |
812 CPUID_EXT_MOVBE,
813 .features[FEAT_8000_0001_EDX] =
814 (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) |
815 CPUID_EXT2_NX,
816 .features[FEAT_8000_0001_ECX] =
817 CPUID_EXT3_LAHF_LM,
818 .xlevel = 0x8000000A,
819 .model_id = "Intel(R) Atom(TM) CPU N270 @ 1.60GHz",
820 },
821 {
822 .name = "Conroe",
823 .level = 4,
824 .vendor = CPUID_VENDOR_INTEL,
825 .family = 6,
826 .model = 15,
827 .stepping = 3,
828 .features[FEAT_1_EDX] =
829 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
830 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
831 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
832 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
833 CPUID_DE | CPUID_FP87,
834 .features[FEAT_1_ECX] =
835 CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
836 .features[FEAT_8000_0001_EDX] =
837 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
838 .features[FEAT_8000_0001_ECX] =
839 CPUID_EXT3_LAHF_LM,
840 .xlevel = 0x8000000A,
841 .model_id = "Intel Celeron_4x0 (Conroe/Merom Class Core 2)",
842 },
843 {
844 .name = "Penryn",
845 .level = 4,
846 .vendor = CPUID_VENDOR_INTEL,
847 .family = 6,
848 .model = 23,
849 .stepping = 3,
850 .features[FEAT_1_EDX] =
851 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
852 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
853 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
854 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
855 CPUID_DE | CPUID_FP87,
856 .features[FEAT_1_ECX] =
857 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
858 CPUID_EXT_SSE3,
859 .features[FEAT_8000_0001_EDX] =
860 CPUID_EXT2_LM | CPUID_EXT2_NX | CPUID_EXT2_SYSCALL,
861 .features[FEAT_8000_0001_ECX] =
862 CPUID_EXT3_LAHF_LM,
863 .xlevel = 0x8000000A,
864 .model_id = "Intel Core 2 Duo P9xxx (Penryn Class Core 2)",
865 },
866 {
867 .name = "Nehalem",
868 .level = 4,
869 .vendor = CPUID_VENDOR_INTEL,
870 .family = 6,
871 .model = 26,
872 .stepping = 3,
873 .features[FEAT_1_EDX] =
874 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
875 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
876 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
877 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
878 CPUID_DE | CPUID_FP87,
879 .features[FEAT_1_ECX] =
880 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
881 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_SSE3,
882 .features[FEAT_8000_0001_EDX] =
883 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
884 .features[FEAT_8000_0001_ECX] =
885 CPUID_EXT3_LAHF_LM,
886 .xlevel = 0x8000000A,
887 .model_id = "Intel Core i7 9xx (Nehalem Class Core i7)",
888 },
889 {
890 .name = "Westmere",
891 .level = 11,
892 .vendor = CPUID_VENDOR_INTEL,
893 .family = 6,
894 .model = 44,
895 .stepping = 1,
896 .features[FEAT_1_EDX] =
897 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
898 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
899 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
900 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
901 CPUID_DE | CPUID_FP87,
902 .features[FEAT_1_ECX] =
903 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
904 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
905 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
906 .features[FEAT_8000_0001_EDX] =
907 CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX,
908 .features[FEAT_8000_0001_ECX] =
909 CPUID_EXT3_LAHF_LM,
910 .xlevel = 0x8000000A,
911 .model_id = "Westmere E56xx/L56xx/X56xx (Nehalem-C)",
912 },
913 {
914 .name = "SandyBridge",
915 .level = 0xd,
916 .vendor = CPUID_VENDOR_INTEL,
917 .family = 6,
918 .model = 42,
919 .stepping = 1,
920 .features[FEAT_1_EDX] =
921 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
922 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
923 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
924 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
925 CPUID_DE | CPUID_FP87,
926 .features[FEAT_1_ECX] =
927 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
928 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_POPCNT |
929 CPUID_EXT_X2APIC | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
930 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
931 CPUID_EXT_SSE3,
932 .features[FEAT_8000_0001_EDX] =
933 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
934 CPUID_EXT2_SYSCALL,
935 .features[FEAT_8000_0001_ECX] =
936 CPUID_EXT3_LAHF_LM,
937 .xlevel = 0x8000000A,
938 .model_id = "Intel Xeon E312xx (Sandy Bridge)",
939 },
940 {
941 .name = "Haswell",
942 .level = 0xd,
943 .vendor = CPUID_VENDOR_INTEL,
944 .family = 6,
945 .model = 60,
946 .stepping = 1,
947 .features[FEAT_1_EDX] =
948 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
949 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
950 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
951 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
952 CPUID_DE | CPUID_FP87,
953 .features[FEAT_1_ECX] =
954 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
955 CPUID_EXT_POPCNT | CPUID_EXT_X2APIC | CPUID_EXT_SSE42 |
956 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_SSSE3 |
957 CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3 |
958 CPUID_EXT_TSC_DEADLINE_TIMER | CPUID_EXT_FMA | CPUID_EXT_MOVBE |
959 CPUID_EXT_PCID,
960 .features[FEAT_8000_0001_EDX] =
961 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_NX |
962 CPUID_EXT2_SYSCALL,
963 .features[FEAT_8000_0001_ECX] =
964 CPUID_EXT3_LAHF_LM,
965 .features[FEAT_7_0_EBX] =
966 CPUID_7_0_EBX_FSGSBASE | CPUID_7_0_EBX_BMI1 |
967 CPUID_7_0_EBX_HLE | CPUID_7_0_EBX_AVX2 | CPUID_7_0_EBX_SMEP |
968 CPUID_7_0_EBX_BMI2 | CPUID_7_0_EBX_ERMS | CPUID_7_0_EBX_INVPCID |
969 CPUID_7_0_EBX_RTM,
970 .xlevel = 0x8000000A,
971 .model_id = "Intel Core Processor (Haswell)",
972 },
973 {
974 .name = "Opteron_G1",
975 .level = 5,
976 .vendor = CPUID_VENDOR_AMD,
977 .family = 15,
978 .model = 6,
979 .stepping = 1,
980 .features[FEAT_1_EDX] =
981 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
982 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
983 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
984 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
985 CPUID_DE | CPUID_FP87,
986 .features[FEAT_1_ECX] =
987 CPUID_EXT_SSE3,
988 .features[FEAT_8000_0001_EDX] =
989 CPUID_EXT2_LM | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
990 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
991 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
992 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
993 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
994 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
995 .xlevel = 0x80000008,
996 .model_id = "AMD Opteron 240 (Gen 1 Class Opteron)",
997 },
998 {
999 .name = "Opteron_G2",
1000 .level = 5,
1001 .vendor = CPUID_VENDOR_AMD,
1002 .family = 15,
1003 .model = 6,
1004 .stepping = 1,
1005 .features[FEAT_1_EDX] =
1006 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1007 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1008 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1009 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1010 CPUID_DE | CPUID_FP87,
1011 .features[FEAT_1_ECX] =
1012 CPUID_EXT_CX16 | CPUID_EXT_SSE3,
1013 .features[FEAT_8000_0001_EDX] =
1014 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1015 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1016 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1017 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1018 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1019 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1020 CPUID_EXT2_DE | CPUID_EXT2_FPU,
1021 .features[FEAT_8000_0001_ECX] =
1022 CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1023 .xlevel = 0x80000008,
1024 .model_id = "AMD Opteron 22xx (Gen 2 Class Opteron)",
1025 },
1026 {
1027 .name = "Opteron_G3",
1028 .level = 5,
1029 .vendor = CPUID_VENDOR_AMD,
1030 .family = 15,
1031 .model = 6,
1032 .stepping = 1,
1033 .features[FEAT_1_EDX] =
1034 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1035 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1036 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1037 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1038 CPUID_DE | CPUID_FP87,
1039 .features[FEAT_1_ECX] =
1040 CPUID_EXT_POPCNT | CPUID_EXT_CX16 | CPUID_EXT_MONITOR |
1041 CPUID_EXT_SSE3,
1042 .features[FEAT_8000_0001_EDX] =
1043 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP | CPUID_EXT2_FXSR |
1044 CPUID_EXT2_MMX | CPUID_EXT2_NX | CPUID_EXT2_PSE36 |
1045 CPUID_EXT2_PAT | CPUID_EXT2_CMOV | CPUID_EXT2_MCA |
1046 CPUID_EXT2_PGE | CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL |
1047 CPUID_EXT2_APIC | CPUID_EXT2_CX8 | CPUID_EXT2_MCE |
1048 CPUID_EXT2_PAE | CPUID_EXT2_MSR | CPUID_EXT2_TSC | CPUID_EXT2_PSE |
1049 CPUID_EXT2_DE | CPUID_EXT2_FPU,
1050 .features[FEAT_8000_0001_ECX] =
1051 CPUID_EXT3_MISALIGNSSE | CPUID_EXT3_SSE4A |
1052 CPUID_EXT3_ABM | CPUID_EXT3_SVM | CPUID_EXT3_LAHF_LM,
1053 .xlevel = 0x80000008,
1054 .model_id = "AMD Opteron 23xx (Gen 3 Class Opteron)",
1055 },
1056 {
1057 .name = "Opteron_G4",
1058 .level = 0xd,
1059 .vendor = CPUID_VENDOR_AMD,
1060 .family = 21,
1061 .model = 1,
1062 .stepping = 2,
1063 .features[FEAT_1_EDX] =
1064 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1065 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1066 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1067 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1068 CPUID_DE | CPUID_FP87,
1069 .features[FEAT_1_ECX] =
1070 CPUID_EXT_AVX | CPUID_EXT_XSAVE | CPUID_EXT_AES |
1071 CPUID_EXT_POPCNT | CPUID_EXT_SSE42 | CPUID_EXT_SSE41 |
1072 CPUID_EXT_CX16 | CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ |
1073 CPUID_EXT_SSE3,
1074 .features[FEAT_8000_0001_EDX] =
1075 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1076 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1077 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1078 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1079 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1080 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1081 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1082 .features[FEAT_8000_0001_ECX] =
1083 CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1084 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1085 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1086 CPUID_EXT3_LAHF_LM,
1087 .xlevel = 0x8000001A,
1088 .model_id = "AMD Opteron 62xx class CPU",
1089 },
1090 {
1091 .name = "Opteron_G5",
1092 .level = 0xd,
1093 .vendor = CPUID_VENDOR_AMD,
1094 .family = 21,
1095 .model = 2,
1096 .stepping = 0,
1097 .features[FEAT_1_EDX] =
1098 CPUID_SSE2 | CPUID_SSE | CPUID_FXSR | CPUID_MMX |
1099 CPUID_CLFLUSH | CPUID_PSE36 | CPUID_PAT | CPUID_CMOV | CPUID_MCA |
1100 CPUID_PGE | CPUID_MTRR | CPUID_SEP | CPUID_APIC | CPUID_CX8 |
1101 CPUID_MCE | CPUID_PAE | CPUID_MSR | CPUID_TSC | CPUID_PSE |
1102 CPUID_DE | CPUID_FP87,
1103 .features[FEAT_1_ECX] =
1104 CPUID_EXT_F16C | CPUID_EXT_AVX | CPUID_EXT_XSAVE |
1105 CPUID_EXT_AES | CPUID_EXT_POPCNT | CPUID_EXT_SSE42 |
1106 CPUID_EXT_SSE41 | CPUID_EXT_CX16 | CPUID_EXT_FMA |
1107 CPUID_EXT_SSSE3 | CPUID_EXT_PCLMULQDQ | CPUID_EXT_SSE3,
1108 .features[FEAT_8000_0001_EDX] =
1109 CPUID_EXT2_LM | CPUID_EXT2_RDTSCP |
1110 CPUID_EXT2_PDPE1GB | CPUID_EXT2_FXSR | CPUID_EXT2_MMX |
1111 CPUID_EXT2_NX | CPUID_EXT2_PSE36 | CPUID_EXT2_PAT |
1112 CPUID_EXT2_CMOV | CPUID_EXT2_MCA | CPUID_EXT2_PGE |
1113 CPUID_EXT2_MTRR | CPUID_EXT2_SYSCALL | CPUID_EXT2_APIC |
1114 CPUID_EXT2_CX8 | CPUID_EXT2_MCE | CPUID_EXT2_PAE | CPUID_EXT2_MSR |
1115 CPUID_EXT2_TSC | CPUID_EXT2_PSE | CPUID_EXT2_DE | CPUID_EXT2_FPU,
1116 .features[FEAT_8000_0001_ECX] =
1117 CPUID_EXT3_TBM | CPUID_EXT3_FMA4 | CPUID_EXT3_XOP |
1118 CPUID_EXT3_3DNOWPREFETCH | CPUID_EXT3_MISALIGNSSE |
1119 CPUID_EXT3_SSE4A | CPUID_EXT3_ABM | CPUID_EXT3_SVM |
1120 CPUID_EXT3_LAHF_LM,
1121 .xlevel = 0x8000001A,
1122 .model_id = "AMD Opteron 63xx class CPU",
1123 },
1124 };
1125
1126 /**
1127 * x86_cpu_compat_set_features:
1128 * @cpu_model: CPU model name to be changed. If NULL, all CPU models are changed
1129 * @w: Identifies the feature word to be changed.
1130 * @feat_add: Feature bits to be added to feature word
1131 * @feat_remove: Feature bits to be removed from feature word
1132 *
1133 * Change CPU model feature bits for compatibility.
1134 *
1135 * This function may be used by machine-type compatibility functions
1136 * to enable or disable feature bits on specific CPU models.
1137 */
1138 void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w,
1139 uint32_t feat_add, uint32_t feat_remove)
1140 {
1141 X86CPUDefinition *def;
1142 int i;
1143 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1144 def = &builtin_x86_defs[i];
1145 if (!cpu_model || !strcmp(cpu_model, def->name)) {
1146 def->features[w] |= feat_add;
1147 def->features[w] &= ~feat_remove;
1148 }
1149 }
1150 }
1151
1152 #ifdef CONFIG_KVM
1153
1154 static int cpu_x86_fill_model_id(char *str)
1155 {
1156 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1157 int i;
1158
1159 for (i = 0; i < 3; i++) {
1160 host_cpuid(0x80000002 + i, 0, &eax, &ebx, &ecx, &edx);
1161 memcpy(str + i * 16 + 0, &eax, 4);
1162 memcpy(str + i * 16 + 4, &ebx, 4);
1163 memcpy(str + i * 16 + 8, &ecx, 4);
1164 memcpy(str + i * 16 + 12, &edx, 4);
1165 }
1166 return 0;
1167 }
1168
1169 static X86CPUDefinition host_cpudef;
1170
1171 /* class_init for the "host" CPU model
1172 *
1173 * This function may be called before KVM is initialized.
1174 */
1175 static void host_x86_cpu_class_init(ObjectClass *oc, void *data)
1176 {
1177 X86CPUClass *xcc = X86_CPU_CLASS(oc);
1178 uint32_t eax = 0, ebx = 0, ecx = 0, edx = 0;
1179
1180 xcc->kvm_required = true;
1181
1182 host_cpuid(0x0, 0, &eax, &ebx, &ecx, &edx);
1183 x86_cpu_vendor_words2str(host_cpudef.vendor, ebx, edx, ecx);
1184
1185 host_cpuid(0x1, 0, &eax, &ebx, &ecx, &edx);
1186 host_cpudef.family = ((eax >> 8) & 0x0F) + ((eax >> 20) & 0xFF);
1187 host_cpudef.model = ((eax >> 4) & 0x0F) | ((eax & 0xF0000) >> 12);
1188 host_cpudef.stepping = eax & 0x0F;
1189
1190 cpu_x86_fill_model_id(host_cpudef.model_id);
1191
1192 xcc->cpu_def = &host_cpudef;
1193 host_cpudef.cache_info_passthrough = true;
1194
1195 /* level, xlevel, xlevel2, and the feature words are initialized on
1196 * instance_init, because they require KVM to be initialized.
1197 */
1198 }
1199
1200 static void host_x86_cpu_initfn(Object *obj)
1201 {
1202 X86CPU *cpu = X86_CPU(obj);
1203 CPUX86State *env = &cpu->env;
1204 KVMState *s = kvm_state;
1205 FeatureWord w;
1206
1207 assert(kvm_enabled());
1208
1209 env->cpuid_level = kvm_arch_get_supported_cpuid(s, 0x0, 0, R_EAX);
1210 env->cpuid_xlevel = kvm_arch_get_supported_cpuid(s, 0x80000000, 0, R_EAX);
1211 env->cpuid_xlevel2 = kvm_arch_get_supported_cpuid(s, 0xC0000000, 0, R_EAX);
1212
1213 for (w = 0; w < FEATURE_WORDS; w++) {
1214 FeatureWordInfo *wi = &feature_word_info[w];
1215 env->features[w] =
1216 kvm_arch_get_supported_cpuid(s, wi->cpuid_eax, wi->cpuid_ecx,
1217 wi->cpuid_reg);
1218 }
1219 object_property_set_bool(OBJECT(cpu), true, "pmu", &error_abort);
1220 }
1221
1222 static const TypeInfo host_x86_cpu_type_info = {
1223 .name = X86_CPU_TYPE_NAME("host"),
1224 .parent = TYPE_X86_CPU,
1225 .instance_init = host_x86_cpu_initfn,
1226 .class_init = host_x86_cpu_class_init,
1227 };
1228
1229 #endif
1230
1231 static int unavailable_host_feature(FeatureWordInfo *f, uint32_t mask)
1232 {
1233 int i;
1234
1235 for (i = 0; i < 32; ++i)
1236 if (1 << i & mask) {
1237 const char *reg = get_register_name_32(f->cpuid_reg);
1238 assert(reg);
1239 fprintf(stderr, "warning: host doesn't support requested feature: "
1240 "CPUID.%02XH:%s%s%s [bit %d]\n",
1241 f->cpuid_eax, reg,
1242 f->feat_names[i] ? "." : "",
1243 f->feat_names[i] ? f->feat_names[i] : "", i);
1244 break;
1245 }
1246 return 0;
1247 }
1248
1249 /* Check if all requested cpu flags are making their way to the guest
1250 *
1251 * Returns 0 if all flags are supported by the host, non-zero otherwise.
1252 *
1253 * This function may be called only if KVM is enabled.
1254 */
1255 static int kvm_check_features_against_host(KVMState *s, X86CPU *cpu)
1256 {
1257 CPUX86State *env = &cpu->env;
1258 int rv = 0;
1259 FeatureWord w;
1260
1261 assert(kvm_enabled());
1262
1263 for (w = 0; w < FEATURE_WORDS; w++) {
1264 FeatureWordInfo *wi = &feature_word_info[w];
1265 uint32_t guest_feat = env->features[w];
1266 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1267 wi->cpuid_ecx,
1268 wi->cpuid_reg);
1269 uint32_t mask;
1270 for (mask = 1; mask; mask <<= 1) {
1271 if (guest_feat & mask && !(host_feat & mask)) {
1272 unavailable_host_feature(wi, mask);
1273 rv = 1;
1274 }
1275 }
1276 }
1277 return rv;
1278 }
1279
1280 static void x86_cpuid_version_get_family(Object *obj, Visitor *v, void *opaque,
1281 const char *name, Error **errp)
1282 {
1283 X86CPU *cpu = X86_CPU(obj);
1284 CPUX86State *env = &cpu->env;
1285 int64_t value;
1286
1287 value = (env->cpuid_version >> 8) & 0xf;
1288 if (value == 0xf) {
1289 value += (env->cpuid_version >> 20) & 0xff;
1290 }
1291 visit_type_int(v, &value, name, errp);
1292 }
1293
1294 static void x86_cpuid_version_set_family(Object *obj, Visitor *v, void *opaque,
1295 const char *name, Error **errp)
1296 {
1297 X86CPU *cpu = X86_CPU(obj);
1298 CPUX86State *env = &cpu->env;
1299 const int64_t min = 0;
1300 const int64_t max = 0xff + 0xf;
1301 Error *local_err = NULL;
1302 int64_t value;
1303
1304 visit_type_int(v, &value, name, &local_err);
1305 if (local_err) {
1306 error_propagate(errp, local_err);
1307 return;
1308 }
1309 if (value < min || value > max) {
1310 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1311 name ? name : "null", value, min, max);
1312 return;
1313 }
1314
1315 env->cpuid_version &= ~0xff00f00;
1316 if (value > 0x0f) {
1317 env->cpuid_version |= 0xf00 | ((value - 0x0f) << 20);
1318 } else {
1319 env->cpuid_version |= value << 8;
1320 }
1321 }
1322
1323 static void x86_cpuid_version_get_model(Object *obj, Visitor *v, void *opaque,
1324 const char *name, Error **errp)
1325 {
1326 X86CPU *cpu = X86_CPU(obj);
1327 CPUX86State *env = &cpu->env;
1328 int64_t value;
1329
1330 value = (env->cpuid_version >> 4) & 0xf;
1331 value |= ((env->cpuid_version >> 16) & 0xf) << 4;
1332 visit_type_int(v, &value, name, errp);
1333 }
1334
1335 static void x86_cpuid_version_set_model(Object *obj, Visitor *v, void *opaque,
1336 const char *name, Error **errp)
1337 {
1338 X86CPU *cpu = X86_CPU(obj);
1339 CPUX86State *env = &cpu->env;
1340 const int64_t min = 0;
1341 const int64_t max = 0xff;
1342 Error *local_err = NULL;
1343 int64_t value;
1344
1345 visit_type_int(v, &value, name, &local_err);
1346 if (local_err) {
1347 error_propagate(errp, local_err);
1348 return;
1349 }
1350 if (value < min || value > max) {
1351 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1352 name ? name : "null", value, min, max);
1353 return;
1354 }
1355
1356 env->cpuid_version &= ~0xf00f0;
1357 env->cpuid_version |= ((value & 0xf) << 4) | ((value >> 4) << 16);
1358 }
1359
1360 static void x86_cpuid_version_get_stepping(Object *obj, Visitor *v,
1361 void *opaque, const char *name,
1362 Error **errp)
1363 {
1364 X86CPU *cpu = X86_CPU(obj);
1365 CPUX86State *env = &cpu->env;
1366 int64_t value;
1367
1368 value = env->cpuid_version & 0xf;
1369 visit_type_int(v, &value, name, errp);
1370 }
1371
1372 static void x86_cpuid_version_set_stepping(Object *obj, Visitor *v,
1373 void *opaque, const char *name,
1374 Error **errp)
1375 {
1376 X86CPU *cpu = X86_CPU(obj);
1377 CPUX86State *env = &cpu->env;
1378 const int64_t min = 0;
1379 const int64_t max = 0xf;
1380 Error *local_err = NULL;
1381 int64_t value;
1382
1383 visit_type_int(v, &value, name, &local_err);
1384 if (local_err) {
1385 error_propagate(errp, local_err);
1386 return;
1387 }
1388 if (value < min || value > max) {
1389 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1390 name ? name : "null", value, min, max);
1391 return;
1392 }
1393
1394 env->cpuid_version &= ~0xf;
1395 env->cpuid_version |= value & 0xf;
1396 }
1397
1398 static void x86_cpuid_get_level(Object *obj, Visitor *v, void *opaque,
1399 const char *name, Error **errp)
1400 {
1401 X86CPU *cpu = X86_CPU(obj);
1402
1403 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1404 }
1405
1406 static void x86_cpuid_set_level(Object *obj, Visitor *v, void *opaque,
1407 const char *name, Error **errp)
1408 {
1409 X86CPU *cpu = X86_CPU(obj);
1410
1411 visit_type_uint32(v, &cpu->env.cpuid_level, name, errp);
1412 }
1413
1414 static void x86_cpuid_get_xlevel(Object *obj, Visitor *v, void *opaque,
1415 const char *name, Error **errp)
1416 {
1417 X86CPU *cpu = X86_CPU(obj);
1418
1419 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1420 }
1421
1422 static void x86_cpuid_set_xlevel(Object *obj, Visitor *v, void *opaque,
1423 const char *name, Error **errp)
1424 {
1425 X86CPU *cpu = X86_CPU(obj);
1426
1427 visit_type_uint32(v, &cpu->env.cpuid_xlevel, name, errp);
1428 }
1429
1430 static char *x86_cpuid_get_vendor(Object *obj, Error **errp)
1431 {
1432 X86CPU *cpu = X86_CPU(obj);
1433 CPUX86State *env = &cpu->env;
1434 char *value;
1435
1436 value = (char *)g_malloc(CPUID_VENDOR_SZ + 1);
1437 x86_cpu_vendor_words2str(value, env->cpuid_vendor1, env->cpuid_vendor2,
1438 env->cpuid_vendor3);
1439 return value;
1440 }
1441
1442 static void x86_cpuid_set_vendor(Object *obj, const char *value,
1443 Error **errp)
1444 {
1445 X86CPU *cpu = X86_CPU(obj);
1446 CPUX86State *env = &cpu->env;
1447 int i;
1448
1449 if (strlen(value) != CPUID_VENDOR_SZ) {
1450 error_set(errp, QERR_PROPERTY_VALUE_BAD, "",
1451 "vendor", value);
1452 return;
1453 }
1454
1455 env->cpuid_vendor1 = 0;
1456 env->cpuid_vendor2 = 0;
1457 env->cpuid_vendor3 = 0;
1458 for (i = 0; i < 4; i++) {
1459 env->cpuid_vendor1 |= ((uint8_t)value[i ]) << (8 * i);
1460 env->cpuid_vendor2 |= ((uint8_t)value[i + 4]) << (8 * i);
1461 env->cpuid_vendor3 |= ((uint8_t)value[i + 8]) << (8 * i);
1462 }
1463 }
1464
1465 static char *x86_cpuid_get_model_id(Object *obj, Error **errp)
1466 {
1467 X86CPU *cpu = X86_CPU(obj);
1468 CPUX86State *env = &cpu->env;
1469 char *value;
1470 int i;
1471
1472 value = g_malloc(48 + 1);
1473 for (i = 0; i < 48; i++) {
1474 value[i] = env->cpuid_model[i >> 2] >> (8 * (i & 3));
1475 }
1476 value[48] = '\0';
1477 return value;
1478 }
1479
1480 static void x86_cpuid_set_model_id(Object *obj, const char *model_id,
1481 Error **errp)
1482 {
1483 X86CPU *cpu = X86_CPU(obj);
1484 CPUX86State *env = &cpu->env;
1485 int c, len, i;
1486
1487 if (model_id == NULL) {
1488 model_id = "";
1489 }
1490 len = strlen(model_id);
1491 memset(env->cpuid_model, 0, 48);
1492 for (i = 0; i < 48; i++) {
1493 if (i >= len) {
1494 c = '\0';
1495 } else {
1496 c = (uint8_t)model_id[i];
1497 }
1498 env->cpuid_model[i >> 2] |= c << (8 * (i & 3));
1499 }
1500 }
1501
1502 static void x86_cpuid_get_tsc_freq(Object *obj, Visitor *v, void *opaque,
1503 const char *name, Error **errp)
1504 {
1505 X86CPU *cpu = X86_CPU(obj);
1506 int64_t value;
1507
1508 value = cpu->env.tsc_khz * 1000;
1509 visit_type_int(v, &value, name, errp);
1510 }
1511
1512 static void x86_cpuid_set_tsc_freq(Object *obj, Visitor *v, void *opaque,
1513 const char *name, Error **errp)
1514 {
1515 X86CPU *cpu = X86_CPU(obj);
1516 const int64_t min = 0;
1517 const int64_t max = INT64_MAX;
1518 Error *local_err = NULL;
1519 int64_t value;
1520
1521 visit_type_int(v, &value, name, &local_err);
1522 if (local_err) {
1523 error_propagate(errp, local_err);
1524 return;
1525 }
1526 if (value < min || value > max) {
1527 error_set(errp, QERR_PROPERTY_VALUE_OUT_OF_RANGE, "",
1528 name ? name : "null", value, min, max);
1529 return;
1530 }
1531
1532 cpu->env.tsc_khz = value / 1000;
1533 }
1534
1535 static void x86_cpuid_get_apic_id(Object *obj, Visitor *v, void *opaque,
1536 const char *name, Error **errp)
1537 {
1538 X86CPU *cpu = X86_CPU(obj);
1539 int64_t value = cpu->env.cpuid_apic_id;
1540
1541 visit_type_int(v, &value, name, errp);
1542 }
1543
1544 static void x86_cpuid_set_apic_id(Object *obj, Visitor *v, void *opaque,
1545 const char *name, Error **errp)
1546 {
1547 X86CPU *cpu = X86_CPU(obj);
1548 DeviceState *dev = DEVICE(obj);
1549 const int64_t min = 0;
1550 const int64_t max = UINT32_MAX;
1551 Error *error = NULL;
1552 int64_t value;
1553
1554 if (dev->realized) {
1555 error_setg(errp, "Attempt to set property '%s' on '%s' after "
1556 "it was realized", name, object_get_typename(obj));
1557 return;
1558 }
1559
1560 visit_type_int(v, &value, name, &error);
1561 if (error) {
1562 error_propagate(errp, error);
1563 return;
1564 }
1565 if (value < min || value > max) {
1566 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1567 " (minimum: %" PRId64 ", maximum: %" PRId64 ")" ,
1568 object_get_typename(obj), name, value, min, max);
1569 return;
1570 }
1571
1572 if ((value != cpu->env.cpuid_apic_id) && cpu_exists(value)) {
1573 error_setg(errp, "CPU with APIC ID %" PRIi64 " exists", value);
1574 return;
1575 }
1576 cpu->env.cpuid_apic_id = value;
1577 }
1578
1579 /* Generic getter for "feature-words" and "filtered-features" properties */
1580 static void x86_cpu_get_feature_words(Object *obj, Visitor *v, void *opaque,
1581 const char *name, Error **errp)
1582 {
1583 uint32_t *array = (uint32_t *)opaque;
1584 FeatureWord w;
1585 Error *err = NULL;
1586 X86CPUFeatureWordInfo word_infos[FEATURE_WORDS] = { };
1587 X86CPUFeatureWordInfoList list_entries[FEATURE_WORDS] = { };
1588 X86CPUFeatureWordInfoList *list = NULL;
1589
1590 for (w = 0; w < FEATURE_WORDS; w++) {
1591 FeatureWordInfo *wi = &feature_word_info[w];
1592 X86CPUFeatureWordInfo *qwi = &word_infos[w];
1593 qwi->cpuid_input_eax = wi->cpuid_eax;
1594 qwi->has_cpuid_input_ecx = wi->cpuid_needs_ecx;
1595 qwi->cpuid_input_ecx = wi->cpuid_ecx;
1596 qwi->cpuid_register = x86_reg_info_32[wi->cpuid_reg].qapi_enum;
1597 qwi->features = array[w];
1598
1599 /* List will be in reverse order, but order shouldn't matter */
1600 list_entries[w].next = list;
1601 list_entries[w].value = &word_infos[w];
1602 list = &list_entries[w];
1603 }
1604
1605 visit_type_X86CPUFeatureWordInfoList(v, &list, "feature-words", &err);
1606 error_propagate(errp, err);
1607 }
1608
1609 static void x86_get_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1610 const char *name, Error **errp)
1611 {
1612 X86CPU *cpu = X86_CPU(obj);
1613 int64_t value = cpu->hyperv_spinlock_attempts;
1614
1615 visit_type_int(v, &value, name, errp);
1616 }
1617
1618 static void x86_set_hv_spinlocks(Object *obj, Visitor *v, void *opaque,
1619 const char *name, Error **errp)
1620 {
1621 const int64_t min = 0xFFF;
1622 const int64_t max = UINT_MAX;
1623 X86CPU *cpu = X86_CPU(obj);
1624 Error *err = NULL;
1625 int64_t value;
1626
1627 visit_type_int(v, &value, name, &err);
1628 if (err) {
1629 error_propagate(errp, err);
1630 return;
1631 }
1632
1633 if (value < min || value > max) {
1634 error_setg(errp, "Property %s.%s doesn't take value %" PRId64
1635 " (minimum: %" PRId64 ", maximum: %" PRId64 ")",
1636 object_get_typename(obj), name ? name : "null",
1637 value, min, max);
1638 return;
1639 }
1640 cpu->hyperv_spinlock_attempts = value;
1641 }
1642
1643 static PropertyInfo qdev_prop_spinlocks = {
1644 .name = "int",
1645 .get = x86_get_hv_spinlocks,
1646 .set = x86_set_hv_spinlocks,
1647 };
1648
1649 /* Convert all '_' in a feature string option name to '-', to make feature
1650 * name conform to QOM property naming rule, which uses '-' instead of '_'.
1651 */
1652 static inline void feat2prop(char *s)
1653 {
1654 while ((s = strchr(s, '_'))) {
1655 *s = '-';
1656 }
1657 }
1658
1659 /* Parse "+feature,-feature,feature=foo" CPU feature string
1660 */
1661 static void x86_cpu_parse_featurestr(CPUState *cs, char *features,
1662 Error **errp)
1663 {
1664 X86CPU *cpu = X86_CPU(cs);
1665 char *featurestr; /* Single 'key=value" string being parsed */
1666 /* Features to be added */
1667 FeatureWordArray plus_features = { 0 };
1668 /* Features to be removed */
1669 FeatureWordArray minus_features = { 0 };
1670 uint32_t numvalue;
1671 CPUX86State *env = &cpu->env;
1672 Error *local_err = NULL;
1673
1674 featurestr = features ? strtok(features, ",") : NULL;
1675
1676 while (featurestr) {
1677 char *val;
1678 if (featurestr[0] == '+') {
1679 add_flagname_to_bitmaps(featurestr + 1, plus_features);
1680 } else if (featurestr[0] == '-') {
1681 add_flagname_to_bitmaps(featurestr + 1, minus_features);
1682 } else if ((val = strchr(featurestr, '='))) {
1683 *val = 0; val++;
1684 feat2prop(featurestr);
1685 if (!strcmp(featurestr, "xlevel")) {
1686 char *err;
1687 char num[32];
1688
1689 numvalue = strtoul(val, &err, 0);
1690 if (!*val || *err) {
1691 error_setg(errp, "bad numerical value %s", val);
1692 return;
1693 }
1694 if (numvalue < 0x80000000) {
1695 error_report("xlevel value shall always be >= 0x80000000"
1696 ", fixup will be removed in future versions");
1697 numvalue += 0x80000000;
1698 }
1699 snprintf(num, sizeof(num), "%" PRIu32, numvalue);
1700 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
1701 } else if (!strcmp(featurestr, "tsc-freq")) {
1702 int64_t tsc_freq;
1703 char *err;
1704 char num[32];
1705
1706 tsc_freq = strtosz_suffix_unit(val, &err,
1707 STRTOSZ_DEFSUFFIX_B, 1000);
1708 if (tsc_freq < 0 || *err) {
1709 error_setg(errp, "bad numerical value %s", val);
1710 return;
1711 }
1712 snprintf(num, sizeof(num), "%" PRId64, tsc_freq);
1713 object_property_parse(OBJECT(cpu), num, "tsc-frequency",
1714 &local_err);
1715 } else if (!strcmp(featurestr, "hv-spinlocks")) {
1716 char *err;
1717 const int min = 0xFFF;
1718 char num[32];
1719 numvalue = strtoul(val, &err, 0);
1720 if (!*val || *err) {
1721 error_setg(errp, "bad numerical value %s", val);
1722 return;
1723 }
1724 if (numvalue < min) {
1725 error_report("hv-spinlocks value shall always be >= 0x%x"
1726 ", fixup will be removed in future versions",
1727 min);
1728 numvalue = min;
1729 }
1730 snprintf(num, sizeof(num), "%" PRId32, numvalue);
1731 object_property_parse(OBJECT(cpu), num, featurestr, &local_err);
1732 } else {
1733 object_property_parse(OBJECT(cpu), val, featurestr, &local_err);
1734 }
1735 } else {
1736 feat2prop(featurestr);
1737 object_property_parse(OBJECT(cpu), "on", featurestr, &local_err);
1738 }
1739 if (local_err) {
1740 error_propagate(errp, local_err);
1741 return;
1742 }
1743 featurestr = strtok(NULL, ",");
1744 }
1745 env->features[FEAT_1_EDX] |= plus_features[FEAT_1_EDX];
1746 env->features[FEAT_1_ECX] |= plus_features[FEAT_1_ECX];
1747 env->features[FEAT_8000_0001_EDX] |= plus_features[FEAT_8000_0001_EDX];
1748 env->features[FEAT_8000_0001_ECX] |= plus_features[FEAT_8000_0001_ECX];
1749 env->features[FEAT_C000_0001_EDX] |= plus_features[FEAT_C000_0001_EDX];
1750 env->features[FEAT_KVM] |= plus_features[FEAT_KVM];
1751 env->features[FEAT_SVM] |= plus_features[FEAT_SVM];
1752 env->features[FEAT_7_0_EBX] |= plus_features[FEAT_7_0_EBX];
1753 env->features[FEAT_1_EDX] &= ~minus_features[FEAT_1_EDX];
1754 env->features[FEAT_1_ECX] &= ~minus_features[FEAT_1_ECX];
1755 env->features[FEAT_8000_0001_EDX] &= ~minus_features[FEAT_8000_0001_EDX];
1756 env->features[FEAT_8000_0001_ECX] &= ~minus_features[FEAT_8000_0001_ECX];
1757 env->features[FEAT_C000_0001_EDX] &= ~minus_features[FEAT_C000_0001_EDX];
1758 env->features[FEAT_KVM] &= ~minus_features[FEAT_KVM];
1759 env->features[FEAT_SVM] &= ~minus_features[FEAT_SVM];
1760 env->features[FEAT_7_0_EBX] &= ~minus_features[FEAT_7_0_EBX];
1761 }
1762
1763 /* generate a composite string into buf of all cpuid names in featureset
1764 * selected by fbits. indicate truncation at bufsize in the event of overflow.
1765 * if flags, suppress names undefined in featureset.
1766 */
1767 static void listflags(char *buf, int bufsize, uint32_t fbits,
1768 const char **featureset, uint32_t flags)
1769 {
1770 const char **p = &featureset[31];
1771 char *q, *b, bit;
1772 int nc;
1773
1774 b = 4 <= bufsize ? buf + (bufsize -= 3) - 1 : NULL;
1775 *buf = '\0';
1776 for (q = buf, bit = 31; fbits && bufsize; --p, fbits &= ~(1 << bit), --bit)
1777 if (fbits & 1 << bit && (*p || !flags)) {
1778 if (*p)
1779 nc = snprintf(q, bufsize, "%s%s", q == buf ? "" : " ", *p);
1780 else
1781 nc = snprintf(q, bufsize, "%s[%d]", q == buf ? "" : " ", bit);
1782 if (bufsize <= nc) {
1783 if (b) {
1784 memcpy(b, "...", sizeof("..."));
1785 }
1786 return;
1787 }
1788 q += nc;
1789 bufsize -= nc;
1790 }
1791 }
1792
1793 /* generate CPU information. */
1794 void x86_cpu_list(FILE *f, fprintf_function cpu_fprintf)
1795 {
1796 X86CPUDefinition *def;
1797 char buf[256];
1798 int i;
1799
1800 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1801 def = &builtin_x86_defs[i];
1802 snprintf(buf, sizeof(buf), "%s", def->name);
1803 (*cpu_fprintf)(f, "x86 %16s %-48s\n", buf, def->model_id);
1804 }
1805 #ifdef CONFIG_KVM
1806 (*cpu_fprintf)(f, "x86 %16s %-48s\n", "host",
1807 "KVM processor with all supported host features "
1808 "(only available in KVM mode)");
1809 #endif
1810
1811 (*cpu_fprintf)(f, "\nRecognized CPUID flags:\n");
1812 for (i = 0; i < ARRAY_SIZE(feature_word_info); i++) {
1813 FeatureWordInfo *fw = &feature_word_info[i];
1814
1815 listflags(buf, sizeof(buf), (uint32_t)~0, fw->feat_names, 1);
1816 (*cpu_fprintf)(f, " %s\n", buf);
1817 }
1818 }
1819
1820 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
1821 {
1822 CpuDefinitionInfoList *cpu_list = NULL;
1823 X86CPUDefinition *def;
1824 int i;
1825
1826 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
1827 CpuDefinitionInfoList *entry;
1828 CpuDefinitionInfo *info;
1829
1830 def = &builtin_x86_defs[i];
1831 info = g_malloc0(sizeof(*info));
1832 info->name = g_strdup(def->name);
1833
1834 entry = g_malloc0(sizeof(*entry));
1835 entry->value = info;
1836 entry->next = cpu_list;
1837 cpu_list = entry;
1838 }
1839
1840 return cpu_list;
1841 }
1842
1843 static void filter_features_for_kvm(X86CPU *cpu)
1844 {
1845 CPUX86State *env = &cpu->env;
1846 KVMState *s = kvm_state;
1847 FeatureWord w;
1848
1849 for (w = 0; w < FEATURE_WORDS; w++) {
1850 FeatureWordInfo *wi = &feature_word_info[w];
1851 uint32_t host_feat = kvm_arch_get_supported_cpuid(s, wi->cpuid_eax,
1852 wi->cpuid_ecx,
1853 wi->cpuid_reg);
1854 uint32_t requested_features = env->features[w];
1855 env->features[w] &= host_feat;
1856 cpu->filtered_features[w] = requested_features & ~env->features[w];
1857 }
1858 }
1859
1860 /* Load data from X86CPUDefinition
1861 */
1862 static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
1863 {
1864 CPUX86State *env = &cpu->env;
1865 const char *vendor;
1866 char host_vendor[CPUID_VENDOR_SZ + 1];
1867
1868 object_property_set_int(OBJECT(cpu), def->level, "level", errp);
1869 object_property_set_int(OBJECT(cpu), def->family, "family", errp);
1870 object_property_set_int(OBJECT(cpu), def->model, "model", errp);
1871 object_property_set_int(OBJECT(cpu), def->stepping, "stepping", errp);
1872 env->features[FEAT_1_EDX] = def->features[FEAT_1_EDX];
1873 env->features[FEAT_1_ECX] = def->features[FEAT_1_ECX];
1874 env->features[FEAT_8000_0001_EDX] = def->features[FEAT_8000_0001_EDX];
1875 env->features[FEAT_8000_0001_ECX] = def->features[FEAT_8000_0001_ECX];
1876 object_property_set_int(OBJECT(cpu), def->xlevel, "xlevel", errp);
1877 env->features[FEAT_KVM] = def->features[FEAT_KVM];
1878 env->features[FEAT_SVM] = def->features[FEAT_SVM];
1879 env->features[FEAT_C000_0001_EDX] = def->features[FEAT_C000_0001_EDX];
1880 env->features[FEAT_7_0_EBX] = def->features[FEAT_7_0_EBX];
1881 env->cpuid_xlevel2 = def->xlevel2;
1882 cpu->cache_info_passthrough = def->cache_info_passthrough;
1883
1884 object_property_set_str(OBJECT(cpu), def->model_id, "model-id", errp);
1885
1886 /* Special cases not set in the X86CPUDefinition structs: */
1887 if (kvm_enabled()) {
1888 FeatureWord w;
1889 for (w = 0; w < FEATURE_WORDS; w++) {
1890 env->features[w] |= kvm_default_features[w];
1891 }
1892 }
1893
1894 env->features[FEAT_1_ECX] |= CPUID_EXT_HYPERVISOR;
1895
1896 /* sysenter isn't supported in compatibility mode on AMD,
1897 * syscall isn't supported in compatibility mode on Intel.
1898 * Normally we advertise the actual CPU vendor, but you can
1899 * override this using the 'vendor' property if you want to use
1900 * KVM's sysenter/syscall emulation in compatibility mode and
1901 * when doing cross vendor migration
1902 */
1903 vendor = def->vendor;
1904 if (kvm_enabled()) {
1905 uint32_t ebx = 0, ecx = 0, edx = 0;
1906 host_cpuid(0, 0, NULL, &ebx, &ecx, &edx);
1907 x86_cpu_vendor_words2str(host_vendor, ebx, edx, ecx);
1908 vendor = host_vendor;
1909 }
1910
1911 object_property_set_str(OBJECT(cpu), vendor, "vendor", errp);
1912
1913 }
1914
1915 X86CPU *cpu_x86_create(const char *cpu_model, DeviceState *icc_bridge,
1916 Error **errp)
1917 {
1918 X86CPU *cpu = NULL;
1919 X86CPUClass *xcc;
1920 ObjectClass *oc;
1921 gchar **model_pieces;
1922 char *name, *features;
1923 Error *error = NULL;
1924
1925 model_pieces = g_strsplit(cpu_model, ",", 2);
1926 if (!model_pieces[0]) {
1927 error_setg(&error, "Invalid/empty CPU model name");
1928 goto out;
1929 }
1930 name = model_pieces[0];
1931 features = model_pieces[1];
1932
1933 oc = x86_cpu_class_by_name(name);
1934 if (oc == NULL) {
1935 error_setg(&error, "Unable to find CPU definition: %s", name);
1936 goto out;
1937 }
1938 xcc = X86_CPU_CLASS(oc);
1939
1940 if (xcc->kvm_required && !kvm_enabled()) {
1941 error_setg(&error, "CPU model '%s' requires KVM", name);
1942 goto out;
1943 }
1944
1945 cpu = X86_CPU(object_new(object_class_get_name(oc)));
1946
1947 #ifndef CONFIG_USER_ONLY
1948 if (icc_bridge == NULL) {
1949 error_setg(&error, "Invalid icc-bridge value");
1950 goto out;
1951 }
1952 qdev_set_parent_bus(DEVICE(cpu), qdev_get_child_bus(icc_bridge, "icc"));
1953 object_unref(OBJECT(cpu));
1954 #endif
1955
1956 x86_cpu_parse_featurestr(CPU(cpu), features, &error);
1957 if (error) {
1958 goto out;
1959 }
1960
1961 out:
1962 if (error != NULL) {
1963 error_propagate(errp, error);
1964 if (cpu) {
1965 object_unref(OBJECT(cpu));
1966 cpu = NULL;
1967 }
1968 }
1969 g_strfreev(model_pieces);
1970 return cpu;
1971 }
1972
1973 X86CPU *cpu_x86_init(const char *cpu_model)
1974 {
1975 Error *error = NULL;
1976 X86CPU *cpu;
1977
1978 cpu = cpu_x86_create(cpu_model, NULL, &error);
1979 if (error) {
1980 goto out;
1981 }
1982
1983 object_property_set_bool(OBJECT(cpu), true, "realized", &error);
1984
1985 out:
1986 if (error) {
1987 error_report("%s", error_get_pretty(error));
1988 error_free(error);
1989 if (cpu != NULL) {
1990 object_unref(OBJECT(cpu));
1991 cpu = NULL;
1992 }
1993 }
1994 return cpu;
1995 }
1996
1997 static void x86_cpu_cpudef_class_init(ObjectClass *oc, void *data)
1998 {
1999 X86CPUDefinition *cpudef = data;
2000 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2001
2002 xcc->cpu_def = cpudef;
2003 }
2004
2005 static void x86_register_cpudef_type(X86CPUDefinition *def)
2006 {
2007 char *typename = x86_cpu_type_name(def->name);
2008 TypeInfo ti = {
2009 .name = typename,
2010 .parent = TYPE_X86_CPU,
2011 .class_init = x86_cpu_cpudef_class_init,
2012 .class_data = def,
2013 };
2014
2015 type_register(&ti);
2016 g_free(typename);
2017 }
2018
2019 #if !defined(CONFIG_USER_ONLY)
2020
2021 void cpu_clear_apic_feature(CPUX86State *env)
2022 {
2023 env->features[FEAT_1_EDX] &= ~CPUID_APIC;
2024 }
2025
2026 #endif /* !CONFIG_USER_ONLY */
2027
2028 /* Initialize list of CPU models, filling some non-static fields if necessary
2029 */
2030 void x86_cpudef_setup(void)
2031 {
2032 int i, j;
2033 static const char *model_with_versions[] = { "qemu32", "qemu64", "athlon" };
2034
2035 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); ++i) {
2036 X86CPUDefinition *def = &builtin_x86_defs[i];
2037
2038 /* Look for specific "cpudef" models that */
2039 /* have the QEMU version in .model_id */
2040 for (j = 0; j < ARRAY_SIZE(model_with_versions); j++) {
2041 if (strcmp(model_with_versions[j], def->name) == 0) {
2042 pstrcpy(def->model_id, sizeof(def->model_id),
2043 "QEMU Virtual CPU version ");
2044 pstrcat(def->model_id, sizeof(def->model_id),
2045 qemu_get_version());
2046 break;
2047 }
2048 }
2049 }
2050 }
2051
2052 static void get_cpuid_vendor(CPUX86State *env, uint32_t *ebx,
2053 uint32_t *ecx, uint32_t *edx)
2054 {
2055 *ebx = env->cpuid_vendor1;
2056 *edx = env->cpuid_vendor2;
2057 *ecx = env->cpuid_vendor3;
2058 }
2059
2060 void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count,
2061 uint32_t *eax, uint32_t *ebx,
2062 uint32_t *ecx, uint32_t *edx)
2063 {
2064 X86CPU *cpu = x86_env_get_cpu(env);
2065 CPUState *cs = CPU(cpu);
2066
2067 /* test if maximum index reached */
2068 if (index & 0x80000000) {
2069 if (index > env->cpuid_xlevel) {
2070 if (env->cpuid_xlevel2 > 0) {
2071 /* Handle the Centaur's CPUID instruction. */
2072 if (index > env->cpuid_xlevel2) {
2073 index = env->cpuid_xlevel2;
2074 } else if (index < 0xC0000000) {
2075 index = env->cpuid_xlevel;
2076 }
2077 } else {
2078 /* Intel documentation states that invalid EAX input will
2079 * return the same information as EAX=cpuid_level
2080 * (Intel SDM Vol. 2A - Instruction Set Reference - CPUID)
2081 */
2082 index = env->cpuid_level;
2083 }
2084 }
2085 } else {
2086 if (index > env->cpuid_level)
2087 index = env->cpuid_level;
2088 }
2089
2090 switch(index) {
2091 case 0:
2092 *eax = env->cpuid_level;
2093 get_cpuid_vendor(env, ebx, ecx, edx);
2094 break;
2095 case 1:
2096 *eax = env->cpuid_version;
2097 *ebx = (env->cpuid_apic_id << 24) | 8 << 8; /* CLFLUSH size in quad words, Linux wants it. */
2098 *ecx = env->features[FEAT_1_ECX];
2099 *edx = env->features[FEAT_1_EDX];
2100 if (cs->nr_cores * cs->nr_threads > 1) {
2101 *ebx |= (cs->nr_cores * cs->nr_threads) << 16;
2102 *edx |= 1 << 28; /* HTT bit */
2103 }
2104 break;
2105 case 2:
2106 /* cache info: needed for Pentium Pro compatibility */
2107 if (cpu->cache_info_passthrough) {
2108 host_cpuid(index, 0, eax, ebx, ecx, edx);
2109 break;
2110 }
2111 *eax = 1; /* Number of CPUID[EAX=2] calls required */
2112 *ebx = 0;
2113 *ecx = 0;
2114 *edx = (L1D_DESCRIPTOR << 16) | \
2115 (L1I_DESCRIPTOR << 8) | \
2116 (L2_DESCRIPTOR);
2117 break;
2118 case 4:
2119 /* cache info: needed for Core compatibility */
2120 if (cpu->cache_info_passthrough) {
2121 host_cpuid(index, count, eax, ebx, ecx, edx);
2122 *eax &= ~0xFC000000;
2123 } else {
2124 *eax = 0;
2125 switch (count) {
2126 case 0: /* L1 dcache info */
2127 *eax |= CPUID_4_TYPE_DCACHE | \
2128 CPUID_4_LEVEL(1) | \
2129 CPUID_4_SELF_INIT_LEVEL;
2130 *ebx = (L1D_LINE_SIZE - 1) | \
2131 ((L1D_PARTITIONS - 1) << 12) | \
2132 ((L1D_ASSOCIATIVITY - 1) << 22);
2133 *ecx = L1D_SETS - 1;
2134 *edx = CPUID_4_NO_INVD_SHARING;
2135 break;
2136 case 1: /* L1 icache info */
2137 *eax |= CPUID_4_TYPE_ICACHE | \
2138 CPUID_4_LEVEL(1) | \
2139 CPUID_4_SELF_INIT_LEVEL;
2140 *ebx = (L1I_LINE_SIZE - 1) | \
2141 ((L1I_PARTITIONS - 1) << 12) | \
2142 ((L1I_ASSOCIATIVITY - 1) << 22);
2143 *ecx = L1I_SETS - 1;
2144 *edx = CPUID_4_NO_INVD_SHARING;
2145 break;
2146 case 2: /* L2 cache info */
2147 *eax |= CPUID_4_TYPE_UNIFIED | \
2148 CPUID_4_LEVEL(2) | \
2149 CPUID_4_SELF_INIT_LEVEL;
2150 if (cs->nr_threads > 1) {
2151 *eax |= (cs->nr_threads - 1) << 14;
2152 }
2153 *ebx = (L2_LINE_SIZE - 1) | \
2154 ((L2_PARTITIONS - 1) << 12) | \
2155 ((L2_ASSOCIATIVITY - 1) << 22);
2156 *ecx = L2_SETS - 1;
2157 *edx = CPUID_4_NO_INVD_SHARING;
2158 break;
2159 default: /* end of info */
2160 *eax = 0;
2161 *ebx = 0;
2162 *ecx = 0;
2163 *edx = 0;
2164 break;
2165 }
2166 }
2167
2168 /* QEMU gives out its own APIC IDs, never pass down bits 31..26. */
2169 if ((*eax & 31) && cs->nr_cores > 1) {
2170 *eax |= (cs->nr_cores - 1) << 26;
2171 }
2172 break;
2173 case 5:
2174 /* mwait info: needed for Core compatibility */
2175 *eax = 0; /* Smallest monitor-line size in bytes */
2176 *ebx = 0; /* Largest monitor-line size in bytes */
2177 *ecx = CPUID_MWAIT_EMX | CPUID_MWAIT_IBE;
2178 *edx = 0;
2179 break;
2180 case 6:
2181 /* Thermal and Power Leaf */
2182 *eax = 0;
2183 *ebx = 0;
2184 *ecx = 0;
2185 *edx = 0;
2186 break;
2187 case 7:
2188 /* Structured Extended Feature Flags Enumeration Leaf */
2189 if (count == 0) {
2190 *eax = 0; /* Maximum ECX value for sub-leaves */
2191 *ebx = env->features[FEAT_7_0_EBX]; /* Feature flags */
2192 *ecx = 0; /* Reserved */
2193 *edx = 0; /* Reserved */
2194 } else {
2195 *eax = 0;
2196 *ebx = 0;
2197 *ecx = 0;
2198 *edx = 0;
2199 }
2200 break;
2201 case 9:
2202 /* Direct Cache Access Information Leaf */
2203 *eax = 0; /* Bits 0-31 in DCA_CAP MSR */
2204 *ebx = 0;
2205 *ecx = 0;
2206 *edx = 0;
2207 break;
2208 case 0xA:
2209 /* Architectural Performance Monitoring Leaf */
2210 if (kvm_enabled() && cpu->enable_pmu) {
2211 KVMState *s = cs->kvm_state;
2212
2213 *eax = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EAX);
2214 *ebx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EBX);
2215 *ecx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_ECX);
2216 *edx = kvm_arch_get_supported_cpuid(s, 0xA, count, R_EDX);
2217 } else {
2218 *eax = 0;
2219 *ebx = 0;
2220 *ecx = 0;
2221 *edx = 0;
2222 }
2223 break;
2224 case 0xD: {
2225 KVMState *s = cs->kvm_state;
2226 uint64_t kvm_mask;
2227 int i;
2228
2229 /* Processor Extended State */
2230 *eax = 0;
2231 *ebx = 0;
2232 *ecx = 0;
2233 *edx = 0;
2234 if (!(env->features[FEAT_1_ECX] & CPUID_EXT_XSAVE) || !kvm_enabled()) {
2235 break;
2236 }
2237 kvm_mask =
2238 kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EAX) |
2239 ((uint64_t)kvm_arch_get_supported_cpuid(s, 0xd, 0, R_EDX) << 32);
2240
2241 if (count == 0) {
2242 *ecx = 0x240;
2243 for (i = 2; i < ARRAY_SIZE(ext_save_areas); i++) {
2244 const ExtSaveArea *esa = &ext_save_areas[i];
2245 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2246 (kvm_mask & (1 << i)) != 0) {
2247 if (i < 32) {
2248 *eax |= 1 << i;
2249 } else {
2250 *edx |= 1 << (i - 32);
2251 }
2252 *ecx = MAX(*ecx, esa->offset + esa->size);
2253 }
2254 }
2255 *eax |= kvm_mask & (XSTATE_FP | XSTATE_SSE);
2256 *ebx = *ecx;
2257 } else if (count == 1) {
2258 *eax = kvm_arch_get_supported_cpuid(s, 0xd, 1, R_EAX);
2259 } else if (count < ARRAY_SIZE(ext_save_areas)) {
2260 const ExtSaveArea *esa = &ext_save_areas[count];
2261 if ((env->features[esa->feature] & esa->bits) == esa->bits &&
2262 (kvm_mask & (1 << count)) != 0) {
2263 *eax = esa->size;
2264 *ebx = esa->offset;
2265 }
2266 }
2267 break;
2268 }
2269 case 0x80000000:
2270 *eax = env->cpuid_xlevel;
2271 *ebx = env->cpuid_vendor1;
2272 *edx = env->cpuid_vendor2;
2273 *ecx = env->cpuid_vendor3;
2274 break;
2275 case 0x80000001:
2276 *eax = env->cpuid_version;
2277 *ebx = 0;
2278 *ecx = env->features[FEAT_8000_0001_ECX];
2279 *edx = env->features[FEAT_8000_0001_EDX];
2280
2281 /* The Linux kernel checks for the CMPLegacy bit and
2282 * discards multiple thread information if it is set.
2283 * So dont set it here for Intel to make Linux guests happy.
2284 */
2285 if (cs->nr_cores * cs->nr_threads > 1) {
2286 uint32_t tebx, tecx, tedx;
2287 get_cpuid_vendor(env, &tebx, &tecx, &tedx);
2288 if (tebx != CPUID_VENDOR_INTEL_1 ||
2289 tedx != CPUID_VENDOR_INTEL_2 ||
2290 tecx != CPUID_VENDOR_INTEL_3) {
2291 *ecx |= 1 << 1; /* CmpLegacy bit */
2292 }
2293 }
2294 break;
2295 case 0x80000002:
2296 case 0x80000003:
2297 case 0x80000004:
2298 *eax = env->cpuid_model[(index - 0x80000002) * 4 + 0];
2299 *ebx = env->cpuid_model[(index - 0x80000002) * 4 + 1];
2300 *ecx = env->cpuid_model[(index - 0x80000002) * 4 + 2];
2301 *edx = env->cpuid_model[(index - 0x80000002) * 4 + 3];
2302 break;
2303 case 0x80000005:
2304 /* cache info (L1 cache) */
2305 if (cpu->cache_info_passthrough) {
2306 host_cpuid(index, 0, eax, ebx, ecx, edx);
2307 break;
2308 }
2309 *eax = (L1_DTLB_2M_ASSOC << 24) | (L1_DTLB_2M_ENTRIES << 16) | \
2310 (L1_ITLB_2M_ASSOC << 8) | (L1_ITLB_2M_ENTRIES);
2311 *ebx = (L1_DTLB_4K_ASSOC << 24) | (L1_DTLB_4K_ENTRIES << 16) | \
2312 (L1_ITLB_4K_ASSOC << 8) | (L1_ITLB_4K_ENTRIES);
2313 *ecx = (L1D_SIZE_KB_AMD << 24) | (L1D_ASSOCIATIVITY_AMD << 16) | \
2314 (L1D_LINES_PER_TAG << 8) | (L1D_LINE_SIZE);
2315 *edx = (L1I_SIZE_KB_AMD << 24) | (L1I_ASSOCIATIVITY_AMD << 16) | \
2316 (L1I_LINES_PER_TAG << 8) | (L1I_LINE_SIZE);
2317 break;
2318 case 0x80000006:
2319 /* cache info (L2 cache) */
2320 if (cpu->cache_info_passthrough) {
2321 host_cpuid(index, 0, eax, ebx, ecx, edx);
2322 break;
2323 }
2324 *eax = (AMD_ENC_ASSOC(L2_DTLB_2M_ASSOC) << 28) | \
2325 (L2_DTLB_2M_ENTRIES << 16) | \
2326 (AMD_ENC_ASSOC(L2_ITLB_2M_ASSOC) << 12) | \
2327 (L2_ITLB_2M_ENTRIES);
2328 *ebx = (AMD_ENC_ASSOC(L2_DTLB_4K_ASSOC) << 28) | \
2329 (L2_DTLB_4K_ENTRIES << 16) | \
2330 (AMD_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | \
2331 (L2_ITLB_4K_ENTRIES);
2332 *ecx = (L2_SIZE_KB_AMD << 16) | \
2333 (AMD_ENC_ASSOC(L2_ASSOCIATIVITY) << 12) | \
2334 (L2_LINES_PER_TAG << 8) | (L2_LINE_SIZE);
2335 *edx = ((L3_SIZE_KB/512) << 18) | \
2336 (AMD_ENC_ASSOC(L3_ASSOCIATIVITY) << 12) | \
2337 (L3_LINES_PER_TAG << 8) | (L3_LINE_SIZE);
2338 break;
2339 case 0x80000008:
2340 /* virtual & phys address size in low 2 bytes. */
2341 /* XXX: This value must match the one used in the MMU code. */
2342 if (env->features[FEAT_8000_0001_EDX] & CPUID_EXT2_LM) {
2343 /* 64 bit processor */
2344 /* XXX: The physical address space is limited to 42 bits in exec.c. */
2345 *eax = 0x00003028; /* 48 bits virtual, 40 bits physical */
2346 } else {
2347 if (env->features[FEAT_1_EDX] & CPUID_PSE36) {
2348 *eax = 0x00000024; /* 36 bits physical */
2349 } else {
2350 *eax = 0x00000020; /* 32 bits physical */
2351 }
2352 }
2353 *ebx = 0;
2354 *ecx = 0;
2355 *edx = 0;
2356 if (cs->nr_cores * cs->nr_threads > 1) {
2357 *ecx |= (cs->nr_cores * cs->nr_threads) - 1;
2358 }
2359 break;
2360 case 0x8000000A:
2361 if (env->features[FEAT_8000_0001_ECX] & CPUID_EXT3_SVM) {
2362 *eax = 0x00000001; /* SVM Revision */
2363 *ebx = 0x00000010; /* nr of ASIDs */
2364 *ecx = 0;
2365 *edx = env->features[FEAT_SVM]; /* optional features */
2366 } else {
2367 *eax = 0;
2368 *ebx = 0;
2369 *ecx = 0;
2370 *edx = 0;
2371 }
2372 break;
2373 case 0xC0000000:
2374 *eax = env->cpuid_xlevel2;
2375 *ebx = 0;
2376 *ecx = 0;
2377 *edx = 0;
2378 break;
2379 case 0xC0000001:
2380 /* Support for VIA CPU's CPUID instruction */
2381 *eax = env->cpuid_version;
2382 *ebx = 0;
2383 *ecx = 0;
2384 *edx = env->features[FEAT_C000_0001_EDX];
2385 break;
2386 case 0xC0000002:
2387 case 0xC0000003:
2388 case 0xC0000004:
2389 /* Reserved for the future, and now filled with zero */
2390 *eax = 0;
2391 *ebx = 0;
2392 *ecx = 0;
2393 *edx = 0;
2394 break;
2395 default:
2396 /* reserved values: zero */
2397 *eax = 0;
2398 *ebx = 0;
2399 *ecx = 0;
2400 *edx = 0;
2401 break;
2402 }
2403 }
2404
2405 /* CPUClass::reset() */
2406 static void x86_cpu_reset(CPUState *s)
2407 {
2408 X86CPU *cpu = X86_CPU(s);
2409 X86CPUClass *xcc = X86_CPU_GET_CLASS(cpu);
2410 CPUX86State *env = &cpu->env;
2411 int i;
2412
2413 xcc->parent_reset(s);
2414
2415 memset(env, 0, offsetof(CPUX86State, cpuid_level));
2416
2417 tlb_flush(s, 1);
2418
2419 env->old_exception = -1;
2420
2421 /* init to reset state */
2422
2423 #ifdef CONFIG_SOFTMMU
2424 env->hflags |= HF_SOFTMMU_MASK;
2425 #endif
2426 env->hflags2 |= HF2_GIF_MASK;
2427
2428 cpu_x86_update_cr0(env, 0x60000010);
2429 env->a20_mask = ~0x0;
2430 env->smbase = 0x30000;
2431
2432 env->idt.limit = 0xffff;
2433 env->gdt.limit = 0xffff;
2434 env->ldt.limit = 0xffff;
2435 env->ldt.flags = DESC_P_MASK | (2 << DESC_TYPE_SHIFT);
2436 env->tr.limit = 0xffff;
2437 env->tr.flags = DESC_P_MASK | (11 << DESC_TYPE_SHIFT);
2438
2439 cpu_x86_load_seg_cache(env, R_CS, 0xf000, 0xffff0000, 0xffff,
2440 DESC_P_MASK | DESC_S_MASK | DESC_CS_MASK |
2441 DESC_R_MASK | DESC_A_MASK);
2442 cpu_x86_load_seg_cache(env, R_DS, 0, 0, 0xffff,
2443 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2444 DESC_A_MASK);
2445 cpu_x86_load_seg_cache(env, R_ES, 0, 0, 0xffff,
2446 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2447 DESC_A_MASK);
2448 cpu_x86_load_seg_cache(env, R_SS, 0, 0, 0xffff,
2449 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2450 DESC_A_MASK);
2451 cpu_x86_load_seg_cache(env, R_FS, 0, 0, 0xffff,
2452 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2453 DESC_A_MASK);
2454 cpu_x86_load_seg_cache(env, R_GS, 0, 0, 0xffff,
2455 DESC_P_MASK | DESC_S_MASK | DESC_W_MASK |
2456 DESC_A_MASK);
2457
2458 env->eip = 0xfff0;
2459 env->regs[R_EDX] = env->cpuid_version;
2460
2461 env->eflags = 0x2;
2462
2463 /* FPU init */
2464 for (i = 0; i < 8; i++) {
2465 env->fptags[i] = 1;
2466 }
2467 env->fpuc = 0x37f;
2468
2469 env->mxcsr = 0x1f80;
2470 env->xstate_bv = XSTATE_FP | XSTATE_SSE;
2471
2472 env->pat = 0x0007040600070406ULL;
2473 env->msr_ia32_misc_enable = MSR_IA32_MISC_ENABLE_DEFAULT;
2474
2475 memset(env->dr, 0, sizeof(env->dr));
2476 env->dr[6] = DR6_FIXED_1;
2477 env->dr[7] = DR7_FIXED_1;
2478 cpu_breakpoint_remove_all(s, BP_CPU);
2479 cpu_watchpoint_remove_all(s, BP_CPU);
2480
2481 env->xcr0 = 1;
2482
2483 #if !defined(CONFIG_USER_ONLY)
2484 /* We hard-wire the BSP to the first CPU. */
2485 if (s->cpu_index == 0) {
2486 apic_designate_bsp(cpu->apic_state);
2487 }
2488
2489 s->halted = !cpu_is_bsp(cpu);
2490
2491 if (kvm_enabled()) {
2492 kvm_arch_reset_vcpu(cpu);
2493 }
2494 #endif
2495 }
2496
2497 #ifndef CONFIG_USER_ONLY
2498 bool cpu_is_bsp(X86CPU *cpu)
2499 {
2500 return cpu_get_apic_base(cpu->apic_state) & MSR_IA32_APICBASE_BSP;
2501 }
2502
2503 /* TODO: remove me, when reset over QOM tree is implemented */
2504 static void x86_cpu_machine_reset_cb(void *opaque)
2505 {
2506 X86CPU *cpu = opaque;
2507 cpu_reset(CPU(cpu));
2508 }
2509 #endif
2510
2511 static void mce_init(X86CPU *cpu)
2512 {
2513 CPUX86State *cenv = &cpu->env;
2514 unsigned int bank;
2515
2516 if (((cenv->cpuid_version >> 8) & 0xf) >= 6
2517 && (cenv->features[FEAT_1_EDX] & (CPUID_MCE | CPUID_MCA)) ==
2518 (CPUID_MCE | CPUID_MCA)) {
2519 cenv->mcg_cap = MCE_CAP_DEF | MCE_BANKS_DEF;
2520 cenv->mcg_ctl = ~(uint64_t)0;
2521 for (bank = 0; bank < MCE_BANKS_DEF; bank++) {
2522 cenv->mce_banks[bank * 4] = ~(uint64_t)0;
2523 }
2524 }
2525 }
2526
2527 #ifndef CONFIG_USER_ONLY
2528 static void x86_cpu_apic_create(X86CPU *cpu, Error **errp)
2529 {
2530 CPUX86State *env = &cpu->env;
2531 DeviceState *dev = DEVICE(cpu);
2532 APICCommonState *apic;
2533 const char *apic_type = "apic";
2534
2535 if (kvm_irqchip_in_kernel()) {
2536 apic_type = "kvm-apic";
2537 } else if (xen_enabled()) {
2538 apic_type = "xen-apic";
2539 }
2540
2541 cpu->apic_state = qdev_try_create(qdev_get_parent_bus(dev), apic_type);
2542 if (cpu->apic_state == NULL) {
2543 error_setg(errp, "APIC device '%s' could not be created", apic_type);
2544 return;
2545 }
2546
2547 object_property_add_child(OBJECT(cpu), "apic",
2548 OBJECT(cpu->apic_state), NULL);
2549 qdev_prop_set_uint8(cpu->apic_state, "id", env->cpuid_apic_id);
2550 /* TODO: convert to link<> */
2551 apic = APIC_COMMON(cpu->apic_state);
2552 apic->cpu = cpu;
2553 }
2554
2555 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2556 {
2557 if (cpu->apic_state == NULL) {
2558 return;
2559 }
2560
2561 if (qdev_init(cpu->apic_state)) {
2562 error_setg(errp, "APIC device '%s' could not be initialized",
2563 object_get_typename(OBJECT(cpu->apic_state)));
2564 return;
2565 }
2566 }
2567 #else
2568 static void x86_cpu_apic_realize(X86CPU *cpu, Error **errp)
2569 {
2570 }
2571 #endif
2572
2573 static void x86_cpu_realizefn(DeviceState *dev, Error **errp)
2574 {
2575 CPUState *cs = CPU(dev);
2576 X86CPU *cpu = X86_CPU(dev);
2577 X86CPUClass *xcc = X86_CPU_GET_CLASS(dev);
2578 CPUX86State *env = &cpu->env;
2579 Error *local_err = NULL;
2580
2581 if (env->features[FEAT_7_0_EBX] && env->cpuid_level < 7) {
2582 env->cpuid_level = 7;
2583 }
2584
2585 /* On AMD CPUs, some CPUID[8000_0001].EDX bits must match the bits on
2586 * CPUID[1].EDX.
2587 */
2588 if (env->cpuid_vendor1 == CPUID_VENDOR_AMD_1 &&
2589 env->cpuid_vendor2 == CPUID_VENDOR_AMD_2 &&
2590 env->cpuid_vendor3 == CPUID_VENDOR_AMD_3) {
2591 env->features[FEAT_8000_0001_EDX] &= ~CPUID_EXT2_AMD_ALIASES;
2592 env->features[FEAT_8000_0001_EDX] |= (env->features[FEAT_1_EDX]
2593 & CPUID_EXT2_AMD_ALIASES);
2594 }
2595
2596 if (!kvm_enabled()) {
2597 env->features[FEAT_1_EDX] &= TCG_FEATURES;
2598 env->features[FEAT_1_ECX] &= TCG_EXT_FEATURES;
2599 env->features[FEAT_8000_0001_EDX] &= (TCG_EXT2_FEATURES
2600 #ifdef TARGET_X86_64
2601 | CPUID_EXT2_SYSCALL | CPUID_EXT2_LM
2602 #endif
2603 );
2604 env->features[FEAT_8000_0001_ECX] &= TCG_EXT3_FEATURES;
2605 env->features[FEAT_SVM] &= TCG_SVM_FEATURES;
2606 } else {
2607 KVMState *s = kvm_state;
2608 if ((cpu->check_cpuid || cpu->enforce_cpuid)
2609 && kvm_check_features_against_host(s, cpu) && cpu->enforce_cpuid) {
2610 error_setg(&local_err,
2611 "Host's CPU doesn't support requested features");
2612 goto out;
2613 }
2614 filter_features_for_kvm(cpu);
2615 }
2616
2617 #ifndef CONFIG_USER_ONLY
2618 qemu_register_reset(x86_cpu_machine_reset_cb, cpu);
2619
2620 if (cpu->env.features[FEAT_1_EDX] & CPUID_APIC || smp_cpus > 1) {
2621 x86_cpu_apic_create(cpu, &local_err);
2622 if (local_err != NULL) {
2623 goto out;
2624 }
2625 }
2626 #endif
2627
2628 mce_init(cpu);
2629 qemu_init_vcpu(cs);
2630
2631 x86_cpu_apic_realize(cpu, &local_err);
2632 if (local_err != NULL) {
2633 goto out;
2634 }
2635 cpu_reset(cs);
2636
2637 xcc->parent_realize(dev, &local_err);
2638 out:
2639 if (local_err != NULL) {
2640 error_propagate(errp, local_err);
2641 return;
2642 }
2643 }
2644
2645 /* Enables contiguous-apic-ID mode, for compatibility */
2646 static bool compat_apic_id_mode;
2647
2648 void enable_compat_apic_id_mode(void)
2649 {
2650 compat_apic_id_mode = true;
2651 }
2652
2653 /* Calculates initial APIC ID for a specific CPU index
2654 *
2655 * Currently we need to be able to calculate the APIC ID from the CPU index
2656 * alone (without requiring a CPU object), as the QEMU<->Seabios interfaces have
2657 * no concept of "CPU index", and the NUMA tables on fw_cfg need the APIC ID of
2658 * all CPUs up to max_cpus.
2659 */
2660 uint32_t x86_cpu_apic_id_from_index(unsigned int cpu_index)
2661 {
2662 uint32_t correct_id;
2663 static bool warned;
2664
2665 correct_id = x86_apicid_from_cpu_idx(smp_cores, smp_threads, cpu_index);
2666 if (compat_apic_id_mode) {
2667 if (cpu_index != correct_id && !warned) {
2668 error_report("APIC IDs set in compatibility mode, "
2669 "CPU topology won't match the configuration");
2670 warned = true;
2671 }
2672 return cpu_index;
2673 } else {
2674 return correct_id;
2675 }
2676 }
2677
2678 static void x86_cpu_initfn(Object *obj)
2679 {
2680 CPUState *cs = CPU(obj);
2681 X86CPU *cpu = X86_CPU(obj);
2682 X86CPUClass *xcc = X86_CPU_GET_CLASS(obj);
2683 CPUX86State *env = &cpu->env;
2684 static int inited;
2685
2686 cs->env_ptr = env;
2687 cpu_exec_init(env);
2688
2689 object_property_add(obj, "family", "int",
2690 x86_cpuid_version_get_family,
2691 x86_cpuid_version_set_family, NULL, NULL, NULL);
2692 object_property_add(obj, "model", "int",
2693 x86_cpuid_version_get_model,
2694 x86_cpuid_version_set_model, NULL, NULL, NULL);
2695 object_property_add(obj, "stepping", "int",
2696 x86_cpuid_version_get_stepping,
2697 x86_cpuid_version_set_stepping, NULL, NULL, NULL);
2698 object_property_add(obj, "level", "int",
2699 x86_cpuid_get_level,
2700 x86_cpuid_set_level, NULL, NULL, NULL);
2701 object_property_add(obj, "xlevel", "int",
2702 x86_cpuid_get_xlevel,
2703 x86_cpuid_set_xlevel, NULL, NULL, NULL);
2704 object_property_add_str(obj, "vendor",
2705 x86_cpuid_get_vendor,
2706 x86_cpuid_set_vendor, NULL);
2707 object_property_add_str(obj, "model-id",
2708 x86_cpuid_get_model_id,
2709 x86_cpuid_set_model_id, NULL);
2710 object_property_add(obj, "tsc-frequency", "int",
2711 x86_cpuid_get_tsc_freq,
2712 x86_cpuid_set_tsc_freq, NULL, NULL, NULL);
2713 object_property_add(obj, "apic-id", "int",
2714 x86_cpuid_get_apic_id,
2715 x86_cpuid_set_apic_id, NULL, NULL, NULL);
2716 object_property_add(obj, "feature-words", "X86CPUFeatureWordInfo",
2717 x86_cpu_get_feature_words,
2718 NULL, NULL, (void *)env->features, NULL);
2719 object_property_add(obj, "filtered-features", "X86CPUFeatureWordInfo",
2720 x86_cpu_get_feature_words,
2721 NULL, NULL, (void *)cpu->filtered_features, NULL);
2722
2723 cpu->hyperv_spinlock_attempts = HYPERV_SPINLOCK_NEVER_RETRY;
2724 env->cpuid_apic_id = x86_cpu_apic_id_from_index(cs->cpu_index);
2725
2726 x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
2727
2728 /* init various static tables used in TCG mode */
2729 if (tcg_enabled() && !inited) {
2730 inited = 1;
2731 optimize_flags_init();
2732 #ifndef CONFIG_USER_ONLY
2733 cpu_set_debug_excp_handler(breakpoint_handler);
2734 #endif
2735 }
2736 }
2737
2738 static int64_t x86_cpu_get_arch_id(CPUState *cs)
2739 {
2740 X86CPU *cpu = X86_CPU(cs);
2741 CPUX86State *env = &cpu->env;
2742
2743 return env->cpuid_apic_id;
2744 }
2745
2746 static bool x86_cpu_get_paging_enabled(const CPUState *cs)
2747 {
2748 X86CPU *cpu = X86_CPU(cs);
2749
2750 return cpu->env.cr[0] & CR0_PG_MASK;
2751 }
2752
2753 static void x86_cpu_set_pc(CPUState *cs, vaddr value)
2754 {
2755 X86CPU *cpu = X86_CPU(cs);
2756
2757 cpu->env.eip = value;
2758 }
2759
2760 static void x86_cpu_synchronize_from_tb(CPUState *cs, TranslationBlock *tb)
2761 {
2762 X86CPU *cpu = X86_CPU(cs);
2763
2764 cpu->env.eip = tb->pc - tb->cs_base;
2765 }
2766
2767 static bool x86_cpu_has_work(CPUState *cs)
2768 {
2769 X86CPU *cpu = X86_CPU(cs);
2770 CPUX86State *env = &cpu->env;
2771
2772 return ((cs->interrupt_request & (CPU_INTERRUPT_HARD |
2773 CPU_INTERRUPT_POLL)) &&
2774 (env->eflags & IF_MASK)) ||
2775 (cs->interrupt_request & (CPU_INTERRUPT_NMI |
2776 CPU_INTERRUPT_INIT |
2777 CPU_INTERRUPT_SIPI |
2778 CPU_INTERRUPT_MCE));
2779 }
2780
2781 static Property x86_cpu_properties[] = {
2782 DEFINE_PROP_BOOL("pmu", X86CPU, enable_pmu, false),
2783 { .name = "hv-spinlocks", .info = &qdev_prop_spinlocks },
2784 DEFINE_PROP_BOOL("hv-relaxed", X86CPU, hyperv_relaxed_timing, false),
2785 DEFINE_PROP_BOOL("hv-vapic", X86CPU, hyperv_vapic, false),
2786 DEFINE_PROP_BOOL("hv-time", X86CPU, hyperv_time, false),
2787 DEFINE_PROP_BOOL("check", X86CPU, check_cpuid, false),
2788 DEFINE_PROP_BOOL("enforce", X86CPU, enforce_cpuid, false),
2789 DEFINE_PROP_BOOL("kvm", X86CPU, expose_kvm, true),
2790 DEFINE_PROP_END_OF_LIST()
2791 };
2792
2793 static void x86_cpu_common_class_init(ObjectClass *oc, void *data)
2794 {
2795 X86CPUClass *xcc = X86_CPU_CLASS(oc);
2796 CPUClass *cc = CPU_CLASS(oc);
2797 DeviceClass *dc = DEVICE_CLASS(oc);
2798
2799 xcc->parent_realize = dc->realize;
2800 dc->realize = x86_cpu_realizefn;
2801 dc->bus_type = TYPE_ICC_BUS;
2802 dc->props = x86_cpu_properties;
2803
2804 xcc->parent_reset = cc->reset;
2805 cc->reset = x86_cpu_reset;
2806 cc->reset_dump_flags = CPU_DUMP_FPU | CPU_DUMP_CCOP;
2807
2808 cc->class_by_name = x86_cpu_class_by_name;
2809 cc->parse_features = x86_cpu_parse_featurestr;
2810 cc->has_work = x86_cpu_has_work;
2811 cc->do_interrupt = x86_cpu_do_interrupt;
2812 cc->dump_state = x86_cpu_dump_state;
2813 cc->set_pc = x86_cpu_set_pc;
2814 cc->synchronize_from_tb = x86_cpu_synchronize_from_tb;
2815 cc->gdb_read_register = x86_cpu_gdb_read_register;
2816 cc->gdb_write_register = x86_cpu_gdb_write_register;
2817 cc->get_arch_id = x86_cpu_get_arch_id;
2818 cc->get_paging_enabled = x86_cpu_get_paging_enabled;
2819 #ifdef CONFIG_USER_ONLY
2820 cc->handle_mmu_fault = x86_cpu_handle_mmu_fault;
2821 #else
2822 cc->get_memory_mapping = x86_cpu_get_memory_mapping;
2823 cc->get_phys_page_debug = x86_cpu_get_phys_page_debug;
2824 cc->write_elf64_note = x86_cpu_write_elf64_note;
2825 cc->write_elf64_qemunote = x86_cpu_write_elf64_qemunote;
2826 cc->write_elf32_note = x86_cpu_write_elf32_note;
2827 cc->write_elf32_qemunote = x86_cpu_write_elf32_qemunote;
2828 cc->vmsd = &vmstate_x86_cpu;
2829 #endif
2830 cc->gdb_num_core_regs = CPU_NB_REGS * 2 + 25;
2831 }
2832
2833 static const TypeInfo x86_cpu_type_info = {
2834 .name = TYPE_X86_CPU,
2835 .parent = TYPE_CPU,
2836 .instance_size = sizeof(X86CPU),
2837 .instance_init = x86_cpu_initfn,
2838 .abstract = true,
2839 .class_size = sizeof(X86CPUClass),
2840 .class_init = x86_cpu_common_class_init,
2841 };
2842
2843 static void x86_cpu_register_types(void)
2844 {
2845 int i;
2846
2847 type_register_static(&x86_cpu_type_info);
2848 for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
2849 x86_register_cpudef_type(&builtin_x86_defs[i]);
2850 }
2851 #ifdef CONFIG_KVM
2852 type_register_static(&host_x86_cpu_type_info);
2853 #endif
2854 }
2855
2856 type_init(x86_cpu_register_types)
QEMU modified to work with kvm