hw/acpi_piix4.c

   1 /*
   2  * ACPI implementation
   3  *
   4  * Copyright (c) 2006 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License version 2 as published by the Free Software Foundation.
   9  *
  10  * This library is distributed in the hope that it will be useful,
  11  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  13  * Lesser General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU Lesser General Public
  16  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  17  */
  18 #include "hw.h"
  19 #include "pc.h"
  20 #include "apm.h"
  21 #include "pm_smbus.h"
  22 #include "pci.h"
  23 #include "acpi.h"
  24 #include "sysemu.h"
  25 #include "range.h"
  26 #include "ioport.h"
  27
  28 //#define DEBUG
  29
  30 #ifdef DEBUG
  31 # define PIIX4_DPRINTF(format, ...)     printf(format, ## __VA_ARGS__)
  32 #else
  33 # define PIIX4_DPRINTF(format, ...)     do { } while (0)
  34 #endif
  35
  36 #define ACPI_DBG_IO_ADDR  0xb044
  37
  38 #define GPE_BASE 0xafe0
  39 #define PROC_BASE 0xaf00
  40 #define GPE_LEN 4
  41 #define PCI_BASE 0xae00
  42 #define PCI_EJ_BASE 0xae08
  43 #define PCI_RMV_BASE 0xae0c
  44
  45 #define PIIX4_CPU_HOTPLUG_STATUS 4
  46 #define PIIX4_PCI_HOTPLUG_STATUS 2
  47
  48 struct gpe_regs {
  49     uint8_t cpus_sts[32];
  50 };
  51
  52 struct pci_status {
  53     uint32_t up;
  54     uint32_t down;
  55 };
  56
  57 typedef struct PIIX4PMState {
  58     PCIDevice dev;
  59     IORange ioport;
  60     ACPIPM1EVT pm1a;
  61     ACPIPM1CNT pm1_cnt;
  62
  63     APMState apm;
  64
  65     ACPIPMTimer tmr;
  66
  67     PMSMBus smb;
  68     uint32_t smb_io_base;
  69
  70     qemu_irq irq;
  71     qemu_irq smi_irq;
  72     int kvm_enabled;
  73     Notifier machine_ready;
  74
  75     /* for pci hotplug */
  76     ACPIGPE gpe;
  77     struct gpe_regs gpe_cpu;
  78     struct pci_status pci0_status;
  79     uint32_t pci0_hotplug_enable;
  80 } PIIX4PMState;
  81
  82 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s);
  83
  84 #define ACPI_ENABLE 0xf1
  85 #define ACPI_DISABLE 0xf0
  86
  87 static void pm_update_sci(PIIX4PMState *s)
  88 {
  89     int sci_level, pmsts;
  90
  91     pmsts = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
  92     sci_level = (((pmsts & s->pm1a.en) &
  93                   (ACPI_BITMASK_RT_CLOCK_ENABLE |
  94                    ACPI_BITMASK_POWER_BUTTON_ENABLE |
  95                    ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
  96                    ACPI_BITMASK_TIMER_ENABLE)) != 0) ||
  97         (((s->gpe.sts[0] & s->gpe.en[0]) & PIIX4_PCI_HOTPLUG_STATUS) != 0);
  98
  99     qemu_set_irq(s->irq, sci_level);
 100     /* schedule a timer interruption if needed */
 101     acpi_pm_tmr_update(&s->tmr, (s->pm1a.en & ACPI_BITMASK_TIMER_ENABLE) &&
 102                        !(pmsts & ACPI_BITMASK_TIMER_STATUS));
 103 }
 104
 105 static void pm_tmr_timer(ACPIPMTimer *tmr)
 106 {
 107     PIIX4PMState *s = container_of(tmr, PIIX4PMState, tmr);
 108     pm_update_sci(s);
 109 }
 110
 111 static void pm_ioport_write(IORange *ioport, uint64_t addr, unsigned width,
 112                             uint64_t val)
 113 {
 114     PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
 115
 116     if (width != 2) {
 117         PIIX4_DPRINTF("PM write port=0x%04x width=%d val=0x%08x\n",
 118                       (unsigned)addr, width, (unsigned)val);
 119     }
 120
 121     switch(addr) {
 122     case 0x00:
 123         acpi_pm1_evt_write_sts(&s->pm1a, &s->tmr, val);
 124         pm_update_sci(s);
 125         break;
 126     case 0x02:
 127         s->pm1a.en = val;
 128         pm_update_sci(s);
 129         break;
 130     case 0x04:
 131         acpi_pm1_cnt_write(&s->pm1a, &s->pm1_cnt, val);
 132         break;
 133     default:
 134         break;
 135     }
 136     PIIX4_DPRINTF("PM writew port=0x%04x val=0x%04x\n", (unsigned int)addr,
 137                   (unsigned int)val);
 138 }
 139
 140 static void pm_ioport_read(IORange *ioport, uint64_t addr, unsigned width,
 141                             uint64_t *data)
 142 {
 143     PIIX4PMState *s = container_of(ioport, PIIX4PMState, ioport);
 144     uint32_t val;
 145
 146     switch(addr) {
 147     case 0x00:
 148         val = acpi_pm1_evt_get_sts(&s->pm1a, s->tmr.overflow_time);
 149         break;
 150     case 0x02:
 151         val = s->pm1a.en;
 152         break;
 153     case 0x04:
 154         val = s->pm1_cnt.cnt;
 155         break;
 156     case 0x08:
 157         val = acpi_pm_tmr_get(&s->tmr);
 158         break;
 159     default:
 160         val = 0;
 161         break;
 162     }
 163     PIIX4_DPRINTF("PM readw port=0x%04x val=0x%04x\n", (unsigned int)addr, val);
 164     *data = val;
 165 }
 166
 167 static const IORangeOps pm_iorange_ops = {
 168     .read = pm_ioport_read,
 169     .write = pm_ioport_write,
 170 };
 171
 172 static void apm_ctrl_changed(uint32_t val, void *arg)
 173 {
 174     PIIX4PMState *s = arg;
 175
 176     /* ACPI specs 3.0, 4.7.2.5 */
 177     acpi_pm1_cnt_update(&s->pm1_cnt, val == ACPI_ENABLE, val == ACPI_DISABLE);
 178
 179     if (s->dev.config[0x5b] & (1 << 1)) {
 180         if (s->smi_irq) {
 181             qemu_irq_raise(s->smi_irq);
 182         }
 183     }
 184 }
 185
 186 static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 187 {
 188     PIIX4_DPRINTF("ACPI: DBG: 0x%08x\n", val);
 189 }
 190
 191 static void pm_io_space_update(PIIX4PMState *s)
 192 {
 193     uint32_t pm_io_base;
 194
 195     if (s->dev.config[0x80] & 1) {
 196         pm_io_base = le32_to_cpu(*(uint32_t *)(s->dev.config + 0x40));
 197         pm_io_base &= 0xffc0;
 198
 199         /* XXX: need to improve memory and ioport allocation */
 200         PIIX4_DPRINTF("PM: mapping to 0x%x\n", pm_io_base);
 201         iorange_init(&s->ioport, &pm_iorange_ops, pm_io_base, 64);
 202         ioport_register(&s->ioport);
 203     }
 204 }
 205
 206 static void pm_write_config(PCIDevice *d,
 207                             uint32_t address, uint32_t val, int len)
 208 {
 209     pci_default_write_config(d, address, val, len);
 210     if (range_covers_byte(address, len, 0x80))
 211         pm_io_space_update((PIIX4PMState *)d);
 212 }
 213
 214 static int vmstate_acpi_post_load(void *opaque, int version_id)
 215 {
 216     PIIX4PMState *s = opaque;
 217
 218     pm_io_space_update(s);
 219     return 0;
 220 }
 221
 222 #define VMSTATE_GPE_ARRAY(_field, _state)                            \
 223  {                                                                   \
 224      .name       = (stringify(_field)),                              \
 225      .version_id = 0,                                                \
 226      .info       = &vmstate_info_uint16,                             \
 227      .size       = sizeof(uint16_t),                                 \
 228      .flags      = VMS_SINGLE | VMS_POINTER,                         \
 229      .offset     = vmstate_offset_pointer(_state, _field, uint8_t),  \
 230  }
 231
 232 static const VMStateDescription vmstate_gpe = {
 233     .name = "gpe",
 234     .version_id = 1,
 235     .minimum_version_id = 1,
 236     .minimum_version_id_old = 1,
 237     .fields      = (VMStateField []) {
 238         VMSTATE_GPE_ARRAY(sts, ACPIGPE),
 239         VMSTATE_GPE_ARRAY(en, ACPIGPE),
 240         VMSTATE_END_OF_LIST()
 241     }
 242 };
 243
 244 static const VMStateDescription vmstate_pci_status = {
 245     .name = "pci_status",
 246     .version_id = 1,
 247     .minimum_version_id = 1,
 248     .minimum_version_id_old = 1,
 249     .fields      = (VMStateField []) {
 250         VMSTATE_UINT32(up, struct pci_status),
 251         VMSTATE_UINT32(down, struct pci_status),
 252         VMSTATE_END_OF_LIST()
 253     }
 254 };
 255
 256 static const VMStateDescription vmstate_acpi = {
 257     .name = "piix4_pm",
 258     .version_id = 2,
 259     .minimum_version_id = 1,
 260     .minimum_version_id_old = 1,
 261     .post_load = vmstate_acpi_post_load,
 262     .fields      = (VMStateField []) {
 263         VMSTATE_PCI_DEVICE(dev, PIIX4PMState),
 264         VMSTATE_UINT16(pm1a.sts, PIIX4PMState),
 265         VMSTATE_UINT16(pm1a.en, PIIX4PMState),
 266         VMSTATE_UINT16(pm1_cnt.cnt, PIIX4PMState),
 267         VMSTATE_STRUCT(apm, PIIX4PMState, 0, vmstate_apm, APMState),
 268         VMSTATE_TIMER(tmr.timer, PIIX4PMState),
 269         VMSTATE_INT64(tmr.overflow_time, PIIX4PMState),
 270         VMSTATE_STRUCT(gpe, PIIX4PMState, 2, vmstate_gpe, ACPIGPE),
 271         VMSTATE_STRUCT(pci0_status, PIIX4PMState, 2, vmstate_pci_status,
 272                        struct pci_status),
 273         VMSTATE_END_OF_LIST()
 274     }
 275 };
 276
 277 static void piix4_update_hotplug(PIIX4PMState *s)
 278 {
 279     PCIDevice *dev = &s->dev;
 280     BusState *bus = qdev_get_parent_bus(&dev->qdev);
 281     DeviceState *qdev, *next;
 282
 283     s->pci0_hotplug_enable = ~0;
 284
 285     QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
 286         PCIDeviceInfo *info = container_of(qdev->info, PCIDeviceInfo, qdev);
 287         PCIDevice *pdev = DO_UPCAST(PCIDevice, qdev, qdev);
 288         int slot = PCI_SLOT(pdev->devfn);
 289
 290         if (info->no_hotplug) {
 291             s->pci0_hotplug_enable &= ~(1 << slot);
 292         }
 293     }
 294 }
 295
 296 static void piix4_reset(void *opaque)
 297 {
 298     PIIX4PMState *s = opaque;
 299     uint8_t *pci_conf = s->dev.config;
 300
 301     pci_conf[0x58] = 0;
 302     pci_conf[0x59] = 0;
 303     pci_conf[0x5a] = 0;
 304     pci_conf[0x5b] = 0;
 305
 306     if (s->kvm_enabled) {
 307         /* Mark SMM as already inited (until KVM supports SMM). */
 308         pci_conf[0x5B] = 0x02;
 309     }
 310     piix4_update_hotplug(s);
 311 }
 312
 313 static void piix4_powerdown(void *opaque, int irq, int power_failing)
 314 {
 315     PIIX4PMState *s = opaque;
 316     ACPIPM1EVT *pm1a = s? &s->pm1a: NULL;
 317     ACPIPMTimer *tmr = s? &s->tmr: NULL;
 318
 319     acpi_pm1_evt_power_down(pm1a, tmr);
 320 }
 321
 322 static void piix4_pm_machine_ready(Notifier *n, void *opaque)
 323 {
 324     PIIX4PMState *s = container_of(n, PIIX4PMState, machine_ready);
 325     uint8_t *pci_conf;
 326
 327     pci_conf = s->dev.config;
 328     pci_conf[0x5f] = (isa_is_ioport_assigned(0x378) ? 0x80 : 0) | 0x10;
 329     pci_conf[0x63] = 0x60;
 330     pci_conf[0x67] = (isa_is_ioport_assigned(0x3f8) ? 0x08 : 0) |
 331         (isa_is_ioport_assigned(0x2f8) ? 0x90 : 0);
 332
 333 }
 334
 335 static PIIX4PMState *global_piix4_pm_state; /* cpu hotadd */
 336
 337 static int piix4_pm_initfn(PCIDevice *dev)
 338 {
 339     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev, dev);
 340     uint8_t *pci_conf;
 341
 342     /* for cpu hotadd */
 343     global_piix4_pm_state = s;
 344
 345     pci_conf = s->dev.config;
 346     pci_conf[0x06] = 0x80;
 347     pci_conf[0x07] = 0x02;
 348     pci_conf[0x09] = 0x00;
 349     pci_conf[0x3d] = 0x01; // interrupt pin 1
 350
 351     pci_conf[0x40] = 0x01; /* PM io base read only bit */
 352
 353 #if defined(TARGET_IA64)
 354     pci_conf[0x40] = 0x41; /* PM io base read only bit */
 355     pci_conf[0x41] = 0x1f;
 356     pm_write_config(s, 0x80, 0x01, 1); /*Set default pm_io_base 0x1f40*/
 357     s->pmcntrl = SCI_EN;
 358 #endif
 359
 360     /* APM */
 361     apm_init(&s->apm, apm_ctrl_changed, s);
 362
 363     register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s);
 364
 365     if (s->kvm_enabled) {
 366         /* Mark SMM as already inited to prevent SMM from running.  KVM does not
 367          * support SMM mode. */
 368         pci_conf[0x5B] = 0x02;
 369     }
 370
 371     /* XXX: which specification is used ? The i82731AB has different
 372        mappings */
 373     pci_conf[0x90] = s->smb_io_base | 1;
 374     pci_conf[0x91] = s->smb_io_base >> 8;
 375     pci_conf[0xd2] = 0x09;
 376     register_ioport_write(s->smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
 377     register_ioport_read(s->smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
 378
 379     acpi_pm_tmr_init(&s->tmr, pm_tmr_timer);
 380     acpi_gpe_init(&s->gpe, GPE_LEN);
 381
 382     qemu_system_powerdown = *qemu_allocate_irqs(piix4_powerdown, s, 1);
 383
 384     pm_smbus_init(&s->dev.qdev, &s->smb);
 385     s->machine_ready.notify = piix4_pm_machine_ready;
 386     qemu_add_machine_init_done_notifier(&s->machine_ready);
 387     qemu_register_reset(piix4_reset, s);
 388     piix4_acpi_system_hot_add_init(dev->bus, s);
 389
 390     return 0;
 391 }
 392
 393 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 394                        qemu_irq sci_irq, qemu_irq cmos_s3, qemu_irq smi_irq,
 395                        int kvm_enabled)
 396 {
 397     PCIDevice *dev;
 398     PIIX4PMState *s;
 399
 400     dev = pci_create(bus, devfn, "PIIX4_PM");
 401     qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
 402
 403     s = DO_UPCAST(PIIX4PMState, dev, dev);
 404     s->irq = sci_irq;
 405     acpi_pm1_cnt_init(&s->pm1_cnt, cmos_s3);
 406     s->smi_irq = smi_irq;
 407     s->kvm_enabled = kvm_enabled;
 408
 409     qdev_init_nofail(&dev->qdev);
 410
 411     return s->smb.smbus;
 412 }
 413
 414 static PCIDeviceInfo piix4_pm_info = {
 415     .qdev.name          = "PIIX4_PM",
 416     .qdev.desc          = "PM",
 417     .qdev.size          = sizeof(PIIX4PMState),
 418     .qdev.vmsd          = &vmstate_acpi,
 419     .qdev.no_user       = 1,
 420     .no_hotplug         = 1,
 421     .init               = piix4_pm_initfn,
 422     .config_write       = pm_write_config,
 423     .vendor_id          = PCI_VENDOR_ID_INTEL,
 424     .device_id          = PCI_DEVICE_ID_INTEL_82371AB_3,
 425     .revision           = 0x03,
 426     .class_id           = PCI_CLASS_BRIDGE_OTHER,
 427     .qdev.props         = (Property[]) {
 428         DEFINE_PROP_UINT32("smb_io_base", PIIX4PMState, smb_io_base, 0),
 429         DEFINE_PROP_END_OF_LIST(),
 430     }
 431 };
 432
 433 static void piix4_pm_register(void)
 434 {
 435     pci_qdev_register(&piix4_pm_info);
 436 }
 437
 438 device_init(piix4_pm_register);
 439
 440 static uint32_t gpe_readb(void *opaque, uint32_t addr)
 441 {
 442     PIIX4PMState *s = opaque;
 443     uint32_t val = 0;
 444     struct gpe_regs *g = &s->gpe_cpu;
 445
 446     switch (addr) {
 447         case PROC_BASE ... PROC_BASE+31:
 448             val = g->cpus_sts[addr - PROC_BASE];
 449             break;
 450         default:
 451             val = acpi_gpe_ioport_readb(&s->gpe, addr);
 452     }
 453
 454     PIIX4_DPRINTF("gpe read %x == %x\n", addr, val);
 455     return val;
 456 }
 457
 458 static void gpe_writeb(void *opaque, uint32_t addr, uint32_t val)
 459 {
 460     PIIX4PMState *s = opaque;
 461
 462     acpi_gpe_ioport_writeb(&s->gpe, addr, val);
 463     pm_update_sci(s);
 464
 465     PIIX4_DPRINTF("gpe write %x <== %d\n", addr, val);
 466 }
 467
 468 static uint32_t pcihotplug_read(void *opaque, uint32_t addr)
 469 {
 470     uint32_t val = 0;
 471     struct pci_status *g = opaque;
 472     switch (addr) {
 473         case PCI_BASE:
 474             val = g->up;
 475             break;
 476         case PCI_BASE + 4:
 477             val = g->down;
 478             break;
 479         default:
 480             break;
 481     }
 482
 483     PIIX4_DPRINTF("pcihotplug read %x == %x\n", addr, val);
 484     return val;
 485 }
 486
 487 static void pcihotplug_write(void *opaque, uint32_t addr, uint32_t val)
 488 {
 489     struct pci_status *g = opaque;
 490     switch (addr) {
 491         case PCI_BASE:
 492             g->up = val;
 493             break;
 494         case PCI_BASE + 4:
 495             g->down = val;
 496             break;
 497    }
 498
 499     PIIX4_DPRINTF("pcihotplug write %x <== %d\n", addr, val);
 500 }
 501
 502 static uint32_t pciej_read(void *opaque, uint32_t addr)
 503 {
 504     PIIX4_DPRINTF("pciej read %x\n", addr);
 505     return 0;
 506 }
 507
 508 static void pciej_write(void *opaque, uint32_t addr, uint32_t val)
 509 {
 510     BusState *bus = opaque;
 511     DeviceState *qdev, *next;
 512     PCIDevice *dev;
 513     PCIDeviceInfo *info;
 514     int slot = ffs(val) - 1;
 515
 516     QLIST_FOREACH_SAFE(qdev, &bus->children, sibling, next) {
 517         dev = DO_UPCAST(PCIDevice, qdev, qdev);
 518         info = container_of(qdev->info, PCIDeviceInfo, qdev);
 519         if (PCI_SLOT(dev->devfn) == slot && !info->no_hotplug) {
 520             qdev_free(qdev);
 521         }
 522     }
 523
 524
 525     PIIX4_DPRINTF("pciej write %x <== %d\n", addr, val);
 526 }
 527
 528 static uint32_t pcirmv_read(void *opaque, uint32_t addr)
 529 {
 530     PIIX4PMState *s = opaque;
 531
 532     return s->pci0_hotplug_enable;
 533 }
 534
 535 static void pcirmv_write(void *opaque, uint32_t addr, uint32_t val)
 536 {
 537     return;
 538 }
 539
 540 extern const char *global_cpu_model;
 541
 542 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
 543                                 PCIHotplugState state);
 544
 545 static void piix4_acpi_system_hot_add_init(PCIBus *bus, PIIX4PMState *s)
 546 {
 547     struct pci_status *pci0_status = &s->pci0_status;
 548     int i = 0, cpus = smp_cpus;
 549
 550     while (cpus > 0) {
 551         s->gpe_cpu.cpus_sts[i++] = (cpus < 8) ? (1 << cpus) - 1 : 0xff;
 552         cpus -= 8;
 553     }
 554
 555     register_ioport_write(GPE_BASE, GPE_LEN, 1, gpe_writeb, s);
 556     register_ioport_read(GPE_BASE, GPE_LEN, 1,  gpe_readb, s);
 557     acpi_gpe_blk(&s->gpe, GPE_BASE);
 558
 559     register_ioport_write(PROC_BASE, 32, 1, gpe_writeb, s);
 560     register_ioport_read(PROC_BASE, 32, 1,  gpe_readb, s);
 561
 562     register_ioport_write(PCI_BASE, 8, 4, pcihotplug_write, pci0_status);
 563     register_ioport_read(PCI_BASE, 8, 4,  pcihotplug_read, pci0_status);
 564
 565     register_ioport_write(PCI_EJ_BASE, 4, 4, pciej_write, bus);
 566     register_ioport_read(PCI_EJ_BASE, 4, 4,  pciej_read, bus);
 567
 568     register_ioport_write(PCI_RMV_BASE, 4, 4, pcirmv_write, s);
 569     register_ioport_read(PCI_RMV_BASE, 4, 4,  pcirmv_read, s);
 570
 571     pci_bus_hotplug(bus, piix4_device_hotplug, &s->dev.qdev);
 572 }
 573
 574 #if defined(TARGET_I386)
 575 static void enable_processor(PIIX4PMState *s, int cpu)
 576 {
 577     struct gpe_regs *g = &s->gpe_cpu;
 578     ACPIGPE *gpe = &s->gpe;
 579
 580     *gpe->sts = *gpe->sts | PIIX4_CPU_HOTPLUG_STATUS;
 581     g->cpus_sts[cpu/8] |= (1 << (cpu%8));
 582 }
 583
 584 static void disable_processor(PIIX4PMState *s, int cpu)
 585 {
 586     struct gpe_regs *g = &s->gpe_cpu;
 587     ACPIGPE *gpe = &s->gpe;
 588
 589     *gpe->sts = *gpe->sts | PIIX4_CPU_HOTPLUG_STATUS;
 590     g->cpus_sts[cpu/8] &= ~(1 << (cpu%8));
 591 }
 592
 593 void qemu_system_cpu_hot_add(int cpu, int state)
 594 {
 595     CPUState *env;
 596     PIIX4PMState *s = global_piix4_pm_state;
 597
 598     if (state && !qemu_get_cpu(cpu)) {
 599         env = pc_new_cpu(global_cpu_model);
 600         if (!env) {
 601             fprintf(stderr, "cpu %d creation failed\n", cpu);
 602             return;
 603         }
 604         env->cpuid_apic_id = cpu;
 605     }
 606
 607     if (state)
 608         enable_processor(s, cpu);
 609     else
 610         disable_processor(s, cpu);
 611
 612     pm_update_sci(s);
 613 }
 614 #endif
 615
 616 static void enable_device(PIIX4PMState *s, int slot)
 617 {
 618     s->gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
 619     s->pci0_status.up |= (1 << slot);
 620 }
 621
 622 static void disable_device(PIIX4PMState *s, int slot)
 623 {
 624     s->gpe.sts[0] |= PIIX4_PCI_HOTPLUG_STATUS;
 625     s->pci0_status.down |= (1 << slot);
 626 }
 627
 628 static int piix4_device_hotplug(DeviceState *qdev, PCIDevice *dev,
 629                                 PCIHotplugState state)
 630 {
 631     int slot = PCI_SLOT(dev->devfn);
 632     PIIX4PMState *s = DO_UPCAST(PIIX4PMState, dev,
 633                                 DO_UPCAST(PCIDevice, qdev, qdev));
 634
 635     /* Don't send event when device is enabled during qemu machine creation:
 636      * it is present on boot, no hotplug event is necessary. We do send an
 637      * event when the device is disabled later. */
 638     if (state == PCI_COLDPLUG_ENABLED) {
 639         return 0;
 640     }
 641
 642     s->pci0_status.up = 0;
 643     s->pci0_status.down = 0;
 644     if (state == PCI_HOTPLUG_ENABLED) {
 645         enable_device(s, slot);
 646     } else {
 647         disable_device(s, slot);
 648     }
 649
 650     pm_update_sci(s);
 651
 652     return 0;
 653 }