target-ppc/mmu-hash64.c

   1 /*
   2  *  PowerPC MMU, TLB, SLB and BAT emulation helpers for QEMU.
   3  *
   4  *  Copyright (c) 2003-2007 Jocelyn Mayer
   5  *  Copyright (c) 2013 David Gibson, IBM Corporation
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  19  */
  20 #include "cpu.h"
  21 #include "helper.h"
  22 #include "sysemu/kvm.h"
  23 #include "kvm_ppc.h"
  24 #include "mmu-hash64.h"
  25
  26 //#define DEBUG_MMU
  27 //#define DEBUG_SLB
  28
  29 #ifdef DEBUG_MMU
  30 #  define LOG_MMU(...) qemu_log(__VA_ARGS__)
  31 #  define LOG_MMU_STATE(env) log_cpu_state((env), 0)
  32 #else
  33 #  define LOG_MMU(...) do { } while (0)
  34 #  define LOG_MMU_STATE(...) do { } while (0)
  35 #endif
  36
  37 #ifdef DEBUG_SLB
  38 #  define LOG_SLB(...) qemu_log(__VA_ARGS__)
  39 #else
  40 #  define LOG_SLB(...) do { } while (0)
  41 #endif
  42
  43 struct mmu_ctx_hash64 {
  44     hwaddr raddr;      /* Real address              */
  45     hwaddr eaddr;      /* Effective address         */
  46     int prot;                      /* Protection bits           */
  47     hwaddr hash[2];    /* Pagetable hash values     */
  48     target_ulong ptem;             /* Virtual segment ID | API  */
  49     int key;                       /* Access key                */
  50     int nx;                        /* Non-execute area          */
  51 };
  52
  53 /*
  54  * SLB handling
  55  */
  56
  57 static ppc_slb_t *slb_lookup(CPUPPCState *env, target_ulong eaddr)
  58 {
  59     uint64_t esid_256M, esid_1T;
  60     int n;
  61
  62     LOG_SLB("%s: eaddr " TARGET_FMT_lx "\n", __func__, eaddr);
  63
  64     esid_256M = (eaddr & SEGMENT_MASK_256M) | SLB_ESID_V;
  65     esid_1T = (eaddr & SEGMENT_MASK_1T) | SLB_ESID_V;
  66
  67     for (n = 0; n < env->slb_nr; n++) {
  68         ppc_slb_t *slb = &env->slb[n];
  69
  70         LOG_SLB("%s: slot %d %016" PRIx64 " %016"
  71                     PRIx64 "\n", __func__, n, slb->esid, slb->vsid);
  72         /* We check for 1T matches on all MMUs here - if the MMU
  73          * doesn't have 1T segment support, we will have prevented 1T
  74          * entries from being inserted in the slbmte code. */
  75         if (((slb->esid == esid_256M) &&
  76              ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_256M))
  77             || ((slb->esid == esid_1T) &&
  78                 ((slb->vsid & SLB_VSID_B) == SLB_VSID_B_1T))) {
  79             return slb;
  80         }
  81     }
  82
  83     return NULL;
  84 }
  85
  86 void dump_slb(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env)
  87 {
  88     int i;
  89     uint64_t slbe, slbv;
  90
  91     cpu_synchronize_state(env);
  92
  93     cpu_fprintf(f, "SLB\tESID\t\t\tVSID\n");
  94     for (i = 0; i < env->slb_nr; i++) {
  95         slbe = env->slb[i].esid;
  96         slbv = env->slb[i].vsid;
  97         if (slbe == 0 && slbv == 0) {
  98             continue;
  99         }
 100         cpu_fprintf(f, "%d\t0x%016" PRIx64 "\t0x%016" PRIx64 "\n",
 101                     i, slbe, slbv);
 102     }
 103 }
 104
 105 void helper_slbia(CPUPPCState *env)
 106 {
 107     int n, do_invalidate;
 108
 109     do_invalidate = 0;
 110     /* XXX: Warning: slbia never invalidates the first segment */
 111     for (n = 1; n < env->slb_nr; n++) {
 112         ppc_slb_t *slb = &env->slb[n];
 113
 114         if (slb->esid & SLB_ESID_V) {
 115             slb->esid &= ~SLB_ESID_V;
 116             /* XXX: given the fact that segment size is 256 MB or 1TB,
 117              *      and we still don't have a tlb_flush_mask(env, n, mask)
 118              *      in QEMU, we just invalidate all TLBs
 119              */
 120             do_invalidate = 1;
 121         }
 122     }
 123     if (do_invalidate) {
 124         tlb_flush(env, 1);
 125     }
 126 }
 127
 128 void helper_slbie(CPUPPCState *env, target_ulong addr)
 129 {
 130     ppc_slb_t *slb;
 131
 132     slb = slb_lookup(env, addr);
 133     if (!slb) {
 134         return;
 135     }
 136
 137     if (slb->esid & SLB_ESID_V) {
 138         slb->esid &= ~SLB_ESID_V;
 139
 140         /* XXX: given the fact that segment size is 256 MB or 1TB,
 141          *      and we still don't have a tlb_flush_mask(env, n, mask)
 142          *      in QEMU, we just invalidate all TLBs
 143          */
 144         tlb_flush(env, 1);
 145     }
 146 }
 147
 148 int ppc_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
 149 {
 150     int slot = rb & 0xfff;
 151     ppc_slb_t *slb = &env->slb[slot];
 152
 153     if (rb & (0x1000 - env->slb_nr)) {
 154         return -1; /* Reserved bits set or slot too high */
 155     }
 156     if (rs & (SLB_VSID_B & ~SLB_VSID_B_1T)) {
 157         return -1; /* Bad segment size */
 158     }
 159     if ((rs & SLB_VSID_B) && !(env->mmu_model & POWERPC_MMU_1TSEG)) {
 160         return -1; /* 1T segment on MMU that doesn't support it */
 161     }
 162
 163     /* Mask out the slot number as we store the entry */
 164     slb->esid = rb & (SLB_ESID_ESID | SLB_ESID_V);
 165     slb->vsid = rs;
 166
 167     LOG_SLB("%s: %d " TARGET_FMT_lx " - " TARGET_FMT_lx " => %016" PRIx64
 168             " %016" PRIx64 "\n", __func__, slot, rb, rs,
 169             slb->esid, slb->vsid);
 170
 171     return 0;
 172 }
 173
 174 static int ppc_load_slb_esid(CPUPPCState *env, target_ulong rb,
 175                              target_ulong *rt)
 176 {
 177     int slot = rb & 0xfff;
 178     ppc_slb_t *slb = &env->slb[slot];
 179
 180     if (slot >= env->slb_nr) {
 181         return -1;
 182     }
 183
 184     *rt = slb->esid;
 185     return 0;
 186 }
 187
 188 static int ppc_load_slb_vsid(CPUPPCState *env, target_ulong rb,
 189                              target_ulong *rt)
 190 {
 191     int slot = rb & 0xfff;
 192     ppc_slb_t *slb = &env->slb[slot];
 193
 194     if (slot >= env->slb_nr) {
 195         return -1;
 196     }
 197
 198     *rt = slb->vsid;
 199     return 0;
 200 }
 201
 202 void helper_store_slb(CPUPPCState *env, target_ulong rb, target_ulong rs)
 203 {
 204     if (ppc_store_slb(env, rb, rs) < 0) {
 205         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 206                                    POWERPC_EXCP_INVAL);
 207     }
 208 }
 209
 210 target_ulong helper_load_slb_esid(CPUPPCState *env, target_ulong rb)
 211 {
 212     target_ulong rt = 0;
 213
 214     if (ppc_load_slb_esid(env, rb, &rt) < 0) {
 215         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 216                                    POWERPC_EXCP_INVAL);
 217     }
 218     return rt;
 219 }
 220
 221 target_ulong helper_load_slb_vsid(CPUPPCState *env, target_ulong rb)
 222 {
 223     target_ulong rt = 0;
 224
 225     if (ppc_load_slb_vsid(env, rb, &rt) < 0) {
 226         helper_raise_exception_err(env, POWERPC_EXCP_PROGRAM,
 227                                    POWERPC_EXCP_INVAL);
 228     }
 229     return rt;
 230 }
 231
 232 /*
 233  * 64-bit hash table MMU handling
 234  */
 235
 236 #define PTE64_CHECK_MASK (TARGET_PAGE_MASK | 0x7F)
 237
 238 static int ppc_hash64_pp_check(int key, int pp, int nx)
 239 {
 240     int access;
 241
 242     /* Compute access rights */
 243     /* When pp is 4, 5 or 7, the result is undefined. Set it to noaccess */
 244     access = 0;
 245     if (key == 0) {
 246         switch (pp) {
 247         case 0x0:
 248         case 0x1:
 249         case 0x2:
 250             access |= PAGE_WRITE;
 251             /* No break here */
 252         case 0x3:
 253         case 0x6:
 254             access |= PAGE_READ;
 255             break;
 256         }
 257     } else {
 258         switch (pp) {
 259         case 0x0:
 260         case 0x6:
 261             access = 0;
 262             break;
 263         case 0x1:
 264         case 0x3:
 265             access = PAGE_READ;
 266             break;
 267         case 0x2:
 268             access = PAGE_READ | PAGE_WRITE;
 269             break;
 270         }
 271     }
 272     if (nx == 0) {
 273         access |= PAGE_EXEC;
 274     }
 275
 276     return access;
 277 }
 278
 279 static int ppc_hash64_check_prot(int prot, int rw, int access_type)
 280 {
 281     int ret;
 282
 283     if (access_type == ACCESS_CODE) {
 284         if (prot & PAGE_EXEC) {
 285             ret = 0;
 286         } else {
 287             ret = -2;
 288         }
 289     } else if (rw) {
 290         if (prot & PAGE_WRITE) {
 291             ret = 0;
 292         } else {
 293             ret = -2;
 294         }
 295     } else {
 296         if (prot & PAGE_READ) {
 297             ret = 0;
 298         } else {
 299             ret = -2;
 300         }
 301     }
 302
 303     return ret;
 304 }
 305
 306 static int pte64_check(struct mmu_ctx_hash64 *ctx, target_ulong pte0,
 307                        target_ulong pte1, int h, int rw, int type)
 308 {
 309     target_ulong mmask;
 310     int access, ret, pp;
 311
 312     ret = -1;
 313     /* Check validity and table match */
 314     if ((pte0 & HPTE64_V_VALID) && (h == !!(pte0 & HPTE64_V_SECONDARY))) {
 315         /* Check vsid & api */
 316         mmask = PTE64_CHECK_MASK;
 317         pp = (pte1 & HPTE64_R_PP) | ((pte1 & HPTE64_R_PP0) >> 61);
 318         /* No execute if either noexec or guarded bits set */
 319         ctx->nx = (pte1 & HPTE64_R_N) || (pte1 & HPTE64_R_G);
 320         if (HPTE64_V_COMPARE(pte0, ctx->ptem)) {
 321             if (ctx->raddr != (hwaddr)-1ULL) {
 322                 /* all matches should have equal RPN, WIMG & PP */
 323                 if ((ctx->raddr & mmask) != (pte1 & mmask)) {
 324                     qemu_log("Bad RPN/WIMG/PP\n");
 325                     return -3;
 326                 }
 327             }
 328             /* Compute access rights */
 329             access = ppc_hash64_pp_check(ctx->key, pp, ctx->nx);
 330             /* Keep the matching PTE informations */
 331             ctx->raddr = pte1;
 332             ctx->prot = access;
 333             ret = ppc_hash64_check_prot(ctx->prot, rw, type);
 334             if (ret == 0) {
 335                 /* Access granted */
 336                 LOG_MMU("PTE access granted !\n");
 337             } else {
 338                 /* Access right violation */
 339                 LOG_MMU("PTE access rejected\n");
 340             }
 341         }
 342     }
 343
 344     return ret;
 345 }
 346
 347 static int ppc_hash64_pte_update_flags(struct mmu_ctx_hash64 *ctx,
 348                                        target_ulong *pte1p,
 349                                        int ret, int rw)
 350 {
 351     int store = 0;
 352
 353     /* Update page flags */
 354     if (!(*pte1p & HPTE64_R_R)) {
 355         /* Update accessed flag */
 356         *pte1p |= HPTE64_R_R;
 357         store = 1;
 358     }
 359     if (!(*pte1p & HPTE64_R_C)) {
 360         if (rw == 1 && ret == 0) {
 361             /* Update changed flag */
 362             *pte1p |= HPTE64_R_C;
 363             store = 1;
 364         } else {
 365             /* Force page fault for first write access */
 366             ctx->prot &= ~PAGE_WRITE;
 367         }
 368     }
 369
 370     return store;
 371 }
 372
 373 /* PTE table lookup */
 374 static int find_pte64(CPUPPCState *env, struct mmu_ctx_hash64 *ctx, int h,
 375                       int rw, int type, int target_page_bits)
 376 {
 377     hwaddr pteg_off;
 378     target_ulong pte0, pte1;
 379     int i, good = -1;
 380     int ret, r;
 381
 382     ret = -1; /* No entry found */
 383     pteg_off = (ctx->hash[h] * HASH_PTEG_SIZE_64) & env->htab_mask;
 384     for (i = 0; i < HPTES_PER_GROUP; i++) {
 385         if (env->external_htab) {
 386             pte0 = ldq_p(env->external_htab + pteg_off + (i * 16));
 387             pte1 = ldq_p(env->external_htab + pteg_off + (i * 16) + 8);
 388         } else {
 389             pte0 = ldq_phys(env->htab_base + pteg_off + (i * 16));
 390             pte1 = ldq_phys(env->htab_base + pteg_off + (i * 16) + 8);
 391         }
 392
 393         r = pte64_check(ctx, pte0, pte1, h, rw, type);
 394         LOG_MMU("Load pte from %016" HWADDR_PRIx " => " TARGET_FMT_lx " "
 395                 TARGET_FMT_lx " %d %d %d " TARGET_FMT_lx "\n",
 396                 pteg_off + (i * 16), pte0, pte1, (int)(pte0 & 1), h,
 397                 (int)((pte0 >> 1) & 1), ctx->ptem);
 398         switch (r) {
 399         case -3:
 400             /* PTE inconsistency */
 401             return -1;
 402         case -2:
 403             /* Access violation */
 404             ret = -2;
 405             good = i;
 406             break;
 407         case -1:
 408         default:
 409             /* No PTE match */
 410             break;
 411         case 0:
 412             /* access granted */
 413             /* XXX: we should go on looping to check all PTEs consistency
 414              *      but if we can speed-up the whole thing as the
 415              *      result would be undefined if PTEs are not consistent.
 416              */
 417             ret = 0;
 418             good = i;
 419             goto done;
 420         }
 421     }
 422     if (good != -1) {
 423     done:
 424         LOG_MMU("found PTE at addr %08" HWADDR_PRIx " prot=%01x ret=%d\n",
 425                 ctx->raddr, ctx->prot, ret);
 426         /* Update page flags */
 427         pte1 = ctx->raddr;
 428         if (ppc_hash64_pte_update_flags(ctx, &pte1, ret, rw) == 1) {
 429             if (env->external_htab) {
 430                 stq_p(env->external_htab + pteg_off + (good * 16) + 8,
 431                       pte1);
 432             } else {
 433                 stq_phys_notdirty(env->htab_base + pteg_off +
 434                                   (good * 16) + 8, pte1);
 435             }
 436         }
 437     }
 438
 439     /* We have a TLB that saves 4K pages, so let's
 440      * split a huge page to 4k chunks */
 441     if (target_page_bits != TARGET_PAGE_BITS) {
 442         ctx->raddr |= (ctx->eaddr & ((1 << target_page_bits) - 1))
 443                       & TARGET_PAGE_MASK;
 444     }
 445     return ret;
 446 }
 447
 448 static int get_segment64(CPUPPCState *env, struct mmu_ctx_hash64 *ctx,
 449                          target_ulong eaddr, int rw, int type)
 450 {
 451     hwaddr hash;
 452     target_ulong vsid;
 453     int pr, target_page_bits;
 454     int ret, ret2;
 455
 456     pr = msr_pr;
 457     ctx->eaddr = eaddr;
 458     ppc_slb_t *slb;
 459     target_ulong pageaddr;
 460     int segment_bits;
 461
 462     LOG_MMU("Check SLBs\n");
 463     slb = slb_lookup(env, eaddr);
 464     if (!slb) {
 465         return -5;
 466     }
 467
 468     if (slb->vsid & SLB_VSID_B) {
 469         vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT_1T;
 470         segment_bits = 40;
 471     } else {
 472         vsid = (slb->vsid & SLB_VSID_VSID) >> SLB_VSID_SHIFT;
 473         segment_bits = 28;
 474     }
 475
 476     target_page_bits = (slb->vsid & SLB_VSID_L)
 477         ? TARGET_PAGE_BITS_16M : TARGET_PAGE_BITS;
 478     ctx->key = !!(pr ? (slb->vsid & SLB_VSID_KP)
 479                   : (slb->vsid & SLB_VSID_KS));
 480     ctx->nx = !!(slb->vsid & SLB_VSID_N);
 481
 482     pageaddr = eaddr & ((1ULL << segment_bits)
 483                             - (1ULL << target_page_bits));
 484     if (slb->vsid & SLB_VSID_B) {
 485         hash = vsid ^ (vsid << 25) ^ (pageaddr >> target_page_bits);
 486     } else {
 487         hash = vsid ^ (pageaddr >> target_page_bits);
 488     }
 489     /* Only 5 bits of the page index are used in the AVPN */
 490     ctx->ptem = (slb->vsid & SLB_VSID_PTEM) |
 491         ((pageaddr >> 16) & ((1ULL << segment_bits) - 0x80));
 492
 493     LOG_MMU("pte segment: key=%d nx %d vsid " TARGET_FMT_lx "\n",
 494             ctx->key, ctx->nx, vsid);
 495     ret = -1;
 496
 497     /* Check if instruction fetch is allowed, if needed */
 498     if (type != ACCESS_CODE || ctx->nx == 0) {
 499         /* Page address translation */
 500         LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
 501                 " hash " TARGET_FMT_plx "\n",
 502                 env->htab_base, env->htab_mask, hash);
 503         ctx->hash[0] = hash;
 504         ctx->hash[1] = ~hash;
 505
 506         /* Initialize real address with an invalid value */
 507         ctx->raddr = (hwaddr)-1ULL;
 508         LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
 509                 " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
 510                 " hash=" TARGET_FMT_plx "\n",
 511                 env->htab_base, env->htab_mask, vsid, ctx->ptem,
 512                 ctx->hash[0]);
 513         /* Primary table lookup */
 514         ret = find_pte64(env, ctx, 0, rw, type, target_page_bits);
 515         if (ret < 0) {
 516             /* Secondary table lookup */
 517             LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
 518                     " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
 519                     " hash=" TARGET_FMT_plx "\n", env->htab_base,
 520                     env->htab_mask, vsid, ctx->ptem, ctx->hash[1]);
 521             ret2 = find_pte64(env, ctx, 1, rw, type, target_page_bits);
 522             if (ret2 != -1) {
 523                 ret = ret2;
 524             }
 525         }
 526     } else {
 527         LOG_MMU("No access allowed\n");
 528         ret = -3;
 529     }
 530
 531     return ret;
 532 }
 533
 534 static int ppc_hash64_get_physical_address(CPUPPCState *env,
 535                                            struct mmu_ctx_hash64 *ctx,
 536                                            target_ulong eaddr, int rw,
 537                                            int access_type)
 538 {
 539     bool real_mode = (access_type == ACCESS_CODE && msr_ir == 0)
 540         || (access_type != ACCESS_CODE && msr_dr == 0);
 541
 542     if (real_mode) {
 543         ctx->raddr = eaddr & 0x0FFFFFFFFFFFFFFFULL;
 544         ctx->prot = PAGE_READ | PAGE_EXEC | PAGE_WRITE;
 545         return 0;
 546     } else {
 547         return get_segment64(env, ctx, eaddr, rw, access_type);
 548     }
 549 }
 550
 551 hwaddr ppc_hash64_get_phys_page_debug(CPUPPCState *env, target_ulong addr)
 552 {
 553     struct mmu_ctx_hash64 ctx;
 554
 555     if (unlikely(ppc_hash64_get_physical_address(env, &ctx, addr, 0, ACCESS_INT)
 556                  != 0)) {
 557         return -1;
 558     }
 559
 560     return ctx.raddr & TARGET_PAGE_MASK;
 561 }
 562
 563 int ppc_hash64_handle_mmu_fault(CPUPPCState *env, target_ulong address, int rw,
 564                                 int mmu_idx)
 565 {
 566     struct mmu_ctx_hash64 ctx;
 567     int access_type;
 568     int ret = 0;
 569
 570     if (rw == 2) {
 571         /* code access */
 572         rw = 0;
 573         access_type = ACCESS_CODE;
 574     } else {
 575         /* data access */
 576         access_type = env->access_type;
 577     }
 578     ret = ppc_hash64_get_physical_address(env, &ctx, address, rw, access_type);
 579     if (ret == 0) {
 580         tlb_set_page(env, address & TARGET_PAGE_MASK,
 581                      ctx.raddr & TARGET_PAGE_MASK, ctx.prot,
 582                      mmu_idx, TARGET_PAGE_SIZE);
 583         ret = 0;
 584     } else if (ret < 0) {
 585         LOG_MMU_STATE(env);
 586         if (access_type == ACCESS_CODE) {
 587             switch (ret) {
 588             case -1:
 589                 env->exception_index = POWERPC_EXCP_ISI;
 590                 env->error_code = 0x40000000;
 591                 break;
 592             case -2:
 593                 /* Access rights violation */
 594                 env->exception_index = POWERPC_EXCP_ISI;
 595                 env->error_code = 0x08000000;
 596                 break;
 597             case -3:
 598                 /* No execute protection violation */
 599                 env->exception_index = POWERPC_EXCP_ISI;
 600                 env->error_code = 0x10000000;
 601                 break;
 602             case -5:
 603                 /* No match in segment table */
 604                 env->exception_index = POWERPC_EXCP_ISEG;
 605                 env->error_code = 0;
 606                 break;
 607             }
 608         } else {
 609             switch (ret) {
 610             case -1:
 611                 /* No matches in page tables or TLB */
 612                 env->exception_index = POWERPC_EXCP_DSI;
 613                 env->error_code = 0;
 614                 env->spr[SPR_DAR] = address;
 615                 if (rw == 1) {
 616                     env->spr[SPR_DSISR] = 0x42000000;
 617                 } else {
 618                     env->spr[SPR_DSISR] = 0x40000000;
 619                 }
 620                 break;
 621             case -2:
 622                 /* Access rights violation */
 623                 env->exception_index = POWERPC_EXCP_DSI;
 624                 env->error_code = 0;
 625                 env->spr[SPR_DAR] = address;
 626                 if (rw == 1) {
 627                     env->spr[SPR_DSISR] = 0x0A000000;
 628                 } else {
 629                     env->spr[SPR_DSISR] = 0x08000000;
 630                 }
 631                 break;
 632             case -5:
 633                 /* No match in segment table */
 634                 env->exception_index = POWERPC_EXCP_DSEG;
 635                 env->error_code = 0;
 636                 env->spr[SPR_DAR] = address;
 637                 break;
 638             }
 639         }
 640 #if 0
 641         printf("%s: set exception to %d %02x\n", __func__,
 642                env->exception, env->error_code);
 643 #endif
 644         ret = 1;
 645     }
 646
 647     return ret;
 648 }