vga: Remove remainder of old conversion cruft
[qemu-kvm.git] / hw / display / vga.c
blob721309f1aa65e57922f121bbe874083a1dd2d0c9
1 /*
2 * QEMU VGA Emulator.
4 * Copyright (c) 2003 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
24 #include "hw/hw.h"
25 #include "vga.h"
26 #include "ui/console.h"
27 #include "hw/i386/pc.h"
28 #include "hw/pci/pci.h"
29 #include "vga_int.h"
30 #include "ui/pixel_ops.h"
31 #include "qemu/timer.h"
32 #include "hw/xen/xen.h"
33 #include "trace.h"
35 //#define DEBUG_VGA
36 //#define DEBUG_VGA_MEM
37 //#define DEBUG_VGA_REG
39 //#define DEBUG_BOCHS_VBE
41 /* 16 state changes per vertical frame @60 Hz */
42 #define VGA_TEXT_CURSOR_PERIOD_MS (1000 * 2 * 16 / 60)
45 * Video Graphics Array (VGA)
47 * Chipset docs for original IBM VGA:
48 * http://www.mcamafia.de/pdf/ibm_vgaxga_trm2.pdf
50 * FreeVGA site:
51 * http://www.osdever.net/FreeVGA/home.htm
53 * Standard VGA features and Bochs VBE extensions are implemented.
56 /* force some bits to zero */
57 const uint8_t sr_mask[8] = {
58 0x03,
59 0x3d,
60 0x0f,
61 0x3f,
62 0x0e,
63 0x00,
64 0x00,
65 0xff,
68 const uint8_t gr_mask[16] = {
69 0x0f, /* 0x00 */
70 0x0f, /* 0x01 */
71 0x0f, /* 0x02 */
72 0x1f, /* 0x03 */
73 0x03, /* 0x04 */
74 0x7b, /* 0x05 */
75 0x0f, /* 0x06 */
76 0x0f, /* 0x07 */
77 0xff, /* 0x08 */
78 0x00, /* 0x09 */
79 0x00, /* 0x0a */
80 0x00, /* 0x0b */
81 0x00, /* 0x0c */
82 0x00, /* 0x0d */
83 0x00, /* 0x0e */
84 0x00, /* 0x0f */
87 #define cbswap_32(__x) \
88 ((uint32_t)( \
89 (((uint32_t)(__x) & (uint32_t)0x000000ffUL) << 24) | \
90 (((uint32_t)(__x) & (uint32_t)0x0000ff00UL) << 8) | \
91 (((uint32_t)(__x) & (uint32_t)0x00ff0000UL) >> 8) | \
92 (((uint32_t)(__x) & (uint32_t)0xff000000UL) >> 24) ))
94 #ifdef HOST_WORDS_BIGENDIAN
95 #define PAT(x) cbswap_32(x)
96 #else
97 #define PAT(x) (x)
98 #endif
100 #ifdef HOST_WORDS_BIGENDIAN
101 #define BIG 1
102 #else
103 #define BIG 0
104 #endif
106 #ifdef HOST_WORDS_BIGENDIAN
107 #define GET_PLANE(data, p) (((data) >> (24 - (p) * 8)) & 0xff)
108 #else
109 #define GET_PLANE(data, p) (((data) >> ((p) * 8)) & 0xff)
110 #endif
112 static const uint32_t mask16[16] = {
113 PAT(0x00000000),
114 PAT(0x000000ff),
115 PAT(0x0000ff00),
116 PAT(0x0000ffff),
117 PAT(0x00ff0000),
118 PAT(0x00ff00ff),
119 PAT(0x00ffff00),
120 PAT(0x00ffffff),
121 PAT(0xff000000),
122 PAT(0xff0000ff),
123 PAT(0xff00ff00),
124 PAT(0xff00ffff),
125 PAT(0xffff0000),
126 PAT(0xffff00ff),
127 PAT(0xffffff00),
128 PAT(0xffffffff),
131 #undef PAT
133 #ifdef HOST_WORDS_BIGENDIAN
134 #define PAT(x) (x)
135 #else
136 #define PAT(x) cbswap_32(x)
137 #endif
139 static const uint32_t dmask16[16] = {
140 PAT(0x00000000),
141 PAT(0x000000ff),
142 PAT(0x0000ff00),
143 PAT(0x0000ffff),
144 PAT(0x00ff0000),
145 PAT(0x00ff00ff),
146 PAT(0x00ffff00),
147 PAT(0x00ffffff),
148 PAT(0xff000000),
149 PAT(0xff0000ff),
150 PAT(0xff00ff00),
151 PAT(0xff00ffff),
152 PAT(0xffff0000),
153 PAT(0xffff00ff),
154 PAT(0xffffff00),
155 PAT(0xffffffff),
158 static const uint32_t dmask4[4] = {
159 PAT(0x00000000),
160 PAT(0x0000ffff),
161 PAT(0xffff0000),
162 PAT(0xffffffff),
165 static uint32_t expand4[256];
166 static uint16_t expand2[256];
167 static uint8_t expand4to8[16];
169 static void vga_update_memory_access(VGACommonState *s)
171 hwaddr base, offset, size;
173 if (s->legacy_address_space == NULL) {
174 return;
177 if (s->has_chain4_alias) {
178 memory_region_del_subregion(s->legacy_address_space, &s->chain4_alias);
179 object_unparent(OBJECT(&s->chain4_alias));
180 s->has_chain4_alias = false;
181 s->plane_updated = 0xf;
183 if ((s->sr[VGA_SEQ_PLANE_WRITE] & VGA_SR02_ALL_PLANES) ==
184 VGA_SR02_ALL_PLANES && s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
185 offset = 0;
186 switch ((s->gr[VGA_GFX_MISC] >> 2) & 3) {
187 case 0:
188 base = 0xa0000;
189 size = 0x20000;
190 break;
191 case 1:
192 base = 0xa0000;
193 size = 0x10000;
194 offset = s->bank_offset;
195 break;
196 case 2:
197 base = 0xb0000;
198 size = 0x8000;
199 break;
200 case 3:
201 default:
202 base = 0xb8000;
203 size = 0x8000;
204 break;
206 base += isa_mem_base;
207 memory_region_init_alias(&s->chain4_alias, memory_region_owner(&s->vram),
208 "vga.chain4", &s->vram, offset, size);
209 memory_region_add_subregion_overlap(s->legacy_address_space, base,
210 &s->chain4_alias, 2);
211 s->has_chain4_alias = true;
215 static void vga_dumb_update_retrace_info(VGACommonState *s)
217 (void) s;
220 static void vga_precise_update_retrace_info(VGACommonState *s)
222 int htotal_chars;
223 int hretr_start_char;
224 int hretr_skew_chars;
225 int hretr_end_char;
227 int vtotal_lines;
228 int vretr_start_line;
229 int vretr_end_line;
231 int dots;
232 #if 0
233 int div2, sldiv2;
234 #endif
235 int clocking_mode;
236 int clock_sel;
237 const int clk_hz[] = {25175000, 28322000, 25175000, 25175000};
238 int64_t chars_per_sec;
239 struct vga_precise_retrace *r = &s->retrace_info.precise;
241 htotal_chars = s->cr[VGA_CRTC_H_TOTAL] + 5;
242 hretr_start_char = s->cr[VGA_CRTC_H_SYNC_START];
243 hretr_skew_chars = (s->cr[VGA_CRTC_H_SYNC_END] >> 5) & 3;
244 hretr_end_char = s->cr[VGA_CRTC_H_SYNC_END] & 0x1f;
246 vtotal_lines = (s->cr[VGA_CRTC_V_TOTAL] |
247 (((s->cr[VGA_CRTC_OVERFLOW] & 1) |
248 ((s->cr[VGA_CRTC_OVERFLOW] >> 4) & 2)) << 8)) + 2;
249 vretr_start_line = s->cr[VGA_CRTC_V_SYNC_START] |
250 ((((s->cr[VGA_CRTC_OVERFLOW] >> 2) & 1) |
251 ((s->cr[VGA_CRTC_OVERFLOW] >> 6) & 2)) << 8);
252 vretr_end_line = s->cr[VGA_CRTC_V_SYNC_END] & 0xf;
254 clocking_mode = (s->sr[VGA_SEQ_CLOCK_MODE] >> 3) & 1;
255 clock_sel = (s->msr >> 2) & 3;
256 dots = (s->msr & 1) ? 8 : 9;
258 chars_per_sec = clk_hz[clock_sel] / dots;
260 htotal_chars <<= clocking_mode;
262 r->total_chars = vtotal_lines * htotal_chars;
263 if (r->freq) {
264 r->ticks_per_char = get_ticks_per_sec() / (r->total_chars * r->freq);
265 } else {
266 r->ticks_per_char = get_ticks_per_sec() / chars_per_sec;
269 r->vstart = vretr_start_line;
270 r->vend = r->vstart + vretr_end_line + 1;
272 r->hstart = hretr_start_char + hretr_skew_chars;
273 r->hend = r->hstart + hretr_end_char + 1;
274 r->htotal = htotal_chars;
276 #if 0
277 div2 = (s->cr[VGA_CRTC_MODE] >> 2) & 1;
278 sldiv2 = (s->cr[VGA_CRTC_MODE] >> 3) & 1;
279 printf (
280 "hz=%f\n"
281 "htotal = %d\n"
282 "hretr_start = %d\n"
283 "hretr_skew = %d\n"
284 "hretr_end = %d\n"
285 "vtotal = %d\n"
286 "vretr_start = %d\n"
287 "vretr_end = %d\n"
288 "div2 = %d sldiv2 = %d\n"
289 "clocking_mode = %d\n"
290 "clock_sel = %d %d\n"
291 "dots = %d\n"
292 "ticks/char = %" PRId64 "\n"
293 "\n",
294 (double) get_ticks_per_sec() / (r->ticks_per_char * r->total_chars),
295 htotal_chars,
296 hretr_start_char,
297 hretr_skew_chars,
298 hretr_end_char,
299 vtotal_lines,
300 vretr_start_line,
301 vretr_end_line,
302 div2, sldiv2,
303 clocking_mode,
304 clock_sel,
305 clk_hz[clock_sel],
306 dots,
307 r->ticks_per_char
309 #endif
312 static uint8_t vga_precise_retrace(VGACommonState *s)
314 struct vga_precise_retrace *r = &s->retrace_info.precise;
315 uint8_t val = s->st01 & ~(ST01_V_RETRACE | ST01_DISP_ENABLE);
317 if (r->total_chars) {
318 int cur_line, cur_line_char, cur_char;
319 int64_t cur_tick;
321 cur_tick = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL);
323 cur_char = (cur_tick / r->ticks_per_char) % r->total_chars;
324 cur_line = cur_char / r->htotal;
326 if (cur_line >= r->vstart && cur_line <= r->vend) {
327 val |= ST01_V_RETRACE | ST01_DISP_ENABLE;
328 } else {
329 cur_line_char = cur_char % r->htotal;
330 if (cur_line_char >= r->hstart && cur_line_char <= r->hend) {
331 val |= ST01_DISP_ENABLE;
335 return val;
336 } else {
337 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
341 static uint8_t vga_dumb_retrace(VGACommonState *s)
343 return s->st01 ^ (ST01_V_RETRACE | ST01_DISP_ENABLE);
346 int vga_ioport_invalid(VGACommonState *s, uint32_t addr)
348 if (s->msr & VGA_MIS_COLOR) {
349 /* Color */
350 return (addr >= 0x3b0 && addr <= 0x3bf);
351 } else {
352 /* Monochrome */
353 return (addr >= 0x3d0 && addr <= 0x3df);
357 uint32_t vga_ioport_read(void *opaque, uint32_t addr)
359 VGACommonState *s = opaque;
360 int val, index;
362 if (vga_ioport_invalid(s, addr)) {
363 val = 0xff;
364 } else {
365 switch(addr) {
366 case VGA_ATT_W:
367 if (s->ar_flip_flop == 0) {
368 val = s->ar_index;
369 } else {
370 val = 0;
372 break;
373 case VGA_ATT_R:
374 index = s->ar_index & 0x1f;
375 if (index < VGA_ATT_C) {
376 val = s->ar[index];
377 } else {
378 val = 0;
380 break;
381 case VGA_MIS_W:
382 val = s->st00;
383 break;
384 case VGA_SEQ_I:
385 val = s->sr_index;
386 break;
387 case VGA_SEQ_D:
388 val = s->sr[s->sr_index];
389 #ifdef DEBUG_VGA_REG
390 printf("vga: read SR%x = 0x%02x\n", s->sr_index, val);
391 #endif
392 break;
393 case VGA_PEL_IR:
394 val = s->dac_state;
395 break;
396 case VGA_PEL_IW:
397 val = s->dac_write_index;
398 break;
399 case VGA_PEL_D:
400 val = s->palette[s->dac_read_index * 3 + s->dac_sub_index];
401 if (++s->dac_sub_index == 3) {
402 s->dac_sub_index = 0;
403 s->dac_read_index++;
405 break;
406 case VGA_FTC_R:
407 val = s->fcr;
408 break;
409 case VGA_MIS_R:
410 val = s->msr;
411 break;
412 case VGA_GFX_I:
413 val = s->gr_index;
414 break;
415 case VGA_GFX_D:
416 val = s->gr[s->gr_index];
417 #ifdef DEBUG_VGA_REG
418 printf("vga: read GR%x = 0x%02x\n", s->gr_index, val);
419 #endif
420 break;
421 case VGA_CRT_IM:
422 case VGA_CRT_IC:
423 val = s->cr_index;
424 break;
425 case VGA_CRT_DM:
426 case VGA_CRT_DC:
427 val = s->cr[s->cr_index];
428 #ifdef DEBUG_VGA_REG
429 printf("vga: read CR%x = 0x%02x\n", s->cr_index, val);
430 #endif
431 break;
432 case VGA_IS1_RM:
433 case VGA_IS1_RC:
434 /* just toggle to fool polling */
435 val = s->st01 = s->retrace(s);
436 s->ar_flip_flop = 0;
437 break;
438 default:
439 val = 0x00;
440 break;
443 #if defined(DEBUG_VGA)
444 printf("VGA: read addr=0x%04x data=0x%02x\n", addr, val);
445 #endif
446 return val;
449 void vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
451 VGACommonState *s = opaque;
452 int index;
454 /* check port range access depending on color/monochrome mode */
455 if (vga_ioport_invalid(s, addr)) {
456 return;
458 #ifdef DEBUG_VGA
459 printf("VGA: write addr=0x%04x data=0x%02x\n", addr, val);
460 #endif
462 switch(addr) {
463 case VGA_ATT_W:
464 if (s->ar_flip_flop == 0) {
465 val &= 0x3f;
466 s->ar_index = val;
467 } else {
468 index = s->ar_index & 0x1f;
469 switch(index) {
470 case VGA_ATC_PALETTE0 ... VGA_ATC_PALETTEF:
471 s->ar[index] = val & 0x3f;
472 break;
473 case VGA_ATC_MODE:
474 s->ar[index] = val & ~0x10;
475 break;
476 case VGA_ATC_OVERSCAN:
477 s->ar[index] = val;
478 break;
479 case VGA_ATC_PLANE_ENABLE:
480 s->ar[index] = val & ~0xc0;
481 break;
482 case VGA_ATC_PEL:
483 s->ar[index] = val & ~0xf0;
484 break;
485 case VGA_ATC_COLOR_PAGE:
486 s->ar[index] = val & ~0xf0;
487 break;
488 default:
489 break;
492 s->ar_flip_flop ^= 1;
493 break;
494 case VGA_MIS_W:
495 s->msr = val & ~0x10;
496 s->update_retrace_info(s);
497 break;
498 case VGA_SEQ_I:
499 s->sr_index = val & 7;
500 break;
501 case VGA_SEQ_D:
502 #ifdef DEBUG_VGA_REG
503 printf("vga: write SR%x = 0x%02x\n", s->sr_index, val);
504 #endif
505 s->sr[s->sr_index] = val & sr_mask[s->sr_index];
506 if (s->sr_index == VGA_SEQ_CLOCK_MODE) {
507 s->update_retrace_info(s);
509 vga_update_memory_access(s);
510 break;
511 case VGA_PEL_IR:
512 s->dac_read_index = val;
513 s->dac_sub_index = 0;
514 s->dac_state = 3;
515 break;
516 case VGA_PEL_IW:
517 s->dac_write_index = val;
518 s->dac_sub_index = 0;
519 s->dac_state = 0;
520 break;
521 case VGA_PEL_D:
522 s->dac_cache[s->dac_sub_index] = val;
523 if (++s->dac_sub_index == 3) {
524 memcpy(&s->palette[s->dac_write_index * 3], s->dac_cache, 3);
525 s->dac_sub_index = 0;
526 s->dac_write_index++;
528 break;
529 case VGA_GFX_I:
530 s->gr_index = val & 0x0f;
531 break;
532 case VGA_GFX_D:
533 #ifdef DEBUG_VGA_REG
534 printf("vga: write GR%x = 0x%02x\n", s->gr_index, val);
535 #endif
536 s->gr[s->gr_index] = val & gr_mask[s->gr_index];
537 vga_update_memory_access(s);
538 break;
539 case VGA_CRT_IM:
540 case VGA_CRT_IC:
541 s->cr_index = val;
542 break;
543 case VGA_CRT_DM:
544 case VGA_CRT_DC:
545 #ifdef DEBUG_VGA_REG
546 printf("vga: write CR%x = 0x%02x\n", s->cr_index, val);
547 #endif
548 /* handle CR0-7 protection */
549 if ((s->cr[VGA_CRTC_V_SYNC_END] & VGA_CR11_LOCK_CR0_CR7) &&
550 s->cr_index <= VGA_CRTC_OVERFLOW) {
551 /* can always write bit 4 of CR7 */
552 if (s->cr_index == VGA_CRTC_OVERFLOW) {
553 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x10) |
554 (val & 0x10);
556 return;
558 s->cr[s->cr_index] = val;
560 switch(s->cr_index) {
561 case VGA_CRTC_H_TOTAL:
562 case VGA_CRTC_H_SYNC_START:
563 case VGA_CRTC_H_SYNC_END:
564 case VGA_CRTC_V_TOTAL:
565 case VGA_CRTC_OVERFLOW:
566 case VGA_CRTC_V_SYNC_END:
567 case VGA_CRTC_MODE:
568 s->update_retrace_info(s);
569 break;
571 break;
572 case VGA_IS1_RM:
573 case VGA_IS1_RC:
574 s->fcr = val & 0x10;
575 break;
580 * Sanity check vbe register writes.
582 * As we don't have a way to signal errors to the guest in the bochs
583 * dispi interface we'll go adjust the registers to the closest valid
584 * value.
586 static void vbe_fixup_regs(VGACommonState *s)
588 uint16_t *r = s->vbe_regs;
589 uint32_t bits, linelength, maxy, offset;
591 if (!(r[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
592 /* vbe is turned off -- nothing to do */
593 return;
596 /* check depth */
597 switch (r[VBE_DISPI_INDEX_BPP]) {
598 case 4:
599 case 8:
600 case 16:
601 case 24:
602 case 32:
603 bits = r[VBE_DISPI_INDEX_BPP];
604 break;
605 case 15:
606 bits = 16;
607 break;
608 default:
609 bits = r[VBE_DISPI_INDEX_BPP] = 8;
610 break;
613 /* check width */
614 r[VBE_DISPI_INDEX_XRES] &= ~7u;
615 if (r[VBE_DISPI_INDEX_XRES] == 0) {
616 r[VBE_DISPI_INDEX_XRES] = 8;
618 if (r[VBE_DISPI_INDEX_XRES] > VBE_DISPI_MAX_XRES) {
619 r[VBE_DISPI_INDEX_XRES] = VBE_DISPI_MAX_XRES;
621 r[VBE_DISPI_INDEX_VIRT_WIDTH] &= ~7u;
622 if (r[VBE_DISPI_INDEX_VIRT_WIDTH] > VBE_DISPI_MAX_XRES) {
623 r[VBE_DISPI_INDEX_VIRT_WIDTH] = VBE_DISPI_MAX_XRES;
625 if (r[VBE_DISPI_INDEX_VIRT_WIDTH] < r[VBE_DISPI_INDEX_XRES]) {
626 r[VBE_DISPI_INDEX_VIRT_WIDTH] = r[VBE_DISPI_INDEX_XRES];
629 /* check height */
630 linelength = r[VBE_DISPI_INDEX_VIRT_WIDTH] * bits / 8;
631 maxy = s->vbe_size / linelength;
632 if (r[VBE_DISPI_INDEX_YRES] == 0) {
633 r[VBE_DISPI_INDEX_YRES] = 1;
635 if (r[VBE_DISPI_INDEX_YRES] > VBE_DISPI_MAX_YRES) {
636 r[VBE_DISPI_INDEX_YRES] = VBE_DISPI_MAX_YRES;
638 if (r[VBE_DISPI_INDEX_YRES] > maxy) {
639 r[VBE_DISPI_INDEX_YRES] = maxy;
642 /* check offset */
643 if (r[VBE_DISPI_INDEX_X_OFFSET] > VBE_DISPI_MAX_XRES) {
644 r[VBE_DISPI_INDEX_X_OFFSET] = VBE_DISPI_MAX_XRES;
646 if (r[VBE_DISPI_INDEX_Y_OFFSET] > VBE_DISPI_MAX_YRES) {
647 r[VBE_DISPI_INDEX_Y_OFFSET] = VBE_DISPI_MAX_YRES;
649 offset = r[VBE_DISPI_INDEX_X_OFFSET] * bits / 8;
650 offset += r[VBE_DISPI_INDEX_Y_OFFSET] * linelength;
651 if (offset + r[VBE_DISPI_INDEX_YRES] * linelength > s->vbe_size) {
652 r[VBE_DISPI_INDEX_Y_OFFSET] = 0;
653 offset = r[VBE_DISPI_INDEX_X_OFFSET] * bits / 8;
654 if (offset + r[VBE_DISPI_INDEX_YRES] * linelength > s->vbe_size) {
655 r[VBE_DISPI_INDEX_X_OFFSET] = 0;
656 offset = 0;
660 /* update vga state */
661 r[VBE_DISPI_INDEX_VIRT_HEIGHT] = maxy;
662 s->vbe_line_offset = linelength;
663 s->vbe_start_addr = offset / 4;
666 static uint32_t vbe_ioport_read_index(void *opaque, uint32_t addr)
668 VGACommonState *s = opaque;
669 uint32_t val;
670 val = s->vbe_index;
671 return val;
674 uint32_t vbe_ioport_read_data(void *opaque, uint32_t addr)
676 VGACommonState *s = opaque;
677 uint32_t val;
679 if (s->vbe_index < VBE_DISPI_INDEX_NB) {
680 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_GETCAPS) {
681 switch(s->vbe_index) {
682 /* XXX: do not hardcode ? */
683 case VBE_DISPI_INDEX_XRES:
684 val = VBE_DISPI_MAX_XRES;
685 break;
686 case VBE_DISPI_INDEX_YRES:
687 val = VBE_DISPI_MAX_YRES;
688 break;
689 case VBE_DISPI_INDEX_BPP:
690 val = VBE_DISPI_MAX_BPP;
691 break;
692 default:
693 val = s->vbe_regs[s->vbe_index];
694 break;
696 } else {
697 val = s->vbe_regs[s->vbe_index];
699 } else if (s->vbe_index == VBE_DISPI_INDEX_VIDEO_MEMORY_64K) {
700 val = s->vbe_size / (64 * 1024);
701 } else {
702 val = 0;
704 #ifdef DEBUG_BOCHS_VBE
705 printf("VBE: read index=0x%x val=0x%x\n", s->vbe_index, val);
706 #endif
707 return val;
710 void vbe_ioport_write_index(void *opaque, uint32_t addr, uint32_t val)
712 VGACommonState *s = opaque;
713 s->vbe_index = val;
716 void vbe_ioport_write_data(void *opaque, uint32_t addr, uint32_t val)
718 VGACommonState *s = opaque;
720 if (s->vbe_index <= VBE_DISPI_INDEX_NB) {
721 #ifdef DEBUG_BOCHS_VBE
722 printf("VBE: write index=0x%x val=0x%x\n", s->vbe_index, val);
723 #endif
724 switch(s->vbe_index) {
725 case VBE_DISPI_INDEX_ID:
726 if (val == VBE_DISPI_ID0 ||
727 val == VBE_DISPI_ID1 ||
728 val == VBE_DISPI_ID2 ||
729 val == VBE_DISPI_ID3 ||
730 val == VBE_DISPI_ID4) {
731 s->vbe_regs[s->vbe_index] = val;
733 break;
734 case VBE_DISPI_INDEX_XRES:
735 case VBE_DISPI_INDEX_YRES:
736 case VBE_DISPI_INDEX_BPP:
737 case VBE_DISPI_INDEX_VIRT_WIDTH:
738 case VBE_DISPI_INDEX_X_OFFSET:
739 case VBE_DISPI_INDEX_Y_OFFSET:
740 s->vbe_regs[s->vbe_index] = val;
741 vbe_fixup_regs(s);
742 break;
743 case VBE_DISPI_INDEX_BANK:
744 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
745 val &= (s->vbe_bank_mask >> 2);
746 } else {
747 val &= s->vbe_bank_mask;
749 s->vbe_regs[s->vbe_index] = val;
750 s->bank_offset = (val << 16);
751 vga_update_memory_access(s);
752 break;
753 case VBE_DISPI_INDEX_ENABLE:
754 if ((val & VBE_DISPI_ENABLED) &&
755 !(s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED)) {
756 int h, shift_control;
758 s->vbe_regs[VBE_DISPI_INDEX_VIRT_WIDTH] = 0;
759 s->vbe_regs[VBE_DISPI_INDEX_X_OFFSET] = 0;
760 s->vbe_regs[VBE_DISPI_INDEX_Y_OFFSET] = 0;
761 s->vbe_regs[VBE_DISPI_INDEX_ENABLE] |= VBE_DISPI_ENABLED;
762 vbe_fixup_regs(s);
764 /* clear the screen (should be done in BIOS) */
765 if (!(val & VBE_DISPI_NOCLEARMEM)) {
766 memset(s->vram_ptr, 0,
767 s->vbe_regs[VBE_DISPI_INDEX_YRES] * s->vbe_line_offset);
770 /* we initialize the VGA graphic mode (should be done
771 in BIOS) */
772 /* graphic mode + memory map 1 */
773 s->gr[VGA_GFX_MISC] = (s->gr[VGA_GFX_MISC] & ~0x0c) | 0x04 |
774 VGA_GR06_GRAPHICS_MODE;
775 s->cr[VGA_CRTC_MODE] |= 3; /* no CGA modes */
776 s->cr[VGA_CRTC_OFFSET] = s->vbe_line_offset >> 3;
777 /* width */
778 s->cr[VGA_CRTC_H_DISP] =
779 (s->vbe_regs[VBE_DISPI_INDEX_XRES] >> 3) - 1;
780 /* height (only meaningful if < 1024) */
781 h = s->vbe_regs[VBE_DISPI_INDEX_YRES] - 1;
782 s->cr[VGA_CRTC_V_DISP_END] = h;
783 s->cr[VGA_CRTC_OVERFLOW] = (s->cr[VGA_CRTC_OVERFLOW] & ~0x42) |
784 ((h >> 7) & 0x02) | ((h >> 3) & 0x40);
785 /* line compare to 1023 */
786 s->cr[VGA_CRTC_LINE_COMPARE] = 0xff;
787 s->cr[VGA_CRTC_OVERFLOW] |= 0x10;
788 s->cr[VGA_CRTC_MAX_SCAN] |= 0x40;
790 if (s->vbe_regs[VBE_DISPI_INDEX_BPP] == 4) {
791 shift_control = 0;
792 s->sr[VGA_SEQ_CLOCK_MODE] &= ~8; /* no double line */
793 } else {
794 shift_control = 2;
795 /* set chain 4 mode */
796 s->sr[VGA_SEQ_MEMORY_MODE] |= VGA_SR04_CHN_4M;
797 /* activate all planes */
798 s->sr[VGA_SEQ_PLANE_WRITE] |= VGA_SR02_ALL_PLANES;
800 s->gr[VGA_GFX_MODE] = (s->gr[VGA_GFX_MODE] & ~0x60) |
801 (shift_control << 5);
802 s->cr[VGA_CRTC_MAX_SCAN] &= ~0x9f; /* no double scan */
803 } else {
804 /* XXX: the bios should do that */
805 s->bank_offset = 0;
807 s->dac_8bit = (val & VBE_DISPI_8BIT_DAC) > 0;
808 s->vbe_regs[s->vbe_index] = val;
809 vga_update_memory_access(s);
810 break;
811 default:
812 break;
817 /* called for accesses between 0xa0000 and 0xc0000 */
818 uint32_t vga_mem_readb(VGACommonState *s, hwaddr addr)
820 int memory_map_mode, plane;
821 uint32_t ret;
823 /* convert to VGA memory offset */
824 memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
825 addr &= 0x1ffff;
826 switch(memory_map_mode) {
827 case 0:
828 break;
829 case 1:
830 if (addr >= 0x10000)
831 return 0xff;
832 addr += s->bank_offset;
833 break;
834 case 2:
835 addr -= 0x10000;
836 if (addr >= 0x8000)
837 return 0xff;
838 break;
839 default:
840 case 3:
841 addr -= 0x18000;
842 if (addr >= 0x8000)
843 return 0xff;
844 break;
847 if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
848 /* chain 4 mode : simplest access */
849 ret = s->vram_ptr[addr];
850 } else if (s->gr[VGA_GFX_MODE] & 0x10) {
851 /* odd/even mode (aka text mode mapping) */
852 plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
853 ret = s->vram_ptr[((addr & ~1) << 1) | plane];
854 } else {
855 /* standard VGA latched access */
856 s->latch = ((uint32_t *)s->vram_ptr)[addr];
858 if (!(s->gr[VGA_GFX_MODE] & 0x08)) {
859 /* read mode 0 */
860 plane = s->gr[VGA_GFX_PLANE_READ];
861 ret = GET_PLANE(s->latch, plane);
862 } else {
863 /* read mode 1 */
864 ret = (s->latch ^ mask16[s->gr[VGA_GFX_COMPARE_VALUE]]) &
865 mask16[s->gr[VGA_GFX_COMPARE_MASK]];
866 ret |= ret >> 16;
867 ret |= ret >> 8;
868 ret = (~ret) & 0xff;
871 return ret;
874 /* called for accesses between 0xa0000 and 0xc0000 */
875 void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val)
877 int memory_map_mode, plane, write_mode, b, func_select, mask;
878 uint32_t write_mask, bit_mask, set_mask;
880 #ifdef DEBUG_VGA_MEM
881 printf("vga: [0x" TARGET_FMT_plx "] = 0x%02x\n", addr, val);
882 #endif
883 /* convert to VGA memory offset */
884 memory_map_mode = (s->gr[VGA_GFX_MISC] >> 2) & 3;
885 addr &= 0x1ffff;
886 switch(memory_map_mode) {
887 case 0:
888 break;
889 case 1:
890 if (addr >= 0x10000)
891 return;
892 addr += s->bank_offset;
893 break;
894 case 2:
895 addr -= 0x10000;
896 if (addr >= 0x8000)
897 return;
898 break;
899 default:
900 case 3:
901 addr -= 0x18000;
902 if (addr >= 0x8000)
903 return;
904 break;
907 if (s->sr[VGA_SEQ_MEMORY_MODE] & VGA_SR04_CHN_4M) {
908 /* chain 4 mode : simplest access */
909 plane = addr & 3;
910 mask = (1 << plane);
911 if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {
912 s->vram_ptr[addr] = val;
913 #ifdef DEBUG_VGA_MEM
914 printf("vga: chain4: [0x" TARGET_FMT_plx "]\n", addr);
915 #endif
916 s->plane_updated |= mask; /* only used to detect font change */
917 memory_region_set_dirty(&s->vram, addr, 1);
919 } else if (s->gr[VGA_GFX_MODE] & 0x10) {
920 /* odd/even mode (aka text mode mapping) */
921 plane = (s->gr[VGA_GFX_PLANE_READ] & 2) | (addr & 1);
922 mask = (1 << plane);
923 if (s->sr[VGA_SEQ_PLANE_WRITE] & mask) {
924 addr = ((addr & ~1) << 1) | plane;
925 s->vram_ptr[addr] = val;
926 #ifdef DEBUG_VGA_MEM
927 printf("vga: odd/even: [0x" TARGET_FMT_plx "]\n", addr);
928 #endif
929 s->plane_updated |= mask; /* only used to detect font change */
930 memory_region_set_dirty(&s->vram, addr, 1);
932 } else {
933 /* standard VGA latched access */
934 write_mode = s->gr[VGA_GFX_MODE] & 3;
935 switch(write_mode) {
936 default:
937 case 0:
938 /* rotate */
939 b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
940 val = ((val >> b) | (val << (8 - b))) & 0xff;
941 val |= val << 8;
942 val |= val << 16;
944 /* apply set/reset mask */
945 set_mask = mask16[s->gr[VGA_GFX_SR_ENABLE]];
946 val = (val & ~set_mask) |
947 (mask16[s->gr[VGA_GFX_SR_VALUE]] & set_mask);
948 bit_mask = s->gr[VGA_GFX_BIT_MASK];
949 break;
950 case 1:
951 val = s->latch;
952 goto do_write;
953 case 2:
954 val = mask16[val & 0x0f];
955 bit_mask = s->gr[VGA_GFX_BIT_MASK];
956 break;
957 case 3:
958 /* rotate */
959 b = s->gr[VGA_GFX_DATA_ROTATE] & 7;
960 val = (val >> b) | (val << (8 - b));
962 bit_mask = s->gr[VGA_GFX_BIT_MASK] & val;
963 val = mask16[s->gr[VGA_GFX_SR_VALUE]];
964 break;
967 /* apply logical operation */
968 func_select = s->gr[VGA_GFX_DATA_ROTATE] >> 3;
969 switch(func_select) {
970 case 0:
971 default:
972 /* nothing to do */
973 break;
974 case 1:
975 /* and */
976 val &= s->latch;
977 break;
978 case 2:
979 /* or */
980 val |= s->latch;
981 break;
982 case 3:
983 /* xor */
984 val ^= s->latch;
985 break;
988 /* apply bit mask */
989 bit_mask |= bit_mask << 8;
990 bit_mask |= bit_mask << 16;
991 val = (val & bit_mask) | (s->latch & ~bit_mask);
993 do_write:
994 /* mask data according to sr[2] */
995 mask = s->sr[VGA_SEQ_PLANE_WRITE];
996 s->plane_updated |= mask; /* only used to detect font change */
997 write_mask = mask16[mask];
998 ((uint32_t *)s->vram_ptr)[addr] =
999 (((uint32_t *)s->vram_ptr)[addr] & ~write_mask) |
1000 (val & write_mask);
1001 #ifdef DEBUG_VGA_MEM
1002 printf("vga: latch: [0x" TARGET_FMT_plx "] mask=0x%08x val=0x%08x\n",
1003 addr * 4, write_mask, val);
1004 #endif
1005 memory_region_set_dirty(&s->vram, addr << 2, sizeof(uint32_t));
1009 typedef void vga_draw_line_func(VGACommonState *s1, uint8_t *d,
1010 const uint8_t *s, int width);
1012 #include "vga_template.h"
1014 static unsigned int rgb_to_pixel32_dup(unsigned int r, unsigned int g, unsigned b)
1016 unsigned int col;
1017 col = rgb_to_pixel32(r, g, b);
1018 return col;
1021 /* return true if the palette was modified */
1022 static int update_palette16(VGACommonState *s)
1024 int full_update, i;
1025 uint32_t v, col, *palette;
1027 full_update = 0;
1028 palette = s->last_palette;
1029 for(i = 0; i < 16; i++) {
1030 v = s->ar[i];
1031 if (s->ar[VGA_ATC_MODE] & 0x80) {
1032 v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xf) << 4) | (v & 0xf);
1033 } else {
1034 v = ((s->ar[VGA_ATC_COLOR_PAGE] & 0xc) << 4) | (v & 0x3f);
1036 v = v * 3;
1037 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1038 c6_to_8(s->palette[v + 1]),
1039 c6_to_8(s->palette[v + 2]));
1040 if (col != palette[i]) {
1041 full_update = 1;
1042 palette[i] = col;
1045 return full_update;
1048 /* return true if the palette was modified */
1049 static int update_palette256(VGACommonState *s)
1051 int full_update, i;
1052 uint32_t v, col, *palette;
1054 full_update = 0;
1055 palette = s->last_palette;
1056 v = 0;
1057 for(i = 0; i < 256; i++) {
1058 if (s->dac_8bit) {
1059 col = s->rgb_to_pixel(s->palette[v],
1060 s->palette[v + 1],
1061 s->palette[v + 2]);
1062 } else {
1063 col = s->rgb_to_pixel(c6_to_8(s->palette[v]),
1064 c6_to_8(s->palette[v + 1]),
1065 c6_to_8(s->palette[v + 2]));
1067 if (col != palette[i]) {
1068 full_update = 1;
1069 palette[i] = col;
1071 v += 3;
1073 return full_update;
1076 static void vga_get_offsets(VGACommonState *s,
1077 uint32_t *pline_offset,
1078 uint32_t *pstart_addr,
1079 uint32_t *pline_compare)
1081 uint32_t start_addr, line_offset, line_compare;
1083 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1084 line_offset = s->vbe_line_offset;
1085 start_addr = s->vbe_start_addr;
1086 line_compare = 65535;
1087 } else {
1088 /* compute line_offset in bytes */
1089 line_offset = s->cr[VGA_CRTC_OFFSET];
1090 line_offset <<= 3;
1092 /* starting address */
1093 start_addr = s->cr[VGA_CRTC_START_LO] |
1094 (s->cr[VGA_CRTC_START_HI] << 8);
1096 /* line compare */
1097 line_compare = s->cr[VGA_CRTC_LINE_COMPARE] |
1098 ((s->cr[VGA_CRTC_OVERFLOW] & 0x10) << 4) |
1099 ((s->cr[VGA_CRTC_MAX_SCAN] & 0x40) << 3);
1101 *pline_offset = line_offset;
1102 *pstart_addr = start_addr;
1103 *pline_compare = line_compare;
1106 /* update start_addr and line_offset. Return TRUE if modified */
1107 static int update_basic_params(VGACommonState *s)
1109 int full_update;
1110 uint32_t start_addr, line_offset, line_compare;
1112 full_update = 0;
1114 s->get_offsets(s, &line_offset, &start_addr, &line_compare);
1116 if (line_offset != s->line_offset ||
1117 start_addr != s->start_addr ||
1118 line_compare != s->line_compare) {
1119 s->line_offset = line_offset;
1120 s->start_addr = start_addr;
1121 s->line_compare = line_compare;
1122 full_update = 1;
1124 return full_update;
1128 static const uint8_t cursor_glyph[32 * 4] = {
1129 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1130 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1131 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1132 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1133 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1134 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1135 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1136 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1137 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1138 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1139 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1140 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1141 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1142 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1143 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1144 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff,
1147 static void vga_get_text_resolution(VGACommonState *s, int *pwidth, int *pheight,
1148 int *pcwidth, int *pcheight)
1150 int width, cwidth, height, cheight;
1152 /* total width & height */
1153 cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
1154 cwidth = 8;
1155 if (!(s->sr[VGA_SEQ_CLOCK_MODE] & VGA_SR01_CHAR_CLK_8DOTS)) {
1156 cwidth = 9;
1158 if (s->sr[VGA_SEQ_CLOCK_MODE] & 0x08) {
1159 cwidth = 16; /* NOTE: no 18 pixel wide */
1161 width = (s->cr[VGA_CRTC_H_DISP] + 1);
1162 if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
1163 /* ugly hack for CGA 160x100x16 - explain me the logic */
1164 height = 100;
1165 } else {
1166 height = s->cr[VGA_CRTC_V_DISP_END] |
1167 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1168 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
1169 height = (height + 1) / cheight;
1172 *pwidth = width;
1173 *pheight = height;
1174 *pcwidth = cwidth;
1175 *pcheight = cheight;
1179 * Text mode update
1180 * Missing:
1181 * - double scan
1182 * - double width
1183 * - underline
1184 * - flashing
1186 static void vga_draw_text(VGACommonState *s, int full_update)
1188 DisplaySurface *surface = qemu_console_surface(s->con);
1189 int cx, cy, cheight, cw, ch, cattr, height, width, ch_attr;
1190 int cx_min, cx_max, linesize, x_incr, line, line1;
1191 uint32_t offset, fgcol, bgcol, v, cursor_offset;
1192 uint8_t *d1, *d, *src, *dest, *cursor_ptr;
1193 const uint8_t *font_ptr, *font_base[2];
1194 int dup9, line_offset;
1195 uint32_t *palette;
1196 uint32_t *ch_attr_ptr;
1197 int64_t now = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
1199 /* compute font data address (in plane 2) */
1200 v = s->sr[VGA_SEQ_CHARACTER_MAP];
1201 offset = (((v >> 4) & 1) | ((v << 1) & 6)) * 8192 * 4 + 2;
1202 if (offset != s->font_offsets[0]) {
1203 s->font_offsets[0] = offset;
1204 full_update = 1;
1206 font_base[0] = s->vram_ptr + offset;
1208 offset = (((v >> 5) & 1) | ((v >> 1) & 6)) * 8192 * 4 + 2;
1209 font_base[1] = s->vram_ptr + offset;
1210 if (offset != s->font_offsets[1]) {
1211 s->font_offsets[1] = offset;
1212 full_update = 1;
1214 if (s->plane_updated & (1 << 2) || s->has_chain4_alias) {
1215 /* if the plane 2 was modified since the last display, it
1216 indicates the font may have been modified */
1217 s->plane_updated = 0;
1218 full_update = 1;
1220 full_update |= update_basic_params(s);
1222 line_offset = s->line_offset;
1224 vga_get_text_resolution(s, &width, &height, &cw, &cheight);
1225 if ((height * width) <= 1) {
1226 /* better than nothing: exit if transient size is too small */
1227 return;
1229 if ((height * width) > CH_ATTR_SIZE) {
1230 /* better than nothing: exit if transient size is too big */
1231 return;
1234 if (width != s->last_width || height != s->last_height ||
1235 cw != s->last_cw || cheight != s->last_ch || s->last_depth) {
1236 s->last_scr_width = width * cw;
1237 s->last_scr_height = height * cheight;
1238 qemu_console_resize(s->con, s->last_scr_width, s->last_scr_height);
1239 surface = qemu_console_surface(s->con);
1240 dpy_text_resize(s->con, width, height);
1241 s->last_depth = 0;
1242 s->last_width = width;
1243 s->last_height = height;
1244 s->last_ch = cheight;
1245 s->last_cw = cw;
1246 full_update = 1;
1248 s->rgb_to_pixel = rgb_to_pixel32_dup;
1249 full_update |= update_palette16(s);
1250 palette = s->last_palette;
1251 x_incr = cw * surface_bytes_per_pixel(surface);
1253 if (full_update) {
1254 s->full_update_text = 1;
1256 if (s->full_update_gfx) {
1257 s->full_update_gfx = 0;
1258 full_update |= 1;
1261 cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
1262 s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
1263 if (cursor_offset != s->cursor_offset ||
1264 s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
1265 s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end) {
1266 /* if the cursor position changed, we update the old and new
1267 chars */
1268 if (s->cursor_offset < CH_ATTR_SIZE)
1269 s->last_ch_attr[s->cursor_offset] = -1;
1270 if (cursor_offset < CH_ATTR_SIZE)
1271 s->last_ch_attr[cursor_offset] = -1;
1272 s->cursor_offset = cursor_offset;
1273 s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
1274 s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
1276 cursor_ptr = s->vram_ptr + (s->start_addr + cursor_offset) * 4;
1277 if (now >= s->cursor_blink_time) {
1278 s->cursor_blink_time = now + VGA_TEXT_CURSOR_PERIOD_MS / 2;
1279 s->cursor_visible_phase = !s->cursor_visible_phase;
1282 dest = surface_data(surface);
1283 linesize = surface_stride(surface);
1284 ch_attr_ptr = s->last_ch_attr;
1285 line = 0;
1286 offset = s->start_addr * 4;
1287 for(cy = 0; cy < height; cy++) {
1288 d1 = dest;
1289 src = s->vram_ptr + offset;
1290 cx_min = width;
1291 cx_max = -1;
1292 for(cx = 0; cx < width; cx++) {
1293 ch_attr = *(uint16_t *)src;
1294 if (full_update || ch_attr != *ch_attr_ptr || src == cursor_ptr) {
1295 if (cx < cx_min)
1296 cx_min = cx;
1297 if (cx > cx_max)
1298 cx_max = cx;
1299 *ch_attr_ptr = ch_attr;
1300 #ifdef HOST_WORDS_BIGENDIAN
1301 ch = ch_attr >> 8;
1302 cattr = ch_attr & 0xff;
1303 #else
1304 ch = ch_attr & 0xff;
1305 cattr = ch_attr >> 8;
1306 #endif
1307 font_ptr = font_base[(cattr >> 3) & 1];
1308 font_ptr += 32 * 4 * ch;
1309 bgcol = palette[cattr >> 4];
1310 fgcol = palette[cattr & 0x0f];
1311 if (cw == 16) {
1312 vga_draw_glyph16(d1, linesize,
1313 font_ptr, cheight, fgcol, bgcol);
1314 } else if (cw != 9) {
1315 vga_draw_glyph8(d1, linesize,
1316 font_ptr, cheight, fgcol, bgcol);
1317 } else {
1318 dup9 = 0;
1319 if (ch >= 0xb0 && ch <= 0xdf &&
1320 (s->ar[VGA_ATC_MODE] & 0x04)) {
1321 dup9 = 1;
1323 vga_draw_glyph9(d1, linesize,
1324 font_ptr, cheight, fgcol, bgcol, dup9);
1326 if (src == cursor_ptr &&
1327 !(s->cr[VGA_CRTC_CURSOR_START] & 0x20) &&
1328 s->cursor_visible_phase) {
1329 int line_start, line_last, h;
1330 /* draw the cursor */
1331 line_start = s->cr[VGA_CRTC_CURSOR_START] & 0x1f;
1332 line_last = s->cr[VGA_CRTC_CURSOR_END] & 0x1f;
1333 /* XXX: check that */
1334 if (line_last > cheight - 1)
1335 line_last = cheight - 1;
1336 if (line_last >= line_start && line_start < cheight) {
1337 h = line_last - line_start + 1;
1338 d = d1 + linesize * line_start;
1339 if (cw == 16) {
1340 vga_draw_glyph16(d, linesize,
1341 cursor_glyph, h, fgcol, bgcol);
1342 } else if (cw != 9) {
1343 vga_draw_glyph8(d, linesize,
1344 cursor_glyph, h, fgcol, bgcol);
1345 } else {
1346 vga_draw_glyph9(d, linesize,
1347 cursor_glyph, h, fgcol, bgcol, 1);
1352 d1 += x_incr;
1353 src += 4;
1354 ch_attr_ptr++;
1356 if (cx_max != -1) {
1357 dpy_gfx_update(s->con, cx_min * cw, cy * cheight,
1358 (cx_max - cx_min + 1) * cw, cheight);
1360 dest += linesize * cheight;
1361 line1 = line + cheight;
1362 offset += line_offset;
1363 if (line < s->line_compare && line1 >= s->line_compare) {
1364 offset = 0;
1366 line = line1;
1370 enum {
1371 VGA_DRAW_LINE2,
1372 VGA_DRAW_LINE2D2,
1373 VGA_DRAW_LINE4,
1374 VGA_DRAW_LINE4D2,
1375 VGA_DRAW_LINE8D2,
1376 VGA_DRAW_LINE8,
1377 VGA_DRAW_LINE15,
1378 VGA_DRAW_LINE16,
1379 VGA_DRAW_LINE24,
1380 VGA_DRAW_LINE32,
1381 VGA_DRAW_LINE_NB,
1384 static vga_draw_line_func * const vga_draw_line_table[VGA_DRAW_LINE_NB] = {
1385 vga_draw_line2,
1386 vga_draw_line2d2,
1387 vga_draw_line4,
1388 vga_draw_line4d2,
1389 vga_draw_line8d2,
1390 vga_draw_line8,
1391 vga_draw_line15,
1392 vga_draw_line16,
1393 vga_draw_line24,
1394 vga_draw_line32,
1397 static int vga_get_bpp(VGACommonState *s)
1399 int ret;
1401 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1402 ret = s->vbe_regs[VBE_DISPI_INDEX_BPP];
1403 } else {
1404 ret = 0;
1406 return ret;
1409 static void vga_get_resolution(VGACommonState *s, int *pwidth, int *pheight)
1411 int width, height;
1413 if (s->vbe_regs[VBE_DISPI_INDEX_ENABLE] & VBE_DISPI_ENABLED) {
1414 width = s->vbe_regs[VBE_DISPI_INDEX_XRES];
1415 height = s->vbe_regs[VBE_DISPI_INDEX_YRES];
1416 } else {
1417 width = (s->cr[VGA_CRTC_H_DISP] + 1) * 8;
1418 height = s->cr[VGA_CRTC_V_DISP_END] |
1419 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1420 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
1421 height = (height + 1);
1423 *pwidth = width;
1424 *pheight = height;
1427 void vga_invalidate_scanlines(VGACommonState *s, int y1, int y2)
1429 int y;
1430 if (y1 >= VGA_MAX_HEIGHT)
1431 return;
1432 if (y2 >= VGA_MAX_HEIGHT)
1433 y2 = VGA_MAX_HEIGHT;
1434 for(y = y1; y < y2; y++) {
1435 s->invalidated_y_table[y >> 5] |= 1 << (y & 0x1f);
1439 void vga_sync_dirty_bitmap(VGACommonState *s)
1441 memory_region_sync_dirty_bitmap(&s->vram);
1444 void vga_dirty_log_start(VGACommonState *s)
1446 memory_region_set_log(&s->vram, true, DIRTY_MEMORY_VGA);
1449 void vga_dirty_log_stop(VGACommonState *s)
1451 memory_region_set_log(&s->vram, false, DIRTY_MEMORY_VGA);
1455 * graphic modes
1457 static void vga_draw_graphic(VGACommonState *s, int full_update)
1459 DisplaySurface *surface = qemu_console_surface(s->con);
1460 int y1, y, update, linesize, y_start, double_scan, mask, depth;
1461 int width, height, shift_control, line_offset, bwidth, bits;
1462 ram_addr_t page0, page1, page_min, page_max;
1463 int disp_width, multi_scan, multi_run;
1464 uint8_t *d;
1465 uint32_t v, addr1, addr;
1466 vga_draw_line_func *vga_draw_line;
1467 #if defined(HOST_WORDS_BIGENDIAN) == defined(TARGET_WORDS_BIGENDIAN)
1468 static const bool byteswap = false;
1469 #else
1470 static const bool byteswap = true;
1471 #endif
1473 full_update |= update_basic_params(s);
1475 if (!full_update)
1476 vga_sync_dirty_bitmap(s);
1478 s->get_resolution(s, &width, &height);
1479 disp_width = width;
1481 shift_control = (s->gr[VGA_GFX_MODE] >> 5) & 3;
1482 double_scan = (s->cr[VGA_CRTC_MAX_SCAN] >> 7);
1483 if (shift_control != 1) {
1484 multi_scan = (((s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1) << double_scan)
1485 - 1;
1486 } else {
1487 /* in CGA modes, multi_scan is ignored */
1488 /* XXX: is it correct ? */
1489 multi_scan = double_scan;
1491 multi_run = multi_scan;
1492 if (shift_control != s->shift_control ||
1493 double_scan != s->double_scan) {
1494 full_update = 1;
1495 s->shift_control = shift_control;
1496 s->double_scan = double_scan;
1499 if (shift_control == 0) {
1500 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1501 disp_width <<= 1;
1503 } else if (shift_control == 1) {
1504 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1505 disp_width <<= 1;
1509 depth = s->get_bpp(s);
1510 if (s->line_offset != s->last_line_offset ||
1511 disp_width != s->last_width ||
1512 height != s->last_height ||
1513 s->last_depth != depth) {
1514 if (depth == 32 || (depth == 16 && !byteswap)) {
1515 pixman_format_code_t format =
1516 qemu_default_pixman_format(depth, !byteswap);
1517 surface = qemu_create_displaysurface_from(disp_width,
1518 height, format, s->line_offset,
1519 s->vram_ptr + (s->start_addr * 4));
1520 dpy_gfx_replace_surface(s->con, surface);
1521 } else {
1522 qemu_console_resize(s->con, disp_width, height);
1523 surface = qemu_console_surface(s->con);
1525 s->last_scr_width = disp_width;
1526 s->last_scr_height = height;
1527 s->last_width = disp_width;
1528 s->last_height = height;
1529 s->last_line_offset = s->line_offset;
1530 s->last_depth = depth;
1531 full_update = 1;
1532 } else if (is_buffer_shared(surface) &&
1533 (full_update || surface_data(surface) != s->vram_ptr
1534 + (s->start_addr * 4))) {
1535 pixman_format_code_t format =
1536 qemu_default_pixman_format(depth, !byteswap);
1537 surface = qemu_create_displaysurface_from(disp_width,
1538 height, format, s->line_offset,
1539 s->vram_ptr + (s->start_addr * 4));
1540 dpy_gfx_replace_surface(s->con, surface);
1543 s->rgb_to_pixel = rgb_to_pixel32_dup;
1545 if (shift_control == 0) {
1546 full_update |= update_palette16(s);
1547 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1548 v = VGA_DRAW_LINE4D2;
1549 } else {
1550 v = VGA_DRAW_LINE4;
1552 bits = 4;
1553 } else if (shift_control == 1) {
1554 full_update |= update_palette16(s);
1555 if (s->sr[VGA_SEQ_CLOCK_MODE] & 8) {
1556 v = VGA_DRAW_LINE2D2;
1557 } else {
1558 v = VGA_DRAW_LINE2;
1560 bits = 4;
1561 } else {
1562 switch(s->get_bpp(s)) {
1563 default:
1564 case 0:
1565 full_update |= update_palette256(s);
1566 v = VGA_DRAW_LINE8D2;
1567 bits = 4;
1568 break;
1569 case 8:
1570 full_update |= update_palette256(s);
1571 v = VGA_DRAW_LINE8;
1572 bits = 8;
1573 break;
1574 case 15:
1575 v = VGA_DRAW_LINE15;
1576 bits = 16;
1577 break;
1578 case 16:
1579 v = VGA_DRAW_LINE16;
1580 bits = 16;
1581 break;
1582 case 24:
1583 v = VGA_DRAW_LINE24;
1584 bits = 24;
1585 break;
1586 case 32:
1587 v = VGA_DRAW_LINE32;
1588 bits = 32;
1589 break;
1592 vga_draw_line = vga_draw_line_table[v];
1594 if (!is_buffer_shared(surface) && s->cursor_invalidate) {
1595 s->cursor_invalidate(s);
1598 line_offset = s->line_offset;
1599 #if 0
1600 printf("w=%d h=%d v=%d line_offset=%d cr[0x09]=0x%02x cr[0x17]=0x%02x linecmp=%d sr[0x01]=0x%02x\n",
1601 width, height, v, line_offset, s->cr[9], s->cr[VGA_CRTC_MODE],
1602 s->line_compare, s->sr[VGA_SEQ_CLOCK_MODE]);
1603 #endif
1604 addr1 = (s->start_addr * 4);
1605 bwidth = (width * bits + 7) / 8;
1606 y_start = -1;
1607 page_min = -1;
1608 page_max = 0;
1609 d = surface_data(surface);
1610 linesize = surface_stride(surface);
1611 y1 = 0;
1612 for(y = 0; y < height; y++) {
1613 addr = addr1;
1614 if (!(s->cr[VGA_CRTC_MODE] & 1)) {
1615 int shift;
1616 /* CGA compatibility handling */
1617 shift = 14 + ((s->cr[VGA_CRTC_MODE] >> 6) & 1);
1618 addr = (addr & ~(1 << shift)) | ((y1 & 1) << shift);
1620 if (!(s->cr[VGA_CRTC_MODE] & 2)) {
1621 addr = (addr & ~0x8000) | ((y1 & 2) << 14);
1623 update = full_update;
1624 page0 = addr;
1625 page1 = addr + bwidth - 1;
1626 update |= memory_region_get_dirty(&s->vram, page0, page1 - page0,
1627 DIRTY_MEMORY_VGA);
1628 /* explicit invalidation for the hardware cursor */
1629 update |= (s->invalidated_y_table[y >> 5] >> (y & 0x1f)) & 1;
1630 if (update) {
1631 if (y_start < 0)
1632 y_start = y;
1633 if (page0 < page_min)
1634 page_min = page0;
1635 if (page1 > page_max)
1636 page_max = page1;
1637 if (!(is_buffer_shared(surface))) {
1638 vga_draw_line(s, d, s->vram_ptr + addr, width);
1639 if (s->cursor_draw_line)
1640 s->cursor_draw_line(s, d, y);
1642 } else {
1643 if (y_start >= 0) {
1644 /* flush to display */
1645 dpy_gfx_update(s->con, 0, y_start,
1646 disp_width, y - y_start);
1647 y_start = -1;
1650 if (!multi_run) {
1651 mask = (s->cr[VGA_CRTC_MODE] & 3) ^ 3;
1652 if ((y1 & mask) == mask)
1653 addr1 += line_offset;
1654 y1++;
1655 multi_run = multi_scan;
1656 } else {
1657 multi_run--;
1659 /* line compare acts on the displayed lines */
1660 if (y == s->line_compare)
1661 addr1 = 0;
1662 d += linesize;
1664 if (y_start >= 0) {
1665 /* flush to display */
1666 dpy_gfx_update(s->con, 0, y_start,
1667 disp_width, y - y_start);
1669 /* reset modified pages */
1670 if (page_max >= page_min) {
1671 memory_region_reset_dirty(&s->vram,
1672 page_min,
1673 page_max - page_min,
1674 DIRTY_MEMORY_VGA);
1676 memset(s->invalidated_y_table, 0, ((height + 31) >> 5) * 4);
1679 static void vga_draw_blank(VGACommonState *s, int full_update)
1681 DisplaySurface *surface = qemu_console_surface(s->con);
1682 int i, w, val;
1683 uint8_t *d;
1685 if (!full_update)
1686 return;
1687 if (s->last_scr_width <= 0 || s->last_scr_height <= 0)
1688 return;
1690 s->rgb_to_pixel = rgb_to_pixel32_dup;
1691 if (surface_bits_per_pixel(surface) == 8) {
1692 val = s->rgb_to_pixel(0, 0, 0);
1693 } else {
1694 val = 0;
1696 w = s->last_scr_width * surface_bytes_per_pixel(surface);
1697 d = surface_data(surface);
1698 for(i = 0; i < s->last_scr_height; i++) {
1699 memset(d, val, w);
1700 d += surface_stride(surface);
1702 dpy_gfx_update(s->con, 0, 0,
1703 s->last_scr_width, s->last_scr_height);
1706 #define GMODE_TEXT 0
1707 #define GMODE_GRAPH 1
1708 #define GMODE_BLANK 2
1710 static void vga_update_display(void *opaque)
1712 VGACommonState *s = opaque;
1713 DisplaySurface *surface = qemu_console_surface(s->con);
1714 int full_update, graphic_mode;
1716 qemu_flush_coalesced_mmio_buffer();
1718 if (surface_bits_per_pixel(surface) == 0) {
1719 /* nothing to do */
1720 } else {
1721 full_update = 0;
1722 if (!(s->ar_index & 0x20)) {
1723 graphic_mode = GMODE_BLANK;
1724 } else {
1725 graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
1727 if (graphic_mode != s->graphic_mode) {
1728 s->graphic_mode = graphic_mode;
1729 s->cursor_blink_time = qemu_clock_get_ms(QEMU_CLOCK_VIRTUAL);
1730 full_update = 1;
1732 switch(graphic_mode) {
1733 case GMODE_TEXT:
1734 vga_draw_text(s, full_update);
1735 break;
1736 case GMODE_GRAPH:
1737 vga_draw_graphic(s, full_update);
1738 break;
1739 case GMODE_BLANK:
1740 default:
1741 vga_draw_blank(s, full_update);
1742 break;
1747 /* force a full display refresh */
1748 static void vga_invalidate_display(void *opaque)
1750 VGACommonState *s = opaque;
1752 s->last_width = -1;
1753 s->last_height = -1;
1756 void vga_common_reset(VGACommonState *s)
1758 s->sr_index = 0;
1759 memset(s->sr, '\0', sizeof(s->sr));
1760 s->gr_index = 0;
1761 memset(s->gr, '\0', sizeof(s->gr));
1762 s->ar_index = 0;
1763 memset(s->ar, '\0', sizeof(s->ar));
1764 s->ar_flip_flop = 0;
1765 s->cr_index = 0;
1766 memset(s->cr, '\0', sizeof(s->cr));
1767 s->msr = 0;
1768 s->fcr = 0;
1769 s->st00 = 0;
1770 s->st01 = 0;
1771 s->dac_state = 0;
1772 s->dac_sub_index = 0;
1773 s->dac_read_index = 0;
1774 s->dac_write_index = 0;
1775 memset(s->dac_cache, '\0', sizeof(s->dac_cache));
1776 s->dac_8bit = 0;
1777 memset(s->palette, '\0', sizeof(s->palette));
1778 s->bank_offset = 0;
1779 s->vbe_index = 0;
1780 memset(s->vbe_regs, '\0', sizeof(s->vbe_regs));
1781 s->vbe_regs[VBE_DISPI_INDEX_ID] = VBE_DISPI_ID5;
1782 s->vbe_start_addr = 0;
1783 s->vbe_line_offset = 0;
1784 s->vbe_bank_mask = (s->vram_size >> 16) - 1;
1785 memset(s->font_offsets, '\0', sizeof(s->font_offsets));
1786 s->graphic_mode = -1; /* force full update */
1787 s->shift_control = 0;
1788 s->double_scan = 0;
1789 s->line_offset = 0;
1790 s->line_compare = 0;
1791 s->start_addr = 0;
1792 s->plane_updated = 0;
1793 s->last_cw = 0;
1794 s->last_ch = 0;
1795 s->last_width = 0;
1796 s->last_height = 0;
1797 s->last_scr_width = 0;
1798 s->last_scr_height = 0;
1799 s->cursor_start = 0;
1800 s->cursor_end = 0;
1801 s->cursor_offset = 0;
1802 memset(s->invalidated_y_table, '\0', sizeof(s->invalidated_y_table));
1803 memset(s->last_palette, '\0', sizeof(s->last_palette));
1804 memset(s->last_ch_attr, '\0', sizeof(s->last_ch_attr));
1805 switch (vga_retrace_method) {
1806 case VGA_RETRACE_DUMB:
1807 break;
1808 case VGA_RETRACE_PRECISE:
1809 memset(&s->retrace_info, 0, sizeof (s->retrace_info));
1810 break;
1812 vga_update_memory_access(s);
1815 static void vga_reset(void *opaque)
1817 VGACommonState *s = opaque;
1818 vga_common_reset(s);
1821 #define TEXTMODE_X(x) ((x) % width)
1822 #define TEXTMODE_Y(x) ((x) / width)
1823 #define VMEM2CHTYPE(v) ((v & 0xff0007ff) | \
1824 ((v & 0x00000800) << 10) | ((v & 0x00007000) >> 1))
1825 /* relay text rendering to the display driver
1826 * instead of doing a full vga_update_display() */
1827 static void vga_update_text(void *opaque, console_ch_t *chardata)
1829 VGACommonState *s = opaque;
1830 int graphic_mode, i, cursor_offset, cursor_visible;
1831 int cw, cheight, width, height, size, c_min, c_max;
1832 uint32_t *src;
1833 console_ch_t *dst, val;
1834 char msg_buffer[80];
1835 int full_update = 0;
1837 qemu_flush_coalesced_mmio_buffer();
1839 if (!(s->ar_index & 0x20)) {
1840 graphic_mode = GMODE_BLANK;
1841 } else {
1842 graphic_mode = s->gr[VGA_GFX_MISC] & VGA_GR06_GRAPHICS_MODE;
1844 if (graphic_mode != s->graphic_mode) {
1845 s->graphic_mode = graphic_mode;
1846 full_update = 1;
1848 if (s->last_width == -1) {
1849 s->last_width = 0;
1850 full_update = 1;
1853 switch (graphic_mode) {
1854 case GMODE_TEXT:
1855 /* TODO: update palette */
1856 full_update |= update_basic_params(s);
1858 /* total width & height */
1859 cheight = (s->cr[VGA_CRTC_MAX_SCAN] & 0x1f) + 1;
1860 cw = 8;
1861 if (!(s->sr[VGA_SEQ_CLOCK_MODE] & VGA_SR01_CHAR_CLK_8DOTS)) {
1862 cw = 9;
1864 if (s->sr[VGA_SEQ_CLOCK_MODE] & 0x08) {
1865 cw = 16; /* NOTE: no 18 pixel wide */
1867 width = (s->cr[VGA_CRTC_H_DISP] + 1);
1868 if (s->cr[VGA_CRTC_V_TOTAL] == 100) {
1869 /* ugly hack for CGA 160x100x16 - explain me the logic */
1870 height = 100;
1871 } else {
1872 height = s->cr[VGA_CRTC_V_DISP_END] |
1873 ((s->cr[VGA_CRTC_OVERFLOW] & 0x02) << 7) |
1874 ((s->cr[VGA_CRTC_OVERFLOW] & 0x40) << 3);
1875 height = (height + 1) / cheight;
1878 size = (height * width);
1879 if (size > CH_ATTR_SIZE) {
1880 if (!full_update)
1881 return;
1883 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Text mode",
1884 width, height);
1885 break;
1888 if (width != s->last_width || height != s->last_height ||
1889 cw != s->last_cw || cheight != s->last_ch) {
1890 s->last_scr_width = width * cw;
1891 s->last_scr_height = height * cheight;
1892 qemu_console_resize(s->con, s->last_scr_width, s->last_scr_height);
1893 dpy_text_resize(s->con, width, height);
1894 s->last_depth = 0;
1895 s->last_width = width;
1896 s->last_height = height;
1897 s->last_ch = cheight;
1898 s->last_cw = cw;
1899 full_update = 1;
1902 if (full_update) {
1903 s->full_update_gfx = 1;
1905 if (s->full_update_text) {
1906 s->full_update_text = 0;
1907 full_update |= 1;
1910 /* Update "hardware" cursor */
1911 cursor_offset = ((s->cr[VGA_CRTC_CURSOR_HI] << 8) |
1912 s->cr[VGA_CRTC_CURSOR_LO]) - s->start_addr;
1913 if (cursor_offset != s->cursor_offset ||
1914 s->cr[VGA_CRTC_CURSOR_START] != s->cursor_start ||
1915 s->cr[VGA_CRTC_CURSOR_END] != s->cursor_end || full_update) {
1916 cursor_visible = !(s->cr[VGA_CRTC_CURSOR_START] & 0x20);
1917 if (cursor_visible && cursor_offset < size && cursor_offset >= 0)
1918 dpy_text_cursor(s->con,
1919 TEXTMODE_X(cursor_offset),
1920 TEXTMODE_Y(cursor_offset));
1921 else
1922 dpy_text_cursor(s->con, -1, -1);
1923 s->cursor_offset = cursor_offset;
1924 s->cursor_start = s->cr[VGA_CRTC_CURSOR_START];
1925 s->cursor_end = s->cr[VGA_CRTC_CURSOR_END];
1928 src = (uint32_t *) s->vram_ptr + s->start_addr;
1929 dst = chardata;
1931 if (full_update) {
1932 for (i = 0; i < size; src ++, dst ++, i ++)
1933 console_write_ch(dst, VMEM2CHTYPE(le32_to_cpu(*src)));
1935 dpy_text_update(s->con, 0, 0, width, height);
1936 } else {
1937 c_max = 0;
1939 for (i = 0; i < size; src ++, dst ++, i ++) {
1940 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
1941 if (*dst != val) {
1942 *dst = val;
1943 c_max = i;
1944 break;
1947 c_min = i;
1948 for (; i < size; src ++, dst ++, i ++) {
1949 console_write_ch(&val, VMEM2CHTYPE(le32_to_cpu(*src)));
1950 if (*dst != val) {
1951 *dst = val;
1952 c_max = i;
1956 if (c_min <= c_max) {
1957 i = TEXTMODE_Y(c_min);
1958 dpy_text_update(s->con, 0, i, width, TEXTMODE_Y(c_max) - i + 1);
1962 return;
1963 case GMODE_GRAPH:
1964 if (!full_update)
1965 return;
1967 s->get_resolution(s, &width, &height);
1968 snprintf(msg_buffer, sizeof(msg_buffer), "%i x %i Graphic mode",
1969 width, height);
1970 break;
1971 case GMODE_BLANK:
1972 default:
1973 if (!full_update)
1974 return;
1976 snprintf(msg_buffer, sizeof(msg_buffer), "VGA Blank mode");
1977 break;
1980 /* Display a message */
1981 s->last_width = 60;
1982 s->last_height = height = 3;
1983 dpy_text_cursor(s->con, -1, -1);
1984 dpy_text_resize(s->con, s->last_width, height);
1986 for (dst = chardata, i = 0; i < s->last_width * height; i ++)
1987 console_write_ch(dst ++, ' ');
1989 size = strlen(msg_buffer);
1990 width = (s->last_width - size) / 2;
1991 dst = chardata + s->last_width + width;
1992 for (i = 0; i < size; i ++)
1993 console_write_ch(dst ++, 0x00200100 | msg_buffer[i]);
1995 dpy_text_update(s->con, 0, 0, s->last_width, height);
1998 static uint64_t vga_mem_read(void *opaque, hwaddr addr,
1999 unsigned size)
2001 VGACommonState *s = opaque;
2003 return vga_mem_readb(s, addr);
2006 static void vga_mem_write(void *opaque, hwaddr addr,
2007 uint64_t data, unsigned size)
2009 VGACommonState *s = opaque;
2011 return vga_mem_writeb(s, addr, data);
2014 const MemoryRegionOps vga_mem_ops = {
2015 .read = vga_mem_read,
2016 .write = vga_mem_write,
2017 .endianness = DEVICE_LITTLE_ENDIAN,
2018 .impl = {
2019 .min_access_size = 1,
2020 .max_access_size = 1,
2024 static int vga_common_post_load(void *opaque, int version_id)
2026 VGACommonState *s = opaque;
2028 /* force refresh */
2029 s->graphic_mode = -1;
2030 return 0;
2033 const VMStateDescription vmstate_vga_common = {
2034 .name = "vga",
2035 .version_id = 2,
2036 .minimum_version_id = 2,
2037 .post_load = vga_common_post_load,
2038 .fields = (VMStateField[]) {
2039 VMSTATE_UINT32(latch, VGACommonState),
2040 VMSTATE_UINT8(sr_index, VGACommonState),
2041 VMSTATE_PARTIAL_BUFFER(sr, VGACommonState, 8),
2042 VMSTATE_UINT8(gr_index, VGACommonState),
2043 VMSTATE_PARTIAL_BUFFER(gr, VGACommonState, 16),
2044 VMSTATE_UINT8(ar_index, VGACommonState),
2045 VMSTATE_BUFFER(ar, VGACommonState),
2046 VMSTATE_INT32(ar_flip_flop, VGACommonState),
2047 VMSTATE_UINT8(cr_index, VGACommonState),
2048 VMSTATE_BUFFER(cr, VGACommonState),
2049 VMSTATE_UINT8(msr, VGACommonState),
2050 VMSTATE_UINT8(fcr, VGACommonState),
2051 VMSTATE_UINT8(st00, VGACommonState),
2052 VMSTATE_UINT8(st01, VGACommonState),
2054 VMSTATE_UINT8(dac_state, VGACommonState),
2055 VMSTATE_UINT8(dac_sub_index, VGACommonState),
2056 VMSTATE_UINT8(dac_read_index, VGACommonState),
2057 VMSTATE_UINT8(dac_write_index, VGACommonState),
2058 VMSTATE_BUFFER(dac_cache, VGACommonState),
2059 VMSTATE_BUFFER(palette, VGACommonState),
2061 VMSTATE_INT32(bank_offset, VGACommonState),
2062 VMSTATE_UINT8_EQUAL(is_vbe_vmstate, VGACommonState),
2063 VMSTATE_UINT16(vbe_index, VGACommonState),
2064 VMSTATE_UINT16_ARRAY(vbe_regs, VGACommonState, VBE_DISPI_INDEX_NB),
2065 VMSTATE_UINT32(vbe_start_addr, VGACommonState),
2066 VMSTATE_UINT32(vbe_line_offset, VGACommonState),
2067 VMSTATE_UINT32(vbe_bank_mask, VGACommonState),
2068 VMSTATE_END_OF_LIST()
2072 static const GraphicHwOps vga_ops = {
2073 .invalidate = vga_invalidate_display,
2074 .gfx_update = vga_update_display,
2075 .text_update = vga_update_text,
2078 void vga_common_init(VGACommonState *s, Object *obj, bool global_vmstate)
2080 int i, j, v, b;
2082 for(i = 0;i < 256; i++) {
2083 v = 0;
2084 for(j = 0; j < 8; j++) {
2085 v |= ((i >> j) & 1) << (j * 4);
2087 expand4[i] = v;
2089 v = 0;
2090 for(j = 0; j < 4; j++) {
2091 v |= ((i >> (2 * j)) & 3) << (j * 4);
2093 expand2[i] = v;
2095 for(i = 0; i < 16; i++) {
2096 v = 0;
2097 for(j = 0; j < 4; j++) {
2098 b = ((i >> j) & 1);
2099 v |= b << (2 * j);
2100 v |= b << (2 * j + 1);
2102 expand4to8[i] = v;
2105 /* valid range: 1 MB -> 256 MB */
2106 s->vram_size = 1024 * 1024;
2107 while (s->vram_size < (s->vram_size_mb << 20) &&
2108 s->vram_size < (256 << 20)) {
2109 s->vram_size <<= 1;
2111 s->vram_size_mb = s->vram_size >> 20;
2112 if (!s->vbe_size) {
2113 s->vbe_size = s->vram_size;
2116 s->is_vbe_vmstate = 1;
2117 memory_region_init_ram(&s->vram, obj, "vga.vram", s->vram_size,
2118 &error_abort);
2119 vmstate_register_ram(&s->vram, global_vmstate ? NULL : DEVICE(obj));
2120 xen_register_framebuffer(&s->vram);
2121 s->vram_ptr = memory_region_get_ram_ptr(&s->vram);
2122 s->get_bpp = vga_get_bpp;
2123 s->get_offsets = vga_get_offsets;
2124 s->get_resolution = vga_get_resolution;
2125 s->hw_ops = &vga_ops;
2126 switch (vga_retrace_method) {
2127 case VGA_RETRACE_DUMB:
2128 s->retrace = vga_dumb_retrace;
2129 s->update_retrace_info = vga_dumb_update_retrace_info;
2130 break;
2132 case VGA_RETRACE_PRECISE:
2133 s->retrace = vga_precise_retrace;
2134 s->update_retrace_info = vga_precise_update_retrace_info;
2135 break;
2137 vga_dirty_log_start(s);
2140 static const MemoryRegionPortio vga_portio_list[] = {
2141 { 0x04, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3b4 */
2142 { 0x0a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3ba */
2143 { 0x10, 16, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3c0 */
2144 { 0x24, 2, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3d4 */
2145 { 0x2a, 1, 1, .read = vga_ioport_read, .write = vga_ioport_write }, /* 3da */
2146 PORTIO_END_OF_LIST(),
2149 static const MemoryRegionPortio vbe_portio_list[] = {
2150 { 0, 1, 2, .read = vbe_ioport_read_index, .write = vbe_ioport_write_index },
2151 # ifdef TARGET_I386
2152 { 1, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
2153 # endif
2154 { 2, 1, 2, .read = vbe_ioport_read_data, .write = vbe_ioport_write_data },
2155 PORTIO_END_OF_LIST(),
2158 /* Used by both ISA and PCI */
2159 MemoryRegion *vga_init_io(VGACommonState *s, Object *obj,
2160 const MemoryRegionPortio **vga_ports,
2161 const MemoryRegionPortio **vbe_ports)
2163 MemoryRegion *vga_mem;
2165 *vga_ports = vga_portio_list;
2166 *vbe_ports = vbe_portio_list;
2168 vga_mem = g_malloc(sizeof(*vga_mem));
2169 memory_region_init_io(vga_mem, obj, &vga_mem_ops, s,
2170 "vga-lowmem", 0x20000);
2171 memory_region_set_flush_coalesced(vga_mem);
2173 return vga_mem;
2176 void vga_init(VGACommonState *s, Object *obj, MemoryRegion *address_space,
2177 MemoryRegion *address_space_io, bool init_vga_ports)
2179 MemoryRegion *vga_io_memory;
2180 const MemoryRegionPortio *vga_ports, *vbe_ports;
2182 qemu_register_reset(vga_reset, s);
2184 s->bank_offset = 0;
2186 s->legacy_address_space = address_space;
2188 vga_io_memory = vga_init_io(s, obj, &vga_ports, &vbe_ports);
2189 memory_region_add_subregion_overlap(address_space,
2190 isa_mem_base + 0x000a0000,
2191 vga_io_memory,
2193 memory_region_set_coalescing(vga_io_memory);
2194 if (init_vga_ports) {
2195 portio_list_init(&s->vga_port_list, obj, vga_ports, s, "vga");
2196 portio_list_set_flush_coalesced(&s->vga_port_list);
2197 portio_list_add(&s->vga_port_list, address_space_io, 0x3b0);
2199 if (vbe_ports) {
2200 portio_list_init(&s->vbe_port_list, obj, vbe_ports, s, "vbe");
2201 portio_list_add(&s->vbe_port_list, address_space_io, 0x1ce);
2205 void vga_init_vbe(VGACommonState *s, Object *obj, MemoryRegion *system_memory)
2207 /* With pc-0.12 and below we map both the PCI BAR and the fixed VBE region,
2208 * so use an alias to avoid double-mapping the same region.
2210 memory_region_init_alias(&s->vram_vbe, obj, "vram.vbe",
2211 &s->vram, 0, memory_region_size(&s->vram));
2212 /* XXX: use optimized standard vga accesses */
2213 memory_region_add_subregion(system_memory,
2214 VBE_DISPI_LFB_PHYSICAL_ADDRESS,
2215 &s->vram_vbe);
2216 s->vbe_mapped = 1;