exec-all.h

   1 /*
   2  * internal execution defines for qemu
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19
  20 #ifndef _EXEC_ALL_H_
  21 #define _EXEC_ALL_H_
  22
  23 #include "qemu-common.h"
  24
  25 /* allow to see translation results - the slowdown should be negligible, so we leave it */
  26 #define DEBUG_DISAS
  27
  28 /* Page tracking code uses ram addresses in system mode, and virtual
  29    addresses in userspace mode.  Define tb_page_addr_t to be an appropriate
  30    type.  */
  31 #if defined(CONFIG_USER_ONLY)
  32 typedef abi_ulong tb_page_addr_t;
  33 #else
  34 typedef ram_addr_t tb_page_addr_t;
  35 #endif
  36
  37 /* is_jmp field values */
  38 #define DISAS_NEXT    0 /* next instruction can be analyzed */
  39 #define DISAS_JUMP    1 /* only pc was modified dynamically */
  40 #define DISAS_UPDATE  2 /* cpu state was modified dynamically */
  41 #define DISAS_TB_JUMP 3 /* only pc was modified statically */
  42
  43 typedef struct TranslationBlock TranslationBlock;
  44
  45 /* XXX: make safe guess about sizes */
  46 #define MAX_OP_PER_INSTR 96
  47
  48 #if HOST_LONG_BITS == 32
  49 #define MAX_OPC_PARAM_PER_ARG 2
  50 #else
  51 #define MAX_OPC_PARAM_PER_ARG 1
  52 #endif
  53 #define MAX_OPC_PARAM_IARGS 4
  54 #define MAX_OPC_PARAM_OARGS 1
  55 #define MAX_OPC_PARAM_ARGS (MAX_OPC_PARAM_IARGS + MAX_OPC_PARAM_OARGS)
  56
  57 /* A Call op needs up to 4 + 2N parameters on 32-bit archs,
  58  * and up to 4 + N parameters on 64-bit archs
  59  * (N = number of input arguments + output arguments).  */
  60 #define MAX_OPC_PARAM (4 + (MAX_OPC_PARAM_PER_ARG * MAX_OPC_PARAM_ARGS))
  61 #define OPC_BUF_SIZE 640
  62 #define OPC_MAX_SIZE (OPC_BUF_SIZE - MAX_OP_PER_INSTR)
  63
  64 /* Maximum size a TCG op can expand to.  This is complicated because a
  65    single op may require several host instructions and register reloads.
  66    For now take a wild guess at 192 bytes, which should allow at least
  67    a couple of fixup instructions per argument.  */
  68 #define TCG_MAX_OP_SIZE 192
  69
  70 #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM)
  71
  72 extern target_ulong gen_opc_pc[OPC_BUF_SIZE];
  73 extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE];
  74 extern uint16_t gen_opc_icount[OPC_BUF_SIZE];
  75
  76 #include "qemu-log.h"
  77
  78 void gen_intermediate_code(CPUState *env, struct TranslationBlock *tb);
  79 void gen_intermediate_code_pc(CPUState *env, struct TranslationBlock *tb);
  80 void gen_pc_load(CPUState *env, struct TranslationBlock *tb,
  81                  unsigned long searched_pc, int pc_pos, void *puc);
  82
  83 void cpu_gen_init(void);
  84 int cpu_gen_code(CPUState *env, struct TranslationBlock *tb,
  85                  int *gen_code_size_ptr);
  86 int cpu_restore_state(struct TranslationBlock *tb,
  87                       CPUState *env, unsigned long searched_pc,
  88                       void *puc);
  89 int cpu_restore_state_copy(struct TranslationBlock *tb,
  90                            CPUState *env, unsigned long searched_pc,
  91                            void *puc);
  92 void cpu_resume_from_signal(CPUState *env1, void *puc);
  93 void cpu_io_recompile(CPUState *env, void *retaddr);
  94 TranslationBlock *tb_gen_code(CPUState *env,
  95                               target_ulong pc, target_ulong cs_base, int flags,
  96                               int cflags);
  97 void cpu_exec_init(CPUState *env);
  98 void QEMU_NORETURN cpu_loop_exit(void);
  99 int page_unprotect(target_ulong address, unsigned long pc, void *puc);
 100 void tb_invalidate_phys_page_range(tb_page_addr_t start, tb_page_addr_t end,
 101                                    int is_cpu_write_access);
 102 void tb_invalidate_page_range(target_ulong start, target_ulong end);
 103 void tlb_flush_page(CPUState *env, target_ulong addr);
 104 void tlb_flush(CPUState *env, int flush_global);
 105 #if !defined(CONFIG_USER_ONLY)
 106 void tlb_set_page(CPUState *env, target_ulong vaddr,
 107                   target_phys_addr_t paddr, int prot,
 108                   int mmu_idx, target_ulong size);
 109 #endif
 110
 111 #define CODE_GEN_ALIGN           16 /* must be >= of the size of a icache line */
 112
 113 #define CODE_GEN_PHYS_HASH_BITS     15
 114 #define CODE_GEN_PHYS_HASH_SIZE     (1 << CODE_GEN_PHYS_HASH_BITS)
 115
 116 #define MIN_CODE_GEN_BUFFER_SIZE     (1024 * 1024)
 117
 118 /* estimated block size for TB allocation */
 119 /* XXX: use a per code average code fragment size and modulate it
 120    according to the host CPU */
 121 #if defined(CONFIG_SOFTMMU)
 122 #define CODE_GEN_AVG_BLOCK_SIZE 128
 123 #else
 124 #define CODE_GEN_AVG_BLOCK_SIZE 64
 125 #endif
 126
 127 #if defined(_ARCH_PPC) || defined(__x86_64__) || defined(__arm__) || defined(__i386__)
 128 #define USE_DIRECT_JUMP
 129 #endif
 130
 131 struct TranslationBlock {
 132     target_ulong pc;   /* simulated PC corresponding to this block (EIP + CS base) */
 133     target_ulong cs_base; /* CS base for this block */
 134     uint64_t flags; /* flags defining in which context the code was generated */
 135     uint16_t size;      /* size of target code for this block (1 <=
 136                            size <= TARGET_PAGE_SIZE) */
 137     uint16_t cflags;    /* compile flags */
 138 #define CF_COUNT_MASK  0x7fff
 139 #define CF_LAST_IO     0x8000 /* Last insn may be an IO access.  */
 140
 141     uint8_t *tc_ptr;    /* pointer to the translated code */
 142     /* next matching tb for physical address. */
 143     struct TranslationBlock *phys_hash_next;
 144     /* first and second physical page containing code. The lower bit
 145        of the pointer tells the index in page_next[] */
 146     struct TranslationBlock *page_next[2];
 147     tb_page_addr_t page_addr[2];
 148
 149     /* the following data are used to directly call another TB from
 150        the code of this one. */
 151     uint16_t tb_next_offset[2]; /* offset of original jump target */
 152 #ifdef USE_DIRECT_JUMP
 153     uint16_t tb_jmp_offset[2]; /* offset of jump instruction */
 154 #else
 155     unsigned long tb_next[2]; /* address of jump generated code */
 156 #endif
 157     /* list of TBs jumping to this one. This is a circular list using
 158        the two least significant bits of the pointers to tell what is
 159        the next pointer: 0 = jmp_next[0], 1 = jmp_next[1], 2 =
 160        jmp_first */
 161     struct TranslationBlock *jmp_next[2];
 162     struct TranslationBlock *jmp_first;
 163     uint32_t icount;
 164 };
 165
 166 static inline unsigned int tb_jmp_cache_hash_page(target_ulong pc)
 167 {
 168     target_ulong tmp;
 169     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 170     return (tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK;
 171 }
 172
 173 static inline unsigned int tb_jmp_cache_hash_func(target_ulong pc)
 174 {
 175     target_ulong tmp;
 176     tmp = pc ^ (pc >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS));
 177     return (((tmp >> (TARGET_PAGE_BITS - TB_JMP_PAGE_BITS)) & TB_JMP_PAGE_MASK)
 178             | (tmp & TB_JMP_ADDR_MASK));
 179 }
 180
 181 static inline unsigned int tb_phys_hash_func(tb_page_addr_t pc)
 182 {
 183     return pc & (CODE_GEN_PHYS_HASH_SIZE - 1);
 184 }
 185
 186 TranslationBlock *tb_alloc(target_ulong pc);
 187 void tb_free(TranslationBlock *tb);
 188 void tb_flush(CPUState *env);
 189 void tb_link_page(TranslationBlock *tb,
 190                   tb_page_addr_t phys_pc, tb_page_addr_t phys_page2);
 191 void tb_phys_invalidate(TranslationBlock *tb, tb_page_addr_t page_addr);
 192
 193 extern TranslationBlock *tb_phys_hash[CODE_GEN_PHYS_HASH_SIZE];
 194 extern uint8_t *code_gen_ptr;
 195 extern int code_gen_max_blocks;
 196
 197 #if defined(USE_DIRECT_JUMP)
 198
 199 #if defined(_ARCH_PPC)
 200 extern void ppc_tb_set_jmp_target(unsigned long jmp_addr, unsigned long addr);
 201 #define tb_set_jmp_target1 ppc_tb_set_jmp_target
 202 #elif defined(__i386__) || defined(__x86_64__)
 203 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 204 {
 205     /* patch the branch destination */
 206     *(uint32_t *)jmp_addr = addr - (jmp_addr + 4);
 207     /* no need to flush icache explicitly */
 208 }
 209 #elif defined(__arm__)
 210 static inline void tb_set_jmp_target1(unsigned long jmp_addr, unsigned long addr)
 211 {
 212 #if QEMU_GNUC_PREREQ(4, 1)
 213     void __clear_cache(char *beg, char *end);
 214 #else
 215     register unsigned long _beg __asm ("a1");
 216     register unsigned long _end __asm ("a2");
 217     register unsigned long _flg __asm ("a3");
 218 #endif
 219
 220     /* we could use a ldr pc, [pc, #-4] kind of branch and avoid the flush */
 221     *(uint32_t *)jmp_addr =
 222         (*(uint32_t *)jmp_addr & ~0xffffff)
 223         | (((addr - (jmp_addr + 8)) >> 2) & 0xffffff);
 224
 225 #if QEMU_GNUC_PREREQ(4, 1)
 226     __clear_cache((char *) jmp_addr, (char *) jmp_addr + 4);
 227 #else
 228     /* flush icache */
 229     _beg = jmp_addr;
 230     _end = jmp_addr + 4;
 231     _flg = 0;
 232     __asm __volatile__ ("swi 0x9f0002" : : "r" (_beg), "r" (_end), "r" (_flg));
 233 #endif
 234 }
 235 #endif
 236
 237 static inline void tb_set_jmp_target(TranslationBlock *tb,
 238                                      int n, unsigned long addr)
 239 {
 240     unsigned long offset;
 241
 242     offset = tb->tb_jmp_offset[n];
 243     tb_set_jmp_target1((unsigned long)(tb->tc_ptr + offset), addr);
 244 }
 245
 246 #else
 247
 248 /* set the jump target */
 249 static inline void tb_set_jmp_target(TranslationBlock *tb,
 250                                      int n, unsigned long addr)
 251 {
 252     tb->tb_next[n] = addr;
 253 }
 254
 255 #endif
 256
 257 static inline void tb_add_jump(TranslationBlock *tb, int n,
 258                                TranslationBlock *tb_next)
 259 {
 260     /* NOTE: this test is only needed for thread safety */
 261     if (!tb->jmp_next[n]) {
 262         /* patch the native jump address */
 263         tb_set_jmp_target(tb, n, (unsigned long)tb_next->tc_ptr);
 264
 265         /* add in TB jmp circular list */
 266         tb->jmp_next[n] = tb_next->jmp_first;
 267         tb_next->jmp_first = (TranslationBlock *)((long)(tb) | (n));
 268     }
 269 }
 270
 271 TranslationBlock *tb_find_pc(unsigned long pc_ptr);
 272
 273 #include "qemu-lock.h"
 274
 275 extern spinlock_t tb_lock;
 276
 277 extern int tb_invalidated_flag;
 278
 279 #if !defined(CONFIG_USER_ONLY)
 280
 281 extern CPUWriteMemoryFunc *io_mem_write[IO_MEM_NB_ENTRIES][4];
 282 extern CPUReadMemoryFunc *io_mem_read[IO_MEM_NB_ENTRIES][4];
 283 extern void *io_mem_opaque[IO_MEM_NB_ENTRIES];
 284
 285 void tlb_fill(target_ulong addr, int is_write, int mmu_idx,
 286               void *retaddr);
 287
 288 #include "softmmu_defs.h"
 289
 290 #define ACCESS_TYPE (NB_MMU_MODES + 1)
 291 #define MEMSUFFIX _code
 292 #define env cpu_single_env
 293
 294 #define DATA_SIZE 1
 295 #include "softmmu_header.h"
 296
 297 #define DATA_SIZE 2
 298 #include "softmmu_header.h"
 299
 300 #define DATA_SIZE 4
 301 #include "softmmu_header.h"
 302
 303 #define DATA_SIZE 8
 304 #include "softmmu_header.h"
 305
 306 #undef ACCESS_TYPE
 307 #undef MEMSUFFIX
 308 #undef env
 309
 310 #endif
 311
 312 #if defined(CONFIG_USER_ONLY)
 313 static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
 314 {
 315     return addr;
 316 }
 317 #else
 318 /* NOTE: this function can trigger an exception */
 319 /* NOTE2: the returned address is not exactly the physical address: it
 320    is the offset relative to phys_ram_base */
 321 static inline tb_page_addr_t get_page_addr_code(CPUState *env1, target_ulong addr)
 322 {
 323     int mmu_idx, page_index, pd;
 324     void *p;
 325
 326     page_index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1);
 327     mmu_idx = cpu_mmu_index(env1);
 328     if (unlikely(env1->tlb_table[mmu_idx][page_index].addr_code !=
 329                  (addr & TARGET_PAGE_MASK))) {
 330         ldub_code(addr);
 331     }
 332     pd = env1->tlb_table[mmu_idx][page_index].addr_code & ~TARGET_PAGE_MASK;
 333     if (pd > IO_MEM_ROM && !(pd & IO_MEM_ROMD)) {
 334 #if defined(TARGET_SPARC) || defined(TARGET_MIPS)
 335         do_unassigned_access(addr, 0, 1, 0, 4);
 336 #else
 337         cpu_abort(env1, "Trying to execute code outside RAM or ROM at 0x" TARGET_FMT_lx "\n", addr);
 338 #endif
 339     }
 340     p = (void *)(unsigned long)addr
 341         + env1->tlb_table[mmu_idx][page_index].addend;
 342     return qemu_ram_addr_from_host(p);
 343 }
 344 #endif
 345
 346 typedef void (CPUDebugExcpHandler)(CPUState *env);
 347
 348 CPUDebugExcpHandler *cpu_set_debug_excp_handler(CPUDebugExcpHandler *handler);
 349
 350 /* vl.c */
 351 extern int singlestep;
 352
 353 /* cpu-exec.c */
 354 extern volatile sig_atomic_t exit_request;
 355
 356 #endif