cpu-all.h

   1 /*
   2  * defines common to all virtual CPUs
   3  *
   4  *  Copyright (c) 2003 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #ifndef CPU_ALL_H
  20 #define CPU_ALL_H
  21
  22 #include "qemu-common.h"
  23 #include "cpu-common.h"
  24
  25 /* some important defines:
  26  *
  27  * WORDS_ALIGNED : if defined, the host cpu can only make word aligned
  28  * memory accesses.
  29  *
  30  * HOST_WORDS_BIGENDIAN : if defined, the host cpu is big endian and
  31  * otherwise little endian.
  32  *
  33  * (TARGET_WORDS_ALIGNED : same for target cpu (not supported yet))
  34  *
  35  * TARGET_WORDS_BIGENDIAN : same for target cpu
  36  */
  37
  38 #include "softfloat.h"
  39
  40 #if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN)
  41 #define BSWAP_NEEDED
  42 #endif
  43
  44 #ifdef BSWAP_NEEDED
  45
  46 static inline uint16_t tswap16(uint16_t s)
  47 {
  48     return bswap16(s);
  49 }
  50
  51 static inline uint32_t tswap32(uint32_t s)
  52 {
  53     return bswap32(s);
  54 }
  55
  56 static inline uint64_t tswap64(uint64_t s)
  57 {
  58     return bswap64(s);
  59 }
  60
  61 static inline void tswap16s(uint16_t *s)
  62 {
  63     *s = bswap16(*s);
  64 }
  65
  66 static inline void tswap32s(uint32_t *s)
  67 {
  68     *s = bswap32(*s);
  69 }
  70
  71 static inline void tswap64s(uint64_t *s)
  72 {
  73     *s = bswap64(*s);
  74 }
  75
  76 #else
  77
  78 static inline uint16_t tswap16(uint16_t s)
  79 {
  80     return s;
  81 }
  82
  83 static inline uint32_t tswap32(uint32_t s)
  84 {
  85     return s;
  86 }
  87
  88 static inline uint64_t tswap64(uint64_t s)
  89 {
  90     return s;
  91 }
  92
  93 static inline void tswap16s(uint16_t *s)
  94 {
  95 }
  96
  97 static inline void tswap32s(uint32_t *s)
  98 {
  99 }
 100
 101 static inline void tswap64s(uint64_t *s)
 102 {
 103 }
 104
 105 #endif
 106
 107 #if TARGET_LONG_SIZE == 4
 108 #define tswapl(s) tswap32(s)
 109 #define tswapls(s) tswap32s((uint32_t *)(s))
 110 #define bswaptls(s) bswap32s(s)
 111 #else
 112 #define tswapl(s) tswap64(s)
 113 #define tswapls(s) tswap64s((uint64_t *)(s))
 114 #define bswaptls(s) bswap64s(s)
 115 #endif
 116
 117 typedef union {
 118     float32 f;
 119     uint32_t l;
 120 } CPU_FloatU;
 121
 122 /* NOTE: arm FPA is horrible as double 32 bit words are stored in big
 123    endian ! */
 124 typedef union {
 125     float64 d;
 126 #if defined(HOST_WORDS_BIGENDIAN)
 127     struct {
 128         uint32_t upper;
 129         uint32_t lower;
 130     } l;
 131 #else
 132     struct {
 133         uint32_t lower;
 134         uint32_t upper;
 135     } l;
 136 #endif
 137     uint64_t ll;
 138 } CPU_DoubleU;
 139
 140 #if defined(FLOATX80)
 141 typedef union {
 142      floatx80 d;
 143      struct {
 144          uint64_t lower;
 145          uint16_t upper;
 146      } l;
 147 } CPU_LDoubleU;
 148 #endif
 149
 150 typedef union {
 151     float128 q;
 152 #if defined(HOST_WORDS_BIGENDIAN)
 153     struct {
 154         uint32_t upmost;
 155         uint32_t upper;
 156         uint32_t lower;
 157         uint32_t lowest;
 158     } l;
 159     struct {
 160         uint64_t upper;
 161         uint64_t lower;
 162     } ll;
 163 #else
 164     struct {
 165         uint32_t lowest;
 166         uint32_t lower;
 167         uint32_t upper;
 168         uint32_t upmost;
 169     } l;
 170     struct {
 171         uint64_t lower;
 172         uint64_t upper;
 173     } ll;
 174 #endif
 175 } CPU_QuadU;
 176
 177 /* CPU memory access without any memory or io remapping */
 178
 179 /*
 180  * the generic syntax for the memory accesses is:
 181  *
 182  * load: ld{type}{sign}{size}{endian}_{access_type}(ptr)
 183  *
 184  * store: st{type}{size}{endian}_{access_type}(ptr, val)
 185  *
 186  * type is:
 187  * (empty): integer access
 188  *   f    : float access
 189  *
 190  * sign is:
 191  * (empty): for floats or 32 bit size
 192  *   u    : unsigned
 193  *   s    : signed
 194  *
 195  * size is:
 196  *   b: 8 bits
 197  *   w: 16 bits
 198  *   l: 32 bits
 199  *   q: 64 bits
 200  *
 201  * endian is:
 202  * (empty): target cpu endianness or 8 bit access
 203  *   r    : reversed target cpu endianness (not implemented yet)
 204  *   be   : big endian (not implemented yet)
 205  *   le   : little endian (not implemented yet)
 206  *
 207  * access_type is:
 208  *   raw    : host memory access
 209  *   user   : user mode access using soft MMU
 210  *   kernel : kernel mode access using soft MMU
 211  */
 212 static inline int ldub_p(const void *ptr)
 213 {
 214     return *(uint8_t *)ptr;
 215 }
 216
 217 static inline int ldsb_p(const void *ptr)
 218 {
 219     return *(int8_t *)ptr;
 220 }
 221
 222 static inline void stb_p(void *ptr, int v)
 223 {
 224     *(uint8_t *)ptr = v;
 225 }
 226
 227 /* NOTE: on arm, putting 2 in /proc/sys/debug/alignment so that the
 228    kernel handles unaligned load/stores may give better results, but
 229    it is a system wide setting : bad */
 230 #if defined(HOST_WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
 231
 232 /* conservative code for little endian unaligned accesses */
 233 static inline int lduw_le_p(const void *ptr)
 234 {
 235 #ifdef _ARCH_PPC
 236     int val;
 237     __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
 238     return val;
 239 #else
 240     const uint8_t *p = ptr;
 241     return p[0] | (p[1] << 8);
 242 #endif
 243 }
 244
 245 static inline int ldsw_le_p(const void *ptr)
 246 {
 247 #ifdef _ARCH_PPC
 248     int val;
 249     __asm__ __volatile__ ("lhbrx %0,0,%1" : "=r" (val) : "r" (ptr));
 250     return (int16_t)val;
 251 #else
 252     const uint8_t *p = ptr;
 253     return (int16_t)(p[0] | (p[1] << 8));
 254 #endif
 255 }
 256
 257 static inline int ldl_le_p(const void *ptr)
 258 {
 259 #ifdef _ARCH_PPC
 260     int val;
 261     __asm__ __volatile__ ("lwbrx %0,0,%1" : "=r" (val) : "r" (ptr));
 262     return val;
 263 #else
 264     const uint8_t *p = ptr;
 265     return p[0] | (p[1] << 8) | (p[2] << 16) | (p[3] << 24);
 266 #endif
 267 }
 268
 269 static inline uint64_t ldq_le_p(const void *ptr)
 270 {
 271     const uint8_t *p = ptr;
 272     uint32_t v1, v2;
 273     v1 = ldl_le_p(p);
 274     v2 = ldl_le_p(p + 4);
 275     return v1 | ((uint64_t)v2 << 32);
 276 }
 277
 278 static inline void stw_le_p(void *ptr, int v)
 279 {
 280 #ifdef _ARCH_PPC
 281     __asm__ __volatile__ ("sthbrx %1,0,%2" : "=m" (*(uint16_t *)ptr) : "r" (v), "r" (ptr));
 282 #else
 283     uint8_t *p = ptr;
 284     p[0] = v;
 285     p[1] = v >> 8;
 286 #endif
 287 }
 288
 289 static inline void stl_le_p(void *ptr, int v)
 290 {
 291 #ifdef _ARCH_PPC
 292     __asm__ __volatile__ ("stwbrx %1,0,%2" : "=m" (*(uint32_t *)ptr) : "r" (v), "r" (ptr));
 293 #else
 294     uint8_t *p = ptr;
 295     p[0] = v;
 296     p[1] = v >> 8;
 297     p[2] = v >> 16;
 298     p[3] = v >> 24;
 299 #endif
 300 }
 301
 302 static inline void stq_le_p(void *ptr, uint64_t v)
 303 {
 304     uint8_t *p = ptr;
 305     stl_le_p(p, (uint32_t)v);
 306     stl_le_p(p + 4, v >> 32);
 307 }
 308
 309 /* float access */
 310
 311 static inline float32 ldfl_le_p(const void *ptr)
 312 {
 313     union {
 314         float32 f;
 315         uint32_t i;
 316     } u;
 317     u.i = ldl_le_p(ptr);
 318     return u.f;
 319 }
 320
 321 static inline void stfl_le_p(void *ptr, float32 v)
 322 {
 323     union {
 324         float32 f;
 325         uint32_t i;
 326     } u;
 327     u.f = v;
 328     stl_le_p(ptr, u.i);
 329 }
 330
 331 static inline float64 ldfq_le_p(const void *ptr)
 332 {
 333     CPU_DoubleU u;
 334     u.l.lower = ldl_le_p(ptr);
 335     u.l.upper = ldl_le_p(ptr + 4);
 336     return u.d;
 337 }
 338
 339 static inline void stfq_le_p(void *ptr, float64 v)
 340 {
 341     CPU_DoubleU u;
 342     u.d = v;
 343     stl_le_p(ptr, u.l.lower);
 344     stl_le_p(ptr + 4, u.l.upper);
 345 }
 346
 347 #else
 348
 349 static inline int lduw_le_p(const void *ptr)
 350 {
 351     return *(uint16_t *)ptr;
 352 }
 353
 354 static inline int ldsw_le_p(const void *ptr)
 355 {
 356     return *(int16_t *)ptr;
 357 }
 358
 359 static inline int ldl_le_p(const void *ptr)
 360 {
 361     return *(uint32_t *)ptr;
 362 }
 363
 364 static inline uint64_t ldq_le_p(const void *ptr)
 365 {
 366     return *(uint64_t *)ptr;
 367 }
 368
 369 static inline void stw_le_p(void *ptr, int v)
 370 {
 371     *(uint16_t *)ptr = v;
 372 }
 373
 374 static inline void stl_le_p(void *ptr, int v)
 375 {
 376     *(uint32_t *)ptr = v;
 377 }
 378
 379 static inline void stq_le_p(void *ptr, uint64_t v)
 380 {
 381     *(uint64_t *)ptr = v;
 382 }
 383
 384 /* float access */
 385
 386 static inline float32 ldfl_le_p(const void *ptr)
 387 {
 388     return *(float32 *)ptr;
 389 }
 390
 391 static inline float64 ldfq_le_p(const void *ptr)
 392 {
 393     return *(float64 *)ptr;
 394 }
 395
 396 static inline void stfl_le_p(void *ptr, float32 v)
 397 {
 398     *(float32 *)ptr = v;
 399 }
 400
 401 static inline void stfq_le_p(void *ptr, float64 v)
 402 {
 403     *(float64 *)ptr = v;
 404 }
 405 #endif
 406
 407 #if !defined(HOST_WORDS_BIGENDIAN) || defined(WORDS_ALIGNED)
 408
 409 static inline int lduw_be_p(const void *ptr)
 410 {
 411 #if defined(__i386__)
 412     int val;
 413     asm volatile ("movzwl %1, %0\n"
 414                   "xchgb %b0, %h0\n"
 415                   : "=q" (val)
 416                   : "m" (*(uint16_t *)ptr));
 417     return val;
 418 #else
 419     const uint8_t *b = ptr;
 420     return ((b[0] << 8) | b[1]);
 421 #endif
 422 }
 423
 424 static inline int ldsw_be_p(const void *ptr)
 425 {
 426 #if defined(__i386__)
 427     int val;
 428     asm volatile ("movzwl %1, %0\n"
 429                   "xchgb %b0, %h0\n"
 430                   : "=q" (val)
 431                   : "m" (*(uint16_t *)ptr));
 432     return (int16_t)val;
 433 #else
 434     const uint8_t *b = ptr;
 435     return (int16_t)((b[0] << 8) | b[1]);
 436 #endif
 437 }
 438
 439 static inline int ldl_be_p(const void *ptr)
 440 {
 441 #if defined(__i386__) || defined(__x86_64__)
 442     int val;
 443     asm volatile ("movl %1, %0\n"
 444                   "bswap %0\n"
 445                   : "=r" (val)
 446                   : "m" (*(uint32_t *)ptr));
 447     return val;
 448 #else
 449     const uint8_t *b = ptr;
 450     return (b[0] << 24) | (b[1] << 16) | (b[2] << 8) | b[3];
 451 #endif
 452 }
 453
 454 static inline uint64_t ldq_be_p(const void *ptr)
 455 {
 456     uint32_t a,b;
 457     a = ldl_be_p(ptr);
 458     b = ldl_be_p((uint8_t *)ptr + 4);
 459     return (((uint64_t)a<<32)|b);
 460 }
 461
 462 static inline void stw_be_p(void *ptr, int v)
 463 {
 464 #if defined(__i386__)
 465     asm volatile ("xchgb %b0, %h0\n"
 466                   "movw %w0, %1\n"
 467                   : "=q" (v)
 468                   : "m" (*(uint16_t *)ptr), "0" (v));
 469 #else
 470     uint8_t *d = (uint8_t *) ptr;
 471     d[0] = v >> 8;
 472     d[1] = v;
 473 #endif
 474 }
 475
 476 static inline void stl_be_p(void *ptr, int v)
 477 {
 478 #if defined(__i386__) || defined(__x86_64__)
 479     asm volatile ("bswap %0\n"
 480                   "movl %0, %1\n"
 481                   : "=r" (v)
 482                   : "m" (*(uint32_t *)ptr), "0" (v));
 483 #else
 484     uint8_t *d = (uint8_t *) ptr;
 485     d[0] = v >> 24;
 486     d[1] = v >> 16;
 487     d[2] = v >> 8;
 488     d[3] = v;
 489 #endif
 490 }
 491
 492 static inline void stq_be_p(void *ptr, uint64_t v)
 493 {
 494     stl_be_p(ptr, v >> 32);
 495     stl_be_p((uint8_t *)ptr + 4, v);
 496 }
 497
 498 /* float access */
 499
 500 static inline float32 ldfl_be_p(const void *ptr)
 501 {
 502     union {
 503         float32 f;
 504         uint32_t i;
 505     } u;
 506     u.i = ldl_be_p(ptr);
 507     return u.f;
 508 }
 509
 510 static inline void stfl_be_p(void *ptr, float32 v)
 511 {
 512     union {
 513         float32 f;
 514         uint32_t i;
 515     } u;
 516     u.f = v;
 517     stl_be_p(ptr, u.i);
 518 }
 519
 520 static inline float64 ldfq_be_p(const void *ptr)
 521 {
 522     CPU_DoubleU u;
 523     u.l.upper = ldl_be_p(ptr);
 524     u.l.lower = ldl_be_p((uint8_t *)ptr + 4);
 525     return u.d;
 526 }
 527
 528 static inline void stfq_be_p(void *ptr, float64 v)
 529 {
 530     CPU_DoubleU u;
 531     u.d = v;
 532     stl_be_p(ptr, u.l.upper);
 533     stl_be_p((uint8_t *)ptr + 4, u.l.lower);
 534 }
 535
 536 #else
 537
 538 static inline int lduw_be_p(const void *ptr)
 539 {
 540     return *(uint16_t *)ptr;
 541 }
 542
 543 static inline int ldsw_be_p(const void *ptr)
 544 {
 545     return *(int16_t *)ptr;
 546 }
 547
 548 static inline int ldl_be_p(const void *ptr)
 549 {
 550     return *(uint32_t *)ptr;
 551 }
 552
 553 static inline uint64_t ldq_be_p(const void *ptr)
 554 {
 555     return *(uint64_t *)ptr;
 556 }
 557
 558 static inline void stw_be_p(void *ptr, int v)
 559 {
 560     *(uint16_t *)ptr = v;
 561 }
 562
 563 static inline void stl_be_p(void *ptr, int v)
 564 {
 565     *(uint32_t *)ptr = v;
 566 }
 567
 568 static inline void stq_be_p(void *ptr, uint64_t v)
 569 {
 570     *(uint64_t *)ptr = v;
 571 }
 572
 573 /* float access */
 574
 575 static inline float32 ldfl_be_p(const void *ptr)
 576 {
 577     return *(float32 *)ptr;
 578 }
 579
 580 static inline float64 ldfq_be_p(const void *ptr)
 581 {
 582     return *(float64 *)ptr;
 583 }
 584
 585 static inline void stfl_be_p(void *ptr, float32 v)
 586 {
 587     *(float32 *)ptr = v;
 588 }
 589
 590 static inline void stfq_be_p(void *ptr, float64 v)
 591 {
 592     *(float64 *)ptr = v;
 593 }
 594
 595 #endif
 596
 597 /* target CPU memory access functions */
 598 #if defined(TARGET_WORDS_BIGENDIAN)
 599 #define lduw_p(p) lduw_be_p(p)
 600 #define ldsw_p(p) ldsw_be_p(p)
 601 #define ldl_p(p) ldl_be_p(p)
 602 #define ldq_p(p) ldq_be_p(p)
 603 #define ldfl_p(p) ldfl_be_p(p)
 604 #define ldfq_p(p) ldfq_be_p(p)
 605 #define stw_p(p, v) stw_be_p(p, v)
 606 #define stl_p(p, v) stl_be_p(p, v)
 607 #define stq_p(p, v) stq_be_p(p, v)
 608 #define stfl_p(p, v) stfl_be_p(p, v)
 609 #define stfq_p(p, v) stfq_be_p(p, v)
 610 #else
 611 #define lduw_p(p) lduw_le_p(p)
 612 #define ldsw_p(p) ldsw_le_p(p)
 613 #define ldl_p(p) ldl_le_p(p)
 614 #define ldq_p(p) ldq_le_p(p)
 615 #define ldfl_p(p) ldfl_le_p(p)
 616 #define ldfq_p(p) ldfq_le_p(p)
 617 #define stw_p(p, v) stw_le_p(p, v)
 618 #define stl_p(p, v) stl_le_p(p, v)
 619 #define stq_p(p, v) stq_le_p(p, v)
 620 #define stfl_p(p, v) stfl_le_p(p, v)
 621 #define stfq_p(p, v) stfq_le_p(p, v)
 622 #endif
 623
 624 /* MMU memory access macros */
 625
 626 #if defined(CONFIG_USER_ONLY)
 627 #include <assert.h>
 628 #include "qemu-types.h"
 629
 630 /* On some host systems the guest address space is reserved on the host.
 631  * This allows the guest address space to be offset to a convenient location.
 632  */
 633 #if defined(CONFIG_USE_GUEST_BASE)
 634 extern unsigned long guest_base;
 635 extern int have_guest_base;
 636 extern unsigned long reserved_va;
 637 #define GUEST_BASE guest_base
 638 #define RESERVED_VA reserved_va
 639 #else
 640 #define GUEST_BASE 0ul
 641 #define RESERVED_VA 0ul
 642 #endif
 643
 644 /* All direct uses of g2h and h2g need to go away for usermode softmmu.  */
 645 #define g2h(x) ((void *)((unsigned long)(x) + GUEST_BASE))
 646
 647 #if HOST_LONG_BITS <= TARGET_VIRT_ADDR_SPACE_BITS
 648 #define h2g_valid(x) 1
 649 #else
 650 #define h2g_valid(x) ({ \
 651     unsigned long __guest = (unsigned long)(x) - GUEST_BASE; \
 652     __guest < (1ul << TARGET_VIRT_ADDR_SPACE_BITS); \
 653 })
 654 #endif
 655
 656 #define h2g(x) ({ \
 657     unsigned long __ret = (unsigned long)(x) - GUEST_BASE; \
 658     /* Check if given address fits target address space */ \
 659     assert(h2g_valid(x)); \
 660     (abi_ulong)__ret; \
 661 })
 662
 663 #define saddr(x) g2h(x)
 664 #define laddr(x) g2h(x)
 665
 666 #else /* !CONFIG_USER_ONLY */
 667 /* NOTE: we use double casts if pointers and target_ulong have
 668    different sizes */
 669 #define saddr(x) (uint8_t *)(long)(x)
 670 #define laddr(x) (uint8_t *)(long)(x)
 671 #endif
 672
 673 #define ldub_raw(p) ldub_p(laddr((p)))
 674 #define ldsb_raw(p) ldsb_p(laddr((p)))
 675 #define lduw_raw(p) lduw_p(laddr((p)))
 676 #define ldsw_raw(p) ldsw_p(laddr((p)))
 677 #define ldl_raw(p) ldl_p(laddr((p)))
 678 #define ldq_raw(p) ldq_p(laddr((p)))
 679 #define ldfl_raw(p) ldfl_p(laddr((p)))
 680 #define ldfq_raw(p) ldfq_p(laddr((p)))
 681 #define stb_raw(p, v) stb_p(saddr((p)), v)
 682 #define stw_raw(p, v) stw_p(saddr((p)), v)
 683 #define stl_raw(p, v) stl_p(saddr((p)), v)
 684 #define stq_raw(p, v) stq_p(saddr((p)), v)
 685 #define stfl_raw(p, v) stfl_p(saddr((p)), v)
 686 #define stfq_raw(p, v) stfq_p(saddr((p)), v)
 687
 688
 689 #if defined(CONFIG_USER_ONLY)
 690
 691 /* if user mode, no other memory access functions */
 692 #define ldub(p) ldub_raw(p)
 693 #define ldsb(p) ldsb_raw(p)
 694 #define lduw(p) lduw_raw(p)
 695 #define ldsw(p) ldsw_raw(p)
 696 #define ldl(p) ldl_raw(p)
 697 #define ldq(p) ldq_raw(p)
 698 #define ldfl(p) ldfl_raw(p)
 699 #define ldfq(p) ldfq_raw(p)
 700 #define stb(p, v) stb_raw(p, v)
 701 #define stw(p, v) stw_raw(p, v)
 702 #define stl(p, v) stl_raw(p, v)
 703 #define stq(p, v) stq_raw(p, v)
 704 #define stfl(p, v) stfl_raw(p, v)
 705 #define stfq(p, v) stfq_raw(p, v)
 706
 707 #define ldub_code(p) ldub_raw(p)
 708 #define ldsb_code(p) ldsb_raw(p)
 709 #define lduw_code(p) lduw_raw(p)
 710 #define ldsw_code(p) ldsw_raw(p)
 711 #define ldl_code(p) ldl_raw(p)
 712 #define ldq_code(p) ldq_raw(p)
 713
 714 #define ldub_kernel(p) ldub_raw(p)
 715 #define ldsb_kernel(p) ldsb_raw(p)
 716 #define lduw_kernel(p) lduw_raw(p)
 717 #define ldsw_kernel(p) ldsw_raw(p)
 718 #define ldl_kernel(p) ldl_raw(p)
 719 #define ldq_kernel(p) ldq_raw(p)
 720 #define ldfl_kernel(p) ldfl_raw(p)
 721 #define ldfq_kernel(p) ldfq_raw(p)
 722 #define stb_kernel(p, v) stb_raw(p, v)
 723 #define stw_kernel(p, v) stw_raw(p, v)
 724 #define stl_kernel(p, v) stl_raw(p, v)
 725 #define stq_kernel(p, v) stq_raw(p, v)
 726 #define stfl_kernel(p, v) stfl_raw(p, v)
 727 #define stfq_kernel(p, vt) stfq_raw(p, v)
 728
 729 #endif /* defined(CONFIG_USER_ONLY) */
 730
 731 /* page related stuff */
 732
 733 #define TARGET_PAGE_SIZE (1 << TARGET_PAGE_BITS)
 734 #define TARGET_PAGE_MASK ~(TARGET_PAGE_SIZE - 1)
 735 #define TARGET_PAGE_ALIGN(addr) (((addr) + TARGET_PAGE_SIZE - 1) & TARGET_PAGE_MASK)
 736
 737 /* ??? These should be the larger of unsigned long and target_ulong.  */
 738 extern unsigned long qemu_real_host_page_size;
 739 extern unsigned long qemu_host_page_bits;
 740 extern unsigned long qemu_host_page_size;
 741 extern unsigned long qemu_host_page_mask;
 742
 743 #define HOST_PAGE_ALIGN(addr) (((addr) + qemu_host_page_size - 1) & qemu_host_page_mask)
 744
 745 /* same as PROT_xxx */
 746 #define PAGE_READ      0x0001
 747 #define PAGE_WRITE     0x0002
 748 #define PAGE_EXEC      0x0004
 749 #define PAGE_BITS      (PAGE_READ | PAGE_WRITE | PAGE_EXEC)
 750 #define PAGE_VALID     0x0008
 751 /* original state of the write flag (used when tracking self-modifying
 752    code */
 753 #define PAGE_WRITE_ORG 0x0010
 754 #if defined(CONFIG_BSD) && defined(CONFIG_USER_ONLY)
 755 /* FIXME: Code that sets/uses this is broken and needs to go away.  */
 756 #define PAGE_RESERVED  0x0020
 757 #endif
 758
 759 #if defined(CONFIG_USER_ONLY)
 760 void page_dump(FILE *f);
 761
 762 typedef int (*walk_memory_regions_fn)(void *, abi_ulong,
 763                                       abi_ulong, unsigned long);
 764 int walk_memory_regions(void *, walk_memory_regions_fn);
 765
 766 int page_get_flags(target_ulong address);
 767 void page_set_flags(target_ulong start, target_ulong end, int flags);
 768 int page_check_range(target_ulong start, target_ulong len, int flags);
 769 #endif
 770
 771 CPUState *cpu_copy(CPUState *env);
 772 CPUState *qemu_get_cpu(int cpu);
 773
 774 #define CPU_DUMP_CODE 0x00010000
 775
 776 void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
 777                     int flags);
 778 void cpu_dump_statistics(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
 779                          int flags);
 780
 781 void QEMU_NORETURN cpu_abort(CPUState *env, const char *fmt, ...)
 782     GCC_FMT_ATTR(2, 3);
 783 extern CPUState *first_cpu;
 784 extern CPUState *cpu_single_env;
 785
 786 /* Flags for use in ENV->INTERRUPT_PENDING.
 787
 788    The numbers assigned here are non-sequential in order to preserve
 789    binary compatibility with the vmstate dump.  Bit 0 (0x0001) was
 790    previously used for CPU_INTERRUPT_EXIT, and is cleared when loading
 791    the vmstate dump.  */
 792
 793 /* External hardware interrupt pending.  This is typically used for
 794    interrupts from devices.  */
 795 #define CPU_INTERRUPT_HARD        0x0002
 796
 797 /* Exit the current TB.  This is typically used when some system-level device
 798    makes some change to the memory mapping.  E.g. the a20 line change.  */
 799 #define CPU_INTERRUPT_EXITTB      0x0004
 800
 801 /* Halt the CPU.  */
 802 #define CPU_INTERRUPT_HALT        0x0020
 803
 804 /* Debug event pending.  */
 805 #define CPU_INTERRUPT_DEBUG       0x0080
 806
 807 /* Several target-specific external hardware interrupts.  Each target/cpu.h
 808    should define proper names based on these defines.  */
 809 #define CPU_INTERRUPT_TGT_EXT_0   0x0008
 810 #define CPU_INTERRUPT_TGT_EXT_1   0x0010
 811 #define CPU_INTERRUPT_TGT_EXT_2   0x0040
 812 #define CPU_INTERRUPT_TGT_EXT_3   0x0200
 813 #define CPU_INTERRUPT_TGT_EXT_4   0x1000
 814
 815 /* Several target-specific internal interrupts.  These differ from the
 816    preceeding target-specific interrupts in that they are intended to
 817    originate from within the cpu itself, typically in response to some
 818    instruction being executed.  These, therefore, are not masked while
 819    single-stepping within the debugger.  */
 820 #define CPU_INTERRUPT_TGT_INT_0   0x0100
 821 #define CPU_INTERRUPT_TGT_INT_1   0x0400
 822 #define CPU_INTERRUPT_TGT_INT_2   0x0800
 823
 824 /* First unused bit: 0x2000.  */
 825
 826 /* The set of all bits that should be masked when single-stepping.  */
 827 #define CPU_INTERRUPT_SSTEP_MASK \
 828     (CPU_INTERRUPT_HARD          \
 829      | CPU_INTERRUPT_TGT_EXT_0   \
 830      | CPU_INTERRUPT_TGT_EXT_1   \
 831      | CPU_INTERRUPT_TGT_EXT_2   \
 832      | CPU_INTERRUPT_TGT_EXT_3   \
 833      | CPU_INTERRUPT_TGT_EXT_4)
 834
 835 #ifndef CONFIG_USER_ONLY
 836 typedef void (*CPUInterruptHandler)(CPUState *, int);
 837
 838 extern CPUInterruptHandler cpu_interrupt_handler;
 839
 840 static inline void cpu_interrupt(CPUState *s, int mask)
 841 {
 842     cpu_interrupt_handler(s, mask);
 843 }
 844 #else /* USER_ONLY */
 845 void cpu_interrupt(CPUState *env, int mask);
 846 #endif /* USER_ONLY */
 847
 848 void cpu_reset_interrupt(CPUState *env, int mask);
 849
 850 void cpu_exit(CPUState *s);
 851
 852 int qemu_cpu_has_work(CPUState *env);
 853
 854 /* Breakpoint/watchpoint flags */
 855 #define BP_MEM_READ           0x01
 856 #define BP_MEM_WRITE          0x02
 857 #define BP_MEM_ACCESS         (BP_MEM_READ | BP_MEM_WRITE)
 858 #define BP_STOP_BEFORE_ACCESS 0x04
 859 #define BP_WATCHPOINT_HIT     0x08
 860 #define BP_GDB                0x10
 861 #define BP_CPU                0x20
 862
 863 int cpu_breakpoint_insert(CPUState *env, target_ulong pc, int flags,
 864                           CPUBreakpoint **breakpoint);
 865 int cpu_breakpoint_remove(CPUState *env, target_ulong pc, int flags);
 866 void cpu_breakpoint_remove_by_ref(CPUState *env, CPUBreakpoint *breakpoint);
 867 void cpu_breakpoint_remove_all(CPUState *env, int mask);
 868 int cpu_watchpoint_insert(CPUState *env, target_ulong addr, target_ulong len,
 869                           int flags, CPUWatchpoint **watchpoint);
 870 int cpu_watchpoint_remove(CPUState *env, target_ulong addr,
 871                           target_ulong len, int flags);
 872 void cpu_watchpoint_remove_by_ref(CPUState *env, CPUWatchpoint *watchpoint);
 873 void cpu_watchpoint_remove_all(CPUState *env, int mask);
 874
 875 #define SSTEP_ENABLE  0x1  /* Enable simulated HW single stepping */
 876 #define SSTEP_NOIRQ   0x2  /* Do not use IRQ while single stepping */
 877 #define SSTEP_NOTIMER 0x4  /* Do not Timers while single stepping */
 878
 879 void cpu_single_step(CPUState *env, int enabled);
 880 void cpu_reset(CPUState *s);
 881 int cpu_is_stopped(CPUState *env);
 882 void run_on_cpu(CPUState *env, void (*func)(void *data), void *data);
 883
 884 #define CPU_LOG_TB_OUT_ASM (1 << 0)
 885 #define CPU_LOG_TB_IN_ASM  (1 << 1)
 886 #define CPU_LOG_TB_OP      (1 << 2)
 887 #define CPU_LOG_TB_OP_OPT  (1 << 3)
 888 #define CPU_LOG_INT        (1 << 4)
 889 #define CPU_LOG_EXEC       (1 << 5)
 890 #define CPU_LOG_PCALL      (1 << 6)
 891 #define CPU_LOG_IOPORT     (1 << 7)
 892 #define CPU_LOG_TB_CPU     (1 << 8)
 893 #define CPU_LOG_RESET      (1 << 9)
 894
 895 /* define log items */
 896 typedef struct CPULogItem {
 897     int mask;
 898     const char *name;
 899     const char *help;
 900 } CPULogItem;
 901
 902 extern const CPULogItem cpu_log_items[];
 903
 904 void cpu_set_log(int log_flags);
 905 void cpu_set_log_filename(const char *filename);
 906 int cpu_str_to_log_mask(const char *str);
 907
 908 #if !defined(CONFIG_USER_ONLY)
 909
 910 /* Return the physical page corresponding to a virtual one. Use it
 911    only for debugging because no protection checks are done. Return -1
 912    if no page found. */
 913 target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr);
 914
 915 /* memory API */
 916
 917 extern int phys_ram_fd;
 918 extern ram_addr_t ram_size;
 919
 920 /* RAM is pre-allocated and passed into qemu_ram_alloc_from_ptr */
 921 #define RAM_PREALLOC_MASK   (1 << 0)
 922
 923 typedef struct RAMBlock {
 924     uint8_t *host;
 925     ram_addr_t offset;
 926     ram_addr_t length;
 927     uint32_t flags;
 928     char idstr[256];
 929     QLIST_ENTRY(RAMBlock) next;
 930 #if defined(__linux__) && !defined(TARGET_S390X)
 931     int fd;
 932 #endif
 933 } RAMBlock;
 934
 935 typedef struct RAMList {
 936     uint8_t *phys_dirty;
 937     QLIST_HEAD(ram, RAMBlock) blocks;
 938 } RAMList;
 939 extern RAMList ram_list;
 940
 941 extern const char *mem_path;
 942 extern int mem_prealloc;
 943
 944 /* physical memory access */
 945
 946 /* MMIO pages are identified by a combination of an IO device index and
 947    3 flags.  The ROMD code stores the page ram offset in iotlb entry,
 948    so only a limited number of ids are avaiable.  */
 949
 950 #define IO_MEM_NB_ENTRIES  (1 << (TARGET_PAGE_BITS  - IO_MEM_SHIFT))
 951
 952 /* Flags stored in the low bits of the TLB virtual address.  These are
 953    defined so that fast path ram access is all zeros.  */
 954 /* Zero if TLB entry is valid.  */
 955 #define TLB_INVALID_MASK   (1 << 3)
 956 /* Set if TLB entry references a clean RAM page.  The iotlb entry will
 957    contain the page physical address.  */
 958 #define TLB_NOTDIRTY    (1 << 4)
 959 /* Set if TLB entry is an IO callback.  */
 960 #define TLB_MMIO        (1 << 5)
 961
 962 #define VGA_DIRTY_FLAG       0x01
 963 #define CODE_DIRTY_FLAG      0x02
 964 #define MIGRATION_DIRTY_FLAG 0x08
 965
 966 /* read dirty bit (return 0 or 1) */
 967 static inline int cpu_physical_memory_is_dirty(ram_addr_t addr)
 968 {
 969     return ram_list.phys_dirty[addr >> TARGET_PAGE_BITS] == 0xff;
 970 }
 971
 972 static inline int cpu_physical_memory_get_dirty_flags(ram_addr_t addr)
 973 {
 974     return ram_list.phys_dirty[addr >> TARGET_PAGE_BITS];
 975 }
 976
 977 static inline int cpu_physical_memory_get_dirty(ram_addr_t addr,
 978                                                 int dirty_flags)
 979 {
 980     return ram_list.phys_dirty[addr >> TARGET_PAGE_BITS] & dirty_flags;
 981 }
 982
 983 static inline void cpu_physical_memory_set_dirty(ram_addr_t addr)
 984 {
 985     ram_list.phys_dirty[addr >> TARGET_PAGE_BITS] = 0xff;
 986 }
 987
 988 static inline int cpu_physical_memory_set_dirty_flags(ram_addr_t addr,
 989                                                       int dirty_flags)
 990 {
 991     return ram_list.phys_dirty[addr >> TARGET_PAGE_BITS] |= dirty_flags;
 992 }
 993
 994 static inline void cpu_physical_memory_mask_dirty_range(ram_addr_t start,
 995                                                         int length,
 996                                                         int dirty_flags)
 997 {
 998     int i, mask, len;
 999     uint8_t *p;
1000
1001     len = length >> TARGET_PAGE_BITS;
1002     mask = ~dirty_flags;
1003     p = ram_list.phys_dirty + (start >> TARGET_PAGE_BITS);
1004     for (i = 0; i < len; i++) {
1005         p[i] &= mask;
1006     }
1007 }
1008
1009 void cpu_physical_memory_reset_dirty(ram_addr_t start, ram_addr_t end,
1010                                      int dirty_flags);
1011 void cpu_tlb_update_dirty(CPUState *env);
1012
1013 int cpu_physical_memory_set_dirty_tracking(int enable);
1014
1015 int cpu_physical_memory_get_dirty_tracking(void);
1016
1017 int cpu_physical_sync_dirty_bitmap(target_phys_addr_t start_addr,
1018                                    target_phys_addr_t end_addr);
1019
1020 int cpu_physical_log_start(target_phys_addr_t start_addr,
1021                            ram_addr_t size);
1022
1023 int cpu_physical_log_stop(target_phys_addr_t start_addr,
1024                           ram_addr_t size);
1025
1026 void dump_exec_info(FILE *f, fprintf_function cpu_fprintf);
1027 #endif /* !CONFIG_USER_ONLY */
1028
1029 int cpu_memory_rw_debug(CPUState *env, target_ulong addr,
1030                         uint8_t *buf, int len, int is_write);
1031
1032 #endif /* CPU_ALL_H */