hw/apic.c

   1 /*
   2  *  APIC support
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  18  */
  19 #include "hw.h"
  20 #include "apic.h"
  21 #include "ioapic.h"
  22 #include "qemu-timer.h"
  23 #include "host-utils.h"
  24 #include "sysbus.h"
  25 #include "trace.h"
  26 #include "kvm.h"
  27
  28 /* APIC Local Vector Table */
  29 #define APIC_LVT_TIMER   0
  30 #define APIC_LVT_THERMAL 1
  31 #define APIC_LVT_PERFORM 2
  32 #define APIC_LVT_LINT0   3
  33 #define APIC_LVT_LINT1   4
  34 #define APIC_LVT_ERROR   5
  35 #define APIC_LVT_NB      6
  36
  37 /* APIC delivery modes */
  38 #define APIC_DM_FIXED   0
  39 #define APIC_DM_LOWPRI  1
  40 #define APIC_DM_SMI     2
  41 #define APIC_DM_NMI     4
  42 #define APIC_DM_INIT    5
  43 #define APIC_DM_SIPI    6
  44 #define APIC_DM_EXTINT  7
  45
  46 /* APIC destination mode */
  47 #define APIC_DESTMODE_FLAT      0xf
  48 #define APIC_DESTMODE_CLUSTER   1
  49
  50 #define APIC_TRIGGER_EDGE  0
  51 #define APIC_TRIGGER_LEVEL 1
  52
  53 #define APIC_LVT_TIMER_PERIODIC         (1<<17)
  54 #define APIC_LVT_MASKED                 (1<<16)
  55 #define APIC_LVT_LEVEL_TRIGGER          (1<<15)
  56 #define APIC_LVT_REMOTE_IRR             (1<<14)
  57 #define APIC_INPUT_POLARITY             (1<<13)
  58 #define APIC_SEND_PENDING               (1<<12)
  59
  60 #define ESR_ILLEGAL_ADDRESS (1 << 7)
  61
  62 #define APIC_SV_DIRECTED_IO             (1<<12)
  63 #define APIC_SV_ENABLE                  (1<<8)
  64
  65 #define MAX_APICS 255
  66 #define MAX_APIC_WORDS 8
  67
  68 /* Intel APIC constants: from include/asm/msidef.h */
  69 #define MSI_DATA_VECTOR_SHIFT           0
  70 #define MSI_DATA_VECTOR_MASK            0x000000ff
  71 #define MSI_DATA_DELIVERY_MODE_SHIFT    8
  72 #define MSI_DATA_TRIGGER_SHIFT          15
  73 #define MSI_DATA_LEVEL_SHIFT            14
  74 #define MSI_ADDR_DEST_MODE_SHIFT        2
  75 #define MSI_ADDR_DEST_ID_SHIFT          12
  76 #define MSI_ADDR_DEST_ID_MASK           0x00ffff0
  77
  78 #define MSI_ADDR_SIZE                   0x100000
  79
  80 typedef struct APICState APICState;
  81
  82 struct APICState {
  83     SysBusDevice busdev;
  84     void *cpu_env;
  85     uint32_t apicbase;
  86     uint8_t id;
  87     uint8_t arb_id;
  88     uint8_t tpr;
  89     uint32_t spurious_vec;
  90     uint8_t log_dest;
  91     uint8_t dest_mode;
  92     uint32_t isr[8];  /* in service register */
  93     uint32_t tmr[8];  /* trigger mode register */
  94     uint32_t irr[8]; /* interrupt request register */
  95     uint32_t lvt[APIC_LVT_NB];
  96     uint32_t esr; /* error register */
  97     uint32_t icr[2];
  98
  99     uint32_t divide_conf;
 100     int count_shift;
 101     uint32_t initial_count;
 102     int64_t initial_count_load_time, next_time;
 103     uint32_t idx;
 104     QEMUTimer *timer;
 105     int sipi_vector;
 106     int wait_for_sipi;
 107 };
 108
 109 static APICState *local_apics[MAX_APICS + 1];
 110 static int apic_irq_delivered;
 111
 112 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode);
 113 static void apic_update_irq(APICState *s);
 114 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 115                                       uint8_t dest, uint8_t dest_mode);
 116
 117 /* Find first bit starting from msb */
 118 static int fls_bit(uint32_t value)
 119 {
 120     return 31 - clz32(value);
 121 }
 122
 123 /* Find first bit starting from lsb */
 124 static int ffs_bit(uint32_t value)
 125 {
 126     return ctz32(value);
 127 }
 128
 129 static inline void set_bit(uint32_t *tab, int index)
 130 {
 131     int i, mask;
 132     i = index >> 5;
 133     mask = 1 << (index & 0x1f);
 134     tab[i] |= mask;
 135 }
 136
 137 static inline void reset_bit(uint32_t *tab, int index)
 138 {
 139     int i, mask;
 140     i = index >> 5;
 141     mask = 1 << (index & 0x1f);
 142     tab[i] &= ~mask;
 143 }
 144
 145 static inline int get_bit(uint32_t *tab, int index)
 146 {
 147     int i, mask;
 148     i = index >> 5;
 149     mask = 1 << (index & 0x1f);
 150     return !!(tab[i] & mask);
 151 }
 152
 153 static void apic_local_deliver(APICState *s, int vector)
 154 {
 155     uint32_t lvt = s->lvt[vector];
 156     int trigger_mode;
 157
 158     trace_apic_local_deliver(vector, (lvt >> 8) & 7);
 159
 160     if (lvt & APIC_LVT_MASKED)
 161         return;
 162
 163     switch ((lvt >> 8) & 7) {
 164     case APIC_DM_SMI:
 165         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SMI);
 166         break;
 167
 168     case APIC_DM_NMI:
 169         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_NMI);
 170         break;
 171
 172     case APIC_DM_EXTINT:
 173         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 174         break;
 175
 176     case APIC_DM_FIXED:
 177         trigger_mode = APIC_TRIGGER_EDGE;
 178         if ((vector == APIC_LVT_LINT0 || vector == APIC_LVT_LINT1) &&
 179             (lvt & APIC_LVT_LEVEL_TRIGGER))
 180             trigger_mode = APIC_TRIGGER_LEVEL;
 181         apic_set_irq(s, lvt & 0xff, trigger_mode);
 182     }
 183 }
 184
 185 void apic_deliver_pic_intr(DeviceState *d, int level)
 186 {
 187     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 188
 189     if (level) {
 190         apic_local_deliver(s, APIC_LVT_LINT0);
 191     } else {
 192         uint32_t lvt = s->lvt[APIC_LVT_LINT0];
 193
 194         switch ((lvt >> 8) & 7) {
 195         case APIC_DM_FIXED:
 196             if (!(lvt & APIC_LVT_LEVEL_TRIGGER))
 197                 break;
 198             reset_bit(s->irr, lvt & 0xff);
 199             /* fall through */
 200         case APIC_DM_EXTINT:
 201             cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 202             break;
 203         }
 204     }
 205 }
 206
 207 #define foreach_apic(apic, deliver_bitmask, code) \
 208 {\
 209     int __i, __j, __mask;\
 210     for(__i = 0; __i < MAX_APIC_WORDS; __i++) {\
 211         __mask = deliver_bitmask[__i];\
 212         if (__mask) {\
 213             for(__j = 0; __j < 32; __j++) {\
 214                 if (__mask & (1 << __j)) {\
 215                     apic = local_apics[__i * 32 + __j];\
 216                     if (apic) {\
 217                         code;\
 218                     }\
 219                 }\
 220             }\
 221         }\
 222     }\
 223 }
 224
 225 static void apic_bus_deliver(const uint32_t *deliver_bitmask,
 226                              uint8_t delivery_mode,
 227                              uint8_t vector_num, uint8_t polarity,
 228                              uint8_t trigger_mode)
 229 {
 230     APICState *apic_iter;
 231
 232     switch (delivery_mode) {
 233         case APIC_DM_LOWPRI:
 234             /* XXX: search for focus processor, arbitration */
 235             {
 236                 int i, d;
 237                 d = -1;
 238                 for(i = 0; i < MAX_APIC_WORDS; i++) {
 239                     if (deliver_bitmask[i]) {
 240                         d = i * 32 + ffs_bit(deliver_bitmask[i]);
 241                         break;
 242                     }
 243                 }
 244                 if (d >= 0) {
 245                     apic_iter = local_apics[d];
 246                     if (apic_iter) {
 247                         apic_set_irq(apic_iter, vector_num, trigger_mode);
 248                     }
 249                 }
 250             }
 251             return;
 252
 253         case APIC_DM_FIXED:
 254             break;
 255
 256         case APIC_DM_SMI:
 257             foreach_apic(apic_iter, deliver_bitmask,
 258                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_SMI) );
 259             return;
 260
 261         case APIC_DM_NMI:
 262             foreach_apic(apic_iter, deliver_bitmask,
 263                 cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_NMI) );
 264             return;
 265
 266         case APIC_DM_INIT:
 267             /* normal INIT IPI sent to processors */
 268             foreach_apic(apic_iter, deliver_bitmask,
 269                          cpu_interrupt(apic_iter->cpu_env, CPU_INTERRUPT_INIT) );
 270             return;
 271
 272         case APIC_DM_EXTINT:
 273             /* handled in I/O APIC code */
 274             break;
 275
 276         default:
 277             return;
 278     }
 279
 280     foreach_apic(apic_iter, deliver_bitmask,
 281                  apic_set_irq(apic_iter, vector_num, trigger_mode) );
 282 }
 283
 284 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
 285                       uint8_t delivery_mode, uint8_t vector_num,
 286                       uint8_t polarity, uint8_t trigger_mode)
 287 {
 288     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 289
 290     trace_apic_deliver_irq(dest, dest_mode, delivery_mode, vector_num,
 291                            polarity, trigger_mode);
 292
 293     apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 294     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 295                      trigger_mode);
 296 }
 297
 298 void cpu_set_apic_base(DeviceState *d, uint64_t val)
 299 {
 300     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 301
 302     trace_cpu_set_apic_base(val);
 303
 304     if (!s)
 305         return;
 306     if (kvm_enabled() && kvm_irqchip_in_kernel())
 307         s->apicbase = val;
 308     else
 309         s->apicbase = (val & 0xfffff000) |
 310             (s->apicbase & (MSR_IA32_APICBASE_BSP | MSR_IA32_APICBASE_ENABLE));
 311     /* if disabled, cannot be enabled again */
 312     if (!(val & MSR_IA32_APICBASE_ENABLE)) {
 313         s->apicbase &= ~MSR_IA32_APICBASE_ENABLE;
 314         cpu_clear_apic_feature(s->cpu_env);
 315         s->spurious_vec &= ~APIC_SV_ENABLE;
 316     }
 317 }
 318
 319 uint64_t cpu_get_apic_base(DeviceState *d)
 320 {
 321     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 322
 323     trace_cpu_get_apic_base(s ? (uint64_t)s->apicbase: 0);
 324
 325     return s ? s->apicbase : 0;
 326 }
 327
 328 void cpu_set_apic_tpr(DeviceState *d, uint8_t val)
 329 {
 330     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 331
 332     if (!s)
 333         return;
 334     s->tpr = (val & 0x0f) << 4;
 335     apic_update_irq(s);
 336 }
 337
 338 uint8_t cpu_get_apic_tpr(DeviceState *d)
 339 {
 340     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 341
 342     return s ? s->tpr >> 4 : 0;
 343 }
 344
 345 /* return -1 if no bit is set */
 346 static int get_highest_priority_int(uint32_t *tab)
 347 {
 348     int i;
 349     for(i = 7; i >= 0; i--) {
 350         if (tab[i] != 0) {
 351             return i * 32 + fls_bit(tab[i]);
 352         }
 353     }
 354     return -1;
 355 }
 356
 357 static int apic_get_ppr(APICState *s)
 358 {
 359     int tpr, isrv, ppr;
 360
 361     tpr = (s->tpr >> 4);
 362     isrv = get_highest_priority_int(s->isr);
 363     if (isrv < 0)
 364         isrv = 0;
 365     isrv >>= 4;
 366     if (tpr >= isrv)
 367         ppr = s->tpr;
 368     else
 369         ppr = isrv << 4;
 370     return ppr;
 371 }
 372
 373 static int apic_get_arb_pri(APICState *s)
 374 {
 375     /* XXX: arbitration */
 376     return 0;
 377 }
 378
 379
 380 /*
 381  * <0 - low prio interrupt,
 382  * 0  - no interrupt,
 383  * >0 - interrupt number
 384  */
 385 static int apic_irq_pending(APICState *s)
 386 {
 387     int irrv, ppr;
 388     irrv = get_highest_priority_int(s->irr);
 389     if (irrv < 0) {
 390         return 0;
 391     }
 392     ppr = apic_get_ppr(s);
 393     if (ppr && (irrv & 0xf0) <= (ppr & 0xf0)) {
 394         return -1;
 395     }
 396
 397     return irrv;
 398 }
 399
 400 /* signal the CPU if an irq is pending */
 401 static void apic_update_irq(APICState *s)
 402 {
 403     if (!(s->spurious_vec & APIC_SV_ENABLE)) {
 404         return;
 405     }
 406     if (apic_irq_pending(s) > 0) {
 407         cpu_interrupt(s->cpu_env, CPU_INTERRUPT_HARD);
 408     }
 409 }
 410
 411 void apic_reset_irq_delivered(void)
 412 {
 413     trace_apic_reset_irq_delivered(apic_irq_delivered);
 414
 415     apic_irq_delivered = 0;
 416 }
 417
 418 int apic_get_irq_delivered(void)
 419 {
 420     trace_apic_get_irq_delivered(apic_irq_delivered);
 421
 422     return apic_irq_delivered;
 423 }
 424
 425 void apic_set_irq_delivered(void)
 426 {
 427     apic_irq_delivered = 1;
 428 }
 429
 430 static void apic_set_irq(APICState *s, int vector_num, int trigger_mode)
 431 {
 432     apic_irq_delivered += !get_bit(s->irr, vector_num);
 433
 434     trace_apic_set_irq(apic_irq_delivered);
 435
 436     set_bit(s->irr, vector_num);
 437     if (trigger_mode)
 438         set_bit(s->tmr, vector_num);
 439     else
 440         reset_bit(s->tmr, vector_num);
 441     apic_update_irq(s);
 442 }
 443
 444 static void apic_eoi(APICState *s)
 445 {
 446     int isrv;
 447     isrv = get_highest_priority_int(s->isr);
 448     if (isrv < 0)
 449         return;
 450     reset_bit(s->isr, isrv);
 451     if (!(s->spurious_vec & APIC_SV_DIRECTED_IO) && get_bit(s->tmr, isrv)) {
 452         ioapic_eoi_broadcast(isrv);
 453     }
 454     apic_update_irq(s);
 455 }
 456
 457 static int apic_find_dest(uint8_t dest)
 458 {
 459     APICState *apic = local_apics[dest];
 460     int i;
 461
 462     if (apic && apic->id == dest)
 463         return dest;  /* shortcut in case apic->id == apic->idx */
 464
 465     for (i = 0; i < MAX_APICS; i++) {
 466         apic = local_apics[i];
 467         if (apic && apic->id == dest)
 468             return i;
 469         if (!apic)
 470             break;
 471     }
 472
 473     return -1;
 474 }
 475
 476 static void apic_get_delivery_bitmask(uint32_t *deliver_bitmask,
 477                                       uint8_t dest, uint8_t dest_mode)
 478 {
 479     APICState *apic_iter;
 480     int i;
 481
 482     if (dest_mode == 0) {
 483         if (dest == 0xff) {
 484             memset(deliver_bitmask, 0xff, MAX_APIC_WORDS * sizeof(uint32_t));
 485         } else {
 486             int idx = apic_find_dest(dest);
 487             memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 488             if (idx >= 0)
 489                 set_bit(deliver_bitmask, idx);
 490         }
 491     } else {
 492         /* XXX: cluster mode */
 493         memset(deliver_bitmask, 0x00, MAX_APIC_WORDS * sizeof(uint32_t));
 494         for(i = 0; i < MAX_APICS; i++) {
 495             apic_iter = local_apics[i];
 496             if (apic_iter) {
 497                 if (apic_iter->dest_mode == 0xf) {
 498                     if (dest & apic_iter->log_dest)
 499                         set_bit(deliver_bitmask, i);
 500                 } else if (apic_iter->dest_mode == 0x0) {
 501                     if ((dest & 0xf0) == (apic_iter->log_dest & 0xf0) &&
 502                         (dest & apic_iter->log_dest & 0x0f)) {
 503                         set_bit(deliver_bitmask, i);
 504                     }
 505                 }
 506             } else {
 507                 break;
 508             }
 509         }
 510     }
 511 }
 512
 513 void apic_init_reset(DeviceState *d)
 514 {
 515     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 516     int i;
 517
 518     if (!s)
 519         return;
 520
 521     s->tpr = 0;
 522     s->spurious_vec = 0xff;
 523     s->log_dest = 0;
 524     s->dest_mode = 0xf;
 525     memset(s->isr, 0, sizeof(s->isr));
 526     memset(s->tmr, 0, sizeof(s->tmr));
 527     memset(s->irr, 0, sizeof(s->irr));
 528     for(i = 0; i < APIC_LVT_NB; i++)
 529         s->lvt[i] = 1 << 16; /* mask LVT */
 530     s->esr = 0;
 531     memset(s->icr, 0, sizeof(s->icr));
 532     s->divide_conf = 0;
 533     s->count_shift = 0;
 534     s->initial_count = 0;
 535     s->initial_count_load_time = 0;
 536     s->next_time = 0;
 537     s->wait_for_sipi = 1;
 538 }
 539
 540 static void apic_startup(APICState *s, int vector_num)
 541 {
 542     s->sipi_vector = vector_num;
 543     cpu_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
 544 }
 545
 546 void apic_sipi(DeviceState *d)
 547 {
 548     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 549
 550     cpu_reset_interrupt(s->cpu_env, CPU_INTERRUPT_SIPI);
 551
 552     if (!s->wait_for_sipi)
 553         return;
 554     cpu_x86_load_seg_cache_sipi(s->cpu_env, s->sipi_vector);
 555     s->wait_for_sipi = 0;
 556 }
 557
 558 static void apic_deliver(DeviceState *d, uint8_t dest, uint8_t dest_mode,
 559                          uint8_t delivery_mode, uint8_t vector_num,
 560                          uint8_t polarity, uint8_t trigger_mode)
 561 {
 562     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 563     uint32_t deliver_bitmask[MAX_APIC_WORDS];
 564     int dest_shorthand = (s->icr[0] >> 18) & 3;
 565     APICState *apic_iter;
 566
 567     switch (dest_shorthand) {
 568     case 0:
 569         apic_get_delivery_bitmask(deliver_bitmask, dest, dest_mode);
 570         break;
 571     case 1:
 572         memset(deliver_bitmask, 0x00, sizeof(deliver_bitmask));
 573         set_bit(deliver_bitmask, s->idx);
 574         break;
 575     case 2:
 576         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 577         break;
 578     case 3:
 579         memset(deliver_bitmask, 0xff, sizeof(deliver_bitmask));
 580         reset_bit(deliver_bitmask, s->idx);
 581         break;
 582     }
 583
 584     switch (delivery_mode) {
 585         case APIC_DM_INIT:
 586             {
 587                 int trig_mode = (s->icr[0] >> 15) & 1;
 588                 int level = (s->icr[0] >> 14) & 1;
 589                 if (level == 0 && trig_mode == 1) {
 590                     foreach_apic(apic_iter, deliver_bitmask,
 591                                  apic_iter->arb_id = apic_iter->id );
 592                     return;
 593                 }
 594             }
 595             break;
 596
 597         case APIC_DM_SIPI:
 598             foreach_apic(apic_iter, deliver_bitmask,
 599                          apic_startup(apic_iter, vector_num) );
 600             return;
 601     }
 602
 603     apic_bus_deliver(deliver_bitmask, delivery_mode, vector_num, polarity,
 604                      trigger_mode);
 605 }
 606
 607 int apic_get_interrupt(DeviceState *d)
 608 {
 609     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 610     int intno;
 611
 612     /* if the APIC is installed or enabled, we let the 8259 handle the
 613        IRQs */
 614     if (!s)
 615         return -1;
 616     if (!(s->spurious_vec & APIC_SV_ENABLE))
 617         return -1;
 618
 619     intno = apic_irq_pending(s);
 620
 621     if (intno == 0) {
 622         return -1;
 623     } else if (intno < 0) {
 624         return s->spurious_vec & 0xff;
 625     }
 626     reset_bit(s->irr, intno);
 627     set_bit(s->isr, intno);
 628     apic_update_irq(s);
 629     return intno;
 630 }
 631
 632 int apic_accept_pic_intr(DeviceState *d)
 633 {
 634     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
 635     uint32_t lvt0;
 636
 637     if (!s)
 638         return -1;
 639
 640     lvt0 = s->lvt[APIC_LVT_LINT0];
 641
 642     if ((s->apicbase & MSR_IA32_APICBASE_ENABLE) == 0 ||
 643         (lvt0 & APIC_LVT_MASKED) == 0)
 644         return 1;
 645
 646     return 0;
 647 }
 648
 649 static uint32_t apic_get_current_count(APICState *s)
 650 {
 651     int64_t d;
 652     uint32_t val;
 653     d = (qemu_get_clock_ns(vm_clock) - s->initial_count_load_time) >>
 654         s->count_shift;
 655     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 656         /* periodic */
 657         val = s->initial_count - (d % ((uint64_t)s->initial_count + 1));
 658     } else {
 659         if (d >= s->initial_count)
 660             val = 0;
 661         else
 662             val = s->initial_count - d;
 663     }
 664     return val;
 665 }
 666
 667 static void apic_timer_update(APICState *s, int64_t current_time)
 668 {
 669     int64_t next_time, d;
 670
 671     if (!(s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED)) {
 672         d = (current_time - s->initial_count_load_time) >>
 673             s->count_shift;
 674         if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 675             if (!s->initial_count)
 676                 goto no_timer;
 677             d = ((d / ((uint64_t)s->initial_count + 1)) + 1) * ((uint64_t)s->initial_count + 1);
 678         } else {
 679             if (d >= s->initial_count)
 680                 goto no_timer;
 681             d = (uint64_t)s->initial_count + 1;
 682         }
 683         next_time = s->initial_count_load_time + (d << s->count_shift);
 684         qemu_mod_timer(s->timer, next_time);
 685         s->next_time = next_time;
 686     } else {
 687     no_timer:
 688         qemu_del_timer(s->timer);
 689     }
 690 }
 691
 692 static void apic_timer(void *opaque)
 693 {
 694     APICState *s = opaque;
 695
 696     apic_local_deliver(s, APIC_LVT_TIMER);
 697     apic_timer_update(s, s->next_time);
 698 }
 699
 700 static uint32_t apic_mem_readb(void *opaque, target_phys_addr_t addr)
 701 {
 702     return 0;
 703 }
 704
 705 static uint32_t apic_mem_readw(void *opaque, target_phys_addr_t addr)
 706 {
 707     return 0;
 708 }
 709
 710 static void apic_mem_writeb(void *opaque, target_phys_addr_t addr, uint32_t val)
 711 {
 712 }
 713
 714 static void apic_mem_writew(void *opaque, target_phys_addr_t addr, uint32_t val)
 715 {
 716 }
 717
 718 static uint32_t apic_mem_readl(void *opaque, target_phys_addr_t addr)
 719 {
 720     DeviceState *d;
 721     APICState *s;
 722     uint32_t val;
 723     int index;
 724
 725     d = cpu_get_current_apic();
 726     if (!d) {
 727         return 0;
 728     }
 729     s = DO_UPCAST(APICState, busdev.qdev, d);
 730
 731     index = (addr >> 4) & 0xff;
 732     switch(index) {
 733     case 0x02: /* id */
 734         val = s->id << 24;
 735         break;
 736     case 0x03: /* version */
 737         val = 0x11 | ((APIC_LVT_NB - 1) << 16); /* version 0x11 */
 738         break;
 739     case 0x08:
 740         val = s->tpr;
 741         break;
 742     case 0x09:
 743         val = apic_get_arb_pri(s);
 744         break;
 745     case 0x0a:
 746         /* ppr */
 747         val = apic_get_ppr(s);
 748         break;
 749     case 0x0b:
 750         val = 0;
 751         break;
 752     case 0x0d:
 753         val = s->log_dest << 24;
 754         break;
 755     case 0x0e:
 756         val = s->dest_mode << 28;
 757         break;
 758     case 0x0f:
 759         val = s->spurious_vec;
 760         break;
 761     case 0x10 ... 0x17:
 762         val = s->isr[index & 7];
 763         break;
 764     case 0x18 ... 0x1f:
 765         val = s->tmr[index & 7];
 766         break;
 767     case 0x20 ... 0x27:
 768         val = s->irr[index & 7];
 769         break;
 770     case 0x28:
 771         val = s->esr;
 772         break;
 773     case 0x30:
 774     case 0x31:
 775         val = s->icr[index & 1];
 776         break;
 777     case 0x32 ... 0x37:
 778         val = s->lvt[index - 0x32];
 779         break;
 780     case 0x38:
 781         val = s->initial_count;
 782         break;
 783     case 0x39:
 784         val = apic_get_current_count(s);
 785         break;
 786     case 0x3e:
 787         val = s->divide_conf;
 788         break;
 789     default:
 790         s->esr |= ESR_ILLEGAL_ADDRESS;
 791         val = 0;
 792         break;
 793     }
 794     trace_apic_mem_readl(addr, val);
 795     return val;
 796 }
 797
 798 static void apic_send_msi(target_phys_addr_t addr, uint32_t data)
 799 {
 800     uint8_t dest = (addr & MSI_ADDR_DEST_ID_MASK) >> MSI_ADDR_DEST_ID_SHIFT;
 801     uint8_t vector = (data & MSI_DATA_VECTOR_MASK) >> MSI_DATA_VECTOR_SHIFT;
 802     uint8_t dest_mode = (addr >> MSI_ADDR_DEST_MODE_SHIFT) & 0x1;
 803     uint8_t trigger_mode = (data >> MSI_DATA_TRIGGER_SHIFT) & 0x1;
 804     uint8_t delivery = (data >> MSI_DATA_DELIVERY_MODE_SHIFT) & 0x7;
 805     /* XXX: Ignore redirection hint. */
 806     apic_deliver_irq(dest, dest_mode, delivery, vector, 0, trigger_mode);
 807 }
 808
 809 static void apic_mem_writel(void *opaque, target_phys_addr_t addr, uint32_t val)
 810 {
 811     DeviceState *d;
 812     APICState *s;
 813     int index = (addr >> 4) & 0xff;
 814     if (addr > 0xfff || !index) {
 815         /* MSI and MMIO APIC are at the same memory location,
 816          * but actually not on the global bus: MSI is on PCI bus
 817          * APIC is connected directly to the CPU.
 818          * Mapping them on the global bus happens to work because
 819          * MSI registers are reserved in APIC MMIO and vice versa. */
 820         apic_send_msi(addr, val);
 821         return;
 822     }
 823
 824     d = cpu_get_current_apic();
 825     if (!d) {
 826         return;
 827     }
 828     s = DO_UPCAST(APICState, busdev.qdev, d);
 829
 830     trace_apic_mem_writel(addr, val);
 831
 832     switch(index) {
 833     case 0x02:
 834         s->id = (val >> 24);
 835         break;
 836     case 0x03:
 837         break;
 838     case 0x08:
 839         s->tpr = val;
 840         apic_update_irq(s);
 841         break;
 842     case 0x09:
 843     case 0x0a:
 844         break;
 845     case 0x0b: /* EOI */
 846         apic_eoi(s);
 847         break;
 848     case 0x0d:
 849         s->log_dest = val >> 24;
 850         break;
 851     case 0x0e:
 852         s->dest_mode = val >> 28;
 853         break;
 854     case 0x0f:
 855         s->spurious_vec = val & 0x1ff;
 856         apic_update_irq(s);
 857         break;
 858     case 0x10 ... 0x17:
 859     case 0x18 ... 0x1f:
 860     case 0x20 ... 0x27:
 861     case 0x28:
 862         break;
 863     case 0x30:
 864         s->icr[0] = val;
 865         apic_deliver(d, (s->icr[1] >> 24) & 0xff, (s->icr[0] >> 11) & 1,
 866                      (s->icr[0] >> 8) & 7, (s->icr[0] & 0xff),
 867                      (s->icr[0] >> 14) & 1, (s->icr[0] >> 15) & 1);
 868         break;
 869     case 0x31:
 870         s->icr[1] = val;
 871         break;
 872     case 0x32 ... 0x37:
 873         {
 874             int n = index - 0x32;
 875             s->lvt[n] = val;
 876             if (n == APIC_LVT_TIMER)
 877                 apic_timer_update(s, qemu_get_clock_ns(vm_clock));
 878         }
 879         break;
 880     case 0x38:
 881         s->initial_count = val;
 882         s->initial_count_load_time = qemu_get_clock_ns(vm_clock);
 883         apic_timer_update(s, s->initial_count_load_time);
 884         break;
 885     case 0x39:
 886         break;
 887     case 0x3e:
 888         {
 889             int v;
 890             s->divide_conf = val & 0xb;
 891             v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 892             s->count_shift = (v + 1) & 7;
 893         }
 894         break;
 895     default:
 896         s->esr |= ESR_ILLEGAL_ADDRESS;
 897         break;
 898     }
 899 }
 900
 901 #ifdef KVM_CAP_IRQCHIP
 902
 903 static inline uint32_t kapic_reg(struct kvm_lapic_state *kapic, int reg_id)
 904 {
 905     return *((uint32_t *) (kapic->regs + (reg_id << 4)));
 906 }
 907
 908 static inline void kapic_set_reg(struct kvm_lapic_state *kapic,
 909                                  int reg_id, uint32_t val)
 910 {
 911     *((uint32_t *) (kapic->regs + (reg_id << 4))) = val;
 912 }
 913
 914 static void kvm_kernel_lapic_save_to_user(APICState *s)
 915 {
 916     struct kvm_lapic_state apic;
 917     struct kvm_lapic_state *kapic = &apic;
 918     int i, v;
 919
 920     kvm_get_lapic(s->cpu_env, kapic);
 921
 922     s->id = kapic_reg(kapic, 0x2) >> 24;
 923     s->tpr = kapic_reg(kapic, 0x8);
 924     s->arb_id = kapic_reg(kapic, 0x9);
 925     s->log_dest = kapic_reg(kapic, 0xd) >> 24;
 926     s->dest_mode = kapic_reg(kapic, 0xe) >> 28;
 927     s->spurious_vec = kapic_reg(kapic, 0xf);
 928     for (i = 0; i < 8; i++) {
 929         s->isr[i] = kapic_reg(kapic, 0x10 + i);
 930         s->tmr[i] = kapic_reg(kapic, 0x18 + i);
 931         s->irr[i] = kapic_reg(kapic, 0x20 + i);
 932     }
 933     s->esr = kapic_reg(kapic, 0x28);
 934     s->icr[0] = kapic_reg(kapic, 0x30);
 935     s->icr[1] = kapic_reg(kapic, 0x31);
 936     for (i = 0; i < APIC_LVT_NB; i++)
 937         s->lvt[i] = kapic_reg(kapic, 0x32 + i);
 938     s->initial_count = kapic_reg(kapic, 0x38);
 939     s->divide_conf = kapic_reg(kapic, 0x3e);
 940
 941     v = (s->divide_conf & 3) | ((s->divide_conf >> 1) & 4);
 942     s->count_shift = (v + 1) & 7;
 943
 944     s->initial_count_load_time = qemu_get_clock_ns(vm_clock);
 945     apic_timer_update(s, s->initial_count_load_time);
 946 }
 947
 948 static void kvm_kernel_lapic_load_from_user(APICState *s)
 949 {
 950     struct kvm_lapic_state apic;
 951     struct kvm_lapic_state *klapic = &apic;
 952     int i;
 953
 954     memset(klapic, 0, sizeof apic);
 955     kapic_set_reg(klapic, 0x2, s->id << 24);
 956     kapic_set_reg(klapic, 0x8, s->tpr);
 957     kapic_set_reg(klapic, 0xd, s->log_dest << 24);
 958     kapic_set_reg(klapic, 0xe, s->dest_mode << 28 | 0x0fffffff);
 959     kapic_set_reg(klapic, 0xf, s->spurious_vec);
 960     for (i = 0; i < 8; i++) {
 961         kapic_set_reg(klapic, 0x10 + i, s->isr[i]);
 962         kapic_set_reg(klapic, 0x18 + i, s->tmr[i]);
 963         kapic_set_reg(klapic, 0x20 + i, s->irr[i]);
 964     }
 965     kapic_set_reg(klapic, 0x28, s->esr);
 966     kapic_set_reg(klapic, 0x30, s->icr[0]);
 967     kapic_set_reg(klapic, 0x31, s->icr[1]);
 968     for (i = 0; i < APIC_LVT_NB; i++)
 969         kapic_set_reg(klapic, 0x32 + i, s->lvt[i]);
 970     kapic_set_reg(klapic, 0x38, s->initial_count);
 971     kapic_set_reg(klapic, 0x3e, s->divide_conf);
 972
 973     kvm_set_lapic(s->cpu_env, klapic);
 974 }
 975
 976 #endif
 977
 978 void kvm_load_lapic(CPUState *env)
 979 {
 980 #ifdef KVM_CAP_IRQCHIP
 981     APICState *s = DO_UPCAST(APICState, busdev.qdev, env->apic_state);
 982
 983     if (!s) {
 984         return;
 985     }
 986
 987     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
 988         kvm_kernel_lapic_load_from_user(s);
 989     }
 990 #endif
 991 }
 992
 993 void kvm_save_lapic(CPUState *env)
 994 {
 995 #ifdef KVM_CAP_IRQCHIP
 996     APICState *s = DO_UPCAST(APICState, busdev.qdev, env->apic_state);
 997
 998     if (!s) {
 999         return;
1000     }
1001
1002     if (kvm_enabled() && kvm_irqchip_in_kernel()) {
1003         kvm_kernel_lapic_save_to_user(s);
1004     }
1005 #endif
1006 }
1007
1008 /* This function is only used for old state version 1 and 2 */
1009 static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
1010 {
1011     APICState *s = opaque;
1012     int i;
1013
1014     if (version_id > 2)
1015         return -EINVAL;
1016
1017     /* XXX: what if the base changes? (registered memory regions) */
1018     qemu_get_be32s(f, &s->apicbase);
1019     qemu_get_8s(f, &s->id);
1020     qemu_get_8s(f, &s->arb_id);
1021     qemu_get_8s(f, &s->tpr);
1022     qemu_get_be32s(f, &s->spurious_vec);
1023     qemu_get_8s(f, &s->log_dest);
1024     qemu_get_8s(f, &s->dest_mode);
1025     for (i = 0; i < 8; i++) {
1026         qemu_get_be32s(f, &s->isr[i]);
1027         qemu_get_be32s(f, &s->tmr[i]);
1028         qemu_get_be32s(f, &s->irr[i]);
1029     }
1030     for (i = 0; i < APIC_LVT_NB; i++) {
1031         qemu_get_be32s(f, &s->lvt[i]);
1032     }
1033     qemu_get_be32s(f, &s->esr);
1034     qemu_get_be32s(f, &s->icr[0]);
1035     qemu_get_be32s(f, &s->icr[1]);
1036     qemu_get_be32s(f, &s->divide_conf);
1037     s->count_shift=qemu_get_be32(f);
1038     qemu_get_be32s(f, &s->initial_count);
1039     s->initial_count_load_time=qemu_get_be64(f);
1040     s->next_time=qemu_get_be64(f);
1041
1042     if (version_id >= 2)
1043         qemu_get_timer(f, s->timer);
1044     return 0;
1045 }
1046
1047 static const VMStateDescription vmstate_apic = {
1048     .name = "apic",
1049     .version_id = 3,
1050     .minimum_version_id = 3,
1051     .minimum_version_id_old = 1,
1052     .load_state_old = apic_load_old,
1053     .fields      = (VMStateField []) {
1054         VMSTATE_UINT32(apicbase, APICState),
1055         VMSTATE_UINT8(id, APICState),
1056         VMSTATE_UINT8(arb_id, APICState),
1057         VMSTATE_UINT8(tpr, APICState),
1058         VMSTATE_UINT32(spurious_vec, APICState),
1059         VMSTATE_UINT8(log_dest, APICState),
1060         VMSTATE_UINT8(dest_mode, APICState),
1061         VMSTATE_UINT32_ARRAY(isr, APICState, 8),
1062         VMSTATE_UINT32_ARRAY(tmr, APICState, 8),
1063         VMSTATE_UINT32_ARRAY(irr, APICState, 8),
1064         VMSTATE_UINT32_ARRAY(lvt, APICState, APIC_LVT_NB),
1065         VMSTATE_UINT32(esr, APICState),
1066         VMSTATE_UINT32_ARRAY(icr, APICState, 2),
1067         VMSTATE_UINT32(divide_conf, APICState),
1068         VMSTATE_INT32(count_shift, APICState),
1069         VMSTATE_UINT32(initial_count, APICState),
1070         VMSTATE_INT64(initial_count_load_time, APICState),
1071         VMSTATE_INT64(next_time, APICState),
1072         VMSTATE_TIMER(timer, APICState),
1073         VMSTATE_END_OF_LIST()
1074     }
1075 };
1076
1077 static void apic_reset(DeviceState *d)
1078 {
1079     APICState *s = DO_UPCAST(APICState, busdev.qdev, d);
1080     int bsp;
1081
1082     bsp = cpu_is_bsp(s->cpu_env);
1083     s->apicbase = 0xfee00000 |
1084         (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
1085
1086     apic_init_reset(d);
1087
1088     if (bsp) {
1089         /*
1090          * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
1091          * time typically by BIOS, so PIC interrupt can be delivered to the
1092          * processor when local APIC is enabled.
1093          */
1094         s->lvt[APIC_LVT_LINT0] = 0x700;
1095     }
1096 }
1097
1098 static CPUReadMemoryFunc * const apic_mem_read[3] = {
1099     apic_mem_readb,
1100     apic_mem_readw,
1101     apic_mem_readl,
1102 };
1103
1104 static CPUWriteMemoryFunc * const apic_mem_write[3] = {
1105     apic_mem_writeb,
1106     apic_mem_writew,
1107     apic_mem_writel,
1108 };
1109
1110 static int apic_init1(SysBusDevice *dev)
1111 {
1112     APICState *s = FROM_SYSBUS(APICState, dev);
1113     int apic_io_memory;
1114     static int last_apic_idx;
1115
1116     if (last_apic_idx >= MAX_APICS) {
1117         return -1;
1118     }
1119     apic_io_memory = cpu_register_io_memory(apic_mem_read,
1120                                             apic_mem_write, NULL,
1121                                             DEVICE_NATIVE_ENDIAN);
1122     sysbus_init_mmio(dev, MSI_ADDR_SIZE, apic_io_memory);
1123
1124     s->timer = qemu_new_timer_ns(vm_clock, apic_timer, s);
1125     s->idx = last_apic_idx++;
1126     local_apics[s->idx] = s;
1127     return 0;
1128 }
1129
1130 static SysBusDeviceInfo apic_info = {
1131     .init = apic_init1,
1132     .qdev.name = "apic",
1133     .qdev.size = sizeof(APICState),
1134     .qdev.vmsd = &vmstate_apic,
1135     .qdev.reset = apic_reset,
1136     .qdev.no_user = 1,
1137     .qdev.props = (Property[]) {
1138         DEFINE_PROP_UINT8("id", APICState, id, -1),
1139         DEFINE_PROP_PTR("cpu_env", APICState, cpu_env),
1140         DEFINE_PROP_END_OF_LIST(),
1141     }
1142 };
1143
1144 static void apic_register_devices(void)
1145 {
1146     sysbus_register_withprop(&apic_info);
1147 }
1148
1149 device_init(apic_register_devices)