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qemu-kvm: Merge kvm_context into KVMState
[qemu-kvm.git] / gdbstub.c
blobdf936916dd5fa5eadece9865ef329544987915d8
1 /*
2 * gdb server stub
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include "config.h"
20 #include "qemu-common.h"
21 #ifdef CONFIG_USER_ONLY
22 #include <stdlib.h>
23 #include <stdio.h>
24 #include <stdarg.h>
25 #include <string.h>
26 #include <errno.h>
27 #include <unistd.h>
28 #include <fcntl.h>
29
30 #include "qemu.h"
31 #else
32 #include "monitor.h"
33 #include "qemu-char.h"
34 #include "sysemu.h"
35 #include "gdbstub.h"
36 #endif
37 #include "qemu-kvm.h"
38
39 #define MAX_PACKET_LENGTH 4096
40
41 #include "exec-all.h"
42 #include "qemu_socket.h"
43 #include "kvm.h"
44
45
46 enum {
47 GDB_SIGNAL_0 = 0,
48 GDB_SIGNAL_INT = 2,
49 GDB_SIGNAL_QUIT = 3,
50 GDB_SIGNAL_TRAP = 5,
51 GDB_SIGNAL_ABRT = 6,
52 GDB_SIGNAL_ALRM = 14,
53 GDB_SIGNAL_IO = 23,
54 GDB_SIGNAL_XCPU = 24,
55 GDB_SIGNAL_UNKNOWN = 143
56 };
57
58 #ifdef CONFIG_USER_ONLY
59
60 /* Map target signal numbers to GDB protocol signal numbers and vice
61 * versa. For user emulation's currently supported systems, we can
62 * assume most signals are defined.
63 */
64
65 static int gdb_signal_table[] = {
66 0,
67 TARGET_SIGHUP,
68 TARGET_SIGINT,
69 TARGET_SIGQUIT,
70 TARGET_SIGILL,
71 TARGET_SIGTRAP,
72 TARGET_SIGABRT,
73 -1, /* SIGEMT */
74 TARGET_SIGFPE,
75 TARGET_SIGKILL,
76 TARGET_SIGBUS,
77 TARGET_SIGSEGV,
78 TARGET_SIGSYS,
79 TARGET_SIGPIPE,
80 TARGET_SIGALRM,
81 TARGET_SIGTERM,
82 TARGET_SIGURG,
83 TARGET_SIGSTOP,
84 TARGET_SIGTSTP,
85 TARGET_SIGCONT,
86 TARGET_SIGCHLD,
87 TARGET_SIGTTIN,
88 TARGET_SIGTTOU,
89 TARGET_SIGIO,
90 TARGET_SIGXCPU,
91 TARGET_SIGXFSZ,
92 TARGET_SIGVTALRM,
93 TARGET_SIGPROF,
94 TARGET_SIGWINCH,
95 -1, /* SIGLOST */
96 TARGET_SIGUSR1,
97 TARGET_SIGUSR2,
98 #ifdef TARGET_SIGPWR
99 TARGET_SIGPWR,
100 #else
101 -1,
102 #endif
103 -1, /* SIGPOLL */
104 -1,
105 -1,
106 -1,
107 -1,
108 -1,
109 -1,
110 -1,
111 -1,
112 -1,
113 -1,
114 -1,
115 #ifdef __SIGRTMIN
116 __SIGRTMIN + 1,
117 __SIGRTMIN + 2,
118 __SIGRTMIN + 3,
119 __SIGRTMIN + 4,
120 __SIGRTMIN + 5,
121 __SIGRTMIN + 6,
122 __SIGRTMIN + 7,
123 __SIGRTMIN + 8,
124 __SIGRTMIN + 9,
125 __SIGRTMIN + 10,
126 __SIGRTMIN + 11,
127 __SIGRTMIN + 12,
128 __SIGRTMIN + 13,
129 __SIGRTMIN + 14,
130 __SIGRTMIN + 15,
131 __SIGRTMIN + 16,
132 __SIGRTMIN + 17,
133 __SIGRTMIN + 18,
134 __SIGRTMIN + 19,
135 __SIGRTMIN + 20,
136 __SIGRTMIN + 21,
137 __SIGRTMIN + 22,
138 __SIGRTMIN + 23,
139 __SIGRTMIN + 24,
140 __SIGRTMIN + 25,
141 __SIGRTMIN + 26,
142 __SIGRTMIN + 27,
143 __SIGRTMIN + 28,
144 __SIGRTMIN + 29,
145 __SIGRTMIN + 30,
146 __SIGRTMIN + 31,
147 -1, /* SIGCANCEL */
148 __SIGRTMIN,
149 __SIGRTMIN + 32,
150 __SIGRTMIN + 33,
151 __SIGRTMIN + 34,
152 __SIGRTMIN + 35,
153 __SIGRTMIN + 36,
154 __SIGRTMIN + 37,
155 __SIGRTMIN + 38,
156 __SIGRTMIN + 39,
157 __SIGRTMIN + 40,
158 __SIGRTMIN + 41,
159 __SIGRTMIN + 42,
160 __SIGRTMIN + 43,
161 __SIGRTMIN + 44,
162 __SIGRTMIN + 45,
163 __SIGRTMIN + 46,
164 __SIGRTMIN + 47,
165 __SIGRTMIN + 48,
166 __SIGRTMIN + 49,
167 __SIGRTMIN + 50,
168 __SIGRTMIN + 51,
169 __SIGRTMIN + 52,
170 __SIGRTMIN + 53,
171 __SIGRTMIN + 54,
172 __SIGRTMIN + 55,
173 __SIGRTMIN + 56,
174 __SIGRTMIN + 57,
175 __SIGRTMIN + 58,
176 __SIGRTMIN + 59,
177 __SIGRTMIN + 60,
178 __SIGRTMIN + 61,
179 __SIGRTMIN + 62,
180 __SIGRTMIN + 63,
181 __SIGRTMIN + 64,
182 __SIGRTMIN + 65,
183 __SIGRTMIN + 66,
184 __SIGRTMIN + 67,
185 __SIGRTMIN + 68,
186 __SIGRTMIN + 69,
187 __SIGRTMIN + 70,
188 __SIGRTMIN + 71,
189 __SIGRTMIN + 72,
190 __SIGRTMIN + 73,
191 __SIGRTMIN + 74,
192 __SIGRTMIN + 75,
193 __SIGRTMIN + 76,
194 __SIGRTMIN + 77,
195 __SIGRTMIN + 78,
196 __SIGRTMIN + 79,
197 __SIGRTMIN + 80,
198 __SIGRTMIN + 81,
199 __SIGRTMIN + 82,
200 __SIGRTMIN + 83,
201 __SIGRTMIN + 84,
202 __SIGRTMIN + 85,
203 __SIGRTMIN + 86,
204 __SIGRTMIN + 87,
205 __SIGRTMIN + 88,
206 __SIGRTMIN + 89,
207 __SIGRTMIN + 90,
208 __SIGRTMIN + 91,
209 __SIGRTMIN + 92,
210 __SIGRTMIN + 93,
211 __SIGRTMIN + 94,
212 __SIGRTMIN + 95,
213 -1, /* SIGINFO */
214 -1, /* UNKNOWN */
215 -1, /* DEFAULT */
216 -1,
217 -1,
218 -1,
219 -1,
220 -1,
221 -1
222 #endif
223 };
224 #else
225 /* In system mode we only need SIGINT and SIGTRAP; other signals
226 are not yet supported. */
227
228 enum {
229 TARGET_SIGINT = 2,
230 TARGET_SIGTRAP = 5
231 };
232
233 static int gdb_signal_table[] = {
234 -1,
235 -1,
236 TARGET_SIGINT,
237 -1,
238 -1,
239 TARGET_SIGTRAP
240 };
241 #endif
242
243 #ifdef CONFIG_USER_ONLY
244 static int target_signal_to_gdb (int sig)
245 {
246 int i;
247 for (i = 0; i < ARRAY_SIZE (gdb_signal_table); i++)
248 if (gdb_signal_table[i] == sig)
249 return i;
250 return GDB_SIGNAL_UNKNOWN;
251 }
252 #endif
253
254 static int gdb_signal_to_target (int sig)
255 {
256 if (sig < ARRAY_SIZE (gdb_signal_table))
257 return gdb_signal_table[sig];
258 else
259 return -1;
260 }
261
262 //#define DEBUG_GDB
263
264 typedef struct GDBRegisterState {
265 int base_reg;
266 int num_regs;
267 gdb_reg_cb get_reg;
268 gdb_reg_cb set_reg;
269 const char *xml;
270 struct GDBRegisterState *next;
271 } GDBRegisterState;
272
273 enum RSState {
274 RS_INACTIVE,
275 RS_IDLE,
276 RS_GETLINE,
277 RS_CHKSUM1,
278 RS_CHKSUM2,
279 RS_SYSCALL,
280 };
281 typedef struct GDBState {
282 CPUState *c_cpu; /* current CPU for step/continue ops */
283 CPUState *g_cpu; /* current CPU for other ops */
284 CPUState *query_cpu; /* for q{f|s}ThreadInfo */
285 enum RSState state; /* parsing state */
286 char line_buf[MAX_PACKET_LENGTH];
287 int line_buf_index;
288 int line_csum;
289 uint8_t last_packet[MAX_PACKET_LENGTH + 4];
290 int last_packet_len;
291 int signal;
292 #ifdef CONFIG_USER_ONLY
293 int fd;
294 int running_state;
295 #else
296 CharDriverState *chr;
297 CharDriverState *mon_chr;
298 #endif
299 } GDBState;
300
301 /* By default use no IRQs and no timers while single stepping so as to
302 * make single stepping like an ICE HW step.
303 */
304 static int sstep_flags = SSTEP_ENABLE|SSTEP_NOIRQ|SSTEP_NOTIMER;
305
306 static GDBState *gdbserver_state;
307
308 /* This is an ugly hack to cope with both new and old gdb.
309 If gdb sends qXfer:features:read then assume we're talking to a newish
310 gdb that understands target descriptions. */
311 static int gdb_has_xml;
312
313 #ifdef CONFIG_USER_ONLY
314 /* XXX: This is not thread safe. Do we care? */
315 static int gdbserver_fd = -1;
316
317 static int get_char(GDBState *s)
318 {
319 uint8_t ch;
320 int ret;
321
322 for(;;) {
323 ret = recv(s->fd, &ch, 1, 0);
324 if (ret < 0) {
325 if (errno == ECONNRESET)
326 s->fd = -1;
327 if (errno != EINTR && errno != EAGAIN)
328 return -1;
329 } else if (ret == 0) {
330 close(s->fd);
331 s->fd = -1;
332 return -1;
333 } else {
334 break;
335 }
336 }
337 return ch;
338 }
339 #endif
340
341 static gdb_syscall_complete_cb gdb_current_syscall_cb;
342
343 static enum {
344 GDB_SYS_UNKNOWN,
345 GDB_SYS_ENABLED,
346 GDB_SYS_DISABLED,
347 } gdb_syscall_mode;
348
349 /* If gdb is connected when the first semihosting syscall occurs then use
350 remote gdb syscalls. Otherwise use native file IO. */
351 int use_gdb_syscalls(void)
352 {
353 if (gdb_syscall_mode == GDB_SYS_UNKNOWN) {
354 gdb_syscall_mode = (gdbserver_state ? GDB_SYS_ENABLED
355 : GDB_SYS_DISABLED);
356 }
357 return gdb_syscall_mode == GDB_SYS_ENABLED;
358 }
359
360 /* Resume execution. */
361 static inline void gdb_continue(GDBState *s)
362 {
363 #ifdef CONFIG_USER_ONLY
364 s->running_state = 1;
365 #else
366 vm_start();
367 #endif
368 }
369
370 static void put_buffer(GDBState *s, const uint8_t *buf, int len)
371 {
372 #ifdef CONFIG_USER_ONLY
373 int ret;
374
375 while (len > 0) {
376 ret = send(s->fd, buf, len, 0);
377 if (ret < 0) {
378 if (errno != EINTR && errno != EAGAIN)
379 return;
380 } else {
381 buf += ret;
382 len -= ret;
383 }
384 }
385 #else
386 qemu_chr_write(s->chr, buf, len);
387 #endif
388 }
389
390 static inline int fromhex(int v)
391 {
392 if (v >= '0' && v <= '9')
393 return v - '0';
394 else if (v >= 'A' && v <= 'F')
395 return v - 'A' + 10;
396 else if (v >= 'a' && v <= 'f')
397 return v - 'a' + 10;
398 else
399 return 0;
400 }
401
402 static inline int tohex(int v)
403 {
404 if (v < 10)
405 return v + '0';
406 else
407 return v - 10 + 'a';
408 }
409
410 static void memtohex(char *buf, const uint8_t *mem, int len)
411 {
412 int i, c;
413 char *q;
414 q = buf;
415 for(i = 0; i < len; i++) {
416 c = mem[i];
417 *q++ = tohex(c >> 4);
418 *q++ = tohex(c & 0xf);
419 }
420 *q = '\0';
421 }
422
423 static void hextomem(uint8_t *mem, const char *buf, int len)
424 {
425 int i;
426
427 for(i = 0; i < len; i++) {
428 mem[i] = (fromhex(buf[0]) << 4) | fromhex(buf[1]);
429 buf += 2;
430 }
431 }
432
433 /* return -1 if error, 0 if OK */
434 static int put_packet_binary(GDBState *s, const char *buf, int len)
435 {
436 int csum, i;
437 uint8_t *p;
438
439 for(;;) {
440 p = s->last_packet;
441 *(p++) = '$';
442 memcpy(p, buf, len);
443 p += len;
444 csum = 0;
445 for(i = 0; i < len; i++) {
446 csum += buf[i];
447 }
448 *(p++) = '#';
449 *(p++) = tohex((csum >> 4) & 0xf);
450 *(p++) = tohex((csum) & 0xf);
451
452 s->last_packet_len = p - s->last_packet;
453 put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
454
455 #ifdef CONFIG_USER_ONLY
456 i = get_char(s);
457 if (i < 0)
458 return -1;
459 if (i == '+')
460 break;
461 #else
462 break;
463 #endif
464 }
465 return 0;
466 }
467
468 /* return -1 if error, 0 if OK */
469 static int put_packet(GDBState *s, const char *buf)
470 {
471 #ifdef DEBUG_GDB
472 printf("reply='%s'\n", buf);
473 #endif
474
475 return put_packet_binary(s, buf, strlen(buf));
476 }
477
478 /* The GDB remote protocol transfers values in target byte order. This means
479 we can use the raw memory access routines to access the value buffer.
480 Conveniently, these also handle the case where the buffer is mis-aligned.
481 */
482 #define GET_REG8(val) do { \
483 stb_p(mem_buf, val); \
484 return 1; \
485 } while(0)
486 #define GET_REG16(val) do { \
487 stw_p(mem_buf, val); \
488 return 2; \
489 } while(0)
490 #define GET_REG32(val) do { \
491 stl_p(mem_buf, val); \
492 return 4; \
493 } while(0)
494 #define GET_REG64(val) do { \
495 stq_p(mem_buf, val); \
496 return 8; \
497 } while(0)
498
499 #if TARGET_LONG_BITS == 64
500 #define GET_REGL(val) GET_REG64(val)
501 #define ldtul_p(addr) ldq_p(addr)
502 #else
503 #define GET_REGL(val) GET_REG32(val)
504 #define ldtul_p(addr) ldl_p(addr)
505 #endif
506
507 #if defined(TARGET_I386)
508
509 #ifdef TARGET_X86_64
510 static const int gpr_map[16] = {
511 R_EAX, R_EBX, R_ECX, R_EDX, R_ESI, R_EDI, R_EBP, R_ESP,
512 8, 9, 10, 11, 12, 13, 14, 15
513 };
514 #else
515 #define gpr_map gpr_map32
516 #endif
517 static const int gpr_map32[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
518
519 #define NUM_CORE_REGS (CPU_NB_REGS * 2 + 25)
520
521 #define IDX_IP_REG CPU_NB_REGS
522 #define IDX_FLAGS_REG (IDX_IP_REG + 1)
523 #define IDX_SEG_REGS (IDX_FLAGS_REG + 1)
524 #define IDX_FP_REGS (IDX_SEG_REGS + 6)
525 #define IDX_XMM_REGS (IDX_FP_REGS + 16)
526 #define IDX_MXCSR_REG (IDX_XMM_REGS + CPU_NB_REGS)
527
528 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
529 {
530 if (n < CPU_NB_REGS) {
531 if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
532 GET_REG64(env->regs[gpr_map[n]]);
533 } else if (n < CPU_NB_REGS32) {
534 GET_REG32(env->regs[gpr_map32[n]]);
535 }
536 } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
537 #ifdef USE_X86LDOUBLE
538 /* FIXME: byteswap float values - after fixing fpregs layout. */
539 memcpy(mem_buf, &env->fpregs[n - IDX_FP_REGS], 10);
540 #else
541 memset(mem_buf, 0, 10);
542 #endif
543 return 10;
544 } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
545 n -= IDX_XMM_REGS;
546 if (n < CPU_NB_REGS32 ||
547 (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
548 stq_p(mem_buf, env->xmm_regs[n].XMM_Q(0));
549 stq_p(mem_buf + 8, env->xmm_regs[n].XMM_Q(1));
550 return 16;
551 }
552 } else {
553 switch (n) {
554 case IDX_IP_REG:
555 if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
556 GET_REG64(env->eip);
557 } else {
558 GET_REG32(env->eip);
559 }
560 case IDX_FLAGS_REG: GET_REG32(env->eflags);
561
562 case IDX_SEG_REGS: GET_REG32(env->segs[R_CS].selector);
563 case IDX_SEG_REGS + 1: GET_REG32(env->segs[R_SS].selector);
564 case IDX_SEG_REGS + 2: GET_REG32(env->segs[R_DS].selector);
565 case IDX_SEG_REGS + 3: GET_REG32(env->segs[R_ES].selector);
566 case IDX_SEG_REGS + 4: GET_REG32(env->segs[R_FS].selector);
567 case IDX_SEG_REGS + 5: GET_REG32(env->segs[R_GS].selector);
568
569 case IDX_FP_REGS + 8: GET_REG32(env->fpuc);
570 case IDX_FP_REGS + 9: GET_REG32((env->fpus & ~0x3800) |
571 (env->fpstt & 0x7) << 11);
572 case IDX_FP_REGS + 10: GET_REG32(0); /* ftag */
573 case IDX_FP_REGS + 11: GET_REG32(0); /* fiseg */
574 case IDX_FP_REGS + 12: GET_REG32(0); /* fioff */
575 case IDX_FP_REGS + 13: GET_REG32(0); /* foseg */
576 case IDX_FP_REGS + 14: GET_REG32(0); /* fooff */
577 case IDX_FP_REGS + 15: GET_REG32(0); /* fop */
578
579 case IDX_MXCSR_REG: GET_REG32(env->mxcsr);
580 }
581 }
582 return 0;
583 }
584
585 static int cpu_x86_gdb_load_seg(CPUState *env, int sreg, uint8_t *mem_buf)
586 {
587 uint16_t selector = ldl_p(mem_buf);
588
589 if (selector != env->segs[sreg].selector) {
590 #if defined(CONFIG_USER_ONLY)
591 cpu_x86_load_seg(env, sreg, selector);
592 #else
593 unsigned int limit, flags;
594 target_ulong base;
595
596 if (!(env->cr[0] & CR0_PE_MASK) || (env->eflags & VM_MASK)) {
597 base = selector << 4;
598 limit = 0xffff;
599 flags = 0;
600 } else {
601 if (!cpu_x86_get_descr_debug(env, selector, &base, &limit, &flags))
602 return 4;
603 }
604 cpu_x86_load_seg_cache(env, sreg, selector, base, limit, flags);
605 #endif
606 }
607 return 4;
608 }
609
610 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
611 {
612 uint32_t tmp;
613
614 if (n < CPU_NB_REGS) {
615 if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
616 env->regs[gpr_map[n]] = ldtul_p(mem_buf);
617 return sizeof(target_ulong);
618 } else if (n < CPU_NB_REGS32) {
619 n = gpr_map32[n];
620 env->regs[n] &= ~0xffffffffUL;
621 env->regs[n] |= (uint32_t)ldl_p(mem_buf);
622 return 4;
623 }
624 } else if (n >= IDX_FP_REGS && n < IDX_FP_REGS + 8) {
625 #ifdef USE_X86LDOUBLE
626 /* FIXME: byteswap float values - after fixing fpregs layout. */
627 memcpy(&env->fpregs[n - IDX_FP_REGS], mem_buf, 10);
628 #endif
629 return 10;
630 } else if (n >= IDX_XMM_REGS && n < IDX_XMM_REGS + CPU_NB_REGS) {
631 n -= IDX_XMM_REGS;
632 if (n < CPU_NB_REGS32 ||
633 (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK)) {
634 env->xmm_regs[n].XMM_Q(0) = ldq_p(mem_buf);
635 env->xmm_regs[n].XMM_Q(1) = ldq_p(mem_buf + 8);
636 return 16;
637 }
638 } else {
639 switch (n) {
640 case IDX_IP_REG:
641 if (TARGET_LONG_BITS == 64 && env->hflags & HF_CS64_MASK) {
642 env->eip = ldq_p(mem_buf);
643 return 8;
644 } else {
645 env->eip &= ~0xffffffffUL;
646 env->eip |= (uint32_t)ldl_p(mem_buf);
647 return 4;
648 }
649 case IDX_FLAGS_REG:
650 env->eflags = ldl_p(mem_buf);
651 return 4;
652
653 case IDX_SEG_REGS: return cpu_x86_gdb_load_seg(env, R_CS, mem_buf);
654 case IDX_SEG_REGS + 1: return cpu_x86_gdb_load_seg(env, R_SS, mem_buf);
655 case IDX_SEG_REGS + 2: return cpu_x86_gdb_load_seg(env, R_DS, mem_buf);
656 case IDX_SEG_REGS + 3: return cpu_x86_gdb_load_seg(env, R_ES, mem_buf);
657 case IDX_SEG_REGS + 4: return cpu_x86_gdb_load_seg(env, R_FS, mem_buf);
658 case IDX_SEG_REGS + 5: return cpu_x86_gdb_load_seg(env, R_GS, mem_buf);
659
660 case IDX_FP_REGS + 8:
661 env->fpuc = ldl_p(mem_buf);
662 return 4;
663 case IDX_FP_REGS + 9:
664 tmp = ldl_p(mem_buf);
665 env->fpstt = (tmp >> 11) & 7;
666 env->fpus = tmp & ~0x3800;
667 return 4;
668 case IDX_FP_REGS + 10: /* ftag */ return 4;
669 case IDX_FP_REGS + 11: /* fiseg */ return 4;
670 case IDX_FP_REGS + 12: /* fioff */ return 4;
671 case IDX_FP_REGS + 13: /* foseg */ return 4;
672 case IDX_FP_REGS + 14: /* fooff */ return 4;
673 case IDX_FP_REGS + 15: /* fop */ return 4;
674
675 case IDX_MXCSR_REG:
676 env->mxcsr = ldl_p(mem_buf);
677 return 4;
678 }
679 }
680 /* Unrecognised register. */
681 return 0;
682 }
683
684 #elif defined (TARGET_PPC)
685
686 /* Old gdb always expects FP registers. Newer (xml-aware) gdb only
687 expects whatever the target description contains. Due to a
688 historical mishap the FP registers appear in between core integer
689 regs and PC, MSR, CR, and so forth. We hack round this by giving the
690 FP regs zero size when talking to a newer gdb. */
691 #define NUM_CORE_REGS 71
692 #if defined (TARGET_PPC64)
693 #define GDB_CORE_XML "power64-core.xml"
694 #else
695 #define GDB_CORE_XML "power-core.xml"
696 #endif
697
698 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
699 {
700 if (n < 32) {
701 /* gprs */
702 GET_REGL(env->gpr[n]);
703 } else if (n < 64) {
704 /* fprs */
705 if (gdb_has_xml)
706 return 0;
707 stfq_p(mem_buf, env->fpr[n-32]);
708 return 8;
709 } else {
710 switch (n) {
711 case 64: GET_REGL(env->nip);
712 case 65: GET_REGL(env->msr);
713 case 66:
714 {
715 uint32_t cr = 0;
716 int i;
717 for (i = 0; i < 8; i++)
718 cr |= env->crf[i] << (32 - ((i + 1) * 4));
719 GET_REG32(cr);
720 }
721 case 67: GET_REGL(env->lr);
722 case 68: GET_REGL(env->ctr);
723 case 69: GET_REGL(env->xer);
724 case 70:
725 {
726 if (gdb_has_xml)
727 return 0;
728 GET_REG32(0); /* fpscr */
729 }
730 }
731 }
732 return 0;
733 }
734
735 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
736 {
737 if (n < 32) {
738 /* gprs */
739 env->gpr[n] = ldtul_p(mem_buf);
740 return sizeof(target_ulong);
741 } else if (n < 64) {
742 /* fprs */
743 if (gdb_has_xml)
744 return 0;
745 env->fpr[n-32] = ldfq_p(mem_buf);
746 return 8;
747 } else {
748 switch (n) {
749 case 64:
750 env->nip = ldtul_p(mem_buf);
751 return sizeof(target_ulong);
752 case 65:
753 ppc_store_msr(env, ldtul_p(mem_buf));
754 return sizeof(target_ulong);
755 case 66:
756 {
757 uint32_t cr = ldl_p(mem_buf);
758 int i;
759 for (i = 0; i < 8; i++)
760 env->crf[i] = (cr >> (32 - ((i + 1) * 4))) & 0xF;
761 return 4;
762 }
763 case 67:
764 env->lr = ldtul_p(mem_buf);
765 return sizeof(target_ulong);
766 case 68:
767 env->ctr = ldtul_p(mem_buf);
768 return sizeof(target_ulong);
769 case 69:
770 env->xer = ldtul_p(mem_buf);
771 return sizeof(target_ulong);
772 case 70:
773 /* fpscr */
774 if (gdb_has_xml)
775 return 0;
776 return 4;
777 }
778 }
779 return 0;
780 }
781
782 #elif defined (TARGET_SPARC)
783
784 #if defined(TARGET_SPARC64) && !defined(TARGET_ABI32)
785 #define NUM_CORE_REGS 86
786 #else
787 #define NUM_CORE_REGS 72
788 #endif
789
790 #ifdef TARGET_ABI32
791 #define GET_REGA(val) GET_REG32(val)
792 #else
793 #define GET_REGA(val) GET_REGL(val)
794 #endif
795
796 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
797 {
798 if (n < 8) {
799 /* g0..g7 */
800 GET_REGA(env->gregs[n]);
801 }
802 if (n < 32) {
803 /* register window */
804 GET_REGA(env->regwptr[n - 8]);
805 }
806 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
807 if (n < 64) {
808 /* fprs */
809 GET_REG32(*((uint32_t *)&env->fpr[n - 32]));
810 }
811 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
812 switch (n) {
813 case 64: GET_REGA(env->y);
814 case 65: GET_REGA(cpu_get_psr(env));
815 case 66: GET_REGA(env->wim);
816 case 67: GET_REGA(env->tbr);
817 case 68: GET_REGA(env->pc);
818 case 69: GET_REGA(env->npc);
819 case 70: GET_REGA(env->fsr);
820 case 71: GET_REGA(0); /* csr */
821 default: GET_REGA(0);
822 }
823 #else
824 if (n < 64) {
825 /* f0-f31 */
826 GET_REG32(*((uint32_t *)&env->fpr[n - 32]));
827 }
828 if (n < 80) {
829 /* f32-f62 (double width, even numbers only) */
830 uint64_t val;
831
832 val = (uint64_t)*((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) << 32;
833 val |= *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]);
834 GET_REG64(val);
835 }
836 switch (n) {
837 case 80: GET_REGL(env->pc);
838 case 81: GET_REGL(env->npc);
839 case 82: GET_REGL((cpu_get_ccr(env) << 32) |
840 ((env->asi & 0xff) << 24) |
841 ((env->pstate & 0xfff) << 8) |
842 cpu_get_cwp64(env));
843 case 83: GET_REGL(env->fsr);
844 case 84: GET_REGL(env->fprs);
845 case 85: GET_REGL(env->y);
846 }
847 #endif
848 return 0;
849 }
850
851 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
852 {
853 #if defined(TARGET_ABI32)
854 abi_ulong tmp;
855
856 tmp = ldl_p(mem_buf);
857 #else
858 target_ulong tmp;
859
860 tmp = ldtul_p(mem_buf);
861 #endif
862
863 if (n < 8) {
864 /* g0..g7 */
865 env->gregs[n] = tmp;
866 } else if (n < 32) {
867 /* register window */
868 env->regwptr[n - 8] = tmp;
869 }
870 #if defined(TARGET_ABI32) || !defined(TARGET_SPARC64)
871 else if (n < 64) {
872 /* fprs */
873 *((uint32_t *)&env->fpr[n - 32]) = tmp;
874 } else {
875 /* Y, PSR, WIM, TBR, PC, NPC, FPSR, CPSR */
876 switch (n) {
877 case 64: env->y = tmp; break;
878 case 65: cpu_put_psr(env, tmp); break;
879 case 66: env->wim = tmp; break;
880 case 67: env->tbr = tmp; break;
881 case 68: env->pc = tmp; break;
882 case 69: env->npc = tmp; break;
883 case 70: env->fsr = tmp; break;
884 default: return 0;
885 }
886 }
887 return 4;
888 #else
889 else if (n < 64) {
890 /* f0-f31 */
891 env->fpr[n] = ldfl_p(mem_buf);
892 return 4;
893 } else if (n < 80) {
894 /* f32-f62 (double width, even numbers only) */
895 *((uint32_t *)&env->fpr[(n - 64) * 2 + 32]) = tmp >> 32;
896 *((uint32_t *)&env->fpr[(n - 64) * 2 + 33]) = tmp;
897 } else {
898 switch (n) {
899 case 80: env->pc = tmp; break;
900 case 81: env->npc = tmp; break;
901 case 82:
902 cpu_put_ccr(env, tmp >> 32);
903 env->asi = (tmp >> 24) & 0xff;
904 env->pstate = (tmp >> 8) & 0xfff;
905 cpu_put_cwp64(env, tmp & 0xff);
906 break;
907 case 83: env->fsr = tmp; break;
908 case 84: env->fprs = tmp; break;
909 case 85: env->y = tmp; break;
910 default: return 0;
911 }
912 }
913 return 8;
914 #endif
915 }
916 #elif defined (TARGET_ARM)
917
918 /* Old gdb always expect FPA registers. Newer (xml-aware) gdb only expect
919 whatever the target description contains. Due to a historical mishap
920 the FPA registers appear in between core integer regs and the CPSR.
921 We hack round this by giving the FPA regs zero size when talking to a
922 newer gdb. */
923 #define NUM_CORE_REGS 26
924 #define GDB_CORE_XML "arm-core.xml"
925
926 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
927 {
928 if (n < 16) {
929 /* Core integer register. */
930 GET_REG32(env->regs[n]);
931 }
932 if (n < 24) {
933 /* FPA registers. */
934 if (gdb_has_xml)
935 return 0;
936 memset(mem_buf, 0, 12);
937 return 12;
938 }
939 switch (n) {
940 case 24:
941 /* FPA status register. */
942 if (gdb_has_xml)
943 return 0;
944 GET_REG32(0);
945 case 25:
946 /* CPSR */
947 GET_REG32(cpsr_read(env));
948 }
949 /* Unknown register. */
950 return 0;
951 }
952
953 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
954 {
955 uint32_t tmp;
956
957 tmp = ldl_p(mem_buf);
958
959 /* Mask out low bit of PC to workaround gdb bugs. This will probably
960 cause problems if we ever implement the Jazelle DBX extensions. */
961 if (n == 15)
962 tmp &= ~1;
963
964 if (n < 16) {
965 /* Core integer register. */
966 env->regs[n] = tmp;
967 return 4;
968 }
969 if (n < 24) { /* 16-23 */
970 /* FPA registers (ignored). */
971 if (gdb_has_xml)
972 return 0;
973 return 12;
974 }
975 switch (n) {
976 case 24:
977 /* FPA status register (ignored). */
978 if (gdb_has_xml)
979 return 0;
980 return 4;
981 case 25:
982 /* CPSR */
983 cpsr_write (env, tmp, 0xffffffff);
984 return 4;
985 }
986 /* Unknown register. */
987 return 0;
988 }
989
990 #elif defined (TARGET_M68K)
991
992 #define NUM_CORE_REGS 18
993
994 #define GDB_CORE_XML "cf-core.xml"
995
996 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
997 {
998 if (n < 8) {
999 /* D0-D7 */
1000 GET_REG32(env->dregs[n]);
1001 } else if (n < 16) {
1002 /* A0-A7 */
1003 GET_REG32(env->aregs[n - 8]);
1004 } else {
1005 switch (n) {
1006 case 16: GET_REG32(env->sr);
1007 case 17: GET_REG32(env->pc);
1008 }
1009 }
1010 /* FP registers not included here because they vary between
1011 ColdFire and m68k. Use XML bits for these. */
1012 return 0;
1013 }
1014
1015 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1016 {
1017 uint32_t tmp;
1018
1019 tmp = ldl_p(mem_buf);
1020
1021 if (n < 8) {
1022 /* D0-D7 */
1023 env->dregs[n] = tmp;
1024 } else if (n < 16) {
1025 /* A0-A7 */
1026 env->aregs[n - 8] = tmp;
1027 } else {
1028 switch (n) {
1029 case 16: env->sr = tmp; break;
1030 case 17: env->pc = tmp; break;
1031 default: return 0;
1032 }
1033 }
1034 return 4;
1035 }
1036 #elif defined (TARGET_MIPS)
1037
1038 #define NUM_CORE_REGS 73
1039
1040 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1041 {
1042 if (n < 32) {
1043 GET_REGL(env->active_tc.gpr[n]);
1044 }
1045 if (env->CP0_Config1 & (1 << CP0C1_FP)) {
1046 if (n >= 38 && n < 70) {
1047 if (env->CP0_Status & (1 << CP0St_FR))
1048 GET_REGL(env->active_fpu.fpr[n - 38].d);
1049 else
1050 GET_REGL(env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX]);
1051 }
1052 switch (n) {
1053 case 70: GET_REGL((int32_t)env->active_fpu.fcr31);
1054 case 71: GET_REGL((int32_t)env->active_fpu.fcr0);
1055 }
1056 }
1057 switch (n) {
1058 case 32: GET_REGL((int32_t)env->CP0_Status);
1059 case 33: GET_REGL(env->active_tc.LO[0]);
1060 case 34: GET_REGL(env->active_tc.HI[0]);
1061 case 35: GET_REGL(env->CP0_BadVAddr);
1062 case 36: GET_REGL((int32_t)env->CP0_Cause);
1063 case 37: GET_REGL(env->active_tc.PC | !!(env->hflags & MIPS_HFLAG_M16));
1064 case 72: GET_REGL(0); /* fp */
1065 case 89: GET_REGL((int32_t)env->CP0_PRid);
1066 }
1067 if (n >= 73 && n <= 88) {
1068 /* 16 embedded regs. */
1069 GET_REGL(0);
1070 }
1071
1072 return 0;
1073 }
1074
1075 /* convert MIPS rounding mode in FCR31 to IEEE library */
1076 static unsigned int ieee_rm[] =
1077 {
1078 float_round_nearest_even,
1079 float_round_to_zero,
1080 float_round_up,
1081 float_round_down
1082 };
1083 #define RESTORE_ROUNDING_MODE \
1084 set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3], &env->active_fpu.fp_status)
1085
1086 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1087 {
1088 target_ulong tmp;
1089
1090 tmp = ldtul_p(mem_buf);
1091
1092 if (n < 32) {
1093 env->active_tc.gpr[n] = tmp;
1094 return sizeof(target_ulong);
1095 }
1096 if (env->CP0_Config1 & (1 << CP0C1_FP)
1097 && n >= 38 && n < 73) {
1098 if (n < 70) {
1099 if (env->CP0_Status & (1 << CP0St_FR))
1100 env->active_fpu.fpr[n - 38].d = tmp;
1101 else
1102 env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp;
1103 }
1104 switch (n) {
1105 case 70:
1106 env->active_fpu.fcr31 = tmp & 0xFF83FFFF;
1107 /* set rounding mode */
1108 RESTORE_ROUNDING_MODE;
1109 #ifndef CONFIG_SOFTFLOAT
1110 /* no floating point exception for native float */
1111 SET_FP_ENABLE(env->active_fpu.fcr31, 0);
1112 #endif
1113 break;
1114 case 71: env->active_fpu.fcr0 = tmp; break;
1115 }
1116 return sizeof(target_ulong);
1117 }
1118 switch (n) {
1119 case 32: env->CP0_Status = tmp; break;
1120 case 33: env->active_tc.LO[0] = tmp; break;
1121 case 34: env->active_tc.HI[0] = tmp; break;
1122 case 35: env->CP0_BadVAddr = tmp; break;
1123 case 36: env->CP0_Cause = tmp; break;
1124 case 37:
1125 env->active_tc.PC = tmp & ~(target_ulong)1;
1126 if (tmp & 1) {
1127 env->hflags |= MIPS_HFLAG_M16;
1128 } else {
1129 env->hflags &= ~(MIPS_HFLAG_M16);
1130 }
1131 break;
1132 case 72: /* fp, ignored */ break;
1133 default:
1134 if (n > 89)
1135 return 0;
1136 /* Other registers are readonly. Ignore writes. */
1137 break;
1138 }
1139
1140 return sizeof(target_ulong);
1141 }
1142 #elif defined (TARGET_SH4)
1143
1144 /* Hint: Use "set architecture sh4" in GDB to see fpu registers */
1145 /* FIXME: We should use XML for this. */
1146
1147 #define NUM_CORE_REGS 59
1148
1149 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1150 {
1151 if (n < 8) {
1152 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
1153 GET_REGL(env->gregs[n + 16]);
1154 } else {
1155 GET_REGL(env->gregs[n]);
1156 }
1157 } else if (n < 16) {
1158 GET_REGL(env->gregs[n]);
1159 } else if (n >= 25 && n < 41) {
1160 GET_REGL(env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)]);
1161 } else if (n >= 43 && n < 51) {
1162 GET_REGL(env->gregs[n - 43]);
1163 } else if (n >= 51 && n < 59) {
1164 GET_REGL(env->gregs[n - (51 - 16)]);
1165 }
1166 switch (n) {
1167 case 16: GET_REGL(env->pc);
1168 case 17: GET_REGL(env->pr);
1169 case 18: GET_REGL(env->gbr);
1170 case 19: GET_REGL(env->vbr);
1171 case 20: GET_REGL(env->mach);
1172 case 21: GET_REGL(env->macl);
1173 case 22: GET_REGL(env->sr);
1174 case 23: GET_REGL(env->fpul);
1175 case 24: GET_REGL(env->fpscr);
1176 case 41: GET_REGL(env->ssr);
1177 case 42: GET_REGL(env->spc);
1178 }
1179
1180 return 0;
1181 }
1182
1183 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1184 {
1185 uint32_t tmp;
1186
1187 tmp = ldl_p(mem_buf);
1188
1189 if (n < 8) {
1190 if ((env->sr & (SR_MD | SR_RB)) == (SR_MD | SR_RB)) {
1191 env->gregs[n + 16] = tmp;
1192 } else {
1193 env->gregs[n] = tmp;
1194 }
1195 return 4;
1196 } else if (n < 16) {
1197 env->gregs[n] = tmp;
1198 return 4;
1199 } else if (n >= 25 && n < 41) {
1200 env->fregs[(n - 25) + ((env->fpscr & FPSCR_FR) ? 16 : 0)] = tmp;
1201 return 4;
1202 } else if (n >= 43 && n < 51) {
1203 env->gregs[n - 43] = tmp;
1204 return 4;
1205 } else if (n >= 51 && n < 59) {
1206 env->gregs[n - (51 - 16)] = tmp;
1207 return 4;
1208 }
1209 switch (n) {
1210 case 16: env->pc = tmp; break;
1211 case 17: env->pr = tmp; break;
1212 case 18: env->gbr = tmp; break;
1213 case 19: env->vbr = tmp; break;
1214 case 20: env->mach = tmp; break;
1215 case 21: env->macl = tmp; break;
1216 case 22: env->sr = tmp; break;
1217 case 23: env->fpul = tmp; break;
1218 case 24: env->fpscr = tmp; break;
1219 case 41: env->ssr = tmp; break;
1220 case 42: env->spc = tmp; break;
1221 default: return 0;
1222 }
1223
1224 return 4;
1225 }
1226 #elif defined (TARGET_MICROBLAZE)
1227
1228 #define NUM_CORE_REGS (32 + 5)
1229
1230 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1231 {
1232 if (n < 32) {
1233 GET_REG32(env->regs[n]);
1234 } else {
1235 GET_REG32(env->sregs[n - 32]);
1236 }
1237 return 0;
1238 }
1239
1240 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1241 {
1242 uint32_t tmp;
1243
1244 if (n > NUM_CORE_REGS)
1245 return 0;
1246
1247 tmp = ldl_p(mem_buf);
1248
1249 if (n < 32) {
1250 env->regs[n] = tmp;
1251 } else {
1252 env->sregs[n - 32] = tmp;
1253 }
1254 return 4;
1255 }
1256 #elif defined (TARGET_CRIS)
1257
1258 #define NUM_CORE_REGS 49
1259
1260 static int
1261 read_register_crisv10(CPUState *env, uint8_t *mem_buf, int n)
1262 {
1263 if (n < 15) {
1264 GET_REG32(env->regs[n]);
1265 }
1266
1267 if (n == 15) {
1268 GET_REG32(env->pc);
1269 }
1270
1271 if (n < 32) {
1272 switch (n) {
1273 case 16:
1274 GET_REG8(env->pregs[n - 16]);
1275 break;
1276 case 17:
1277 GET_REG8(env->pregs[n - 16]);
1278 break;
1279 case 20:
1280 case 21:
1281 GET_REG16(env->pregs[n - 16]);
1282 break;
1283 default:
1284 if (n >= 23) {
1285 GET_REG32(env->pregs[n - 16]);
1286 }
1287 break;
1288 }
1289 }
1290 return 0;
1291 }
1292
1293 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1294 {
1295 uint8_t srs;
1296
1297 if (env->pregs[PR_VR] < 32)
1298 return read_register_crisv10(env, mem_buf, n);
1299
1300 srs = env->pregs[PR_SRS];
1301 if (n < 16) {
1302 GET_REG32(env->regs[n]);
1303 }
1304
1305 if (n >= 21 && n < 32) {
1306 GET_REG32(env->pregs[n - 16]);
1307 }
1308 if (n >= 33 && n < 49) {
1309 GET_REG32(env->sregs[srs][n - 33]);
1310 }
1311 switch (n) {
1312 case 16: GET_REG8(env->pregs[0]);
1313 case 17: GET_REG8(env->pregs[1]);
1314 case 18: GET_REG32(env->pregs[2]);
1315 case 19: GET_REG8(srs);
1316 case 20: GET_REG16(env->pregs[4]);
1317 case 32: GET_REG32(env->pc);
1318 }
1319
1320 return 0;
1321 }
1322
1323 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1324 {
1325 uint32_t tmp;
1326
1327 if (n > 49)
1328 return 0;
1329
1330 tmp = ldl_p(mem_buf);
1331
1332 if (n < 16) {
1333 env->regs[n] = tmp;
1334 }
1335
1336 if (n >= 21 && n < 32) {
1337 env->pregs[n - 16] = tmp;
1338 }
1339
1340 /* FIXME: Should support function regs be writable? */
1341 switch (n) {
1342 case 16: return 1;
1343 case 17: return 1;
1344 case 18: env->pregs[PR_PID] = tmp; break;
1345 case 19: return 1;
1346 case 20: return 2;
1347 case 32: env->pc = tmp; break;
1348 }
1349
1350 return 4;
1351 }
1352 #elif defined (TARGET_ALPHA)
1353
1354 #define NUM_CORE_REGS 67
1355
1356 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1357 {
1358 uint64_t val;
1359 CPU_DoubleU d;
1360
1361 switch (n) {
1362 case 0 ... 30:
1363 val = env->ir[n];
1364 break;
1365 case 32 ... 62:
1366 d.d = env->fir[n - 32];
1367 val = d.ll;
1368 break;
1369 case 63:
1370 val = cpu_alpha_load_fpcr(env);
1371 break;
1372 case 64:
1373 val = env->pc;
1374 break;
1375 case 66:
1376 val = env->unique;
1377 break;
1378 case 31:
1379 case 65:
1380 /* 31 really is the zero register; 65 is unassigned in the
1381 gdb protocol, but is still required to occupy 8 bytes. */
1382 val = 0;
1383 break;
1384 default:
1385 return 0;
1386 }
1387 GET_REGL(val);
1388 }
1389
1390 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1391 {
1392 target_ulong tmp = ldtul_p(mem_buf);
1393 CPU_DoubleU d;
1394
1395 switch (n) {
1396 case 0 ... 30:
1397 env->ir[n] = tmp;
1398 break;
1399 case 32 ... 62:
1400 d.ll = tmp;
1401 env->fir[n - 32] = d.d;
1402 break;
1403 case 63:
1404 cpu_alpha_store_fpcr(env, tmp);
1405 break;
1406 case 64:
1407 env->pc = tmp;
1408 break;
1409 case 66:
1410 env->unique = tmp;
1411 break;
1412 case 31:
1413 case 65:
1414 /* 31 really is the zero register; 65 is unassigned in the
1415 gdb protocol, but is still required to occupy 8 bytes. */
1416 break;
1417 default:
1418 return 0;
1419 }
1420 return 8;
1421 }
1422 #elif defined (TARGET_S390X)
1423
1424 #define NUM_CORE_REGS S390_NUM_TOTAL_REGS
1425
1426 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1427 {
1428 switch (n) {
1429 case S390_PSWM_REGNUM: GET_REGL(env->psw.mask); break;
1430 case S390_PSWA_REGNUM: GET_REGL(env->psw.addr); break;
1431 case S390_R0_REGNUM ... S390_R15_REGNUM:
1432 GET_REGL(env->regs[n-S390_R0_REGNUM]); break;
1433 case S390_A0_REGNUM ... S390_A15_REGNUM:
1434 GET_REG32(env->aregs[n-S390_A0_REGNUM]); break;
1435 case S390_FPC_REGNUM: GET_REG32(env->fpc); break;
1436 case S390_F0_REGNUM ... S390_F15_REGNUM:
1437 /* XXX */
1438 break;
1439 case S390_PC_REGNUM: GET_REGL(env->psw.addr); break;
1440 case S390_CC_REGNUM: GET_REG32(env->cc); break;
1441 }
1442
1443 return 0;
1444 }
1445
1446 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1447 {
1448 target_ulong tmpl;
1449 uint32_t tmp32;
1450 int r = 8;
1451 tmpl = ldtul_p(mem_buf);
1452 tmp32 = ldl_p(mem_buf);
1453
1454 switch (n) {
1455 case S390_PSWM_REGNUM: env->psw.mask = tmpl; break;
1456 case S390_PSWA_REGNUM: env->psw.addr = tmpl; break;
1457 case S390_R0_REGNUM ... S390_R15_REGNUM:
1458 env->regs[n-S390_R0_REGNUM] = tmpl; break;
1459 case S390_A0_REGNUM ... S390_A15_REGNUM:
1460 env->aregs[n-S390_A0_REGNUM] = tmp32; r=4; break;
1461 case S390_FPC_REGNUM: env->fpc = tmp32; r=4; break;
1462 case S390_F0_REGNUM ... S390_F15_REGNUM:
1463 /* XXX */
1464 break;
1465 case S390_PC_REGNUM: env->psw.addr = tmpl; break;
1466 case S390_CC_REGNUM: env->cc = tmp32; r=4; break;
1467 }
1468
1469 return r;
1470 }
1471 #elif defined (TARGET_LM32)
1472
1473 #include "hw/lm32_pic.h"
1474 #define NUM_CORE_REGS (32 + 7)
1475
1476 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1477 {
1478 if (n < 32) {
1479 GET_REG32(env->regs[n]);
1480 } else {
1481 switch (n) {
1482 case 32:
1483 GET_REG32(env->pc);
1484 break;
1485 /* FIXME: put in right exception ID */
1486 case 33:
1487 GET_REG32(0);
1488 break;
1489 case 34:
1490 GET_REG32(env->eba);
1491 break;
1492 case 35:
1493 GET_REG32(env->deba);
1494 break;
1495 case 36:
1496 GET_REG32(env->ie);
1497 break;
1498 case 37:
1499 GET_REG32(lm32_pic_get_im(env->pic_state));
1500 break;
1501 case 38:
1502 GET_REG32(lm32_pic_get_ip(env->pic_state));
1503 break;
1504 }
1505 }
1506 return 0;
1507 }
1508
1509 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1510 {
1511 uint32_t tmp;
1512
1513 if (n > NUM_CORE_REGS) {
1514 return 0;
1515 }
1516
1517 tmp = ldl_p(mem_buf);
1518
1519 if (n < 32) {
1520 env->regs[n] = tmp;
1521 } else {
1522 switch (n) {
1523 case 32:
1524 env->pc = tmp;
1525 break;
1526 case 34:
1527 env->eba = tmp;
1528 break;
1529 case 35:
1530 env->deba = tmp;
1531 break;
1532 case 36:
1533 env->ie = tmp;
1534 break;
1535 case 37:
1536 lm32_pic_set_im(env->pic_state, tmp);
1537 break;
1538 case 38:
1539 lm32_pic_set_ip(env->pic_state, tmp);
1540 break;
1541 }
1542 }
1543 return 4;
1544 }
1545 #else
1546
1547 #define NUM_CORE_REGS 0
1548
1549 static int cpu_gdb_read_register(CPUState *env, uint8_t *mem_buf, int n)
1550 {
1551 return 0;
1552 }
1553
1554 static int cpu_gdb_write_register(CPUState *env, uint8_t *mem_buf, int n)
1555 {
1556 return 0;
1557 }
1558
1559 #endif
1560
1561 static int num_g_regs = NUM_CORE_REGS;
1562
1563 #ifdef GDB_CORE_XML
1564 /* Encode data using the encoding for 'x' packets. */
1565 static int memtox(char *buf, const char *mem, int len)
1566 {
1567 char *p = buf;
1568 char c;
1569
1570 while (len--) {
1571 c = *(mem++);
1572 switch (c) {
1573 case '#': case '$': case '*': case '}':
1574 *(p++) = '}';
1575 *(p++) = c ^ 0x20;
1576 break;
1577 default:
1578 *(p++) = c;
1579 break;
1580 }
1581 }
1582 return p - buf;
1583 }
1584
1585 static const char *get_feature_xml(const char *p, const char **newp)
1586 {
1587 size_t len;
1588 int i;
1589 const char *name;
1590 static char target_xml[1024];
1591
1592 len = 0;
1593 while (p[len] && p[len] != ':')
1594 len++;
1595 *newp = p + len;
1596
1597 name = NULL;
1598 if (strncmp(p, "target.xml", len) == 0) {
1599 /* Generate the XML description for this CPU. */
1600 if (!target_xml[0]) {
1601 GDBRegisterState *r;
1602
1603 snprintf(target_xml, sizeof(target_xml),
1604 "<?xml version=\"1.0\"?>"
1605 "<!DOCTYPE target SYSTEM \"gdb-target.dtd\">"
1606 "<target>"
1607 "<xi:include href=\"%s\"/>",
1608 GDB_CORE_XML);
1609
1610 for (r = first_cpu->gdb_regs; r; r = r->next) {
1611 pstrcat(target_xml, sizeof(target_xml), "<xi:include href=\"");
1612 pstrcat(target_xml, sizeof(target_xml), r->xml);
1613 pstrcat(target_xml, sizeof(target_xml), "\"/>");
1614 }
1615 pstrcat(target_xml, sizeof(target_xml), "</target>");
1616 }
1617 return target_xml;
1618 }
1619 for (i = 0; ; i++) {
1620 name = xml_builtin[i][0];
1621 if (!name || (strncmp(name, p, len) == 0 && strlen(name) == len))
1622 break;
1623 }
1624 return name ? xml_builtin[i][1] : NULL;
1625 }
1626 #endif
1627
1628 static int gdb_read_register(CPUState *env, uint8_t *mem_buf, int reg)
1629 {
1630 GDBRegisterState *r;
1631
1632 if (reg < NUM_CORE_REGS)
1633 return cpu_gdb_read_register(env, mem_buf, reg);
1634
1635 for (r = env->gdb_regs; r; r = r->next) {
1636 if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1637 return r->get_reg(env, mem_buf, reg - r->base_reg);
1638 }
1639 }
1640 return 0;
1641 }
1642
1643 static int gdb_write_register(CPUState *env, uint8_t *mem_buf, int reg)
1644 {
1645 GDBRegisterState *r;
1646
1647 if (reg < NUM_CORE_REGS)
1648 return cpu_gdb_write_register(env, mem_buf, reg);
1649
1650 for (r = env->gdb_regs; r; r = r->next) {
1651 if (r->base_reg <= reg && reg < r->base_reg + r->num_regs) {
1652 return r->set_reg(env, mem_buf, reg - r->base_reg);
1653 }
1654 }
1655 return 0;
1656 }
1657
1658 /* Register a supplemental set of CPU registers. If g_pos is nonzero it
1659 specifies the first register number and these registers are included in
1660 a standard "g" packet. Direction is relative to gdb, i.e. get_reg is
1661 gdb reading a CPU register, and set_reg is gdb modifying a CPU register.
1662 */
1663
1664 void gdb_register_coprocessor(CPUState * env,
1665 gdb_reg_cb get_reg, gdb_reg_cb set_reg,
1666 int num_regs, const char *xml, int g_pos)
1667 {
1668 GDBRegisterState *s;
1669 GDBRegisterState **p;
1670 static int last_reg = NUM_CORE_REGS;
1671
1672 s = (GDBRegisterState *)qemu_mallocz(sizeof(GDBRegisterState));
1673 s->base_reg = last_reg;
1674 s->num_regs = num_regs;
1675 s->get_reg = get_reg;
1676 s->set_reg = set_reg;
1677 s->xml = xml;
1678 p = &env->gdb_regs;
1679 while (*p) {
1680 /* Check for duplicates. */
1681 if (strcmp((*p)->xml, xml) == 0)
1682 return;
1683 p = &(*p)->next;
1684 }
1685 /* Add to end of list. */
1686 last_reg += num_regs;
1687 *p = s;
1688 if (g_pos) {
1689 if (g_pos != s->base_reg) {
1690 fprintf(stderr, "Error: Bad gdb register numbering for '%s'\n"
1691 "Expected %d got %d\n", xml, g_pos, s->base_reg);
1692 } else {
1693 num_g_regs = last_reg;
1694 }
1695 }
1696 }
1697
1698 #ifndef CONFIG_USER_ONLY
1699 static const int xlat_gdb_type[] = {
1700 [GDB_WATCHPOINT_WRITE] = BP_GDB | BP_MEM_WRITE,
1701 [GDB_WATCHPOINT_READ] = BP_GDB | BP_MEM_READ,
1702 [GDB_WATCHPOINT_ACCESS] = BP_GDB | BP_MEM_ACCESS,
1703 };
1704 #endif
1705
1706 static int gdb_breakpoint_insert(target_ulong addr, target_ulong len, int type)
1707 {
1708 CPUState *env;
1709 int err = 0;
1710
1711 if (kvm_enabled())
1712 return kvm_insert_breakpoint(gdbserver_state->c_cpu, addr, len, type);
1713
1714 switch (type) {
1715 case GDB_BREAKPOINT_SW:
1716 case GDB_BREAKPOINT_HW:
1717 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1718 err = cpu_breakpoint_insert(env, addr, BP_GDB, NULL);
1719 if (err)
1720 break;
1721 }
1722 return err;
1723 #ifndef CONFIG_USER_ONLY
1724 case GDB_WATCHPOINT_WRITE:
1725 case GDB_WATCHPOINT_READ:
1726 case GDB_WATCHPOINT_ACCESS:
1727 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1728 err = cpu_watchpoint_insert(env, addr, len, xlat_gdb_type[type],
1729 NULL);
1730 if (err)
1731 break;
1732 }
1733 return err;
1734 #endif
1735 default:
1736 return -ENOSYS;
1737 }
1738 }
1739
1740 static int gdb_breakpoint_remove(target_ulong addr, target_ulong len, int type)
1741 {
1742 CPUState *env;
1743 int err = 0;
1744
1745 if (kvm_enabled())
1746 return kvm_remove_breakpoint(gdbserver_state->c_cpu, addr, len, type);
1747
1748 switch (type) {
1749 case GDB_BREAKPOINT_SW:
1750 case GDB_BREAKPOINT_HW:
1751 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1752 err = cpu_breakpoint_remove(env, addr, BP_GDB);
1753 if (err)
1754 break;
1755 }
1756 return err;
1757 #ifndef CONFIG_USER_ONLY
1758 case GDB_WATCHPOINT_WRITE:
1759 case GDB_WATCHPOINT_READ:
1760 case GDB_WATCHPOINT_ACCESS:
1761 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1762 err = cpu_watchpoint_remove(env, addr, len, xlat_gdb_type[type]);
1763 if (err)
1764 break;
1765 }
1766 return err;
1767 #endif
1768 default:
1769 return -ENOSYS;
1770 }
1771 }
1772
1773 static void gdb_breakpoint_remove_all(void)
1774 {
1775 CPUState *env;
1776
1777 if (kvm_enabled()) {
1778 kvm_remove_all_breakpoints(gdbserver_state->c_cpu);
1779 return;
1780 }
1781
1782 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1783 cpu_breakpoint_remove_all(env, BP_GDB);
1784 #ifndef CONFIG_USER_ONLY
1785 cpu_watchpoint_remove_all(env, BP_GDB);
1786 #endif
1787 }
1788 }
1789
1790 static void gdb_set_cpu_pc(GDBState *s, target_ulong pc)
1791 {
1792 #if defined(TARGET_I386)
1793 cpu_synchronize_state(s->c_cpu);
1794 s->c_cpu->eip = pc;
1795 #elif defined (TARGET_PPC)
1796 s->c_cpu->nip = pc;
1797 #elif defined (TARGET_SPARC)
1798 s->c_cpu->pc = pc;
1799 s->c_cpu->npc = pc + 4;
1800 #elif defined (TARGET_ARM)
1801 s->c_cpu->regs[15] = pc;
1802 #elif defined (TARGET_SH4)
1803 s->c_cpu->pc = pc;
1804 #elif defined (TARGET_MIPS)
1805 s->c_cpu->active_tc.PC = pc & ~(target_ulong)1;
1806 if (pc & 1) {
1807 s->c_cpu->hflags |= MIPS_HFLAG_M16;
1808 } else {
1809 s->c_cpu->hflags &= ~(MIPS_HFLAG_M16);
1810 }
1811 #elif defined (TARGET_MICROBLAZE)
1812 s->c_cpu->sregs[SR_PC] = pc;
1813 #elif defined (TARGET_CRIS)
1814 s->c_cpu->pc = pc;
1815 #elif defined (TARGET_ALPHA)
1816 s->c_cpu->pc = pc;
1817 #elif defined (TARGET_S390X)
1818 cpu_synchronize_state(s->c_cpu);
1819 s->c_cpu->psw.addr = pc;
1820 #elif defined (TARGET_LM32)
1821 s->c_cpu->pc = pc;
1822 #endif
1823 }
1824
1825 static inline int gdb_id(CPUState *env)
1826 {
1827 #if defined(CONFIG_USER_ONLY) && defined(CONFIG_USE_NPTL)
1828 return env->host_tid;
1829 #else
1830 return env->cpu_index + 1;
1831 #endif
1832 }
1833
1834 static CPUState *find_cpu(uint32_t thread_id)
1835 {
1836 CPUState *env;
1837
1838 for (env = first_cpu; env != NULL; env = env->next_cpu) {
1839 if (gdb_id(env) == thread_id) {
1840 return env;
1841 }
1842 }
1843
1844 return NULL;
1845 }
1846
1847 static int gdb_handle_packet(GDBState *s, const char *line_buf)
1848 {
1849 CPUState *env;
1850 const char *p;
1851 uint32_t thread;
1852 int ch, reg_size, type, res;
1853 char buf[MAX_PACKET_LENGTH];
1854 uint8_t mem_buf[MAX_PACKET_LENGTH];
1855 uint8_t *registers;
1856 target_ulong addr, len;
1857
1858 #ifdef DEBUG_GDB
1859 printf("command='%s'\n", line_buf);
1860 #endif
1861 p = line_buf;
1862 ch = *p++;
1863 switch(ch) {
1864 case '?':
1865 /* TODO: Make this return the correct value for user-mode. */
1866 snprintf(buf, sizeof(buf), "T%02xthread:%02x;", GDB_SIGNAL_TRAP,
1867 gdb_id(s->c_cpu));
1868 put_packet(s, buf);
1869 /* Remove all the breakpoints when this query is issued,
1870 * because gdb is doing and initial connect and the state
1871 * should be cleaned up.
1872 */
1873 gdb_breakpoint_remove_all();
1874 break;
1875 case 'c':
1876 if (*p != '\0') {
1877 addr = strtoull(p, (char **)&p, 16);
1878 gdb_set_cpu_pc(s, addr);
1879 }
1880 s->signal = 0;
1881 gdb_continue(s);
1882 return RS_IDLE;
1883 case 'C':
1884 s->signal = gdb_signal_to_target (strtoul(p, (char **)&p, 16));
1885 if (s->signal == -1)
1886 s->signal = 0;
1887 gdb_continue(s);
1888 return RS_IDLE;
1889 case 'v':
1890 if (strncmp(p, "Cont", 4) == 0) {
1891 int res_signal, res_thread;
1892
1893 p += 4;
1894 if (*p == '?') {
1895 put_packet(s, "vCont;c;C;s;S");
1896 break;
1897 }
1898 res = 0;
1899 res_signal = 0;
1900 res_thread = 0;
1901 while (*p) {
1902 int action, signal;
1903
1904 if (*p++ != ';') {
1905 res = 0;
1906 break;
1907 }
1908 action = *p++;
1909 signal = 0;
1910 if (action == 'C' || action == 'S') {
1911 signal = strtoul(p, (char **)&p, 16);
1912 } else if (action != 'c' && action != 's') {
1913 res = 0;
1914 break;
1915 }
1916 thread = 0;
1917 if (*p == ':') {
1918 thread = strtoull(p+1, (char **)&p, 16);
1919 }
1920 action = tolower(action);
1921 if (res == 0 || (res == 'c' && action == 's')) {
1922 res = action;
1923 res_signal = signal;
1924 res_thread = thread;
1925 }
1926 }
1927 if (res) {
1928 if (res_thread != -1 && res_thread != 0) {
1929 env = find_cpu(res_thread);
1930 if (env == NULL) {
1931 put_packet(s, "E22");
1932 break;
1933 }
1934 s->c_cpu = env;
1935 }
1936 if (res == 's') {
1937 cpu_single_step(s->c_cpu, sstep_flags);
1938 }
1939 s->signal = res_signal;
1940 gdb_continue(s);
1941 return RS_IDLE;
1942 }
1943 break;
1944 } else {
1945 goto unknown_command;
1946 }
1947 case 'k':
1948 /* Kill the target */
1949 fprintf(stderr, "\nQEMU: Terminated via GDBstub\n");
1950 exit(0);
1951 case 'D':
1952 /* Detach packet */
1953 gdb_breakpoint_remove_all();
1954 gdb_syscall_mode = GDB_SYS_DISABLED;
1955 gdb_continue(s);
1956 put_packet(s, "OK");
1957 break;
1958 case 's':
1959 if (*p != '\0') {
1960 addr = strtoull(p, (char **)&p, 16);
1961 gdb_set_cpu_pc(s, addr);
1962 }
1963 cpu_single_step(s->c_cpu, sstep_flags);
1964 gdb_continue(s);
1965 return RS_IDLE;
1966 case 'F':
1967 {
1968 target_ulong ret;
1969 target_ulong err;
1970
1971 ret = strtoull(p, (char **)&p, 16);
1972 if (*p == ',') {
1973 p++;
1974 err = strtoull(p, (char **)&p, 16);
1975 } else {
1976 err = 0;
1977 }
1978 if (*p == ',')
1979 p++;
1980 type = *p;
1981 if (gdb_current_syscall_cb)
1982 gdb_current_syscall_cb(s->c_cpu, ret, err);
1983 if (type == 'C') {
1984 put_packet(s, "T02");
1985 } else {
1986 gdb_continue(s);
1987 }
1988 }
1989 break;
1990 case 'g':
1991 cpu_synchronize_state(s->g_cpu);
1992 len = 0;
1993 for (addr = 0; addr < num_g_regs; addr++) {
1994 reg_size = gdb_read_register(s->g_cpu, mem_buf + len, addr);
1995 len += reg_size;
1996 }
1997 memtohex(buf, mem_buf, len);
1998 put_packet(s, buf);
1999 break;
2000 case 'G':
2001 cpu_synchronize_state(s->g_cpu);
2002 registers = mem_buf;
2003 len = strlen(p) / 2;
2004 hextomem((uint8_t *)registers, p, len);
2005 for (addr = 0; addr < num_g_regs && len > 0; addr++) {
2006 reg_size = gdb_write_register(s->g_cpu, registers, addr);
2007 len -= reg_size;
2008 registers += reg_size;
2009 }
2010 put_packet(s, "OK");
2011 break;
2012 case 'm':
2013 addr = strtoull(p, (char **)&p, 16);
2014 if (*p == ',')
2015 p++;
2016 len = strtoull(p, NULL, 16);
2017 if (cpu_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 0) != 0) {
2018 put_packet (s, "E14");
2019 } else {
2020 memtohex(buf, mem_buf, len);
2021 put_packet(s, buf);
2022 }
2023 break;
2024 case 'M':
2025 addr = strtoull(p, (char **)&p, 16);
2026 if (*p == ',')
2027 p++;
2028 len = strtoull(p, (char **)&p, 16);
2029 if (*p == ':')
2030 p++;
2031 hextomem(mem_buf, p, len);
2032 if (cpu_memory_rw_debug(s->g_cpu, addr, mem_buf, len, 1) != 0)
2033 put_packet(s, "E14");
2034 else
2035 put_packet(s, "OK");
2036 break;
2037 case 'p':
2038 /* Older gdb are really dumb, and don't use 'g' if 'p' is avaialable.
2039 This works, but can be very slow. Anything new enough to
2040 understand XML also knows how to use this properly. */
2041 if (!gdb_has_xml)
2042 goto unknown_command;
2043 addr = strtoull(p, (char **)&p, 16);
2044 reg_size = gdb_read_register(s->g_cpu, mem_buf, addr);
2045 if (reg_size) {
2046 memtohex(buf, mem_buf, reg_size);
2047 put_packet(s, buf);
2048 } else {
2049 put_packet(s, "E14");
2050 }
2051 break;
2052 case 'P':
2053 if (!gdb_has_xml)
2054 goto unknown_command;
2055 addr = strtoull(p, (char **)&p, 16);
2056 if (*p == '=')
2057 p++;
2058 reg_size = strlen(p) / 2;
2059 hextomem(mem_buf, p, reg_size);
2060 gdb_write_register(s->g_cpu, mem_buf, addr);
2061 put_packet(s, "OK");
2062 break;
2063 case 'Z':
2064 case 'z':
2065 type = strtoul(p, (char **)&p, 16);
2066 if (*p == ',')
2067 p++;
2068 addr = strtoull(p, (char **)&p, 16);
2069 if (*p == ',')
2070 p++;
2071 len = strtoull(p, (char **)&p, 16);
2072 if (ch == 'Z')
2073 res = gdb_breakpoint_insert(addr, len, type);
2074 else
2075 res = gdb_breakpoint_remove(addr, len, type);
2076 if (res >= 0)
2077 put_packet(s, "OK");
2078 else if (res == -ENOSYS)
2079 put_packet(s, "");
2080 else
2081 put_packet(s, "E22");
2082 break;
2083 case 'H':
2084 type = *p++;
2085 thread = strtoull(p, (char **)&p, 16);
2086 if (thread == -1 || thread == 0) {
2087 put_packet(s, "OK");
2088 break;
2089 }
2090 env = find_cpu(thread);
2091 if (env == NULL) {
2092 put_packet(s, "E22");
2093 break;
2094 }
2095 switch (type) {
2096 case 'c':
2097 s->c_cpu = env;
2098 put_packet(s, "OK");
2099 break;
2100 case 'g':
2101 s->g_cpu = env;
2102 put_packet(s, "OK");
2103 break;
2104 default:
2105 put_packet(s, "E22");
2106 break;
2107 }
2108 break;
2109 case 'T':
2110 thread = strtoull(p, (char **)&p, 16);
2111 env = find_cpu(thread);
2112
2113 if (env != NULL) {
2114 put_packet(s, "OK");
2115 } else {
2116 put_packet(s, "E22");
2117 }
2118 break;
2119 case 'q':
2120 case 'Q':
2121 /* parse any 'q' packets here */
2122 if (!strcmp(p,"qemu.sstepbits")) {
2123 /* Query Breakpoint bit definitions */
2124 snprintf(buf, sizeof(buf), "ENABLE=%x,NOIRQ=%x,NOTIMER=%x",
2125 SSTEP_ENABLE,
2126 SSTEP_NOIRQ,
2127 SSTEP_NOTIMER);
2128 put_packet(s, buf);
2129 break;
2130 } else if (strncmp(p,"qemu.sstep",10) == 0) {
2131 /* Display or change the sstep_flags */
2132 p += 10;
2133 if (*p != '=') {
2134 /* Display current setting */
2135 snprintf(buf, sizeof(buf), "0x%x", sstep_flags);
2136 put_packet(s, buf);
2137 break;
2138 }
2139 p++;
2140 type = strtoul(p, (char **)&p, 16);
2141 sstep_flags = type;
2142 put_packet(s, "OK");
2143 break;
2144 } else if (strcmp(p,"C") == 0) {
2145 /* "Current thread" remains vague in the spec, so always return
2146 * the first CPU (gdb returns the first thread). */
2147 put_packet(s, "QC1");
2148 break;
2149 } else if (strcmp(p,"fThreadInfo") == 0) {
2150 s->query_cpu = first_cpu;
2151 goto report_cpuinfo;
2152 } else if (strcmp(p,"sThreadInfo") == 0) {
2153 report_cpuinfo:
2154 if (s->query_cpu) {
2155 snprintf(buf, sizeof(buf), "m%x", gdb_id(s->query_cpu));
2156 put_packet(s, buf);
2157 s->query_cpu = s->query_cpu->next_cpu;
2158 } else
2159 put_packet(s, "l");
2160 break;
2161 } else if (strncmp(p,"ThreadExtraInfo,", 16) == 0) {
2162 thread = strtoull(p+16, (char **)&p, 16);
2163 env = find_cpu(thread);
2164 if (env != NULL) {
2165 cpu_synchronize_state(env);
2166 len = snprintf((char *)mem_buf, sizeof(mem_buf),
2167 "CPU#%d [%s]", env->cpu_index,
2168 env->halted ? "halted " : "running");
2169 memtohex(buf, mem_buf, len);
2170 put_packet(s, buf);
2171 }
2172 break;
2173 }
2174 #ifdef CONFIG_USER_ONLY
2175 else if (strncmp(p, "Offsets", 7) == 0) {
2176 TaskState *ts = s->c_cpu->opaque;
2177
2178 snprintf(buf, sizeof(buf),
2179 "Text=" TARGET_ABI_FMT_lx ";Data=" TARGET_ABI_FMT_lx
2180 ";Bss=" TARGET_ABI_FMT_lx,
2181 ts->info->code_offset,
2182 ts->info->data_offset,
2183 ts->info->data_offset);
2184 put_packet(s, buf);
2185 break;
2186 }
2187 #else /* !CONFIG_USER_ONLY */
2188 else if (strncmp(p, "Rcmd,", 5) == 0) {
2189 int len = strlen(p + 5);
2190
2191 if ((len % 2) != 0) {
2192 put_packet(s, "E01");
2193 break;
2194 }
2195 hextomem(mem_buf, p + 5, len);
2196 len = len / 2;
2197 mem_buf[len++] = 0;
2198 qemu_chr_read(s->mon_chr, mem_buf, len);
2199 put_packet(s, "OK");
2200 break;
2201 }
2202 #endif /* !CONFIG_USER_ONLY */
2203 if (strncmp(p, "Supported", 9) == 0) {
2204 snprintf(buf, sizeof(buf), "PacketSize=%x", MAX_PACKET_LENGTH);
2205 #ifdef GDB_CORE_XML
2206 pstrcat(buf, sizeof(buf), ";qXfer:features:read+");
2207 #endif
2208 put_packet(s, buf);
2209 break;
2210 }
2211 #ifdef GDB_CORE_XML
2212 if (strncmp(p, "Xfer:features:read:", 19) == 0) {
2213 const char *xml;
2214 target_ulong total_len;
2215
2216 gdb_has_xml = 1;
2217 p += 19;
2218 xml = get_feature_xml(p, &p);
2219 if (!xml) {
2220 snprintf(buf, sizeof(buf), "E00");
2221 put_packet(s, buf);
2222 break;
2223 }
2224
2225 if (*p == ':')
2226 p++;
2227 addr = strtoul(p, (char **)&p, 16);
2228 if (*p == ',')
2229 p++;
2230 len = strtoul(p, (char **)&p, 16);
2231
2232 total_len = strlen(xml);
2233 if (addr > total_len) {
2234 snprintf(buf, sizeof(buf), "E00");
2235 put_packet(s, buf);
2236 break;
2237 }
2238 if (len > (MAX_PACKET_LENGTH - 5) / 2)
2239 len = (MAX_PACKET_LENGTH - 5) / 2;
2240 if (len < total_len - addr) {
2241 buf[0] = 'm';
2242 len = memtox(buf + 1, xml + addr, len);
2243 } else {
2244 buf[0] = 'l';
2245 len = memtox(buf + 1, xml + addr, total_len - addr);
2246 }
2247 put_packet_binary(s, buf, len + 1);
2248 break;
2249 }
2250 #endif
2251 /* Unrecognised 'q' command. */
2252 goto unknown_command;
2253
2254 default:
2255 unknown_command:
2256 /* put empty packet */
2257 buf[0] = '\0';
2258 put_packet(s, buf);
2259 break;
2260 }
2261 return RS_IDLE;
2262 }
2263
2264 void gdb_set_stop_cpu(CPUState *env)
2265 {
2266 gdbserver_state->c_cpu = env;
2267 gdbserver_state->g_cpu = env;
2268 }
2269
2270 #ifndef CONFIG_USER_ONLY
2271 static void gdb_vm_state_change(void *opaque, int running, int reason)
2272 {
2273 GDBState *s = gdbserver_state;
2274 CPUState *env = s->c_cpu;
2275 char buf[256];
2276 const char *type;
2277 int ret;
2278
2279 if (running || s->state == RS_INACTIVE || s->state == RS_SYSCALL) {
2280 return;
2281 }
2282 switch (reason) {
2283 case VMSTOP_DEBUG:
2284 if (env->watchpoint_hit) {
2285 switch (env->watchpoint_hit->flags & BP_MEM_ACCESS) {
2286 case BP_MEM_READ:
2287 type = "r";
2288 break;
2289 case BP_MEM_ACCESS:
2290 type = "a";
2291 break;
2292 default:
2293 type = "";
2294 break;
2295 }
2296 snprintf(buf, sizeof(buf),
2297 "T%02xthread:%02x;%swatch:" TARGET_FMT_lx ";",
2298 GDB_SIGNAL_TRAP, gdb_id(env), type,
2299 env->watchpoint_hit->vaddr);
2300 env->watchpoint_hit = NULL;
2301 goto send_packet;
2302 }
2303 tb_flush(env);
2304 ret = GDB_SIGNAL_TRAP;
2305 break;
2306 case VMSTOP_USER:
2307 ret = GDB_SIGNAL_INT;
2308 break;
2309 case VMSTOP_SHUTDOWN:
2310 ret = GDB_SIGNAL_QUIT;
2311 break;
2312 case VMSTOP_DISKFULL:
2313 ret = GDB_SIGNAL_IO;
2314 break;
2315 case VMSTOP_WATCHDOG:
2316 ret = GDB_SIGNAL_ALRM;
2317 break;
2318 case VMSTOP_PANIC:
2319 ret = GDB_SIGNAL_ABRT;
2320 break;
2321 case VMSTOP_SAVEVM:
2322 case VMSTOP_LOADVM:
2323 return;
2324 case VMSTOP_MIGRATE:
2325 ret = GDB_SIGNAL_XCPU;
2326 break;
2327 default:
2328 ret = GDB_SIGNAL_UNKNOWN;
2329 break;
2330 }
2331 snprintf(buf, sizeof(buf), "T%02xthread:%02x;", ret, gdb_id(env));
2332
2333 send_packet:
2334 put_packet(s, buf);
2335
2336 /* disable single step if it was enabled */
2337 cpu_single_step(env, 0);
2338 }
2339 #endif
2340
2341 /* Send a gdb syscall request.
2342 This accepts limited printf-style format specifiers, specifically:
2343 %x - target_ulong argument printed in hex.
2344 %lx - 64-bit argument printed in hex.
2345 %s - string pointer (target_ulong) and length (int) pair. */
2346 void gdb_do_syscall(gdb_syscall_complete_cb cb, const char *fmt, ...)
2347 {
2348 va_list va;
2349 char buf[256];
2350 char *p;
2351 target_ulong addr;
2352 uint64_t i64;
2353 GDBState *s;
2354
2355 s = gdbserver_state;
2356 if (!s)
2357 return;
2358 gdb_current_syscall_cb = cb;
2359 s->state = RS_SYSCALL;
2360 #ifndef CONFIG_USER_ONLY
2361 vm_stop(VMSTOP_DEBUG);
2362 #endif
2363 s->state = RS_IDLE;
2364 va_start(va, fmt);
2365 p = buf;
2366 *(p++) = 'F';
2367 while (*fmt) {
2368 if (*fmt == '%') {
2369 fmt++;
2370 switch (*fmt++) {
2371 case 'x':
2372 addr = va_arg(va, target_ulong);
2373 p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx, addr);
2374 break;
2375 case 'l':
2376 if (*(fmt++) != 'x')
2377 goto bad_format;
2378 i64 = va_arg(va, uint64_t);
2379 p += snprintf(p, &buf[sizeof(buf)] - p, "%" PRIx64, i64);
2380 break;
2381 case 's':
2382 addr = va_arg(va, target_ulong);
2383 p += snprintf(p, &buf[sizeof(buf)] - p, TARGET_FMT_lx "/%x",
2384 addr, va_arg(va, int));
2385 break;
2386 default:
2387 bad_format:
2388 fprintf(stderr, "gdbstub: Bad syscall format string '%s'\n",
2389 fmt - 1);
2390 break;
2391 }
2392 } else {
2393 *(p++) = *(fmt++);
2394 }
2395 }
2396 *p = 0;
2397 va_end(va);
2398 put_packet(s, buf);
2399 #ifdef CONFIG_USER_ONLY
2400 gdb_handlesig(s->c_cpu, 0);
2401 #else
2402 cpu_exit(s->c_cpu);
2403 #endif
2404 }
2405
2406 static void gdb_read_byte(GDBState *s, int ch)
2407 {
2408 int i, csum;
2409 uint8_t reply;
2410
2411 #ifndef CONFIG_USER_ONLY
2412 if (s->last_packet_len) {
2413 /* Waiting for a response to the last packet. If we see the start
2414 of a new command then abandon the previous response. */
2415 if (ch == '-') {
2416 #ifdef DEBUG_GDB
2417 printf("Got NACK, retransmitting\n");
2418 #endif
2419 put_buffer(s, (uint8_t *)s->last_packet, s->last_packet_len);
2420 }
2421 #ifdef DEBUG_GDB
2422 else if (ch == '+')
2423 printf("Got ACK\n");
2424 else
2425 printf("Got '%c' when expecting ACK/NACK\n", ch);
2426 #endif
2427 if (ch == '+' || ch == '$')
2428 s->last_packet_len = 0;
2429 if (ch != '$')
2430 return;
2431 }
2432 if (vm_running) {
2433 /* when the CPU is running, we cannot do anything except stop
2434 it when receiving a char */
2435 vm_stop(VMSTOP_USER);
2436 } else
2437 #endif
2438 {
2439 switch(s->state) {
2440 case RS_IDLE:
2441 if (ch == '$') {
2442 s->line_buf_index = 0;
2443 s->state = RS_GETLINE;
2444 }
2445 break;
2446 case RS_GETLINE:
2447 if (ch == '#') {
2448 s->state = RS_CHKSUM1;
2449 } else if (s->line_buf_index >= sizeof(s->line_buf) - 1) {
2450 s->state = RS_IDLE;
2451 } else {
2452 s->line_buf[s->line_buf_index++] = ch;
2453 }
2454 break;
2455 case RS_CHKSUM1:
2456 s->line_buf[s->line_buf_index] = '\0';
2457 s->line_csum = fromhex(ch) << 4;
2458 s->state = RS_CHKSUM2;
2459 break;
2460 case RS_CHKSUM2:
2461 s->line_csum |= fromhex(ch);
2462 csum = 0;
2463 for(i = 0; i < s->line_buf_index; i++) {
2464 csum += s->line_buf[i];
2465 }
2466 if (s->line_csum != (csum & 0xff)) {
2467 reply = '-';
2468 put_buffer(s, &reply, 1);
2469 s->state = RS_IDLE;
2470 } else {
2471 reply = '+';
2472 put_buffer(s, &reply, 1);
2473 s->state = gdb_handle_packet(s, s->line_buf);
2474 }
2475 break;
2476 default:
2477 abort();
2478 }
2479 }
2480 }
2481
2482 /* Tell the remote gdb that the process has exited. */
2483 void gdb_exit(CPUState *env, int code)
2484 {
2485 GDBState *s;
2486 char buf[4];
2487
2488 s = gdbserver_state;
2489 if (!s) {
2490 return;
2491 }
2492 #ifdef CONFIG_USER_ONLY
2493 if (gdbserver_fd < 0 || s->fd < 0) {
2494 return;
2495 }
2496 #endif
2497
2498 snprintf(buf, sizeof(buf), "W%02x", (uint8_t)code);
2499 put_packet(s, buf);
2500
2501 #ifndef CONFIG_USER_ONLY
2502 if (s->chr) {
2503 qemu_chr_close(s->chr);
2504 }
2505 #endif
2506 }
2507
2508 #ifdef CONFIG_USER_ONLY
2509 int
2510 gdb_queuesig (void)
2511 {
2512 GDBState *s;
2513
2514 s = gdbserver_state;
2515
2516 if (gdbserver_fd < 0 || s->fd < 0)
2517 return 0;
2518 else
2519 return 1;
2520 }
2521
2522 int
2523 gdb_handlesig (CPUState *env, int sig)
2524 {
2525 GDBState *s;
2526 char buf[256];
2527 int n;
2528
2529 s = gdbserver_state;
2530 if (gdbserver_fd < 0 || s->fd < 0)
2531 return sig;
2532
2533 /* disable single step if it was enabled */
2534 cpu_single_step(env, 0);
2535 tb_flush(env);
2536
2537 if (sig != 0)
2538 {
2539 snprintf(buf, sizeof(buf), "S%02x", target_signal_to_gdb (sig));
2540 put_packet(s, buf);
2541 }
2542 /* put_packet() might have detected that the peer terminated the
2543 connection. */
2544 if (s->fd < 0)
2545 return sig;
2546
2547 sig = 0;
2548 s->state = RS_IDLE;
2549 s->running_state = 0;
2550 while (s->running_state == 0) {
2551 n = read (s->fd, buf, 256);
2552 if (n > 0)
2553 {
2554 int i;
2555
2556 for (i = 0; i < n; i++)
2557 gdb_read_byte (s, buf[i]);
2558 }
2559 else if (n == 0 || errno != EAGAIN)
2560 {
2561 /* XXX: Connection closed. Should probably wait for annother
2562 connection before continuing. */
2563 return sig;
2564 }
2565 }
2566 sig = s->signal;
2567 s->signal = 0;
2568 return sig;
2569 }
2570
2571 /* Tell the remote gdb that the process has exited due to SIG. */
2572 void gdb_signalled(CPUState *env, int sig)
2573 {
2574 GDBState *s;
2575 char buf[4];
2576
2577 s = gdbserver_state;
2578 if (gdbserver_fd < 0 || s->fd < 0)
2579 return;
2580
2581 snprintf(buf, sizeof(buf), "X%02x", target_signal_to_gdb (sig));
2582 put_packet(s, buf);
2583 }
2584
2585 static void gdb_accept(void)
2586 {
2587 GDBState *s;
2588 struct sockaddr_in sockaddr;
2589 socklen_t len;
2590 int val, fd;
2591
2592 for(;;) {
2593 len = sizeof(sockaddr);
2594 fd = accept(gdbserver_fd, (struct sockaddr *)&sockaddr, &len);
2595 if (fd < 0 && errno != EINTR) {
2596 perror("accept");
2597 return;
2598 } else if (fd >= 0) {
2599 #ifndef _WIN32
2600 fcntl(fd, F_SETFD, FD_CLOEXEC);
2601 #endif
2602 break;
2603 }
2604 }
2605
2606 /* set short latency */
2607 val = 1;
2608 setsockopt(fd, IPPROTO_TCP, TCP_NODELAY, (char *)&val, sizeof(val));
2609
2610 s = qemu_mallocz(sizeof(GDBState));
2611 s->c_cpu = first_cpu;
2612 s->g_cpu = first_cpu;
2613 s->fd = fd;
2614 gdb_has_xml = 0;
2615
2616 gdbserver_state = s;
2617
2618 fcntl(fd, F_SETFL, O_NONBLOCK);
2619 }
2620
2621 static int gdbserver_open(int port)
2622 {
2623 struct sockaddr_in sockaddr;
2624 int fd, val, ret;
2625
2626 fd = socket(PF_INET, SOCK_STREAM, 0);
2627 if (fd < 0) {
2628 perror("socket");
2629 return -1;
2630 }
2631 #ifndef _WIN32
2632 fcntl(fd, F_SETFD, FD_CLOEXEC);
2633 #endif
2634
2635 /* allow fast reuse */
2636 val = 1;
2637 setsockopt(fd, SOL_SOCKET, SO_REUSEADDR, (char *)&val, sizeof(val));
2638
2639 sockaddr.sin_family = AF_INET;
2640 sockaddr.sin_port = htons(port);
2641 sockaddr.sin_addr.s_addr = 0;
2642 ret = bind(fd, (struct sockaddr *)&sockaddr, sizeof(sockaddr));
2643 if (ret < 0) {
2644 perror("bind");
2645 return -1;
2646 }
2647 ret = listen(fd, 0);
2648 if (ret < 0) {
2649 perror("listen");
2650 return -1;
2651 }
2652 return fd;
2653 }
2654
2655 int gdbserver_start(int port)
2656 {
2657 gdbserver_fd = gdbserver_open(port);
2658 if (gdbserver_fd < 0)
2659 return -1;
2660 /* accept connections */
2661 gdb_accept();
2662 return 0;
2663 }
2664
2665 /* Disable gdb stub for child processes. */
2666 void gdbserver_fork(CPUState *env)
2667 {
2668 GDBState *s = gdbserver_state;
2669 if (gdbserver_fd < 0 || s->fd < 0)
2670 return;
2671 close(s->fd);
2672 s->fd = -1;
2673 cpu_breakpoint_remove_all(env, BP_GDB);
2674 cpu_watchpoint_remove_all(env, BP_GDB);
2675 }
2676 #else
2677 static int gdb_chr_can_receive(void *opaque)
2678 {
2679 /* We can handle an arbitrarily large amount of data.
2680 Pick the maximum packet size, which is as good as anything. */
2681 return MAX_PACKET_LENGTH;
2682 }
2683
2684 static void gdb_chr_receive(void *opaque, const uint8_t *buf, int size)
2685 {
2686 int i;
2687
2688 for (i = 0; i < size; i++) {
2689 gdb_read_byte(gdbserver_state, buf[i]);
2690 }
2691 }
2692
2693 static void gdb_chr_event(void *opaque, int event)
2694 {
2695 switch (event) {
2696 case CHR_EVENT_OPENED:
2697 vm_stop(VMSTOP_USER);
2698 gdb_has_xml = 0;
2699 break;
2700 default:
2701 break;
2702 }
2703 }
2704
2705 static void gdb_monitor_output(GDBState *s, const char *msg, int len)
2706 {
2707 char buf[MAX_PACKET_LENGTH];
2708
2709 buf[0] = 'O';
2710 if (len > (MAX_PACKET_LENGTH/2) - 1)
2711 len = (MAX_PACKET_LENGTH/2) - 1;
2712 memtohex(buf + 1, (uint8_t *)msg, len);
2713 put_packet(s, buf);
2714 }
2715
2716 static int gdb_monitor_write(CharDriverState *chr, const uint8_t *buf, int len)
2717 {
2718 const char *p = (const char *)buf;
2719 int max_sz;
2720
2721 max_sz = (sizeof(gdbserver_state->last_packet) - 2) / 2;
2722 for (;;) {
2723 if (len <= max_sz) {
2724 gdb_monitor_output(gdbserver_state, p, len);
2725 break;
2726 }
2727 gdb_monitor_output(gdbserver_state, p, max_sz);
2728 p += max_sz;
2729 len -= max_sz;
2730 }
2731 return len;
2732 }
2733
2734 #ifndef _WIN32
2735 static void gdb_sigterm_handler(int signal)
2736 {
2737 if (vm_running) {
2738 vm_stop(VMSTOP_USER);
2739 }
2740 }
2741 #endif
2742
2743 int gdbserver_start(const char *device)
2744 {
2745 GDBState *s;
2746 char gdbstub_device_name[128];
2747 CharDriverState *chr = NULL;
2748 CharDriverState *mon_chr;
2749
2750 if (!device)
2751 return -1;
2752 if (strcmp(device, "none") != 0) {
2753 if (strstart(device, "tcp:", NULL)) {
2754 /* enforce required TCP attributes */
2755 snprintf(gdbstub_device_name, sizeof(gdbstub_device_name),
2756 "%s,nowait,nodelay,server", device);
2757 device = gdbstub_device_name;
2758 }
2759 #ifndef _WIN32
2760 else if (strcmp(device, "stdio") == 0) {
2761 struct sigaction act;
2762
2763 memset(&act, 0, sizeof(act));
2764 act.sa_handler = gdb_sigterm_handler;
2765 sigaction(SIGINT, &act, NULL);
2766 }
2767 #endif
2768 chr = qemu_chr_open("gdb", device, NULL);
2769 if (!chr)
2770 return -1;
2771
2772 qemu_chr_add_handlers(chr, gdb_chr_can_receive, gdb_chr_receive,
2773 gdb_chr_event, NULL);
2774 }
2775
2776 s = gdbserver_state;
2777 if (!s) {
2778 s = qemu_mallocz(sizeof(GDBState));
2779 gdbserver_state = s;
2780
2781 qemu_add_vm_change_state_handler(gdb_vm_state_change, NULL);
2782
2783 /* Initialize a monitor terminal for gdb */
2784 mon_chr = qemu_mallocz(sizeof(*mon_chr));
2785 mon_chr->chr_write = gdb_monitor_write;
2786 monitor_init(mon_chr, 0);
2787 } else {
2788 if (s->chr)
2789 qemu_chr_close(s->chr);
2790 mon_chr = s->mon_chr;
2791 memset(s, 0, sizeof(GDBState));
2792 }
2793 s->c_cpu = first_cpu;
2794 s->g_cpu = first_cpu;
2795 s->chr = chr;
2796 s->state = chr ? RS_IDLE : RS_INACTIVE;
2797 s->mon_chr = mon_chr;
2798
2799 return 0;
2800 }
2801 #endif
QEMU modified to work with kvm