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Merge remote-tracking branch 'mdroth/qga-pull-3-12-2012' into staging
[qemu-kvm.git] / hw / usb-ehci.c
blobdf742f7f02b3a7d3921450427f292c1ee4192ccf
1 /*
2 * QEMU USB EHCI Emulation
3 *
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
5 *
6 * EHCI project was started by Mark Burkley, with contributions by
7 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
8 * Jan Kiszka and Vincent Palatin contributed bugfixes.
9 *
10 *
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or(at your option) any later version.
15 *
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #include "hw.h"
26 #include "qemu-timer.h"
27 #include "usb.h"
28 #include "pci.h"
29 #include "monitor.h"
30 #include "trace.h"
31 #include "dma.h"
32
33 #define EHCI_DEBUG 0
34
35 #if EHCI_DEBUG
36 #define DPRINTF printf
37 #else
38 #define DPRINTF(...)
39 #endif
40
41 /* internal processing - reset HC to try and recover */
42 #define USB_RET_PROCERR (-99)
43
44 #define MMIO_SIZE 0x1000
45
46 /* Capability Registers Base Address - section 2.2 */
47 #define CAPREGBASE 0x0000
48 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
49 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
50 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
51 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
52 #define EECP HCCPARAMS + 1
53 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c
54 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010
55
56 #define OPREGBASE 0x0020 // Operational Registers Base Address
57
58 #define USBCMD OPREGBASE + 0x0000
59 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
60 #define USBCMD_HCRESET (1 << 1) // HC Reset
61 #define USBCMD_FLS (3 << 2) // Frame List Size
62 #define USBCMD_FLS_SH 2 // Frame List Size Shift
63 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
64 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
65 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
66 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
67 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
68 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
69 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
70 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
71
72 #define USBSTS OPREGBASE + 0x0004
73 #define USBSTS_RO_MASK 0x0000003f
74 #define USBSTS_INT (1 << 0) // USB Interrupt
75 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
76 #define USBSTS_PCD (1 << 2) // Port Change Detect
77 #define USBSTS_FLR (1 << 3) // Frame List Rollover
78 #define USBSTS_HSE (1 << 4) // Host System Error
79 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
80 #define USBSTS_HALT (1 << 12) // HC Halted
81 #define USBSTS_REC (1 << 13) // Reclamation
82 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
83 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
84
85 /*
86 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
87 * so no need to redefine here.
88 */
89 #define USBINTR OPREGBASE + 0x0008
90 #define USBINTR_MASK 0x0000003f
91
92 #define FRINDEX OPREGBASE + 0x000c
93 #define CTRLDSSEGMENT OPREGBASE + 0x0010
94 #define PERIODICLISTBASE OPREGBASE + 0x0014
95 #define ASYNCLISTADDR OPREGBASE + 0x0018
96 #define ASYNCLISTADDR_MASK 0xffffffe0
97
98 #define CONFIGFLAG OPREGBASE + 0x0040
99
100 #define PORTSC (OPREGBASE + 0x0044)
101 #define PORTSC_BEGIN PORTSC
102 #define PORTSC_END (PORTSC + 4 * NB_PORTS)
103 /*
104 * Bits that are reserved or are read-only are masked out of values
105 * written to us by software
106 */
107 #define PORTSC_RO_MASK 0x007001c0
108 #define PORTSC_RWC_MASK 0x0000002a
109 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
110 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
111 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
112 #define PORTSC_PTC (15 << 16) // Port Test Control
113 #define PORTSC_PTC_SH 16 // Port Test Control shift
114 #define PORTSC_PIC (3 << 14) // Port Indicator Control
115 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
116 #define PORTSC_POWNER (1 << 13) // Port Owner
117 #define PORTSC_PPOWER (1 << 12) // Port Power
118 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
119 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
120 #define PORTSC_PRESET (1 << 8) // Port Reset
121 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
122 #define PORTSC_FPRES (1 << 6) // Force Port Resume
123 #define PORTSC_OCC (1 << 5) // Over Current Change
124 #define PORTSC_OCA (1 << 4) // Over Current Active
125 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
126 #define PORTSC_PED (1 << 2) // Port Enable/Disable
127 #define PORTSC_CSC (1 << 1) // Connect Status Change
128 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
129
130 #define FRAME_TIMER_FREQ 1000
131 #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ)
132
133 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
134 #define NB_PORTS 6 // Number of downstream ports
135 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
136 #define MAX_ITERATIONS 20 // Max number of QH before we break the loop
137 #define MAX_QH 100 // Max allowable queue heads in a chain
138
139 /* Internal periodic / asynchronous schedule state machine states
140 */
141 typedef enum {
142 EST_INACTIVE = 1000,
143 EST_ACTIVE,
144 EST_EXECUTING,
145 EST_SLEEPING,
146 /* The following states are internal to the state machine function
147 */
148 EST_WAITLISTHEAD,
149 EST_FETCHENTRY,
150 EST_FETCHQH,
151 EST_FETCHITD,
152 EST_FETCHSITD,
153 EST_ADVANCEQUEUE,
154 EST_FETCHQTD,
155 EST_EXECUTE,
156 EST_WRITEBACK,
157 EST_HORIZONTALQH
158 } EHCI_STATES;
159
160 /* macros for accessing fields within next link pointer entry */
161 #define NLPTR_GET(x) ((x) & 0xffffffe0)
162 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
163 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
164
165 /* link pointer types */
166 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
167 #define NLPTR_TYPE_QH 1 // queue head
168 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
169 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
170
171
172 /* EHCI spec version 1.0 Section 3.3
173 */
174 typedef struct EHCIitd {
175 uint32_t next;
176
177 uint32_t transact[8];
178 #define ITD_XACT_ACTIVE (1 << 31)
179 #define ITD_XACT_DBERROR (1 << 30)
180 #define ITD_XACT_BABBLE (1 << 29)
181 #define ITD_XACT_XACTERR (1 << 28)
182 #define ITD_XACT_LENGTH_MASK 0x0fff0000
183 #define ITD_XACT_LENGTH_SH 16
184 #define ITD_XACT_IOC (1 << 15)
185 #define ITD_XACT_PGSEL_MASK 0x00007000
186 #define ITD_XACT_PGSEL_SH 12
187 #define ITD_XACT_OFFSET_MASK 0x00000fff
188
189 uint32_t bufptr[7];
190 #define ITD_BUFPTR_MASK 0xfffff000
191 #define ITD_BUFPTR_SH 12
192 #define ITD_BUFPTR_EP_MASK 0x00000f00
193 #define ITD_BUFPTR_EP_SH 8
194 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
195 #define ITD_BUFPTR_DEVADDR_SH 0
196 #define ITD_BUFPTR_DIRECTION (1 << 11)
197 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
198 #define ITD_BUFPTR_MAXPKT_SH 0
199 #define ITD_BUFPTR_MULT_MASK 0x00000003
200 #define ITD_BUFPTR_MULT_SH 0
201 } EHCIitd;
202
203 /* EHCI spec version 1.0 Section 3.4
204 */
205 typedef struct EHCIsitd {
206 uint32_t next; // Standard next link pointer
207 uint32_t epchar;
208 #define SITD_EPCHAR_IO (1 << 31)
209 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
210 #define SITD_EPCHAR_PORTNUM_SH 24
211 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000
212 #define SITD_EPCHAR_HUBADDR_SH 16
213 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00
214 #define SITD_EPCHAR_EPNUM_SH 8
215 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
216
217 uint32_t uframe;
218 #define SITD_UFRAME_CMASK_MASK 0x0000ff00
219 #define SITD_UFRAME_CMASK_SH 8
220 #define SITD_UFRAME_SMASK_MASK 0x000000ff
221
222 uint32_t results;
223 #define SITD_RESULTS_IOC (1 << 31)
224 #define SITD_RESULTS_PGSEL (1 << 30)
225 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000
226 #define SITD_RESULTS_TYBYTES_SH 16
227 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
228 #define SITD_RESULTS_CPROGMASK_SH 8
229 #define SITD_RESULTS_ACTIVE (1 << 7)
230 #define SITD_RESULTS_ERR (1 << 6)
231 #define SITD_RESULTS_DBERR (1 << 5)
232 #define SITD_RESULTS_BABBLE (1 << 4)
233 #define SITD_RESULTS_XACTERR (1 << 3)
234 #define SITD_RESULTS_MISSEDUF (1 << 2)
235 #define SITD_RESULTS_SPLITXSTATE (1 << 1)
236
237 uint32_t bufptr[2];
238 #define SITD_BUFPTR_MASK 0xfffff000
239 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff
240 #define SITD_BUFPTR_TPOS_MASK 0x00000018
241 #define SITD_BUFPTR_TPOS_SH 3
242 #define SITD_BUFPTR_TCNT_MASK 0x00000007
243
244 uint32_t backptr; // Standard next link pointer
245 } EHCIsitd;
246
247 /* EHCI spec version 1.0 Section 3.5
248 */
249 typedef struct EHCIqtd {
250 uint32_t next; // Standard next link pointer
251 uint32_t altnext; // Standard next link pointer
252 uint32_t token;
253 #define QTD_TOKEN_DTOGGLE (1 << 31)
254 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000
255 #define QTD_TOKEN_TBYTES_SH 16
256 #define QTD_TOKEN_IOC (1 << 15)
257 #define QTD_TOKEN_CPAGE_MASK 0x00007000
258 #define QTD_TOKEN_CPAGE_SH 12
259 #define QTD_TOKEN_CERR_MASK 0x00000c00
260 #define QTD_TOKEN_CERR_SH 10
261 #define QTD_TOKEN_PID_MASK 0x00000300
262 #define QTD_TOKEN_PID_SH 8
263 #define QTD_TOKEN_ACTIVE (1 << 7)
264 #define QTD_TOKEN_HALT (1 << 6)
265 #define QTD_TOKEN_DBERR (1 << 5)
266 #define QTD_TOKEN_BABBLE (1 << 4)
267 #define QTD_TOKEN_XACTERR (1 << 3)
268 #define QTD_TOKEN_MISSEDUF (1 << 2)
269 #define QTD_TOKEN_SPLITXSTATE (1 << 1)
270 #define QTD_TOKEN_PING (1 << 0)
271
272 uint32_t bufptr[5]; // Standard buffer pointer
273 #define QTD_BUFPTR_MASK 0xfffff000
274 #define QTD_BUFPTR_SH 12
275 } EHCIqtd;
276
277 /* EHCI spec version 1.0 Section 3.6
278 */
279 typedef struct EHCIqh {
280 uint32_t next; // Standard next link pointer
281
282 /* endpoint characteristics */
283 uint32_t epchar;
284 #define QH_EPCHAR_RL_MASK 0xf0000000
285 #define QH_EPCHAR_RL_SH 28
286 #define QH_EPCHAR_C (1 << 27)
287 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000
288 #define QH_EPCHAR_MPLEN_SH 16
289 #define QH_EPCHAR_H (1 << 15)
290 #define QH_EPCHAR_DTC (1 << 14)
291 #define QH_EPCHAR_EPS_MASK 0x00003000
292 #define QH_EPCHAR_EPS_SH 12
293 #define EHCI_QH_EPS_FULL 0
294 #define EHCI_QH_EPS_LOW 1
295 #define EHCI_QH_EPS_HIGH 2
296 #define EHCI_QH_EPS_RESERVED 3
297
298 #define QH_EPCHAR_EP_MASK 0x00000f00
299 #define QH_EPCHAR_EP_SH 8
300 #define QH_EPCHAR_I (1 << 7)
301 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f
302 #define QH_EPCHAR_DEVADDR_SH 0
303
304 /* endpoint capabilities */
305 uint32_t epcap;
306 #define QH_EPCAP_MULT_MASK 0xc0000000
307 #define QH_EPCAP_MULT_SH 30
308 #define QH_EPCAP_PORTNUM_MASK 0x3f800000
309 #define QH_EPCAP_PORTNUM_SH 23
310 #define QH_EPCAP_HUBADDR_MASK 0x007f0000
311 #define QH_EPCAP_HUBADDR_SH 16
312 #define QH_EPCAP_CMASK_MASK 0x0000ff00
313 #define QH_EPCAP_CMASK_SH 8
314 #define QH_EPCAP_SMASK_MASK 0x000000ff
315 #define QH_EPCAP_SMASK_SH 0
316
317 uint32_t current_qtd; // Standard next link pointer
318 uint32_t next_qtd; // Standard next link pointer
319 uint32_t altnext_qtd;
320 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
321 #define QH_ALTNEXT_NAKCNT_SH 1
322
323 uint32_t token; // Same as QTD token
324 uint32_t bufptr[5]; // Standard buffer pointer
325 #define BUFPTR_CPROGMASK_MASK 0x000000ff
326 #define BUFPTR_FRAMETAG_MASK 0x0000001f
327 #define BUFPTR_SBYTES_MASK 0x00000fe0
328 #define BUFPTR_SBYTES_SH 5
329 } EHCIqh;
330
331 /* EHCI spec version 1.0 Section 3.7
332 */
333 typedef struct EHCIfstn {
334 uint32_t next; // Standard next link pointer
335 uint32_t backptr; // Standard next link pointer
336 } EHCIfstn;
337
338 typedef struct EHCIQueue EHCIQueue;
339 typedef struct EHCIState EHCIState;
340
341 enum async_state {
342 EHCI_ASYNC_NONE = 0,
343 EHCI_ASYNC_INFLIGHT,
344 EHCI_ASYNC_FINISHED,
345 };
346
347 struct EHCIQueue {
348 EHCIState *ehci;
349 QTAILQ_ENTRY(EHCIQueue) next;
350 uint32_t seen;
351 uint64_t ts;
352
353 /* cached data from guest - needs to be flushed
354 * when guest removes an entry (doorbell, handshake sequence)
355 */
356 EHCIqh qh; // copy of current QH (being worked on)
357 uint32_t qhaddr; // address QH read from
358 EHCIqtd qtd; // copy of current QTD (being worked on)
359 uint32_t qtdaddr; // address QTD read from
360
361 USBPacket packet;
362 QEMUSGList sgl;
363 int pid;
364 uint32_t tbytes;
365 enum async_state async;
366 int usb_status;
367 };
368
369 typedef QTAILQ_HEAD(EHCIQueueHead, EHCIQueue) EHCIQueueHead;
370
371 struct EHCIState {
372 PCIDevice dev;
373 USBBus bus;
374 qemu_irq irq;
375 MemoryRegion mem;
376 int companion_count;
377
378 /* properties */
379 uint32_t freq;
380 uint32_t maxframes;
381
382 /*
383 * EHCI spec version 1.0 Section 2.3
384 * Host Controller Operational Registers
385 */
386 union {
387 uint8_t mmio[MMIO_SIZE];
388 struct {
389 uint8_t cap[OPREGBASE];
390 uint32_t usbcmd;
391 uint32_t usbsts;
392 uint32_t usbintr;
393 uint32_t frindex;
394 uint32_t ctrldssegment;
395 uint32_t periodiclistbase;
396 uint32_t asynclistaddr;
397 uint32_t notused[9];
398 uint32_t configflag;
399 uint32_t portsc[NB_PORTS];
400 };
401 };
402
403 /*
404 * Internal states, shadow registers, etc
405 */
406 uint32_t sofv;
407 QEMUTimer *frame_timer;
408 int attach_poll_counter;
409 int astate; // Current state in asynchronous schedule
410 int pstate; // Current state in periodic schedule
411 USBPort ports[NB_PORTS];
412 USBPort *companion_ports[NB_PORTS];
413 uint32_t usbsts_pending;
414 EHCIQueueHead aqueues;
415 EHCIQueueHead pqueues;
416
417 uint32_t a_fetch_addr; // which address to look at next
418 uint32_t p_fetch_addr; // which address to look at next
419
420 USBPacket ipacket;
421 QEMUSGList isgl;
422 int isoch_pause;
423
424 uint64_t last_run_ns;
425 };
426
427 #define SET_LAST_RUN_CLOCK(s) \
428 (s)->last_run_ns = qemu_get_clock_ns(vm_clock);
429
430 /* nifty macros from Arnon's EHCI version */
431 #define get_field(data, field) \
432 (((data) & field##_MASK) >> field##_SH)
433
434 #define set_field(data, newval, field) do { \
435 uint32_t val = *data; \
436 val &= ~ field##_MASK; \
437 val |= ((newval) << field##_SH) & field##_MASK; \
438 *data = val; \
439 } while(0)
440
441 static const char *ehci_state_names[] = {
442 [EST_INACTIVE] = "INACTIVE",
443 [EST_ACTIVE] = "ACTIVE",
444 [EST_EXECUTING] = "EXECUTING",
445 [EST_SLEEPING] = "SLEEPING",
446 [EST_WAITLISTHEAD] = "WAITLISTHEAD",
447 [EST_FETCHENTRY] = "FETCH ENTRY",
448 [EST_FETCHQH] = "FETCH QH",
449 [EST_FETCHITD] = "FETCH ITD",
450 [EST_ADVANCEQUEUE] = "ADVANCEQUEUE",
451 [EST_FETCHQTD] = "FETCH QTD",
452 [EST_EXECUTE] = "EXECUTE",
453 [EST_WRITEBACK] = "WRITEBACK",
454 [EST_HORIZONTALQH] = "HORIZONTALQH",
455 };
456
457 static const char *ehci_mmio_names[] = {
458 [CAPLENGTH] = "CAPLENGTH",
459 [HCIVERSION] = "HCIVERSION",
460 [HCSPARAMS] = "HCSPARAMS",
461 [HCCPARAMS] = "HCCPARAMS",
462 [USBCMD] = "USBCMD",
463 [USBSTS] = "USBSTS",
464 [USBINTR] = "USBINTR",
465 [FRINDEX] = "FRINDEX",
466 [PERIODICLISTBASE] = "P-LIST BASE",
467 [ASYNCLISTADDR] = "A-LIST ADDR",
468 [PORTSC_BEGIN] = "PORTSC #0",
469 [PORTSC_BEGIN + 4] = "PORTSC #1",
470 [PORTSC_BEGIN + 8] = "PORTSC #2",
471 [PORTSC_BEGIN + 12] = "PORTSC #3",
472 [PORTSC_BEGIN + 16] = "PORTSC #4",
473 [PORTSC_BEGIN + 20] = "PORTSC #5",
474 [CONFIGFLAG] = "CONFIGFLAG",
475 };
476
477 static const char *nr2str(const char **n, size_t len, uint32_t nr)
478 {
479 if (nr < len && n[nr] != NULL) {
480 return n[nr];
481 } else {
482 return "unknown";
483 }
484 }
485
486 static const char *state2str(uint32_t state)
487 {
488 return nr2str(ehci_state_names, ARRAY_SIZE(ehci_state_names), state);
489 }
490
491 static const char *addr2str(target_phys_addr_t addr)
492 {
493 return nr2str(ehci_mmio_names, ARRAY_SIZE(ehci_mmio_names), addr);
494 }
495
496 static void ehci_trace_usbsts(uint32_t mask, int state)
497 {
498 /* interrupts */
499 if (mask & USBSTS_INT) {
500 trace_usb_ehci_usbsts("INT", state);
501 }
502 if (mask & USBSTS_ERRINT) {
503 trace_usb_ehci_usbsts("ERRINT", state);
504 }
505 if (mask & USBSTS_PCD) {
506 trace_usb_ehci_usbsts("PCD", state);
507 }
508 if (mask & USBSTS_FLR) {
509 trace_usb_ehci_usbsts("FLR", state);
510 }
511 if (mask & USBSTS_HSE) {
512 trace_usb_ehci_usbsts("HSE", state);
513 }
514 if (mask & USBSTS_IAA) {
515 trace_usb_ehci_usbsts("IAA", state);
516 }
517
518 /* status */
519 if (mask & USBSTS_HALT) {
520 trace_usb_ehci_usbsts("HALT", state);
521 }
522 if (mask & USBSTS_REC) {
523 trace_usb_ehci_usbsts("REC", state);
524 }
525 if (mask & USBSTS_PSS) {
526 trace_usb_ehci_usbsts("PSS", state);
527 }
528 if (mask & USBSTS_ASS) {
529 trace_usb_ehci_usbsts("ASS", state);
530 }
531 }
532
533 static inline void ehci_set_usbsts(EHCIState *s, int mask)
534 {
535 if ((s->usbsts & mask) == mask) {
536 return;
537 }
538 ehci_trace_usbsts(mask, 1);
539 s->usbsts |= mask;
540 }
541
542 static inline void ehci_clear_usbsts(EHCIState *s, int mask)
543 {
544 if ((s->usbsts & mask) == 0) {
545 return;
546 }
547 ehci_trace_usbsts(mask, 0);
548 s->usbsts &= ~mask;
549 }
550
551 static inline void ehci_set_interrupt(EHCIState *s, int intr)
552 {
553 int level = 0;
554
555 // TODO honour interrupt threshold requests
556
557 ehci_set_usbsts(s, intr);
558
559 if ((s->usbsts & USBINTR_MASK) & s->usbintr) {
560 level = 1;
561 }
562
563 qemu_set_irq(s->irq, level);
564 }
565
566 static inline void ehci_record_interrupt(EHCIState *s, int intr)
567 {
568 s->usbsts_pending |= intr;
569 }
570
571 static inline void ehci_commit_interrupt(EHCIState *s)
572 {
573 if (!s->usbsts_pending) {
574 return;
575 }
576 ehci_set_interrupt(s, s->usbsts_pending);
577 s->usbsts_pending = 0;
578 }
579
580 static void ehci_set_state(EHCIState *s, int async, int state)
581 {
582 if (async) {
583 trace_usb_ehci_state("async", state2str(state));
584 s->astate = state;
585 } else {
586 trace_usb_ehci_state("periodic", state2str(state));
587 s->pstate = state;
588 }
589 }
590
591 static int ehci_get_state(EHCIState *s, int async)
592 {
593 return async ? s->astate : s->pstate;
594 }
595
596 static void ehci_set_fetch_addr(EHCIState *s, int async, uint32_t addr)
597 {
598 if (async) {
599 s->a_fetch_addr = addr;
600 } else {
601 s->p_fetch_addr = addr;
602 }
603 }
604
605 static int ehci_get_fetch_addr(EHCIState *s, int async)
606 {
607 return async ? s->a_fetch_addr : s->p_fetch_addr;
608 }
609
610 static void ehci_trace_qh(EHCIQueue *q, target_phys_addr_t addr, EHCIqh *qh)
611 {
612 /* need three here due to argument count limits */
613 trace_usb_ehci_qh_ptrs(q, addr, qh->next,
614 qh->current_qtd, qh->next_qtd, qh->altnext_qtd);
615 trace_usb_ehci_qh_fields(addr,
616 get_field(qh->epchar, QH_EPCHAR_RL),
617 get_field(qh->epchar, QH_EPCHAR_MPLEN),
618 get_field(qh->epchar, QH_EPCHAR_EPS),
619 get_field(qh->epchar, QH_EPCHAR_EP),
620 get_field(qh->epchar, QH_EPCHAR_DEVADDR));
621 trace_usb_ehci_qh_bits(addr,
622 (bool)(qh->epchar & QH_EPCHAR_C),
623 (bool)(qh->epchar & QH_EPCHAR_H),
624 (bool)(qh->epchar & QH_EPCHAR_DTC),
625 (bool)(qh->epchar & QH_EPCHAR_I));
626 }
627
628 static void ehci_trace_qtd(EHCIQueue *q, target_phys_addr_t addr, EHCIqtd *qtd)
629 {
630 /* need three here due to argument count limits */
631 trace_usb_ehci_qtd_ptrs(q, addr, qtd->next, qtd->altnext);
632 trace_usb_ehci_qtd_fields(addr,
633 get_field(qtd->token, QTD_TOKEN_TBYTES),
634 get_field(qtd->token, QTD_TOKEN_CPAGE),
635 get_field(qtd->token, QTD_TOKEN_CERR),
636 get_field(qtd->token, QTD_TOKEN_PID));
637 trace_usb_ehci_qtd_bits(addr,
638 (bool)(qtd->token & QTD_TOKEN_IOC),
639 (bool)(qtd->token & QTD_TOKEN_ACTIVE),
640 (bool)(qtd->token & QTD_TOKEN_HALT),
641 (bool)(qtd->token & QTD_TOKEN_BABBLE),
642 (bool)(qtd->token & QTD_TOKEN_XACTERR));
643 }
644
645 static void ehci_trace_itd(EHCIState *s, target_phys_addr_t addr, EHCIitd *itd)
646 {
647 trace_usb_ehci_itd(addr, itd->next,
648 get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT),
649 get_field(itd->bufptr[2], ITD_BUFPTR_MULT),
650 get_field(itd->bufptr[0], ITD_BUFPTR_EP),
651 get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR));
652 }
653
654 static void ehci_trace_sitd(EHCIState *s, target_phys_addr_t addr,
655 EHCIsitd *sitd)
656 {
657 trace_usb_ehci_sitd(addr, sitd->next,
658 (bool)(sitd->results & SITD_RESULTS_ACTIVE));
659 }
660
661 /* queue management */
662
663 static EHCIQueue *ehci_alloc_queue(EHCIState *ehci, int async)
664 {
665 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
666 EHCIQueue *q;
667
668 q = g_malloc0(sizeof(*q));
669 q->ehci = ehci;
670 QTAILQ_INSERT_HEAD(head, q, next);
671 trace_usb_ehci_queue_action(q, "alloc");
672 return q;
673 }
674
675 static void ehci_free_queue(EHCIQueue *q, int async)
676 {
677 EHCIQueueHead *head = async ? &q->ehci->aqueues : &q->ehci->pqueues;
678 trace_usb_ehci_queue_action(q, "free");
679 if (q->async == EHCI_ASYNC_INFLIGHT) {
680 usb_cancel_packet(&q->packet);
681 }
682 QTAILQ_REMOVE(head, q, next);
683 g_free(q);
684 }
685
686 static EHCIQueue *ehci_find_queue_by_qh(EHCIState *ehci, uint32_t addr,
687 int async)
688 {
689 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
690 EHCIQueue *q;
691
692 QTAILQ_FOREACH(q, head, next) {
693 if (addr == q->qhaddr) {
694 return q;
695 }
696 }
697 return NULL;
698 }
699
700 static void ehci_queues_rip_unused(EHCIState *ehci, int async, int flush)
701 {
702 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
703 EHCIQueue *q, *tmp;
704
705 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
706 if (q->seen) {
707 q->seen = 0;
708 q->ts = ehci->last_run_ns;
709 continue;
710 }
711 if (!flush && ehci->last_run_ns < q->ts + 250000000) {
712 /* allow 0.25 sec idle */
713 continue;
714 }
715 ehci_free_queue(q, async);
716 }
717 }
718
719 static void ehci_queues_rip_device(EHCIState *ehci, USBDevice *dev, int async)
720 {
721 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
722 EHCIQueue *q, *tmp;
723
724 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
725 if (!usb_packet_is_inflight(&q->packet) ||
726 q->packet.ep->dev != dev) {
727 continue;
728 }
729 ehci_free_queue(q, async);
730 }
731 }
732
733 static void ehci_queues_rip_all(EHCIState *ehci, int async)
734 {
735 EHCIQueueHead *head = async ? &ehci->aqueues : &ehci->pqueues;
736 EHCIQueue *q, *tmp;
737
738 QTAILQ_FOREACH_SAFE(q, head, next, tmp) {
739 ehci_free_queue(q, async);
740 }
741 }
742
743 /* Attach or detach a device on root hub */
744
745 static void ehci_attach(USBPort *port)
746 {
747 EHCIState *s = port->opaque;
748 uint32_t *portsc = &s->portsc[port->index];
749
750 trace_usb_ehci_port_attach(port->index, port->dev->product_desc);
751
752 if (*portsc & PORTSC_POWNER) {
753 USBPort *companion = s->companion_ports[port->index];
754 companion->dev = port->dev;
755 companion->ops->attach(companion);
756 return;
757 }
758
759 *portsc |= PORTSC_CONNECT;
760 *portsc |= PORTSC_CSC;
761
762 ehci_set_interrupt(s, USBSTS_PCD);
763 }
764
765 static void ehci_detach(USBPort *port)
766 {
767 EHCIState *s = port->opaque;
768 uint32_t *portsc = &s->portsc[port->index];
769
770 trace_usb_ehci_port_detach(port->index);
771
772 if (*portsc & PORTSC_POWNER) {
773 USBPort *companion = s->companion_ports[port->index];
774 companion->ops->detach(companion);
775 companion->dev = NULL;
776 /*
777 * EHCI spec 4.2.2: "When a disconnect occurs... On the event,
778 * the port ownership is returned immediately to the EHCI controller."
779 */
780 *portsc &= ~PORTSC_POWNER;
781 return;
782 }
783
784 ehci_queues_rip_device(s, port->dev, 0);
785 ehci_queues_rip_device(s, port->dev, 1);
786
787 *portsc &= ~(PORTSC_CONNECT|PORTSC_PED);
788 *portsc |= PORTSC_CSC;
789
790 ehci_set_interrupt(s, USBSTS_PCD);
791 }
792
793 static void ehci_child_detach(USBPort *port, USBDevice *child)
794 {
795 EHCIState *s = port->opaque;
796 uint32_t portsc = s->portsc[port->index];
797
798 if (portsc & PORTSC_POWNER) {
799 USBPort *companion = s->companion_ports[port->index];
800 companion->ops->child_detach(companion, child);
801 companion->dev = NULL;
802 return;
803 }
804
805 ehci_queues_rip_device(s, child, 0);
806 ehci_queues_rip_device(s, child, 1);
807 }
808
809 static void ehci_wakeup(USBPort *port)
810 {
811 EHCIState *s = port->opaque;
812 uint32_t portsc = s->portsc[port->index];
813
814 if (portsc & PORTSC_POWNER) {
815 USBPort *companion = s->companion_ports[port->index];
816 if (companion->ops->wakeup) {
817 companion->ops->wakeup(companion);
818 }
819 }
820 }
821
822 static int ehci_register_companion(USBBus *bus, USBPort *ports[],
823 uint32_t portcount, uint32_t firstport)
824 {
825 EHCIState *s = container_of(bus, EHCIState, bus);
826 uint32_t i;
827
828 if (firstport + portcount > NB_PORTS) {
829 qerror_report(QERR_INVALID_PARAMETER_VALUE, "firstport",
830 "firstport on masterbus");
831 error_printf_unless_qmp(
832 "firstport value of %u makes companion take ports %u - %u, which "
833 "is outside of the valid range of 0 - %u\n", firstport, firstport,
834 firstport + portcount - 1, NB_PORTS - 1);
835 return -1;
836 }
837
838 for (i = 0; i < portcount; i++) {
839 if (s->companion_ports[firstport + i]) {
840 qerror_report(QERR_INVALID_PARAMETER_VALUE, "masterbus",
841 "an USB masterbus");
842 error_printf_unless_qmp(
843 "port %u on masterbus %s already has a companion assigned\n",
844 firstport + i, bus->qbus.name);
845 return -1;
846 }
847 }
848
849 for (i = 0; i < portcount; i++) {
850 s->companion_ports[firstport + i] = ports[i];
851 s->ports[firstport + i].speedmask |=
852 USB_SPEED_MASK_LOW | USB_SPEED_MASK_FULL;
853 /* Ensure devs attached before the initial reset go to the companion */
854 s->portsc[firstport + i] = PORTSC_POWNER;
855 }
856
857 s->companion_count++;
858 s->mmio[0x05] = (s->companion_count << 4) | portcount;
859
860 return 0;
861 }
862
863 static USBDevice *ehci_find_device(EHCIState *ehci, uint8_t addr)
864 {
865 USBDevice *dev;
866 USBPort *port;
867 int i;
868
869 for (i = 0; i < NB_PORTS; i++) {
870 port = &ehci->ports[i];
871 if (!(ehci->portsc[i] & PORTSC_PED)) {
872 DPRINTF("Port %d not enabled\n", i);
873 continue;
874 }
875 dev = usb_find_device(port, addr);
876 if (dev != NULL) {
877 return dev;
878 }
879 }
880 return NULL;
881 }
882
883 /* 4.1 host controller initialization */
884 static void ehci_reset(void *opaque)
885 {
886 EHCIState *s = opaque;
887 int i;
888 USBDevice *devs[NB_PORTS];
889
890 trace_usb_ehci_reset();
891
892 /*
893 * Do the detach before touching portsc, so that it correctly gets send to
894 * us or to our companion based on PORTSC_POWNER before the reset.
895 */
896 for(i = 0; i < NB_PORTS; i++) {
897 devs[i] = s->ports[i].dev;
898 if (devs[i] && devs[i]->attached) {
899 usb_detach(&s->ports[i]);
900 }
901 }
902
903 memset(&s->mmio[OPREGBASE], 0x00, MMIO_SIZE - OPREGBASE);
904
905 s->usbcmd = NB_MAXINTRATE << USBCMD_ITC_SH;
906 s->usbsts = USBSTS_HALT;
907
908 s->astate = EST_INACTIVE;
909 s->pstate = EST_INACTIVE;
910 s->isoch_pause = -1;
911 s->attach_poll_counter = 0;
912
913 for(i = 0; i < NB_PORTS; i++) {
914 if (s->companion_ports[i]) {
915 s->portsc[i] = PORTSC_POWNER | PORTSC_PPOWER;
916 } else {
917 s->portsc[i] = PORTSC_PPOWER;
918 }
919 if (devs[i] && devs[i]->attached) {
920 usb_attach(&s->ports[i]);
921 usb_device_reset(devs[i]);
922 }
923 }
924 ehci_queues_rip_all(s, 0);
925 ehci_queues_rip_all(s, 1);
926 qemu_del_timer(s->frame_timer);
927 }
928
929 static uint32_t ehci_mem_readb(void *ptr, target_phys_addr_t addr)
930 {
931 EHCIState *s = ptr;
932 uint32_t val;
933
934 val = s->mmio[addr];
935
936 return val;
937 }
938
939 static uint32_t ehci_mem_readw(void *ptr, target_phys_addr_t addr)
940 {
941 EHCIState *s = ptr;
942 uint32_t val;
943
944 val = s->mmio[addr] | (s->mmio[addr+1] << 8);
945
946 return val;
947 }
948
949 static uint32_t ehci_mem_readl(void *ptr, target_phys_addr_t addr)
950 {
951 EHCIState *s = ptr;
952 uint32_t val;
953
954 val = s->mmio[addr] | (s->mmio[addr+1] << 8) |
955 (s->mmio[addr+2] << 16) | (s->mmio[addr+3] << 24);
956
957 trace_usb_ehci_mmio_readl(addr, addr2str(addr), val);
958 return val;
959 }
960
961 static void ehci_mem_writeb(void *ptr, target_phys_addr_t addr, uint32_t val)
962 {
963 fprintf(stderr, "EHCI doesn't handle byte writes to MMIO\n");
964 exit(1);
965 }
966
967 static void ehci_mem_writew(void *ptr, target_phys_addr_t addr, uint32_t val)
968 {
969 fprintf(stderr, "EHCI doesn't handle 16-bit writes to MMIO\n");
970 exit(1);
971 }
972
973 static void handle_port_owner_write(EHCIState *s, int port, uint32_t owner)
974 {
975 USBDevice *dev = s->ports[port].dev;
976 uint32_t *portsc = &s->portsc[port];
977 uint32_t orig;
978
979 if (s->companion_ports[port] == NULL)
980 return;
981
982 owner = owner & PORTSC_POWNER;
983 orig = *portsc & PORTSC_POWNER;
984
985 if (!(owner ^ orig)) {
986 return;
987 }
988
989 if (dev && dev->attached) {
990 usb_detach(&s->ports[port]);
991 }
992
993 *portsc &= ~PORTSC_POWNER;
994 *portsc |= owner;
995
996 if (dev && dev->attached) {
997 usb_attach(&s->ports[port]);
998 }
999 }
1000
1001 static void handle_port_status_write(EHCIState *s, int port, uint32_t val)
1002 {
1003 uint32_t *portsc = &s->portsc[port];
1004 USBDevice *dev = s->ports[port].dev;
1005
1006 /* Clear rwc bits */
1007 *portsc &= ~(val & PORTSC_RWC_MASK);
1008 /* The guest may clear, but not set the PED bit */
1009 *portsc &= val | ~PORTSC_PED;
1010 /* POWNER is masked out by RO_MASK as it is RO when we've no companion */
1011 handle_port_owner_write(s, port, val);
1012 /* And finally apply RO_MASK */
1013 val &= PORTSC_RO_MASK;
1014
1015 if ((val & PORTSC_PRESET) && !(*portsc & PORTSC_PRESET)) {
1016 trace_usb_ehci_port_reset(port, 1);
1017 }
1018
1019 if (!(val & PORTSC_PRESET) &&(*portsc & PORTSC_PRESET)) {
1020 trace_usb_ehci_port_reset(port, 0);
1021 if (dev && dev->attached) {
1022 usb_port_reset(&s->ports[port]);
1023 *portsc &= ~PORTSC_CSC;
1024 }
1025
1026 /*
1027 * Table 2.16 Set the enable bit(and enable bit change) to indicate
1028 * to SW that this port has a high speed device attached
1029 */
1030 if (dev && dev->attached && (dev->speedmask & USB_SPEED_MASK_HIGH)) {
1031 val |= PORTSC_PED;
1032 }
1033 }
1034
1035 *portsc &= ~PORTSC_RO_MASK;
1036 *portsc |= val;
1037 }
1038
1039 static void ehci_mem_writel(void *ptr, target_phys_addr_t addr, uint32_t val)
1040 {
1041 EHCIState *s = ptr;
1042 uint32_t *mmio = (uint32_t *)(&s->mmio[addr]);
1043 uint32_t old = *mmio;
1044 int i;
1045
1046 trace_usb_ehci_mmio_writel(addr, addr2str(addr), val);
1047
1048 /* Only aligned reads are allowed on OHCI */
1049 if (addr & 3) {
1050 fprintf(stderr, "usb-ehci: Mis-aligned write to addr 0x"
1051 TARGET_FMT_plx "\n", addr);
1052 return;
1053 }
1054
1055 if (addr >= PORTSC && addr < PORTSC + 4 * NB_PORTS) {
1056 handle_port_status_write(s, (addr-PORTSC)/4, val);
1057 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
1058 return;
1059 }
1060
1061 if (addr < OPREGBASE) {
1062 fprintf(stderr, "usb-ehci: write attempt to read-only register"
1063 TARGET_FMT_plx "\n", addr);
1064 return;
1065 }
1066
1067
1068 /* Do any register specific pre-write processing here. */
1069 switch(addr) {
1070 case USBCMD:
1071 if ((val & USBCMD_RUNSTOP) && !(s->usbcmd & USBCMD_RUNSTOP)) {
1072 qemu_mod_timer(s->frame_timer, qemu_get_clock_ns(vm_clock));
1073 SET_LAST_RUN_CLOCK(s);
1074 ehci_clear_usbsts(s, USBSTS_HALT);
1075 }
1076
1077 if (!(val & USBCMD_RUNSTOP) && (s->usbcmd & USBCMD_RUNSTOP)) {
1078 qemu_del_timer(s->frame_timer);
1079 ehci_queues_rip_all(s, 0);
1080 ehci_queues_rip_all(s, 1);
1081 ehci_set_usbsts(s, USBSTS_HALT);
1082 }
1083
1084 if (val & USBCMD_HCRESET) {
1085 ehci_reset(s);
1086 val = s->usbcmd;
1087 }
1088
1089 /* not supporting dynamic frame list size at the moment */
1090 if ((val & USBCMD_FLS) && !(s->usbcmd & USBCMD_FLS)) {
1091 fprintf(stderr, "attempt to set frame list size -- value %d\n",
1092 val & USBCMD_FLS);
1093 val &= ~USBCMD_FLS;
1094 }
1095 break;
1096
1097 case USBSTS:
1098 val &= USBSTS_RO_MASK; // bits 6 thru 31 are RO
1099 ehci_clear_usbsts(s, val); // bits 0 thru 5 are R/WC
1100 val = s->usbsts;
1101 ehci_set_interrupt(s, 0);
1102 break;
1103
1104 case USBINTR:
1105 val &= USBINTR_MASK;
1106 break;
1107
1108 case FRINDEX:
1109 s->sofv = val >> 3;
1110 break;
1111
1112 case CONFIGFLAG:
1113 val &= 0x1;
1114 if (val) {
1115 for(i = 0; i < NB_PORTS; i++)
1116 handle_port_owner_write(s, i, 0);
1117 }
1118 break;
1119
1120 case PERIODICLISTBASE:
1121 if ((s->usbcmd & USBCMD_PSE) && (s->usbcmd & USBCMD_RUNSTOP)) {
1122 fprintf(stderr,
1123 "ehci: PERIODIC list base register set while periodic schedule\n"
1124 " is enabled and HC is enabled\n");
1125 }
1126 break;
1127
1128 case ASYNCLISTADDR:
1129 if ((s->usbcmd & USBCMD_ASE) && (s->usbcmd & USBCMD_RUNSTOP)) {
1130 fprintf(stderr,
1131 "ehci: ASYNC list address register set while async schedule\n"
1132 " is enabled and HC is enabled\n");
1133 }
1134 break;
1135 }
1136
1137 *mmio = val;
1138 trace_usb_ehci_mmio_change(addr, addr2str(addr), *mmio, old);
1139 }
1140
1141
1142 // TODO : Put in common header file, duplication from usb-ohci.c
1143
1144 /* Get an array of dwords from main memory */
1145 static inline int get_dwords(EHCIState *ehci, uint32_t addr,
1146 uint32_t *buf, int num)
1147 {
1148 int i;
1149
1150 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1151 pci_dma_read(&ehci->dev, addr, buf, sizeof(*buf));
1152 *buf = le32_to_cpu(*buf);
1153 }
1154
1155 return 1;
1156 }
1157
1158 /* Put an array of dwords in to main memory */
1159 static inline int put_dwords(EHCIState *ehci, uint32_t addr,
1160 uint32_t *buf, int num)
1161 {
1162 int i;
1163
1164 for(i = 0; i < num; i++, buf++, addr += sizeof(*buf)) {
1165 uint32_t tmp = cpu_to_le32(*buf);
1166 pci_dma_write(&ehci->dev, addr, &tmp, sizeof(tmp));
1167 }
1168
1169 return 1;
1170 }
1171
1172 // 4.10.2
1173
1174 static int ehci_qh_do_overlay(EHCIQueue *q)
1175 {
1176 int i;
1177 int dtoggle;
1178 int ping;
1179 int eps;
1180 int reload;
1181
1182 // remember values in fields to preserve in qh after overlay
1183
1184 dtoggle = q->qh.token & QTD_TOKEN_DTOGGLE;
1185 ping = q->qh.token & QTD_TOKEN_PING;
1186
1187 q->qh.current_qtd = q->qtdaddr;
1188 q->qh.next_qtd = q->qtd.next;
1189 q->qh.altnext_qtd = q->qtd.altnext;
1190 q->qh.token = q->qtd.token;
1191
1192
1193 eps = get_field(q->qh.epchar, QH_EPCHAR_EPS);
1194 if (eps == EHCI_QH_EPS_HIGH) {
1195 q->qh.token &= ~QTD_TOKEN_PING;
1196 q->qh.token |= ping;
1197 }
1198
1199 reload = get_field(q->qh.epchar, QH_EPCHAR_RL);
1200 set_field(&q->qh.altnext_qtd, reload, QH_ALTNEXT_NAKCNT);
1201
1202 for (i = 0; i < 5; i++) {
1203 q->qh.bufptr[i] = q->qtd.bufptr[i];
1204 }
1205
1206 if (!(q->qh.epchar & QH_EPCHAR_DTC)) {
1207 // preserve QH DT bit
1208 q->qh.token &= ~QTD_TOKEN_DTOGGLE;
1209 q->qh.token |= dtoggle;
1210 }
1211
1212 q->qh.bufptr[1] &= ~BUFPTR_CPROGMASK_MASK;
1213 q->qh.bufptr[2] &= ~BUFPTR_FRAMETAG_MASK;
1214
1215 put_dwords(q->ehci, NLPTR_GET(q->qhaddr), (uint32_t *) &q->qh,
1216 sizeof(EHCIqh) >> 2);
1217
1218 return 0;
1219 }
1220
1221 static int ehci_init_transfer(EHCIQueue *q)
1222 {
1223 uint32_t cpage, offset, bytes, plen;
1224 dma_addr_t page;
1225
1226 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
1227 bytes = get_field(q->qh.token, QTD_TOKEN_TBYTES);
1228 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
1229 pci_dma_sglist_init(&q->sgl, &q->ehci->dev, 5);
1230
1231 while (bytes > 0) {
1232 if (cpage > 4) {
1233 fprintf(stderr, "cpage out of range (%d)\n", cpage);
1234 return USB_RET_PROCERR;
1235 }
1236
1237 page = q->qh.bufptr[cpage] & QTD_BUFPTR_MASK;
1238 page += offset;
1239 plen = bytes;
1240 if (plen > 4096 - offset) {
1241 plen = 4096 - offset;
1242 offset = 0;
1243 cpage++;
1244 }
1245
1246 qemu_sglist_add(&q->sgl, page, plen);
1247 bytes -= plen;
1248 }
1249 return 0;
1250 }
1251
1252 static void ehci_finish_transfer(EHCIQueue *q, int status)
1253 {
1254 uint32_t cpage, offset;
1255
1256 qemu_sglist_destroy(&q->sgl);
1257
1258 if (status > 0) {
1259 /* update cpage & offset */
1260 cpage = get_field(q->qh.token, QTD_TOKEN_CPAGE);
1261 offset = q->qh.bufptr[0] & ~QTD_BUFPTR_MASK;
1262
1263 offset += status;
1264 cpage += offset >> QTD_BUFPTR_SH;
1265 offset &= ~QTD_BUFPTR_MASK;
1266
1267 set_field(&q->qh.token, cpage, QTD_TOKEN_CPAGE);
1268 q->qh.bufptr[0] &= QTD_BUFPTR_MASK;
1269 q->qh.bufptr[0] |= offset;
1270 }
1271 }
1272
1273 static void ehci_async_complete_packet(USBPort *port, USBPacket *packet)
1274 {
1275 EHCIQueue *q;
1276 EHCIState *s = port->opaque;
1277 uint32_t portsc = s->portsc[port->index];
1278
1279 if (portsc & PORTSC_POWNER) {
1280 USBPort *companion = s->companion_ports[port->index];
1281 companion->ops->complete(companion, packet);
1282 return;
1283 }
1284
1285 q = container_of(packet, EHCIQueue, packet);
1286 trace_usb_ehci_queue_action(q, "wakeup");
1287 assert(q->async == EHCI_ASYNC_INFLIGHT);
1288 q->async = EHCI_ASYNC_FINISHED;
1289 q->usb_status = packet->result;
1290 }
1291
1292 static void ehci_execute_complete(EHCIQueue *q)
1293 {
1294 assert(q->async != EHCI_ASYNC_INFLIGHT);
1295 q->async = EHCI_ASYNC_NONE;
1296
1297 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1298 q->qhaddr, q->qh.next, q->qtdaddr, q->usb_status);
1299
1300 if (q->usb_status < 0) {
1301 switch(q->usb_status) {
1302 case USB_RET_IOERROR:
1303 case USB_RET_NODEV:
1304 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_XACTERR);
1305 set_field(&q->qh.token, 0, QTD_TOKEN_CERR);
1306 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1307 break;
1308 case USB_RET_STALL:
1309 q->qh.token |= QTD_TOKEN_HALT;
1310 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1311 break;
1312 case USB_RET_NAK:
1313 set_field(&q->qh.altnext_qtd, 0, QH_ALTNEXT_NAKCNT);
1314 return; /* We're not done yet with this transaction */
1315 case USB_RET_BABBLE:
1316 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE);
1317 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1318 break;
1319 default:
1320 /* should not be triggerable */
1321 fprintf(stderr, "USB invalid response %d to handle\n", q->usb_status);
1322 assert(0);
1323 break;
1324 }
1325 } else if ((q->usb_status > q->tbytes) && (q->pid == USB_TOKEN_IN)) {
1326 q->usb_status = USB_RET_BABBLE;
1327 q->qh.token |= (QTD_TOKEN_HALT | QTD_TOKEN_BABBLE);
1328 ehci_record_interrupt(q->ehci, USBSTS_ERRINT);
1329 } else {
1330 // TODO check 4.12 for splits
1331
1332 if (q->tbytes && q->pid == USB_TOKEN_IN) {
1333 q->tbytes -= q->usb_status;
1334 } else {
1335 q->tbytes = 0;
1336 }
1337
1338 DPRINTF("updating tbytes to %d\n", q->tbytes);
1339 set_field(&q->qh.token, q->tbytes, QTD_TOKEN_TBYTES);
1340 }
1341 ehci_finish_transfer(q, q->usb_status);
1342 usb_packet_unmap(&q->packet);
1343
1344 q->qh.token ^= QTD_TOKEN_DTOGGLE;
1345 q->qh.token &= ~QTD_TOKEN_ACTIVE;
1346
1347 if (q->qh.token & QTD_TOKEN_IOC) {
1348 ehci_record_interrupt(q->ehci, USBSTS_INT);
1349 }
1350 }
1351
1352 // 4.10.3
1353
1354 static int ehci_execute(EHCIQueue *q)
1355 {
1356 USBDevice *dev;
1357 USBEndpoint *ep;
1358 int ret;
1359 int endp;
1360 int devadr;
1361
1362 if ( !(q->qh.token & QTD_TOKEN_ACTIVE)) {
1363 fprintf(stderr, "Attempting to execute inactive QH\n");
1364 return USB_RET_PROCERR;
1365 }
1366
1367 q->tbytes = (q->qh.token & QTD_TOKEN_TBYTES_MASK) >> QTD_TOKEN_TBYTES_SH;
1368 if (q->tbytes > BUFF_SIZE) {
1369 fprintf(stderr, "Request for more bytes than allowed\n");
1370 return USB_RET_PROCERR;
1371 }
1372
1373 q->pid = (q->qh.token & QTD_TOKEN_PID_MASK) >> QTD_TOKEN_PID_SH;
1374 switch(q->pid) {
1375 case 0: q->pid = USB_TOKEN_OUT; break;
1376 case 1: q->pid = USB_TOKEN_IN; break;
1377 case 2: q->pid = USB_TOKEN_SETUP; break;
1378 default: fprintf(stderr, "bad token\n"); break;
1379 }
1380
1381 if (ehci_init_transfer(q) != 0) {
1382 return USB_RET_PROCERR;
1383 }
1384
1385 endp = get_field(q->qh.epchar, QH_EPCHAR_EP);
1386 devadr = get_field(q->qh.epchar, QH_EPCHAR_DEVADDR);
1387
1388 /* TODO: associating device with ehci port */
1389 dev = ehci_find_device(q->ehci, devadr);
1390 ep = usb_ep_get(dev, q->pid, endp);
1391
1392 usb_packet_setup(&q->packet, q->pid, ep);
1393 usb_packet_map(&q->packet, &q->sgl);
1394
1395 ret = usb_handle_packet(dev, &q->packet);
1396 DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd "
1397 "(total %d) endp %x ret %d\n",
1398 q->qhaddr, q->qh.next, q->qtdaddr, q->pid,
1399 q->packet.iov.size, q->tbytes, endp, ret);
1400
1401 if (ret > BUFF_SIZE) {
1402 fprintf(stderr, "ret from usb_handle_packet > BUFF_SIZE\n");
1403 return USB_RET_PROCERR;
1404 }
1405
1406 return ret;
1407 }
1408
1409 /* 4.7.2
1410 */
1411
1412 static int ehci_process_itd(EHCIState *ehci,
1413 EHCIitd *itd)
1414 {
1415 USBDevice *dev;
1416 USBEndpoint *ep;
1417 int ret;
1418 uint32_t i, len, pid, dir, devaddr, endp;
1419 uint32_t pg, off, ptr1, ptr2, max, mult;
1420
1421 dir =(itd->bufptr[1] & ITD_BUFPTR_DIRECTION);
1422 devaddr = get_field(itd->bufptr[0], ITD_BUFPTR_DEVADDR);
1423 endp = get_field(itd->bufptr[0], ITD_BUFPTR_EP);
1424 max = get_field(itd->bufptr[1], ITD_BUFPTR_MAXPKT);
1425 mult = get_field(itd->bufptr[2], ITD_BUFPTR_MULT);
1426
1427 for(i = 0; i < 8; i++) {
1428 if (itd->transact[i] & ITD_XACT_ACTIVE) {
1429 pg = get_field(itd->transact[i], ITD_XACT_PGSEL);
1430 off = itd->transact[i] & ITD_XACT_OFFSET_MASK;
1431 ptr1 = (itd->bufptr[pg] & ITD_BUFPTR_MASK);
1432 ptr2 = (itd->bufptr[pg+1] & ITD_BUFPTR_MASK);
1433 len = get_field(itd->transact[i], ITD_XACT_LENGTH);
1434
1435 if (len > max * mult) {
1436 len = max * mult;
1437 }
1438
1439 if (len > BUFF_SIZE) {
1440 return USB_RET_PROCERR;
1441 }
1442
1443 pci_dma_sglist_init(&ehci->isgl, &ehci->dev, 2);
1444 if (off + len > 4096) {
1445 /* transfer crosses page border */
1446 uint32_t len2 = off + len - 4096;
1447 uint32_t len1 = len - len2;
1448 qemu_sglist_add(&ehci->isgl, ptr1 + off, len1);
1449 qemu_sglist_add(&ehci->isgl, ptr2, len2);
1450 } else {
1451 qemu_sglist_add(&ehci->isgl, ptr1 + off, len);
1452 }
1453
1454 pid = dir ? USB_TOKEN_IN : USB_TOKEN_OUT;
1455
1456 dev = ehci_find_device(ehci, devaddr);
1457 ep = usb_ep_get(dev, pid, endp);
1458 if (ep->type == USB_ENDPOINT_XFER_ISOC) {
1459 usb_packet_setup(&ehci->ipacket, pid, ep);
1460 usb_packet_map(&ehci->ipacket, &ehci->isgl);
1461 ret = usb_handle_packet(dev, &ehci->ipacket);
1462 assert(ret != USB_RET_ASYNC);
1463 usb_packet_unmap(&ehci->ipacket);
1464 } else {
1465 DPRINTF("ISOCH: attempt to addess non-iso endpoint\n");
1466 ret = USB_RET_NAK;
1467 }
1468 qemu_sglist_destroy(&ehci->isgl);
1469
1470 if (ret < 0) {
1471 switch (ret) {
1472 default:
1473 fprintf(stderr, "Unexpected iso usb result: %d\n", ret);
1474 /* Fall through */
1475 case USB_RET_IOERROR:
1476 case USB_RET_NODEV:
1477 /* 3.3.2: XACTERR is only allowed on IN transactions */
1478 if (dir) {
1479 itd->transact[i] |= ITD_XACT_XACTERR;
1480 ehci_record_interrupt(ehci, USBSTS_ERRINT);
1481 }
1482 break;
1483 case USB_RET_BABBLE:
1484 itd->transact[i] |= ITD_XACT_BABBLE;
1485 ehci_record_interrupt(ehci, USBSTS_ERRINT);
1486 break;
1487 case USB_RET_NAK:
1488 /* no data for us, so do a zero-length transfer */
1489 ret = 0;
1490 break;
1491 }
1492 }
1493 if (ret >= 0) {
1494 if (!dir) {
1495 /* OUT */
1496 set_field(&itd->transact[i], len - ret, ITD_XACT_LENGTH);
1497 } else {
1498 /* IN */
1499 set_field(&itd->transact[i], ret, ITD_XACT_LENGTH);
1500 }
1501 }
1502 if (itd->transact[i] & ITD_XACT_IOC) {
1503 ehci_record_interrupt(ehci, USBSTS_INT);
1504 }
1505 itd->transact[i] &= ~ITD_XACT_ACTIVE;
1506 }
1507 }
1508 return 0;
1509 }
1510
1511 /* This state is the entry point for asynchronous schedule
1512 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1513 */
1514 static int ehci_state_waitlisthead(EHCIState *ehci, int async)
1515 {
1516 EHCIqh qh;
1517 int i = 0;
1518 int again = 0;
1519 uint32_t entry = ehci->asynclistaddr;
1520
1521 /* set reclamation flag at start event (4.8.6) */
1522 if (async) {
1523 ehci_set_usbsts(ehci, USBSTS_REC);
1524 }
1525
1526 ehci_queues_rip_unused(ehci, async, 0);
1527
1528 /* Find the head of the list (4.9.1.1) */
1529 for(i = 0; i < MAX_QH; i++) {
1530 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &qh,
1531 sizeof(EHCIqh) >> 2);
1532 ehci_trace_qh(NULL, NLPTR_GET(entry), &qh);
1533
1534 if (qh.epchar & QH_EPCHAR_H) {
1535 if (async) {
1536 entry |= (NLPTR_TYPE_QH << 1);
1537 }
1538
1539 ehci_set_fetch_addr(ehci, async, entry);
1540 ehci_set_state(ehci, async, EST_FETCHENTRY);
1541 again = 1;
1542 goto out;
1543 }
1544
1545 entry = qh.next;
1546 if (entry == ehci->asynclistaddr) {
1547 break;
1548 }
1549 }
1550
1551 /* no head found for list. */
1552
1553 ehci_set_state(ehci, async, EST_ACTIVE);
1554
1555 out:
1556 return again;
1557 }
1558
1559
1560 /* This state is the entry point for periodic schedule processing as
1561 * well as being a continuation state for async processing.
1562 */
1563 static int ehci_state_fetchentry(EHCIState *ehci, int async)
1564 {
1565 int again = 0;
1566 uint32_t entry = ehci_get_fetch_addr(ehci, async);
1567
1568 if (NLPTR_TBIT(entry)) {
1569 ehci_set_state(ehci, async, EST_ACTIVE);
1570 goto out;
1571 }
1572
1573 /* section 4.8, only QH in async schedule */
1574 if (async && (NLPTR_TYPE_GET(entry) != NLPTR_TYPE_QH)) {
1575 fprintf(stderr, "non queue head request in async schedule\n");
1576 return -1;
1577 }
1578
1579 switch (NLPTR_TYPE_GET(entry)) {
1580 case NLPTR_TYPE_QH:
1581 ehci_set_state(ehci, async, EST_FETCHQH);
1582 again = 1;
1583 break;
1584
1585 case NLPTR_TYPE_ITD:
1586 ehci_set_state(ehci, async, EST_FETCHITD);
1587 again = 1;
1588 break;
1589
1590 case NLPTR_TYPE_STITD:
1591 ehci_set_state(ehci, async, EST_FETCHSITD);
1592 again = 1;
1593 break;
1594
1595 default:
1596 /* TODO: handle FSTN type */
1597 fprintf(stderr, "FETCHENTRY: entry at %X is of type %d "
1598 "which is not supported yet\n", entry, NLPTR_TYPE_GET(entry));
1599 return -1;
1600 }
1601
1602 out:
1603 return again;
1604 }
1605
1606 static EHCIQueue *ehci_state_fetchqh(EHCIState *ehci, int async)
1607 {
1608 uint32_t entry;
1609 EHCIQueue *q;
1610
1611 entry = ehci_get_fetch_addr(ehci, async);
1612 q = ehci_find_queue_by_qh(ehci, entry, async);
1613 if (NULL == q) {
1614 q = ehci_alloc_queue(ehci, async);
1615 }
1616 q->qhaddr = entry;
1617 q->seen++;
1618
1619 if (q->seen > 1) {
1620 /* we are going in circles -- stop processing */
1621 ehci_set_state(ehci, async, EST_ACTIVE);
1622 q = NULL;
1623 goto out;
1624 }
1625
1626 get_dwords(ehci, NLPTR_GET(q->qhaddr),
1627 (uint32_t *) &q->qh, sizeof(EHCIqh) >> 2);
1628 ehci_trace_qh(q, NLPTR_GET(q->qhaddr), &q->qh);
1629
1630 if (q->async == EHCI_ASYNC_INFLIGHT) {
1631 /* I/O still in progress -- skip queue */
1632 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1633 goto out;
1634 }
1635 if (q->async == EHCI_ASYNC_FINISHED) {
1636 /* I/O finished -- continue processing queue */
1637 trace_usb_ehci_queue_action(q, "resume");
1638 ehci_set_state(ehci, async, EST_EXECUTING);
1639 goto out;
1640 }
1641
1642 if (async && (q->qh.epchar & QH_EPCHAR_H)) {
1643
1644 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1645 if (ehci->usbsts & USBSTS_REC) {
1646 ehci_clear_usbsts(ehci, USBSTS_REC);
1647 } else {
1648 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1649 " - done processing\n", q->qhaddr);
1650 ehci_set_state(ehci, async, EST_ACTIVE);
1651 q = NULL;
1652 goto out;
1653 }
1654 }
1655
1656 #if EHCI_DEBUG
1657 if (q->qhaddr != q->qh.next) {
1658 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1659 q->qhaddr,
1660 q->qh.epchar & QH_EPCHAR_H,
1661 q->qh.token & QTD_TOKEN_HALT,
1662 q->qh.token & QTD_TOKEN_ACTIVE,
1663 q->qh.next);
1664 }
1665 #endif
1666
1667 if (q->qh.token & QTD_TOKEN_HALT) {
1668 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1669
1670 } else if ((q->qh.token & QTD_TOKEN_ACTIVE) &&
1671 (NLPTR_TBIT(q->qh.current_qtd) == 0)) {
1672 q->qtdaddr = q->qh.current_qtd;
1673 ehci_set_state(ehci, async, EST_FETCHQTD);
1674
1675 } else {
1676 /* EHCI spec version 1.0 Section 4.10.2 */
1677 ehci_set_state(ehci, async, EST_ADVANCEQUEUE);
1678 }
1679
1680 out:
1681 return q;
1682 }
1683
1684 static int ehci_state_fetchitd(EHCIState *ehci, int async)
1685 {
1686 uint32_t entry;
1687 EHCIitd itd;
1688
1689 assert(!async);
1690 entry = ehci_get_fetch_addr(ehci, async);
1691
1692 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1693 sizeof(EHCIitd) >> 2);
1694 ehci_trace_itd(ehci, entry, &itd);
1695
1696 if (ehci_process_itd(ehci, &itd) != 0) {
1697 return -1;
1698 }
1699
1700 put_dwords(ehci, NLPTR_GET(entry), (uint32_t *) &itd,
1701 sizeof(EHCIitd) >> 2);
1702 ehci_set_fetch_addr(ehci, async, itd.next);
1703 ehci_set_state(ehci, async, EST_FETCHENTRY);
1704
1705 return 1;
1706 }
1707
1708 static int ehci_state_fetchsitd(EHCIState *ehci, int async)
1709 {
1710 uint32_t entry;
1711 EHCIsitd sitd;
1712
1713 assert(!async);
1714 entry = ehci_get_fetch_addr(ehci, async);
1715
1716 get_dwords(ehci, NLPTR_GET(entry), (uint32_t *)&sitd,
1717 sizeof(EHCIsitd) >> 2);
1718 ehci_trace_sitd(ehci, entry, &sitd);
1719
1720 if (!(sitd.results & SITD_RESULTS_ACTIVE)) {
1721 /* siTD is not active, nothing to do */;
1722 } else {
1723 /* TODO: split transfers are not implemented */
1724 fprintf(stderr, "WARNING: Skipping active siTD\n");
1725 }
1726
1727 ehci_set_fetch_addr(ehci, async, sitd.next);
1728 ehci_set_state(ehci, async, EST_FETCHENTRY);
1729 return 1;
1730 }
1731
1732 /* Section 4.10.2 - paragraph 3 */
1733 static int ehci_state_advqueue(EHCIQueue *q, int async)
1734 {
1735 #if 0
1736 /* TO-DO: 4.10.2 - paragraph 2
1737 * if I-bit is set to 1 and QH is not active
1738 * go to horizontal QH
1739 */
1740 if (I-bit set) {
1741 ehci_set_state(ehci, async, EST_HORIZONTALQH);
1742 goto out;
1743 }
1744 #endif
1745
1746 /*
1747 * want data and alt-next qTD is valid
1748 */
1749 if (((q->qh.token & QTD_TOKEN_TBYTES_MASK) != 0) &&
1750 (NLPTR_TBIT(q->qh.altnext_qtd) == 0)) {
1751 q->qtdaddr = q->qh.altnext_qtd;
1752 ehci_set_state(q->ehci, async, EST_FETCHQTD);
1753
1754 /*
1755 * next qTD is valid
1756 */
1757 } else if (NLPTR_TBIT(q->qh.next_qtd) == 0) {
1758 q->qtdaddr = q->qh.next_qtd;
1759 ehci_set_state(q->ehci, async, EST_FETCHQTD);
1760
1761 /*
1762 * no valid qTD, try next QH
1763 */
1764 } else {
1765 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1766 }
1767
1768 return 1;
1769 }
1770
1771 /* Section 4.10.2 - paragraph 4 */
1772 static int ehci_state_fetchqtd(EHCIQueue *q, int async)
1773 {
1774 int again = 0;
1775
1776 get_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &q->qtd,
1777 sizeof(EHCIqtd) >> 2);
1778 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), &q->qtd);
1779
1780 if (q->qtd.token & QTD_TOKEN_ACTIVE) {
1781 ehci_set_state(q->ehci, async, EST_EXECUTE);
1782 again = 1;
1783 } else {
1784 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1785 again = 1;
1786 }
1787
1788 return again;
1789 }
1790
1791 static int ehci_state_horizqh(EHCIQueue *q, int async)
1792 {
1793 int again = 0;
1794
1795 if (ehci_get_fetch_addr(q->ehci, async) != q->qh.next) {
1796 ehci_set_fetch_addr(q->ehci, async, q->qh.next);
1797 ehci_set_state(q->ehci, async, EST_FETCHENTRY);
1798 again = 1;
1799 } else {
1800 ehci_set_state(q->ehci, async, EST_ACTIVE);
1801 }
1802
1803 return again;
1804 }
1805
1806 /*
1807 * Write the qh back to guest physical memory. This step isn't
1808 * in the EHCI spec but we need to do it since we don't share
1809 * physical memory with our guest VM.
1810 *
1811 * The first three dwords are read-only for the EHCI, so skip them
1812 * when writing back the qh.
1813 */
1814 static void ehci_flush_qh(EHCIQueue *q)
1815 {
1816 uint32_t *qh = (uint32_t *) &q->qh;
1817 uint32_t dwords = sizeof(EHCIqh) >> 2;
1818 uint32_t addr = NLPTR_GET(q->qhaddr);
1819
1820 put_dwords(q->ehci, addr + 3 * sizeof(uint32_t), qh + 3, dwords - 3);
1821 }
1822
1823 static int ehci_state_execute(EHCIQueue *q, int async)
1824 {
1825 int again = 0;
1826
1827 if (ehci_qh_do_overlay(q) != 0) {
1828 return -1;
1829 }
1830
1831 // TODO verify enough time remains in the uframe as in 4.4.1.1
1832 // TODO write back ptr to async list when done or out of time
1833 // TODO Windows does not seem to ever set the MULT field
1834
1835 if (!async) {
1836 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1837 if (!transactCtr) {
1838 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1839 again = 1;
1840 goto out;
1841 }
1842 }
1843
1844 if (async) {
1845 ehci_set_usbsts(q->ehci, USBSTS_REC);
1846 }
1847
1848 q->usb_status = ehci_execute(q);
1849 if (q->usb_status == USB_RET_PROCERR) {
1850 again = -1;
1851 goto out;
1852 }
1853 if (q->usb_status == USB_RET_ASYNC) {
1854 ehci_flush_qh(q);
1855 trace_usb_ehci_queue_action(q, "suspend");
1856 q->async = EHCI_ASYNC_INFLIGHT;
1857 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1858 again = 1;
1859 goto out;
1860 }
1861
1862 ehci_set_state(q->ehci, async, EST_EXECUTING);
1863 again = 1;
1864
1865 out:
1866 return again;
1867 }
1868
1869 static int ehci_state_executing(EHCIQueue *q, int async)
1870 {
1871 int again = 0;
1872
1873 ehci_execute_complete(q);
1874 if (q->usb_status == USB_RET_ASYNC) {
1875 goto out;
1876 }
1877 if (q->usb_status == USB_RET_PROCERR) {
1878 again = -1;
1879 goto out;
1880 }
1881
1882 // 4.10.3
1883 if (!async) {
1884 int transactCtr = get_field(q->qh.epcap, QH_EPCAP_MULT);
1885 transactCtr--;
1886 set_field(&q->qh.epcap, transactCtr, QH_EPCAP_MULT);
1887 // 4.10.3, bottom of page 82, should exit this state when transaction
1888 // counter decrements to 0
1889 }
1890
1891 /* 4.10.5 */
1892 if (q->usb_status == USB_RET_NAK) {
1893 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1894 } else {
1895 ehci_set_state(q->ehci, async, EST_WRITEBACK);
1896 }
1897
1898 again = 1;
1899
1900 out:
1901 ehci_flush_qh(q);
1902 return again;
1903 }
1904
1905
1906 static int ehci_state_writeback(EHCIQueue *q, int async)
1907 {
1908 int again = 0;
1909
1910 /* Write back the QTD from the QH area */
1911 ehci_trace_qtd(q, NLPTR_GET(q->qtdaddr), (EHCIqtd*) &q->qh.next_qtd);
1912 put_dwords(q->ehci, NLPTR_GET(q->qtdaddr), (uint32_t *) &q->qh.next_qtd,
1913 sizeof(EHCIqtd) >> 2);
1914
1915 /*
1916 * EHCI specs say go horizontal here.
1917 *
1918 * We can also advance the queue here for performance reasons. We
1919 * need to take care to only take that shortcut in case we've
1920 * processed the qtd just written back without errors, i.e. halt
1921 * bit is clear.
1922 */
1923 if (q->qh.token & QTD_TOKEN_HALT) {
1924 ehci_set_state(q->ehci, async, EST_HORIZONTALQH);
1925 again = 1;
1926 } else {
1927 ehci_set_state(q->ehci, async, EST_ADVANCEQUEUE);
1928 again = 1;
1929 }
1930 return again;
1931 }
1932
1933 /*
1934 * This is the state machine that is common to both async and periodic
1935 */
1936
1937 static void ehci_advance_state(EHCIState *ehci,
1938 int async)
1939 {
1940 EHCIQueue *q = NULL;
1941 int again;
1942 int iter = 0;
1943
1944 do {
1945 if (ehci_get_state(ehci, async) == EST_FETCHQH) {
1946 iter++;
1947 /* if we are roaming a lot of QH without executing a qTD
1948 * something is wrong with the linked list. TO-DO: why is
1949 * this hack needed?
1950 */
1951 assert(iter < MAX_ITERATIONS);
1952 #if 0
1953 if (iter > MAX_ITERATIONS) {
1954 DPRINTF("\n*** advance_state: bailing on MAX ITERATIONS***\n");
1955 ehci_set_state(ehci, async, EST_ACTIVE);
1956 break;
1957 }
1958 #endif
1959 }
1960 switch(ehci_get_state(ehci, async)) {
1961 case EST_WAITLISTHEAD:
1962 again = ehci_state_waitlisthead(ehci, async);
1963 break;
1964
1965 case EST_FETCHENTRY:
1966 again = ehci_state_fetchentry(ehci, async);
1967 break;
1968
1969 case EST_FETCHQH:
1970 q = ehci_state_fetchqh(ehci, async);
1971 again = q ? 1 : 0;
1972 break;
1973
1974 case EST_FETCHITD:
1975 again = ehci_state_fetchitd(ehci, async);
1976 break;
1977
1978 case EST_FETCHSITD:
1979 again = ehci_state_fetchsitd(ehci, async);
1980 break;
1981
1982 case EST_ADVANCEQUEUE:
1983 again = ehci_state_advqueue(q, async);
1984 break;
1985
1986 case EST_FETCHQTD:
1987 again = ehci_state_fetchqtd(q, async);
1988 break;
1989
1990 case EST_HORIZONTALQH:
1991 again = ehci_state_horizqh(q, async);
1992 break;
1993
1994 case EST_EXECUTE:
1995 iter = 0;
1996 again = ehci_state_execute(q, async);
1997 break;
1998
1999 case EST_EXECUTING:
2000 assert(q != NULL);
2001 again = ehci_state_executing(q, async);
2002 break;
2003
2004 case EST_WRITEBACK:
2005 assert(q != NULL);
2006 again = ehci_state_writeback(q, async);
2007 break;
2008
2009 default:
2010 fprintf(stderr, "Bad state!\n");
2011 again = -1;
2012 assert(0);
2013 break;
2014 }
2015
2016 if (again < 0) {
2017 fprintf(stderr, "processing error - resetting ehci HC\n");
2018 ehci_reset(ehci);
2019 again = 0;
2020 assert(0);
2021 }
2022 }
2023 while (again);
2024
2025 ehci_commit_interrupt(ehci);
2026 }
2027
2028 static void ehci_advance_async_state(EHCIState *ehci)
2029 {
2030 const int async = 1;
2031
2032 switch(ehci_get_state(ehci, async)) {
2033 case EST_INACTIVE:
2034 if (!(ehci->usbcmd & USBCMD_ASE)) {
2035 break;
2036 }
2037 ehci_set_usbsts(ehci, USBSTS_ASS);
2038 ehci_set_state(ehci, async, EST_ACTIVE);
2039 // No break, fall through to ACTIVE
2040
2041 case EST_ACTIVE:
2042 if ( !(ehci->usbcmd & USBCMD_ASE)) {
2043 ehci_queues_rip_all(ehci, async);
2044 ehci_clear_usbsts(ehci, USBSTS_ASS);
2045 ehci_set_state(ehci, async, EST_INACTIVE);
2046 break;
2047 }
2048
2049 /* make sure guest has acknowledged the doorbell interrupt */
2050 /* TO-DO: is this really needed? */
2051 if (ehci->usbsts & USBSTS_IAA) {
2052 DPRINTF("IAA status bit still set.\n");
2053 break;
2054 }
2055
2056 /* check that address register has been set */
2057 if (ehci->asynclistaddr == 0) {
2058 break;
2059 }
2060
2061 ehci_set_state(ehci, async, EST_WAITLISTHEAD);
2062 ehci_advance_state(ehci, async);
2063
2064 /* If the doorbell is set, the guest wants to make a change to the
2065 * schedule. The host controller needs to release cached data.
2066 * (section 4.8.2)
2067 */
2068 if (ehci->usbcmd & USBCMD_IAAD) {
2069 /* Remove all unseen qhs from the async qhs queue */
2070 ehci_queues_rip_unused(ehci, async, 1);
2071 DPRINTF("ASYNC: doorbell request acknowledged\n");
2072 ehci->usbcmd &= ~USBCMD_IAAD;
2073 ehci_set_interrupt(ehci, USBSTS_IAA);
2074 }
2075 break;
2076
2077 default:
2078 /* this should only be due to a developer mistake */
2079 fprintf(stderr, "ehci: Bad asynchronous state %d. "
2080 "Resetting to active\n", ehci->astate);
2081 assert(0);
2082 }
2083 }
2084
2085 static void ehci_advance_periodic_state(EHCIState *ehci)
2086 {
2087 uint32_t entry;
2088 uint32_t list;
2089 const int async = 0;
2090
2091 // 4.6
2092
2093 switch(ehci_get_state(ehci, async)) {
2094 case EST_INACTIVE:
2095 if ( !(ehci->frindex & 7) && (ehci->usbcmd & USBCMD_PSE)) {
2096 ehci_set_usbsts(ehci, USBSTS_PSS);
2097 ehci_set_state(ehci, async, EST_ACTIVE);
2098 // No break, fall through to ACTIVE
2099 } else
2100 break;
2101
2102 case EST_ACTIVE:
2103 if ( !(ehci->frindex & 7) && !(ehci->usbcmd & USBCMD_PSE)) {
2104 ehci_queues_rip_all(ehci, async);
2105 ehci_clear_usbsts(ehci, USBSTS_PSS);
2106 ehci_set_state(ehci, async, EST_INACTIVE);
2107 break;
2108 }
2109
2110 list = ehci->periodiclistbase & 0xfffff000;
2111 /* check that register has been set */
2112 if (list == 0) {
2113 break;
2114 }
2115 list |= ((ehci->frindex & 0x1ff8) >> 1);
2116
2117 pci_dma_read(&ehci->dev, list, &entry, sizeof entry);
2118 entry = le32_to_cpu(entry);
2119
2120 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
2121 ehci->frindex / 8, list, entry);
2122 ehci_set_fetch_addr(ehci, async,entry);
2123 ehci_set_state(ehci, async, EST_FETCHENTRY);
2124 ehci_advance_state(ehci, async);
2125 ehci_queues_rip_unused(ehci, async, 0);
2126 break;
2127
2128 default:
2129 /* this should only be due to a developer mistake */
2130 fprintf(stderr, "ehci: Bad periodic state %d. "
2131 "Resetting to active\n", ehci->pstate);
2132 assert(0);
2133 }
2134 }
2135
2136 static void ehci_frame_timer(void *opaque)
2137 {
2138 EHCIState *ehci = opaque;
2139 int64_t expire_time, t_now;
2140 uint64_t ns_elapsed;
2141 int frames;
2142 int i;
2143 int skipped_frames = 0;
2144
2145 t_now = qemu_get_clock_ns(vm_clock);
2146 expire_time = t_now + (get_ticks_per_sec() / ehci->freq);
2147
2148 ns_elapsed = t_now - ehci->last_run_ns;
2149 frames = ns_elapsed / FRAME_TIMER_NS;
2150
2151 for (i = 0; i < frames; i++) {
2152 if ( !(ehci->usbsts & USBSTS_HALT)) {
2153 if (ehci->isoch_pause <= 0) {
2154 ehci->frindex += 8;
2155 }
2156
2157 if (ehci->frindex > 0x00001fff) {
2158 ehci->frindex = 0;
2159 ehci_set_interrupt(ehci, USBSTS_FLR);
2160 }
2161
2162 ehci->sofv = (ehci->frindex - 1) >> 3;
2163 ehci->sofv &= 0x000003ff;
2164 }
2165
2166 if (frames - i > ehci->maxframes) {
2167 skipped_frames++;
2168 } else {
2169 ehci_advance_periodic_state(ehci);
2170 }
2171
2172 ehci->last_run_ns += FRAME_TIMER_NS;
2173 }
2174
2175 #if 0
2176 if (skipped_frames) {
2177 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames);
2178 }
2179 #endif
2180
2181 /* Async is not inside loop since it executes everything it can once
2182 * called
2183 */
2184 ehci_advance_async_state(ehci);
2185
2186 qemu_mod_timer(ehci->frame_timer, expire_time);
2187 }
2188
2189
2190 static const MemoryRegionOps ehci_mem_ops = {
2191 .old_mmio = {
2192 .read = { ehci_mem_readb, ehci_mem_readw, ehci_mem_readl },
2193 .write = { ehci_mem_writeb, ehci_mem_writew, ehci_mem_writel },
2194 },
2195 .endianness = DEVICE_LITTLE_ENDIAN,
2196 };
2197
2198 static int usb_ehci_initfn(PCIDevice *dev);
2199
2200 static USBPortOps ehci_port_ops = {
2201 .attach = ehci_attach,
2202 .detach = ehci_detach,
2203 .child_detach = ehci_child_detach,
2204 .wakeup = ehci_wakeup,
2205 .complete = ehci_async_complete_packet,
2206 };
2207
2208 static USBBusOps ehci_bus_ops = {
2209 .register_companion = ehci_register_companion,
2210 };
2211
2212 static const VMStateDescription vmstate_ehci = {
2213 .name = "ehci",
2214 .unmigratable = 1,
2215 };
2216
2217 static Property ehci_properties[] = {
2218 DEFINE_PROP_UINT32("freq", EHCIState, freq, FRAME_TIMER_FREQ),
2219 DEFINE_PROP_UINT32("maxframes", EHCIState, maxframes, 128),
2220 DEFINE_PROP_END_OF_LIST(),
2221 };
2222
2223 static void ehci_class_init(ObjectClass *klass, void *data)
2224 {
2225 DeviceClass *dc = DEVICE_CLASS(klass);
2226 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2227
2228 k->init = usb_ehci_initfn;
2229 k->vendor_id = PCI_VENDOR_ID_INTEL;
2230 k->device_id = PCI_DEVICE_ID_INTEL_82801D; /* ich4 */
2231 k->revision = 0x10;
2232 k->class_id = PCI_CLASS_SERIAL_USB;
2233 dc->vmsd = &vmstate_ehci;
2234 dc->props = ehci_properties;
2235 }
2236
2237 static TypeInfo ehci_info = {
2238 .name = "usb-ehci",
2239 .parent = TYPE_PCI_DEVICE,
2240 .instance_size = sizeof(EHCIState),
2241 .class_init = ehci_class_init,
2242 };
2243
2244 static void ich9_ehci_class_init(ObjectClass *klass, void *data)
2245 {
2246 DeviceClass *dc = DEVICE_CLASS(klass);
2247 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2248
2249 k->init = usb_ehci_initfn;
2250 k->vendor_id = PCI_VENDOR_ID_INTEL;
2251 k->device_id = PCI_DEVICE_ID_INTEL_82801I_EHCI1;
2252 k->revision = 0x03;
2253 k->class_id = PCI_CLASS_SERIAL_USB;
2254 dc->vmsd = &vmstate_ehci;
2255 dc->props = ehci_properties;
2256 }
2257
2258 static TypeInfo ich9_ehci_info = {
2259 .name = "ich9-usb-ehci1",
2260 .parent = TYPE_PCI_DEVICE,
2261 .instance_size = sizeof(EHCIState),
2262 .class_init = ich9_ehci_class_init,
2263 };
2264
2265 static int usb_ehci_initfn(PCIDevice *dev)
2266 {
2267 EHCIState *s = DO_UPCAST(EHCIState, dev, dev);
2268 uint8_t *pci_conf = s->dev.config;
2269 int i;
2270
2271 pci_set_byte(&pci_conf[PCI_CLASS_PROG], 0x20);
2272
2273 /* capabilities pointer */
2274 pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x00);
2275 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
2276
2277 pci_set_byte(&pci_conf[PCI_INTERRUPT_PIN], 4); /* interrupt pin D */
2278 pci_set_byte(&pci_conf[PCI_MIN_GNT], 0);
2279 pci_set_byte(&pci_conf[PCI_MAX_LAT], 0);
2280
2281 // pci_conf[0x50] = 0x01; // power management caps
2282
2283 pci_set_byte(&pci_conf[USB_SBRN], USB_RELEASE_2); // release number (2.1.4)
2284 pci_set_byte(&pci_conf[0x61], 0x20); // frame length adjustment (2.1.5)
2285 pci_set_word(&pci_conf[0x62], 0x00); // port wake up capability (2.1.6)
2286
2287 pci_conf[0x64] = 0x00;
2288 pci_conf[0x65] = 0x00;
2289 pci_conf[0x66] = 0x00;
2290 pci_conf[0x67] = 0x00;
2291 pci_conf[0x68] = 0x01;
2292 pci_conf[0x69] = 0x00;
2293 pci_conf[0x6a] = 0x00;
2294 pci_conf[0x6b] = 0x00; // USBLEGSUP
2295 pci_conf[0x6c] = 0x00;
2296 pci_conf[0x6d] = 0x00;
2297 pci_conf[0x6e] = 0x00;
2298 pci_conf[0x6f] = 0xc0; // USBLEFCTLSTS
2299
2300 // 2.2 host controller interface version
2301 s->mmio[0x00] = (uint8_t) OPREGBASE;
2302 s->mmio[0x01] = 0x00;
2303 s->mmio[0x02] = 0x00;
2304 s->mmio[0x03] = 0x01; // HC version
2305 s->mmio[0x04] = NB_PORTS; // Number of downstream ports
2306 s->mmio[0x05] = 0x00; // No companion ports at present
2307 s->mmio[0x06] = 0x00;
2308 s->mmio[0x07] = 0x00;
2309 s->mmio[0x08] = 0x80; // We can cache whole frame, not 64-bit capable
2310 s->mmio[0x09] = 0x68; // EECP
2311 s->mmio[0x0a] = 0x00;
2312 s->mmio[0x0b] = 0x00;
2313
2314 s->irq = s->dev.irq[3];
2315
2316 usb_bus_new(&s->bus, &ehci_bus_ops, &s->dev.qdev);
2317 for(i = 0; i < NB_PORTS; i++) {
2318 usb_register_port(&s->bus, &s->ports[i], s, i, &ehci_port_ops,
2319 USB_SPEED_MASK_HIGH);
2320 s->ports[i].dev = 0;
2321 }
2322
2323 s->frame_timer = qemu_new_timer_ns(vm_clock, ehci_frame_timer, s);
2324 QTAILQ_INIT(&s->aqueues);
2325 QTAILQ_INIT(&s->pqueues);
2326
2327 qemu_register_reset(ehci_reset, s);
2328
2329 memory_region_init_io(&s->mem, &ehci_mem_ops, s, "ehci", MMIO_SIZE);
2330 pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mem);
2331
2332 return 0;
2333 }
2334
2335 static void ehci_register_types(void)
2336 {
2337 type_register_static(&ehci_info);
2338 type_register_static(&ich9_ehci_info);
2339 }
2340
2341 type_init(ehci_register_types)
2342
2343 /*
2344 * vim: expandtab ts=4
2345 */
QEMU modified to work with kvm