hw/msix.c

   1 /*
   2  * MSI-X device support
   3  *
   4  * This module includes support for MSI-X in pci devices.
   5  *
   6  * Author: Michael S. Tsirkin <mst@redhat.com>
   7  *
   8  *  Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
   9  *
  10  * This work is licensed under the terms of the GNU GPL, version 2.  See
  11  * the COPYING file in the top-level directory.
  12  *
  13  * Contributions after 2012-01-13 are licensed under the terms of the
  14  * GNU GPL, version 2 or (at your option) any later version.
  15  */
  16
  17 #include "hw.h"
  18 #include "msi.h"
  19 #include "msix.h"
  20 #include "pci.h"
  21 #include "range.h"
  22
  23 #define MSIX_CAP_LENGTH 12
  24
  25 /* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
  26 #define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
  27 #define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
  28 #define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)
  29
  30 static MSIMessage msix_get_message(PCIDevice *dev, unsigned vector)
  31 {
  32     uint8_t *table_entry = dev->msix_table + vector * PCI_MSIX_ENTRY_SIZE;
  33     MSIMessage msg;
  34
  35     msg.address = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR);
  36     msg.data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA);
  37     return msg;
  38 }
  39
  40 /*
  41  * Special API for POWER to configure the vectors through
  42  * a side channel. Should never be used by devices.
  43  */
  44 void msix_set_message(PCIDevice *dev, int vector, struct MSIMessage msg)
  45 {
  46     uint8_t *table_entry = dev->msix_table + vector * PCI_MSIX_ENTRY_SIZE;
  47
  48     pci_set_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR, msg.address);
  49     pci_set_long(table_entry + PCI_MSIX_ENTRY_DATA, msg.data);
  50     table_entry[PCI_MSIX_ENTRY_VECTOR_CTRL] &= ~PCI_MSIX_ENTRY_CTRL_MASKBIT;
  51 }
  52
  53 static uint8_t msix_pending_mask(int vector)
  54 {
  55     return 1 << (vector % 8);
  56 }
  57
  58 static uint8_t *msix_pending_byte(PCIDevice *dev, int vector)
  59 {
  60     return dev->msix_pba + vector / 8;
  61 }
  62
  63 static int msix_is_pending(PCIDevice *dev, int vector)
  64 {
  65     return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
  66 }
  67
  68 static void msix_set_pending(PCIDevice *dev, int vector)
  69 {
  70     *msix_pending_byte(dev, vector) |= msix_pending_mask(vector);
  71 }
  72
  73 static void msix_clr_pending(PCIDevice *dev, int vector)
  74 {
  75     *msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
  76 }
  77
  78 static bool msix_vector_masked(PCIDevice *dev, int vector, bool fmask)
  79 {
  80     unsigned offset = vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
  81     return fmask || dev->msix_table[offset] & PCI_MSIX_ENTRY_CTRL_MASKBIT;
  82 }
  83
  84 static bool msix_is_masked(PCIDevice *dev, int vector)
  85 {
  86     return msix_vector_masked(dev, vector, dev->msix_function_masked);
  87 }
  88
  89 static void msix_fire_vector_notifier(PCIDevice *dev,
  90                                       unsigned int vector, bool is_masked)
  91 {
  92     MSIMessage msg;
  93     int ret;
  94
  95     if (!dev->msix_vector_use_notifier) {
  96         return;
  97     }
  98     if (is_masked) {
  99         dev->msix_vector_release_notifier(dev, vector);
 100     } else {
 101         msg = msix_get_message(dev, vector);
 102         ret = dev->msix_vector_use_notifier(dev, vector, msg);
 103         assert(ret >= 0);
 104     }
 105 }
 106
 107 static void msix_handle_mask_update(PCIDevice *dev, int vector, bool was_masked)
 108 {
 109     bool is_masked = msix_is_masked(dev, vector);
 110
 111     if (is_masked == was_masked) {
 112         return;
 113     }
 114
 115     msix_fire_vector_notifier(dev, vector, is_masked);
 116
 117     if (!is_masked && msix_is_pending(dev, vector)) {
 118         msix_clr_pending(dev, vector);
 119         msix_notify(dev, vector);
 120     }
 121 }
 122
 123 static void msix_update_function_masked(PCIDevice *dev)
 124 {
 125     dev->msix_function_masked = !msix_enabled(dev) ||
 126         (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] & MSIX_MASKALL_MASK);
 127 }
 128
 129 /* Handle MSI-X capability config write. */
 130 void msix_write_config(PCIDevice *dev, uint32_t addr,
 131                        uint32_t val, int len)
 132 {
 133     unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
 134     int vector;
 135     bool was_masked;
 136
 137     if (!msix_present(dev) || !range_covers_byte(addr, len, enable_pos)) {
 138         return;
 139     }
 140
 141     was_masked = dev->msix_function_masked;
 142     msix_update_function_masked(dev);
 143
 144     if (!msix_enabled(dev)) {
 145         return;
 146     }
 147
 148     pci_device_deassert_intx(dev);
 149
 150     if (dev->msix_function_masked == was_masked) {
 151         return;
 152     }
 153
 154     for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
 155         msix_handle_mask_update(dev, vector,
 156                                 msix_vector_masked(dev, vector, was_masked));
 157     }
 158 }
 159
 160 static uint64_t msix_table_mmio_read(void *opaque, target_phys_addr_t addr,
 161                                      unsigned size)
 162 {
 163     PCIDevice *dev = opaque;
 164
 165     return pci_get_long(dev->msix_table + addr);
 166 }
 167
 168 static void msix_table_mmio_write(void *opaque, target_phys_addr_t addr,
 169                                   uint64_t val, unsigned size)
 170 {
 171     PCIDevice *dev = opaque;
 172     int vector = addr / PCI_MSIX_ENTRY_SIZE;
 173     bool was_masked;
 174
 175     was_masked = msix_is_masked(dev, vector);
 176     pci_set_long(dev->msix_table + addr, val);
 177     msix_handle_mask_update(dev, vector, was_masked);
 178 }
 179
 180 static const MemoryRegionOps msix_table_mmio_ops = {
 181     .read = msix_table_mmio_read,
 182     .write = msix_table_mmio_write,
 183     /* TODO: MSIX should be LITTLE_ENDIAN. */
 184     .endianness = DEVICE_NATIVE_ENDIAN,
 185     .valid = {
 186         .min_access_size = 4,
 187         .max_access_size = 4,
 188     },
 189 };
 190
 191 static uint64_t msix_pba_mmio_read(void *opaque, target_phys_addr_t addr,
 192                                    unsigned size)
 193 {
 194     PCIDevice *dev = opaque;
 195
 196     return pci_get_long(dev->msix_pba + addr);
 197 }
 198
 199 static const MemoryRegionOps msix_pba_mmio_ops = {
 200     .read = msix_pba_mmio_read,
 201     /* TODO: MSIX should be LITTLE_ENDIAN. */
 202     .endianness = DEVICE_NATIVE_ENDIAN,
 203     .valid = {
 204         .min_access_size = 4,
 205         .max_access_size = 4,
 206     },
 207 };
 208
 209 static void msix_mask_all(struct PCIDevice *dev, unsigned nentries)
 210 {
 211     int vector;
 212
 213     for (vector = 0; vector < nentries; ++vector) {
 214         unsigned offset =
 215             vector * PCI_MSIX_ENTRY_SIZE + PCI_MSIX_ENTRY_VECTOR_CTRL;
 216         bool was_masked = msix_is_masked(dev, vector);
 217
 218         dev->msix_table[offset] |= PCI_MSIX_ENTRY_CTRL_MASKBIT;
 219         msix_handle_mask_update(dev, vector, was_masked);
 220     }
 221 }
 222
 223 /* Initialize the MSI-X structures */
 224 int msix_init(struct PCIDevice *dev, unsigned short nentries,
 225               MemoryRegion *table_bar, uint8_t table_bar_nr,
 226               unsigned table_offset, MemoryRegion *pba_bar,
 227               uint8_t pba_bar_nr, unsigned pba_offset, uint8_t cap_pos)
 228 {
 229     int cap;
 230     unsigned table_size, pba_size;
 231     uint8_t *config;
 232
 233     /* Nothing to do if MSI is not supported by interrupt controller */
 234     if (!msi_supported) {
 235         return -ENOTSUP;
 236     }
 237
 238     if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1) {
 239         return -EINVAL;
 240     }
 241
 242     table_size = nentries * PCI_MSIX_ENTRY_SIZE;
 243     pba_size = QEMU_ALIGN_UP(nentries, 64) / 8;
 244
 245     /* Sanity test: table & pba don't overlap, fit within BARs, min aligned */
 246     if ((table_bar_nr == pba_bar_nr &&
 247          ranges_overlap(table_offset, table_size, pba_offset, pba_size)) ||
 248         table_offset + table_size > memory_region_size(table_bar) ||
 249         pba_offset + pba_size > memory_region_size(pba_bar) ||
 250         (table_offset | pba_offset) & PCI_MSIX_FLAGS_BIRMASK) {
 251         return -EINVAL;
 252     }
 253
 254     cap = pci_add_capability(dev, PCI_CAP_ID_MSIX, cap_pos, MSIX_CAP_LENGTH);
 255     if (cap < 0) {
 256         return cap;
 257     }
 258
 259     dev->msix_cap = cap;
 260     dev->cap_present |= QEMU_PCI_CAP_MSIX;
 261     config = dev->config + cap;
 262
 263     pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
 264     dev->msix_entries_nr = nentries;
 265     dev->msix_function_masked = true;
 266
 267     pci_set_long(config + PCI_MSIX_TABLE, table_offset | table_bar_nr);
 268     pci_set_long(config + PCI_MSIX_PBA, pba_offset | pba_bar_nr);
 269
 270     /* Make flags bit writable. */
 271     dev->wmask[cap + MSIX_CONTROL_OFFSET] |= MSIX_ENABLE_MASK |
 272                                              MSIX_MASKALL_MASK;
 273
 274     dev->msix_table = g_malloc0(table_size);
 275     dev->msix_pba = g_malloc0(pba_size);
 276     dev->msix_entry_used = g_malloc0(nentries * sizeof *dev->msix_entry_used);
 277
 278     msix_mask_all(dev, nentries);
 279
 280     memory_region_init_io(&dev->msix_table_mmio, &msix_table_mmio_ops, dev,
 281                           "msix-table", table_size);
 282     memory_region_add_subregion(table_bar, table_offset, &dev->msix_table_mmio);
 283     memory_region_init_io(&dev->msix_pba_mmio, &msix_pba_mmio_ops, dev,
 284                           "msix-pba", pba_size);
 285     memory_region_add_subregion(pba_bar, pba_offset, &dev->msix_pba_mmio);
 286
 287     return 0;
 288 }
 289
 290 int msix_init_exclusive_bar(PCIDevice *dev, unsigned short nentries,
 291                             uint8_t bar_nr)
 292 {
 293     int ret;
 294     char *name;
 295
 296     /*
 297      * Migration compatibility dictates that this remains a 4k
 298      * BAR with the vector table in the lower half and PBA in
 299      * the upper half.  Do not use these elsewhere!
 300      */
 301 #define MSIX_EXCLUSIVE_BAR_SIZE 4096
 302 #define MSIX_EXCLUSIVE_BAR_TABLE_OFFSET 0
 303 #define MSIX_EXCLUSIVE_BAR_PBA_OFFSET (MSIX_EXCLUSIVE_BAR_SIZE / 2)
 304 #define MSIX_EXCLUSIVE_CAP_OFFSET 0
 305
 306     if (nentries * PCI_MSIX_ENTRY_SIZE > MSIX_EXCLUSIVE_BAR_PBA_OFFSET) {
 307         return -EINVAL;
 308     }
 309
 310     if (asprintf(&name, "%s-msix", dev->name) == -1) {
 311         return -ENOMEM;
 312     }
 313
 314     memory_region_init(&dev->msix_exclusive_bar, name, MSIX_EXCLUSIVE_BAR_SIZE);
 315
 316     free(name);
 317
 318     ret = msix_init(dev, nentries, &dev->msix_exclusive_bar, bar_nr,
 319                     MSIX_EXCLUSIVE_BAR_TABLE_OFFSET, &dev->msix_exclusive_bar,
 320                     bar_nr, MSIX_EXCLUSIVE_BAR_PBA_OFFSET,
 321                     MSIX_EXCLUSIVE_CAP_OFFSET);
 322     if (ret) {
 323         memory_region_destroy(&dev->msix_exclusive_bar);
 324         return ret;
 325     }
 326
 327     pci_register_bar(dev, bar_nr, PCI_BASE_ADDRESS_SPACE_MEMORY,
 328                      &dev->msix_exclusive_bar);
 329
 330     return 0;
 331 }
 332
 333 static void msix_free_irq_entries(PCIDevice *dev)
 334 {
 335     int vector;
 336
 337     for (vector = 0; vector < dev->msix_entries_nr; ++vector) {
 338         dev->msix_entry_used[vector] = 0;
 339         msix_clr_pending(dev, vector);
 340     }
 341 }
 342
 343 /* Clean up resources for the device. */
 344 void msix_uninit(PCIDevice *dev, MemoryRegion *table_bar, MemoryRegion *pba_bar)
 345 {
 346     if (!msix_present(dev)) {
 347         return;
 348     }
 349     pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
 350     dev->msix_cap = 0;
 351     msix_free_irq_entries(dev);
 352     dev->msix_entries_nr = 0;
 353     memory_region_del_subregion(pba_bar, &dev->msix_pba_mmio);
 354     memory_region_destroy(&dev->msix_pba_mmio);
 355     g_free(dev->msix_pba);
 356     dev->msix_pba = NULL;
 357     memory_region_del_subregion(table_bar, &dev->msix_table_mmio);
 358     memory_region_destroy(&dev->msix_table_mmio);
 359     g_free(dev->msix_table);
 360     dev->msix_table = NULL;
 361     g_free(dev->msix_entry_used);
 362     dev->msix_entry_used = NULL;
 363     dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
 364     return;
 365 }
 366
 367 void msix_uninit_exclusive_bar(PCIDevice *dev)
 368 {
 369     if (msix_present(dev)) {
 370         msix_uninit(dev, &dev->msix_exclusive_bar, &dev->msix_exclusive_bar);
 371         memory_region_destroy(&dev->msix_exclusive_bar);
 372     }
 373 }
 374
 375 void msix_save(PCIDevice *dev, QEMUFile *f)
 376 {
 377     unsigned n = dev->msix_entries_nr;
 378
 379     if (!msix_present(dev)) {
 380         return;
 381     }
 382
 383     qemu_put_buffer(f, dev->msix_table, n * PCI_MSIX_ENTRY_SIZE);
 384     qemu_put_buffer(f, dev->msix_pba, (n + 7) / 8);
 385 }
 386
 387 /* Should be called after restoring the config space. */
 388 void msix_load(PCIDevice *dev, QEMUFile *f)
 389 {
 390     unsigned n = dev->msix_entries_nr;
 391     unsigned int vector;
 392
 393     if (!msix_present(dev)) {
 394         return;
 395     }
 396
 397     msix_free_irq_entries(dev);
 398     qemu_get_buffer(f, dev->msix_table, n * PCI_MSIX_ENTRY_SIZE);
 399     qemu_get_buffer(f, dev->msix_pba, (n + 7) / 8);
 400     msix_update_function_masked(dev);
 401
 402     for (vector = 0; vector < n; vector++) {
 403         msix_handle_mask_update(dev, vector, true);
 404     }
 405 }
 406
 407 /* Does device support MSI-X? */
 408 int msix_present(PCIDevice *dev)
 409 {
 410     return dev->cap_present & QEMU_PCI_CAP_MSIX;
 411 }
 412
 413 /* Is MSI-X enabled? */
 414 int msix_enabled(PCIDevice *dev)
 415 {
 416     return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
 417         (dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
 418          MSIX_ENABLE_MASK);
 419 }
 420
 421 /* Send an MSI-X message */
 422 void msix_notify(PCIDevice *dev, unsigned vector)
 423 {
 424     MSIMessage msg;
 425
 426     if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
 427         return;
 428     if (msix_is_masked(dev, vector)) {
 429         msix_set_pending(dev, vector);
 430         return;
 431     }
 432
 433     msg = msix_get_message(dev, vector);
 434
 435     stl_le_phys(msg.address, msg.data);
 436 }
 437
 438 void msix_reset(PCIDevice *dev)
 439 {
 440     if (!msix_present(dev)) {
 441         return;
 442     }
 443     msix_free_irq_entries(dev);
 444     dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &=
 445             ~dev->wmask[dev->msix_cap + MSIX_CONTROL_OFFSET];
 446     memset(dev->msix_table, 0, dev->msix_entries_nr * PCI_MSIX_ENTRY_SIZE);
 447     memset(dev->msix_pba, 0, QEMU_ALIGN_UP(dev->msix_entries_nr, 64) / 8);
 448     msix_mask_all(dev, dev->msix_entries_nr);
 449 }
 450
 451 /* PCI spec suggests that devices make it possible for software to configure
 452  * less vectors than supported by the device, but does not specify a standard
 453  * mechanism for devices to do so.
 454  *
 455  * We support this by asking devices to declare vectors software is going to
 456  * actually use, and checking this on the notification path. Devices that
 457  * don't want to follow the spec suggestion can declare all vectors as used. */
 458
 459 /* Mark vector as used. */
 460 int msix_vector_use(PCIDevice *dev, unsigned vector)
 461 {
 462     if (vector >= dev->msix_entries_nr)
 463         return -EINVAL;
 464     dev->msix_entry_used[vector]++;
 465     return 0;
 466 }
 467
 468 /* Mark vector as unused. */
 469 void msix_vector_unuse(PCIDevice *dev, unsigned vector)
 470 {
 471     if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector]) {
 472         return;
 473     }
 474     if (--dev->msix_entry_used[vector]) {
 475         return;
 476     }
 477     msix_clr_pending(dev, vector);
 478 }
 479
 480 void msix_unuse_all_vectors(PCIDevice *dev)
 481 {
 482     if (!msix_present(dev)) {
 483         return;
 484     }
 485     msix_free_irq_entries(dev);
 486 }
 487
 488 unsigned int msix_nr_vectors_allocated(const PCIDevice *dev)
 489 {
 490     return dev->msix_entries_nr;
 491 }
 492
 493 static int msix_set_notifier_for_vector(PCIDevice *dev, unsigned int vector)
 494 {
 495     MSIMessage msg;
 496
 497     if (msix_is_masked(dev, vector)) {
 498         return 0;
 499     }
 500     msg = msix_get_message(dev, vector);
 501     return dev->msix_vector_use_notifier(dev, vector, msg);
 502 }
 503
 504 static void msix_unset_notifier_for_vector(PCIDevice *dev, unsigned int vector)
 505 {
 506     if (msix_is_masked(dev, vector)) {
 507         return;
 508     }
 509     dev->msix_vector_release_notifier(dev, vector);
 510 }
 511
 512 int msix_set_vector_notifiers(PCIDevice *dev,
 513                               MSIVectorUseNotifier use_notifier,
 514                               MSIVectorReleaseNotifier release_notifier)
 515 {
 516     int vector, ret;
 517
 518     assert(use_notifier && release_notifier);
 519
 520     dev->msix_vector_use_notifier = use_notifier;
 521     dev->msix_vector_release_notifier = release_notifier;
 522
 523     if ((dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
 524         (MSIX_ENABLE_MASK | MSIX_MASKALL_MASK)) == MSIX_ENABLE_MASK) {
 525         for (vector = 0; vector < dev->msix_entries_nr; vector++) {
 526             ret = msix_set_notifier_for_vector(dev, vector);
 527             if (ret < 0) {
 528                 goto undo;
 529             }
 530         }
 531     }
 532     return 0;
 533
 534 undo:
 535     while (--vector >= 0) {
 536         msix_unset_notifier_for_vector(dev, vector);
 537     }
 538     dev->msix_vector_use_notifier = NULL;
 539     dev->msix_vector_release_notifier = NULL;
 540     return ret;
 541 }
 542
 543 void msix_unset_vector_notifiers(PCIDevice *dev)
 544 {
 545     int vector;
 546
 547     assert(dev->msix_vector_use_notifier &&
 548            dev->msix_vector_release_notifier);
 549
 550     if ((dev->config[dev->msix_cap + MSIX_CONTROL_OFFSET] &
 551         (MSIX_ENABLE_MASK | MSIX_MASKALL_MASK)) == MSIX_ENABLE_MASK) {
 552         for (vector = 0; vector < dev->msix_entries_nr; vector++) {
 553             msix_unset_notifier_for_vector(dev, vector);
 554         }
 555     }
 556     dev->msix_vector_use_notifier = NULL;
 557     dev->msix_vector_release_notifier = NULL;
 558 }