hw/ppc405_boards.c

   1 /*
   2  * QEMU PowerPC 405 evaluation boards emulation
   3  *
   4  * Copyright (c) 2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "ppc.h"
  26 #include "ppc405.h"
  27 #include "nvram.h"
  28 #include "flash.h"
  29 #include "sysemu.h"
  30 #include "block.h"
  31 #include "boards.h"
  32 #include "qemu-log.h"
  33 #include "loader.h"
  34 #include "blockdev.h"
  35 #include "exec-memory.h"
  36
  37 #define BIOS_FILENAME "ppc405_rom.bin"
  38 #define BIOS_SIZE (2048 * 1024)
  39
  40 #define KERNEL_LOAD_ADDR 0x00000000
  41 #define INITRD_LOAD_ADDR 0x01800000
  42
  43 #define USE_FLASH_BIOS
  44
  45 #define DEBUG_BOARD_INIT
  46
  47 /*****************************************************************************/
  48 /* PPC405EP reference board (IBM) */
  49 /* Standalone board with:
  50  * - PowerPC 405EP CPU
  51  * - SDRAM (0x00000000)
  52  * - Flash (0xFFF80000)
  53  * - SRAM  (0xFFF00000)
  54  * - NVRAM (0xF0000000)
  55  * - FPGA  (0xF0300000)
  56  */
  57 typedef struct ref405ep_fpga_t ref405ep_fpga_t;
  58 struct ref405ep_fpga_t {
  59     uint8_t reg0;
  60     uint8_t reg1;
  61 };
  62
  63 static uint32_t ref405ep_fpga_readb (void *opaque, target_phys_addr_t addr)
  64 {
  65     ref405ep_fpga_t *fpga;
  66     uint32_t ret;
  67
  68     fpga = opaque;
  69     switch (addr) {
  70     case 0x0:
  71         ret = fpga->reg0;
  72         break;
  73     case 0x1:
  74         ret = fpga->reg1;
  75         break;
  76     default:
  77         ret = 0;
  78         break;
  79     }
  80
  81     return ret;
  82 }
  83
  84 static void ref405ep_fpga_writeb (void *opaque,
  85                                   target_phys_addr_t addr, uint32_t value)
  86 {
  87     ref405ep_fpga_t *fpga;
  88
  89     fpga = opaque;
  90     switch (addr) {
  91     case 0x0:
  92         /* Read only */
  93         break;
  94     case 0x1:
  95         fpga->reg1 = value;
  96         break;
  97     default:
  98         break;
  99     }
 100 }
 101
 102 static uint32_t ref405ep_fpga_readw (void *opaque, target_phys_addr_t addr)
 103 {
 104     uint32_t ret;
 105
 106     ret = ref405ep_fpga_readb(opaque, addr) << 8;
 107     ret |= ref405ep_fpga_readb(opaque, addr + 1);
 108
 109     return ret;
 110 }
 111
 112 static void ref405ep_fpga_writew (void *opaque,
 113                                   target_phys_addr_t addr, uint32_t value)
 114 {
 115     ref405ep_fpga_writeb(opaque, addr, (value >> 8) & 0xFF);
 116     ref405ep_fpga_writeb(opaque, addr + 1, value & 0xFF);
 117 }
 118
 119 static uint32_t ref405ep_fpga_readl (void *opaque, target_phys_addr_t addr)
 120 {
 121     uint32_t ret;
 122
 123     ret = ref405ep_fpga_readb(opaque, addr) << 24;
 124     ret |= ref405ep_fpga_readb(opaque, addr + 1) << 16;
 125     ret |= ref405ep_fpga_readb(opaque, addr + 2) << 8;
 126     ret |= ref405ep_fpga_readb(opaque, addr + 3);
 127
 128     return ret;
 129 }
 130
 131 static void ref405ep_fpga_writel (void *opaque,
 132                                   target_phys_addr_t addr, uint32_t value)
 133 {
 134     ref405ep_fpga_writeb(opaque, addr, (value >> 24) & 0xFF);
 135     ref405ep_fpga_writeb(opaque, addr + 1, (value >> 16) & 0xFF);
 136     ref405ep_fpga_writeb(opaque, addr + 2, (value >> 8) & 0xFF);
 137     ref405ep_fpga_writeb(opaque, addr + 3, value & 0xFF);
 138 }
 139
 140 static const MemoryRegionOps ref405ep_fpga_ops = {
 141     .old_mmio = {
 142         .read = {
 143             ref405ep_fpga_readb, ref405ep_fpga_readw, ref405ep_fpga_readl,
 144         },
 145         .write = {
 146             ref405ep_fpga_writeb, ref405ep_fpga_writew, ref405ep_fpga_writel,
 147         },
 148     },
 149     .endianness = DEVICE_NATIVE_ENDIAN,
 150 };
 151
 152 static void ref405ep_fpga_reset (void *opaque)
 153 {
 154     ref405ep_fpga_t *fpga;
 155
 156     fpga = opaque;
 157     fpga->reg0 = 0x00;
 158     fpga->reg1 = 0x0F;
 159 }
 160
 161 static void ref405ep_fpga_init (MemoryRegion *sysmem, uint32_t base)
 162 {
 163     ref405ep_fpga_t *fpga;
 164     MemoryRegion *fpga_memory = g_new(MemoryRegion, 1);
 165
 166     fpga = g_malloc0(sizeof(ref405ep_fpga_t));
 167     memory_region_init_io(fpga_memory, &ref405ep_fpga_ops, fpga,
 168                           "fpga", 0x00000100);
 169     memory_region_add_subregion(sysmem, base, fpga_memory);
 170     qemu_register_reset(&ref405ep_fpga_reset, fpga);
 171 }
 172
 173 static void ref405ep_init (ram_addr_t ram_size,
 174                            const char *boot_device,
 175                            const char *kernel_filename,
 176                            const char *kernel_cmdline,
 177                            const char *initrd_filename,
 178                            const char *cpu_model)
 179 {
 180     char *filename;
 181     ppc4xx_bd_info_t bd;
 182     CPUPPCState *env;
 183     qemu_irq *pic;
 184     MemoryRegion *bios;
 185     MemoryRegion *sram = g_new(MemoryRegion, 1);
 186     ram_addr_t bdloc;
 187     MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
 188     target_phys_addr_t ram_bases[2], ram_sizes[2];
 189     target_ulong sram_size;
 190     long bios_size;
 191     //int phy_addr = 0;
 192     //static int phy_addr = 1;
 193     target_ulong kernel_base, initrd_base;
 194     long kernel_size, initrd_size;
 195     int linux_boot;
 196     int fl_idx, fl_sectors, len;
 197     DriveInfo *dinfo;
 198     MemoryRegion *sysmem = get_system_memory();
 199
 200     /* XXX: fix this */
 201     memory_region_init_ram(&ram_memories[0], "ef405ep.ram", 0x08000000);
 202     vmstate_register_ram_global(&ram_memories[0]);
 203     ram_bases[0] = 0;
 204     ram_sizes[0] = 0x08000000;
 205     memory_region_init(&ram_memories[1], "ef405ep.ram1", 0);
 206     ram_bases[1] = 0x00000000;
 207     ram_sizes[1] = 0x00000000;
 208     ram_size = 128 * 1024 * 1024;
 209 #ifdef DEBUG_BOARD_INIT
 210     printf("%s: register cpu\n", __func__);
 211 #endif
 212     env = ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
 213                         33333333, &pic, kernel_filename == NULL ? 0 : 1);
 214     /* allocate SRAM */
 215     sram_size = 512 * 1024;
 216     memory_region_init_ram(sram, "ef405ep.sram", sram_size);
 217     vmstate_register_ram_global(sram);
 218     memory_region_add_subregion(sysmem, 0xFFF00000, sram);
 219     /* allocate and load BIOS */
 220 #ifdef DEBUG_BOARD_INIT
 221     printf("%s: register BIOS\n", __func__);
 222 #endif
 223     fl_idx = 0;
 224 #ifdef USE_FLASH_BIOS
 225     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 226     if (dinfo) {
 227         bios_size = bdrv_getlength(dinfo->bdrv);
 228         fl_sectors = (bios_size + 65535) >> 16;
 229 #ifdef DEBUG_BOARD_INIT
 230         printf("Register parallel flash %d size %lx"
 231                " at addr %lx '%s' %d\n",
 232                fl_idx, bios_size, -bios_size,
 233                bdrv_get_device_name(dinfo->bdrv), fl_sectors);
 234 #endif
 235         pflash_cfi02_register((uint32_t)(-bios_size),
 236                               NULL, "ef405ep.bios", bios_size,
 237                               dinfo->bdrv, 65536, fl_sectors, 1,
 238                               2, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 239                               1);
 240         fl_idx++;
 241     } else
 242 #endif
 243     {
 244 #ifdef DEBUG_BOARD_INIT
 245         printf("Load BIOS from file\n");
 246 #endif
 247         bios = g_new(MemoryRegion, 1);
 248         memory_region_init_ram(bios, "ef405ep.bios", BIOS_SIZE);
 249         vmstate_register_ram_global(bios);
 250         if (bios_name == NULL)
 251             bios_name = BIOS_FILENAME;
 252         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 253         if (filename) {
 254             bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
 255             g_free(filename);
 256         } else {
 257             bios_size = -1;
 258         }
 259         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 260             fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
 261                     bios_name);
 262             exit(1);
 263         }
 264         bios_size = (bios_size + 0xfff) & ~0xfff;
 265         memory_region_set_readonly(bios, true);
 266         memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
 267     }
 268     /* Register FPGA */
 269 #ifdef DEBUG_BOARD_INIT
 270     printf("%s: register FPGA\n", __func__);
 271 #endif
 272     ref405ep_fpga_init(sysmem, 0xF0300000);
 273     /* Register NVRAM */
 274 #ifdef DEBUG_BOARD_INIT
 275     printf("%s: register NVRAM\n", __func__);
 276 #endif
 277     m48t59_init(NULL, 0xF0000000, 0, 8192, 8);
 278     /* Load kernel */
 279     linux_boot = (kernel_filename != NULL);
 280     if (linux_boot) {
 281 #ifdef DEBUG_BOARD_INIT
 282         printf("%s: load kernel\n", __func__);
 283 #endif
 284         memset(&bd, 0, sizeof(bd));
 285         bd.bi_memstart = 0x00000000;
 286         bd.bi_memsize = ram_size;
 287         bd.bi_flashstart = -bios_size;
 288         bd.bi_flashsize = -bios_size;
 289         bd.bi_flashoffset = 0;
 290         bd.bi_sramstart = 0xFFF00000;
 291         bd.bi_sramsize = sram_size;
 292         bd.bi_bootflags = 0;
 293         bd.bi_intfreq = 133333333;
 294         bd.bi_busfreq = 33333333;
 295         bd.bi_baudrate = 115200;
 296         bd.bi_s_version[0] = 'Q';
 297         bd.bi_s_version[1] = 'M';
 298         bd.bi_s_version[2] = 'U';
 299         bd.bi_s_version[3] = '\0';
 300         bd.bi_r_version[0] = 'Q';
 301         bd.bi_r_version[1] = 'E';
 302         bd.bi_r_version[2] = 'M';
 303         bd.bi_r_version[3] = 'U';
 304         bd.bi_r_version[4] = '\0';
 305         bd.bi_procfreq = 133333333;
 306         bd.bi_plb_busfreq = 33333333;
 307         bd.bi_pci_busfreq = 33333333;
 308         bd.bi_opbfreq = 33333333;
 309         bdloc = ppc405_set_bootinfo(env, &bd, 0x00000001);
 310         env->gpr[3] = bdloc;
 311         kernel_base = KERNEL_LOAD_ADDR;
 312         /* now we can load the kernel */
 313         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 314                                           ram_size - kernel_base);
 315         if (kernel_size < 0) {
 316             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 317                     kernel_filename);
 318             exit(1);
 319         }
 320         printf("Load kernel size %ld at " TARGET_FMT_lx,
 321                kernel_size, kernel_base);
 322         /* load initrd */
 323         if (initrd_filename) {
 324             initrd_base = INITRD_LOAD_ADDR;
 325             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 326                                               ram_size - initrd_base);
 327             if (initrd_size < 0) {
 328                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 329                         initrd_filename);
 330                 exit(1);
 331             }
 332         } else {
 333             initrd_base = 0;
 334             initrd_size = 0;
 335         }
 336         env->gpr[4] = initrd_base;
 337         env->gpr[5] = initrd_size;
 338         if (kernel_cmdline != NULL) {
 339             len = strlen(kernel_cmdline);
 340             bdloc -= ((len + 255) & ~255);
 341             cpu_physical_memory_write(bdloc, (void *)kernel_cmdline, len + 1);
 342             env->gpr[6] = bdloc;
 343             env->gpr[7] = bdloc + len;
 344         } else {
 345             env->gpr[6] = 0;
 346             env->gpr[7] = 0;
 347         }
 348         env->nip = KERNEL_LOAD_ADDR;
 349     } else {
 350         kernel_base = 0;
 351         kernel_size = 0;
 352         initrd_base = 0;
 353         initrd_size = 0;
 354         bdloc = 0;
 355     }
 356 #ifdef DEBUG_BOARD_INIT
 357     printf("%s: Done\n", __func__);
 358 #endif
 359     printf("bdloc " RAM_ADDR_FMT "\n", bdloc);
 360 }
 361
 362 static QEMUMachine ref405ep_machine = {
 363     .name = "ref405ep",
 364     .desc = "ref405ep",
 365     .init = ref405ep_init,
 366 };
 367
 368 /*****************************************************************************/
 369 /* AMCC Taihu evaluation board */
 370 /* - PowerPC 405EP processor
 371  * - SDRAM               128 MB at 0x00000000
 372  * - Boot flash          2 MB   at 0xFFE00000
 373  * - Application flash   32 MB  at 0xFC000000
 374  * - 2 serial ports
 375  * - 2 ethernet PHY
 376  * - 1 USB 1.1 device    0x50000000
 377  * - 1 LCD display       0x50100000
 378  * - 1 CPLD              0x50100000
 379  * - 1 I2C EEPROM
 380  * - 1 I2C thermal sensor
 381  * - a set of LEDs
 382  * - bit-bang SPI port using GPIOs
 383  * - 1 EBC interface connector 0 0x50200000
 384  * - 1 cardbus controller + expansion slot.
 385  * - 1 PCI expansion slot.
 386  */
 387 typedef struct taihu_cpld_t taihu_cpld_t;
 388 struct taihu_cpld_t {
 389     uint8_t reg0;
 390     uint8_t reg1;
 391 };
 392
 393 static uint32_t taihu_cpld_readb (void *opaque, target_phys_addr_t addr)
 394 {
 395     taihu_cpld_t *cpld;
 396     uint32_t ret;
 397
 398     cpld = opaque;
 399     switch (addr) {
 400     case 0x0:
 401         ret = cpld->reg0;
 402         break;
 403     case 0x1:
 404         ret = cpld->reg1;
 405         break;
 406     default:
 407         ret = 0;
 408         break;
 409     }
 410
 411     return ret;
 412 }
 413
 414 static void taihu_cpld_writeb (void *opaque,
 415                                target_phys_addr_t addr, uint32_t value)
 416 {
 417     taihu_cpld_t *cpld;
 418
 419     cpld = opaque;
 420     switch (addr) {
 421     case 0x0:
 422         /* Read only */
 423         break;
 424     case 0x1:
 425         cpld->reg1 = value;
 426         break;
 427     default:
 428         break;
 429     }
 430 }
 431
 432 static uint32_t taihu_cpld_readw (void *opaque, target_phys_addr_t addr)
 433 {
 434     uint32_t ret;
 435
 436     ret = taihu_cpld_readb(opaque, addr) << 8;
 437     ret |= taihu_cpld_readb(opaque, addr + 1);
 438
 439     return ret;
 440 }
 441
 442 static void taihu_cpld_writew (void *opaque,
 443                                target_phys_addr_t addr, uint32_t value)
 444 {
 445     taihu_cpld_writeb(opaque, addr, (value >> 8) & 0xFF);
 446     taihu_cpld_writeb(opaque, addr + 1, value & 0xFF);
 447 }
 448
 449 static uint32_t taihu_cpld_readl (void *opaque, target_phys_addr_t addr)
 450 {
 451     uint32_t ret;
 452
 453     ret = taihu_cpld_readb(opaque, addr) << 24;
 454     ret |= taihu_cpld_readb(opaque, addr + 1) << 16;
 455     ret |= taihu_cpld_readb(opaque, addr + 2) << 8;
 456     ret |= taihu_cpld_readb(opaque, addr + 3);
 457
 458     return ret;
 459 }
 460
 461 static void taihu_cpld_writel (void *opaque,
 462                                target_phys_addr_t addr, uint32_t value)
 463 {
 464     taihu_cpld_writel(opaque, addr, (value >> 24) & 0xFF);
 465     taihu_cpld_writel(opaque, addr + 1, (value >> 16) & 0xFF);
 466     taihu_cpld_writel(opaque, addr + 2, (value >> 8) & 0xFF);
 467     taihu_cpld_writeb(opaque, addr + 3, value & 0xFF);
 468 }
 469
 470 static const MemoryRegionOps taihu_cpld_ops = {
 471     .old_mmio = {
 472         .read = { taihu_cpld_readb, taihu_cpld_readw, taihu_cpld_readl, },
 473         .write = { taihu_cpld_writeb, taihu_cpld_writew, taihu_cpld_writel, },
 474     },
 475     .endianness = DEVICE_NATIVE_ENDIAN,
 476 };
 477
 478 static void taihu_cpld_reset (void *opaque)
 479 {
 480     taihu_cpld_t *cpld;
 481
 482     cpld = opaque;
 483     cpld->reg0 = 0x01;
 484     cpld->reg1 = 0x80;
 485 }
 486
 487 static void taihu_cpld_init (MemoryRegion *sysmem, uint32_t base)
 488 {
 489     taihu_cpld_t *cpld;
 490     MemoryRegion *cpld_memory = g_new(MemoryRegion, 1);
 491
 492     cpld = g_malloc0(sizeof(taihu_cpld_t));
 493     memory_region_init_io(cpld_memory, &taihu_cpld_ops, cpld, "cpld", 0x100);
 494     memory_region_add_subregion(sysmem, base, cpld_memory);
 495     qemu_register_reset(&taihu_cpld_reset, cpld);
 496 }
 497
 498 static void taihu_405ep_init(ram_addr_t ram_size,
 499                              const char *boot_device,
 500                              const char *kernel_filename,
 501                              const char *kernel_cmdline,
 502                              const char *initrd_filename,
 503                              const char *cpu_model)
 504 {
 505     char *filename;
 506     qemu_irq *pic;
 507     MemoryRegion *sysmem = get_system_memory();
 508     MemoryRegion *bios;
 509     MemoryRegion *ram_memories = g_malloc(2 * sizeof(*ram_memories));
 510     target_phys_addr_t ram_bases[2], ram_sizes[2];
 511     long bios_size;
 512     target_ulong kernel_base, initrd_base;
 513     long kernel_size, initrd_size;
 514     int linux_boot;
 515     int fl_idx, fl_sectors;
 516     DriveInfo *dinfo;
 517
 518     /* RAM is soldered to the board so the size cannot be changed */
 519     memory_region_init_ram(&ram_memories[0],
 520                            "taihu_405ep.ram-0", 0x04000000);
 521     vmstate_register_ram_global(&ram_memories[0]);
 522     ram_bases[0] = 0;
 523     ram_sizes[0] = 0x04000000;
 524     memory_region_init_ram(&ram_memories[1],
 525                            "taihu_405ep.ram-1", 0x04000000);
 526     vmstate_register_ram_global(&ram_memories[1]);
 527     ram_bases[1] = 0x04000000;
 528     ram_sizes[1] = 0x04000000;
 529     ram_size = 0x08000000;
 530 #ifdef DEBUG_BOARD_INIT
 531     printf("%s: register cpu\n", __func__);
 532 #endif
 533     ppc405ep_init(sysmem, ram_memories, ram_bases, ram_sizes,
 534                   33333333, &pic, kernel_filename == NULL ? 0 : 1);
 535     /* allocate and load BIOS */
 536 #ifdef DEBUG_BOARD_INIT
 537     printf("%s: register BIOS\n", __func__);
 538 #endif
 539     fl_idx = 0;
 540 #if defined(USE_FLASH_BIOS)
 541     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 542     if (dinfo) {
 543         bios_size = bdrv_getlength(dinfo->bdrv);
 544         /* XXX: should check that size is 2MB */
 545         //        bios_size = 2 * 1024 * 1024;
 546         fl_sectors = (bios_size + 65535) >> 16;
 547 #ifdef DEBUG_BOARD_INIT
 548         printf("Register parallel flash %d size %lx"
 549                " at addr %lx '%s' %d\n",
 550                fl_idx, bios_size, -bios_size,
 551                bdrv_get_device_name(dinfo->bdrv), fl_sectors);
 552 #endif
 553         pflash_cfi02_register((uint32_t)(-bios_size),
 554                               NULL, "taihu_405ep.bios", bios_size,
 555                               dinfo->bdrv, 65536, fl_sectors, 1,
 556                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 557                               1);
 558         fl_idx++;
 559     } else
 560 #endif
 561     {
 562 #ifdef DEBUG_BOARD_INIT
 563         printf("Load BIOS from file\n");
 564 #endif
 565         if (bios_name == NULL)
 566             bios_name = BIOS_FILENAME;
 567         bios = g_new(MemoryRegion, 1);
 568         memory_region_init_ram(bios, "taihu_405ep.bios", BIOS_SIZE);
 569         vmstate_register_ram_global(bios);
 570         filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 571         if (filename) {
 572             bios_size = load_image(filename, memory_region_get_ram_ptr(bios));
 573             g_free(filename);
 574         } else {
 575             bios_size = -1;
 576         }
 577         if (bios_size < 0 || bios_size > BIOS_SIZE) {
 578             fprintf(stderr, "qemu: could not load PowerPC bios '%s'\n",
 579                     bios_name);
 580             exit(1);
 581         }
 582         bios_size = (bios_size + 0xfff) & ~0xfff;
 583         memory_region_set_readonly(bios, true);
 584         memory_region_add_subregion(sysmem, (uint32_t)(-bios_size), bios);
 585     }
 586     /* Register Linux flash */
 587     dinfo = drive_get(IF_PFLASH, 0, fl_idx);
 588     if (dinfo) {
 589         bios_size = bdrv_getlength(dinfo->bdrv);
 590         /* XXX: should check that size is 32MB */
 591         bios_size = 32 * 1024 * 1024;
 592         fl_sectors = (bios_size + 65535) >> 16;
 593 #ifdef DEBUG_BOARD_INIT
 594         printf("Register parallel flash %d size %lx"
 595                " at addr " TARGET_FMT_lx " '%s'\n",
 596                fl_idx, bios_size, (target_ulong)0xfc000000,
 597                bdrv_get_device_name(dinfo->bdrv));
 598 #endif
 599         pflash_cfi02_register(0xfc000000, NULL, "taihu_405ep.flash", bios_size,
 600                               dinfo->bdrv, 65536, fl_sectors, 1,
 601                               4, 0x0001, 0x22DA, 0x0000, 0x0000, 0x555, 0x2AA,
 602                               1);
 603         fl_idx++;
 604     }
 605     /* Register CLPD & LCD display */
 606 #ifdef DEBUG_BOARD_INIT
 607     printf("%s: register CPLD\n", __func__);
 608 #endif
 609     taihu_cpld_init(sysmem, 0x50100000);
 610     /* Load kernel */
 611     linux_boot = (kernel_filename != NULL);
 612     if (linux_boot) {
 613 #ifdef DEBUG_BOARD_INIT
 614         printf("%s: load kernel\n", __func__);
 615 #endif
 616         kernel_base = KERNEL_LOAD_ADDR;
 617         /* now we can load the kernel */
 618         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 619                                           ram_size - kernel_base);
 620         if (kernel_size < 0) {
 621             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 622                     kernel_filename);
 623             exit(1);
 624         }
 625         /* load initrd */
 626         if (initrd_filename) {
 627             initrd_base = INITRD_LOAD_ADDR;
 628             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 629                                               ram_size - initrd_base);
 630             if (initrd_size < 0) {
 631                 fprintf(stderr,
 632                         "qemu: could not load initial ram disk '%s'\n",
 633                         initrd_filename);
 634                 exit(1);
 635             }
 636         } else {
 637             initrd_base = 0;
 638             initrd_size = 0;
 639         }
 640     } else {
 641         kernel_base = 0;
 642         kernel_size = 0;
 643         initrd_base = 0;
 644         initrd_size = 0;
 645     }
 646 #ifdef DEBUG_BOARD_INIT
 647     printf("%s: Done\n", __func__);
 648 #endif
 649 }
 650
 651 static QEMUMachine taihu_machine = {
 652     .name = "taihu",
 653     .desc = "taihu",
 654     .init = taihu_405ep_init,
 655 };
 656
 657 static void ppc405_machine_init(void)
 658 {
 659     qemu_register_machine(&ref405ep_machine);
 660     qemu_register_machine(&taihu_machine);
 661 }
 662
 663 machine_init(ppc405_machine_init);