include/hw/i386/pc.h

   1 #ifndef HW_PC_H
   2 #define HW_PC_H
   3
   4 #include "qemu-common.h"
   5 #include "exec/memory.h"
   6 #include "hw/isa/isa.h"
   7 #include "hw/block/fdc.h"
   8 #include "net/net.h"
   9 #include "hw/i386/ioapic.h"
  10
  11 #include "qemu/range.h"
  12 #include "qemu/bitmap.h"
  13 #include "sysemu/sysemu.h"
  14 #include "hw/pci/pci.h"
  15 #include "hw/boards.h"
  16
  17 #define HPET_INTCAP "hpet-intcap"
  18
  19 /**
  20  * PCMachineState:
  21  * @hotplug_memory_base: address in guest RAM address space where hotplug memory
  22  * address space begins.
  23  * @hotplug_memory: hotplug memory addess space container
  24  * @acpi_dev: link to ACPI PM device that performs ACPI hotplug handling
  25  */
  26 struct PCMachineState {
  27     /*< private >*/
  28     MachineState parent_obj;
  29
  30     /* <public> */
  31     ram_addr_t hotplug_memory_base;
  32     MemoryRegion hotplug_memory;
  33
  34     HotplugHandler *acpi_dev;
  35 };
  36
  37 #define PC_MACHINE_ACPI_DEVICE_PROP "acpi-device"
  38 #define PC_MACHINE_MEMHP_REGION_SIZE "hotplug-memory-region-size"
  39
  40 /**
  41  * PCMachineClass:
  42  * @get_hotplug_handler: pointer to parent class callback @get_hotplug_handler
  43  */
  44 struct PCMachineClass {
  45     /*< private >*/
  46     MachineClass parent_class;
  47
  48     /*< public >*/
  49     HotplugHandler *(*get_hotplug_handler)(MachineState *machine,
  50                                            DeviceState *dev);
  51 };
  52
  53 typedef struct PCMachineState PCMachineState;
  54 typedef struct PCMachineClass PCMachineClass;
  55
  56 #define TYPE_PC_MACHINE "generic-pc-machine"
  57 #define PC_MACHINE(obj) \
  58     OBJECT_CHECK(PCMachineState, (obj), TYPE_PC_MACHINE)
  59 #define PC_MACHINE_GET_CLASS(obj) \
  60     OBJECT_GET_CLASS(PCMachineClass, (obj), TYPE_PC_MACHINE)
  61 #define PC_MACHINE_CLASS(klass) \
  62     OBJECT_CLASS_CHECK(PCMachineClass, (klass), TYPE_PC_MACHINE)
  63
  64 void qemu_register_pc_machine(QEMUMachine *m);
  65
  66 /* PC-style peripherals (also used by other machines).  */
  67
  68 typedef struct PcPciInfo {
  69     Range w32;
  70     Range w64;
  71 } PcPciInfo;
  72
  73 #define ACPI_PM_PROP_S3_DISABLED "disable_s3"
  74 #define ACPI_PM_PROP_S4_DISABLED "disable_s4"
  75 #define ACPI_PM_PROP_S4_VAL "s4_val"
  76 #define ACPI_PM_PROP_SCI_INT "sci_int"
  77 #define ACPI_PM_PROP_ACPI_ENABLE_CMD "acpi_enable_cmd"
  78 #define ACPI_PM_PROP_ACPI_DISABLE_CMD "acpi_disable_cmd"
  79 #define ACPI_PM_PROP_PM_IO_BASE "pm_io_base"
  80 #define ACPI_PM_PROP_GPE0_BLK "gpe0_blk"
  81 #define ACPI_PM_PROP_GPE0_BLK_LEN "gpe0_blk_len"
  82
  83 struct PcGuestInfo {
  84     bool has_pci_info;
  85     bool isapc_ram_fw;
  86     hwaddr ram_size, ram_size_below_4g;
  87     unsigned apic_id_limit;
  88     bool apic_xrupt_override;
  89     uint64_t numa_nodes;
  90     uint64_t *node_mem;
  91     uint64_t *node_cpu;
  92     FWCfgState *fw_cfg;
  93     bool has_acpi_build;
  94     bool has_reserved_memory;
  95 };
  96
  97 /* parallel.c */
  98 static inline bool parallel_init(ISABus *bus, int index, CharDriverState *chr)
  99 {
 100     DeviceState *dev;
 101     ISADevice *isadev;
 102
 103     isadev = isa_try_create(bus, "isa-parallel");
 104     if (!isadev) {
 105         return false;
 106     }
 107     dev = DEVICE(isadev);
 108     qdev_prop_set_uint32(dev, "index", index);
 109     qdev_prop_set_chr(dev, "chardev", chr);
 110     if (qdev_init(dev) < 0) {
 111         return false;
 112     }
 113     return true;
 114 }
 115
 116 bool parallel_mm_init(MemoryRegion *address_space,
 117                       hwaddr base, int it_shift, qemu_irq irq,
 118                       CharDriverState *chr);
 119
 120 /* i8259.c */
 121
 122 extern DeviceState *isa_pic;
 123 qemu_irq *i8259_init(ISABus *bus, qemu_irq parent_irq);
 124 qemu_irq *kvm_i8259_init(ISABus *bus);
 125 int pic_read_irq(DeviceState *d);
 126 int pic_get_output(DeviceState *d);
 127 void pic_info(Monitor *mon, const QDict *qdict);
 128 void irq_info(Monitor *mon, const QDict *qdict);
 129
 130 /* Global System Interrupts */
 131
 132 #define GSI_NUM_PINS IOAPIC_NUM_PINS
 133
 134 typedef struct GSIState {
 135     qemu_irq i8259_irq[ISA_NUM_IRQS];
 136     qemu_irq ioapic_irq[IOAPIC_NUM_PINS];
 137 } GSIState;
 138
 139 void gsi_handler(void *opaque, int n, int level);
 140
 141 /* vmport.c */
 142 typedef uint32_t (VMPortReadFunc)(void *opaque, uint32_t address);
 143
 144 static inline void vmport_init(ISABus *bus)
 145 {
 146     isa_create_simple(bus, "vmport");
 147 }
 148
 149 void vmport_register(unsigned char command, VMPortReadFunc *func, void *opaque);
 150 void vmmouse_get_data(uint32_t *data);
 151 void vmmouse_set_data(const uint32_t *data);
 152
 153 /* pckbd.c */
 154
 155 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
 156 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
 157                    MemoryRegion *region, ram_addr_t size,
 158                    hwaddr mask);
 159 void i8042_isa_mouse_fake_event(void *opaque);
 160 void i8042_setup_a20_line(ISADevice *dev, qemu_irq *a20_out);
 161
 162 /* pc.c */
 163 extern int fd_bootchk;
 164
 165 void pc_register_ferr_irq(qemu_irq irq);
 166 void pc_acpi_smi_interrupt(void *opaque, int irq, int level);
 167
 168 void pc_cpus_init(const char *cpu_model, DeviceState *icc_bridge);
 169 void pc_hot_add_cpu(const int64_t id, Error **errp);
 170 void pc_acpi_init(const char *default_dsdt);
 171
 172 PcGuestInfo *pc_guest_info_init(ram_addr_t below_4g_mem_size,
 173                                 ram_addr_t above_4g_mem_size);
 174
 175 #define PCI_HOST_PROP_PCI_HOLE_START   "pci-hole-start"
 176 #define PCI_HOST_PROP_PCI_HOLE_END     "pci-hole-end"
 177 #define PCI_HOST_PROP_PCI_HOLE64_START "pci-hole64-start"
 178 #define PCI_HOST_PROP_PCI_HOLE64_END   "pci-hole64-end"
 179 #define PCI_HOST_PROP_PCI_HOLE64_SIZE  "pci-hole64-size"
 180 #define DEFAULT_PCI_HOLE64_SIZE (~0x0ULL)
 181
 182
 183 void pc_pci_as_mapping_init(Object *owner, MemoryRegion *system_memory,
 184                             MemoryRegion *pci_address_space);
 185
 186 FWCfgState *pc_memory_init(MemoryRegion *system_memory,
 187                            const char *kernel_filename,
 188                            const char *kernel_cmdline,
 189                            const char *initrd_filename,
 190                            ram_addr_t below_4g_mem_size,
 191                            ram_addr_t above_4g_mem_size,
 192                            MemoryRegion *rom_memory,
 193                            MemoryRegion **ram_memory,
 194                            PcGuestInfo *guest_info);
 195 qemu_irq *pc_allocate_cpu_irq(void);
 196 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus);
 197 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
 198                           ISADevice **rtc_state,
 199                           ISADevice **floppy,
 200                           bool no_vmport,
 201                           uint32 hpet_irqs);
 202 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd);
 203 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 204                   const char *boot_device,
 205                   ISADevice *floppy, BusState *ide0, BusState *ide1,
 206                   ISADevice *s);
 207 void pc_nic_init(ISABus *isa_bus, PCIBus *pci_bus);
 208 void pc_pci_device_init(PCIBus *pci_bus);
 209
 210 typedef void (*cpu_set_smm_t)(int smm, void *arg);
 211 void cpu_smm_register(cpu_set_smm_t callback, void *arg);
 212
 213 void ioapic_init_gsi(GSIState *gsi_state, const char *parent_name);
 214
 215 /* acpi_piix.c */
 216
 217 I2CBus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 218                       qemu_irq sci_irq, qemu_irq smi_irq,
 219                       int kvm_enabled, FWCfgState *fw_cfg,
 220                       DeviceState **piix4_pm);
 221 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
 222
 223 /* hpet.c */
 224 extern int no_hpet;
 225
 226 /* piix_pci.c */
 227 struct PCII440FXState;
 228 typedef struct PCII440FXState PCII440FXState;
 229
 230 PCIBus *i440fx_init(PCII440FXState **pi440fx_state, int *piix_devfn,
 231                     ISABus **isa_bus, qemu_irq *pic,
 232                     MemoryRegion *address_space_mem,
 233                     MemoryRegion *address_space_io,
 234                     ram_addr_t ram_size,
 235                     ram_addr_t below_4g_mem_size,
 236                     ram_addr_t above_4g_mem_size,
 237                     MemoryRegion *pci_memory,
 238                     MemoryRegion *ram_memory);
 239
 240 PCIBus *find_i440fx(void);
 241 /* piix4.c */
 242 extern PCIDevice *piix4_dev;
 243 int piix4_init(PCIBus *bus, ISABus **isa_bus, int devfn);
 244
 245 /* vga.c */
 246 enum vga_retrace_method {
 247     VGA_RETRACE_DUMB,
 248     VGA_RETRACE_PRECISE
 249 };
 250
 251 extern enum vga_retrace_method vga_retrace_method;
 252
 253 int isa_vga_mm_init(hwaddr vram_base,
 254                     hwaddr ctrl_base, int it_shift,
 255                     MemoryRegion *address_space);
 256
 257 /* ne2000.c */
 258 static inline bool isa_ne2000_init(ISABus *bus, int base, int irq, NICInfo *nd)
 259 {
 260     DeviceState *dev;
 261     ISADevice *isadev;
 262
 263     qemu_check_nic_model(nd, "ne2k_isa");
 264
 265     isadev = isa_try_create(bus, "ne2k_isa");
 266     if (!isadev) {
 267         return false;
 268     }
 269     dev = DEVICE(isadev);
 270     qdev_prop_set_uint32(dev, "iobase", base);
 271     qdev_prop_set_uint32(dev, "irq",    irq);
 272     qdev_set_nic_properties(dev, nd);
 273     qdev_init_nofail(dev);
 274     return true;
 275 }
 276
 277 /* pc_sysfw.c */
 278 void pc_system_firmware_init(MemoryRegion *rom_memory,
 279                              bool isapc_ram_fw);
 280
 281 /* pvpanic.c */
 282 uint16_t pvpanic_port(void);
 283
 284 /* e820 types */
 285 #define E820_RAM        1
 286 #define E820_RESERVED   2
 287 #define E820_ACPI       3
 288 #define E820_NVS        4
 289 #define E820_UNUSABLE   5
 290
 291 int e820_add_entry(uint64_t, uint64_t, uint32_t);
 292 int e820_get_num_entries(void);
 293 bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *);
 294
 295 #define PC_Q35_COMPAT_2_0 \
 296         PC_COMPAT_2_0, \
 297         {\
 298             .driver   = "ICH9 LPC",\
 299             .property = "memory-hotplug-support",\
 300             .value    = "off",\
 301         }
 302
 303 #define PC_Q35_COMPAT_1_7 \
 304         PC_COMPAT_1_7, \
 305         PC_Q35_COMPAT_2_0, \
 306         {\
 307             .driver   = "hpet",\
 308             .property = HPET_INTCAP,\
 309             .value    = stringify(4),\
 310         }
 311
 312 #define PC_Q35_COMPAT_1_6 \
 313         PC_COMPAT_1_6, \
 314         PC_Q35_COMPAT_1_7
 315
 316 #define PC_Q35_COMPAT_1_5 \
 317         PC_COMPAT_1_5, \
 318         PC_Q35_COMPAT_1_6
 319
 320 #define PC_Q35_COMPAT_1_4 \
 321         PC_COMPAT_1_4, \
 322         PC_Q35_COMPAT_1_5
 323
 324 #define PC_COMPAT_2_0 \
 325         {\
 326             .driver   = "PIIX4_PM",\
 327             .property = "memory-hotplug-support",\
 328             .value    = "off",\
 329         },\
 330         {\
 331             .driver   = "apic",\
 332             .property = "version",\
 333             .value    = stringify(0x11),\
 334         },\
 335         {\
 336             .driver   = "nec-usb-xhci",\
 337             .property = "superspeed-ports-first",\
 338             .value    = "off",\
 339         },\
 340         {\
 341             .driver   = "pci-serial",\
 342             .property = "prog_if",\
 343             .value    = stringify(0),\
 344         },\
 345         {\
 346             .driver   = "pci-serial-2x",\
 347             .property = "prof_if",\
 348             .value    = stringify(0),\
 349         },\
 350         {\
 351             .driver   = "pci-serial-4x",\
 352             .property = "prog_if",\
 353             .value    = stringify(0),\
 354         }
 355
 356 #define PC_COMPAT_1_7 \
 357         PC_COMPAT_2_0, \
 358         {\
 359             .driver   = TYPE_USB_DEVICE,\
 360             .property = "msos-desc",\
 361             .value    = "no",\
 362         },\
 363         {\
 364             .driver   = "PIIX4_PM",\
 365             .property = "acpi-pci-hotplug-with-bridge-support",\
 366             .value    = "off",\
 367         }
 368
 369 #define PC_COMPAT_1_6 \
 370         PC_COMPAT_1_7, \
 371         {\
 372             .driver   = "e1000",\
 373             .property = "mitigation",\
 374             .value    = "off",\
 375         },{\
 376             .driver   = "qemu64-" TYPE_X86_CPU,\
 377             .property = "model",\
 378             .value    = stringify(2),\
 379         },{\
 380             .driver   = "qemu32-" TYPE_X86_CPU,\
 381             .property = "model",\
 382             .value    = stringify(3),\
 383         },{\
 384             .driver   = "i440FX-pcihost",\
 385             .property = "short_root_bus",\
 386             .value    = stringify(1),\
 387         },{\
 388             .driver   = "q35-pcihost",\
 389             .property = "short_root_bus",\
 390             .value    = stringify(1),\
 391         }
 392
 393 #define PC_COMPAT_1_5 \
 394         PC_COMPAT_1_6, \
 395         {\
 396             .driver   = "Conroe-" TYPE_X86_CPU,\
 397             .property = "model",\
 398             .value    = stringify(2),\
 399         },{\
 400             .driver   = "Conroe-" TYPE_X86_CPU,\
 401             .property = "level",\
 402             .value    = stringify(2),\
 403         },{\
 404             .driver   = "Penryn-" TYPE_X86_CPU,\
 405             .property = "model",\
 406             .value    = stringify(2),\
 407         },{\
 408             .driver   = "Penryn-" TYPE_X86_CPU,\
 409             .property = "level",\
 410             .value    = stringify(2),\
 411         },{\
 412             .driver   = "Nehalem-" TYPE_X86_CPU,\
 413             .property = "model",\
 414             .value    = stringify(2),\
 415         },{\
 416             .driver   = "Nehalem-" TYPE_X86_CPU,\
 417             .property = "level",\
 418             .value    = stringify(2),\
 419         },{\
 420             .driver   = "virtio-net-pci",\
 421             .property = "any_layout",\
 422             .value    = "off",\
 423         },{\
 424             .driver = TYPE_X86_CPU,\
 425             .property = "pmu",\
 426             .value = "on",\
 427         },{\
 428             .driver   = "i440FX-pcihost",\
 429             .property = "short_root_bus",\
 430             .value    = stringify(0),\
 431         },{\
 432             .driver   = "q35-pcihost",\
 433             .property = "short_root_bus",\
 434             .value    = stringify(0),\
 435         }
 436
 437 #define PC_COMPAT_1_4 \
 438         PC_COMPAT_1_5, \
 439         {\
 440             .driver   = "scsi-hd",\
 441             .property = "discard_granularity",\
 442             .value    = stringify(0),\
 443         },{\
 444             .driver   = "scsi-cd",\
 445             .property = "discard_granularity",\
 446             .value    = stringify(0),\
 447         },{\
 448             .driver   = "scsi-disk",\
 449             .property = "discard_granularity",\
 450             .value    = stringify(0),\
 451         },{\
 452             .driver   = "ide-hd",\
 453             .property = "discard_granularity",\
 454             .value    = stringify(0),\
 455         },{\
 456             .driver   = "ide-cd",\
 457             .property = "discard_granularity",\
 458             .value    = stringify(0),\
 459         },{\
 460             .driver   = "ide-drive",\
 461             .property = "discard_granularity",\
 462             .value    = stringify(0),\
 463         },{\
 464             .driver   = "virtio-blk-pci",\
 465             .property = "discard_granularity",\
 466             .value    = stringify(0),\
 467         },{\
 468             .driver   = "virtio-serial-pci",\
 469             .property = "vectors",\
 470             /* DEV_NVECTORS_UNSPECIFIED as a uint32_t string */\
 471             .value    = stringify(0xFFFFFFFF),\
 472         },{ \
 473             .driver   = "virtio-net-pci", \
 474             .property = "ctrl_guest_offloads", \
 475             .value    = "off", \
 476         },{\
 477             .driver   = "e1000",\
 478             .property = "romfile",\
 479             .value    = "pxe-e1000.rom",\
 480         },{\
 481             .driver   = "ne2k_pci",\
 482             .property = "romfile",\
 483             .value    = "pxe-ne2k_pci.rom",\
 484         },{\
 485             .driver   = "pcnet",\
 486             .property = "romfile",\
 487             .value    = "pxe-pcnet.rom",\
 488         },{\
 489             .driver   = "rtl8139",\
 490             .property = "romfile",\
 491             .value    = "pxe-rtl8139.rom",\
 492         },{\
 493             .driver   = "virtio-net-pci",\
 494             .property = "romfile",\
 495             .value    = "pxe-virtio.rom",\
 496         },{\
 497             .driver   = "486-" TYPE_X86_CPU,\
 498             .property = "model",\
 499             .value    = stringify(0),\
 500         }
 501
 502 #define PC_COMMON_MACHINE_OPTIONS \
 503     .default_boot_order = "cad"
 504
 505 #define PC_DEFAULT_MACHINE_OPTIONS \
 506     PC_COMMON_MACHINE_OPTIONS, \
 507     .hot_add_cpu = pc_hot_add_cpu, \
 508     .max_cpus = 255
 509
 510 #endif