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memory: Flush coalesced MMIO on mapping and state changes
[qemu-kvm.git] / target-i386 / translate.c
blobeb0cabcf191bb54f9a4f4d30d23b33031cb986c9
1 /*
2 * i386 translation
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 *
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
10 *
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
15 *
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
18 */
19 #include <stdarg.h>
20 #include <stdlib.h>
21 #include <stdio.h>
22 #include <string.h>
23 #include <inttypes.h>
24 #include <signal.h>
25
26 #include "cpu.h"
27 #include "disas.h"
28 #include "tcg-op.h"
29
30 #include "helper.h"
31 #define GEN_HELPER 1
32 #include "helper.h"
33
34 #define PREFIX_REPZ 0x01
35 #define PREFIX_REPNZ 0x02
36 #define PREFIX_LOCK 0x04
37 #define PREFIX_DATA 0x08
38 #define PREFIX_ADR 0x10
39
40 #ifdef TARGET_X86_64
41 #define CODE64(s) ((s)->code64)
42 #define REX_X(s) ((s)->rex_x)
43 #define REX_B(s) ((s)->rex_b)
44 #else
45 #define CODE64(s) 0
46 #define REX_X(s) 0
47 #define REX_B(s) 0
48 #endif
49
50 //#define MACRO_TEST 1
51
52 /* global register indexes */
53 static TCGv_ptr cpu_env;
54 static TCGv cpu_A0, cpu_cc_src, cpu_cc_dst, cpu_cc_tmp;
55 static TCGv_i32 cpu_cc_op;
56 static TCGv cpu_regs[CPU_NB_REGS];
57 /* local temps */
58 static TCGv cpu_T[2], cpu_T3;
59 /* local register indexes (only used inside old micro ops) */
60 static TCGv cpu_tmp0, cpu_tmp4;
61 static TCGv_ptr cpu_ptr0, cpu_ptr1;
62 static TCGv_i32 cpu_tmp2_i32, cpu_tmp3_i32;
63 static TCGv_i64 cpu_tmp1_i64;
64 static TCGv cpu_tmp5;
65
66 static uint8_t gen_opc_cc_op[OPC_BUF_SIZE];
67
68 #include "gen-icount.h"
69
70 #ifdef TARGET_X86_64
71 static int x86_64_hregs;
72 #endif
73
74 typedef struct DisasContext {
75 /* current insn context */
76 int override; /* -1 if no override */
77 int prefix;
78 int aflag, dflag;
79 target_ulong pc; /* pc = eip + cs_base */
80 int is_jmp; /* 1 = means jump (stop translation), 2 means CPU
81 static state change (stop translation) */
82 /* current block context */
83 target_ulong cs_base; /* base of CS segment */
84 int pe; /* protected mode */
85 int code32; /* 32 bit code segment */
86 #ifdef TARGET_X86_64
87 int lma; /* long mode active */
88 int code64; /* 64 bit code segment */
89 int rex_x, rex_b;
90 #endif
91 int ss32; /* 32 bit stack segment */
92 int cc_op; /* current CC operation */
93 int addseg; /* non zero if either DS/ES/SS have a non zero base */
94 int f_st; /* currently unused */
95 int vm86; /* vm86 mode */
96 int cpl;
97 int iopl;
98 int tf; /* TF cpu flag */
99 int singlestep_enabled; /* "hardware" single step enabled */
100 int jmp_opt; /* use direct block chaining for direct jumps */
101 int mem_index; /* select memory access functions */
102 uint64_t flags; /* all execution flags */
103 struct TranslationBlock *tb;
104 int popl_esp_hack; /* for correct popl with esp base handling */
105 int rip_offset; /* only used in x86_64, but left for simplicity */
106 int cpuid_features;
107 int cpuid_ext_features;
108 int cpuid_ext2_features;
109 int cpuid_ext3_features;
110 } DisasContext;
111
112 static void gen_eob(DisasContext *s);
113 static void gen_jmp(DisasContext *s, target_ulong eip);
114 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num);
115
116 /* i386 arith/logic operations */
117 enum {
118 OP_ADDL,
119 OP_ORL,
120 OP_ADCL,
121 OP_SBBL,
122 OP_ANDL,
123 OP_SUBL,
124 OP_XORL,
125 OP_CMPL,
126 };
127
128 /* i386 shift ops */
129 enum {
130 OP_ROL,
131 OP_ROR,
132 OP_RCL,
133 OP_RCR,
134 OP_SHL,
135 OP_SHR,
136 OP_SHL1, /* undocumented */
137 OP_SAR = 7,
138 };
139
140 enum {
141 JCC_O,
142 JCC_B,
143 JCC_Z,
144 JCC_BE,
145 JCC_S,
146 JCC_P,
147 JCC_L,
148 JCC_LE,
149 };
150
151 /* operand size */
152 enum {
153 OT_BYTE = 0,
154 OT_WORD,
155 OT_LONG,
156 OT_QUAD,
157 };
158
159 enum {
160 /* I386 int registers */
161 OR_EAX, /* MUST be even numbered */
162 OR_ECX,
163 OR_EDX,
164 OR_EBX,
165 OR_ESP,
166 OR_EBP,
167 OR_ESI,
168 OR_EDI,
169
170 OR_TMP0 = 16, /* temporary operand register */
171 OR_TMP1,
172 OR_A0, /* temporary register used when doing address evaluation */
173 };
174
175 static inline void gen_op_movl_T0_0(void)
176 {
177 tcg_gen_movi_tl(cpu_T[0], 0);
178 }
179
180 static inline void gen_op_movl_T0_im(int32_t val)
181 {
182 tcg_gen_movi_tl(cpu_T[0], val);
183 }
184
185 static inline void gen_op_movl_T0_imu(uint32_t val)
186 {
187 tcg_gen_movi_tl(cpu_T[0], val);
188 }
189
190 static inline void gen_op_movl_T1_im(int32_t val)
191 {
192 tcg_gen_movi_tl(cpu_T[1], val);
193 }
194
195 static inline void gen_op_movl_T1_imu(uint32_t val)
196 {
197 tcg_gen_movi_tl(cpu_T[1], val);
198 }
199
200 static inline void gen_op_movl_A0_im(uint32_t val)
201 {
202 tcg_gen_movi_tl(cpu_A0, val);
203 }
204
205 #ifdef TARGET_X86_64
206 static inline void gen_op_movq_A0_im(int64_t val)
207 {
208 tcg_gen_movi_tl(cpu_A0, val);
209 }
210 #endif
211
212 static inline void gen_movtl_T0_im(target_ulong val)
213 {
214 tcg_gen_movi_tl(cpu_T[0], val);
215 }
216
217 static inline void gen_movtl_T1_im(target_ulong val)
218 {
219 tcg_gen_movi_tl(cpu_T[1], val);
220 }
221
222 static inline void gen_op_andl_T0_ffff(void)
223 {
224 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
225 }
226
227 static inline void gen_op_andl_T0_im(uint32_t val)
228 {
229 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], val);
230 }
231
232 static inline void gen_op_movl_T0_T1(void)
233 {
234 tcg_gen_mov_tl(cpu_T[0], cpu_T[1]);
235 }
236
237 static inline void gen_op_andl_A0_ffff(void)
238 {
239 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffff);
240 }
241
242 #ifdef TARGET_X86_64
243
244 #define NB_OP_SIZES 4
245
246 #else /* !TARGET_X86_64 */
247
248 #define NB_OP_SIZES 3
249
250 #endif /* !TARGET_X86_64 */
251
252 #if defined(HOST_WORDS_BIGENDIAN)
253 #define REG_B_OFFSET (sizeof(target_ulong) - 1)
254 #define REG_H_OFFSET (sizeof(target_ulong) - 2)
255 #define REG_W_OFFSET (sizeof(target_ulong) - 2)
256 #define REG_L_OFFSET (sizeof(target_ulong) - 4)
257 #define REG_LH_OFFSET (sizeof(target_ulong) - 8)
258 #else
259 #define REG_B_OFFSET 0
260 #define REG_H_OFFSET 1
261 #define REG_W_OFFSET 0
262 #define REG_L_OFFSET 0
263 #define REG_LH_OFFSET 4
264 #endif
265
266 /* In instruction encodings for byte register accesses the
267 * register number usually indicates "low 8 bits of register N";
268 * however there are some special cases where N 4..7 indicates
269 * [AH, CH, DH, BH], ie "bits 15..8 of register N-4". Return
270 * true for this special case, false otherwise.
271 */
272 static inline bool byte_reg_is_xH(int reg)
273 {
274 if (reg < 4) {
275 return false;
276 }
277 #ifdef TARGET_X86_64
278 if (reg >= 8 || x86_64_hregs) {
279 return false;
280 }
281 #endif
282 return true;
283 }
284
285 static inline void gen_op_mov_reg_v(int ot, int reg, TCGv t0)
286 {
287 switch(ot) {
288 case OT_BYTE:
289 if (!byte_reg_is_xH(reg)) {
290 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 8);
291 } else {
292 tcg_gen_deposit_tl(cpu_regs[reg - 4], cpu_regs[reg - 4], t0, 8, 8);
293 }
294 break;
295 case OT_WORD:
296 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], t0, 0, 16);
297 break;
298 default: /* XXX this shouldn't be reached; abort? */
299 case OT_LONG:
300 /* For x86_64, this sets the higher half of register to zero.
301 For i386, this is equivalent to a mov. */
302 tcg_gen_ext32u_tl(cpu_regs[reg], t0);
303 break;
304 #ifdef TARGET_X86_64
305 case OT_QUAD:
306 tcg_gen_mov_tl(cpu_regs[reg], t0);
307 break;
308 #endif
309 }
310 }
311
312 static inline void gen_op_mov_reg_T0(int ot, int reg)
313 {
314 gen_op_mov_reg_v(ot, reg, cpu_T[0]);
315 }
316
317 static inline void gen_op_mov_reg_T1(int ot, int reg)
318 {
319 gen_op_mov_reg_v(ot, reg, cpu_T[1]);
320 }
321
322 static inline void gen_op_mov_reg_A0(int size, int reg)
323 {
324 switch(size) {
325 case 0:
326 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_A0, 0, 16);
327 break;
328 default: /* XXX this shouldn't be reached; abort? */
329 case 1:
330 /* For x86_64, this sets the higher half of register to zero.
331 For i386, this is equivalent to a mov. */
332 tcg_gen_ext32u_tl(cpu_regs[reg], cpu_A0);
333 break;
334 #ifdef TARGET_X86_64
335 case 2:
336 tcg_gen_mov_tl(cpu_regs[reg], cpu_A0);
337 break;
338 #endif
339 }
340 }
341
342 static inline void gen_op_mov_v_reg(int ot, TCGv t0, int reg)
343 {
344 if (ot == OT_BYTE && byte_reg_is_xH(reg)) {
345 tcg_gen_shri_tl(t0, cpu_regs[reg - 4], 8);
346 tcg_gen_ext8u_tl(t0, t0);
347 } else {
348 tcg_gen_mov_tl(t0, cpu_regs[reg]);
349 }
350 }
351
352 static inline void gen_op_mov_TN_reg(int ot, int t_index, int reg)
353 {
354 gen_op_mov_v_reg(ot, cpu_T[t_index], reg);
355 }
356
357 static inline void gen_op_movl_A0_reg(int reg)
358 {
359 tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
360 }
361
362 static inline void gen_op_addl_A0_im(int32_t val)
363 {
364 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
365 #ifdef TARGET_X86_64
366 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
367 #endif
368 }
369
370 #ifdef TARGET_X86_64
371 static inline void gen_op_addq_A0_im(int64_t val)
372 {
373 tcg_gen_addi_tl(cpu_A0, cpu_A0, val);
374 }
375 #endif
376
377 static void gen_add_A0_im(DisasContext *s, int val)
378 {
379 #ifdef TARGET_X86_64
380 if (CODE64(s))
381 gen_op_addq_A0_im(val);
382 else
383 #endif
384 gen_op_addl_A0_im(val);
385 }
386
387 static inline void gen_op_addl_T0_T1(void)
388 {
389 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
390 }
391
392 static inline void gen_op_jmp_T0(void)
393 {
394 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, eip));
395 }
396
397 static inline void gen_op_add_reg_im(int size, int reg, int32_t val)
398 {
399 switch(size) {
400 case 0:
401 tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
402 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16);
403 break;
404 case 1:
405 tcg_gen_addi_tl(cpu_tmp0, cpu_regs[reg], val);
406 /* For x86_64, this sets the higher half of register to zero.
407 For i386, this is equivalent to a nop. */
408 tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
409 tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
410 break;
411 #ifdef TARGET_X86_64
412 case 2:
413 tcg_gen_addi_tl(cpu_regs[reg], cpu_regs[reg], val);
414 break;
415 #endif
416 }
417 }
418
419 static inline void gen_op_add_reg_T0(int size, int reg)
420 {
421 switch(size) {
422 case 0:
423 tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
424 tcg_gen_deposit_tl(cpu_regs[reg], cpu_regs[reg], cpu_tmp0, 0, 16);
425 break;
426 case 1:
427 tcg_gen_add_tl(cpu_tmp0, cpu_regs[reg], cpu_T[0]);
428 /* For x86_64, this sets the higher half of register to zero.
429 For i386, this is equivalent to a nop. */
430 tcg_gen_ext32u_tl(cpu_tmp0, cpu_tmp0);
431 tcg_gen_mov_tl(cpu_regs[reg], cpu_tmp0);
432 break;
433 #ifdef TARGET_X86_64
434 case 2:
435 tcg_gen_add_tl(cpu_regs[reg], cpu_regs[reg], cpu_T[0]);
436 break;
437 #endif
438 }
439 }
440
441 static inline void gen_op_set_cc_op(int32_t val)
442 {
443 tcg_gen_movi_i32(cpu_cc_op, val);
444 }
445
446 static inline void gen_op_addl_A0_reg_sN(int shift, int reg)
447 {
448 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
449 if (shift != 0)
450 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
451 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
452 /* For x86_64, this sets the higher half of register to zero.
453 For i386, this is equivalent to a nop. */
454 tcg_gen_ext32u_tl(cpu_A0, cpu_A0);
455 }
456
457 static inline void gen_op_movl_A0_seg(int reg)
458 {
459 tcg_gen_ld32u_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base) + REG_L_OFFSET);
460 }
461
462 static inline void gen_op_addl_A0_seg(DisasContext *s, int reg)
463 {
464 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base));
465 #ifdef TARGET_X86_64
466 if (CODE64(s)) {
467 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
468 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
469 } else {
470 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
471 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
472 }
473 #else
474 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
475 #endif
476 }
477
478 #ifdef TARGET_X86_64
479 static inline void gen_op_movq_A0_seg(int reg)
480 {
481 tcg_gen_ld_tl(cpu_A0, cpu_env, offsetof(CPUX86State, segs[reg].base));
482 }
483
484 static inline void gen_op_addq_A0_seg(int reg)
485 {
486 tcg_gen_ld_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, segs[reg].base));
487 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
488 }
489
490 static inline void gen_op_movq_A0_reg(int reg)
491 {
492 tcg_gen_mov_tl(cpu_A0, cpu_regs[reg]);
493 }
494
495 static inline void gen_op_addq_A0_reg_sN(int shift, int reg)
496 {
497 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[reg]);
498 if (shift != 0)
499 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, shift);
500 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
501 }
502 #endif
503
504 static inline void gen_op_lds_T0_A0(int idx)
505 {
506 int mem_index = (idx >> 2) - 1;
507 switch(idx & 3) {
508 case 0:
509 tcg_gen_qemu_ld8s(cpu_T[0], cpu_A0, mem_index);
510 break;
511 case 1:
512 tcg_gen_qemu_ld16s(cpu_T[0], cpu_A0, mem_index);
513 break;
514 default:
515 case 2:
516 tcg_gen_qemu_ld32s(cpu_T[0], cpu_A0, mem_index);
517 break;
518 }
519 }
520
521 static inline void gen_op_ld_v(int idx, TCGv t0, TCGv a0)
522 {
523 int mem_index = (idx >> 2) - 1;
524 switch(idx & 3) {
525 case 0:
526 tcg_gen_qemu_ld8u(t0, a0, mem_index);
527 break;
528 case 1:
529 tcg_gen_qemu_ld16u(t0, a0, mem_index);
530 break;
531 case 2:
532 tcg_gen_qemu_ld32u(t0, a0, mem_index);
533 break;
534 default:
535 case 3:
536 /* Should never happen on 32-bit targets. */
537 #ifdef TARGET_X86_64
538 tcg_gen_qemu_ld64(t0, a0, mem_index);
539 #endif
540 break;
541 }
542 }
543
544 /* XXX: always use ldu or lds */
545 static inline void gen_op_ld_T0_A0(int idx)
546 {
547 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
548 }
549
550 static inline void gen_op_ldu_T0_A0(int idx)
551 {
552 gen_op_ld_v(idx, cpu_T[0], cpu_A0);
553 }
554
555 static inline void gen_op_ld_T1_A0(int idx)
556 {
557 gen_op_ld_v(idx, cpu_T[1], cpu_A0);
558 }
559
560 static inline void gen_op_st_v(int idx, TCGv t0, TCGv a0)
561 {
562 int mem_index = (idx >> 2) - 1;
563 switch(idx & 3) {
564 case 0:
565 tcg_gen_qemu_st8(t0, a0, mem_index);
566 break;
567 case 1:
568 tcg_gen_qemu_st16(t0, a0, mem_index);
569 break;
570 case 2:
571 tcg_gen_qemu_st32(t0, a0, mem_index);
572 break;
573 default:
574 case 3:
575 /* Should never happen on 32-bit targets. */
576 #ifdef TARGET_X86_64
577 tcg_gen_qemu_st64(t0, a0, mem_index);
578 #endif
579 break;
580 }
581 }
582
583 static inline void gen_op_st_T0_A0(int idx)
584 {
585 gen_op_st_v(idx, cpu_T[0], cpu_A0);
586 }
587
588 static inline void gen_op_st_T1_A0(int idx)
589 {
590 gen_op_st_v(idx, cpu_T[1], cpu_A0);
591 }
592
593 static inline void gen_jmp_im(target_ulong pc)
594 {
595 tcg_gen_movi_tl(cpu_tmp0, pc);
596 tcg_gen_st_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State, eip));
597 }
598
599 static inline void gen_string_movl_A0_ESI(DisasContext *s)
600 {
601 int override;
602
603 override = s->override;
604 #ifdef TARGET_X86_64
605 if (s->aflag == 2) {
606 if (override >= 0) {
607 gen_op_movq_A0_seg(override);
608 gen_op_addq_A0_reg_sN(0, R_ESI);
609 } else {
610 gen_op_movq_A0_reg(R_ESI);
611 }
612 } else
613 #endif
614 if (s->aflag) {
615 /* 32 bit address */
616 if (s->addseg && override < 0)
617 override = R_DS;
618 if (override >= 0) {
619 gen_op_movl_A0_seg(override);
620 gen_op_addl_A0_reg_sN(0, R_ESI);
621 } else {
622 gen_op_movl_A0_reg(R_ESI);
623 }
624 } else {
625 /* 16 address, always override */
626 if (override < 0)
627 override = R_DS;
628 gen_op_movl_A0_reg(R_ESI);
629 gen_op_andl_A0_ffff();
630 gen_op_addl_A0_seg(s, override);
631 }
632 }
633
634 static inline void gen_string_movl_A0_EDI(DisasContext *s)
635 {
636 #ifdef TARGET_X86_64
637 if (s->aflag == 2) {
638 gen_op_movq_A0_reg(R_EDI);
639 } else
640 #endif
641 if (s->aflag) {
642 if (s->addseg) {
643 gen_op_movl_A0_seg(R_ES);
644 gen_op_addl_A0_reg_sN(0, R_EDI);
645 } else {
646 gen_op_movl_A0_reg(R_EDI);
647 }
648 } else {
649 gen_op_movl_A0_reg(R_EDI);
650 gen_op_andl_A0_ffff();
651 gen_op_addl_A0_seg(s, R_ES);
652 }
653 }
654
655 static inline void gen_op_movl_T0_Dshift(int ot)
656 {
657 tcg_gen_ld32s_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, df));
658 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], ot);
659 };
660
661 static void gen_extu(int ot, TCGv reg)
662 {
663 switch(ot) {
664 case OT_BYTE:
665 tcg_gen_ext8u_tl(reg, reg);
666 break;
667 case OT_WORD:
668 tcg_gen_ext16u_tl(reg, reg);
669 break;
670 case OT_LONG:
671 tcg_gen_ext32u_tl(reg, reg);
672 break;
673 default:
674 break;
675 }
676 }
677
678 static void gen_exts(int ot, TCGv reg)
679 {
680 switch(ot) {
681 case OT_BYTE:
682 tcg_gen_ext8s_tl(reg, reg);
683 break;
684 case OT_WORD:
685 tcg_gen_ext16s_tl(reg, reg);
686 break;
687 case OT_LONG:
688 tcg_gen_ext32s_tl(reg, reg);
689 break;
690 default:
691 break;
692 }
693 }
694
695 static inline void gen_op_jnz_ecx(int size, int label1)
696 {
697 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
698 gen_extu(size + 1, cpu_tmp0);
699 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, label1);
700 }
701
702 static inline void gen_op_jz_ecx(int size, int label1)
703 {
704 tcg_gen_mov_tl(cpu_tmp0, cpu_regs[R_ECX]);
705 gen_extu(size + 1, cpu_tmp0);
706 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
707 }
708
709 static void gen_helper_in_func(int ot, TCGv v, TCGv_i32 n)
710 {
711 switch (ot) {
712 case 0: gen_helper_inb(v, n); break;
713 case 1: gen_helper_inw(v, n); break;
714 case 2: gen_helper_inl(v, n); break;
715 }
716
717 }
718
719 static void gen_helper_out_func(int ot, TCGv_i32 v, TCGv_i32 n)
720 {
721 switch (ot) {
722 case 0: gen_helper_outb(v, n); break;
723 case 1: gen_helper_outw(v, n); break;
724 case 2: gen_helper_outl(v, n); break;
725 }
726
727 }
728
729 static void gen_check_io(DisasContext *s, int ot, target_ulong cur_eip,
730 uint32_t svm_flags)
731 {
732 int state_saved;
733 target_ulong next_eip;
734
735 state_saved = 0;
736 if (s->pe && (s->cpl > s->iopl || s->vm86)) {
737 if (s->cc_op != CC_OP_DYNAMIC)
738 gen_op_set_cc_op(s->cc_op);
739 gen_jmp_im(cur_eip);
740 state_saved = 1;
741 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
742 switch (ot) {
743 case 0:
744 gen_helper_check_iob(cpu_env, cpu_tmp2_i32);
745 break;
746 case 1:
747 gen_helper_check_iow(cpu_env, cpu_tmp2_i32);
748 break;
749 case 2:
750 gen_helper_check_iol(cpu_env, cpu_tmp2_i32);
751 break;
752 }
753 }
754 if(s->flags & HF_SVMI_MASK) {
755 if (!state_saved) {
756 if (s->cc_op != CC_OP_DYNAMIC)
757 gen_op_set_cc_op(s->cc_op);
758 gen_jmp_im(cur_eip);
759 }
760 svm_flags |= (1 << (4 + ot));
761 next_eip = s->pc - s->cs_base;
762 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
763 gen_helper_svm_check_io(cpu_env, cpu_tmp2_i32,
764 tcg_const_i32(svm_flags),
765 tcg_const_i32(next_eip - cur_eip));
766 }
767 }
768
769 static inline void gen_movs(DisasContext *s, int ot)
770 {
771 gen_string_movl_A0_ESI(s);
772 gen_op_ld_T0_A0(ot + s->mem_index);
773 gen_string_movl_A0_EDI(s);
774 gen_op_st_T0_A0(ot + s->mem_index);
775 gen_op_movl_T0_Dshift(ot);
776 gen_op_add_reg_T0(s->aflag, R_ESI);
777 gen_op_add_reg_T0(s->aflag, R_EDI);
778 }
779
780 static inline void gen_update_cc_op(DisasContext *s)
781 {
782 if (s->cc_op != CC_OP_DYNAMIC) {
783 gen_op_set_cc_op(s->cc_op);
784 s->cc_op = CC_OP_DYNAMIC;
785 }
786 }
787
788 static void gen_op_update1_cc(void)
789 {
790 tcg_gen_discard_tl(cpu_cc_src);
791 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
792 }
793
794 static void gen_op_update2_cc(void)
795 {
796 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
797 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
798 }
799
800 static inline void gen_op_cmpl_T0_T1_cc(void)
801 {
802 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
803 tcg_gen_sub_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
804 }
805
806 static inline void gen_op_testl_T0_T1_cc(void)
807 {
808 tcg_gen_discard_tl(cpu_cc_src);
809 tcg_gen_and_tl(cpu_cc_dst, cpu_T[0], cpu_T[1]);
810 }
811
812 static void gen_op_update_neg_cc(void)
813 {
814 tcg_gen_neg_tl(cpu_cc_src, cpu_T[0]);
815 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
816 }
817
818 /* compute eflags.C to reg */
819 static void gen_compute_eflags_c(TCGv reg)
820 {
821 gen_helper_cc_compute_c(cpu_tmp2_i32, cpu_env, cpu_cc_op);
822 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
823 }
824
825 /* compute all eflags to cc_src */
826 static void gen_compute_eflags(TCGv reg)
827 {
828 gen_helper_cc_compute_all(cpu_tmp2_i32, cpu_env, cpu_cc_op);
829 tcg_gen_extu_i32_tl(reg, cpu_tmp2_i32);
830 }
831
832 static inline void gen_setcc_slow_T0(DisasContext *s, int jcc_op)
833 {
834 if (s->cc_op != CC_OP_DYNAMIC)
835 gen_op_set_cc_op(s->cc_op);
836 switch(jcc_op) {
837 case JCC_O:
838 gen_compute_eflags(cpu_T[0]);
839 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 11);
840 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
841 break;
842 case JCC_B:
843 gen_compute_eflags_c(cpu_T[0]);
844 break;
845 case JCC_Z:
846 gen_compute_eflags(cpu_T[0]);
847 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 6);
848 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
849 break;
850 case JCC_BE:
851 gen_compute_eflags(cpu_tmp0);
852 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 6);
853 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
854 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
855 break;
856 case JCC_S:
857 gen_compute_eflags(cpu_T[0]);
858 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 7);
859 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
860 break;
861 case JCC_P:
862 gen_compute_eflags(cpu_T[0]);
863 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 2);
864 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
865 break;
866 case JCC_L:
867 gen_compute_eflags(cpu_tmp0);
868 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
869 tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 7); /* CC_S */
870 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
871 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
872 break;
873 default:
874 case JCC_LE:
875 gen_compute_eflags(cpu_tmp0);
876 tcg_gen_shri_tl(cpu_T[0], cpu_tmp0, 11); /* CC_O */
877 tcg_gen_shri_tl(cpu_tmp4, cpu_tmp0, 7); /* CC_S */
878 tcg_gen_shri_tl(cpu_tmp0, cpu_tmp0, 6); /* CC_Z */
879 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
880 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
881 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 1);
882 break;
883 }
884 }
885
886 /* return true if setcc_slow is not needed (WARNING: must be kept in
887 sync with gen_jcc1) */
888 static int is_fast_jcc_case(DisasContext *s, int b)
889 {
890 int jcc_op;
891 jcc_op = (b >> 1) & 7;
892 switch(s->cc_op) {
893 /* we optimize the cmp/jcc case */
894 case CC_OP_SUBB:
895 case CC_OP_SUBW:
896 case CC_OP_SUBL:
897 case CC_OP_SUBQ:
898 if (jcc_op == JCC_O || jcc_op == JCC_P)
899 goto slow_jcc;
900 break;
901
902 /* some jumps are easy to compute */
903 case CC_OP_ADDB:
904 case CC_OP_ADDW:
905 case CC_OP_ADDL:
906 case CC_OP_ADDQ:
907
908 case CC_OP_LOGICB:
909 case CC_OP_LOGICW:
910 case CC_OP_LOGICL:
911 case CC_OP_LOGICQ:
912
913 case CC_OP_INCB:
914 case CC_OP_INCW:
915 case CC_OP_INCL:
916 case CC_OP_INCQ:
917
918 case CC_OP_DECB:
919 case CC_OP_DECW:
920 case CC_OP_DECL:
921 case CC_OP_DECQ:
922
923 case CC_OP_SHLB:
924 case CC_OP_SHLW:
925 case CC_OP_SHLL:
926 case CC_OP_SHLQ:
927 if (jcc_op != JCC_Z && jcc_op != JCC_S)
928 goto slow_jcc;
929 break;
930 default:
931 slow_jcc:
932 return 0;
933 }
934 return 1;
935 }
936
937 /* generate a conditional jump to label 'l1' according to jump opcode
938 value 'b'. In the fast case, T0 is guaranted not to be used. */
939 static inline void gen_jcc1(DisasContext *s, int cc_op, int b, int l1)
940 {
941 int inv, jcc_op, size, cond;
942 TCGv t0;
943
944 inv = b & 1;
945 jcc_op = (b >> 1) & 7;
946
947 switch(cc_op) {
948 /* we optimize the cmp/jcc case */
949 case CC_OP_SUBB:
950 case CC_OP_SUBW:
951 case CC_OP_SUBL:
952 case CC_OP_SUBQ:
953
954 size = cc_op - CC_OP_SUBB;
955 switch(jcc_op) {
956 case JCC_Z:
957 fast_jcc_z:
958 switch(size) {
959 case 0:
960 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xff);
961 t0 = cpu_tmp0;
962 break;
963 case 1:
964 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffff);
965 t0 = cpu_tmp0;
966 break;
967 #ifdef TARGET_X86_64
968 case 2:
969 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0xffffffff);
970 t0 = cpu_tmp0;
971 break;
972 #endif
973 default:
974 t0 = cpu_cc_dst;
975 break;
976 }
977 tcg_gen_brcondi_tl(inv ? TCG_COND_NE : TCG_COND_EQ, t0, 0, l1);
978 break;
979 case JCC_S:
980 fast_jcc_s:
981 switch(size) {
982 case 0:
983 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80);
984 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
985 0, l1);
986 break;
987 case 1:
988 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x8000);
989 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
990 0, l1);
991 break;
992 #ifdef TARGET_X86_64
993 case 2:
994 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_dst, 0x80000000);
995 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE, cpu_tmp0,
996 0, l1);
997 break;
998 #endif
999 default:
1000 tcg_gen_brcondi_tl(inv ? TCG_COND_GE : TCG_COND_LT, cpu_cc_dst,
1001 0, l1);
1002 break;
1003 }
1004 break;
1005
1006 case JCC_B:
1007 cond = inv ? TCG_COND_GEU : TCG_COND_LTU;
1008 goto fast_jcc_b;
1009 case JCC_BE:
1010 cond = inv ? TCG_COND_GTU : TCG_COND_LEU;
1011 fast_jcc_b:
1012 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1013 switch(size) {
1014 case 0:
1015 t0 = cpu_tmp0;
1016 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xff);
1017 tcg_gen_andi_tl(t0, cpu_cc_src, 0xff);
1018 break;
1019 case 1:
1020 t0 = cpu_tmp0;
1021 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffff);
1022 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffff);
1023 break;
1024 #ifdef TARGET_X86_64
1025 case 2:
1026 t0 = cpu_tmp0;
1027 tcg_gen_andi_tl(cpu_tmp4, cpu_tmp4, 0xffffffff);
1028 tcg_gen_andi_tl(t0, cpu_cc_src, 0xffffffff);
1029 break;
1030 #endif
1031 default:
1032 t0 = cpu_cc_src;
1033 break;
1034 }
1035 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1036 break;
1037
1038 case JCC_L:
1039 cond = inv ? TCG_COND_GE : TCG_COND_LT;
1040 goto fast_jcc_l;
1041 case JCC_LE:
1042 cond = inv ? TCG_COND_GT : TCG_COND_LE;
1043 fast_jcc_l:
1044 tcg_gen_add_tl(cpu_tmp4, cpu_cc_dst, cpu_cc_src);
1045 switch(size) {
1046 case 0:
1047 t0 = cpu_tmp0;
1048 tcg_gen_ext8s_tl(cpu_tmp4, cpu_tmp4);
1049 tcg_gen_ext8s_tl(t0, cpu_cc_src);
1050 break;
1051 case 1:
1052 t0 = cpu_tmp0;
1053 tcg_gen_ext16s_tl(cpu_tmp4, cpu_tmp4);
1054 tcg_gen_ext16s_tl(t0, cpu_cc_src);
1055 break;
1056 #ifdef TARGET_X86_64
1057 case 2:
1058 t0 = cpu_tmp0;
1059 tcg_gen_ext32s_tl(cpu_tmp4, cpu_tmp4);
1060 tcg_gen_ext32s_tl(t0, cpu_cc_src);
1061 break;
1062 #endif
1063 default:
1064 t0 = cpu_cc_src;
1065 break;
1066 }
1067 tcg_gen_brcond_tl(cond, cpu_tmp4, t0, l1);
1068 break;
1069
1070 default:
1071 goto slow_jcc;
1072 }
1073 break;
1074
1075 /* some jumps are easy to compute */
1076 case CC_OP_ADDB:
1077 case CC_OP_ADDW:
1078 case CC_OP_ADDL:
1079 case CC_OP_ADDQ:
1080
1081 case CC_OP_ADCB:
1082 case CC_OP_ADCW:
1083 case CC_OP_ADCL:
1084 case CC_OP_ADCQ:
1085
1086 case CC_OP_SBBB:
1087 case CC_OP_SBBW:
1088 case CC_OP_SBBL:
1089 case CC_OP_SBBQ:
1090
1091 case CC_OP_LOGICB:
1092 case CC_OP_LOGICW:
1093 case CC_OP_LOGICL:
1094 case CC_OP_LOGICQ:
1095
1096 case CC_OP_INCB:
1097 case CC_OP_INCW:
1098 case CC_OP_INCL:
1099 case CC_OP_INCQ:
1100
1101 case CC_OP_DECB:
1102 case CC_OP_DECW:
1103 case CC_OP_DECL:
1104 case CC_OP_DECQ:
1105
1106 case CC_OP_SHLB:
1107 case CC_OP_SHLW:
1108 case CC_OP_SHLL:
1109 case CC_OP_SHLQ:
1110
1111 case CC_OP_SARB:
1112 case CC_OP_SARW:
1113 case CC_OP_SARL:
1114 case CC_OP_SARQ:
1115 switch(jcc_op) {
1116 case JCC_Z:
1117 size = (cc_op - CC_OP_ADDB) & 3;
1118 goto fast_jcc_z;
1119 case JCC_S:
1120 size = (cc_op - CC_OP_ADDB) & 3;
1121 goto fast_jcc_s;
1122 default:
1123 goto slow_jcc;
1124 }
1125 break;
1126 default:
1127 slow_jcc:
1128 gen_setcc_slow_T0(s, jcc_op);
1129 tcg_gen_brcondi_tl(inv ? TCG_COND_EQ : TCG_COND_NE,
1130 cpu_T[0], 0, l1);
1131 break;
1132 }
1133 }
1134
1135 /* XXX: does not work with gdbstub "ice" single step - not a
1136 serious problem */
1137 static int gen_jz_ecx_string(DisasContext *s, target_ulong next_eip)
1138 {
1139 int l1, l2;
1140
1141 l1 = gen_new_label();
1142 l2 = gen_new_label();
1143 gen_op_jnz_ecx(s->aflag, l1);
1144 gen_set_label(l2);
1145 gen_jmp_tb(s, next_eip, 1);
1146 gen_set_label(l1);
1147 return l2;
1148 }
1149
1150 static inline void gen_stos(DisasContext *s, int ot)
1151 {
1152 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1153 gen_string_movl_A0_EDI(s);
1154 gen_op_st_T0_A0(ot + s->mem_index);
1155 gen_op_movl_T0_Dshift(ot);
1156 gen_op_add_reg_T0(s->aflag, R_EDI);
1157 }
1158
1159 static inline void gen_lods(DisasContext *s, int ot)
1160 {
1161 gen_string_movl_A0_ESI(s);
1162 gen_op_ld_T0_A0(ot + s->mem_index);
1163 gen_op_mov_reg_T0(ot, R_EAX);
1164 gen_op_movl_T0_Dshift(ot);
1165 gen_op_add_reg_T0(s->aflag, R_ESI);
1166 }
1167
1168 static inline void gen_scas(DisasContext *s, int ot)
1169 {
1170 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
1171 gen_string_movl_A0_EDI(s);
1172 gen_op_ld_T1_A0(ot + s->mem_index);
1173 gen_op_cmpl_T0_T1_cc();
1174 gen_op_movl_T0_Dshift(ot);
1175 gen_op_add_reg_T0(s->aflag, R_EDI);
1176 }
1177
1178 static inline void gen_cmps(DisasContext *s, int ot)
1179 {
1180 gen_string_movl_A0_ESI(s);
1181 gen_op_ld_T0_A0(ot + s->mem_index);
1182 gen_string_movl_A0_EDI(s);
1183 gen_op_ld_T1_A0(ot + s->mem_index);
1184 gen_op_cmpl_T0_T1_cc();
1185 gen_op_movl_T0_Dshift(ot);
1186 gen_op_add_reg_T0(s->aflag, R_ESI);
1187 gen_op_add_reg_T0(s->aflag, R_EDI);
1188 }
1189
1190 static inline void gen_ins(DisasContext *s, int ot)
1191 {
1192 if (use_icount)
1193 gen_io_start();
1194 gen_string_movl_A0_EDI(s);
1195 /* Note: we must do this dummy write first to be restartable in
1196 case of page fault. */
1197 gen_op_movl_T0_0();
1198 gen_op_st_T0_A0(ot + s->mem_index);
1199 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1200 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1201 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1202 gen_helper_in_func(ot, cpu_T[0], cpu_tmp2_i32);
1203 gen_op_st_T0_A0(ot + s->mem_index);
1204 gen_op_movl_T0_Dshift(ot);
1205 gen_op_add_reg_T0(s->aflag, R_EDI);
1206 if (use_icount)
1207 gen_io_end();
1208 }
1209
1210 static inline void gen_outs(DisasContext *s, int ot)
1211 {
1212 if (use_icount)
1213 gen_io_start();
1214 gen_string_movl_A0_ESI(s);
1215 gen_op_ld_T0_A0(ot + s->mem_index);
1216
1217 gen_op_mov_TN_reg(OT_WORD, 1, R_EDX);
1218 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[1]);
1219 tcg_gen_andi_i32(cpu_tmp2_i32, cpu_tmp2_i32, 0xffff);
1220 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[0]);
1221 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
1222
1223 gen_op_movl_T0_Dshift(ot);
1224 gen_op_add_reg_T0(s->aflag, R_ESI);
1225 if (use_icount)
1226 gen_io_end();
1227 }
1228
1229 /* same method as Valgrind : we generate jumps to current or next
1230 instruction */
1231 #define GEN_REPZ(op) \
1232 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1233 target_ulong cur_eip, target_ulong next_eip) \
1234 { \
1235 int l2;\
1236 gen_update_cc_op(s); \
1237 l2 = gen_jz_ecx_string(s, next_eip); \
1238 gen_ ## op(s, ot); \
1239 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1240 /* a loop would cause two single step exceptions if ECX = 1 \
1241 before rep string_insn */ \
1242 if (!s->jmp_opt) \
1243 gen_op_jz_ecx(s->aflag, l2); \
1244 gen_jmp(s, cur_eip); \
1245 }
1246
1247 #define GEN_REPZ2(op) \
1248 static inline void gen_repz_ ## op(DisasContext *s, int ot, \
1249 target_ulong cur_eip, \
1250 target_ulong next_eip, \
1251 int nz) \
1252 { \
1253 int l2;\
1254 gen_update_cc_op(s); \
1255 l2 = gen_jz_ecx_string(s, next_eip); \
1256 gen_ ## op(s, ot); \
1257 gen_op_add_reg_im(s->aflag, R_ECX, -1); \
1258 gen_op_set_cc_op(CC_OP_SUBB + ot); \
1259 gen_jcc1(s, CC_OP_SUBB + ot, (JCC_Z << 1) | (nz ^ 1), l2); \
1260 if (!s->jmp_opt) \
1261 gen_op_jz_ecx(s->aflag, l2); \
1262 gen_jmp(s, cur_eip); \
1263 }
1264
1265 GEN_REPZ(movs)
1266 GEN_REPZ(stos)
1267 GEN_REPZ(lods)
1268 GEN_REPZ(ins)
1269 GEN_REPZ(outs)
1270 GEN_REPZ2(scas)
1271 GEN_REPZ2(cmps)
1272
1273 static void gen_helper_fp_arith_ST0_FT0(int op)
1274 {
1275 switch (op) {
1276 case 0:
1277 gen_helper_fadd_ST0_FT0(cpu_env);
1278 break;
1279 case 1:
1280 gen_helper_fmul_ST0_FT0(cpu_env);
1281 break;
1282 case 2:
1283 gen_helper_fcom_ST0_FT0(cpu_env);
1284 break;
1285 case 3:
1286 gen_helper_fcom_ST0_FT0(cpu_env);
1287 break;
1288 case 4:
1289 gen_helper_fsub_ST0_FT0(cpu_env);
1290 break;
1291 case 5:
1292 gen_helper_fsubr_ST0_FT0(cpu_env);
1293 break;
1294 case 6:
1295 gen_helper_fdiv_ST0_FT0(cpu_env);
1296 break;
1297 case 7:
1298 gen_helper_fdivr_ST0_FT0(cpu_env);
1299 break;
1300 }
1301 }
1302
1303 /* NOTE the exception in "r" op ordering */
1304 static void gen_helper_fp_arith_STN_ST0(int op, int opreg)
1305 {
1306 TCGv_i32 tmp = tcg_const_i32(opreg);
1307 switch (op) {
1308 case 0:
1309 gen_helper_fadd_STN_ST0(cpu_env, tmp);
1310 break;
1311 case 1:
1312 gen_helper_fmul_STN_ST0(cpu_env, tmp);
1313 break;
1314 case 4:
1315 gen_helper_fsubr_STN_ST0(cpu_env, tmp);
1316 break;
1317 case 5:
1318 gen_helper_fsub_STN_ST0(cpu_env, tmp);
1319 break;
1320 case 6:
1321 gen_helper_fdivr_STN_ST0(cpu_env, tmp);
1322 break;
1323 case 7:
1324 gen_helper_fdiv_STN_ST0(cpu_env, tmp);
1325 break;
1326 }
1327 }
1328
1329 /* if d == OR_TMP0, it means memory operand (address in A0) */
1330 static void gen_op(DisasContext *s1, int op, int ot, int d)
1331 {
1332 if (d != OR_TMP0) {
1333 gen_op_mov_TN_reg(ot, 0, d);
1334 } else {
1335 gen_op_ld_T0_A0(ot + s1->mem_index);
1336 }
1337 switch(op) {
1338 case OP_ADCL:
1339 if (s1->cc_op != CC_OP_DYNAMIC)
1340 gen_op_set_cc_op(s1->cc_op);
1341 gen_compute_eflags_c(cpu_tmp4);
1342 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1343 tcg_gen_add_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1344 if (d != OR_TMP0)
1345 gen_op_mov_reg_T0(ot, d);
1346 else
1347 gen_op_st_T0_A0(ot + s1->mem_index);
1348 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1349 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1350 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1351 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1352 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_ADDB + ot);
1353 s1->cc_op = CC_OP_DYNAMIC;
1354 break;
1355 case OP_SBBL:
1356 if (s1->cc_op != CC_OP_DYNAMIC)
1357 gen_op_set_cc_op(s1->cc_op);
1358 gen_compute_eflags_c(cpu_tmp4);
1359 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1360 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_tmp4);
1361 if (d != OR_TMP0)
1362 gen_op_mov_reg_T0(ot, d);
1363 else
1364 gen_op_st_T0_A0(ot + s1->mem_index);
1365 tcg_gen_mov_tl(cpu_cc_src, cpu_T[1]);
1366 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1367 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp4);
1368 tcg_gen_shli_i32(cpu_tmp2_i32, cpu_tmp2_i32, 2);
1369 tcg_gen_addi_i32(cpu_cc_op, cpu_tmp2_i32, CC_OP_SUBB + ot);
1370 s1->cc_op = CC_OP_DYNAMIC;
1371 break;
1372 case OP_ADDL:
1373 gen_op_addl_T0_T1();
1374 if (d != OR_TMP0)
1375 gen_op_mov_reg_T0(ot, d);
1376 else
1377 gen_op_st_T0_A0(ot + s1->mem_index);
1378 gen_op_update2_cc();
1379 s1->cc_op = CC_OP_ADDB + ot;
1380 break;
1381 case OP_SUBL:
1382 tcg_gen_sub_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1383 if (d != OR_TMP0)
1384 gen_op_mov_reg_T0(ot, d);
1385 else
1386 gen_op_st_T0_A0(ot + s1->mem_index);
1387 gen_op_update2_cc();
1388 s1->cc_op = CC_OP_SUBB + ot;
1389 break;
1390 default:
1391 case OP_ANDL:
1392 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1393 if (d != OR_TMP0)
1394 gen_op_mov_reg_T0(ot, d);
1395 else
1396 gen_op_st_T0_A0(ot + s1->mem_index);
1397 gen_op_update1_cc();
1398 s1->cc_op = CC_OP_LOGICB + ot;
1399 break;
1400 case OP_ORL:
1401 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1402 if (d != OR_TMP0)
1403 gen_op_mov_reg_T0(ot, d);
1404 else
1405 gen_op_st_T0_A0(ot + s1->mem_index);
1406 gen_op_update1_cc();
1407 s1->cc_op = CC_OP_LOGICB + ot;
1408 break;
1409 case OP_XORL:
1410 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
1411 if (d != OR_TMP0)
1412 gen_op_mov_reg_T0(ot, d);
1413 else
1414 gen_op_st_T0_A0(ot + s1->mem_index);
1415 gen_op_update1_cc();
1416 s1->cc_op = CC_OP_LOGICB + ot;
1417 break;
1418 case OP_CMPL:
1419 gen_op_cmpl_T0_T1_cc();
1420 s1->cc_op = CC_OP_SUBB + ot;
1421 break;
1422 }
1423 }
1424
1425 /* if d == OR_TMP0, it means memory operand (address in A0) */
1426 static void gen_inc(DisasContext *s1, int ot, int d, int c)
1427 {
1428 if (d != OR_TMP0)
1429 gen_op_mov_TN_reg(ot, 0, d);
1430 else
1431 gen_op_ld_T0_A0(ot + s1->mem_index);
1432 if (s1->cc_op != CC_OP_DYNAMIC)
1433 gen_op_set_cc_op(s1->cc_op);
1434 if (c > 0) {
1435 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], 1);
1436 s1->cc_op = CC_OP_INCB + ot;
1437 } else {
1438 tcg_gen_addi_tl(cpu_T[0], cpu_T[0], -1);
1439 s1->cc_op = CC_OP_DECB + ot;
1440 }
1441 if (d != OR_TMP0)
1442 gen_op_mov_reg_T0(ot, d);
1443 else
1444 gen_op_st_T0_A0(ot + s1->mem_index);
1445 gen_compute_eflags_c(cpu_cc_src);
1446 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1447 }
1448
1449 static void gen_shift_rm_T1(DisasContext *s, int ot, int op1,
1450 int is_right, int is_arith)
1451 {
1452 target_ulong mask;
1453 int shift_label;
1454 TCGv t0, t1, t2;
1455
1456 if (ot == OT_QUAD) {
1457 mask = 0x3f;
1458 } else {
1459 mask = 0x1f;
1460 }
1461
1462 /* load */
1463 if (op1 == OR_TMP0) {
1464 gen_op_ld_T0_A0(ot + s->mem_index);
1465 } else {
1466 gen_op_mov_TN_reg(ot, 0, op1);
1467 }
1468
1469 t0 = tcg_temp_local_new();
1470 t1 = tcg_temp_local_new();
1471 t2 = tcg_temp_local_new();
1472
1473 tcg_gen_andi_tl(t2, cpu_T[1], mask);
1474
1475 if (is_right) {
1476 if (is_arith) {
1477 gen_exts(ot, cpu_T[0]);
1478 tcg_gen_mov_tl(t0, cpu_T[0]);
1479 tcg_gen_sar_tl(cpu_T[0], cpu_T[0], t2);
1480 } else {
1481 gen_extu(ot, cpu_T[0]);
1482 tcg_gen_mov_tl(t0, cpu_T[0]);
1483 tcg_gen_shr_tl(cpu_T[0], cpu_T[0], t2);
1484 }
1485 } else {
1486 tcg_gen_mov_tl(t0, cpu_T[0]);
1487 tcg_gen_shl_tl(cpu_T[0], cpu_T[0], t2);
1488 }
1489
1490 /* store */
1491 if (op1 == OR_TMP0) {
1492 gen_op_st_T0_A0(ot + s->mem_index);
1493 } else {
1494 gen_op_mov_reg_T0(ot, op1);
1495 }
1496
1497 /* update eflags if non zero shift */
1498 if (s->cc_op != CC_OP_DYNAMIC) {
1499 gen_op_set_cc_op(s->cc_op);
1500 }
1501
1502 tcg_gen_mov_tl(t1, cpu_T[0]);
1503
1504 shift_label = gen_new_label();
1505 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, shift_label);
1506
1507 tcg_gen_addi_tl(t2, t2, -1);
1508 tcg_gen_mov_tl(cpu_cc_dst, t1);
1509
1510 if (is_right) {
1511 if (is_arith) {
1512 tcg_gen_sar_tl(cpu_cc_src, t0, t2);
1513 } else {
1514 tcg_gen_shr_tl(cpu_cc_src, t0, t2);
1515 }
1516 } else {
1517 tcg_gen_shl_tl(cpu_cc_src, t0, t2);
1518 }
1519
1520 if (is_right) {
1521 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1522 } else {
1523 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1524 }
1525
1526 gen_set_label(shift_label);
1527 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1528
1529 tcg_temp_free(t0);
1530 tcg_temp_free(t1);
1531 tcg_temp_free(t2);
1532 }
1533
1534 static void gen_shift_rm_im(DisasContext *s, int ot, int op1, int op2,
1535 int is_right, int is_arith)
1536 {
1537 int mask;
1538
1539 if (ot == OT_QUAD)
1540 mask = 0x3f;
1541 else
1542 mask = 0x1f;
1543
1544 /* load */
1545 if (op1 == OR_TMP0)
1546 gen_op_ld_T0_A0(ot + s->mem_index);
1547 else
1548 gen_op_mov_TN_reg(ot, 0, op1);
1549
1550 op2 &= mask;
1551 if (op2 != 0) {
1552 if (is_right) {
1553 if (is_arith) {
1554 gen_exts(ot, cpu_T[0]);
1555 tcg_gen_sari_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1556 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], op2);
1557 } else {
1558 gen_extu(ot, cpu_T[0]);
1559 tcg_gen_shri_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1560 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], op2);
1561 }
1562 } else {
1563 tcg_gen_shli_tl(cpu_tmp4, cpu_T[0], op2 - 1);
1564 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], op2);
1565 }
1566 }
1567
1568 /* store */
1569 if (op1 == OR_TMP0)
1570 gen_op_st_T0_A0(ot + s->mem_index);
1571 else
1572 gen_op_mov_reg_T0(ot, op1);
1573
1574 /* update eflags if non zero shift */
1575 if (op2 != 0) {
1576 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
1577 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
1578 if (is_right)
1579 s->cc_op = CC_OP_SARB + ot;
1580 else
1581 s->cc_op = CC_OP_SHLB + ot;
1582 }
1583 }
1584
1585 static inline void tcg_gen_lshift(TCGv ret, TCGv arg1, target_long arg2)
1586 {
1587 if (arg2 >= 0)
1588 tcg_gen_shli_tl(ret, arg1, arg2);
1589 else
1590 tcg_gen_shri_tl(ret, arg1, -arg2);
1591 }
1592
1593 static void gen_rot_rm_T1(DisasContext *s, int ot, int op1,
1594 int is_right)
1595 {
1596 target_ulong mask;
1597 int label1, label2, data_bits;
1598 TCGv t0, t1, t2, a0;
1599
1600 /* XXX: inefficient, but we must use local temps */
1601 t0 = tcg_temp_local_new();
1602 t1 = tcg_temp_local_new();
1603 t2 = tcg_temp_local_new();
1604 a0 = tcg_temp_local_new();
1605
1606 if (ot == OT_QUAD)
1607 mask = 0x3f;
1608 else
1609 mask = 0x1f;
1610
1611 /* load */
1612 if (op1 == OR_TMP0) {
1613 tcg_gen_mov_tl(a0, cpu_A0);
1614 gen_op_ld_v(ot + s->mem_index, t0, a0);
1615 } else {
1616 gen_op_mov_v_reg(ot, t0, op1);
1617 }
1618
1619 tcg_gen_mov_tl(t1, cpu_T[1]);
1620
1621 tcg_gen_andi_tl(t1, t1, mask);
1622
1623 /* Must test zero case to avoid using undefined behaviour in TCG
1624 shifts. */
1625 label1 = gen_new_label();
1626 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label1);
1627
1628 if (ot <= OT_WORD)
1629 tcg_gen_andi_tl(cpu_tmp0, t1, (1 << (3 + ot)) - 1);
1630 else
1631 tcg_gen_mov_tl(cpu_tmp0, t1);
1632
1633 gen_extu(ot, t0);
1634 tcg_gen_mov_tl(t2, t0);
1635
1636 data_bits = 8 << ot;
1637 /* XXX: rely on behaviour of shifts when operand 2 overflows (XXX:
1638 fix TCG definition) */
1639 if (is_right) {
1640 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp0);
1641 tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
1642 tcg_gen_shl_tl(t0, t0, cpu_tmp0);
1643 } else {
1644 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp0);
1645 tcg_gen_subfi_tl(cpu_tmp0, data_bits, cpu_tmp0);
1646 tcg_gen_shr_tl(t0, t0, cpu_tmp0);
1647 }
1648 tcg_gen_or_tl(t0, t0, cpu_tmp4);
1649
1650 gen_set_label(label1);
1651 /* store */
1652 if (op1 == OR_TMP0) {
1653 gen_op_st_v(ot + s->mem_index, t0, a0);
1654 } else {
1655 gen_op_mov_reg_v(ot, op1, t0);
1656 }
1657
1658 /* update eflags */
1659 if (s->cc_op != CC_OP_DYNAMIC)
1660 gen_op_set_cc_op(s->cc_op);
1661
1662 label2 = gen_new_label();
1663 tcg_gen_brcondi_tl(TCG_COND_EQ, t1, 0, label2);
1664
1665 gen_compute_eflags(cpu_cc_src);
1666 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1667 tcg_gen_xor_tl(cpu_tmp0, t2, t0);
1668 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1669 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1670 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1671 if (is_right) {
1672 tcg_gen_shri_tl(t0, t0, data_bits - 1);
1673 }
1674 tcg_gen_andi_tl(t0, t0, CC_C);
1675 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1676
1677 tcg_gen_discard_tl(cpu_cc_dst);
1678 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1679
1680 gen_set_label(label2);
1681 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1682
1683 tcg_temp_free(t0);
1684 tcg_temp_free(t1);
1685 tcg_temp_free(t2);
1686 tcg_temp_free(a0);
1687 }
1688
1689 static void gen_rot_rm_im(DisasContext *s, int ot, int op1, int op2,
1690 int is_right)
1691 {
1692 int mask;
1693 int data_bits;
1694 TCGv t0, t1, a0;
1695
1696 /* XXX: inefficient, but we must use local temps */
1697 t0 = tcg_temp_local_new();
1698 t1 = tcg_temp_local_new();
1699 a0 = tcg_temp_local_new();
1700
1701 if (ot == OT_QUAD)
1702 mask = 0x3f;
1703 else
1704 mask = 0x1f;
1705
1706 /* load */
1707 if (op1 == OR_TMP0) {
1708 tcg_gen_mov_tl(a0, cpu_A0);
1709 gen_op_ld_v(ot + s->mem_index, t0, a0);
1710 } else {
1711 gen_op_mov_v_reg(ot, t0, op1);
1712 }
1713
1714 gen_extu(ot, t0);
1715 tcg_gen_mov_tl(t1, t0);
1716
1717 op2 &= mask;
1718 data_bits = 8 << ot;
1719 if (op2 != 0) {
1720 int shift = op2 & ((1 << (3 + ot)) - 1);
1721 if (is_right) {
1722 tcg_gen_shri_tl(cpu_tmp4, t0, shift);
1723 tcg_gen_shli_tl(t0, t0, data_bits - shift);
1724 }
1725 else {
1726 tcg_gen_shli_tl(cpu_tmp4, t0, shift);
1727 tcg_gen_shri_tl(t0, t0, data_bits - shift);
1728 }
1729 tcg_gen_or_tl(t0, t0, cpu_tmp4);
1730 }
1731
1732 /* store */
1733 if (op1 == OR_TMP0) {
1734 gen_op_st_v(ot + s->mem_index, t0, a0);
1735 } else {
1736 gen_op_mov_reg_v(ot, op1, t0);
1737 }
1738
1739 if (op2 != 0) {
1740 /* update eflags */
1741 if (s->cc_op != CC_OP_DYNAMIC)
1742 gen_op_set_cc_op(s->cc_op);
1743
1744 gen_compute_eflags(cpu_cc_src);
1745 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~(CC_O | CC_C));
1746 tcg_gen_xor_tl(cpu_tmp0, t1, t0);
1747 tcg_gen_lshift(cpu_tmp0, cpu_tmp0, 11 - (data_bits - 1));
1748 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_O);
1749 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_tmp0);
1750 if (is_right) {
1751 tcg_gen_shri_tl(t0, t0, data_bits - 1);
1752 }
1753 tcg_gen_andi_tl(t0, t0, CC_C);
1754 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t0);
1755
1756 tcg_gen_discard_tl(cpu_cc_dst);
1757 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1758 s->cc_op = CC_OP_EFLAGS;
1759 }
1760
1761 tcg_temp_free(t0);
1762 tcg_temp_free(t1);
1763 tcg_temp_free(a0);
1764 }
1765
1766 /* XXX: add faster immediate = 1 case */
1767 static void gen_rotc_rm_T1(DisasContext *s, int ot, int op1,
1768 int is_right)
1769 {
1770 int label1;
1771
1772 if (s->cc_op != CC_OP_DYNAMIC)
1773 gen_op_set_cc_op(s->cc_op);
1774
1775 /* load */
1776 if (op1 == OR_TMP0)
1777 gen_op_ld_T0_A0(ot + s->mem_index);
1778 else
1779 gen_op_mov_TN_reg(ot, 0, op1);
1780
1781 if (is_right) {
1782 switch (ot) {
1783 case 0:
1784 gen_helper_rcrb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1785 break;
1786 case 1:
1787 gen_helper_rcrw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1788 break;
1789 case 2:
1790 gen_helper_rcrl(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1791 break;
1792 #ifdef TARGET_X86_64
1793 case 3:
1794 gen_helper_rcrq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1795 break;
1796 #endif
1797 }
1798 } else {
1799 switch (ot) {
1800 case 0:
1801 gen_helper_rclb(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1802 break;
1803 case 1:
1804 gen_helper_rclw(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1805 break;
1806 case 2:
1807 gen_helper_rcll(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1808 break;
1809 #ifdef TARGET_X86_64
1810 case 3:
1811 gen_helper_rclq(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
1812 break;
1813 #endif
1814 }
1815 }
1816 /* store */
1817 if (op1 == OR_TMP0)
1818 gen_op_st_T0_A0(ot + s->mem_index);
1819 else
1820 gen_op_mov_reg_T0(ot, op1);
1821
1822 /* update eflags */
1823 label1 = gen_new_label();
1824 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_cc_tmp, -1, label1);
1825
1826 tcg_gen_mov_tl(cpu_cc_src, cpu_cc_tmp);
1827 tcg_gen_discard_tl(cpu_cc_dst);
1828 tcg_gen_movi_i32(cpu_cc_op, CC_OP_EFLAGS);
1829
1830 gen_set_label(label1);
1831 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1832 }
1833
1834 /* XXX: add faster immediate case */
1835 static void gen_shiftd_rm_T1_T3(DisasContext *s, int ot, int op1,
1836 int is_right)
1837 {
1838 int label1, label2, data_bits;
1839 target_ulong mask;
1840 TCGv t0, t1, t2, a0;
1841
1842 t0 = tcg_temp_local_new();
1843 t1 = tcg_temp_local_new();
1844 t2 = tcg_temp_local_new();
1845 a0 = tcg_temp_local_new();
1846
1847 if (ot == OT_QUAD)
1848 mask = 0x3f;
1849 else
1850 mask = 0x1f;
1851
1852 /* load */
1853 if (op1 == OR_TMP0) {
1854 tcg_gen_mov_tl(a0, cpu_A0);
1855 gen_op_ld_v(ot + s->mem_index, t0, a0);
1856 } else {
1857 gen_op_mov_v_reg(ot, t0, op1);
1858 }
1859
1860 tcg_gen_andi_tl(cpu_T3, cpu_T3, mask);
1861
1862 tcg_gen_mov_tl(t1, cpu_T[1]);
1863 tcg_gen_mov_tl(t2, cpu_T3);
1864
1865 /* Must test zero case to avoid using undefined behaviour in TCG
1866 shifts. */
1867 label1 = gen_new_label();
1868 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
1869
1870 tcg_gen_addi_tl(cpu_tmp5, t2, -1);
1871 if (ot == OT_WORD) {
1872 /* Note: we implement the Intel behaviour for shift count > 16 */
1873 if (is_right) {
1874 tcg_gen_andi_tl(t0, t0, 0xffff);
1875 tcg_gen_shli_tl(cpu_tmp0, t1, 16);
1876 tcg_gen_or_tl(t0, t0, cpu_tmp0);
1877 tcg_gen_ext32u_tl(t0, t0);
1878
1879 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1880
1881 /* only needed if count > 16, but a test would complicate */
1882 tcg_gen_subfi_tl(cpu_tmp5, 32, t2);
1883 tcg_gen_shl_tl(cpu_tmp0, t0, cpu_tmp5);
1884
1885 tcg_gen_shr_tl(t0, t0, t2);
1886
1887 tcg_gen_or_tl(t0, t0, cpu_tmp0);
1888 } else {
1889 /* XXX: not optimal */
1890 tcg_gen_andi_tl(t0, t0, 0xffff);
1891 tcg_gen_shli_tl(t1, t1, 16);
1892 tcg_gen_or_tl(t1, t1, t0);
1893 tcg_gen_ext32u_tl(t1, t1);
1894
1895 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1896 tcg_gen_subfi_tl(cpu_tmp0, 32, cpu_tmp5);
1897 tcg_gen_shr_tl(cpu_tmp5, t1, cpu_tmp0);
1898 tcg_gen_or_tl(cpu_tmp4, cpu_tmp4, cpu_tmp5);
1899
1900 tcg_gen_shl_tl(t0, t0, t2);
1901 tcg_gen_subfi_tl(cpu_tmp5, 32, t2);
1902 tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1903 tcg_gen_or_tl(t0, t0, t1);
1904 }
1905 } else {
1906 data_bits = 8 << ot;
1907 if (is_right) {
1908 if (ot == OT_LONG)
1909 tcg_gen_ext32u_tl(t0, t0);
1910
1911 tcg_gen_shr_tl(cpu_tmp4, t0, cpu_tmp5);
1912
1913 tcg_gen_shr_tl(t0, t0, t2);
1914 tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2);
1915 tcg_gen_shl_tl(t1, t1, cpu_tmp5);
1916 tcg_gen_or_tl(t0, t0, t1);
1917
1918 } else {
1919 if (ot == OT_LONG)
1920 tcg_gen_ext32u_tl(t1, t1);
1921
1922 tcg_gen_shl_tl(cpu_tmp4, t0, cpu_tmp5);
1923
1924 tcg_gen_shl_tl(t0, t0, t2);
1925 tcg_gen_subfi_tl(cpu_tmp5, data_bits, t2);
1926 tcg_gen_shr_tl(t1, t1, cpu_tmp5);
1927 tcg_gen_or_tl(t0, t0, t1);
1928 }
1929 }
1930 tcg_gen_mov_tl(t1, cpu_tmp4);
1931
1932 gen_set_label(label1);
1933 /* store */
1934 if (op1 == OR_TMP0) {
1935 gen_op_st_v(ot + s->mem_index, t0, a0);
1936 } else {
1937 gen_op_mov_reg_v(ot, op1, t0);
1938 }
1939
1940 /* update eflags */
1941 if (s->cc_op != CC_OP_DYNAMIC)
1942 gen_op_set_cc_op(s->cc_op);
1943
1944 label2 = gen_new_label();
1945 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label2);
1946
1947 tcg_gen_mov_tl(cpu_cc_src, t1);
1948 tcg_gen_mov_tl(cpu_cc_dst, t0);
1949 if (is_right) {
1950 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SARB + ot);
1951 } else {
1952 tcg_gen_movi_i32(cpu_cc_op, CC_OP_SHLB + ot);
1953 }
1954 gen_set_label(label2);
1955 s->cc_op = CC_OP_DYNAMIC; /* cannot predict flags after */
1956
1957 tcg_temp_free(t0);
1958 tcg_temp_free(t1);
1959 tcg_temp_free(t2);
1960 tcg_temp_free(a0);
1961 }
1962
1963 static void gen_shift(DisasContext *s1, int op, int ot, int d, int s)
1964 {
1965 if (s != OR_TMP1)
1966 gen_op_mov_TN_reg(ot, 1, s);
1967 switch(op) {
1968 case OP_ROL:
1969 gen_rot_rm_T1(s1, ot, d, 0);
1970 break;
1971 case OP_ROR:
1972 gen_rot_rm_T1(s1, ot, d, 1);
1973 break;
1974 case OP_SHL:
1975 case OP_SHL1:
1976 gen_shift_rm_T1(s1, ot, d, 0, 0);
1977 break;
1978 case OP_SHR:
1979 gen_shift_rm_T1(s1, ot, d, 1, 0);
1980 break;
1981 case OP_SAR:
1982 gen_shift_rm_T1(s1, ot, d, 1, 1);
1983 break;
1984 case OP_RCL:
1985 gen_rotc_rm_T1(s1, ot, d, 0);
1986 break;
1987 case OP_RCR:
1988 gen_rotc_rm_T1(s1, ot, d, 1);
1989 break;
1990 }
1991 }
1992
1993 static void gen_shifti(DisasContext *s1, int op, int ot, int d, int c)
1994 {
1995 switch(op) {
1996 case OP_ROL:
1997 gen_rot_rm_im(s1, ot, d, c, 0);
1998 break;
1999 case OP_ROR:
2000 gen_rot_rm_im(s1, ot, d, c, 1);
2001 break;
2002 case OP_SHL:
2003 case OP_SHL1:
2004 gen_shift_rm_im(s1, ot, d, c, 0, 0);
2005 break;
2006 case OP_SHR:
2007 gen_shift_rm_im(s1, ot, d, c, 1, 0);
2008 break;
2009 case OP_SAR:
2010 gen_shift_rm_im(s1, ot, d, c, 1, 1);
2011 break;
2012 default:
2013 /* currently not optimized */
2014 gen_op_movl_T1_im(c);
2015 gen_shift(s1, op, ot, d, OR_TMP1);
2016 break;
2017 }
2018 }
2019
2020 static void gen_lea_modrm(DisasContext *s, int modrm, int *reg_ptr, int *offset_ptr)
2021 {
2022 target_long disp;
2023 int havesib;
2024 int base;
2025 int index;
2026 int scale;
2027 int opreg;
2028 int mod, rm, code, override, must_add_seg;
2029
2030 override = s->override;
2031 must_add_seg = s->addseg;
2032 if (override >= 0)
2033 must_add_seg = 1;
2034 mod = (modrm >> 6) & 3;
2035 rm = modrm & 7;
2036
2037 if (s->aflag) {
2038
2039 havesib = 0;
2040 base = rm;
2041 index = 0;
2042 scale = 0;
2043
2044 if (base == 4) {
2045 havesib = 1;
2046 code = cpu_ldub_code(cpu_single_env, s->pc++);
2047 scale = (code >> 6) & 3;
2048 index = ((code >> 3) & 7) | REX_X(s);
2049 base = (code & 7);
2050 }
2051 base |= REX_B(s);
2052
2053 switch (mod) {
2054 case 0:
2055 if ((base & 7) == 5) {
2056 base = -1;
2057 disp = (int32_t)cpu_ldl_code(cpu_single_env, s->pc);
2058 s->pc += 4;
2059 if (CODE64(s) && !havesib) {
2060 disp += s->pc + s->rip_offset;
2061 }
2062 } else {
2063 disp = 0;
2064 }
2065 break;
2066 case 1:
2067 disp = (int8_t)cpu_ldub_code(cpu_single_env, s->pc++);
2068 break;
2069 default:
2070 case 2:
2071 disp = (int32_t)cpu_ldl_code(cpu_single_env, s->pc);
2072 s->pc += 4;
2073 break;
2074 }
2075
2076 if (base >= 0) {
2077 /* for correct popl handling with esp */
2078 if (base == 4 && s->popl_esp_hack)
2079 disp += s->popl_esp_hack;
2080 #ifdef TARGET_X86_64
2081 if (s->aflag == 2) {
2082 gen_op_movq_A0_reg(base);
2083 if (disp != 0) {
2084 gen_op_addq_A0_im(disp);
2085 }
2086 } else
2087 #endif
2088 {
2089 gen_op_movl_A0_reg(base);
2090 if (disp != 0)
2091 gen_op_addl_A0_im(disp);
2092 }
2093 } else {
2094 #ifdef TARGET_X86_64
2095 if (s->aflag == 2) {
2096 gen_op_movq_A0_im(disp);
2097 } else
2098 #endif
2099 {
2100 gen_op_movl_A0_im(disp);
2101 }
2102 }
2103 /* index == 4 means no index */
2104 if (havesib && (index != 4)) {
2105 #ifdef TARGET_X86_64
2106 if (s->aflag == 2) {
2107 gen_op_addq_A0_reg_sN(scale, index);
2108 } else
2109 #endif
2110 {
2111 gen_op_addl_A0_reg_sN(scale, index);
2112 }
2113 }
2114 if (must_add_seg) {
2115 if (override < 0) {
2116 if (base == R_EBP || base == R_ESP)
2117 override = R_SS;
2118 else
2119 override = R_DS;
2120 }
2121 #ifdef TARGET_X86_64
2122 if (s->aflag == 2) {
2123 gen_op_addq_A0_seg(override);
2124 } else
2125 #endif
2126 {
2127 gen_op_addl_A0_seg(s, override);
2128 }
2129 }
2130 } else {
2131 switch (mod) {
2132 case 0:
2133 if (rm == 6) {
2134 disp = cpu_lduw_code(cpu_single_env, s->pc);
2135 s->pc += 2;
2136 gen_op_movl_A0_im(disp);
2137 rm = 0; /* avoid SS override */
2138 goto no_rm;
2139 } else {
2140 disp = 0;
2141 }
2142 break;
2143 case 1:
2144 disp = (int8_t)cpu_ldub_code(cpu_single_env, s->pc++);
2145 break;
2146 default:
2147 case 2:
2148 disp = cpu_lduw_code(cpu_single_env, s->pc);
2149 s->pc += 2;
2150 break;
2151 }
2152 switch(rm) {
2153 case 0:
2154 gen_op_movl_A0_reg(R_EBX);
2155 gen_op_addl_A0_reg_sN(0, R_ESI);
2156 break;
2157 case 1:
2158 gen_op_movl_A0_reg(R_EBX);
2159 gen_op_addl_A0_reg_sN(0, R_EDI);
2160 break;
2161 case 2:
2162 gen_op_movl_A0_reg(R_EBP);
2163 gen_op_addl_A0_reg_sN(0, R_ESI);
2164 break;
2165 case 3:
2166 gen_op_movl_A0_reg(R_EBP);
2167 gen_op_addl_A0_reg_sN(0, R_EDI);
2168 break;
2169 case 4:
2170 gen_op_movl_A0_reg(R_ESI);
2171 break;
2172 case 5:
2173 gen_op_movl_A0_reg(R_EDI);
2174 break;
2175 case 6:
2176 gen_op_movl_A0_reg(R_EBP);
2177 break;
2178 default:
2179 case 7:
2180 gen_op_movl_A0_reg(R_EBX);
2181 break;
2182 }
2183 if (disp != 0)
2184 gen_op_addl_A0_im(disp);
2185 gen_op_andl_A0_ffff();
2186 no_rm:
2187 if (must_add_seg) {
2188 if (override < 0) {
2189 if (rm == 2 || rm == 3 || rm == 6)
2190 override = R_SS;
2191 else
2192 override = R_DS;
2193 }
2194 gen_op_addl_A0_seg(s, override);
2195 }
2196 }
2197
2198 opreg = OR_A0;
2199 disp = 0;
2200 *reg_ptr = opreg;
2201 *offset_ptr = disp;
2202 }
2203
2204 static void gen_nop_modrm(DisasContext *s, int modrm)
2205 {
2206 int mod, rm, base, code;
2207
2208 mod = (modrm >> 6) & 3;
2209 if (mod == 3)
2210 return;
2211 rm = modrm & 7;
2212
2213 if (s->aflag) {
2214
2215 base = rm;
2216
2217 if (base == 4) {
2218 code = cpu_ldub_code(cpu_single_env, s->pc++);
2219 base = (code & 7);
2220 }
2221
2222 switch (mod) {
2223 case 0:
2224 if (base == 5) {
2225 s->pc += 4;
2226 }
2227 break;
2228 case 1:
2229 s->pc++;
2230 break;
2231 default:
2232 case 2:
2233 s->pc += 4;
2234 break;
2235 }
2236 } else {
2237 switch (mod) {
2238 case 0:
2239 if (rm == 6) {
2240 s->pc += 2;
2241 }
2242 break;
2243 case 1:
2244 s->pc++;
2245 break;
2246 default:
2247 case 2:
2248 s->pc += 2;
2249 break;
2250 }
2251 }
2252 }
2253
2254 /* used for LEA and MOV AX, mem */
2255 static void gen_add_A0_ds_seg(DisasContext *s)
2256 {
2257 int override, must_add_seg;
2258 must_add_seg = s->addseg;
2259 override = R_DS;
2260 if (s->override >= 0) {
2261 override = s->override;
2262 must_add_seg = 1;
2263 }
2264 if (must_add_seg) {
2265 #ifdef TARGET_X86_64
2266 if (CODE64(s)) {
2267 gen_op_addq_A0_seg(override);
2268 } else
2269 #endif
2270 {
2271 gen_op_addl_A0_seg(s, override);
2272 }
2273 }
2274 }
2275
2276 /* generate modrm memory load or store of 'reg'. TMP0 is used if reg ==
2277 OR_TMP0 */
2278 static void gen_ldst_modrm(DisasContext *s, int modrm, int ot, int reg, int is_store)
2279 {
2280 int mod, rm, opreg, disp;
2281
2282 mod = (modrm >> 6) & 3;
2283 rm = (modrm & 7) | REX_B(s);
2284 if (mod == 3) {
2285 if (is_store) {
2286 if (reg != OR_TMP0)
2287 gen_op_mov_TN_reg(ot, 0, reg);
2288 gen_op_mov_reg_T0(ot, rm);
2289 } else {
2290 gen_op_mov_TN_reg(ot, 0, rm);
2291 if (reg != OR_TMP0)
2292 gen_op_mov_reg_T0(ot, reg);
2293 }
2294 } else {
2295 gen_lea_modrm(s, modrm, &opreg, &disp);
2296 if (is_store) {
2297 if (reg != OR_TMP0)
2298 gen_op_mov_TN_reg(ot, 0, reg);
2299 gen_op_st_T0_A0(ot + s->mem_index);
2300 } else {
2301 gen_op_ld_T0_A0(ot + s->mem_index);
2302 if (reg != OR_TMP0)
2303 gen_op_mov_reg_T0(ot, reg);
2304 }
2305 }
2306 }
2307
2308 static inline uint32_t insn_get(DisasContext *s, int ot)
2309 {
2310 uint32_t ret;
2311
2312 switch(ot) {
2313 case OT_BYTE:
2314 ret = cpu_ldub_code(cpu_single_env, s->pc);
2315 s->pc++;
2316 break;
2317 case OT_WORD:
2318 ret = cpu_lduw_code(cpu_single_env, s->pc);
2319 s->pc += 2;
2320 break;
2321 default:
2322 case OT_LONG:
2323 ret = cpu_ldl_code(cpu_single_env, s->pc);
2324 s->pc += 4;
2325 break;
2326 }
2327 return ret;
2328 }
2329
2330 static inline int insn_const_size(unsigned int ot)
2331 {
2332 if (ot <= OT_LONG)
2333 return 1 << ot;
2334 else
2335 return 4;
2336 }
2337
2338 static inline void gen_goto_tb(DisasContext *s, int tb_num, target_ulong eip)
2339 {
2340 TranslationBlock *tb;
2341 target_ulong pc;
2342
2343 pc = s->cs_base + eip;
2344 tb = s->tb;
2345 /* NOTE: we handle the case where the TB spans two pages here */
2346 if ((pc & TARGET_PAGE_MASK) == (tb->pc & TARGET_PAGE_MASK) ||
2347 (pc & TARGET_PAGE_MASK) == ((s->pc - 1) & TARGET_PAGE_MASK)) {
2348 /* jump to same page: we can use a direct jump */
2349 tcg_gen_goto_tb(tb_num);
2350 gen_jmp_im(eip);
2351 tcg_gen_exit_tb((tcg_target_long)tb + tb_num);
2352 } else {
2353 /* jump to another page: currently not optimized */
2354 gen_jmp_im(eip);
2355 gen_eob(s);
2356 }
2357 }
2358
2359 static inline void gen_jcc(DisasContext *s, int b,
2360 target_ulong val, target_ulong next_eip)
2361 {
2362 int l1, l2, cc_op;
2363
2364 cc_op = s->cc_op;
2365 gen_update_cc_op(s);
2366 if (s->jmp_opt) {
2367 l1 = gen_new_label();
2368 gen_jcc1(s, cc_op, b, l1);
2369
2370 gen_goto_tb(s, 0, next_eip);
2371
2372 gen_set_label(l1);
2373 gen_goto_tb(s, 1, val);
2374 s->is_jmp = DISAS_TB_JUMP;
2375 } else {
2376
2377 l1 = gen_new_label();
2378 l2 = gen_new_label();
2379 gen_jcc1(s, cc_op, b, l1);
2380
2381 gen_jmp_im(next_eip);
2382 tcg_gen_br(l2);
2383
2384 gen_set_label(l1);
2385 gen_jmp_im(val);
2386 gen_set_label(l2);
2387 gen_eob(s);
2388 }
2389 }
2390
2391 static void gen_setcc(DisasContext *s, int b)
2392 {
2393 int inv, jcc_op, l1;
2394 TCGv t0;
2395
2396 if (is_fast_jcc_case(s, b)) {
2397 /* nominal case: we use a jump */
2398 /* XXX: make it faster by adding new instructions in TCG */
2399 t0 = tcg_temp_local_new();
2400 tcg_gen_movi_tl(t0, 0);
2401 l1 = gen_new_label();
2402 gen_jcc1(s, s->cc_op, b ^ 1, l1);
2403 tcg_gen_movi_tl(t0, 1);
2404 gen_set_label(l1);
2405 tcg_gen_mov_tl(cpu_T[0], t0);
2406 tcg_temp_free(t0);
2407 } else {
2408 /* slow case: it is more efficient not to generate a jump,
2409 although it is questionnable whether this optimization is
2410 worth to */
2411 inv = b & 1;
2412 jcc_op = (b >> 1) & 7;
2413 gen_setcc_slow_T0(s, jcc_op);
2414 if (inv) {
2415 tcg_gen_xori_tl(cpu_T[0], cpu_T[0], 1);
2416 }
2417 }
2418 }
2419
2420 static inline void gen_op_movl_T0_seg(int seg_reg)
2421 {
2422 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
2423 offsetof(CPUX86State,segs[seg_reg].selector));
2424 }
2425
2426 static inline void gen_op_movl_seg_T0_vm(int seg_reg)
2427 {
2428 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xffff);
2429 tcg_gen_st32_tl(cpu_T[0], cpu_env,
2430 offsetof(CPUX86State,segs[seg_reg].selector));
2431 tcg_gen_shli_tl(cpu_T[0], cpu_T[0], 4);
2432 tcg_gen_st_tl(cpu_T[0], cpu_env,
2433 offsetof(CPUX86State,segs[seg_reg].base));
2434 }
2435
2436 /* move T0 to seg_reg and compute if the CPU state may change. Never
2437 call this function with seg_reg == R_CS */
2438 static void gen_movl_seg_T0(DisasContext *s, int seg_reg, target_ulong cur_eip)
2439 {
2440 if (s->pe && !s->vm86) {
2441 /* XXX: optimize by finding processor state dynamically */
2442 if (s->cc_op != CC_OP_DYNAMIC)
2443 gen_op_set_cc_op(s->cc_op);
2444 gen_jmp_im(cur_eip);
2445 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
2446 gen_helper_load_seg(cpu_env, tcg_const_i32(seg_reg), cpu_tmp2_i32);
2447 /* abort translation because the addseg value may change or
2448 because ss32 may change. For R_SS, translation must always
2449 stop as a special handling must be done to disable hardware
2450 interrupts for the next instruction */
2451 if (seg_reg == R_SS || (s->code32 && seg_reg < R_FS))
2452 s->is_jmp = DISAS_TB_JUMP;
2453 } else {
2454 gen_op_movl_seg_T0_vm(seg_reg);
2455 if (seg_reg == R_SS)
2456 s->is_jmp = DISAS_TB_JUMP;
2457 }
2458 }
2459
2460 static inline int svm_is_rep(int prefixes)
2461 {
2462 return ((prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) ? 8 : 0);
2463 }
2464
2465 static inline void
2466 gen_svm_check_intercept_param(DisasContext *s, target_ulong pc_start,
2467 uint32_t type, uint64_t param)
2468 {
2469 /* no SVM activated; fast case */
2470 if (likely(!(s->flags & HF_SVMI_MASK)))
2471 return;
2472 if (s->cc_op != CC_OP_DYNAMIC)
2473 gen_op_set_cc_op(s->cc_op);
2474 gen_jmp_im(pc_start - s->cs_base);
2475 gen_helper_svm_check_intercept_param(cpu_env, tcg_const_i32(type),
2476 tcg_const_i64(param));
2477 }
2478
2479 static inline void
2480 gen_svm_check_intercept(DisasContext *s, target_ulong pc_start, uint64_t type)
2481 {
2482 gen_svm_check_intercept_param(s, pc_start, type, 0);
2483 }
2484
2485 static inline void gen_stack_update(DisasContext *s, int addend)
2486 {
2487 #ifdef TARGET_X86_64
2488 if (CODE64(s)) {
2489 gen_op_add_reg_im(2, R_ESP, addend);
2490 } else
2491 #endif
2492 if (s->ss32) {
2493 gen_op_add_reg_im(1, R_ESP, addend);
2494 } else {
2495 gen_op_add_reg_im(0, R_ESP, addend);
2496 }
2497 }
2498
2499 /* generate a push. It depends on ss32, addseg and dflag */
2500 static void gen_push_T0(DisasContext *s)
2501 {
2502 #ifdef TARGET_X86_64
2503 if (CODE64(s)) {
2504 gen_op_movq_A0_reg(R_ESP);
2505 if (s->dflag) {
2506 gen_op_addq_A0_im(-8);
2507 gen_op_st_T0_A0(OT_QUAD + s->mem_index);
2508 } else {
2509 gen_op_addq_A0_im(-2);
2510 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2511 }
2512 gen_op_mov_reg_A0(2, R_ESP);
2513 } else
2514 #endif
2515 {
2516 gen_op_movl_A0_reg(R_ESP);
2517 if (!s->dflag)
2518 gen_op_addl_A0_im(-2);
2519 else
2520 gen_op_addl_A0_im(-4);
2521 if (s->ss32) {
2522 if (s->addseg) {
2523 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2524 gen_op_addl_A0_seg(s, R_SS);
2525 }
2526 } else {
2527 gen_op_andl_A0_ffff();
2528 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2529 gen_op_addl_A0_seg(s, R_SS);
2530 }
2531 gen_op_st_T0_A0(s->dflag + 1 + s->mem_index);
2532 if (s->ss32 && !s->addseg)
2533 gen_op_mov_reg_A0(1, R_ESP);
2534 else
2535 gen_op_mov_reg_T1(s->ss32 + 1, R_ESP);
2536 }
2537 }
2538
2539 /* generate a push. It depends on ss32, addseg and dflag */
2540 /* slower version for T1, only used for call Ev */
2541 static void gen_push_T1(DisasContext *s)
2542 {
2543 #ifdef TARGET_X86_64
2544 if (CODE64(s)) {
2545 gen_op_movq_A0_reg(R_ESP);
2546 if (s->dflag) {
2547 gen_op_addq_A0_im(-8);
2548 gen_op_st_T1_A0(OT_QUAD + s->mem_index);
2549 } else {
2550 gen_op_addq_A0_im(-2);
2551 gen_op_st_T0_A0(OT_WORD + s->mem_index);
2552 }
2553 gen_op_mov_reg_A0(2, R_ESP);
2554 } else
2555 #endif
2556 {
2557 gen_op_movl_A0_reg(R_ESP);
2558 if (!s->dflag)
2559 gen_op_addl_A0_im(-2);
2560 else
2561 gen_op_addl_A0_im(-4);
2562 if (s->ss32) {
2563 if (s->addseg) {
2564 gen_op_addl_A0_seg(s, R_SS);
2565 }
2566 } else {
2567 gen_op_andl_A0_ffff();
2568 gen_op_addl_A0_seg(s, R_SS);
2569 }
2570 gen_op_st_T1_A0(s->dflag + 1 + s->mem_index);
2571
2572 if (s->ss32 && !s->addseg)
2573 gen_op_mov_reg_A0(1, R_ESP);
2574 else
2575 gen_stack_update(s, (-2) << s->dflag);
2576 }
2577 }
2578
2579 /* two step pop is necessary for precise exceptions */
2580 static void gen_pop_T0(DisasContext *s)
2581 {
2582 #ifdef TARGET_X86_64
2583 if (CODE64(s)) {
2584 gen_op_movq_A0_reg(R_ESP);
2585 gen_op_ld_T0_A0((s->dflag ? OT_QUAD : OT_WORD) + s->mem_index);
2586 } else
2587 #endif
2588 {
2589 gen_op_movl_A0_reg(R_ESP);
2590 if (s->ss32) {
2591 if (s->addseg)
2592 gen_op_addl_A0_seg(s, R_SS);
2593 } else {
2594 gen_op_andl_A0_ffff();
2595 gen_op_addl_A0_seg(s, R_SS);
2596 }
2597 gen_op_ld_T0_A0(s->dflag + 1 + s->mem_index);
2598 }
2599 }
2600
2601 static void gen_pop_update(DisasContext *s)
2602 {
2603 #ifdef TARGET_X86_64
2604 if (CODE64(s) && s->dflag) {
2605 gen_stack_update(s, 8);
2606 } else
2607 #endif
2608 {
2609 gen_stack_update(s, 2 << s->dflag);
2610 }
2611 }
2612
2613 static void gen_stack_A0(DisasContext *s)
2614 {
2615 gen_op_movl_A0_reg(R_ESP);
2616 if (!s->ss32)
2617 gen_op_andl_A0_ffff();
2618 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2619 if (s->addseg)
2620 gen_op_addl_A0_seg(s, R_SS);
2621 }
2622
2623 /* NOTE: wrap around in 16 bit not fully handled */
2624 static void gen_pusha(DisasContext *s)
2625 {
2626 int i;
2627 gen_op_movl_A0_reg(R_ESP);
2628 gen_op_addl_A0_im(-16 << s->dflag);
2629 if (!s->ss32)
2630 gen_op_andl_A0_ffff();
2631 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2632 if (s->addseg)
2633 gen_op_addl_A0_seg(s, R_SS);
2634 for(i = 0;i < 8; i++) {
2635 gen_op_mov_TN_reg(OT_LONG, 0, 7 - i);
2636 gen_op_st_T0_A0(OT_WORD + s->dflag + s->mem_index);
2637 gen_op_addl_A0_im(2 << s->dflag);
2638 }
2639 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2640 }
2641
2642 /* NOTE: wrap around in 16 bit not fully handled */
2643 static void gen_popa(DisasContext *s)
2644 {
2645 int i;
2646 gen_op_movl_A0_reg(R_ESP);
2647 if (!s->ss32)
2648 gen_op_andl_A0_ffff();
2649 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2650 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], 16 << s->dflag);
2651 if (s->addseg)
2652 gen_op_addl_A0_seg(s, R_SS);
2653 for(i = 0;i < 8; i++) {
2654 /* ESP is not reloaded */
2655 if (i != 3) {
2656 gen_op_ld_T0_A0(OT_WORD + s->dflag + s->mem_index);
2657 gen_op_mov_reg_T0(OT_WORD + s->dflag, 7 - i);
2658 }
2659 gen_op_addl_A0_im(2 << s->dflag);
2660 }
2661 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2662 }
2663
2664 static void gen_enter(DisasContext *s, int esp_addend, int level)
2665 {
2666 int ot, opsize;
2667
2668 level &= 0x1f;
2669 #ifdef TARGET_X86_64
2670 if (CODE64(s)) {
2671 ot = s->dflag ? OT_QUAD : OT_WORD;
2672 opsize = 1 << ot;
2673
2674 gen_op_movl_A0_reg(R_ESP);
2675 gen_op_addq_A0_im(-opsize);
2676 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2677
2678 /* push bp */
2679 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2680 gen_op_st_T0_A0(ot + s->mem_index);
2681 if (level) {
2682 /* XXX: must save state */
2683 gen_helper_enter64_level(cpu_env, tcg_const_i32(level),
2684 tcg_const_i32((ot == OT_QUAD)),
2685 cpu_T[1]);
2686 }
2687 gen_op_mov_reg_T1(ot, R_EBP);
2688 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2689 gen_op_mov_reg_T1(OT_QUAD, R_ESP);
2690 } else
2691 #endif
2692 {
2693 ot = s->dflag + OT_WORD;
2694 opsize = 2 << s->dflag;
2695
2696 gen_op_movl_A0_reg(R_ESP);
2697 gen_op_addl_A0_im(-opsize);
2698 if (!s->ss32)
2699 gen_op_andl_A0_ffff();
2700 tcg_gen_mov_tl(cpu_T[1], cpu_A0);
2701 if (s->addseg)
2702 gen_op_addl_A0_seg(s, R_SS);
2703 /* push bp */
2704 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
2705 gen_op_st_T0_A0(ot + s->mem_index);
2706 if (level) {
2707 /* XXX: must save state */
2708 gen_helper_enter_level(cpu_env, tcg_const_i32(level),
2709 tcg_const_i32(s->dflag),
2710 cpu_T[1]);
2711 }
2712 gen_op_mov_reg_T1(ot, R_EBP);
2713 tcg_gen_addi_tl(cpu_T[1], cpu_T[1], -esp_addend + (-opsize * level));
2714 gen_op_mov_reg_T1(OT_WORD + s->ss32, R_ESP);
2715 }
2716 }
2717
2718 static void gen_exception(DisasContext *s, int trapno, target_ulong cur_eip)
2719 {
2720 if (s->cc_op != CC_OP_DYNAMIC)
2721 gen_op_set_cc_op(s->cc_op);
2722 gen_jmp_im(cur_eip);
2723 gen_helper_raise_exception(cpu_env, tcg_const_i32(trapno));
2724 s->is_jmp = DISAS_TB_JUMP;
2725 }
2726
2727 /* an interrupt is different from an exception because of the
2728 privilege checks */
2729 static void gen_interrupt(DisasContext *s, int intno,
2730 target_ulong cur_eip, target_ulong next_eip)
2731 {
2732 if (s->cc_op != CC_OP_DYNAMIC)
2733 gen_op_set_cc_op(s->cc_op);
2734 gen_jmp_im(cur_eip);
2735 gen_helper_raise_interrupt(cpu_env, tcg_const_i32(intno),
2736 tcg_const_i32(next_eip - cur_eip));
2737 s->is_jmp = DISAS_TB_JUMP;
2738 }
2739
2740 static void gen_debug(DisasContext *s, target_ulong cur_eip)
2741 {
2742 if (s->cc_op != CC_OP_DYNAMIC)
2743 gen_op_set_cc_op(s->cc_op);
2744 gen_jmp_im(cur_eip);
2745 gen_helper_debug(cpu_env);
2746 s->is_jmp = DISAS_TB_JUMP;
2747 }
2748
2749 /* generate a generic end of block. Trace exception is also generated
2750 if needed */
2751 static void gen_eob(DisasContext *s)
2752 {
2753 if (s->cc_op != CC_OP_DYNAMIC)
2754 gen_op_set_cc_op(s->cc_op);
2755 if (s->tb->flags & HF_INHIBIT_IRQ_MASK) {
2756 gen_helper_reset_inhibit_irq(cpu_env);
2757 }
2758 if (s->tb->flags & HF_RF_MASK) {
2759 gen_helper_reset_rf(cpu_env);
2760 }
2761 if (s->singlestep_enabled) {
2762 gen_helper_debug(cpu_env);
2763 } else if (s->tf) {
2764 gen_helper_single_step(cpu_env);
2765 } else {
2766 tcg_gen_exit_tb(0);
2767 }
2768 s->is_jmp = DISAS_TB_JUMP;
2769 }
2770
2771 /* generate a jump to eip. No segment change must happen before as a
2772 direct call to the next block may occur */
2773 static void gen_jmp_tb(DisasContext *s, target_ulong eip, int tb_num)
2774 {
2775 if (s->jmp_opt) {
2776 gen_update_cc_op(s);
2777 gen_goto_tb(s, tb_num, eip);
2778 s->is_jmp = DISAS_TB_JUMP;
2779 } else {
2780 gen_jmp_im(eip);
2781 gen_eob(s);
2782 }
2783 }
2784
2785 static void gen_jmp(DisasContext *s, target_ulong eip)
2786 {
2787 gen_jmp_tb(s, eip, 0);
2788 }
2789
2790 static inline void gen_ldq_env_A0(int idx, int offset)
2791 {
2792 int mem_index = (idx >> 2) - 1;
2793 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2794 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset);
2795 }
2796
2797 static inline void gen_stq_env_A0(int idx, int offset)
2798 {
2799 int mem_index = (idx >> 2) - 1;
2800 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset);
2801 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2802 }
2803
2804 static inline void gen_ldo_env_A0(int idx, int offset)
2805 {
2806 int mem_index = (idx >> 2) - 1;
2807 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0, mem_index);
2808 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2809 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2810 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2811 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2812 }
2813
2814 static inline void gen_sto_env_A0(int idx, int offset)
2815 {
2816 int mem_index = (idx >> 2) - 1;
2817 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(0)));
2818 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0, mem_index);
2819 tcg_gen_addi_tl(cpu_tmp0, cpu_A0, 8);
2820 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, offset + offsetof(XMMReg, XMM_Q(1)));
2821 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_tmp0, mem_index);
2822 }
2823
2824 static inline void gen_op_movo(int d_offset, int s_offset)
2825 {
2826 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2827 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2828 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset + 8);
2829 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset + 8);
2830 }
2831
2832 static inline void gen_op_movq(int d_offset, int s_offset)
2833 {
2834 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env, s_offset);
2835 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2836 }
2837
2838 static inline void gen_op_movl(int d_offset, int s_offset)
2839 {
2840 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env, s_offset);
2841 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, d_offset);
2842 }
2843
2844 static inline void gen_op_movq_env_0(int d_offset)
2845 {
2846 tcg_gen_movi_i64(cpu_tmp1_i64, 0);
2847 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env, d_offset);
2848 }
2849
2850 typedef void (*SSEFunc_i_ep)(TCGv_i32 val, TCGv_ptr env, TCGv_ptr reg);
2851 typedef void (*SSEFunc_l_ep)(TCGv_i64 val, TCGv_ptr env, TCGv_ptr reg);
2852 typedef void (*SSEFunc_0_epi)(TCGv_ptr env, TCGv_ptr reg, TCGv_i32 val);
2853 typedef void (*SSEFunc_0_epl)(TCGv_ptr env, TCGv_ptr reg, TCGv_i64 val);
2854 typedef void (*SSEFunc_0_epp)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b);
2855 typedef void (*SSEFunc_0_eppi)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b,
2856 TCGv_i32 val);
2857 typedef void (*SSEFunc_0_ppi)(TCGv_ptr reg_a, TCGv_ptr reg_b, TCGv_i32 val);
2858 typedef void (*SSEFunc_0_eppt)(TCGv_ptr env, TCGv_ptr reg_a, TCGv_ptr reg_b,
2859 TCGv val);
2860
2861 #define SSE_SPECIAL ((void *)1)
2862 #define SSE_DUMMY ((void *)2)
2863
2864 #define MMX_OP2(x) { gen_helper_ ## x ## _mmx, gen_helper_ ## x ## _xmm }
2865 #define SSE_FOP(x) { gen_helper_ ## x ## ps, gen_helper_ ## x ## pd, \
2866 gen_helper_ ## x ## ss, gen_helper_ ## x ## sd, }
2867
2868 static const SSEFunc_0_epp sse_op_table1[256][4] = {
2869 /* 3DNow! extensions */
2870 [0x0e] = { SSE_DUMMY }, /* femms */
2871 [0x0f] = { SSE_DUMMY }, /* pf... */
2872 /* pure SSE operations */
2873 [0x10] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2874 [0x11] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movups, movupd, movss, movsd */
2875 [0x12] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd, movsldup, movddup */
2876 [0x13] = { SSE_SPECIAL, SSE_SPECIAL }, /* movlps, movlpd */
2877 [0x14] = { gen_helper_punpckldq_xmm, gen_helper_punpcklqdq_xmm },
2878 [0x15] = { gen_helper_punpckhdq_xmm, gen_helper_punpckhqdq_xmm },
2879 [0x16] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd, movshdup */
2880 [0x17] = { SSE_SPECIAL, SSE_SPECIAL }, /* movhps, movhpd */
2881
2882 [0x28] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2883 [0x29] = { SSE_SPECIAL, SSE_SPECIAL }, /* movaps, movapd */
2884 [0x2a] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtpi2ps, cvtpi2pd, cvtsi2ss, cvtsi2sd */
2885 [0x2b] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movntps, movntpd, movntss, movntsd */
2886 [0x2c] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvttps2pi, cvttpd2pi, cvttsd2si, cvttss2si */
2887 [0x2d] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* cvtps2pi, cvtpd2pi, cvtsd2si, cvtss2si */
2888 [0x2e] = { gen_helper_ucomiss, gen_helper_ucomisd },
2889 [0x2f] = { gen_helper_comiss, gen_helper_comisd },
2890 [0x50] = { SSE_SPECIAL, SSE_SPECIAL }, /* movmskps, movmskpd */
2891 [0x51] = SSE_FOP(sqrt),
2892 [0x52] = { gen_helper_rsqrtps, NULL, gen_helper_rsqrtss, NULL },
2893 [0x53] = { gen_helper_rcpps, NULL, gen_helper_rcpss, NULL },
2894 [0x54] = { gen_helper_pand_xmm, gen_helper_pand_xmm }, /* andps, andpd */
2895 [0x55] = { gen_helper_pandn_xmm, gen_helper_pandn_xmm }, /* andnps, andnpd */
2896 [0x56] = { gen_helper_por_xmm, gen_helper_por_xmm }, /* orps, orpd */
2897 [0x57] = { gen_helper_pxor_xmm, gen_helper_pxor_xmm }, /* xorps, xorpd */
2898 [0x58] = SSE_FOP(add),
2899 [0x59] = SSE_FOP(mul),
2900 [0x5a] = { gen_helper_cvtps2pd, gen_helper_cvtpd2ps,
2901 gen_helper_cvtss2sd, gen_helper_cvtsd2ss },
2902 [0x5b] = { gen_helper_cvtdq2ps, gen_helper_cvtps2dq, gen_helper_cvttps2dq },
2903 [0x5c] = SSE_FOP(sub),
2904 [0x5d] = SSE_FOP(min),
2905 [0x5e] = SSE_FOP(div),
2906 [0x5f] = SSE_FOP(max),
2907
2908 [0xc2] = SSE_FOP(cmpeq),
2909 [0xc6] = { (SSEFunc_0_epp)gen_helper_shufps,
2910 (SSEFunc_0_epp)gen_helper_shufpd }, /* XXX: casts */
2911
2912 [0x38] = { SSE_SPECIAL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* SSSE3/SSE4 */
2913 [0x3a] = { SSE_SPECIAL, SSE_SPECIAL }, /* SSSE3/SSE4 */
2914
2915 /* MMX ops and their SSE extensions */
2916 [0x60] = MMX_OP2(punpcklbw),
2917 [0x61] = MMX_OP2(punpcklwd),
2918 [0x62] = MMX_OP2(punpckldq),
2919 [0x63] = MMX_OP2(packsswb),
2920 [0x64] = MMX_OP2(pcmpgtb),
2921 [0x65] = MMX_OP2(pcmpgtw),
2922 [0x66] = MMX_OP2(pcmpgtl),
2923 [0x67] = MMX_OP2(packuswb),
2924 [0x68] = MMX_OP2(punpckhbw),
2925 [0x69] = MMX_OP2(punpckhwd),
2926 [0x6a] = MMX_OP2(punpckhdq),
2927 [0x6b] = MMX_OP2(packssdw),
2928 [0x6c] = { NULL, gen_helper_punpcklqdq_xmm },
2929 [0x6d] = { NULL, gen_helper_punpckhqdq_xmm },
2930 [0x6e] = { SSE_SPECIAL, SSE_SPECIAL }, /* movd mm, ea */
2931 [0x6f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, , movqdu */
2932 [0x70] = { (SSEFunc_0_epp)gen_helper_pshufw_mmx,
2933 (SSEFunc_0_epp)gen_helper_pshufd_xmm,
2934 (SSEFunc_0_epp)gen_helper_pshufhw_xmm,
2935 (SSEFunc_0_epp)gen_helper_pshuflw_xmm }, /* XXX: casts */
2936 [0x71] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftw */
2937 [0x72] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftd */
2938 [0x73] = { SSE_SPECIAL, SSE_SPECIAL }, /* shiftq */
2939 [0x74] = MMX_OP2(pcmpeqb),
2940 [0x75] = MMX_OP2(pcmpeqw),
2941 [0x76] = MMX_OP2(pcmpeql),
2942 [0x77] = { SSE_DUMMY }, /* emms */
2943 [0x78] = { NULL, SSE_SPECIAL, NULL, SSE_SPECIAL }, /* extrq_i, insertq_i */
2944 [0x79] = { NULL, gen_helper_extrq_r, NULL, gen_helper_insertq_r },
2945 [0x7c] = { NULL, gen_helper_haddpd, NULL, gen_helper_haddps },
2946 [0x7d] = { NULL, gen_helper_hsubpd, NULL, gen_helper_hsubps },
2947 [0x7e] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movd, movd, , movq */
2948 [0x7f] = { SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL }, /* movq, movdqa, movdqu */
2949 [0xc4] = { SSE_SPECIAL, SSE_SPECIAL }, /* pinsrw */
2950 [0xc5] = { SSE_SPECIAL, SSE_SPECIAL }, /* pextrw */
2951 [0xd0] = { NULL, gen_helper_addsubpd, NULL, gen_helper_addsubps },
2952 [0xd1] = MMX_OP2(psrlw),
2953 [0xd2] = MMX_OP2(psrld),
2954 [0xd3] = MMX_OP2(psrlq),
2955 [0xd4] = MMX_OP2(paddq),
2956 [0xd5] = MMX_OP2(pmullw),
2957 [0xd6] = { NULL, SSE_SPECIAL, SSE_SPECIAL, SSE_SPECIAL },
2958 [0xd7] = { SSE_SPECIAL, SSE_SPECIAL }, /* pmovmskb */
2959 [0xd8] = MMX_OP2(psubusb),
2960 [0xd9] = MMX_OP2(psubusw),
2961 [0xda] = MMX_OP2(pminub),
2962 [0xdb] = MMX_OP2(pand),
2963 [0xdc] = MMX_OP2(paddusb),
2964 [0xdd] = MMX_OP2(paddusw),
2965 [0xde] = MMX_OP2(pmaxub),
2966 [0xdf] = MMX_OP2(pandn),
2967 [0xe0] = MMX_OP2(pavgb),
2968 [0xe1] = MMX_OP2(psraw),
2969 [0xe2] = MMX_OP2(psrad),
2970 [0xe3] = MMX_OP2(pavgw),
2971 [0xe4] = MMX_OP2(pmulhuw),
2972 [0xe5] = MMX_OP2(pmulhw),
2973 [0xe6] = { NULL, gen_helper_cvttpd2dq, gen_helper_cvtdq2pd, gen_helper_cvtpd2dq },
2974 [0xe7] = { SSE_SPECIAL , SSE_SPECIAL }, /* movntq, movntq */
2975 [0xe8] = MMX_OP2(psubsb),
2976 [0xe9] = MMX_OP2(psubsw),
2977 [0xea] = MMX_OP2(pminsw),
2978 [0xeb] = MMX_OP2(por),
2979 [0xec] = MMX_OP2(paddsb),
2980 [0xed] = MMX_OP2(paddsw),
2981 [0xee] = MMX_OP2(pmaxsw),
2982 [0xef] = MMX_OP2(pxor),
2983 [0xf0] = { NULL, NULL, NULL, SSE_SPECIAL }, /* lddqu */
2984 [0xf1] = MMX_OP2(psllw),
2985 [0xf2] = MMX_OP2(pslld),
2986 [0xf3] = MMX_OP2(psllq),
2987 [0xf4] = MMX_OP2(pmuludq),
2988 [0xf5] = MMX_OP2(pmaddwd),
2989 [0xf6] = MMX_OP2(psadbw),
2990 [0xf7] = { (SSEFunc_0_epp)gen_helper_maskmov_mmx,
2991 (SSEFunc_0_epp)gen_helper_maskmov_xmm }, /* XXX: casts */
2992 [0xf8] = MMX_OP2(psubb),
2993 [0xf9] = MMX_OP2(psubw),
2994 [0xfa] = MMX_OP2(psubl),
2995 [0xfb] = MMX_OP2(psubq),
2996 [0xfc] = MMX_OP2(paddb),
2997 [0xfd] = MMX_OP2(paddw),
2998 [0xfe] = MMX_OP2(paddl),
2999 };
3000
3001 static const SSEFunc_0_epp sse_op_table2[3 * 8][2] = {
3002 [0 + 2] = MMX_OP2(psrlw),
3003 [0 + 4] = MMX_OP2(psraw),
3004 [0 + 6] = MMX_OP2(psllw),
3005 [8 + 2] = MMX_OP2(psrld),
3006 [8 + 4] = MMX_OP2(psrad),
3007 [8 + 6] = MMX_OP2(pslld),
3008 [16 + 2] = MMX_OP2(psrlq),
3009 [16 + 3] = { NULL, gen_helper_psrldq_xmm },
3010 [16 + 6] = MMX_OP2(psllq),
3011 [16 + 7] = { NULL, gen_helper_pslldq_xmm },
3012 };
3013
3014 static const SSEFunc_0_epi sse_op_table3ai[] = {
3015 gen_helper_cvtsi2ss,
3016 gen_helper_cvtsi2sd
3017 };
3018
3019 #ifdef TARGET_X86_64
3020 static const SSEFunc_0_epl sse_op_table3aq[] = {
3021 gen_helper_cvtsq2ss,
3022 gen_helper_cvtsq2sd
3023 };
3024 #endif
3025
3026 static const SSEFunc_i_ep sse_op_table3bi[] = {
3027 gen_helper_cvttss2si,
3028 gen_helper_cvtss2si,
3029 gen_helper_cvttsd2si,
3030 gen_helper_cvtsd2si
3031 };
3032
3033 #ifdef TARGET_X86_64
3034 static const SSEFunc_l_ep sse_op_table3bq[] = {
3035 gen_helper_cvttss2sq,
3036 gen_helper_cvtss2sq,
3037 gen_helper_cvttsd2sq,
3038 gen_helper_cvtsd2sq
3039 };
3040 #endif
3041
3042 static const SSEFunc_0_epp sse_op_table4[8][4] = {
3043 SSE_FOP(cmpeq),
3044 SSE_FOP(cmplt),
3045 SSE_FOP(cmple),
3046 SSE_FOP(cmpunord),
3047 SSE_FOP(cmpneq),
3048 SSE_FOP(cmpnlt),
3049 SSE_FOP(cmpnle),
3050 SSE_FOP(cmpord),
3051 };
3052
3053 static const SSEFunc_0_epp sse_op_table5[256] = {
3054 [0x0c] = gen_helper_pi2fw,
3055 [0x0d] = gen_helper_pi2fd,
3056 [0x1c] = gen_helper_pf2iw,
3057 [0x1d] = gen_helper_pf2id,
3058 [0x8a] = gen_helper_pfnacc,
3059 [0x8e] = gen_helper_pfpnacc,
3060 [0x90] = gen_helper_pfcmpge,
3061 [0x94] = gen_helper_pfmin,
3062 [0x96] = gen_helper_pfrcp,
3063 [0x97] = gen_helper_pfrsqrt,
3064 [0x9a] = gen_helper_pfsub,
3065 [0x9e] = gen_helper_pfadd,
3066 [0xa0] = gen_helper_pfcmpgt,
3067 [0xa4] = gen_helper_pfmax,
3068 [0xa6] = gen_helper_movq, /* pfrcpit1; no need to actually increase precision */
3069 [0xa7] = gen_helper_movq, /* pfrsqit1 */
3070 [0xaa] = gen_helper_pfsubr,
3071 [0xae] = gen_helper_pfacc,
3072 [0xb0] = gen_helper_pfcmpeq,
3073 [0xb4] = gen_helper_pfmul,
3074 [0xb6] = gen_helper_movq, /* pfrcpit2 */
3075 [0xb7] = gen_helper_pmulhrw_mmx,
3076 [0xbb] = gen_helper_pswapd,
3077 [0xbf] = gen_helper_pavgb_mmx /* pavgusb */
3078 };
3079
3080 struct SSEOpHelper_epp {
3081 SSEFunc_0_epp op[2];
3082 uint32_t ext_mask;
3083 };
3084
3085 struct SSEOpHelper_eppi {
3086 SSEFunc_0_eppi op[2];
3087 uint32_t ext_mask;
3088 };
3089
3090 #define SSSE3_OP(x) { MMX_OP2(x), CPUID_EXT_SSSE3 }
3091 #define SSE41_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE41 }
3092 #define SSE42_OP(x) { { NULL, gen_helper_ ## x ## _xmm }, CPUID_EXT_SSE42 }
3093 #define SSE41_SPECIAL { { NULL, SSE_SPECIAL }, CPUID_EXT_SSE41 }
3094
3095 static const struct SSEOpHelper_epp sse_op_table6[256] = {
3096 [0x00] = SSSE3_OP(pshufb),
3097 [0x01] = SSSE3_OP(phaddw),
3098 [0x02] = SSSE3_OP(phaddd),
3099 [0x03] = SSSE3_OP(phaddsw),
3100 [0x04] = SSSE3_OP(pmaddubsw),
3101 [0x05] = SSSE3_OP(phsubw),
3102 [0x06] = SSSE3_OP(phsubd),
3103 [0x07] = SSSE3_OP(phsubsw),
3104 [0x08] = SSSE3_OP(psignb),
3105 [0x09] = SSSE3_OP(psignw),
3106 [0x0a] = SSSE3_OP(psignd),
3107 [0x0b] = SSSE3_OP(pmulhrsw),
3108 [0x10] = SSE41_OP(pblendvb),
3109 [0x14] = SSE41_OP(blendvps),
3110 [0x15] = SSE41_OP(blendvpd),
3111 [0x17] = SSE41_OP(ptest),
3112 [0x1c] = SSSE3_OP(pabsb),
3113 [0x1d] = SSSE3_OP(pabsw),
3114 [0x1e] = SSSE3_OP(pabsd),
3115 [0x20] = SSE41_OP(pmovsxbw),
3116 [0x21] = SSE41_OP(pmovsxbd),
3117 [0x22] = SSE41_OP(pmovsxbq),
3118 [0x23] = SSE41_OP(pmovsxwd),
3119 [0x24] = SSE41_OP(pmovsxwq),
3120 [0x25] = SSE41_OP(pmovsxdq),
3121 [0x28] = SSE41_OP(pmuldq),
3122 [0x29] = SSE41_OP(pcmpeqq),
3123 [0x2a] = SSE41_SPECIAL, /* movntqda */
3124 [0x2b] = SSE41_OP(packusdw),
3125 [0x30] = SSE41_OP(pmovzxbw),
3126 [0x31] = SSE41_OP(pmovzxbd),
3127 [0x32] = SSE41_OP(pmovzxbq),
3128 [0x33] = SSE41_OP(pmovzxwd),
3129 [0x34] = SSE41_OP(pmovzxwq),
3130 [0x35] = SSE41_OP(pmovzxdq),
3131 [0x37] = SSE42_OP(pcmpgtq),
3132 [0x38] = SSE41_OP(pminsb),
3133 [0x39] = SSE41_OP(pminsd),
3134 [0x3a] = SSE41_OP(pminuw),
3135 [0x3b] = SSE41_OP(pminud),
3136 [0x3c] = SSE41_OP(pmaxsb),
3137 [0x3d] = SSE41_OP(pmaxsd),
3138 [0x3e] = SSE41_OP(pmaxuw),
3139 [0x3f] = SSE41_OP(pmaxud),
3140 [0x40] = SSE41_OP(pmulld),
3141 [0x41] = SSE41_OP(phminposuw),
3142 };
3143
3144 static const struct SSEOpHelper_eppi sse_op_table7[256] = {
3145 [0x08] = SSE41_OP(roundps),
3146 [0x09] = SSE41_OP(roundpd),
3147 [0x0a] = SSE41_OP(roundss),
3148 [0x0b] = SSE41_OP(roundsd),
3149 [0x0c] = SSE41_OP(blendps),
3150 [0x0d] = SSE41_OP(blendpd),
3151 [0x0e] = SSE41_OP(pblendw),
3152 [0x0f] = SSSE3_OP(palignr),
3153 [0x14] = SSE41_SPECIAL, /* pextrb */
3154 [0x15] = SSE41_SPECIAL, /* pextrw */
3155 [0x16] = SSE41_SPECIAL, /* pextrd/pextrq */
3156 [0x17] = SSE41_SPECIAL, /* extractps */
3157 [0x20] = SSE41_SPECIAL, /* pinsrb */
3158 [0x21] = SSE41_SPECIAL, /* insertps */
3159 [0x22] = SSE41_SPECIAL, /* pinsrd/pinsrq */
3160 [0x40] = SSE41_OP(dpps),
3161 [0x41] = SSE41_OP(dppd),
3162 [0x42] = SSE41_OP(mpsadbw),
3163 [0x60] = SSE42_OP(pcmpestrm),
3164 [0x61] = SSE42_OP(pcmpestri),
3165 [0x62] = SSE42_OP(pcmpistrm),
3166 [0x63] = SSE42_OP(pcmpistri),
3167 };
3168
3169 static void gen_sse(DisasContext *s, int b, target_ulong pc_start, int rex_r)
3170 {
3171 int b1, op1_offset, op2_offset, is_xmm, val, ot;
3172 int modrm, mod, rm, reg, reg_addr, offset_addr;
3173 SSEFunc_0_epp sse_fn_epp;
3174 SSEFunc_0_eppi sse_fn_eppi;
3175 SSEFunc_0_ppi sse_fn_ppi;
3176 SSEFunc_0_eppt sse_fn_eppt;
3177
3178 b &= 0xff;
3179 if (s->prefix & PREFIX_DATA)
3180 b1 = 1;
3181 else if (s->prefix & PREFIX_REPZ)
3182 b1 = 2;
3183 else if (s->prefix & PREFIX_REPNZ)
3184 b1 = 3;
3185 else
3186 b1 = 0;
3187 sse_fn_epp = sse_op_table1[b][b1];
3188 if (!sse_fn_epp) {
3189 goto illegal_op;
3190 }
3191 if ((b <= 0x5f && b >= 0x10) || b == 0xc6 || b == 0xc2) {
3192 is_xmm = 1;
3193 } else {
3194 if (b1 == 0) {
3195 /* MMX case */
3196 is_xmm = 0;
3197 } else {
3198 is_xmm = 1;
3199 }
3200 }
3201 /* simple MMX/SSE operation */
3202 if (s->flags & HF_TS_MASK) {
3203 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
3204 return;
3205 }
3206 if (s->flags & HF_EM_MASK) {
3207 illegal_op:
3208 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
3209 return;
3210 }
3211 if (is_xmm && !(s->flags & HF_OSFXSR_MASK))
3212 if ((b != 0x38 && b != 0x3a) || (s->prefix & PREFIX_DATA))
3213 goto illegal_op;
3214 if (b == 0x0e) {
3215 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
3216 goto illegal_op;
3217 /* femms */
3218 gen_helper_emms(cpu_env);
3219 return;
3220 }
3221 if (b == 0x77) {
3222 /* emms */
3223 gen_helper_emms(cpu_env);
3224 return;
3225 }
3226 /* prepare MMX state (XXX: optimize by storing fptt and fptags in
3227 the static cpu state) */
3228 if (!is_xmm) {
3229 gen_helper_enter_mmx(cpu_env);
3230 }
3231
3232 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
3233 reg = ((modrm >> 3) & 7);
3234 if (is_xmm)
3235 reg |= rex_r;
3236 mod = (modrm >> 6) & 3;
3237 if (sse_fn_epp == SSE_SPECIAL) {
3238 b |= (b1 << 8);
3239 switch(b) {
3240 case 0x0e7: /* movntq */
3241 if (mod == 3)
3242 goto illegal_op;
3243 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3244 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3245 break;
3246 case 0x1e7: /* movntdq */
3247 case 0x02b: /* movntps */
3248 case 0x12b: /* movntps */
3249 if (mod == 3)
3250 goto illegal_op;
3251 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3252 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3253 break;
3254 case 0x3f0: /* lddqu */
3255 if (mod == 3)
3256 goto illegal_op;
3257 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3258 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3259 break;
3260 case 0x22b: /* movntss */
3261 case 0x32b: /* movntsd */
3262 if (mod == 3)
3263 goto illegal_op;
3264 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3265 if (b1 & 1) {
3266 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,
3267 xmm_regs[reg]));
3268 } else {
3269 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3270 xmm_regs[reg].XMM_L(0)));
3271 gen_op_st_T0_A0(OT_LONG + s->mem_index);
3272 }
3273 break;
3274 case 0x6e: /* movd mm, ea */
3275 #ifdef TARGET_X86_64
3276 if (s->dflag == 2) {
3277 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3278 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,fpregs[reg].mmx));
3279 } else
3280 #endif
3281 {
3282 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3283 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3284 offsetof(CPUX86State,fpregs[reg].mmx));
3285 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3286 gen_helper_movl_mm_T0_mmx(cpu_ptr0, cpu_tmp2_i32);
3287 }
3288 break;
3289 case 0x16e: /* movd xmm, ea */
3290 #ifdef TARGET_X86_64
3291 if (s->dflag == 2) {
3292 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 0);
3293 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3294 offsetof(CPUX86State,xmm_regs[reg]));
3295 gen_helper_movq_mm_T0_xmm(cpu_ptr0, cpu_T[0]);
3296 } else
3297 #endif
3298 {
3299 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 0);
3300 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3301 offsetof(CPUX86State,xmm_regs[reg]));
3302 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3303 gen_helper_movl_mm_T0_xmm(cpu_ptr0, cpu_tmp2_i32);
3304 }
3305 break;
3306 case 0x6f: /* movq mm, ea */
3307 if (mod != 3) {
3308 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3309 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3310 } else {
3311 rm = (modrm & 7);
3312 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3313 offsetof(CPUX86State,fpregs[rm].mmx));
3314 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
3315 offsetof(CPUX86State,fpregs[reg].mmx));
3316 }
3317 break;
3318 case 0x010: /* movups */
3319 case 0x110: /* movupd */
3320 case 0x028: /* movaps */
3321 case 0x128: /* movapd */
3322 case 0x16f: /* movdqa xmm, ea */
3323 case 0x26f: /* movdqu xmm, ea */
3324 if (mod != 3) {
3325 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3326 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3327 } else {
3328 rm = (modrm & 7) | REX_B(s);
3329 gen_op_movo(offsetof(CPUX86State,xmm_regs[reg]),
3330 offsetof(CPUX86State,xmm_regs[rm]));
3331 }
3332 break;
3333 case 0x210: /* movss xmm, ea */
3334 if (mod != 3) {
3335 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3336 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3337 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3338 gen_op_movl_T0_0();
3339 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3340 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3341 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3342 } else {
3343 rm = (modrm & 7) | REX_B(s);
3344 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3345 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3346 }
3347 break;
3348 case 0x310: /* movsd xmm, ea */
3349 if (mod != 3) {
3350 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3351 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3352 gen_op_movl_T0_0();
3353 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3354 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3355 } else {
3356 rm = (modrm & 7) | REX_B(s);
3357 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3358 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3359 }
3360 break;
3361 case 0x012: /* movlps */
3362 case 0x112: /* movlpd */
3363 if (mod != 3) {
3364 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3365 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3366 } else {
3367 /* movhlps */
3368 rm = (modrm & 7) | REX_B(s);
3369 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3370 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3371 }
3372 break;
3373 case 0x212: /* movsldup */
3374 if (mod != 3) {
3375 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3376 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3377 } else {
3378 rm = (modrm & 7) | REX_B(s);
3379 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3380 offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)));
3381 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3382 offsetof(CPUX86State,xmm_regs[rm].XMM_L(2)));
3383 }
3384 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3385 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3386 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3387 offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)));
3388 break;
3389 case 0x312: /* movddup */
3390 if (mod != 3) {
3391 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3392 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3393 } else {
3394 rm = (modrm & 7) | REX_B(s);
3395 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3396 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3397 }
3398 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3399 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3400 break;
3401 case 0x016: /* movhps */
3402 case 0x116: /* movhpd */
3403 if (mod != 3) {
3404 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3405 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3406 } else {
3407 /* movlhps */
3408 rm = (modrm & 7) | REX_B(s);
3409 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)),
3410 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3411 }
3412 break;
3413 case 0x216: /* movshdup */
3414 if (mod != 3) {
3415 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3416 gen_ldo_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3417 } else {
3418 rm = (modrm & 7) | REX_B(s);
3419 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)),
3420 offsetof(CPUX86State,xmm_regs[rm].XMM_L(1)));
3421 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)),
3422 offsetof(CPUX86State,xmm_regs[rm].XMM_L(3)));
3423 }
3424 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)),
3425 offsetof(CPUX86State,xmm_regs[reg].XMM_L(1)));
3426 gen_op_movl(offsetof(CPUX86State,xmm_regs[reg].XMM_L(2)),
3427 offsetof(CPUX86State,xmm_regs[reg].XMM_L(3)));
3428 break;
3429 case 0x178:
3430 case 0x378:
3431 {
3432 int bit_index, field_length;
3433
3434 if (b1 == 1 && reg != 0)
3435 goto illegal_op;
3436 field_length = cpu_ldub_code(cpu_single_env, s->pc++) & 0x3F;
3437 bit_index = cpu_ldub_code(cpu_single_env, s->pc++) & 0x3F;
3438 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3439 offsetof(CPUX86State,xmm_regs[reg]));
3440 if (b1 == 1)
3441 gen_helper_extrq_i(cpu_env, cpu_ptr0,
3442 tcg_const_i32(bit_index),
3443 tcg_const_i32(field_length));
3444 else
3445 gen_helper_insertq_i(cpu_env, cpu_ptr0,
3446 tcg_const_i32(bit_index),
3447 tcg_const_i32(field_length));
3448 }
3449 break;
3450 case 0x7e: /* movd ea, mm */
3451 #ifdef TARGET_X86_64
3452 if (s->dflag == 2) {
3453 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3454 offsetof(CPUX86State,fpregs[reg].mmx));
3455 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3456 } else
3457 #endif
3458 {
3459 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3460 offsetof(CPUX86State,fpregs[reg].mmx.MMX_L(0)));
3461 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3462 }
3463 break;
3464 case 0x17e: /* movd ea, xmm */
3465 #ifdef TARGET_X86_64
3466 if (s->dflag == 2) {
3467 tcg_gen_ld_i64(cpu_T[0], cpu_env,
3468 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3469 gen_ldst_modrm(s, modrm, OT_QUAD, OR_TMP0, 1);
3470 } else
3471 #endif
3472 {
3473 tcg_gen_ld32u_tl(cpu_T[0], cpu_env,
3474 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3475 gen_ldst_modrm(s, modrm, OT_LONG, OR_TMP0, 1);
3476 }
3477 break;
3478 case 0x27e: /* movq xmm, ea */
3479 if (mod != 3) {
3480 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3481 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3482 } else {
3483 rm = (modrm & 7) | REX_B(s);
3484 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3485 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3486 }
3487 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3488 break;
3489 case 0x7f: /* movq ea, mm */
3490 if (mod != 3) {
3491 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3492 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,fpregs[reg].mmx));
3493 } else {
3494 rm = (modrm & 7);
3495 gen_op_movq(offsetof(CPUX86State,fpregs[rm].mmx),
3496 offsetof(CPUX86State,fpregs[reg].mmx));
3497 }
3498 break;
3499 case 0x011: /* movups */
3500 case 0x111: /* movupd */
3501 case 0x029: /* movaps */
3502 case 0x129: /* movapd */
3503 case 0x17f: /* movdqa ea, xmm */
3504 case 0x27f: /* movdqu ea, xmm */
3505 if (mod != 3) {
3506 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3507 gen_sto_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg]));
3508 } else {
3509 rm = (modrm & 7) | REX_B(s);
3510 gen_op_movo(offsetof(CPUX86State,xmm_regs[rm]),
3511 offsetof(CPUX86State,xmm_regs[reg]));
3512 }
3513 break;
3514 case 0x211: /* movss ea, xmm */
3515 if (mod != 3) {
3516 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3517 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3518 gen_op_st_T0_A0(OT_LONG + s->mem_index);
3519 } else {
3520 rm = (modrm & 7) | REX_B(s);
3521 gen_op_movl(offsetof(CPUX86State,xmm_regs[rm].XMM_L(0)),
3522 offsetof(CPUX86State,xmm_regs[reg].XMM_L(0)));
3523 }
3524 break;
3525 case 0x311: /* movsd ea, xmm */
3526 if (mod != 3) {
3527 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3528 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3529 } else {
3530 rm = (modrm & 7) | REX_B(s);
3531 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3532 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3533 }
3534 break;
3535 case 0x013: /* movlps */
3536 case 0x113: /* movlpd */
3537 if (mod != 3) {
3538 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3539 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3540 } else {
3541 goto illegal_op;
3542 }
3543 break;
3544 case 0x017: /* movhps */
3545 case 0x117: /* movhpd */
3546 if (mod != 3) {
3547 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3548 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3549 } else {
3550 goto illegal_op;
3551 }
3552 break;
3553 case 0x71: /* shift mm, im */
3554 case 0x72:
3555 case 0x73:
3556 case 0x171: /* shift xmm, im */
3557 case 0x172:
3558 case 0x173:
3559 if (b1 >= 2) {
3560 goto illegal_op;
3561 }
3562 val = cpu_ldub_code(cpu_single_env, s->pc++);
3563 if (is_xmm) {
3564 gen_op_movl_T0_im(val);
3565 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3566 gen_op_movl_T0_0();
3567 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(1)));
3568 op1_offset = offsetof(CPUX86State,xmm_t0);
3569 } else {
3570 gen_op_movl_T0_im(val);
3571 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(0)));
3572 gen_op_movl_T0_0();
3573 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,mmx_t0.MMX_L(1)));
3574 op1_offset = offsetof(CPUX86State,mmx_t0);
3575 }
3576 sse_fn_epp = sse_op_table2[((b - 1) & 3) * 8 +
3577 (((modrm >> 3)) & 7)][b1];
3578 if (!sse_fn_epp) {
3579 goto illegal_op;
3580 }
3581 if (is_xmm) {
3582 rm = (modrm & 7) | REX_B(s);
3583 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3584 } else {
3585 rm = (modrm & 7);
3586 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3587 }
3588 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3589 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op1_offset);
3590 sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1);
3591 break;
3592 case 0x050: /* movmskps */
3593 rm = (modrm & 7) | REX_B(s);
3594 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3595 offsetof(CPUX86State,xmm_regs[rm]));
3596 gen_helper_movmskps(cpu_tmp2_i32, cpu_env, cpu_ptr0);
3597 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3598 gen_op_mov_reg_T0(OT_LONG, reg);
3599 break;
3600 case 0x150: /* movmskpd */
3601 rm = (modrm & 7) | REX_B(s);
3602 tcg_gen_addi_ptr(cpu_ptr0, cpu_env,
3603 offsetof(CPUX86State,xmm_regs[rm]));
3604 gen_helper_movmskpd(cpu_tmp2_i32, cpu_env, cpu_ptr0);
3605 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3606 gen_op_mov_reg_T0(OT_LONG, reg);
3607 break;
3608 case 0x02a: /* cvtpi2ps */
3609 case 0x12a: /* cvtpi2pd */
3610 gen_helper_enter_mmx(cpu_env);
3611 if (mod != 3) {
3612 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3613 op2_offset = offsetof(CPUX86State,mmx_t0);
3614 gen_ldq_env_A0(s->mem_index, op2_offset);
3615 } else {
3616 rm = (modrm & 7);
3617 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3618 }
3619 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3620 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3621 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3622 switch(b >> 8) {
3623 case 0x0:
3624 gen_helper_cvtpi2ps(cpu_env, cpu_ptr0, cpu_ptr1);
3625 break;
3626 default:
3627 case 0x1:
3628 gen_helper_cvtpi2pd(cpu_env, cpu_ptr0, cpu_ptr1);
3629 break;
3630 }
3631 break;
3632 case 0x22a: /* cvtsi2ss */
3633 case 0x32a: /* cvtsi2sd */
3634 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3635 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3636 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3637 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3638 if (ot == OT_LONG) {
3639 SSEFunc_0_epi sse_fn_epi = sse_op_table3ai[(b >> 8) & 1];
3640 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3641 sse_fn_epi(cpu_env, cpu_ptr0, cpu_tmp2_i32);
3642 } else {
3643 #ifdef TARGET_X86_64
3644 SSEFunc_0_epl sse_fn_epl = sse_op_table3aq[(b >> 8) & 1];
3645 sse_fn_epl(cpu_env, cpu_ptr0, cpu_T[0]);
3646 #else
3647 goto illegal_op;
3648 #endif
3649 }
3650 break;
3651 case 0x02c: /* cvttps2pi */
3652 case 0x12c: /* cvttpd2pi */
3653 case 0x02d: /* cvtps2pi */
3654 case 0x12d: /* cvtpd2pi */
3655 gen_helper_enter_mmx(cpu_env);
3656 if (mod != 3) {
3657 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3658 op2_offset = offsetof(CPUX86State,xmm_t0);
3659 gen_ldo_env_A0(s->mem_index, op2_offset);
3660 } else {
3661 rm = (modrm & 7) | REX_B(s);
3662 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3663 }
3664 op1_offset = offsetof(CPUX86State,fpregs[reg & 7].mmx);
3665 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3666 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3667 switch(b) {
3668 case 0x02c:
3669 gen_helper_cvttps2pi(cpu_env, cpu_ptr0, cpu_ptr1);
3670 break;
3671 case 0x12c:
3672 gen_helper_cvttpd2pi(cpu_env, cpu_ptr0, cpu_ptr1);
3673 break;
3674 case 0x02d:
3675 gen_helper_cvtps2pi(cpu_env, cpu_ptr0, cpu_ptr1);
3676 break;
3677 case 0x12d:
3678 gen_helper_cvtpd2pi(cpu_env, cpu_ptr0, cpu_ptr1);
3679 break;
3680 }
3681 break;
3682 case 0x22c: /* cvttss2si */
3683 case 0x32c: /* cvttsd2si */
3684 case 0x22d: /* cvtss2si */
3685 case 0x32d: /* cvtsd2si */
3686 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3687 if (mod != 3) {
3688 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3689 if ((b >> 8) & 1) {
3690 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_Q(0)));
3691 } else {
3692 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
3693 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
3694 }
3695 op2_offset = offsetof(CPUX86State,xmm_t0);
3696 } else {
3697 rm = (modrm & 7) | REX_B(s);
3698 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
3699 }
3700 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op2_offset);
3701 if (ot == OT_LONG) {
3702 SSEFunc_i_ep sse_fn_i_ep =
3703 sse_op_table3bi[((b >> 7) & 2) | (b & 1)];
3704 sse_fn_i_ep(cpu_tmp2_i32, cpu_env, cpu_ptr0);
3705 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3706 } else {
3707 #ifdef TARGET_X86_64
3708 SSEFunc_l_ep sse_fn_l_ep =
3709 sse_op_table3bq[((b >> 7) & 2) | (b & 1)];
3710 sse_fn_l_ep(cpu_T[0], cpu_env, cpu_ptr0);
3711 #else
3712 goto illegal_op;
3713 #endif
3714 }
3715 gen_op_mov_reg_T0(ot, reg);
3716 break;
3717 case 0xc4: /* pinsrw */
3718 case 0x1c4:
3719 s->rip_offset = 1;
3720 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
3721 val = cpu_ldub_code(cpu_single_env, s->pc++);
3722 if (b1) {
3723 val &= 7;
3724 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3725 offsetof(CPUX86State,xmm_regs[reg].XMM_W(val)));
3726 } else {
3727 val &= 3;
3728 tcg_gen_st16_tl(cpu_T[0], cpu_env,
3729 offsetof(CPUX86State,fpregs[reg].mmx.MMX_W(val)));
3730 }
3731 break;
3732 case 0xc5: /* pextrw */
3733 case 0x1c5:
3734 if (mod != 3)
3735 goto illegal_op;
3736 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3737 val = cpu_ldub_code(cpu_single_env, s->pc++);
3738 if (b1) {
3739 val &= 7;
3740 rm = (modrm & 7) | REX_B(s);
3741 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3742 offsetof(CPUX86State,xmm_regs[rm].XMM_W(val)));
3743 } else {
3744 val &= 3;
3745 rm = (modrm & 7);
3746 tcg_gen_ld16u_tl(cpu_T[0], cpu_env,
3747 offsetof(CPUX86State,fpregs[rm].mmx.MMX_W(val)));
3748 }
3749 reg = ((modrm >> 3) & 7) | rex_r;
3750 gen_op_mov_reg_T0(ot, reg);
3751 break;
3752 case 0x1d6: /* movq ea, xmm */
3753 if (mod != 3) {
3754 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3755 gen_stq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3756 } else {
3757 rm = (modrm & 7) | REX_B(s);
3758 gen_op_movq(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)),
3759 offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)));
3760 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[rm].XMM_Q(1)));
3761 }
3762 break;
3763 case 0x2d6: /* movq2dq */
3764 gen_helper_enter_mmx(cpu_env);
3765 rm = (modrm & 7);
3766 gen_op_movq(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(0)),
3767 offsetof(CPUX86State,fpregs[rm].mmx));
3768 gen_op_movq_env_0(offsetof(CPUX86State,xmm_regs[reg].XMM_Q(1)));
3769 break;
3770 case 0x3d6: /* movdq2q */
3771 gen_helper_enter_mmx(cpu_env);
3772 rm = (modrm & 7) | REX_B(s);
3773 gen_op_movq(offsetof(CPUX86State,fpregs[reg & 7].mmx),
3774 offsetof(CPUX86State,xmm_regs[rm].XMM_Q(0)));
3775 break;
3776 case 0xd7: /* pmovmskb */
3777 case 0x1d7:
3778 if (mod != 3)
3779 goto illegal_op;
3780 if (b1) {
3781 rm = (modrm & 7) | REX_B(s);
3782 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,xmm_regs[rm]));
3783 gen_helper_pmovmskb_xmm(cpu_tmp2_i32, cpu_env, cpu_ptr0);
3784 } else {
3785 rm = (modrm & 7);
3786 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, offsetof(CPUX86State,fpregs[rm].mmx));
3787 gen_helper_pmovmskb_mmx(cpu_tmp2_i32, cpu_env, cpu_ptr0);
3788 }
3789 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3790 reg = ((modrm >> 3) & 7) | rex_r;
3791 gen_op_mov_reg_T0(OT_LONG, reg);
3792 break;
3793 case 0x138:
3794 if (s->prefix & PREFIX_REPNZ)
3795 goto crc32;
3796 case 0x038:
3797 b = modrm;
3798 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
3799 rm = modrm & 7;
3800 reg = ((modrm >> 3) & 7) | rex_r;
3801 mod = (modrm >> 6) & 3;
3802 if (b1 >= 2) {
3803 goto illegal_op;
3804 }
3805
3806 sse_fn_epp = sse_op_table6[b].op[b1];
3807 if (!sse_fn_epp) {
3808 goto illegal_op;
3809 }
3810 if (!(s->cpuid_ext_features & sse_op_table6[b].ext_mask))
3811 goto illegal_op;
3812
3813 if (b1) {
3814 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
3815 if (mod == 3) {
3816 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
3817 } else {
3818 op2_offset = offsetof(CPUX86State,xmm_t0);
3819 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3820 switch (b) {
3821 case 0x20: case 0x30: /* pmovsxbw, pmovzxbw */
3822 case 0x23: case 0x33: /* pmovsxwd, pmovzxwd */
3823 case 0x25: case 0x35: /* pmovsxdq, pmovzxdq */
3824 gen_ldq_env_A0(s->mem_index, op2_offset +
3825 offsetof(XMMReg, XMM_Q(0)));
3826 break;
3827 case 0x21: case 0x31: /* pmovsxbd, pmovzxbd */
3828 case 0x24: case 0x34: /* pmovsxwq, pmovzxwq */
3829 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3830 (s->mem_index >> 2) - 1);
3831 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3832 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, op2_offset +
3833 offsetof(XMMReg, XMM_L(0)));
3834 break;
3835 case 0x22: case 0x32: /* pmovsxbq, pmovzxbq */
3836 tcg_gen_qemu_ld16u(cpu_tmp0, cpu_A0,
3837 (s->mem_index >> 2) - 1);
3838 tcg_gen_st16_tl(cpu_tmp0, cpu_env, op2_offset +
3839 offsetof(XMMReg, XMM_W(0)));
3840 break;
3841 case 0x2a: /* movntqda */
3842 gen_ldo_env_A0(s->mem_index, op1_offset);
3843 return;
3844 default:
3845 gen_ldo_env_A0(s->mem_index, op2_offset);
3846 }
3847 }
3848 } else {
3849 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
3850 if (mod == 3) {
3851 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
3852 } else {
3853 op2_offset = offsetof(CPUX86State,mmx_t0);
3854 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3855 gen_ldq_env_A0(s->mem_index, op2_offset);
3856 }
3857 }
3858 if (sse_fn_epp == SSE_SPECIAL) {
3859 goto illegal_op;
3860 }
3861
3862 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
3863 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
3864 sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1);
3865
3866 if (b == 0x17)
3867 s->cc_op = CC_OP_EFLAGS;
3868 break;
3869 case 0x338: /* crc32 */
3870 crc32:
3871 b = modrm;
3872 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
3873 reg = ((modrm >> 3) & 7) | rex_r;
3874
3875 if (b != 0xf0 && b != 0xf1)
3876 goto illegal_op;
3877 if (!(s->cpuid_ext_features & CPUID_EXT_SSE42))
3878 goto illegal_op;
3879
3880 if (b == 0xf0)
3881 ot = OT_BYTE;
3882 else if (b == 0xf1 && s->dflag != 2)
3883 if (s->prefix & PREFIX_DATA)
3884 ot = OT_WORD;
3885 else
3886 ot = OT_LONG;
3887 else
3888 ot = OT_QUAD;
3889
3890 gen_op_mov_TN_reg(OT_LONG, 0, reg);
3891 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
3892 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
3893 gen_helper_crc32(cpu_T[0], cpu_tmp2_i32,
3894 cpu_T[0], tcg_const_i32(8 << ot));
3895
3896 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3897 gen_op_mov_reg_T0(ot, reg);
3898 break;
3899 case 0x03a:
3900 case 0x13a:
3901 b = modrm;
3902 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
3903 rm = modrm & 7;
3904 reg = ((modrm >> 3) & 7) | rex_r;
3905 mod = (modrm >> 6) & 3;
3906 if (b1 >= 2) {
3907 goto illegal_op;
3908 }
3909
3910 sse_fn_eppi = sse_op_table7[b].op[b1];
3911 if (!sse_fn_eppi) {
3912 goto illegal_op;
3913 }
3914 if (!(s->cpuid_ext_features & sse_op_table7[b].ext_mask))
3915 goto illegal_op;
3916
3917 if (sse_fn_eppi == SSE_SPECIAL) {
3918 ot = (s->dflag == 2) ? OT_QUAD : OT_LONG;
3919 rm = (modrm & 7) | REX_B(s);
3920 if (mod != 3)
3921 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
3922 reg = ((modrm >> 3) & 7) | rex_r;
3923 val = cpu_ldub_code(cpu_single_env, s->pc++);
3924 switch (b) {
3925 case 0x14: /* pextrb */
3926 tcg_gen_ld8u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3927 xmm_regs[reg].XMM_B(val & 15)));
3928 if (mod == 3)
3929 gen_op_mov_reg_T0(ot, rm);
3930 else
3931 tcg_gen_qemu_st8(cpu_T[0], cpu_A0,
3932 (s->mem_index >> 2) - 1);
3933 break;
3934 case 0x15: /* pextrw */
3935 tcg_gen_ld16u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3936 xmm_regs[reg].XMM_W(val & 7)));
3937 if (mod == 3)
3938 gen_op_mov_reg_T0(ot, rm);
3939 else
3940 tcg_gen_qemu_st16(cpu_T[0], cpu_A0,
3941 (s->mem_index >> 2) - 1);
3942 break;
3943 case 0x16:
3944 if (ot == OT_LONG) { /* pextrd */
3945 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
3946 offsetof(CPUX86State,
3947 xmm_regs[reg].XMM_L(val & 3)));
3948 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
3949 if (mod == 3)
3950 gen_op_mov_reg_v(ot, rm, cpu_T[0]);
3951 else
3952 tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
3953 (s->mem_index >> 2) - 1);
3954 } else { /* pextrq */
3955 #ifdef TARGET_X86_64
3956 tcg_gen_ld_i64(cpu_tmp1_i64, cpu_env,
3957 offsetof(CPUX86State,
3958 xmm_regs[reg].XMM_Q(val & 1)));
3959 if (mod == 3)
3960 gen_op_mov_reg_v(ot, rm, cpu_tmp1_i64);
3961 else
3962 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
3963 (s->mem_index >> 2) - 1);
3964 #else
3965 goto illegal_op;
3966 #endif
3967 }
3968 break;
3969 case 0x17: /* extractps */
3970 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,
3971 xmm_regs[reg].XMM_L(val & 3)));
3972 if (mod == 3)
3973 gen_op_mov_reg_T0(ot, rm);
3974 else
3975 tcg_gen_qemu_st32(cpu_T[0], cpu_A0,
3976 (s->mem_index >> 2) - 1);
3977 break;
3978 case 0x20: /* pinsrb */
3979 if (mod == 3)
3980 gen_op_mov_TN_reg(OT_LONG, 0, rm);
3981 else
3982 tcg_gen_qemu_ld8u(cpu_tmp0, cpu_A0,
3983 (s->mem_index >> 2) - 1);
3984 tcg_gen_st8_tl(cpu_tmp0, cpu_env, offsetof(CPUX86State,
3985 xmm_regs[reg].XMM_B(val & 15)));
3986 break;
3987 case 0x21: /* insertps */
3988 if (mod == 3) {
3989 tcg_gen_ld_i32(cpu_tmp2_i32, cpu_env,
3990 offsetof(CPUX86State,xmm_regs[rm]
3991 .XMM_L((val >> 6) & 3)));
3992 } else {
3993 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
3994 (s->mem_index >> 2) - 1);
3995 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
3996 }
3997 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
3998 offsetof(CPUX86State,xmm_regs[reg]
3999 .XMM_L((val >> 4) & 3)));
4000 if ((val >> 0) & 1)
4001 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4002 cpu_env, offsetof(CPUX86State,
4003 xmm_regs[reg].XMM_L(0)));
4004 if ((val >> 1) & 1)
4005 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4006 cpu_env, offsetof(CPUX86State,
4007 xmm_regs[reg].XMM_L(1)));
4008 if ((val >> 2) & 1)
4009 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4010 cpu_env, offsetof(CPUX86State,
4011 xmm_regs[reg].XMM_L(2)));
4012 if ((val >> 3) & 1)
4013 tcg_gen_st_i32(tcg_const_i32(0 /*float32_zero*/),
4014 cpu_env, offsetof(CPUX86State,
4015 xmm_regs[reg].XMM_L(3)));
4016 break;
4017 case 0x22:
4018 if (ot == OT_LONG) { /* pinsrd */
4019 if (mod == 3)
4020 gen_op_mov_v_reg(ot, cpu_tmp0, rm);
4021 else
4022 tcg_gen_qemu_ld32u(cpu_tmp0, cpu_A0,
4023 (s->mem_index >> 2) - 1);
4024 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_tmp0);
4025 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env,
4026 offsetof(CPUX86State,
4027 xmm_regs[reg].XMM_L(val & 3)));
4028 } else { /* pinsrq */
4029 #ifdef TARGET_X86_64
4030 if (mod == 3)
4031 gen_op_mov_v_reg(ot, cpu_tmp1_i64, rm);
4032 else
4033 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
4034 (s->mem_index >> 2) - 1);
4035 tcg_gen_st_i64(cpu_tmp1_i64, cpu_env,
4036 offsetof(CPUX86State,
4037 xmm_regs[reg].XMM_Q(val & 1)));
4038 #else
4039 goto illegal_op;
4040 #endif
4041 }
4042 break;
4043 }
4044 return;
4045 }
4046
4047 if (b1) {
4048 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
4049 if (mod == 3) {
4050 op2_offset = offsetof(CPUX86State,xmm_regs[rm | REX_B(s)]);
4051 } else {
4052 op2_offset = offsetof(CPUX86State,xmm_t0);
4053 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4054 gen_ldo_env_A0(s->mem_index, op2_offset);
4055 }
4056 } else {
4057 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
4058 if (mod == 3) {
4059 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
4060 } else {
4061 op2_offset = offsetof(CPUX86State,mmx_t0);
4062 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4063 gen_ldq_env_A0(s->mem_index, op2_offset);
4064 }
4065 }
4066 val = cpu_ldub_code(cpu_single_env, s->pc++);
4067
4068 if ((b & 0xfc) == 0x60) { /* pcmpXstrX */
4069 s->cc_op = CC_OP_EFLAGS;
4070
4071 if (s->dflag == 2)
4072 /* The helper must use entire 64-bit gp registers */
4073 val |= 1 << 8;
4074 }
4075
4076 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4077 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4078 sse_fn_eppi(cpu_env, cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
4079 break;
4080 default:
4081 goto illegal_op;
4082 }
4083 } else {
4084 /* generic MMX or SSE operation */
4085 switch(b) {
4086 case 0x70: /* pshufx insn */
4087 case 0xc6: /* pshufx insn */
4088 case 0xc2: /* compare insns */
4089 s->rip_offset = 1;
4090 break;
4091 default:
4092 break;
4093 }
4094 if (is_xmm) {
4095 op1_offset = offsetof(CPUX86State,xmm_regs[reg]);
4096 if (mod != 3) {
4097 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4098 op2_offset = offsetof(CPUX86State,xmm_t0);
4099 if (b1 >= 2 && ((b >= 0x50 && b <= 0x5f && b != 0x5b) ||
4100 b == 0xc2)) {
4101 /* specific case for SSE single instructions */
4102 if (b1 == 2) {
4103 /* 32 bit access */
4104 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
4105 tcg_gen_st32_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,xmm_t0.XMM_L(0)));
4106 } else {
4107 /* 64 bit access */
4108 gen_ldq_env_A0(s->mem_index, offsetof(CPUX86State,xmm_t0.XMM_D(0)));
4109 }
4110 } else {
4111 gen_ldo_env_A0(s->mem_index, op2_offset);
4112 }
4113 } else {
4114 rm = (modrm & 7) | REX_B(s);
4115 op2_offset = offsetof(CPUX86State,xmm_regs[rm]);
4116 }
4117 } else {
4118 op1_offset = offsetof(CPUX86State,fpregs[reg].mmx);
4119 if (mod != 3) {
4120 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4121 op2_offset = offsetof(CPUX86State,mmx_t0);
4122 gen_ldq_env_A0(s->mem_index, op2_offset);
4123 } else {
4124 rm = (modrm & 7);
4125 op2_offset = offsetof(CPUX86State,fpregs[rm].mmx);
4126 }
4127 }
4128 switch(b) {
4129 case 0x0f: /* 3DNow! data insns */
4130 if (!(s->cpuid_ext2_features & CPUID_EXT2_3DNOW))
4131 goto illegal_op;
4132 val = cpu_ldub_code(cpu_single_env, s->pc++);
4133 sse_fn_epp = sse_op_table5[val];
4134 if (!sse_fn_epp) {
4135 goto illegal_op;
4136 }
4137 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4138 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4139 sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1);
4140 break;
4141 case 0x70: /* pshufx insn */
4142 case 0xc6: /* pshufx insn */
4143 val = cpu_ldub_code(cpu_single_env, s->pc++);
4144 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4145 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4146 /* XXX: introduce a new table? */
4147 sse_fn_ppi = (SSEFunc_0_ppi)sse_fn_epp;
4148 sse_fn_ppi(cpu_ptr0, cpu_ptr1, tcg_const_i32(val));
4149 break;
4150 case 0xc2:
4151 /* compare insns */
4152 val = cpu_ldub_code(cpu_single_env, s->pc++);
4153 if (val >= 8)
4154 goto illegal_op;
4155 sse_fn_epp = sse_op_table4[val][b1];
4156
4157 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4158 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4159 sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1);
4160 break;
4161 case 0xf7:
4162 /* maskmov : we must prepare A0 */
4163 if (mod != 3)
4164 goto illegal_op;
4165 #ifdef TARGET_X86_64
4166 if (s->aflag == 2) {
4167 gen_op_movq_A0_reg(R_EDI);
4168 } else
4169 #endif
4170 {
4171 gen_op_movl_A0_reg(R_EDI);
4172 if (s->aflag == 0)
4173 gen_op_andl_A0_ffff();
4174 }
4175 gen_add_A0_ds_seg(s);
4176
4177 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4178 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4179 /* XXX: introduce a new table? */
4180 sse_fn_eppt = (SSEFunc_0_eppt)sse_fn_epp;
4181 sse_fn_eppt(cpu_env, cpu_ptr0, cpu_ptr1, cpu_A0);
4182 break;
4183 default:
4184 tcg_gen_addi_ptr(cpu_ptr0, cpu_env, op1_offset);
4185 tcg_gen_addi_ptr(cpu_ptr1, cpu_env, op2_offset);
4186 sse_fn_epp(cpu_env, cpu_ptr0, cpu_ptr1);
4187 break;
4188 }
4189 if (b == 0x2e || b == 0x2f) {
4190 s->cc_op = CC_OP_EFLAGS;
4191 }
4192 }
4193 }
4194
4195 /* convert one instruction. s->is_jmp is set if the translation must
4196 be stopped. Return the next pc value */
4197 static target_ulong disas_insn(DisasContext *s, target_ulong pc_start)
4198 {
4199 int b, prefixes, aflag, dflag;
4200 int shift, ot;
4201 int modrm, reg, rm, mod, reg_addr, op, opreg, offset_addr, val;
4202 target_ulong next_eip, tval;
4203 int rex_w, rex_r;
4204
4205 if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP)))
4206 tcg_gen_debug_insn_start(pc_start);
4207 s->pc = pc_start;
4208 prefixes = 0;
4209 aflag = s->code32;
4210 dflag = s->code32;
4211 s->override = -1;
4212 rex_w = -1;
4213 rex_r = 0;
4214 #ifdef TARGET_X86_64
4215 s->rex_x = 0;
4216 s->rex_b = 0;
4217 x86_64_hregs = 0;
4218 #endif
4219 s->rip_offset = 0; /* for relative ip address */
4220 next_byte:
4221 b = cpu_ldub_code(cpu_single_env, s->pc);
4222 s->pc++;
4223 /* check prefixes */
4224 #ifdef TARGET_X86_64
4225 if (CODE64(s)) {
4226 switch (b) {
4227 case 0xf3:
4228 prefixes |= PREFIX_REPZ;
4229 goto next_byte;
4230 case 0xf2:
4231 prefixes |= PREFIX_REPNZ;
4232 goto next_byte;
4233 case 0xf0:
4234 prefixes |= PREFIX_LOCK;
4235 goto next_byte;
4236 case 0x2e:
4237 s->override = R_CS;
4238 goto next_byte;
4239 case 0x36:
4240 s->override = R_SS;
4241 goto next_byte;
4242 case 0x3e:
4243 s->override = R_DS;
4244 goto next_byte;
4245 case 0x26:
4246 s->override = R_ES;
4247 goto next_byte;
4248 case 0x64:
4249 s->override = R_FS;
4250 goto next_byte;
4251 case 0x65:
4252 s->override = R_GS;
4253 goto next_byte;
4254 case 0x66:
4255 prefixes |= PREFIX_DATA;
4256 goto next_byte;
4257 case 0x67:
4258 prefixes |= PREFIX_ADR;
4259 goto next_byte;
4260 case 0x40 ... 0x4f:
4261 /* REX prefix */
4262 rex_w = (b >> 3) & 1;
4263 rex_r = (b & 0x4) << 1;
4264 s->rex_x = (b & 0x2) << 2;
4265 REX_B(s) = (b & 0x1) << 3;
4266 x86_64_hregs = 1; /* select uniform byte register addressing */
4267 goto next_byte;
4268 }
4269 if (rex_w == 1) {
4270 /* 0x66 is ignored if rex.w is set */
4271 dflag = 2;
4272 } else {
4273 if (prefixes & PREFIX_DATA)
4274 dflag ^= 1;
4275 }
4276 if (!(prefixes & PREFIX_ADR))
4277 aflag = 2;
4278 } else
4279 #endif
4280 {
4281 switch (b) {
4282 case 0xf3:
4283 prefixes |= PREFIX_REPZ;
4284 goto next_byte;
4285 case 0xf2:
4286 prefixes |= PREFIX_REPNZ;
4287 goto next_byte;
4288 case 0xf0:
4289 prefixes |= PREFIX_LOCK;
4290 goto next_byte;
4291 case 0x2e:
4292 s->override = R_CS;
4293 goto next_byte;
4294 case 0x36:
4295 s->override = R_SS;
4296 goto next_byte;
4297 case 0x3e:
4298 s->override = R_DS;
4299 goto next_byte;
4300 case 0x26:
4301 s->override = R_ES;
4302 goto next_byte;
4303 case 0x64:
4304 s->override = R_FS;
4305 goto next_byte;
4306 case 0x65:
4307 s->override = R_GS;
4308 goto next_byte;
4309 case 0x66:
4310 prefixes |= PREFIX_DATA;
4311 goto next_byte;
4312 case 0x67:
4313 prefixes |= PREFIX_ADR;
4314 goto next_byte;
4315 }
4316 if (prefixes & PREFIX_DATA)
4317 dflag ^= 1;
4318 if (prefixes & PREFIX_ADR)
4319 aflag ^= 1;
4320 }
4321
4322 s->prefix = prefixes;
4323 s->aflag = aflag;
4324 s->dflag = dflag;
4325
4326 /* lock generation */
4327 if (prefixes & PREFIX_LOCK)
4328 gen_helper_lock();
4329
4330 /* now check op code */
4331 reswitch:
4332 switch(b) {
4333 case 0x0f:
4334 /**************************/
4335 /* extended op code */
4336 b = cpu_ldub_code(cpu_single_env, s->pc++) | 0x100;
4337 goto reswitch;
4338
4339 /**************************/
4340 /* arith & logic */
4341 case 0x00 ... 0x05:
4342 case 0x08 ... 0x0d:
4343 case 0x10 ... 0x15:
4344 case 0x18 ... 0x1d:
4345 case 0x20 ... 0x25:
4346 case 0x28 ... 0x2d:
4347 case 0x30 ... 0x35:
4348 case 0x38 ... 0x3d:
4349 {
4350 int op, f, val;
4351 op = (b >> 3) & 7;
4352 f = (b >> 1) & 3;
4353
4354 if ((b & 1) == 0)
4355 ot = OT_BYTE;
4356 else
4357 ot = dflag + OT_WORD;
4358
4359 switch(f) {
4360 case 0: /* OP Ev, Gv */
4361 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
4362 reg = ((modrm >> 3) & 7) | rex_r;
4363 mod = (modrm >> 6) & 3;
4364 rm = (modrm & 7) | REX_B(s);
4365 if (mod != 3) {
4366 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4367 opreg = OR_TMP0;
4368 } else if (op == OP_XORL && rm == reg) {
4369 xor_zero:
4370 /* xor reg, reg optimisation */
4371 gen_op_movl_T0_0();
4372 s->cc_op = CC_OP_LOGICB + ot;
4373 gen_op_mov_reg_T0(ot, reg);
4374 gen_op_update1_cc();
4375 break;
4376 } else {
4377 opreg = rm;
4378 }
4379 gen_op_mov_TN_reg(ot, 1, reg);
4380 gen_op(s, op, ot, opreg);
4381 break;
4382 case 1: /* OP Gv, Ev */
4383 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
4384 mod = (modrm >> 6) & 3;
4385 reg = ((modrm >> 3) & 7) | rex_r;
4386 rm = (modrm & 7) | REX_B(s);
4387 if (mod != 3) {
4388 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4389 gen_op_ld_T1_A0(ot + s->mem_index);
4390 } else if (op == OP_XORL && rm == reg) {
4391 goto xor_zero;
4392 } else {
4393 gen_op_mov_TN_reg(ot, 1, rm);
4394 }
4395 gen_op(s, op, ot, reg);
4396 break;
4397 case 2: /* OP A, Iv */
4398 val = insn_get(s, ot);
4399 gen_op_movl_T1_im(val);
4400 gen_op(s, op, ot, OR_EAX);
4401 break;
4402 }
4403 }
4404 break;
4405
4406 case 0x82:
4407 if (CODE64(s))
4408 goto illegal_op;
4409 case 0x80: /* GRP1 */
4410 case 0x81:
4411 case 0x83:
4412 {
4413 int val;
4414
4415 if ((b & 1) == 0)
4416 ot = OT_BYTE;
4417 else
4418 ot = dflag + OT_WORD;
4419
4420 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
4421 mod = (modrm >> 6) & 3;
4422 rm = (modrm & 7) | REX_B(s);
4423 op = (modrm >> 3) & 7;
4424
4425 if (mod != 3) {
4426 if (b == 0x83)
4427 s->rip_offset = 1;
4428 else
4429 s->rip_offset = insn_const_size(ot);
4430 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4431 opreg = OR_TMP0;
4432 } else {
4433 opreg = rm;
4434 }
4435
4436 switch(b) {
4437 default:
4438 case 0x80:
4439 case 0x81:
4440 case 0x82:
4441 val = insn_get(s, ot);
4442 break;
4443 case 0x83:
4444 val = (int8_t)insn_get(s, OT_BYTE);
4445 break;
4446 }
4447 gen_op_movl_T1_im(val);
4448 gen_op(s, op, ot, opreg);
4449 }
4450 break;
4451
4452 /**************************/
4453 /* inc, dec, and other misc arith */
4454 case 0x40 ... 0x47: /* inc Gv */
4455 ot = dflag ? OT_LONG : OT_WORD;
4456 gen_inc(s, ot, OR_EAX + (b & 7), 1);
4457 break;
4458 case 0x48 ... 0x4f: /* dec Gv */
4459 ot = dflag ? OT_LONG : OT_WORD;
4460 gen_inc(s, ot, OR_EAX + (b & 7), -1);
4461 break;
4462 case 0xf6: /* GRP3 */
4463 case 0xf7:
4464 if ((b & 1) == 0)
4465 ot = OT_BYTE;
4466 else
4467 ot = dflag + OT_WORD;
4468
4469 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
4470 mod = (modrm >> 6) & 3;
4471 rm = (modrm & 7) | REX_B(s);
4472 op = (modrm >> 3) & 7;
4473 if (mod != 3) {
4474 if (op == 0)
4475 s->rip_offset = insn_const_size(ot);
4476 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4477 gen_op_ld_T0_A0(ot + s->mem_index);
4478 } else {
4479 gen_op_mov_TN_reg(ot, 0, rm);
4480 }
4481
4482 switch(op) {
4483 case 0: /* test */
4484 val = insn_get(s, ot);
4485 gen_op_movl_T1_im(val);
4486 gen_op_testl_T0_T1_cc();
4487 s->cc_op = CC_OP_LOGICB + ot;
4488 break;
4489 case 2: /* not */
4490 tcg_gen_not_tl(cpu_T[0], cpu_T[0]);
4491 if (mod != 3) {
4492 gen_op_st_T0_A0(ot + s->mem_index);
4493 } else {
4494 gen_op_mov_reg_T0(ot, rm);
4495 }
4496 break;
4497 case 3: /* neg */
4498 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
4499 if (mod != 3) {
4500 gen_op_st_T0_A0(ot + s->mem_index);
4501 } else {
4502 gen_op_mov_reg_T0(ot, rm);
4503 }
4504 gen_op_update_neg_cc();
4505 s->cc_op = CC_OP_SUBB + ot;
4506 break;
4507 case 4: /* mul */
4508 switch(ot) {
4509 case OT_BYTE:
4510 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4511 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
4512 tcg_gen_ext8u_tl(cpu_T[1], cpu_T[1]);
4513 /* XXX: use 32 bit mul which could be faster */
4514 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4515 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4516 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4517 tcg_gen_andi_tl(cpu_cc_src, cpu_T[0], 0xff00);
4518 s->cc_op = CC_OP_MULB;
4519 break;
4520 case OT_WORD:
4521 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4522 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
4523 tcg_gen_ext16u_tl(cpu_T[1], cpu_T[1]);
4524 /* XXX: use 32 bit mul which could be faster */
4525 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4526 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4527 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4528 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4529 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4530 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4531 s->cc_op = CC_OP_MULW;
4532 break;
4533 default:
4534 case OT_LONG:
4535 #ifdef TARGET_X86_64
4536 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4537 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
4538 tcg_gen_ext32u_tl(cpu_T[1], cpu_T[1]);
4539 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4540 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4541 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4542 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4543 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4544 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4545 #else
4546 {
4547 TCGv_i64 t0, t1;
4548 t0 = tcg_temp_new_i64();
4549 t1 = tcg_temp_new_i64();
4550 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4551 tcg_gen_extu_i32_i64(t0, cpu_T[0]);
4552 tcg_gen_extu_i32_i64(t1, cpu_T[1]);
4553 tcg_gen_mul_i64(t0, t0, t1);
4554 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4555 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4556 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4557 tcg_gen_shri_i64(t0, t0, 32);
4558 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4559 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4560 tcg_gen_mov_tl(cpu_cc_src, cpu_T[0]);
4561 }
4562 #endif
4563 s->cc_op = CC_OP_MULL;
4564 break;
4565 #ifdef TARGET_X86_64
4566 case OT_QUAD:
4567 gen_helper_mulq_EAX_T0(cpu_env, cpu_T[0]);
4568 s->cc_op = CC_OP_MULQ;
4569 break;
4570 #endif
4571 }
4572 break;
4573 case 5: /* imul */
4574 switch(ot) {
4575 case OT_BYTE:
4576 gen_op_mov_TN_reg(OT_BYTE, 1, R_EAX);
4577 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4578 tcg_gen_ext8s_tl(cpu_T[1], cpu_T[1]);
4579 /* XXX: use 32 bit mul which could be faster */
4580 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4581 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4582 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4583 tcg_gen_ext8s_tl(cpu_tmp0, cpu_T[0]);
4584 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4585 s->cc_op = CC_OP_MULB;
4586 break;
4587 case OT_WORD:
4588 gen_op_mov_TN_reg(OT_WORD, 1, R_EAX);
4589 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4590 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4591 /* XXX: use 32 bit mul which could be faster */
4592 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4593 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4594 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4595 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4596 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4597 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 16);
4598 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4599 s->cc_op = CC_OP_MULW;
4600 break;
4601 default:
4602 case OT_LONG:
4603 #ifdef TARGET_X86_64
4604 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4605 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4606 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4607 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4608 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4609 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4610 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4611 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4612 tcg_gen_shri_tl(cpu_T[0], cpu_T[0], 32);
4613 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4614 #else
4615 {
4616 TCGv_i64 t0, t1;
4617 t0 = tcg_temp_new_i64();
4618 t1 = tcg_temp_new_i64();
4619 gen_op_mov_TN_reg(OT_LONG, 1, R_EAX);
4620 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4621 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4622 tcg_gen_mul_i64(t0, t0, t1);
4623 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4624 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4625 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4626 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4627 tcg_gen_shri_i64(t0, t0, 32);
4628 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4629 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4630 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4631 }
4632 #endif
4633 s->cc_op = CC_OP_MULL;
4634 break;
4635 #ifdef TARGET_X86_64
4636 case OT_QUAD:
4637 gen_helper_imulq_EAX_T0(cpu_env, cpu_T[0]);
4638 s->cc_op = CC_OP_MULQ;
4639 break;
4640 #endif
4641 }
4642 break;
4643 case 6: /* div */
4644 switch(ot) {
4645 case OT_BYTE:
4646 gen_jmp_im(pc_start - s->cs_base);
4647 gen_helper_divb_AL(cpu_env, cpu_T[0]);
4648 break;
4649 case OT_WORD:
4650 gen_jmp_im(pc_start - s->cs_base);
4651 gen_helper_divw_AX(cpu_env, cpu_T[0]);
4652 break;
4653 default:
4654 case OT_LONG:
4655 gen_jmp_im(pc_start - s->cs_base);
4656 gen_helper_divl_EAX(cpu_env, cpu_T[0]);
4657 break;
4658 #ifdef TARGET_X86_64
4659 case OT_QUAD:
4660 gen_jmp_im(pc_start - s->cs_base);
4661 gen_helper_divq_EAX(cpu_env, cpu_T[0]);
4662 break;
4663 #endif
4664 }
4665 break;
4666 case 7: /* idiv */
4667 switch(ot) {
4668 case OT_BYTE:
4669 gen_jmp_im(pc_start - s->cs_base);
4670 gen_helper_idivb_AL(cpu_env, cpu_T[0]);
4671 break;
4672 case OT_WORD:
4673 gen_jmp_im(pc_start - s->cs_base);
4674 gen_helper_idivw_AX(cpu_env, cpu_T[0]);
4675 break;
4676 default:
4677 case OT_LONG:
4678 gen_jmp_im(pc_start - s->cs_base);
4679 gen_helper_idivl_EAX(cpu_env, cpu_T[0]);
4680 break;
4681 #ifdef TARGET_X86_64
4682 case OT_QUAD:
4683 gen_jmp_im(pc_start - s->cs_base);
4684 gen_helper_idivq_EAX(cpu_env, cpu_T[0]);
4685 break;
4686 #endif
4687 }
4688 break;
4689 default:
4690 goto illegal_op;
4691 }
4692 break;
4693
4694 case 0xfe: /* GRP4 */
4695 case 0xff: /* GRP5 */
4696 if ((b & 1) == 0)
4697 ot = OT_BYTE;
4698 else
4699 ot = dflag + OT_WORD;
4700
4701 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
4702 mod = (modrm >> 6) & 3;
4703 rm = (modrm & 7) | REX_B(s);
4704 op = (modrm >> 3) & 7;
4705 if (op >= 2 && b == 0xfe) {
4706 goto illegal_op;
4707 }
4708 if (CODE64(s)) {
4709 if (op == 2 || op == 4) {
4710 /* operand size for jumps is 64 bit */
4711 ot = OT_QUAD;
4712 } else if (op == 3 || op == 5) {
4713 ot = dflag ? OT_LONG + (rex_w == 1) : OT_WORD;
4714 } else if (op == 6) {
4715 /* default push size is 64 bit */
4716 ot = dflag ? OT_QUAD : OT_WORD;
4717 }
4718 }
4719 if (mod != 3) {
4720 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4721 if (op >= 2 && op != 3 && op != 5)
4722 gen_op_ld_T0_A0(ot + s->mem_index);
4723 } else {
4724 gen_op_mov_TN_reg(ot, 0, rm);
4725 }
4726
4727 switch(op) {
4728 case 0: /* inc Ev */
4729 if (mod != 3)
4730 opreg = OR_TMP0;
4731 else
4732 opreg = rm;
4733 gen_inc(s, ot, opreg, 1);
4734 break;
4735 case 1: /* dec Ev */
4736 if (mod != 3)
4737 opreg = OR_TMP0;
4738 else
4739 opreg = rm;
4740 gen_inc(s, ot, opreg, -1);
4741 break;
4742 case 2: /* call Ev */
4743 /* XXX: optimize if memory (no 'and' is necessary) */
4744 if (s->dflag == 0)
4745 gen_op_andl_T0_ffff();
4746 next_eip = s->pc - s->cs_base;
4747 gen_movtl_T1_im(next_eip);
4748 gen_push_T1(s);
4749 gen_op_jmp_T0();
4750 gen_eob(s);
4751 break;
4752 case 3: /* lcall Ev */
4753 gen_op_ld_T1_A0(ot + s->mem_index);
4754 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4755 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4756 do_lcall:
4757 if (s->pe && !s->vm86) {
4758 if (s->cc_op != CC_OP_DYNAMIC)
4759 gen_op_set_cc_op(s->cc_op);
4760 gen_jmp_im(pc_start - s->cs_base);
4761 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4762 gen_helper_lcall_protected(cpu_env, cpu_tmp2_i32, cpu_T[1],
4763 tcg_const_i32(dflag),
4764 tcg_const_i32(s->pc - pc_start));
4765 } else {
4766 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4767 gen_helper_lcall_real(cpu_env, cpu_tmp2_i32, cpu_T[1],
4768 tcg_const_i32(dflag),
4769 tcg_const_i32(s->pc - s->cs_base));
4770 }
4771 gen_eob(s);
4772 break;
4773 case 4: /* jmp Ev */
4774 if (s->dflag == 0)
4775 gen_op_andl_T0_ffff();
4776 gen_op_jmp_T0();
4777 gen_eob(s);
4778 break;
4779 case 5: /* ljmp Ev */
4780 gen_op_ld_T1_A0(ot + s->mem_index);
4781 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
4782 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
4783 do_ljmp:
4784 if (s->pe && !s->vm86) {
4785 if (s->cc_op != CC_OP_DYNAMIC)
4786 gen_op_set_cc_op(s->cc_op);
4787 gen_jmp_im(pc_start - s->cs_base);
4788 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
4789 gen_helper_ljmp_protected(cpu_env, cpu_tmp2_i32, cpu_T[1],
4790 tcg_const_i32(s->pc - pc_start));
4791 } else {
4792 gen_op_movl_seg_T0_vm(R_CS);
4793 gen_op_movl_T0_T1();
4794 gen_op_jmp_T0();
4795 }
4796 gen_eob(s);
4797 break;
4798 case 6: /* push Ev */
4799 gen_push_T0(s);
4800 break;
4801 default:
4802 goto illegal_op;
4803 }
4804 break;
4805
4806 case 0x84: /* test Ev, Gv */
4807 case 0x85:
4808 if ((b & 1) == 0)
4809 ot = OT_BYTE;
4810 else
4811 ot = dflag + OT_WORD;
4812
4813 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
4814 reg = ((modrm >> 3) & 7) | rex_r;
4815
4816 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4817 gen_op_mov_TN_reg(ot, 1, reg);
4818 gen_op_testl_T0_T1_cc();
4819 s->cc_op = CC_OP_LOGICB + ot;
4820 break;
4821
4822 case 0xa8: /* test eAX, Iv */
4823 case 0xa9:
4824 if ((b & 1) == 0)
4825 ot = OT_BYTE;
4826 else
4827 ot = dflag + OT_WORD;
4828 val = insn_get(s, ot);
4829
4830 gen_op_mov_TN_reg(ot, 0, OR_EAX);
4831 gen_op_movl_T1_im(val);
4832 gen_op_testl_T0_T1_cc();
4833 s->cc_op = CC_OP_LOGICB + ot;
4834 break;
4835
4836 case 0x98: /* CWDE/CBW */
4837 #ifdef TARGET_X86_64
4838 if (dflag == 2) {
4839 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4840 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4841 gen_op_mov_reg_T0(OT_QUAD, R_EAX);
4842 } else
4843 #endif
4844 if (dflag == 1) {
4845 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4846 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4847 gen_op_mov_reg_T0(OT_LONG, R_EAX);
4848 } else {
4849 gen_op_mov_TN_reg(OT_BYTE, 0, R_EAX);
4850 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
4851 gen_op_mov_reg_T0(OT_WORD, R_EAX);
4852 }
4853 break;
4854 case 0x99: /* CDQ/CWD */
4855 #ifdef TARGET_X86_64
4856 if (dflag == 2) {
4857 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
4858 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 63);
4859 gen_op_mov_reg_T0(OT_QUAD, R_EDX);
4860 } else
4861 #endif
4862 if (dflag == 1) {
4863 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
4864 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4865 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 31);
4866 gen_op_mov_reg_T0(OT_LONG, R_EDX);
4867 } else {
4868 gen_op_mov_TN_reg(OT_WORD, 0, R_EAX);
4869 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4870 tcg_gen_sari_tl(cpu_T[0], cpu_T[0], 15);
4871 gen_op_mov_reg_T0(OT_WORD, R_EDX);
4872 }
4873 break;
4874 case 0x1af: /* imul Gv, Ev */
4875 case 0x69: /* imul Gv, Ev, I */
4876 case 0x6b:
4877 ot = dflag + OT_WORD;
4878 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
4879 reg = ((modrm >> 3) & 7) | rex_r;
4880 if (b == 0x69)
4881 s->rip_offset = insn_const_size(ot);
4882 else if (b == 0x6b)
4883 s->rip_offset = 1;
4884 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
4885 if (b == 0x69) {
4886 val = insn_get(s, ot);
4887 gen_op_movl_T1_im(val);
4888 } else if (b == 0x6b) {
4889 val = (int8_t)insn_get(s, OT_BYTE);
4890 gen_op_movl_T1_im(val);
4891 } else {
4892 gen_op_mov_TN_reg(ot, 1, reg);
4893 }
4894
4895 #ifdef TARGET_X86_64
4896 if (ot == OT_QUAD) {
4897 gen_helper_imulq_T0_T1(cpu_T[0], cpu_env, cpu_T[0], cpu_T[1]);
4898 } else
4899 #endif
4900 if (ot == OT_LONG) {
4901 #ifdef TARGET_X86_64
4902 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
4903 tcg_gen_ext32s_tl(cpu_T[1], cpu_T[1]);
4904 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4905 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4906 tcg_gen_ext32s_tl(cpu_tmp0, cpu_T[0]);
4907 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4908 #else
4909 {
4910 TCGv_i64 t0, t1;
4911 t0 = tcg_temp_new_i64();
4912 t1 = tcg_temp_new_i64();
4913 tcg_gen_ext_i32_i64(t0, cpu_T[0]);
4914 tcg_gen_ext_i32_i64(t1, cpu_T[1]);
4915 tcg_gen_mul_i64(t0, t0, t1);
4916 tcg_gen_trunc_i64_i32(cpu_T[0], t0);
4917 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4918 tcg_gen_sari_tl(cpu_tmp0, cpu_T[0], 31);
4919 tcg_gen_shri_i64(t0, t0, 32);
4920 tcg_gen_trunc_i64_i32(cpu_T[1], t0);
4921 tcg_gen_sub_tl(cpu_cc_src, cpu_T[1], cpu_tmp0);
4922 }
4923 #endif
4924 } else {
4925 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
4926 tcg_gen_ext16s_tl(cpu_T[1], cpu_T[1]);
4927 /* XXX: use 32 bit mul which could be faster */
4928 tcg_gen_mul_tl(cpu_T[0], cpu_T[0], cpu_T[1]);
4929 tcg_gen_mov_tl(cpu_cc_dst, cpu_T[0]);
4930 tcg_gen_ext16s_tl(cpu_tmp0, cpu_T[0]);
4931 tcg_gen_sub_tl(cpu_cc_src, cpu_T[0], cpu_tmp0);
4932 }
4933 gen_op_mov_reg_T0(ot, reg);
4934 s->cc_op = CC_OP_MULB + ot;
4935 break;
4936 case 0x1c0:
4937 case 0x1c1: /* xadd Ev, Gv */
4938 if ((b & 1) == 0)
4939 ot = OT_BYTE;
4940 else
4941 ot = dflag + OT_WORD;
4942 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
4943 reg = ((modrm >> 3) & 7) | rex_r;
4944 mod = (modrm >> 6) & 3;
4945 if (mod == 3) {
4946 rm = (modrm & 7) | REX_B(s);
4947 gen_op_mov_TN_reg(ot, 0, reg);
4948 gen_op_mov_TN_reg(ot, 1, rm);
4949 gen_op_addl_T0_T1();
4950 gen_op_mov_reg_T1(ot, reg);
4951 gen_op_mov_reg_T0(ot, rm);
4952 } else {
4953 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4954 gen_op_mov_TN_reg(ot, 0, reg);
4955 gen_op_ld_T1_A0(ot + s->mem_index);
4956 gen_op_addl_T0_T1();
4957 gen_op_st_T0_A0(ot + s->mem_index);
4958 gen_op_mov_reg_T1(ot, reg);
4959 }
4960 gen_op_update2_cc();
4961 s->cc_op = CC_OP_ADDB + ot;
4962 break;
4963 case 0x1b0:
4964 case 0x1b1: /* cmpxchg Ev, Gv */
4965 {
4966 int label1, label2;
4967 TCGv t0, t1, t2, a0;
4968
4969 if ((b & 1) == 0)
4970 ot = OT_BYTE;
4971 else
4972 ot = dflag + OT_WORD;
4973 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
4974 reg = ((modrm >> 3) & 7) | rex_r;
4975 mod = (modrm >> 6) & 3;
4976 t0 = tcg_temp_local_new();
4977 t1 = tcg_temp_local_new();
4978 t2 = tcg_temp_local_new();
4979 a0 = tcg_temp_local_new();
4980 gen_op_mov_v_reg(ot, t1, reg);
4981 if (mod == 3) {
4982 rm = (modrm & 7) | REX_B(s);
4983 gen_op_mov_v_reg(ot, t0, rm);
4984 } else {
4985 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
4986 tcg_gen_mov_tl(a0, cpu_A0);
4987 gen_op_ld_v(ot + s->mem_index, t0, a0);
4988 rm = 0; /* avoid warning */
4989 }
4990 label1 = gen_new_label();
4991 tcg_gen_sub_tl(t2, cpu_regs[R_EAX], t0);
4992 gen_extu(ot, t2);
4993 tcg_gen_brcondi_tl(TCG_COND_EQ, t2, 0, label1);
4994 label2 = gen_new_label();
4995 if (mod == 3) {
4996 gen_op_mov_reg_v(ot, R_EAX, t0);
4997 tcg_gen_br(label2);
4998 gen_set_label(label1);
4999 gen_op_mov_reg_v(ot, rm, t1);
5000 } else {
5001 /* perform no-op store cycle like physical cpu; must be
5002 before changing accumulator to ensure idempotency if
5003 the store faults and the instruction is restarted */
5004 gen_op_st_v(ot + s->mem_index, t0, a0);
5005 gen_op_mov_reg_v(ot, R_EAX, t0);
5006 tcg_gen_br(label2);
5007 gen_set_label(label1);
5008 gen_op_st_v(ot + s->mem_index, t1, a0);
5009 }
5010 gen_set_label(label2);
5011 tcg_gen_mov_tl(cpu_cc_src, t0);
5012 tcg_gen_mov_tl(cpu_cc_dst, t2);
5013 s->cc_op = CC_OP_SUBB + ot;
5014 tcg_temp_free(t0);
5015 tcg_temp_free(t1);
5016 tcg_temp_free(t2);
5017 tcg_temp_free(a0);
5018 }
5019 break;
5020 case 0x1c7: /* cmpxchg8b */
5021 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
5022 mod = (modrm >> 6) & 3;
5023 if ((mod == 3) || ((modrm & 0x38) != 0x8))
5024 goto illegal_op;
5025 #ifdef TARGET_X86_64
5026 if (dflag == 2) {
5027 if (!(s->cpuid_ext_features & CPUID_EXT_CX16))
5028 goto illegal_op;
5029 gen_jmp_im(pc_start - s->cs_base);
5030 if (s->cc_op != CC_OP_DYNAMIC)
5031 gen_op_set_cc_op(s->cc_op);
5032 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5033 gen_helper_cmpxchg16b(cpu_env, cpu_A0);
5034 } else
5035 #endif
5036 {
5037 if (!(s->cpuid_features & CPUID_CX8))
5038 goto illegal_op;
5039 gen_jmp_im(pc_start - s->cs_base);
5040 if (s->cc_op != CC_OP_DYNAMIC)
5041 gen_op_set_cc_op(s->cc_op);
5042 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5043 gen_helper_cmpxchg8b(cpu_env, cpu_A0);
5044 }
5045 s->cc_op = CC_OP_EFLAGS;
5046 break;
5047
5048 /**************************/
5049 /* push/pop */
5050 case 0x50 ... 0x57: /* push */
5051 gen_op_mov_TN_reg(OT_LONG, 0, (b & 7) | REX_B(s));
5052 gen_push_T0(s);
5053 break;
5054 case 0x58 ... 0x5f: /* pop */
5055 if (CODE64(s)) {
5056 ot = dflag ? OT_QUAD : OT_WORD;
5057 } else {
5058 ot = dflag + OT_WORD;
5059 }
5060 gen_pop_T0(s);
5061 /* NOTE: order is important for pop %sp */
5062 gen_pop_update(s);
5063 gen_op_mov_reg_T0(ot, (b & 7) | REX_B(s));
5064 break;
5065 case 0x60: /* pusha */
5066 if (CODE64(s))
5067 goto illegal_op;
5068 gen_pusha(s);
5069 break;
5070 case 0x61: /* popa */
5071 if (CODE64(s))
5072 goto illegal_op;
5073 gen_popa(s);
5074 break;
5075 case 0x68: /* push Iv */
5076 case 0x6a:
5077 if (CODE64(s)) {
5078 ot = dflag ? OT_QUAD : OT_WORD;
5079 } else {
5080 ot = dflag + OT_WORD;
5081 }
5082 if (b == 0x68)
5083 val = insn_get(s, ot);
5084 else
5085 val = (int8_t)insn_get(s, OT_BYTE);
5086 gen_op_movl_T0_im(val);
5087 gen_push_T0(s);
5088 break;
5089 case 0x8f: /* pop Ev */
5090 if (CODE64(s)) {
5091 ot = dflag ? OT_QUAD : OT_WORD;
5092 } else {
5093 ot = dflag + OT_WORD;
5094 }
5095 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
5096 mod = (modrm >> 6) & 3;
5097 gen_pop_T0(s);
5098 if (mod == 3) {
5099 /* NOTE: order is important for pop %sp */
5100 gen_pop_update(s);
5101 rm = (modrm & 7) | REX_B(s);
5102 gen_op_mov_reg_T0(ot, rm);
5103 } else {
5104 /* NOTE: order is important too for MMU exceptions */
5105 s->popl_esp_hack = 1 << ot;
5106 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
5107 s->popl_esp_hack = 0;
5108 gen_pop_update(s);
5109 }
5110 break;
5111 case 0xc8: /* enter */
5112 {
5113 int level;
5114 val = cpu_lduw_code(cpu_single_env, s->pc);
5115 s->pc += 2;
5116 level = cpu_ldub_code(cpu_single_env, s->pc++);
5117 gen_enter(s, val, level);
5118 }
5119 break;
5120 case 0xc9: /* leave */
5121 /* XXX: exception not precise (ESP is updated before potential exception) */
5122 if (CODE64(s)) {
5123 gen_op_mov_TN_reg(OT_QUAD, 0, R_EBP);
5124 gen_op_mov_reg_T0(OT_QUAD, R_ESP);
5125 } else if (s->ss32) {
5126 gen_op_mov_TN_reg(OT_LONG, 0, R_EBP);
5127 gen_op_mov_reg_T0(OT_LONG, R_ESP);
5128 } else {
5129 gen_op_mov_TN_reg(OT_WORD, 0, R_EBP);
5130 gen_op_mov_reg_T0(OT_WORD, R_ESP);
5131 }
5132 gen_pop_T0(s);
5133 if (CODE64(s)) {
5134 ot = dflag ? OT_QUAD : OT_WORD;
5135 } else {
5136 ot = dflag + OT_WORD;
5137 }
5138 gen_op_mov_reg_T0(ot, R_EBP);
5139 gen_pop_update(s);
5140 break;
5141 case 0x06: /* push es */
5142 case 0x0e: /* push cs */
5143 case 0x16: /* push ss */
5144 case 0x1e: /* push ds */
5145 if (CODE64(s))
5146 goto illegal_op;
5147 gen_op_movl_T0_seg(b >> 3);
5148 gen_push_T0(s);
5149 break;
5150 case 0x1a0: /* push fs */
5151 case 0x1a8: /* push gs */
5152 gen_op_movl_T0_seg((b >> 3) & 7);
5153 gen_push_T0(s);
5154 break;
5155 case 0x07: /* pop es */
5156 case 0x17: /* pop ss */
5157 case 0x1f: /* pop ds */
5158 if (CODE64(s))
5159 goto illegal_op;
5160 reg = b >> 3;
5161 gen_pop_T0(s);
5162 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5163 gen_pop_update(s);
5164 if (reg == R_SS) {
5165 /* if reg == SS, inhibit interrupts/trace. */
5166 /* If several instructions disable interrupts, only the
5167 _first_ does it */
5168 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
5169 gen_helper_set_inhibit_irq(cpu_env);
5170 s->tf = 0;
5171 }
5172 if (s->is_jmp) {
5173 gen_jmp_im(s->pc - s->cs_base);
5174 gen_eob(s);
5175 }
5176 break;
5177 case 0x1a1: /* pop fs */
5178 case 0x1a9: /* pop gs */
5179 gen_pop_T0(s);
5180 gen_movl_seg_T0(s, (b >> 3) & 7, pc_start - s->cs_base);
5181 gen_pop_update(s);
5182 if (s->is_jmp) {
5183 gen_jmp_im(s->pc - s->cs_base);
5184 gen_eob(s);
5185 }
5186 break;
5187
5188 /**************************/
5189 /* mov */
5190 case 0x88:
5191 case 0x89: /* mov Gv, Ev */
5192 if ((b & 1) == 0)
5193 ot = OT_BYTE;
5194 else
5195 ot = dflag + OT_WORD;
5196 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
5197 reg = ((modrm >> 3) & 7) | rex_r;
5198
5199 /* generate a generic store */
5200 gen_ldst_modrm(s, modrm, ot, reg, 1);
5201 break;
5202 case 0xc6:
5203 case 0xc7: /* mov Ev, Iv */
5204 if ((b & 1) == 0)
5205 ot = OT_BYTE;
5206 else
5207 ot = dflag + OT_WORD;
5208 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
5209 mod = (modrm >> 6) & 3;
5210 if (mod != 3) {
5211 s->rip_offset = insn_const_size(ot);
5212 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5213 }
5214 val = insn_get(s, ot);
5215 gen_op_movl_T0_im(val);
5216 if (mod != 3)
5217 gen_op_st_T0_A0(ot + s->mem_index);
5218 else
5219 gen_op_mov_reg_T0(ot, (modrm & 7) | REX_B(s));
5220 break;
5221 case 0x8a:
5222 case 0x8b: /* mov Ev, Gv */
5223 if ((b & 1) == 0)
5224 ot = OT_BYTE;
5225 else
5226 ot = OT_WORD + dflag;
5227 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
5228 reg = ((modrm >> 3) & 7) | rex_r;
5229
5230 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
5231 gen_op_mov_reg_T0(ot, reg);
5232 break;
5233 case 0x8e: /* mov seg, Gv */
5234 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
5235 reg = (modrm >> 3) & 7;
5236 if (reg >= 6 || reg == R_CS)
5237 goto illegal_op;
5238 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
5239 gen_movl_seg_T0(s, reg, pc_start - s->cs_base);
5240 if (reg == R_SS) {
5241 /* if reg == SS, inhibit interrupts/trace */
5242 /* If several instructions disable interrupts, only the
5243 _first_ does it */
5244 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
5245 gen_helper_set_inhibit_irq(cpu_env);
5246 s->tf = 0;
5247 }
5248 if (s->is_jmp) {
5249 gen_jmp_im(s->pc - s->cs_base);
5250 gen_eob(s);
5251 }
5252 break;
5253 case 0x8c: /* mov Gv, seg */
5254 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
5255 reg = (modrm >> 3) & 7;
5256 mod = (modrm >> 6) & 3;
5257 if (reg >= 6)
5258 goto illegal_op;
5259 gen_op_movl_T0_seg(reg);
5260 if (mod == 3)
5261 ot = OT_WORD + dflag;
5262 else
5263 ot = OT_WORD;
5264 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
5265 break;
5266
5267 case 0x1b6: /* movzbS Gv, Eb */
5268 case 0x1b7: /* movzwS Gv, Eb */
5269 case 0x1be: /* movsbS Gv, Eb */
5270 case 0x1bf: /* movswS Gv, Eb */
5271 {
5272 int d_ot;
5273 /* d_ot is the size of destination */
5274 d_ot = dflag + OT_WORD;
5275 /* ot is the size of source */
5276 ot = (b & 1) + OT_BYTE;
5277 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
5278 reg = ((modrm >> 3) & 7) | rex_r;
5279 mod = (modrm >> 6) & 3;
5280 rm = (modrm & 7) | REX_B(s);
5281
5282 if (mod == 3) {
5283 gen_op_mov_TN_reg(ot, 0, rm);
5284 switch(ot | (b & 8)) {
5285 case OT_BYTE:
5286 tcg_gen_ext8u_tl(cpu_T[0], cpu_T[0]);
5287 break;
5288 case OT_BYTE | 8:
5289 tcg_gen_ext8s_tl(cpu_T[0], cpu_T[0]);
5290 break;
5291 case OT_WORD:
5292 tcg_gen_ext16u_tl(cpu_T[0], cpu_T[0]);
5293 break;
5294 default:
5295 case OT_WORD | 8:
5296 tcg_gen_ext16s_tl(cpu_T[0], cpu_T[0]);
5297 break;
5298 }
5299 gen_op_mov_reg_T0(d_ot, reg);
5300 } else {
5301 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5302 if (b & 8) {
5303 gen_op_lds_T0_A0(ot + s->mem_index);
5304 } else {
5305 gen_op_ldu_T0_A0(ot + s->mem_index);
5306 }
5307 gen_op_mov_reg_T0(d_ot, reg);
5308 }
5309 }
5310 break;
5311
5312 case 0x8d: /* lea */
5313 ot = dflag + OT_WORD;
5314 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
5315 mod = (modrm >> 6) & 3;
5316 if (mod == 3)
5317 goto illegal_op;
5318 reg = ((modrm >> 3) & 7) | rex_r;
5319 /* we must ensure that no segment is added */
5320 s->override = -1;
5321 val = s->addseg;
5322 s->addseg = 0;
5323 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5324 s->addseg = val;
5325 gen_op_mov_reg_A0(ot - OT_WORD, reg);
5326 break;
5327
5328 case 0xa0: /* mov EAX, Ov */
5329 case 0xa1:
5330 case 0xa2: /* mov Ov, EAX */
5331 case 0xa3:
5332 {
5333 target_ulong offset_addr;
5334
5335 if ((b & 1) == 0)
5336 ot = OT_BYTE;
5337 else
5338 ot = dflag + OT_WORD;
5339 #ifdef TARGET_X86_64
5340 if (s->aflag == 2) {
5341 offset_addr = cpu_ldq_code(cpu_single_env, s->pc);
5342 s->pc += 8;
5343 gen_op_movq_A0_im(offset_addr);
5344 } else
5345 #endif
5346 {
5347 if (s->aflag) {
5348 offset_addr = insn_get(s, OT_LONG);
5349 } else {
5350 offset_addr = insn_get(s, OT_WORD);
5351 }
5352 gen_op_movl_A0_im(offset_addr);
5353 }
5354 gen_add_A0_ds_seg(s);
5355 if ((b & 2) == 0) {
5356 gen_op_ld_T0_A0(ot + s->mem_index);
5357 gen_op_mov_reg_T0(ot, R_EAX);
5358 } else {
5359 gen_op_mov_TN_reg(ot, 0, R_EAX);
5360 gen_op_st_T0_A0(ot + s->mem_index);
5361 }
5362 }
5363 break;
5364 case 0xd7: /* xlat */
5365 #ifdef TARGET_X86_64
5366 if (s->aflag == 2) {
5367 gen_op_movq_A0_reg(R_EBX);
5368 gen_op_mov_TN_reg(OT_QUAD, 0, R_EAX);
5369 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
5370 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
5371 } else
5372 #endif
5373 {
5374 gen_op_movl_A0_reg(R_EBX);
5375 gen_op_mov_TN_reg(OT_LONG, 0, R_EAX);
5376 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], 0xff);
5377 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_T[0]);
5378 if (s->aflag == 0)
5379 gen_op_andl_A0_ffff();
5380 else
5381 tcg_gen_andi_tl(cpu_A0, cpu_A0, 0xffffffff);
5382 }
5383 gen_add_A0_ds_seg(s);
5384 gen_op_ldu_T0_A0(OT_BYTE + s->mem_index);
5385 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
5386 break;
5387 case 0xb0 ... 0xb7: /* mov R, Ib */
5388 val = insn_get(s, OT_BYTE);
5389 gen_op_movl_T0_im(val);
5390 gen_op_mov_reg_T0(OT_BYTE, (b & 7) | REX_B(s));
5391 break;
5392 case 0xb8 ... 0xbf: /* mov R, Iv */
5393 #ifdef TARGET_X86_64
5394 if (dflag == 2) {
5395 uint64_t tmp;
5396 /* 64 bit case */
5397 tmp = cpu_ldq_code(cpu_single_env, s->pc);
5398 s->pc += 8;
5399 reg = (b & 7) | REX_B(s);
5400 gen_movtl_T0_im(tmp);
5401 gen_op_mov_reg_T0(OT_QUAD, reg);
5402 } else
5403 #endif
5404 {
5405 ot = dflag ? OT_LONG : OT_WORD;
5406 val = insn_get(s, ot);
5407 reg = (b & 7) | REX_B(s);
5408 gen_op_movl_T0_im(val);
5409 gen_op_mov_reg_T0(ot, reg);
5410 }
5411 break;
5412
5413 case 0x91 ... 0x97: /* xchg R, EAX */
5414 do_xchg_reg_eax:
5415 ot = dflag + OT_WORD;
5416 reg = (b & 7) | REX_B(s);
5417 rm = R_EAX;
5418 goto do_xchg_reg;
5419 case 0x86:
5420 case 0x87: /* xchg Ev, Gv */
5421 if ((b & 1) == 0)
5422 ot = OT_BYTE;
5423 else
5424 ot = dflag + OT_WORD;
5425 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
5426 reg = ((modrm >> 3) & 7) | rex_r;
5427 mod = (modrm >> 6) & 3;
5428 if (mod == 3) {
5429 rm = (modrm & 7) | REX_B(s);
5430 do_xchg_reg:
5431 gen_op_mov_TN_reg(ot, 0, reg);
5432 gen_op_mov_TN_reg(ot, 1, rm);
5433 gen_op_mov_reg_T0(ot, rm);
5434 gen_op_mov_reg_T1(ot, reg);
5435 } else {
5436 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5437 gen_op_mov_TN_reg(ot, 0, reg);
5438 /* for xchg, lock is implicit */
5439 if (!(prefixes & PREFIX_LOCK))
5440 gen_helper_lock();
5441 gen_op_ld_T1_A0(ot + s->mem_index);
5442 gen_op_st_T0_A0(ot + s->mem_index);
5443 if (!(prefixes & PREFIX_LOCK))
5444 gen_helper_unlock();
5445 gen_op_mov_reg_T1(ot, reg);
5446 }
5447 break;
5448 case 0xc4: /* les Gv */
5449 if (CODE64(s))
5450 goto illegal_op;
5451 op = R_ES;
5452 goto do_lxx;
5453 case 0xc5: /* lds Gv */
5454 if (CODE64(s))
5455 goto illegal_op;
5456 op = R_DS;
5457 goto do_lxx;
5458 case 0x1b2: /* lss Gv */
5459 op = R_SS;
5460 goto do_lxx;
5461 case 0x1b4: /* lfs Gv */
5462 op = R_FS;
5463 goto do_lxx;
5464 case 0x1b5: /* lgs Gv */
5465 op = R_GS;
5466 do_lxx:
5467 ot = dflag ? OT_LONG : OT_WORD;
5468 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
5469 reg = ((modrm >> 3) & 7) | rex_r;
5470 mod = (modrm >> 6) & 3;
5471 if (mod == 3)
5472 goto illegal_op;
5473 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5474 gen_op_ld_T1_A0(ot + s->mem_index);
5475 gen_add_A0_im(s, 1 << (ot - OT_WORD + 1));
5476 /* load the segment first to handle exceptions properly */
5477 gen_op_ldu_T0_A0(OT_WORD + s->mem_index);
5478 gen_movl_seg_T0(s, op, pc_start - s->cs_base);
5479 /* then put the data */
5480 gen_op_mov_reg_T1(ot, reg);
5481 if (s->is_jmp) {
5482 gen_jmp_im(s->pc - s->cs_base);
5483 gen_eob(s);
5484 }
5485 break;
5486
5487 /************************/
5488 /* shifts */
5489 case 0xc0:
5490 case 0xc1:
5491 /* shift Ev,Ib */
5492 shift = 2;
5493 grp2:
5494 {
5495 if ((b & 1) == 0)
5496 ot = OT_BYTE;
5497 else
5498 ot = dflag + OT_WORD;
5499
5500 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
5501 mod = (modrm >> 6) & 3;
5502 op = (modrm >> 3) & 7;
5503
5504 if (mod != 3) {
5505 if (shift == 2) {
5506 s->rip_offset = 1;
5507 }
5508 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5509 opreg = OR_TMP0;
5510 } else {
5511 opreg = (modrm & 7) | REX_B(s);
5512 }
5513
5514 /* simpler op */
5515 if (shift == 0) {
5516 gen_shift(s, op, ot, opreg, OR_ECX);
5517 } else {
5518 if (shift == 2) {
5519 shift = cpu_ldub_code(cpu_single_env, s->pc++);
5520 }
5521 gen_shifti(s, op, ot, opreg, shift);
5522 }
5523 }
5524 break;
5525 case 0xd0:
5526 case 0xd1:
5527 /* shift Ev,1 */
5528 shift = 1;
5529 goto grp2;
5530 case 0xd2:
5531 case 0xd3:
5532 /* shift Ev,cl */
5533 shift = 0;
5534 goto grp2;
5535
5536 case 0x1a4: /* shld imm */
5537 op = 0;
5538 shift = 1;
5539 goto do_shiftd;
5540 case 0x1a5: /* shld cl */
5541 op = 0;
5542 shift = 0;
5543 goto do_shiftd;
5544 case 0x1ac: /* shrd imm */
5545 op = 1;
5546 shift = 1;
5547 goto do_shiftd;
5548 case 0x1ad: /* shrd cl */
5549 op = 1;
5550 shift = 0;
5551 do_shiftd:
5552 ot = dflag + OT_WORD;
5553 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
5554 mod = (modrm >> 6) & 3;
5555 rm = (modrm & 7) | REX_B(s);
5556 reg = ((modrm >> 3) & 7) | rex_r;
5557 if (mod != 3) {
5558 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5559 opreg = OR_TMP0;
5560 } else {
5561 opreg = rm;
5562 }
5563 gen_op_mov_TN_reg(ot, 1, reg);
5564
5565 if (shift) {
5566 val = cpu_ldub_code(cpu_single_env, s->pc++);
5567 tcg_gen_movi_tl(cpu_T3, val);
5568 } else {
5569 tcg_gen_mov_tl(cpu_T3, cpu_regs[R_ECX]);
5570 }
5571 gen_shiftd_rm_T1_T3(s, ot, opreg, op);
5572 break;
5573
5574 /************************/
5575 /* floats */
5576 case 0xd8 ... 0xdf:
5577 if (s->flags & (HF_EM_MASK | HF_TS_MASK)) {
5578 /* if CR0.EM or CR0.TS are set, generate an FPU exception */
5579 /* XXX: what to do if illegal op ? */
5580 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
5581 break;
5582 }
5583 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
5584 mod = (modrm >> 6) & 3;
5585 rm = modrm & 7;
5586 op = ((b & 7) << 3) | ((modrm >> 3) & 7);
5587 if (mod != 3) {
5588 /* memory op */
5589 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
5590 switch(op) {
5591 case 0x00 ... 0x07: /* fxxxs */
5592 case 0x10 ... 0x17: /* fixxxl */
5593 case 0x20 ... 0x27: /* fxxxl */
5594 case 0x30 ... 0x37: /* fixxx */
5595 {
5596 int op1;
5597 op1 = op & 7;
5598
5599 switch(op >> 4) {
5600 case 0:
5601 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5602 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5603 gen_helper_flds_FT0(cpu_env, cpu_tmp2_i32);
5604 break;
5605 case 1:
5606 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5607 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5608 gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
5609 break;
5610 case 2:
5611 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5612 (s->mem_index >> 2) - 1);
5613 gen_helper_fldl_FT0(cpu_env, cpu_tmp1_i64);
5614 break;
5615 case 3:
5616 default:
5617 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5618 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5619 gen_helper_fildl_FT0(cpu_env, cpu_tmp2_i32);
5620 break;
5621 }
5622
5623 gen_helper_fp_arith_ST0_FT0(op1);
5624 if (op1 == 3) {
5625 /* fcomp needs pop */
5626 gen_helper_fpop(cpu_env);
5627 }
5628 }
5629 break;
5630 case 0x08: /* flds */
5631 case 0x0a: /* fsts */
5632 case 0x0b: /* fstps */
5633 case 0x18 ... 0x1b: /* fildl, fisttpl, fistl, fistpl */
5634 case 0x28 ... 0x2b: /* fldl, fisttpll, fstl, fstpl */
5635 case 0x38 ... 0x3b: /* filds, fisttps, fists, fistps */
5636 switch(op & 7) {
5637 case 0:
5638 switch(op >> 4) {
5639 case 0:
5640 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5641 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5642 gen_helper_flds_ST0(cpu_env, cpu_tmp2_i32);
5643 break;
5644 case 1:
5645 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
5646 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5647 gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
5648 break;
5649 case 2:
5650 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5651 (s->mem_index >> 2) - 1);
5652 gen_helper_fldl_ST0(cpu_env, cpu_tmp1_i64);
5653 break;
5654 case 3:
5655 default:
5656 gen_op_lds_T0_A0(OT_WORD + s->mem_index);
5657 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5658 gen_helper_fildl_ST0(cpu_env, cpu_tmp2_i32);
5659 break;
5660 }
5661 break;
5662 case 1:
5663 /* XXX: the corresponding CPUID bit must be tested ! */
5664 switch(op >> 4) {
5665 case 1:
5666 gen_helper_fisttl_ST0(cpu_tmp2_i32, cpu_env);
5667 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5668 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5669 break;
5670 case 2:
5671 gen_helper_fisttll_ST0(cpu_tmp1_i64, cpu_env);
5672 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5673 (s->mem_index >> 2) - 1);
5674 break;
5675 case 3:
5676 default:
5677 gen_helper_fistt_ST0(cpu_tmp2_i32, cpu_env);
5678 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5679 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5680 break;
5681 }
5682 gen_helper_fpop(cpu_env);
5683 break;
5684 default:
5685 switch(op >> 4) {
5686 case 0:
5687 gen_helper_fsts_ST0(cpu_tmp2_i32, cpu_env);
5688 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5689 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5690 break;
5691 case 1:
5692 gen_helper_fistl_ST0(cpu_tmp2_i32, cpu_env);
5693 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5694 gen_op_st_T0_A0(OT_LONG + s->mem_index);
5695 break;
5696 case 2:
5697 gen_helper_fstl_ST0(cpu_tmp1_i64, cpu_env);
5698 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5699 (s->mem_index >> 2) - 1);
5700 break;
5701 case 3:
5702 default:
5703 gen_helper_fist_ST0(cpu_tmp2_i32, cpu_env);
5704 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5705 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5706 break;
5707 }
5708 if ((op & 7) == 3)
5709 gen_helper_fpop(cpu_env);
5710 break;
5711 }
5712 break;
5713 case 0x0c: /* fldenv mem */
5714 if (s->cc_op != CC_OP_DYNAMIC)
5715 gen_op_set_cc_op(s->cc_op);
5716 gen_jmp_im(pc_start - s->cs_base);
5717 gen_helper_fldenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
5718 break;
5719 case 0x0d: /* fldcw mem */
5720 gen_op_ld_T0_A0(OT_WORD + s->mem_index);
5721 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
5722 gen_helper_fldcw(cpu_env, cpu_tmp2_i32);
5723 break;
5724 case 0x0e: /* fnstenv mem */
5725 if (s->cc_op != CC_OP_DYNAMIC)
5726 gen_op_set_cc_op(s->cc_op);
5727 gen_jmp_im(pc_start - s->cs_base);
5728 gen_helper_fstenv(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
5729 break;
5730 case 0x0f: /* fnstcw mem */
5731 gen_helper_fnstcw(cpu_tmp2_i32, cpu_env);
5732 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5733 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5734 break;
5735 case 0x1d: /* fldt mem */
5736 if (s->cc_op != CC_OP_DYNAMIC)
5737 gen_op_set_cc_op(s->cc_op);
5738 gen_jmp_im(pc_start - s->cs_base);
5739 gen_helper_fldt_ST0(cpu_env, cpu_A0);
5740 break;
5741 case 0x1f: /* fstpt mem */
5742 if (s->cc_op != CC_OP_DYNAMIC)
5743 gen_op_set_cc_op(s->cc_op);
5744 gen_jmp_im(pc_start - s->cs_base);
5745 gen_helper_fstt_ST0(cpu_env, cpu_A0);
5746 gen_helper_fpop(cpu_env);
5747 break;
5748 case 0x2c: /* frstor mem */
5749 if (s->cc_op != CC_OP_DYNAMIC)
5750 gen_op_set_cc_op(s->cc_op);
5751 gen_jmp_im(pc_start - s->cs_base);
5752 gen_helper_frstor(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
5753 break;
5754 case 0x2e: /* fnsave mem */
5755 if (s->cc_op != CC_OP_DYNAMIC)
5756 gen_op_set_cc_op(s->cc_op);
5757 gen_jmp_im(pc_start - s->cs_base);
5758 gen_helper_fsave(cpu_env, cpu_A0, tcg_const_i32(s->dflag));
5759 break;
5760 case 0x2f: /* fnstsw mem */
5761 gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
5762 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
5763 gen_op_st_T0_A0(OT_WORD + s->mem_index);
5764 break;
5765 case 0x3c: /* fbld */
5766 if (s->cc_op != CC_OP_DYNAMIC)
5767 gen_op_set_cc_op(s->cc_op);
5768 gen_jmp_im(pc_start - s->cs_base);
5769 gen_helper_fbld_ST0(cpu_env, cpu_A0);
5770 break;
5771 case 0x3e: /* fbstp */
5772 if (s->cc_op != CC_OP_DYNAMIC)
5773 gen_op_set_cc_op(s->cc_op);
5774 gen_jmp_im(pc_start - s->cs_base);
5775 gen_helper_fbst_ST0(cpu_env, cpu_A0);
5776 gen_helper_fpop(cpu_env);
5777 break;
5778 case 0x3d: /* fildll */
5779 tcg_gen_qemu_ld64(cpu_tmp1_i64, cpu_A0,
5780 (s->mem_index >> 2) - 1);
5781 gen_helper_fildll_ST0(cpu_env, cpu_tmp1_i64);
5782 break;
5783 case 0x3f: /* fistpll */
5784 gen_helper_fistll_ST0(cpu_tmp1_i64, cpu_env);
5785 tcg_gen_qemu_st64(cpu_tmp1_i64, cpu_A0,
5786 (s->mem_index >> 2) - 1);
5787 gen_helper_fpop(cpu_env);
5788 break;
5789 default:
5790 goto illegal_op;
5791 }
5792 } else {
5793 /* register float ops */
5794 opreg = rm;
5795
5796 switch(op) {
5797 case 0x08: /* fld sti */
5798 gen_helper_fpush(cpu_env);
5799 gen_helper_fmov_ST0_STN(cpu_env,
5800 tcg_const_i32((opreg + 1) & 7));
5801 break;
5802 case 0x09: /* fxchg sti */
5803 case 0x29: /* fxchg4 sti, undocumented op */
5804 case 0x39: /* fxchg7 sti, undocumented op */
5805 gen_helper_fxchg_ST0_STN(cpu_env, tcg_const_i32(opreg));
5806 break;
5807 case 0x0a: /* grp d9/2 */
5808 switch(rm) {
5809 case 0: /* fnop */
5810 /* check exceptions (FreeBSD FPU probe) */
5811 if (s->cc_op != CC_OP_DYNAMIC)
5812 gen_op_set_cc_op(s->cc_op);
5813 gen_jmp_im(pc_start - s->cs_base);
5814 gen_helper_fwait(cpu_env);
5815 break;
5816 default:
5817 goto illegal_op;
5818 }
5819 break;
5820 case 0x0c: /* grp d9/4 */
5821 switch(rm) {
5822 case 0: /* fchs */
5823 gen_helper_fchs_ST0(cpu_env);
5824 break;
5825 case 1: /* fabs */
5826 gen_helper_fabs_ST0(cpu_env);
5827 break;
5828 case 4: /* ftst */
5829 gen_helper_fldz_FT0(cpu_env);
5830 gen_helper_fcom_ST0_FT0(cpu_env);
5831 break;
5832 case 5: /* fxam */
5833 gen_helper_fxam_ST0(cpu_env);
5834 break;
5835 default:
5836 goto illegal_op;
5837 }
5838 break;
5839 case 0x0d: /* grp d9/5 */
5840 {
5841 switch(rm) {
5842 case 0:
5843 gen_helper_fpush(cpu_env);
5844 gen_helper_fld1_ST0(cpu_env);
5845 break;
5846 case 1:
5847 gen_helper_fpush(cpu_env);
5848 gen_helper_fldl2t_ST0(cpu_env);
5849 break;
5850 case 2:
5851 gen_helper_fpush(cpu_env);
5852 gen_helper_fldl2e_ST0(cpu_env);
5853 break;
5854 case 3:
5855 gen_helper_fpush(cpu_env);
5856 gen_helper_fldpi_ST0(cpu_env);
5857 break;
5858 case 4:
5859 gen_helper_fpush(cpu_env);
5860 gen_helper_fldlg2_ST0(cpu_env);
5861 break;
5862 case 5:
5863 gen_helper_fpush(cpu_env);
5864 gen_helper_fldln2_ST0(cpu_env);
5865 break;
5866 case 6:
5867 gen_helper_fpush(cpu_env);
5868 gen_helper_fldz_ST0(cpu_env);
5869 break;
5870 default:
5871 goto illegal_op;
5872 }
5873 }
5874 break;
5875 case 0x0e: /* grp d9/6 */
5876 switch(rm) {
5877 case 0: /* f2xm1 */
5878 gen_helper_f2xm1(cpu_env);
5879 break;
5880 case 1: /* fyl2x */
5881 gen_helper_fyl2x(cpu_env);
5882 break;
5883 case 2: /* fptan */
5884 gen_helper_fptan(cpu_env);
5885 break;
5886 case 3: /* fpatan */
5887 gen_helper_fpatan(cpu_env);
5888 break;
5889 case 4: /* fxtract */
5890 gen_helper_fxtract(cpu_env);
5891 break;
5892 case 5: /* fprem1 */
5893 gen_helper_fprem1(cpu_env);
5894 break;
5895 case 6: /* fdecstp */
5896 gen_helper_fdecstp(cpu_env);
5897 break;
5898 default:
5899 case 7: /* fincstp */
5900 gen_helper_fincstp(cpu_env);
5901 break;
5902 }
5903 break;
5904 case 0x0f: /* grp d9/7 */
5905 switch(rm) {
5906 case 0: /* fprem */
5907 gen_helper_fprem(cpu_env);
5908 break;
5909 case 1: /* fyl2xp1 */
5910 gen_helper_fyl2xp1(cpu_env);
5911 break;
5912 case 2: /* fsqrt */
5913 gen_helper_fsqrt(cpu_env);
5914 break;
5915 case 3: /* fsincos */
5916 gen_helper_fsincos(cpu_env);
5917 break;
5918 case 5: /* fscale */
5919 gen_helper_fscale(cpu_env);
5920 break;
5921 case 4: /* frndint */
5922 gen_helper_frndint(cpu_env);
5923 break;
5924 case 6: /* fsin */
5925 gen_helper_fsin(cpu_env);
5926 break;
5927 default:
5928 case 7: /* fcos */
5929 gen_helper_fcos(cpu_env);
5930 break;
5931 }
5932 break;
5933 case 0x00: case 0x01: case 0x04 ... 0x07: /* fxxx st, sti */
5934 case 0x20: case 0x21: case 0x24 ... 0x27: /* fxxx sti, st */
5935 case 0x30: case 0x31: case 0x34 ... 0x37: /* fxxxp sti, st */
5936 {
5937 int op1;
5938
5939 op1 = op & 7;
5940 if (op >= 0x20) {
5941 gen_helper_fp_arith_STN_ST0(op1, opreg);
5942 if (op >= 0x30)
5943 gen_helper_fpop(cpu_env);
5944 } else {
5945 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
5946 gen_helper_fp_arith_ST0_FT0(op1);
5947 }
5948 }
5949 break;
5950 case 0x02: /* fcom */
5951 case 0x22: /* fcom2, undocumented op */
5952 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
5953 gen_helper_fcom_ST0_FT0(cpu_env);
5954 break;
5955 case 0x03: /* fcomp */
5956 case 0x23: /* fcomp3, undocumented op */
5957 case 0x32: /* fcomp5, undocumented op */
5958 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
5959 gen_helper_fcom_ST0_FT0(cpu_env);
5960 gen_helper_fpop(cpu_env);
5961 break;
5962 case 0x15: /* da/5 */
5963 switch(rm) {
5964 case 1: /* fucompp */
5965 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1));
5966 gen_helper_fucom_ST0_FT0(cpu_env);
5967 gen_helper_fpop(cpu_env);
5968 gen_helper_fpop(cpu_env);
5969 break;
5970 default:
5971 goto illegal_op;
5972 }
5973 break;
5974 case 0x1c:
5975 switch(rm) {
5976 case 0: /* feni (287 only, just do nop here) */
5977 break;
5978 case 1: /* fdisi (287 only, just do nop here) */
5979 break;
5980 case 2: /* fclex */
5981 gen_helper_fclex(cpu_env);
5982 break;
5983 case 3: /* fninit */
5984 gen_helper_fninit(cpu_env);
5985 break;
5986 case 4: /* fsetpm (287 only, just do nop here) */
5987 break;
5988 default:
5989 goto illegal_op;
5990 }
5991 break;
5992 case 0x1d: /* fucomi */
5993 if (s->cc_op != CC_OP_DYNAMIC)
5994 gen_op_set_cc_op(s->cc_op);
5995 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
5996 gen_helper_fucomi_ST0_FT0(cpu_env);
5997 s->cc_op = CC_OP_EFLAGS;
5998 break;
5999 case 0x1e: /* fcomi */
6000 if (s->cc_op != CC_OP_DYNAMIC)
6001 gen_op_set_cc_op(s->cc_op);
6002 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6003 gen_helper_fcomi_ST0_FT0(cpu_env);
6004 s->cc_op = CC_OP_EFLAGS;
6005 break;
6006 case 0x28: /* ffree sti */
6007 gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg));
6008 break;
6009 case 0x2a: /* fst sti */
6010 gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg));
6011 break;
6012 case 0x2b: /* fstp sti */
6013 case 0x0b: /* fstp1 sti, undocumented op */
6014 case 0x3a: /* fstp8 sti, undocumented op */
6015 case 0x3b: /* fstp9 sti, undocumented op */
6016 gen_helper_fmov_STN_ST0(cpu_env, tcg_const_i32(opreg));
6017 gen_helper_fpop(cpu_env);
6018 break;
6019 case 0x2c: /* fucom st(i) */
6020 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6021 gen_helper_fucom_ST0_FT0(cpu_env);
6022 break;
6023 case 0x2d: /* fucomp st(i) */
6024 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6025 gen_helper_fucom_ST0_FT0(cpu_env);
6026 gen_helper_fpop(cpu_env);
6027 break;
6028 case 0x33: /* de/3 */
6029 switch(rm) {
6030 case 1: /* fcompp */
6031 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(1));
6032 gen_helper_fcom_ST0_FT0(cpu_env);
6033 gen_helper_fpop(cpu_env);
6034 gen_helper_fpop(cpu_env);
6035 break;
6036 default:
6037 goto illegal_op;
6038 }
6039 break;
6040 case 0x38: /* ffreep sti, undocumented op */
6041 gen_helper_ffree_STN(cpu_env, tcg_const_i32(opreg));
6042 gen_helper_fpop(cpu_env);
6043 break;
6044 case 0x3c: /* df/4 */
6045 switch(rm) {
6046 case 0:
6047 gen_helper_fnstsw(cpu_tmp2_i32, cpu_env);
6048 tcg_gen_extu_i32_tl(cpu_T[0], cpu_tmp2_i32);
6049 gen_op_mov_reg_T0(OT_WORD, R_EAX);
6050 break;
6051 default:
6052 goto illegal_op;
6053 }
6054 break;
6055 case 0x3d: /* fucomip */
6056 if (s->cc_op != CC_OP_DYNAMIC)
6057 gen_op_set_cc_op(s->cc_op);
6058 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6059 gen_helper_fucomi_ST0_FT0(cpu_env);
6060 gen_helper_fpop(cpu_env);
6061 s->cc_op = CC_OP_EFLAGS;
6062 break;
6063 case 0x3e: /* fcomip */
6064 if (s->cc_op != CC_OP_DYNAMIC)
6065 gen_op_set_cc_op(s->cc_op);
6066 gen_helper_fmov_FT0_STN(cpu_env, tcg_const_i32(opreg));
6067 gen_helper_fcomi_ST0_FT0(cpu_env);
6068 gen_helper_fpop(cpu_env);
6069 s->cc_op = CC_OP_EFLAGS;
6070 break;
6071 case 0x10 ... 0x13: /* fcmovxx */
6072 case 0x18 ... 0x1b:
6073 {
6074 int op1, l1;
6075 static const uint8_t fcmov_cc[8] = {
6076 (JCC_B << 1),
6077 (JCC_Z << 1),
6078 (JCC_BE << 1),
6079 (JCC_P << 1),
6080 };
6081 op1 = fcmov_cc[op & 3] | (((op >> 3) & 1) ^ 1);
6082 l1 = gen_new_label();
6083 gen_jcc1(s, s->cc_op, op1, l1);
6084 gen_helper_fmov_ST0_STN(cpu_env, tcg_const_i32(opreg));
6085 gen_set_label(l1);
6086 }
6087 break;
6088 default:
6089 goto illegal_op;
6090 }
6091 }
6092 break;
6093 /************************/
6094 /* string ops */
6095
6096 case 0xa4: /* movsS */
6097 case 0xa5:
6098 if ((b & 1) == 0)
6099 ot = OT_BYTE;
6100 else
6101 ot = dflag + OT_WORD;
6102
6103 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6104 gen_repz_movs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6105 } else {
6106 gen_movs(s, ot);
6107 }
6108 break;
6109
6110 case 0xaa: /* stosS */
6111 case 0xab:
6112 if ((b & 1) == 0)
6113 ot = OT_BYTE;
6114 else
6115 ot = dflag + OT_WORD;
6116
6117 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6118 gen_repz_stos(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6119 } else {
6120 gen_stos(s, ot);
6121 }
6122 break;
6123 case 0xac: /* lodsS */
6124 case 0xad:
6125 if ((b & 1) == 0)
6126 ot = OT_BYTE;
6127 else
6128 ot = dflag + OT_WORD;
6129 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6130 gen_repz_lods(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6131 } else {
6132 gen_lods(s, ot);
6133 }
6134 break;
6135 case 0xae: /* scasS */
6136 case 0xaf:
6137 if ((b & 1) == 0)
6138 ot = OT_BYTE;
6139 else
6140 ot = dflag + OT_WORD;
6141 if (prefixes & PREFIX_REPNZ) {
6142 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
6143 } else if (prefixes & PREFIX_REPZ) {
6144 gen_repz_scas(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
6145 } else {
6146 gen_scas(s, ot);
6147 s->cc_op = CC_OP_SUBB + ot;
6148 }
6149 break;
6150
6151 case 0xa6: /* cmpsS */
6152 case 0xa7:
6153 if ((b & 1) == 0)
6154 ot = OT_BYTE;
6155 else
6156 ot = dflag + OT_WORD;
6157 if (prefixes & PREFIX_REPNZ) {
6158 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 1);
6159 } else if (prefixes & PREFIX_REPZ) {
6160 gen_repz_cmps(s, ot, pc_start - s->cs_base, s->pc - s->cs_base, 0);
6161 } else {
6162 gen_cmps(s, ot);
6163 s->cc_op = CC_OP_SUBB + ot;
6164 }
6165 break;
6166 case 0x6c: /* insS */
6167 case 0x6d:
6168 if ((b & 1) == 0)
6169 ot = OT_BYTE;
6170 else
6171 ot = dflag ? OT_LONG : OT_WORD;
6172 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6173 gen_op_andl_T0_ffff();
6174 gen_check_io(s, ot, pc_start - s->cs_base,
6175 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes) | 4);
6176 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6177 gen_repz_ins(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6178 } else {
6179 gen_ins(s, ot);
6180 if (use_icount) {
6181 gen_jmp(s, s->pc - s->cs_base);
6182 }
6183 }
6184 break;
6185 case 0x6e: /* outsS */
6186 case 0x6f:
6187 if ((b & 1) == 0)
6188 ot = OT_BYTE;
6189 else
6190 ot = dflag ? OT_LONG : OT_WORD;
6191 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6192 gen_op_andl_T0_ffff();
6193 gen_check_io(s, ot, pc_start - s->cs_base,
6194 svm_is_rep(prefixes) | 4);
6195 if (prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) {
6196 gen_repz_outs(s, ot, pc_start - s->cs_base, s->pc - s->cs_base);
6197 } else {
6198 gen_outs(s, ot);
6199 if (use_icount) {
6200 gen_jmp(s, s->pc - s->cs_base);
6201 }
6202 }
6203 break;
6204
6205 /************************/
6206 /* port I/O */
6207
6208 case 0xe4:
6209 case 0xe5:
6210 if ((b & 1) == 0)
6211 ot = OT_BYTE;
6212 else
6213 ot = dflag ? OT_LONG : OT_WORD;
6214 val = cpu_ldub_code(cpu_single_env, s->pc++);
6215 gen_op_movl_T0_im(val);
6216 gen_check_io(s, ot, pc_start - s->cs_base,
6217 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
6218 if (use_icount)
6219 gen_io_start();
6220 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6221 gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
6222 gen_op_mov_reg_T1(ot, R_EAX);
6223 if (use_icount) {
6224 gen_io_end();
6225 gen_jmp(s, s->pc - s->cs_base);
6226 }
6227 break;
6228 case 0xe6:
6229 case 0xe7:
6230 if ((b & 1) == 0)
6231 ot = OT_BYTE;
6232 else
6233 ot = dflag ? OT_LONG : OT_WORD;
6234 val = cpu_ldub_code(cpu_single_env, s->pc++);
6235 gen_op_movl_T0_im(val);
6236 gen_check_io(s, ot, pc_start - s->cs_base,
6237 svm_is_rep(prefixes));
6238 gen_op_mov_TN_reg(ot, 1, R_EAX);
6239
6240 if (use_icount)
6241 gen_io_start();
6242 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6243 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
6244 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
6245 if (use_icount) {
6246 gen_io_end();
6247 gen_jmp(s, s->pc - s->cs_base);
6248 }
6249 break;
6250 case 0xec:
6251 case 0xed:
6252 if ((b & 1) == 0)
6253 ot = OT_BYTE;
6254 else
6255 ot = dflag ? OT_LONG : OT_WORD;
6256 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6257 gen_op_andl_T0_ffff();
6258 gen_check_io(s, ot, pc_start - s->cs_base,
6259 SVM_IOIO_TYPE_MASK | svm_is_rep(prefixes));
6260 if (use_icount)
6261 gen_io_start();
6262 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6263 gen_helper_in_func(ot, cpu_T[1], cpu_tmp2_i32);
6264 gen_op_mov_reg_T1(ot, R_EAX);
6265 if (use_icount) {
6266 gen_io_end();
6267 gen_jmp(s, s->pc - s->cs_base);
6268 }
6269 break;
6270 case 0xee:
6271 case 0xef:
6272 if ((b & 1) == 0)
6273 ot = OT_BYTE;
6274 else
6275 ot = dflag ? OT_LONG : OT_WORD;
6276 gen_op_mov_TN_reg(OT_WORD, 0, R_EDX);
6277 gen_op_andl_T0_ffff();
6278 gen_check_io(s, ot, pc_start - s->cs_base,
6279 svm_is_rep(prefixes));
6280 gen_op_mov_TN_reg(ot, 1, R_EAX);
6281
6282 if (use_icount)
6283 gen_io_start();
6284 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6285 tcg_gen_trunc_tl_i32(cpu_tmp3_i32, cpu_T[1]);
6286 gen_helper_out_func(ot, cpu_tmp2_i32, cpu_tmp3_i32);
6287 if (use_icount) {
6288 gen_io_end();
6289 gen_jmp(s, s->pc - s->cs_base);
6290 }
6291 break;
6292
6293 /************************/
6294 /* control */
6295 case 0xc2: /* ret im */
6296 val = cpu_ldsw_code(cpu_single_env, s->pc);
6297 s->pc += 2;
6298 gen_pop_T0(s);
6299 if (CODE64(s) && s->dflag)
6300 s->dflag = 2;
6301 gen_stack_update(s, val + (2 << s->dflag));
6302 if (s->dflag == 0)
6303 gen_op_andl_T0_ffff();
6304 gen_op_jmp_T0();
6305 gen_eob(s);
6306 break;
6307 case 0xc3: /* ret */
6308 gen_pop_T0(s);
6309 gen_pop_update(s);
6310 if (s->dflag == 0)
6311 gen_op_andl_T0_ffff();
6312 gen_op_jmp_T0();
6313 gen_eob(s);
6314 break;
6315 case 0xca: /* lret im */
6316 val = cpu_ldsw_code(cpu_single_env, s->pc);
6317 s->pc += 2;
6318 do_lret:
6319 if (s->pe && !s->vm86) {
6320 if (s->cc_op != CC_OP_DYNAMIC)
6321 gen_op_set_cc_op(s->cc_op);
6322 gen_jmp_im(pc_start - s->cs_base);
6323 gen_helper_lret_protected(cpu_env, tcg_const_i32(s->dflag),
6324 tcg_const_i32(val));
6325 } else {
6326 gen_stack_A0(s);
6327 /* pop offset */
6328 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
6329 if (s->dflag == 0)
6330 gen_op_andl_T0_ffff();
6331 /* NOTE: keeping EIP updated is not a problem in case of
6332 exception */
6333 gen_op_jmp_T0();
6334 /* pop selector */
6335 gen_op_addl_A0_im(2 << s->dflag);
6336 gen_op_ld_T0_A0(1 + s->dflag + s->mem_index);
6337 gen_op_movl_seg_T0_vm(R_CS);
6338 /* add stack offset */
6339 gen_stack_update(s, val + (4 << s->dflag));
6340 }
6341 gen_eob(s);
6342 break;
6343 case 0xcb: /* lret */
6344 val = 0;
6345 goto do_lret;
6346 case 0xcf: /* iret */
6347 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IRET);
6348 if (!s->pe) {
6349 /* real mode */
6350 gen_helper_iret_real(cpu_env, tcg_const_i32(s->dflag));
6351 s->cc_op = CC_OP_EFLAGS;
6352 } else if (s->vm86) {
6353 if (s->iopl != 3) {
6354 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6355 } else {
6356 gen_helper_iret_real(cpu_env, tcg_const_i32(s->dflag));
6357 s->cc_op = CC_OP_EFLAGS;
6358 }
6359 } else {
6360 if (s->cc_op != CC_OP_DYNAMIC)
6361 gen_op_set_cc_op(s->cc_op);
6362 gen_jmp_im(pc_start - s->cs_base);
6363 gen_helper_iret_protected(cpu_env, tcg_const_i32(s->dflag),
6364 tcg_const_i32(s->pc - s->cs_base));
6365 s->cc_op = CC_OP_EFLAGS;
6366 }
6367 gen_eob(s);
6368 break;
6369 case 0xe8: /* call im */
6370 {
6371 if (dflag)
6372 tval = (int32_t)insn_get(s, OT_LONG);
6373 else
6374 tval = (int16_t)insn_get(s, OT_WORD);
6375 next_eip = s->pc - s->cs_base;
6376 tval += next_eip;
6377 if (s->dflag == 0)
6378 tval &= 0xffff;
6379 else if(!CODE64(s))
6380 tval &= 0xffffffff;
6381 gen_movtl_T0_im(next_eip);
6382 gen_push_T0(s);
6383 gen_jmp(s, tval);
6384 }
6385 break;
6386 case 0x9a: /* lcall im */
6387 {
6388 unsigned int selector, offset;
6389
6390 if (CODE64(s))
6391 goto illegal_op;
6392 ot = dflag ? OT_LONG : OT_WORD;
6393 offset = insn_get(s, ot);
6394 selector = insn_get(s, OT_WORD);
6395
6396 gen_op_movl_T0_im(selector);
6397 gen_op_movl_T1_imu(offset);
6398 }
6399 goto do_lcall;
6400 case 0xe9: /* jmp im */
6401 if (dflag)
6402 tval = (int32_t)insn_get(s, OT_LONG);
6403 else
6404 tval = (int16_t)insn_get(s, OT_WORD);
6405 tval += s->pc - s->cs_base;
6406 if (s->dflag == 0)
6407 tval &= 0xffff;
6408 else if(!CODE64(s))
6409 tval &= 0xffffffff;
6410 gen_jmp(s, tval);
6411 break;
6412 case 0xea: /* ljmp im */
6413 {
6414 unsigned int selector, offset;
6415
6416 if (CODE64(s))
6417 goto illegal_op;
6418 ot = dflag ? OT_LONG : OT_WORD;
6419 offset = insn_get(s, ot);
6420 selector = insn_get(s, OT_WORD);
6421
6422 gen_op_movl_T0_im(selector);
6423 gen_op_movl_T1_imu(offset);
6424 }
6425 goto do_ljmp;
6426 case 0xeb: /* jmp Jb */
6427 tval = (int8_t)insn_get(s, OT_BYTE);
6428 tval += s->pc - s->cs_base;
6429 if (s->dflag == 0)
6430 tval &= 0xffff;
6431 gen_jmp(s, tval);
6432 break;
6433 case 0x70 ... 0x7f: /* jcc Jb */
6434 tval = (int8_t)insn_get(s, OT_BYTE);
6435 goto do_jcc;
6436 case 0x180 ... 0x18f: /* jcc Jv */
6437 if (dflag) {
6438 tval = (int32_t)insn_get(s, OT_LONG);
6439 } else {
6440 tval = (int16_t)insn_get(s, OT_WORD);
6441 }
6442 do_jcc:
6443 next_eip = s->pc - s->cs_base;
6444 tval += next_eip;
6445 if (s->dflag == 0)
6446 tval &= 0xffff;
6447 gen_jcc(s, b, tval, next_eip);
6448 break;
6449
6450 case 0x190 ... 0x19f: /* setcc Gv */
6451 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
6452 gen_setcc(s, b);
6453 gen_ldst_modrm(s, modrm, OT_BYTE, OR_TMP0, 1);
6454 break;
6455 case 0x140 ... 0x14f: /* cmov Gv, Ev */
6456 {
6457 int l1;
6458 TCGv t0;
6459
6460 ot = dflag + OT_WORD;
6461 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
6462 reg = ((modrm >> 3) & 7) | rex_r;
6463 mod = (modrm >> 6) & 3;
6464 t0 = tcg_temp_local_new();
6465 if (mod != 3) {
6466 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6467 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
6468 } else {
6469 rm = (modrm & 7) | REX_B(s);
6470 gen_op_mov_v_reg(ot, t0, rm);
6471 }
6472 #ifdef TARGET_X86_64
6473 if (ot == OT_LONG) {
6474 /* XXX: specific Intel behaviour ? */
6475 l1 = gen_new_label();
6476 gen_jcc1(s, s->cc_op, b ^ 1, l1);
6477 tcg_gen_mov_tl(cpu_regs[reg], t0);
6478 gen_set_label(l1);
6479 tcg_gen_ext32u_tl(cpu_regs[reg], cpu_regs[reg]);
6480 } else
6481 #endif
6482 {
6483 l1 = gen_new_label();
6484 gen_jcc1(s, s->cc_op, b ^ 1, l1);
6485 gen_op_mov_reg_v(ot, reg, t0);
6486 gen_set_label(l1);
6487 }
6488 tcg_temp_free(t0);
6489 }
6490 break;
6491
6492 /************************/
6493 /* flags */
6494 case 0x9c: /* pushf */
6495 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PUSHF);
6496 if (s->vm86 && s->iopl != 3) {
6497 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6498 } else {
6499 if (s->cc_op != CC_OP_DYNAMIC)
6500 gen_op_set_cc_op(s->cc_op);
6501 gen_helper_read_eflags(cpu_T[0], cpu_env);
6502 gen_push_T0(s);
6503 }
6504 break;
6505 case 0x9d: /* popf */
6506 gen_svm_check_intercept(s, pc_start, SVM_EXIT_POPF);
6507 if (s->vm86 && s->iopl != 3) {
6508 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6509 } else {
6510 gen_pop_T0(s);
6511 if (s->cpl == 0) {
6512 if (s->dflag) {
6513 gen_helper_write_eflags(cpu_env, cpu_T[0],
6514 tcg_const_i32((TF_MASK | AC_MASK |
6515 ID_MASK | NT_MASK |
6516 IF_MASK |
6517 IOPL_MASK)));
6518 } else {
6519 gen_helper_write_eflags(cpu_env, cpu_T[0],
6520 tcg_const_i32((TF_MASK | AC_MASK |
6521 ID_MASK | NT_MASK |
6522 IF_MASK | IOPL_MASK)
6523 & 0xffff));
6524 }
6525 } else {
6526 if (s->cpl <= s->iopl) {
6527 if (s->dflag) {
6528 gen_helper_write_eflags(cpu_env, cpu_T[0],
6529 tcg_const_i32((TF_MASK |
6530 AC_MASK |
6531 ID_MASK |
6532 NT_MASK |
6533 IF_MASK)));
6534 } else {
6535 gen_helper_write_eflags(cpu_env, cpu_T[0],
6536 tcg_const_i32((TF_MASK |
6537 AC_MASK |
6538 ID_MASK |
6539 NT_MASK |
6540 IF_MASK)
6541 & 0xffff));
6542 }
6543 } else {
6544 if (s->dflag) {
6545 gen_helper_write_eflags(cpu_env, cpu_T[0],
6546 tcg_const_i32((TF_MASK | AC_MASK |
6547 ID_MASK | NT_MASK)));
6548 } else {
6549 gen_helper_write_eflags(cpu_env, cpu_T[0],
6550 tcg_const_i32((TF_MASK | AC_MASK |
6551 ID_MASK | NT_MASK)
6552 & 0xffff));
6553 }
6554 }
6555 }
6556 gen_pop_update(s);
6557 s->cc_op = CC_OP_EFLAGS;
6558 /* abort translation because TF flag may change */
6559 gen_jmp_im(s->pc - s->cs_base);
6560 gen_eob(s);
6561 }
6562 break;
6563 case 0x9e: /* sahf */
6564 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
6565 goto illegal_op;
6566 gen_op_mov_TN_reg(OT_BYTE, 0, R_AH);
6567 if (s->cc_op != CC_OP_DYNAMIC)
6568 gen_op_set_cc_op(s->cc_op);
6569 gen_compute_eflags(cpu_cc_src);
6570 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, CC_O);
6571 tcg_gen_andi_tl(cpu_T[0], cpu_T[0], CC_S | CC_Z | CC_A | CC_P | CC_C);
6572 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, cpu_T[0]);
6573 s->cc_op = CC_OP_EFLAGS;
6574 break;
6575 case 0x9f: /* lahf */
6576 if (CODE64(s) && !(s->cpuid_ext3_features & CPUID_EXT3_LAHF_LM))
6577 goto illegal_op;
6578 if (s->cc_op != CC_OP_DYNAMIC)
6579 gen_op_set_cc_op(s->cc_op);
6580 gen_compute_eflags(cpu_T[0]);
6581 /* Note: gen_compute_eflags() only gives the condition codes */
6582 tcg_gen_ori_tl(cpu_T[0], cpu_T[0], 0x02);
6583 gen_op_mov_reg_T0(OT_BYTE, R_AH);
6584 break;
6585 case 0xf5: /* cmc */
6586 if (s->cc_op != CC_OP_DYNAMIC)
6587 gen_op_set_cc_op(s->cc_op);
6588 gen_compute_eflags(cpu_cc_src);
6589 tcg_gen_xori_tl(cpu_cc_src, cpu_cc_src, CC_C);
6590 s->cc_op = CC_OP_EFLAGS;
6591 break;
6592 case 0xf8: /* clc */
6593 if (s->cc_op != CC_OP_DYNAMIC)
6594 gen_op_set_cc_op(s->cc_op);
6595 gen_compute_eflags(cpu_cc_src);
6596 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_C);
6597 s->cc_op = CC_OP_EFLAGS;
6598 break;
6599 case 0xf9: /* stc */
6600 if (s->cc_op != CC_OP_DYNAMIC)
6601 gen_op_set_cc_op(s->cc_op);
6602 gen_compute_eflags(cpu_cc_src);
6603 tcg_gen_ori_tl(cpu_cc_src, cpu_cc_src, CC_C);
6604 s->cc_op = CC_OP_EFLAGS;
6605 break;
6606 case 0xfc: /* cld */
6607 tcg_gen_movi_i32(cpu_tmp2_i32, 1);
6608 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df));
6609 break;
6610 case 0xfd: /* std */
6611 tcg_gen_movi_i32(cpu_tmp2_i32, -1);
6612 tcg_gen_st_i32(cpu_tmp2_i32, cpu_env, offsetof(CPUX86State, df));
6613 break;
6614
6615 /************************/
6616 /* bit operations */
6617 case 0x1ba: /* bt/bts/btr/btc Gv, im */
6618 ot = dflag + OT_WORD;
6619 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
6620 op = (modrm >> 3) & 7;
6621 mod = (modrm >> 6) & 3;
6622 rm = (modrm & 7) | REX_B(s);
6623 if (mod != 3) {
6624 s->rip_offset = 1;
6625 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6626 gen_op_ld_T0_A0(ot + s->mem_index);
6627 } else {
6628 gen_op_mov_TN_reg(ot, 0, rm);
6629 }
6630 /* load shift */
6631 val = cpu_ldub_code(cpu_single_env, s->pc++);
6632 gen_op_movl_T1_im(val);
6633 if (op < 4)
6634 goto illegal_op;
6635 op -= 4;
6636 goto bt_op;
6637 case 0x1a3: /* bt Gv, Ev */
6638 op = 0;
6639 goto do_btx;
6640 case 0x1ab: /* bts */
6641 op = 1;
6642 goto do_btx;
6643 case 0x1b3: /* btr */
6644 op = 2;
6645 goto do_btx;
6646 case 0x1bb: /* btc */
6647 op = 3;
6648 do_btx:
6649 ot = dflag + OT_WORD;
6650 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
6651 reg = ((modrm >> 3) & 7) | rex_r;
6652 mod = (modrm >> 6) & 3;
6653 rm = (modrm & 7) | REX_B(s);
6654 gen_op_mov_TN_reg(OT_LONG, 1, reg);
6655 if (mod != 3) {
6656 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6657 /* specific case: we need to add a displacement */
6658 gen_exts(ot, cpu_T[1]);
6659 tcg_gen_sari_tl(cpu_tmp0, cpu_T[1], 3 + ot);
6660 tcg_gen_shli_tl(cpu_tmp0, cpu_tmp0, ot);
6661 tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
6662 gen_op_ld_T0_A0(ot + s->mem_index);
6663 } else {
6664 gen_op_mov_TN_reg(ot, 0, rm);
6665 }
6666 bt_op:
6667 tcg_gen_andi_tl(cpu_T[1], cpu_T[1], (1 << (3 + ot)) - 1);
6668 switch(op) {
6669 case 0:
6670 tcg_gen_shr_tl(cpu_cc_src, cpu_T[0], cpu_T[1]);
6671 tcg_gen_movi_tl(cpu_cc_dst, 0);
6672 break;
6673 case 1:
6674 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6675 tcg_gen_movi_tl(cpu_tmp0, 1);
6676 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6677 tcg_gen_or_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6678 break;
6679 case 2:
6680 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6681 tcg_gen_movi_tl(cpu_tmp0, 1);
6682 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6683 tcg_gen_not_tl(cpu_tmp0, cpu_tmp0);
6684 tcg_gen_and_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6685 break;
6686 default:
6687 case 3:
6688 tcg_gen_shr_tl(cpu_tmp4, cpu_T[0], cpu_T[1]);
6689 tcg_gen_movi_tl(cpu_tmp0, 1);
6690 tcg_gen_shl_tl(cpu_tmp0, cpu_tmp0, cpu_T[1]);
6691 tcg_gen_xor_tl(cpu_T[0], cpu_T[0], cpu_tmp0);
6692 break;
6693 }
6694 s->cc_op = CC_OP_SARB + ot;
6695 if (op != 0) {
6696 if (mod != 3)
6697 gen_op_st_T0_A0(ot + s->mem_index);
6698 else
6699 gen_op_mov_reg_T0(ot, rm);
6700 tcg_gen_mov_tl(cpu_cc_src, cpu_tmp4);
6701 tcg_gen_movi_tl(cpu_cc_dst, 0);
6702 }
6703 break;
6704 case 0x1bc: /* bsf */
6705 case 0x1bd: /* bsr */
6706 {
6707 int label1;
6708 TCGv t0;
6709
6710 ot = dflag + OT_WORD;
6711 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
6712 reg = ((modrm >> 3) & 7) | rex_r;
6713 gen_ldst_modrm(s,modrm, ot, OR_TMP0, 0);
6714 gen_extu(ot, cpu_T[0]);
6715 t0 = tcg_temp_local_new();
6716 tcg_gen_mov_tl(t0, cpu_T[0]);
6717 if ((b & 1) && (prefixes & PREFIX_REPZ) &&
6718 (s->cpuid_ext3_features & CPUID_EXT3_ABM)) {
6719 switch(ot) {
6720 case OT_WORD: gen_helper_lzcnt(cpu_T[0], t0,
6721 tcg_const_i32(16)); break;
6722 case OT_LONG: gen_helper_lzcnt(cpu_T[0], t0,
6723 tcg_const_i32(32)); break;
6724 case OT_QUAD: gen_helper_lzcnt(cpu_T[0], t0,
6725 tcg_const_i32(64)); break;
6726 }
6727 gen_op_mov_reg_T0(ot, reg);
6728 } else {
6729 label1 = gen_new_label();
6730 tcg_gen_movi_tl(cpu_cc_dst, 0);
6731 tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 0, label1);
6732 if (b & 1) {
6733 gen_helper_bsr(cpu_T[0], t0);
6734 } else {
6735 gen_helper_bsf(cpu_T[0], t0);
6736 }
6737 gen_op_mov_reg_T0(ot, reg);
6738 tcg_gen_movi_tl(cpu_cc_dst, 1);
6739 gen_set_label(label1);
6740 tcg_gen_discard_tl(cpu_cc_src);
6741 s->cc_op = CC_OP_LOGICB + ot;
6742 }
6743 tcg_temp_free(t0);
6744 }
6745 break;
6746 /************************/
6747 /* bcd */
6748 case 0x27: /* daa */
6749 if (CODE64(s))
6750 goto illegal_op;
6751 if (s->cc_op != CC_OP_DYNAMIC)
6752 gen_op_set_cc_op(s->cc_op);
6753 gen_helper_daa(cpu_env);
6754 s->cc_op = CC_OP_EFLAGS;
6755 break;
6756 case 0x2f: /* das */
6757 if (CODE64(s))
6758 goto illegal_op;
6759 if (s->cc_op != CC_OP_DYNAMIC)
6760 gen_op_set_cc_op(s->cc_op);
6761 gen_helper_das(cpu_env);
6762 s->cc_op = CC_OP_EFLAGS;
6763 break;
6764 case 0x37: /* aaa */
6765 if (CODE64(s))
6766 goto illegal_op;
6767 if (s->cc_op != CC_OP_DYNAMIC)
6768 gen_op_set_cc_op(s->cc_op);
6769 gen_helper_aaa(cpu_env);
6770 s->cc_op = CC_OP_EFLAGS;
6771 break;
6772 case 0x3f: /* aas */
6773 if (CODE64(s))
6774 goto illegal_op;
6775 if (s->cc_op != CC_OP_DYNAMIC)
6776 gen_op_set_cc_op(s->cc_op);
6777 gen_helper_aas(cpu_env);
6778 s->cc_op = CC_OP_EFLAGS;
6779 break;
6780 case 0xd4: /* aam */
6781 if (CODE64(s))
6782 goto illegal_op;
6783 val = cpu_ldub_code(cpu_single_env, s->pc++);
6784 if (val == 0) {
6785 gen_exception(s, EXCP00_DIVZ, pc_start - s->cs_base);
6786 } else {
6787 gen_helper_aam(cpu_env, tcg_const_i32(val));
6788 s->cc_op = CC_OP_LOGICB;
6789 }
6790 break;
6791 case 0xd5: /* aad */
6792 if (CODE64(s))
6793 goto illegal_op;
6794 val = cpu_ldub_code(cpu_single_env, s->pc++);
6795 gen_helper_aad(cpu_env, tcg_const_i32(val));
6796 s->cc_op = CC_OP_LOGICB;
6797 break;
6798 /************************/
6799 /* misc */
6800 case 0x90: /* nop */
6801 /* XXX: correct lock test for all insn */
6802 if (prefixes & PREFIX_LOCK) {
6803 goto illegal_op;
6804 }
6805 /* If REX_B is set, then this is xchg eax, r8d, not a nop. */
6806 if (REX_B(s)) {
6807 goto do_xchg_reg_eax;
6808 }
6809 if (prefixes & PREFIX_REPZ) {
6810 gen_svm_check_intercept(s, pc_start, SVM_EXIT_PAUSE);
6811 }
6812 break;
6813 case 0x9b: /* fwait */
6814 if ((s->flags & (HF_MP_MASK | HF_TS_MASK)) ==
6815 (HF_MP_MASK | HF_TS_MASK)) {
6816 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
6817 } else {
6818 if (s->cc_op != CC_OP_DYNAMIC)
6819 gen_op_set_cc_op(s->cc_op);
6820 gen_jmp_im(pc_start - s->cs_base);
6821 gen_helper_fwait(cpu_env);
6822 }
6823 break;
6824 case 0xcc: /* int3 */
6825 gen_interrupt(s, EXCP03_INT3, pc_start - s->cs_base, s->pc - s->cs_base);
6826 break;
6827 case 0xcd: /* int N */
6828 val = cpu_ldub_code(cpu_single_env, s->pc++);
6829 if (s->vm86 && s->iopl != 3) {
6830 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6831 } else {
6832 gen_interrupt(s, val, pc_start - s->cs_base, s->pc - s->cs_base);
6833 }
6834 break;
6835 case 0xce: /* into */
6836 if (CODE64(s))
6837 goto illegal_op;
6838 if (s->cc_op != CC_OP_DYNAMIC)
6839 gen_op_set_cc_op(s->cc_op);
6840 gen_jmp_im(pc_start - s->cs_base);
6841 gen_helper_into(cpu_env, tcg_const_i32(s->pc - pc_start));
6842 break;
6843 #ifdef WANT_ICEBP
6844 case 0xf1: /* icebp (undocumented, exits to external debugger) */
6845 gen_svm_check_intercept(s, pc_start, SVM_EXIT_ICEBP);
6846 #if 1
6847 gen_debug(s, pc_start - s->cs_base);
6848 #else
6849 /* start debug */
6850 tb_flush(cpu_single_env);
6851 cpu_set_log(CPU_LOG_INT | CPU_LOG_TB_IN_ASM);
6852 #endif
6853 break;
6854 #endif
6855 case 0xfa: /* cli */
6856 if (!s->vm86) {
6857 if (s->cpl <= s->iopl) {
6858 gen_helper_cli(cpu_env);
6859 } else {
6860 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6861 }
6862 } else {
6863 if (s->iopl == 3) {
6864 gen_helper_cli(cpu_env);
6865 } else {
6866 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6867 }
6868 }
6869 break;
6870 case 0xfb: /* sti */
6871 if (!s->vm86) {
6872 if (s->cpl <= s->iopl) {
6873 gen_sti:
6874 gen_helper_sti(cpu_env);
6875 /* interruptions are enabled only the first insn after sti */
6876 /* If several instructions disable interrupts, only the
6877 _first_ does it */
6878 if (!(s->tb->flags & HF_INHIBIT_IRQ_MASK))
6879 gen_helper_set_inhibit_irq(cpu_env);
6880 /* give a chance to handle pending irqs */
6881 gen_jmp_im(s->pc - s->cs_base);
6882 gen_eob(s);
6883 } else {
6884 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6885 }
6886 } else {
6887 if (s->iopl == 3) {
6888 goto gen_sti;
6889 } else {
6890 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6891 }
6892 }
6893 break;
6894 case 0x62: /* bound */
6895 if (CODE64(s))
6896 goto illegal_op;
6897 ot = dflag ? OT_LONG : OT_WORD;
6898 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
6899 reg = (modrm >> 3) & 7;
6900 mod = (modrm >> 6) & 3;
6901 if (mod == 3)
6902 goto illegal_op;
6903 gen_op_mov_TN_reg(ot, 0, reg);
6904 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
6905 gen_jmp_im(pc_start - s->cs_base);
6906 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
6907 if (ot == OT_WORD) {
6908 gen_helper_boundw(cpu_env, cpu_A0, cpu_tmp2_i32);
6909 } else {
6910 gen_helper_boundl(cpu_env, cpu_A0, cpu_tmp2_i32);
6911 }
6912 break;
6913 case 0x1c8 ... 0x1cf: /* bswap reg */
6914 reg = (b & 7) | REX_B(s);
6915 #ifdef TARGET_X86_64
6916 if (dflag == 2) {
6917 gen_op_mov_TN_reg(OT_QUAD, 0, reg);
6918 tcg_gen_bswap64_i64(cpu_T[0], cpu_T[0]);
6919 gen_op_mov_reg_T0(OT_QUAD, reg);
6920 } else
6921 #endif
6922 {
6923 gen_op_mov_TN_reg(OT_LONG, 0, reg);
6924 tcg_gen_ext32u_tl(cpu_T[0], cpu_T[0]);
6925 tcg_gen_bswap32_tl(cpu_T[0], cpu_T[0]);
6926 gen_op_mov_reg_T0(OT_LONG, reg);
6927 }
6928 break;
6929 case 0xd6: /* salc */
6930 if (CODE64(s))
6931 goto illegal_op;
6932 if (s->cc_op != CC_OP_DYNAMIC)
6933 gen_op_set_cc_op(s->cc_op);
6934 gen_compute_eflags_c(cpu_T[0]);
6935 tcg_gen_neg_tl(cpu_T[0], cpu_T[0]);
6936 gen_op_mov_reg_T0(OT_BYTE, R_EAX);
6937 break;
6938 case 0xe0: /* loopnz */
6939 case 0xe1: /* loopz */
6940 case 0xe2: /* loop */
6941 case 0xe3: /* jecxz */
6942 {
6943 int l1, l2, l3;
6944
6945 tval = (int8_t)insn_get(s, OT_BYTE);
6946 next_eip = s->pc - s->cs_base;
6947 tval += next_eip;
6948 if (s->dflag == 0)
6949 tval &= 0xffff;
6950
6951 l1 = gen_new_label();
6952 l2 = gen_new_label();
6953 l3 = gen_new_label();
6954 b &= 3;
6955 switch(b) {
6956 case 0: /* loopnz */
6957 case 1: /* loopz */
6958 if (s->cc_op != CC_OP_DYNAMIC)
6959 gen_op_set_cc_op(s->cc_op);
6960 gen_op_add_reg_im(s->aflag, R_ECX, -1);
6961 gen_op_jz_ecx(s->aflag, l3);
6962 gen_compute_eflags(cpu_tmp0);
6963 tcg_gen_andi_tl(cpu_tmp0, cpu_tmp0, CC_Z);
6964 if (b == 0) {
6965 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, l1);
6966 } else {
6967 tcg_gen_brcondi_tl(TCG_COND_NE, cpu_tmp0, 0, l1);
6968 }
6969 break;
6970 case 2: /* loop */
6971 gen_op_add_reg_im(s->aflag, R_ECX, -1);
6972 gen_op_jnz_ecx(s->aflag, l1);
6973 break;
6974 default:
6975 case 3: /* jcxz */
6976 gen_op_jz_ecx(s->aflag, l1);
6977 break;
6978 }
6979
6980 gen_set_label(l3);
6981 gen_jmp_im(next_eip);
6982 tcg_gen_br(l2);
6983
6984 gen_set_label(l1);
6985 gen_jmp_im(tval);
6986 gen_set_label(l2);
6987 gen_eob(s);
6988 }
6989 break;
6990 case 0x130: /* wrmsr */
6991 case 0x132: /* rdmsr */
6992 if (s->cpl != 0) {
6993 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
6994 } else {
6995 if (s->cc_op != CC_OP_DYNAMIC)
6996 gen_op_set_cc_op(s->cc_op);
6997 gen_jmp_im(pc_start - s->cs_base);
6998 if (b & 2) {
6999 gen_helper_rdmsr(cpu_env);
7000 } else {
7001 gen_helper_wrmsr(cpu_env);
7002 }
7003 }
7004 break;
7005 case 0x131: /* rdtsc */
7006 if (s->cc_op != CC_OP_DYNAMIC)
7007 gen_op_set_cc_op(s->cc_op);
7008 gen_jmp_im(pc_start - s->cs_base);
7009 if (use_icount)
7010 gen_io_start();
7011 gen_helper_rdtsc(cpu_env);
7012 if (use_icount) {
7013 gen_io_end();
7014 gen_jmp(s, s->pc - s->cs_base);
7015 }
7016 break;
7017 case 0x133: /* rdpmc */
7018 if (s->cc_op != CC_OP_DYNAMIC)
7019 gen_op_set_cc_op(s->cc_op);
7020 gen_jmp_im(pc_start - s->cs_base);
7021 gen_helper_rdpmc(cpu_env);
7022 break;
7023 case 0x134: /* sysenter */
7024 /* For Intel SYSENTER is valid on 64-bit */
7025 if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
7026 goto illegal_op;
7027 if (!s->pe) {
7028 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7029 } else {
7030 gen_update_cc_op(s);
7031 gen_jmp_im(pc_start - s->cs_base);
7032 gen_helper_sysenter(cpu_env);
7033 gen_eob(s);
7034 }
7035 break;
7036 case 0x135: /* sysexit */
7037 /* For Intel SYSEXIT is valid on 64-bit */
7038 if (CODE64(s) && cpu_single_env->cpuid_vendor1 != CPUID_VENDOR_INTEL_1)
7039 goto illegal_op;
7040 if (!s->pe) {
7041 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7042 } else {
7043 gen_update_cc_op(s);
7044 gen_jmp_im(pc_start - s->cs_base);
7045 gen_helper_sysexit(cpu_env, tcg_const_i32(dflag));
7046 gen_eob(s);
7047 }
7048 break;
7049 #ifdef TARGET_X86_64
7050 case 0x105: /* syscall */
7051 /* XXX: is it usable in real mode ? */
7052 gen_update_cc_op(s);
7053 gen_jmp_im(pc_start - s->cs_base);
7054 gen_helper_syscall(cpu_env, tcg_const_i32(s->pc - pc_start));
7055 gen_eob(s);
7056 break;
7057 case 0x107: /* sysret */
7058 if (!s->pe) {
7059 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7060 } else {
7061 gen_update_cc_op(s);
7062 gen_jmp_im(pc_start - s->cs_base);
7063 gen_helper_sysret(cpu_env, tcg_const_i32(s->dflag));
7064 /* condition codes are modified only in long mode */
7065 if (s->lma)
7066 s->cc_op = CC_OP_EFLAGS;
7067 gen_eob(s);
7068 }
7069 break;
7070 #endif
7071 case 0x1a2: /* cpuid */
7072 if (s->cc_op != CC_OP_DYNAMIC)
7073 gen_op_set_cc_op(s->cc_op);
7074 gen_jmp_im(pc_start - s->cs_base);
7075 gen_helper_cpuid(cpu_env);
7076 break;
7077 case 0xf4: /* hlt */
7078 if (s->cpl != 0) {
7079 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7080 } else {
7081 if (s->cc_op != CC_OP_DYNAMIC)
7082 gen_op_set_cc_op(s->cc_op);
7083 gen_jmp_im(pc_start - s->cs_base);
7084 gen_helper_hlt(cpu_env, tcg_const_i32(s->pc - pc_start));
7085 s->is_jmp = DISAS_TB_JUMP;
7086 }
7087 break;
7088 case 0x100:
7089 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
7090 mod = (modrm >> 6) & 3;
7091 op = (modrm >> 3) & 7;
7092 switch(op) {
7093 case 0: /* sldt */
7094 if (!s->pe || s->vm86)
7095 goto illegal_op;
7096 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_READ);
7097 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,ldt.selector));
7098 ot = OT_WORD;
7099 if (mod == 3)
7100 ot += s->dflag;
7101 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
7102 break;
7103 case 2: /* lldt */
7104 if (!s->pe || s->vm86)
7105 goto illegal_op;
7106 if (s->cpl != 0) {
7107 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7108 } else {
7109 gen_svm_check_intercept(s, pc_start, SVM_EXIT_LDTR_WRITE);
7110 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7111 gen_jmp_im(pc_start - s->cs_base);
7112 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
7113 gen_helper_lldt(cpu_env, cpu_tmp2_i32);
7114 }
7115 break;
7116 case 1: /* str */
7117 if (!s->pe || s->vm86)
7118 goto illegal_op;
7119 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_READ);
7120 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,tr.selector));
7121 ot = OT_WORD;
7122 if (mod == 3)
7123 ot += s->dflag;
7124 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 1);
7125 break;
7126 case 3: /* ltr */
7127 if (!s->pe || s->vm86)
7128 goto illegal_op;
7129 if (s->cpl != 0) {
7130 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7131 } else {
7132 gen_svm_check_intercept(s, pc_start, SVM_EXIT_TR_WRITE);
7133 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7134 gen_jmp_im(pc_start - s->cs_base);
7135 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
7136 gen_helper_ltr(cpu_env, cpu_tmp2_i32);
7137 }
7138 break;
7139 case 4: /* verr */
7140 case 5: /* verw */
7141 if (!s->pe || s->vm86)
7142 goto illegal_op;
7143 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7144 if (s->cc_op != CC_OP_DYNAMIC)
7145 gen_op_set_cc_op(s->cc_op);
7146 if (op == 4) {
7147 gen_helper_verr(cpu_env, cpu_T[0]);
7148 } else {
7149 gen_helper_verw(cpu_env, cpu_T[0]);
7150 }
7151 s->cc_op = CC_OP_EFLAGS;
7152 break;
7153 default:
7154 goto illegal_op;
7155 }
7156 break;
7157 case 0x101:
7158 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
7159 mod = (modrm >> 6) & 3;
7160 op = (modrm >> 3) & 7;
7161 rm = modrm & 7;
7162 switch(op) {
7163 case 0: /* sgdt */
7164 if (mod == 3)
7165 goto illegal_op;
7166 gen_svm_check_intercept(s, pc_start, SVM_EXIT_GDTR_READ);
7167 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7168 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.limit));
7169 gen_op_st_T0_A0(OT_WORD + s->mem_index);
7170 gen_add_A0_im(s, 2);
7171 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, gdt.base));
7172 if (!s->dflag)
7173 gen_op_andl_T0_im(0xffffff);
7174 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
7175 break;
7176 case 1:
7177 if (mod == 3) {
7178 switch (rm) {
7179 case 0: /* monitor */
7180 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
7181 s->cpl != 0)
7182 goto illegal_op;
7183 if (s->cc_op != CC_OP_DYNAMIC)
7184 gen_op_set_cc_op(s->cc_op);
7185 gen_jmp_im(pc_start - s->cs_base);
7186 #ifdef TARGET_X86_64
7187 if (s->aflag == 2) {
7188 gen_op_movq_A0_reg(R_EAX);
7189 } else
7190 #endif
7191 {
7192 gen_op_movl_A0_reg(R_EAX);
7193 if (s->aflag == 0)
7194 gen_op_andl_A0_ffff();
7195 }
7196 gen_add_A0_ds_seg(s);
7197 gen_helper_monitor(cpu_env, cpu_A0);
7198 break;
7199 case 1: /* mwait */
7200 if (!(s->cpuid_ext_features & CPUID_EXT_MONITOR) ||
7201 s->cpl != 0)
7202 goto illegal_op;
7203 gen_update_cc_op(s);
7204 gen_jmp_im(pc_start - s->cs_base);
7205 gen_helper_mwait(cpu_env, tcg_const_i32(s->pc - pc_start));
7206 gen_eob(s);
7207 break;
7208 default:
7209 goto illegal_op;
7210 }
7211 } else { /* sidt */
7212 gen_svm_check_intercept(s, pc_start, SVM_EXIT_IDTR_READ);
7213 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7214 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.limit));
7215 gen_op_st_T0_A0(OT_WORD + s->mem_index);
7216 gen_add_A0_im(s, 2);
7217 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, idt.base));
7218 if (!s->dflag)
7219 gen_op_andl_T0_im(0xffffff);
7220 gen_op_st_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
7221 }
7222 break;
7223 case 2: /* lgdt */
7224 case 3: /* lidt */
7225 if (mod == 3) {
7226 if (s->cc_op != CC_OP_DYNAMIC)
7227 gen_op_set_cc_op(s->cc_op);
7228 gen_jmp_im(pc_start - s->cs_base);
7229 switch(rm) {
7230 case 0: /* VMRUN */
7231 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7232 goto illegal_op;
7233 if (s->cpl != 0) {
7234 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7235 break;
7236 } else {
7237 gen_helper_vmrun(cpu_env, tcg_const_i32(s->aflag),
7238 tcg_const_i32(s->pc - pc_start));
7239 tcg_gen_exit_tb(0);
7240 s->is_jmp = DISAS_TB_JUMP;
7241 }
7242 break;
7243 case 1: /* VMMCALL */
7244 if (!(s->flags & HF_SVME_MASK))
7245 goto illegal_op;
7246 gen_helper_vmmcall(cpu_env);
7247 break;
7248 case 2: /* VMLOAD */
7249 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7250 goto illegal_op;
7251 if (s->cpl != 0) {
7252 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7253 break;
7254 } else {
7255 gen_helper_vmload(cpu_env, tcg_const_i32(s->aflag));
7256 }
7257 break;
7258 case 3: /* VMSAVE */
7259 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7260 goto illegal_op;
7261 if (s->cpl != 0) {
7262 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7263 break;
7264 } else {
7265 gen_helper_vmsave(cpu_env, tcg_const_i32(s->aflag));
7266 }
7267 break;
7268 case 4: /* STGI */
7269 if ((!(s->flags & HF_SVME_MASK) &&
7270 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
7271 !s->pe)
7272 goto illegal_op;
7273 if (s->cpl != 0) {
7274 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7275 break;
7276 } else {
7277 gen_helper_stgi(cpu_env);
7278 }
7279 break;
7280 case 5: /* CLGI */
7281 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7282 goto illegal_op;
7283 if (s->cpl != 0) {
7284 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7285 break;
7286 } else {
7287 gen_helper_clgi(cpu_env);
7288 }
7289 break;
7290 case 6: /* SKINIT */
7291 if ((!(s->flags & HF_SVME_MASK) &&
7292 !(s->cpuid_ext3_features & CPUID_EXT3_SKINIT)) ||
7293 !s->pe)
7294 goto illegal_op;
7295 gen_helper_skinit(cpu_env);
7296 break;
7297 case 7: /* INVLPGA */
7298 if (!(s->flags & HF_SVME_MASK) || !s->pe)
7299 goto illegal_op;
7300 if (s->cpl != 0) {
7301 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7302 break;
7303 } else {
7304 gen_helper_invlpga(cpu_env, tcg_const_i32(s->aflag));
7305 }
7306 break;
7307 default:
7308 goto illegal_op;
7309 }
7310 } else if (s->cpl != 0) {
7311 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7312 } else {
7313 gen_svm_check_intercept(s, pc_start,
7314 op==2 ? SVM_EXIT_GDTR_WRITE : SVM_EXIT_IDTR_WRITE);
7315 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7316 gen_op_ld_T1_A0(OT_WORD + s->mem_index);
7317 gen_add_A0_im(s, 2);
7318 gen_op_ld_T0_A0(CODE64(s) + OT_LONG + s->mem_index);
7319 if (!s->dflag)
7320 gen_op_andl_T0_im(0xffffff);
7321 if (op == 2) {
7322 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,gdt.base));
7323 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,gdt.limit));
7324 } else {
7325 tcg_gen_st_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,idt.base));
7326 tcg_gen_st32_tl(cpu_T[1], cpu_env, offsetof(CPUX86State,idt.limit));
7327 }
7328 }
7329 break;
7330 case 4: /* smsw */
7331 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_CR0);
7332 #if defined TARGET_X86_64 && defined HOST_WORDS_BIGENDIAN
7333 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]) + 4);
7334 #else
7335 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,cr[0]));
7336 #endif
7337 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 1);
7338 break;
7339 case 6: /* lmsw */
7340 if (s->cpl != 0) {
7341 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7342 } else {
7343 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
7344 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7345 gen_helper_lmsw(cpu_env, cpu_T[0]);
7346 gen_jmp_im(s->pc - s->cs_base);
7347 gen_eob(s);
7348 }
7349 break;
7350 case 7:
7351 if (mod != 3) { /* invlpg */
7352 if (s->cpl != 0) {
7353 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7354 } else {
7355 if (s->cc_op != CC_OP_DYNAMIC)
7356 gen_op_set_cc_op(s->cc_op);
7357 gen_jmp_im(pc_start - s->cs_base);
7358 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7359 gen_helper_invlpg(cpu_env, cpu_A0);
7360 gen_jmp_im(s->pc - s->cs_base);
7361 gen_eob(s);
7362 }
7363 } else {
7364 switch (rm) {
7365 case 0: /* swapgs */
7366 #ifdef TARGET_X86_64
7367 if (CODE64(s)) {
7368 if (s->cpl != 0) {
7369 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7370 } else {
7371 tcg_gen_ld_tl(cpu_T[0], cpu_env,
7372 offsetof(CPUX86State,segs[R_GS].base));
7373 tcg_gen_ld_tl(cpu_T[1], cpu_env,
7374 offsetof(CPUX86State,kernelgsbase));
7375 tcg_gen_st_tl(cpu_T[1], cpu_env,
7376 offsetof(CPUX86State,segs[R_GS].base));
7377 tcg_gen_st_tl(cpu_T[0], cpu_env,
7378 offsetof(CPUX86State,kernelgsbase));
7379 }
7380 } else
7381 #endif
7382 {
7383 goto illegal_op;
7384 }
7385 break;
7386 case 1: /* rdtscp */
7387 if (!(s->cpuid_ext2_features & CPUID_EXT2_RDTSCP))
7388 goto illegal_op;
7389 if (s->cc_op != CC_OP_DYNAMIC)
7390 gen_op_set_cc_op(s->cc_op);
7391 gen_jmp_im(pc_start - s->cs_base);
7392 if (use_icount)
7393 gen_io_start();
7394 gen_helper_rdtscp(cpu_env);
7395 if (use_icount) {
7396 gen_io_end();
7397 gen_jmp(s, s->pc - s->cs_base);
7398 }
7399 break;
7400 default:
7401 goto illegal_op;
7402 }
7403 }
7404 break;
7405 default:
7406 goto illegal_op;
7407 }
7408 break;
7409 case 0x108: /* invd */
7410 case 0x109: /* wbinvd */
7411 if (s->cpl != 0) {
7412 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7413 } else {
7414 gen_svm_check_intercept(s, pc_start, (b & 2) ? SVM_EXIT_INVD : SVM_EXIT_WBINVD);
7415 /* nothing to do */
7416 }
7417 break;
7418 case 0x63: /* arpl or movslS (x86_64) */
7419 #ifdef TARGET_X86_64
7420 if (CODE64(s)) {
7421 int d_ot;
7422 /* d_ot is the size of destination */
7423 d_ot = dflag + OT_WORD;
7424
7425 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
7426 reg = ((modrm >> 3) & 7) | rex_r;
7427 mod = (modrm >> 6) & 3;
7428 rm = (modrm & 7) | REX_B(s);
7429
7430 if (mod == 3) {
7431 gen_op_mov_TN_reg(OT_LONG, 0, rm);
7432 /* sign extend */
7433 if (d_ot == OT_QUAD)
7434 tcg_gen_ext32s_tl(cpu_T[0], cpu_T[0]);
7435 gen_op_mov_reg_T0(d_ot, reg);
7436 } else {
7437 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7438 if (d_ot == OT_QUAD) {
7439 gen_op_lds_T0_A0(OT_LONG + s->mem_index);
7440 } else {
7441 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
7442 }
7443 gen_op_mov_reg_T0(d_ot, reg);
7444 }
7445 } else
7446 #endif
7447 {
7448 int label1;
7449 TCGv t0, t1, t2, a0;
7450
7451 if (!s->pe || s->vm86)
7452 goto illegal_op;
7453 t0 = tcg_temp_local_new();
7454 t1 = tcg_temp_local_new();
7455 t2 = tcg_temp_local_new();
7456 ot = OT_WORD;
7457 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
7458 reg = (modrm >> 3) & 7;
7459 mod = (modrm >> 6) & 3;
7460 rm = modrm & 7;
7461 if (mod != 3) {
7462 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7463 gen_op_ld_v(ot + s->mem_index, t0, cpu_A0);
7464 a0 = tcg_temp_local_new();
7465 tcg_gen_mov_tl(a0, cpu_A0);
7466 } else {
7467 gen_op_mov_v_reg(ot, t0, rm);
7468 TCGV_UNUSED(a0);
7469 }
7470 gen_op_mov_v_reg(ot, t1, reg);
7471 tcg_gen_andi_tl(cpu_tmp0, t0, 3);
7472 tcg_gen_andi_tl(t1, t1, 3);
7473 tcg_gen_movi_tl(t2, 0);
7474 label1 = gen_new_label();
7475 tcg_gen_brcond_tl(TCG_COND_GE, cpu_tmp0, t1, label1);
7476 tcg_gen_andi_tl(t0, t0, ~3);
7477 tcg_gen_or_tl(t0, t0, t1);
7478 tcg_gen_movi_tl(t2, CC_Z);
7479 gen_set_label(label1);
7480 if (mod != 3) {
7481 gen_op_st_v(ot + s->mem_index, t0, a0);
7482 tcg_temp_free(a0);
7483 } else {
7484 gen_op_mov_reg_v(ot, rm, t0);
7485 }
7486 if (s->cc_op != CC_OP_DYNAMIC)
7487 gen_op_set_cc_op(s->cc_op);
7488 gen_compute_eflags(cpu_cc_src);
7489 tcg_gen_andi_tl(cpu_cc_src, cpu_cc_src, ~CC_Z);
7490 tcg_gen_or_tl(cpu_cc_src, cpu_cc_src, t2);
7491 s->cc_op = CC_OP_EFLAGS;
7492 tcg_temp_free(t0);
7493 tcg_temp_free(t1);
7494 tcg_temp_free(t2);
7495 }
7496 break;
7497 case 0x102: /* lar */
7498 case 0x103: /* lsl */
7499 {
7500 int label1;
7501 TCGv t0;
7502 if (!s->pe || s->vm86)
7503 goto illegal_op;
7504 ot = dflag ? OT_LONG : OT_WORD;
7505 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
7506 reg = ((modrm >> 3) & 7) | rex_r;
7507 gen_ldst_modrm(s, modrm, OT_WORD, OR_TMP0, 0);
7508 t0 = tcg_temp_local_new();
7509 if (s->cc_op != CC_OP_DYNAMIC)
7510 gen_op_set_cc_op(s->cc_op);
7511 if (b == 0x102) {
7512 gen_helper_lar(t0, cpu_env, cpu_T[0]);
7513 } else {
7514 gen_helper_lsl(t0, cpu_env, cpu_T[0]);
7515 }
7516 tcg_gen_andi_tl(cpu_tmp0, cpu_cc_src, CC_Z);
7517 label1 = gen_new_label();
7518 tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_tmp0, 0, label1);
7519 gen_op_mov_reg_v(ot, reg, t0);
7520 gen_set_label(label1);
7521 s->cc_op = CC_OP_EFLAGS;
7522 tcg_temp_free(t0);
7523 }
7524 break;
7525 case 0x118:
7526 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
7527 mod = (modrm >> 6) & 3;
7528 op = (modrm >> 3) & 7;
7529 switch(op) {
7530 case 0: /* prefetchnta */
7531 case 1: /* prefetchnt0 */
7532 case 2: /* prefetchnt0 */
7533 case 3: /* prefetchnt0 */
7534 if (mod == 3)
7535 goto illegal_op;
7536 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7537 /* nothing more to do */
7538 break;
7539 default: /* nop (multi byte) */
7540 gen_nop_modrm(s, modrm);
7541 break;
7542 }
7543 break;
7544 case 0x119 ... 0x11f: /* nop (multi byte) */
7545 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
7546 gen_nop_modrm(s, modrm);
7547 break;
7548 case 0x120: /* mov reg, crN */
7549 case 0x122: /* mov crN, reg */
7550 if (s->cpl != 0) {
7551 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7552 } else {
7553 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
7554 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7555 * AMD documentation (24594.pdf) and testing of
7556 * intel 386 and 486 processors all show that the mod bits
7557 * are assumed to be 1's, regardless of actual values.
7558 */
7559 rm = (modrm & 7) | REX_B(s);
7560 reg = ((modrm >> 3) & 7) | rex_r;
7561 if (CODE64(s))
7562 ot = OT_QUAD;
7563 else
7564 ot = OT_LONG;
7565 if ((prefixes & PREFIX_LOCK) && (reg == 0) &&
7566 (s->cpuid_ext3_features & CPUID_EXT3_CR8LEG)) {
7567 reg = 8;
7568 }
7569 switch(reg) {
7570 case 0:
7571 case 2:
7572 case 3:
7573 case 4:
7574 case 8:
7575 if (s->cc_op != CC_OP_DYNAMIC)
7576 gen_op_set_cc_op(s->cc_op);
7577 gen_jmp_im(pc_start - s->cs_base);
7578 if (b & 2) {
7579 gen_op_mov_TN_reg(ot, 0, rm);
7580 gen_helper_write_crN(cpu_env, tcg_const_i32(reg),
7581 cpu_T[0]);
7582 gen_jmp_im(s->pc - s->cs_base);
7583 gen_eob(s);
7584 } else {
7585 gen_helper_read_crN(cpu_T[0], cpu_env, tcg_const_i32(reg));
7586 gen_op_mov_reg_T0(ot, rm);
7587 }
7588 break;
7589 default:
7590 goto illegal_op;
7591 }
7592 }
7593 break;
7594 case 0x121: /* mov reg, drN */
7595 case 0x123: /* mov drN, reg */
7596 if (s->cpl != 0) {
7597 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7598 } else {
7599 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
7600 /* Ignore the mod bits (assume (modrm&0xc0)==0xc0).
7601 * AMD documentation (24594.pdf) and testing of
7602 * intel 386 and 486 processors all show that the mod bits
7603 * are assumed to be 1's, regardless of actual values.
7604 */
7605 rm = (modrm & 7) | REX_B(s);
7606 reg = ((modrm >> 3) & 7) | rex_r;
7607 if (CODE64(s))
7608 ot = OT_QUAD;
7609 else
7610 ot = OT_LONG;
7611 /* XXX: do it dynamically with CR4.DE bit */
7612 if (reg == 4 || reg == 5 || reg >= 8)
7613 goto illegal_op;
7614 if (b & 2) {
7615 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_DR0 + reg);
7616 gen_op_mov_TN_reg(ot, 0, rm);
7617 gen_helper_movl_drN_T0(cpu_env, tcg_const_i32(reg), cpu_T[0]);
7618 gen_jmp_im(s->pc - s->cs_base);
7619 gen_eob(s);
7620 } else {
7621 gen_svm_check_intercept(s, pc_start, SVM_EXIT_READ_DR0 + reg);
7622 tcg_gen_ld_tl(cpu_T[0], cpu_env, offsetof(CPUX86State,dr[reg]));
7623 gen_op_mov_reg_T0(ot, rm);
7624 }
7625 }
7626 break;
7627 case 0x106: /* clts */
7628 if (s->cpl != 0) {
7629 gen_exception(s, EXCP0D_GPF, pc_start - s->cs_base);
7630 } else {
7631 gen_svm_check_intercept(s, pc_start, SVM_EXIT_WRITE_CR0);
7632 gen_helper_clts(cpu_env);
7633 /* abort block because static cpu state changed */
7634 gen_jmp_im(s->pc - s->cs_base);
7635 gen_eob(s);
7636 }
7637 break;
7638 /* MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4 support */
7639 case 0x1c3: /* MOVNTI reg, mem */
7640 if (!(s->cpuid_features & CPUID_SSE2))
7641 goto illegal_op;
7642 ot = s->dflag == 2 ? OT_QUAD : OT_LONG;
7643 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
7644 mod = (modrm >> 6) & 3;
7645 if (mod == 3)
7646 goto illegal_op;
7647 reg = ((modrm >> 3) & 7) | rex_r;
7648 /* generate a generic store */
7649 gen_ldst_modrm(s, modrm, ot, reg, 1);
7650 break;
7651 case 0x1ae:
7652 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
7653 mod = (modrm >> 6) & 3;
7654 op = (modrm >> 3) & 7;
7655 switch(op) {
7656 case 0: /* fxsave */
7657 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
7658 (s->prefix & PREFIX_LOCK))
7659 goto illegal_op;
7660 if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) {
7661 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7662 break;
7663 }
7664 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7665 if (s->cc_op != CC_OP_DYNAMIC)
7666 gen_op_set_cc_op(s->cc_op);
7667 gen_jmp_im(pc_start - s->cs_base);
7668 gen_helper_fxsave(cpu_env, cpu_A0, tcg_const_i32((s->dflag == 2)));
7669 break;
7670 case 1: /* fxrstor */
7671 if (mod == 3 || !(s->cpuid_features & CPUID_FXSR) ||
7672 (s->prefix & PREFIX_LOCK))
7673 goto illegal_op;
7674 if ((s->flags & HF_EM_MASK) || (s->flags & HF_TS_MASK)) {
7675 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7676 break;
7677 }
7678 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7679 if (s->cc_op != CC_OP_DYNAMIC)
7680 gen_op_set_cc_op(s->cc_op);
7681 gen_jmp_im(pc_start - s->cs_base);
7682 gen_helper_fxrstor(cpu_env, cpu_A0,
7683 tcg_const_i32((s->dflag == 2)));
7684 break;
7685 case 2: /* ldmxcsr */
7686 case 3: /* stmxcsr */
7687 if (s->flags & HF_TS_MASK) {
7688 gen_exception(s, EXCP07_PREX, pc_start - s->cs_base);
7689 break;
7690 }
7691 if ((s->flags & HF_EM_MASK) || !(s->flags & HF_OSFXSR_MASK) ||
7692 mod == 3)
7693 goto illegal_op;
7694 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7695 if (op == 2) {
7696 gen_op_ld_T0_A0(OT_LONG + s->mem_index);
7697 tcg_gen_trunc_tl_i32(cpu_tmp2_i32, cpu_T[0]);
7698 gen_helper_ldmxcsr(cpu_env, cpu_tmp2_i32);
7699 } else {
7700 tcg_gen_ld32u_tl(cpu_T[0], cpu_env, offsetof(CPUX86State, mxcsr));
7701 gen_op_st_T0_A0(OT_LONG + s->mem_index);
7702 }
7703 break;
7704 case 5: /* lfence */
7705 case 6: /* mfence */
7706 if ((modrm & 0xc7) != 0xc0 || !(s->cpuid_features & CPUID_SSE2))
7707 goto illegal_op;
7708 break;
7709 case 7: /* sfence / clflush */
7710 if ((modrm & 0xc7) == 0xc0) {
7711 /* sfence */
7712 /* XXX: also check for cpuid_ext2_features & CPUID_EXT2_EMMX */
7713 if (!(s->cpuid_features & CPUID_SSE))
7714 goto illegal_op;
7715 } else {
7716 /* clflush */
7717 if (!(s->cpuid_features & CPUID_CLFLUSH))
7718 goto illegal_op;
7719 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7720 }
7721 break;
7722 default:
7723 goto illegal_op;
7724 }
7725 break;
7726 case 0x10d: /* 3DNow! prefetch(w) */
7727 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
7728 mod = (modrm >> 6) & 3;
7729 if (mod == 3)
7730 goto illegal_op;
7731 gen_lea_modrm(s, modrm, &reg_addr, &offset_addr);
7732 /* ignore for now */
7733 break;
7734 case 0x1aa: /* rsm */
7735 gen_svm_check_intercept(s, pc_start, SVM_EXIT_RSM);
7736 if (!(s->flags & HF_SMM_MASK))
7737 goto illegal_op;
7738 gen_update_cc_op(s);
7739 gen_jmp_im(s->pc - s->cs_base);
7740 gen_helper_rsm(cpu_env);
7741 gen_eob(s);
7742 break;
7743 case 0x1b8: /* SSE4.2 popcnt */
7744 if ((prefixes & (PREFIX_REPZ | PREFIX_LOCK | PREFIX_REPNZ)) !=
7745 PREFIX_REPZ)
7746 goto illegal_op;
7747 if (!(s->cpuid_ext_features & CPUID_EXT_POPCNT))
7748 goto illegal_op;
7749
7750 modrm = cpu_ldub_code(cpu_single_env, s->pc++);
7751 reg = ((modrm >> 3) & 7);
7752
7753 if (s->prefix & PREFIX_DATA)
7754 ot = OT_WORD;
7755 else if (s->dflag != 2)
7756 ot = OT_LONG;
7757 else
7758 ot = OT_QUAD;
7759
7760 gen_ldst_modrm(s, modrm, ot, OR_TMP0, 0);
7761 gen_helper_popcnt(cpu_T[0], cpu_env, cpu_T[0], tcg_const_i32(ot));
7762 gen_op_mov_reg_T0(ot, reg);
7763
7764 s->cc_op = CC_OP_EFLAGS;
7765 break;
7766 case 0x10e ... 0x10f:
7767 /* 3DNow! instructions, ignore prefixes */
7768 s->prefix &= ~(PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA);
7769 case 0x110 ... 0x117:
7770 case 0x128 ... 0x12f:
7771 case 0x138 ... 0x13a:
7772 case 0x150 ... 0x179:
7773 case 0x17c ... 0x17f:
7774 case 0x1c2:
7775 case 0x1c4 ... 0x1c6:
7776 case 0x1d0 ... 0x1fe:
7777 gen_sse(s, b, pc_start, rex_r);
7778 break;
7779 default:
7780 goto illegal_op;
7781 }
7782 /* lock generation */
7783 if (s->prefix & PREFIX_LOCK)
7784 gen_helper_unlock();
7785 return s->pc;
7786 illegal_op:
7787 if (s->prefix & PREFIX_LOCK)
7788 gen_helper_unlock();
7789 /* XXX: ensure that no lock was generated */
7790 gen_exception(s, EXCP06_ILLOP, pc_start - s->cs_base);
7791 return s->pc;
7792 }
7793
7794 void optimize_flags_init(void)
7795 {
7796 cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env");
7797 cpu_cc_op = tcg_global_mem_new_i32(TCG_AREG0,
7798 offsetof(CPUX86State, cc_op), "cc_op");
7799 cpu_cc_src = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_src),
7800 "cc_src");
7801 cpu_cc_dst = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_dst),
7802 "cc_dst");
7803 cpu_cc_tmp = tcg_global_mem_new(TCG_AREG0, offsetof(CPUX86State, cc_tmp),
7804 "cc_tmp");
7805
7806 #ifdef TARGET_X86_64
7807 cpu_regs[R_EAX] = tcg_global_mem_new_i64(TCG_AREG0,
7808 offsetof(CPUX86State, regs[R_EAX]), "rax");
7809 cpu_regs[R_ECX] = tcg_global_mem_new_i64(TCG_AREG0,
7810 offsetof(CPUX86State, regs[R_ECX]), "rcx");
7811 cpu_regs[R_EDX] = tcg_global_mem_new_i64(TCG_AREG0,
7812 offsetof(CPUX86State, regs[R_EDX]), "rdx");
7813 cpu_regs[R_EBX] = tcg_global_mem_new_i64(TCG_AREG0,
7814 offsetof(CPUX86State, regs[R_EBX]), "rbx");
7815 cpu_regs[R_ESP] = tcg_global_mem_new_i64(TCG_AREG0,
7816 offsetof(CPUX86State, regs[R_ESP]), "rsp");
7817 cpu_regs[R_EBP] = tcg_global_mem_new_i64(TCG_AREG0,
7818 offsetof(CPUX86State, regs[R_EBP]), "rbp");
7819 cpu_regs[R_ESI] = tcg_global_mem_new_i64(TCG_AREG0,
7820 offsetof(CPUX86State, regs[R_ESI]), "rsi");
7821 cpu_regs[R_EDI] = tcg_global_mem_new_i64(TCG_AREG0,
7822 offsetof(CPUX86State, regs[R_EDI]), "rdi");
7823 cpu_regs[8] = tcg_global_mem_new_i64(TCG_AREG0,
7824 offsetof(CPUX86State, regs[8]), "r8");
7825 cpu_regs[9] = tcg_global_mem_new_i64(TCG_AREG0,
7826 offsetof(CPUX86State, regs[9]), "r9");
7827 cpu_regs[10] = tcg_global_mem_new_i64(TCG_AREG0,
7828 offsetof(CPUX86State, regs[10]), "r10");
7829 cpu_regs[11] = tcg_global_mem_new_i64(TCG_AREG0,
7830 offsetof(CPUX86State, regs[11]), "r11");
7831 cpu_regs[12] = tcg_global_mem_new_i64(TCG_AREG0,
7832 offsetof(CPUX86State, regs[12]), "r12");
7833 cpu_regs[13] = tcg_global_mem_new_i64(TCG_AREG0,
7834 offsetof(CPUX86State, regs[13]), "r13");
7835 cpu_regs[14] = tcg_global_mem_new_i64(TCG_AREG0,
7836 offsetof(CPUX86State, regs[14]), "r14");
7837 cpu_regs[15] = tcg_global_mem_new_i64(TCG_AREG0,
7838 offsetof(CPUX86State, regs[15]), "r15");
7839 #else
7840 cpu_regs[R_EAX] = tcg_global_mem_new_i32(TCG_AREG0,
7841 offsetof(CPUX86State, regs[R_EAX]), "eax");
7842 cpu_regs[R_ECX] = tcg_global_mem_new_i32(TCG_AREG0,
7843 offsetof(CPUX86State, regs[R_ECX]), "ecx");
7844 cpu_regs[R_EDX] = tcg_global_mem_new_i32(TCG_AREG0,
7845 offsetof(CPUX86State, regs[R_EDX]), "edx");
7846 cpu_regs[R_EBX] = tcg_global_mem_new_i32(TCG_AREG0,
7847 offsetof(CPUX86State, regs[R_EBX]), "ebx");
7848 cpu_regs[R_ESP] = tcg_global_mem_new_i32(TCG_AREG0,
7849 offsetof(CPUX86State, regs[R_ESP]), "esp");
7850 cpu_regs[R_EBP] = tcg_global_mem_new_i32(TCG_AREG0,
7851 offsetof(CPUX86State, regs[R_EBP]), "ebp");
7852 cpu_regs[R_ESI] = tcg_global_mem_new_i32(TCG_AREG0,
7853 offsetof(CPUX86State, regs[R_ESI]), "esi");
7854 cpu_regs[R_EDI] = tcg_global_mem_new_i32(TCG_AREG0,
7855 offsetof(CPUX86State, regs[R_EDI]), "edi");
7856 #endif
7857
7858 /* register helpers */
7859 #define GEN_HELPER 2
7860 #include "helper.h"
7861 }
7862
7863 /* generate intermediate code in gen_opc_buf and gen_opparam_buf for
7864 basic block 'tb'. If search_pc is TRUE, also generate PC
7865 information for each intermediate instruction. */
7866 static inline void gen_intermediate_code_internal(CPUX86State *env,
7867 TranslationBlock *tb,
7868 int search_pc)
7869 {
7870 DisasContext dc1, *dc = &dc1;
7871 target_ulong pc_ptr;
7872 uint16_t *gen_opc_end;
7873 CPUBreakpoint *bp;
7874 int j, lj;
7875 uint64_t flags;
7876 target_ulong pc_start;
7877 target_ulong cs_base;
7878 int num_insns;
7879 int max_insns;
7880
7881 /* generate intermediate code */
7882 pc_start = tb->pc;
7883 cs_base = tb->cs_base;
7884 flags = tb->flags;
7885
7886 dc->pe = (flags >> HF_PE_SHIFT) & 1;
7887 dc->code32 = (flags >> HF_CS32_SHIFT) & 1;
7888 dc->ss32 = (flags >> HF_SS32_SHIFT) & 1;
7889 dc->addseg = (flags >> HF_ADDSEG_SHIFT) & 1;
7890 dc->f_st = 0;
7891 dc->vm86 = (flags >> VM_SHIFT) & 1;
7892 dc->cpl = (flags >> HF_CPL_SHIFT) & 3;
7893 dc->iopl = (flags >> IOPL_SHIFT) & 3;
7894 dc->tf = (flags >> TF_SHIFT) & 1;
7895 dc->singlestep_enabled = env->singlestep_enabled;
7896 dc->cc_op = CC_OP_DYNAMIC;
7897 dc->cs_base = cs_base;
7898 dc->tb = tb;
7899 dc->popl_esp_hack = 0;
7900 /* select memory access functions */
7901 dc->mem_index = 0;
7902 if (flags & HF_SOFTMMU_MASK) {
7903 if (dc->cpl == 3)
7904 dc->mem_index = 2 * 4;
7905 else
7906 dc->mem_index = 1 * 4;
7907 }
7908 dc->cpuid_features = env->cpuid_features;
7909 dc->cpuid_ext_features = env->cpuid_ext_features;
7910 dc->cpuid_ext2_features = env->cpuid_ext2_features;
7911 dc->cpuid_ext3_features = env->cpuid_ext3_features;
7912 #ifdef TARGET_X86_64
7913 dc->lma = (flags >> HF_LMA_SHIFT) & 1;
7914 dc->code64 = (flags >> HF_CS64_SHIFT) & 1;
7915 #endif
7916 dc->flags = flags;
7917 dc->jmp_opt = !(dc->tf || env->singlestep_enabled ||
7918 (flags & HF_INHIBIT_IRQ_MASK)
7919 #ifndef CONFIG_SOFTMMU
7920 || (flags & HF_SOFTMMU_MASK)
7921 #endif
7922 );
7923 #if 0
7924 /* check addseg logic */
7925 if (!dc->addseg && (dc->vm86 || !dc->pe || !dc->code32))
7926 printf("ERROR addseg\n");
7927 #endif
7928
7929 cpu_T[0] = tcg_temp_new();
7930 cpu_T[1] = tcg_temp_new();
7931 cpu_A0 = tcg_temp_new();
7932 cpu_T3 = tcg_temp_new();
7933
7934 cpu_tmp0 = tcg_temp_new();
7935 cpu_tmp1_i64 = tcg_temp_new_i64();
7936 cpu_tmp2_i32 = tcg_temp_new_i32();
7937 cpu_tmp3_i32 = tcg_temp_new_i32();
7938 cpu_tmp4 = tcg_temp_new();
7939 cpu_tmp5 = tcg_temp_new();
7940 cpu_ptr0 = tcg_temp_new_ptr();
7941 cpu_ptr1 = tcg_temp_new_ptr();
7942
7943 gen_opc_end = gen_opc_buf + OPC_MAX_SIZE;
7944
7945 dc->is_jmp = DISAS_NEXT;
7946 pc_ptr = pc_start;
7947 lj = -1;
7948 num_insns = 0;
7949 max_insns = tb->cflags & CF_COUNT_MASK;
7950 if (max_insns == 0)
7951 max_insns = CF_COUNT_MASK;
7952
7953 gen_icount_start();
7954 for(;;) {
7955 if (unlikely(!QTAILQ_EMPTY(&env->breakpoints))) {
7956 QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
7957 if (bp->pc == pc_ptr &&
7958 !((bp->flags & BP_CPU) && (tb->flags & HF_RF_MASK))) {
7959 gen_debug(dc, pc_ptr - dc->cs_base);
7960 break;
7961 }
7962 }
7963 }
7964 if (search_pc) {
7965 j = gen_opc_ptr - gen_opc_buf;
7966 if (lj < j) {
7967 lj++;
7968 while (lj < j)
7969 gen_opc_instr_start[lj++] = 0;
7970 }
7971 gen_opc_pc[lj] = pc_ptr;
7972 gen_opc_cc_op[lj] = dc->cc_op;
7973 gen_opc_instr_start[lj] = 1;
7974 gen_opc_icount[lj] = num_insns;
7975 }
7976 if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO))
7977 gen_io_start();
7978
7979 pc_ptr = disas_insn(dc, pc_ptr);
7980 num_insns++;
7981 /* stop translation if indicated */
7982 if (dc->is_jmp)
7983 break;
7984 /* if single step mode, we generate only one instruction and
7985 generate an exception */
7986 /* if irq were inhibited with HF_INHIBIT_IRQ_MASK, we clear
7987 the flag and abort the translation to give the irqs a
7988 change to be happen */
7989 if (dc->tf || dc->singlestep_enabled ||
7990 (flags & HF_INHIBIT_IRQ_MASK)) {
7991 gen_jmp_im(pc_ptr - dc->cs_base);
7992 gen_eob(dc);
7993 break;
7994 }
7995 /* if too long translation, stop generation too */
7996 if (gen_opc_ptr >= gen_opc_end ||
7997 (pc_ptr - pc_start) >= (TARGET_PAGE_SIZE - 32) ||
7998 num_insns >= max_insns) {
7999 gen_jmp_im(pc_ptr - dc->cs_base);
8000 gen_eob(dc);
8001 break;
8002 }
8003 if (singlestep) {
8004 gen_jmp_im(pc_ptr - dc->cs_base);
8005 gen_eob(dc);
8006 break;
8007 }
8008 }
8009 if (tb->cflags & CF_LAST_IO)
8010 gen_io_end();
8011 gen_icount_end(tb, num_insns);
8012 *gen_opc_ptr = INDEX_op_end;
8013 /* we don't forget to fill the last values */
8014 if (search_pc) {
8015 j = gen_opc_ptr - gen_opc_buf;
8016 lj++;
8017 while (lj <= j)
8018 gen_opc_instr_start[lj++] = 0;
8019 }
8020
8021 #ifdef DEBUG_DISAS
8022 if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) {
8023 int disas_flags;
8024 qemu_log("----------------\n");
8025 qemu_log("IN: %s\n", lookup_symbol(pc_start));
8026 #ifdef TARGET_X86_64
8027 if (dc->code64)
8028 disas_flags = 2;
8029 else
8030 #endif
8031 disas_flags = !dc->code32;
8032 log_target_disas(pc_start, pc_ptr - pc_start, disas_flags);
8033 qemu_log("\n");
8034 }
8035 #endif
8036
8037 if (!search_pc) {
8038 tb->size = pc_ptr - pc_start;
8039 tb->icount = num_insns;
8040 }
8041 }
8042
8043 void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
8044 {
8045 gen_intermediate_code_internal(env, tb, 0);
8046 }
8047
8048 void gen_intermediate_code_pc(CPUX86State *env, TranslationBlock *tb)
8049 {
8050 gen_intermediate_code_internal(env, tb, 1);
8051 }
8052
8053 void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, int pc_pos)
8054 {
8055 int cc_op;
8056 #ifdef DEBUG_DISAS
8057 if (qemu_loglevel_mask(CPU_LOG_TB_OP)) {
8058 int i;
8059 qemu_log("RESTORE:\n");
8060 for(i = 0;i <= pc_pos; i++) {
8061 if (gen_opc_instr_start[i]) {
8062 qemu_log("0x%04x: " TARGET_FMT_lx "\n", i, gen_opc_pc[i]);
8063 }
8064 }
8065 qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n",
8066 pc_pos, gen_opc_pc[pc_pos] - tb->cs_base,
8067 (uint32_t)tb->cs_base);
8068 }
8069 #endif
8070 env->eip = gen_opc_pc[pc_pos] - tb->cs_base;
8071 cc_op = gen_opc_cc_op[pc_pos];
8072 if (cc_op != CC_OP_DYNAMIC)
8073 env->cc_op = cc_op;
8074 }
QEMU modified to work with kvm