hw/char/lm32_uart.c

   1 /*
   2  *  QEMU model of the LatticeMico32 UART block.
   3  *
   4  *  Copyright (c) 2010 Michael Walle <michael@walle.cc>
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  *
  19  *
  20  * Specification available at:
  21  *   http://www.latticesemi.com/documents/mico32uart.pdf
  22  */
  23
  24
  25 #include "hw/hw.h"
  26 #include "hw/sysbus.h"
  27 #include "trace.h"
  28 #include "sysemu/char.h"
  29 #include "qemu/error-report.h"
  30
  31 enum {
  32     R_RXTX = 0,
  33     R_IER,
  34     R_IIR,
  35     R_LCR,
  36     R_MCR,
  37     R_LSR,
  38     R_MSR,
  39     R_DIV,
  40     R_MAX
  41 };
  42
  43 enum {
  44     IER_RBRI = (1<<0),
  45     IER_THRI = (1<<1),
  46     IER_RLSI = (1<<2),
  47     IER_MSI  = (1<<3),
  48 };
  49
  50 enum {
  51     IIR_STAT = (1<<0),
  52     IIR_ID0  = (1<<1),
  53     IIR_ID1  = (1<<2),
  54 };
  55
  56 enum {
  57     LCR_WLS0 = (1<<0),
  58     LCR_WLS1 = (1<<1),
  59     LCR_STB  = (1<<2),
  60     LCR_PEN  = (1<<3),
  61     LCR_EPS  = (1<<4),
  62     LCR_SP   = (1<<5),
  63     LCR_SB   = (1<<6),
  64 };
  65
  66 enum {
  67     MCR_DTR  = (1<<0),
  68     MCR_RTS  = (1<<1),
  69 };
  70
  71 enum {
  72     LSR_DR   = (1<<0),
  73     LSR_OE   = (1<<1),
  74     LSR_PE   = (1<<2),
  75     LSR_FE   = (1<<3),
  76     LSR_BI   = (1<<4),
  77     LSR_THRE = (1<<5),
  78     LSR_TEMT = (1<<6),
  79 };
  80
  81 enum {
  82     MSR_DCTS = (1<<0),
  83     MSR_DDSR = (1<<1),
  84     MSR_TERI = (1<<2),
  85     MSR_DDCD = (1<<3),
  86     MSR_CTS  = (1<<4),
  87     MSR_DSR  = (1<<5),
  88     MSR_RI   = (1<<6),
  89     MSR_DCD  = (1<<7),
  90 };
  91
  92 #define TYPE_LM32_UART "lm32-uart"
  93 #define LM32_UART(obj) OBJECT_CHECK(LM32UartState, (obj), TYPE_LM32_UART)
  94
  95 struct LM32UartState {
  96     SysBusDevice parent_obj;
  97
  98     MemoryRegion iomem;
  99     CharDriverState *chr;
 100     qemu_irq irq;
 101
 102     uint32_t regs[R_MAX];
 103 };
 104 typedef struct LM32UartState LM32UartState;
 105
 106 static void uart_update_irq(LM32UartState *s)
 107 {
 108     unsigned int irq;
 109
 110     if ((s->regs[R_LSR] & (LSR_OE | LSR_PE | LSR_FE | LSR_BI))
 111             && (s->regs[R_IER] & IER_RLSI)) {
 112         irq = 1;
 113         s->regs[R_IIR] = IIR_ID1 | IIR_ID0;
 114     } else if ((s->regs[R_LSR] & LSR_DR) && (s->regs[R_IER] & IER_RBRI)) {
 115         irq = 1;
 116         s->regs[R_IIR] = IIR_ID1;
 117     } else if ((s->regs[R_LSR] & LSR_THRE) && (s->regs[R_IER] & IER_THRI)) {
 118         irq = 1;
 119         s->regs[R_IIR] = IIR_ID0;
 120     } else if ((s->regs[R_MSR] & 0x0f) && (s->regs[R_IER] & IER_MSI)) {
 121         irq = 1;
 122         s->regs[R_IIR] = 0;
 123     } else {
 124         irq = 0;
 125         s->regs[R_IIR] = IIR_STAT;
 126     }
 127
 128     trace_lm32_uart_irq_state(irq);
 129     qemu_set_irq(s->irq, irq);
 130 }
 131
 132 static uint64_t uart_read(void *opaque, hwaddr addr,
 133                           unsigned size)
 134 {
 135     LM32UartState *s = opaque;
 136     uint32_t r = 0;
 137
 138     addr >>= 2;
 139     switch (addr) {
 140     case R_RXTX:
 141         r = s->regs[R_RXTX];
 142         s->regs[R_LSR] &= ~LSR_DR;
 143         uart_update_irq(s);
 144         qemu_chr_accept_input(s->chr);
 145         break;
 146     case R_IIR:
 147     case R_LSR:
 148     case R_MSR:
 149         r = s->regs[addr];
 150         break;
 151     case R_IER:
 152     case R_LCR:
 153     case R_MCR:
 154     case R_DIV:
 155         error_report("lm32_uart: read access to write only register 0x"
 156                 TARGET_FMT_plx, addr << 2);
 157         break;
 158     default:
 159         error_report("lm32_uart: read access to unknown register 0x"
 160                 TARGET_FMT_plx, addr << 2);
 161         break;
 162     }
 163
 164     trace_lm32_uart_memory_read(addr << 2, r);
 165     return r;
 166 }
 167
 168 static void uart_write(void *opaque, hwaddr addr,
 169                        uint64_t value, unsigned size)
 170 {
 171     LM32UartState *s = opaque;
 172     unsigned char ch = value;
 173
 174     trace_lm32_uart_memory_write(addr, value);
 175
 176     addr >>= 2;
 177     switch (addr) {
 178     case R_RXTX:
 179         if (s->chr) {
 180             qemu_chr_fe_write_all(s->chr, &ch, 1);
 181         }
 182         break;
 183     case R_IER:
 184     case R_LCR:
 185     case R_MCR:
 186     case R_DIV:
 187         s->regs[addr] = value;
 188         break;
 189     case R_IIR:
 190     case R_LSR:
 191     case R_MSR:
 192         error_report("lm32_uart: write access to read only register 0x"
 193                 TARGET_FMT_plx, addr << 2);
 194         break;
 195     default:
 196         error_report("lm32_uart: write access to unknown register 0x"
 197                 TARGET_FMT_plx, addr << 2);
 198         break;
 199     }
 200     uart_update_irq(s);
 201 }
 202
 203 static const MemoryRegionOps uart_ops = {
 204     .read = uart_read,
 205     .write = uart_write,
 206     .endianness = DEVICE_NATIVE_ENDIAN,
 207     .valid = {
 208         .min_access_size = 4,
 209         .max_access_size = 4,
 210     },
 211 };
 212
 213 static void uart_rx(void *opaque, const uint8_t *buf, int size)
 214 {
 215     LM32UartState *s = opaque;
 216
 217     if (s->regs[R_LSR] & LSR_DR) {
 218         s->regs[R_LSR] |= LSR_OE;
 219     }
 220
 221     s->regs[R_LSR] |= LSR_DR;
 222     s->regs[R_RXTX] = *buf;
 223
 224     uart_update_irq(s);
 225 }
 226
 227 static int uart_can_rx(void *opaque)
 228 {
 229     LM32UartState *s = opaque;
 230
 231     return !(s->regs[R_LSR] & LSR_DR);
 232 }
 233
 234 static void uart_event(void *opaque, int event)
 235 {
 236 }
 237
 238 static void uart_reset(DeviceState *d)
 239 {
 240     LM32UartState *s = LM32_UART(d);
 241     int i;
 242
 243     for (i = 0; i < R_MAX; i++) {
 244         s->regs[i] = 0;
 245     }
 246
 247     /* defaults */
 248     s->regs[R_LSR] = LSR_THRE | LSR_TEMT;
 249 }
 250
 251 static int lm32_uart_init(SysBusDevice *dev)
 252 {
 253     LM32UartState *s = LM32_UART(dev);
 254
 255     sysbus_init_irq(dev, &s->irq);
 256
 257     memory_region_init_io(&s->iomem, OBJECT(s), &uart_ops, s,
 258                           "uart", R_MAX * 4);
 259     sysbus_init_mmio(dev, &s->iomem);
 260
 261     s->chr = qemu_char_get_next_serial();
 262     if (s->chr) {
 263         qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
 264     }
 265
 266     return 0;
 267 }
 268
 269 static const VMStateDescription vmstate_lm32_uart = {
 270     .name = "lm32-uart",
 271     .version_id = 1,
 272     .minimum_version_id = 1,
 273     .fields = (VMStateField[]) {
 274         VMSTATE_UINT32_ARRAY(regs, LM32UartState, R_MAX),
 275         VMSTATE_END_OF_LIST()
 276     }
 277 };
 278
 279 static void lm32_uart_class_init(ObjectClass *klass, void *data)
 280 {
 281     DeviceClass *dc = DEVICE_CLASS(klass);
 282     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 283
 284     k->init = lm32_uart_init;
 285     dc->reset = uart_reset;
 286     dc->vmsd = &vmstate_lm32_uart;
 287 }
 288
 289 static const TypeInfo lm32_uart_info = {
 290     .name          = TYPE_LM32_UART,
 291     .parent        = TYPE_SYS_BUS_DEVICE,
 292     .instance_size = sizeof(LM32UartState),
 293     .class_init    = lm32_uart_class_init,
 294 };
 295
 296 static void lm32_uart_register_types(void)
 297 {
 298     type_register_static(&lm32_uart_info);
 299 }
 300
 301 type_init(lm32_uart_register_types)