hw/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "serial.h"
  27 #include "apic.h"
  28 #include "fdc.h"
  29 #include "ide.h"
  30 #include "pci.h"
  31 #include "monitor.h"
  32 #include "fw_cfg.h"
  33 #include "hpet_emul.h"
  34 #include "smbios.h"
  35 #include "loader.h"
  36 #include "elf.h"
  37 #include "multiboot.h"
  38 #include "mc146818rtc.h"
  39 #include "i8254.h"
  40 #include "pcspk.h"
  41 #include "msi.h"
  42 #include "sysbus.h"
  43 #include "sysemu.h"
  44 #include "kvm.h"
  45 #include "kvm_i386.h"
  46 #include "xen.h"
  47 #include "blockdev.h"
  48 #include "hw/block-common.h"
  49 #include "ui/qemu-spice.h"
  50 #include "memory.h"
  51 #include "exec-memory.h"
  52 #include "arch_init.h"
  53 #include "bitmap.h"
  54
  55 /* debug PC/ISA interrupts */
  56 //#define DEBUG_IRQ
  57
  58 #ifdef DEBUG_IRQ
  59 #define DPRINTF(fmt, ...)                                       \
  60     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  61 #else
  62 #define DPRINTF(fmt, ...)
  63 #endif
  64
  65 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  66 #define ACPI_DATA_SIZE       0x10000
  67 #define BIOS_CFG_IOPORT 0x510
  68 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  69 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  70 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  71 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  72 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
  73
  74 #define MSI_ADDR_BASE 0xfee00000
  75
  76 #define E820_NR_ENTRIES         16
  77
  78 struct e820_entry {
  79     uint64_t address;
  80     uint64_t length;
  81     uint32_t type;
  82 } QEMU_PACKED __attribute((__aligned__(4)));
  83
  84 struct e820_table {
  85     uint32_t count;
  86     struct e820_entry entry[E820_NR_ENTRIES];
  87 } QEMU_PACKED __attribute((__aligned__(4)));
  88
  89 static struct e820_table e820_table;
  90 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
  91
  92 void gsi_handler(void *opaque, int n, int level)
  93 {
  94     GSIState *s = opaque;
  95
  96     DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
  97     if (n < ISA_NUM_IRQS) {
  98         qemu_set_irq(s->i8259_irq[n], level);
  99     }
 100     qemu_set_irq(s->ioapic_irq[n], level);
 101 }
 102
 103 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
 104 {
 105 }
 106
 107 /* MSDOS compatibility mode FPU exception support */
 108 static qemu_irq ferr_irq;
 109
 110 void pc_register_ferr_irq(qemu_irq irq)
 111 {
 112     ferr_irq = irq;
 113 }
 114
 115 /* XXX: add IGNNE support */
 116 void cpu_set_ferr(CPUX86State *s)
 117 {
 118     qemu_irq_raise(ferr_irq);
 119 }
 120
 121 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
 122 {
 123     qemu_irq_lower(ferr_irq);
 124 }
 125
 126 /* TSC handling */
 127 uint64_t cpu_get_tsc(CPUX86State *env)
 128 {
 129     return cpu_get_ticks();
 130 }
 131
 132 /* SMM support */
 133
 134 static cpu_set_smm_t smm_set;
 135 static void *smm_arg;
 136
 137 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
 138 {
 139     assert(smm_set == NULL);
 140     assert(smm_arg == NULL);
 141     smm_set = callback;
 142     smm_arg = arg;
 143 }
 144
 145 void cpu_smm_update(CPUX86State *env)
 146 {
 147     if (smm_set && smm_arg && env == first_cpu)
 148         smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
 149 }
 150
 151
 152 /* IRQ handling */
 153 int cpu_get_pic_interrupt(CPUX86State *env)
 154 {
 155     int intno;
 156
 157     intno = apic_get_interrupt(env->apic_state);
 158     if (intno >= 0) {
 159         return intno;
 160     }
 161     /* read the irq from the PIC */
 162     if (!apic_accept_pic_intr(env->apic_state)) {
 163         return -1;
 164     }
 165
 166     intno = pic_read_irq(isa_pic);
 167     return intno;
 168 }
 169
 170 static void pic_irq_request(void *opaque, int irq, int level)
 171 {
 172     CPUX86State *env = first_cpu;
 173
 174     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
 175     if (env->apic_state) {
 176         while (env) {
 177             if (apic_accept_pic_intr(env->apic_state)) {
 178                 apic_deliver_pic_intr(env->apic_state, level);
 179             }
 180             env = env->next_cpu;
 181         }
 182     } else {
 183         if (level)
 184             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 185         else
 186             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 187     }
 188 }
 189
 190 /* PC cmos mappings */
 191
 192 #define REG_EQUIPMENT_BYTE          0x14
 193
 194 static int cmos_get_fd_drive_type(FDriveType fd0)
 195 {
 196     int val;
 197
 198     switch (fd0) {
 199     case FDRIVE_DRV_144:
 200         /* 1.44 Mb 3"5 drive */
 201         val = 4;
 202         break;
 203     case FDRIVE_DRV_288:
 204         /* 2.88 Mb 3"5 drive */
 205         val = 5;
 206         break;
 207     case FDRIVE_DRV_120:
 208         /* 1.2 Mb 5"5 drive */
 209         val = 2;
 210         break;
 211     case FDRIVE_DRV_NONE:
 212     default:
 213         val = 0;
 214         break;
 215     }
 216     return val;
 217 }
 218
 219 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
 220                          int16_t cylinders, int8_t heads, int8_t sectors)
 221 {
 222     rtc_set_memory(s, type_ofs, 47);
 223     rtc_set_memory(s, info_ofs, cylinders);
 224     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 225     rtc_set_memory(s, info_ofs + 2, heads);
 226     rtc_set_memory(s, info_ofs + 3, 0xff);
 227     rtc_set_memory(s, info_ofs + 4, 0xff);
 228     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 229     rtc_set_memory(s, info_ofs + 6, cylinders);
 230     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 231     rtc_set_memory(s, info_ofs + 8, sectors);
 232 }
 233
 234 /* convert boot_device letter to something recognizable by the bios */
 235 static int boot_device2nibble(char boot_device)
 236 {
 237     switch(boot_device) {
 238     case 'a':
 239     case 'b':
 240         return 0x01; /* floppy boot */
 241     case 'c':
 242         return 0x02; /* hard drive boot */
 243     case 'd':
 244         return 0x03; /* CD-ROM boot */
 245     case 'n':
 246         return 0x04; /* Network boot */
 247     }
 248     return 0;
 249 }
 250
 251 static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk)
 252 {
 253 #define PC_MAX_BOOT_DEVICES 3
 254     int nbds, bds[3] = { 0, };
 255     int i;
 256
 257     nbds = strlen(boot_device);
 258     if (nbds > PC_MAX_BOOT_DEVICES) {
 259         error_report("Too many boot devices for PC");
 260         return(1);
 261     }
 262     for (i = 0; i < nbds; i++) {
 263         bds[i] = boot_device2nibble(boot_device[i]);
 264         if (bds[i] == 0) {
 265             error_report("Invalid boot device for PC: '%c'",
 266                          boot_device[i]);
 267             return(1);
 268         }
 269     }
 270     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 271     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 272     return(0);
 273 }
 274
 275 static int pc_boot_set(void *opaque, const char *boot_device)
 276 {
 277     return set_boot_dev(opaque, boot_device, 0);
 278 }
 279
 280 typedef struct pc_cmos_init_late_arg {
 281     ISADevice *rtc_state;
 282     BusState *idebus[2];
 283 } pc_cmos_init_late_arg;
 284
 285 static void pc_cmos_init_late(void *opaque)
 286 {
 287     pc_cmos_init_late_arg *arg = opaque;
 288     ISADevice *s = arg->rtc_state;
 289     int16_t cylinders;
 290     int8_t heads, sectors;
 291     int val;
 292     int i, trans;
 293
 294     val = 0;
 295     if (ide_get_geometry(arg->idebus[0], 0,
 296                          &cylinders, &heads, &sectors) >= 0) {
 297         cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
 298         val |= 0xf0;
 299     }
 300     if (ide_get_geometry(arg->idebus[0], 1,
 301                          &cylinders, &heads, &sectors) >= 0) {
 302         cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
 303         val |= 0x0f;
 304     }
 305     rtc_set_memory(s, 0x12, val);
 306
 307     val = 0;
 308     for (i = 0; i < 4; i++) {
 309         /* NOTE: ide_get_geometry() returns the physical
 310            geometry.  It is always such that: 1 <= sects <= 63, 1
 311            <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 312            geometry can be different if a translation is done. */
 313         if (ide_get_geometry(arg->idebus[i / 2], i % 2,
 314                              &cylinders, &heads, &sectors) >= 0) {
 315             trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
 316             assert((trans & ~3) == 0);
 317             val |= trans << (i * 2);
 318         }
 319     }
 320     rtc_set_memory(s, 0x39, val);
 321
 322     qemu_unregister_reset(pc_cmos_init_late, opaque);
 323 }
 324
 325 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 326                   const char *boot_device,
 327                   ISADevice *floppy, BusState *idebus0, BusState *idebus1,
 328                   ISADevice *s)
 329 {
 330     int val, nb, i;
 331     FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
 332     static pc_cmos_init_late_arg arg;
 333
 334     /* various important CMOS locations needed by PC/Bochs bios */
 335
 336     /* memory size */
 337     /* base memory (first MiB) */
 338     val = MIN(ram_size / 1024, 640);
 339     rtc_set_memory(s, 0x15, val);
 340     rtc_set_memory(s, 0x16, val >> 8);
 341     /* extended memory (next 64MiB) */
 342     if (ram_size > 1024 * 1024) {
 343         val = (ram_size - 1024 * 1024) / 1024;
 344     } else {
 345         val = 0;
 346     }
 347     if (val > 65535)
 348         val = 65535;
 349     rtc_set_memory(s, 0x17, val);
 350     rtc_set_memory(s, 0x18, val >> 8);
 351     rtc_set_memory(s, 0x30, val);
 352     rtc_set_memory(s, 0x31, val >> 8);
 353     /* memory between 16MiB and 4GiB */
 354     if (ram_size > 16 * 1024 * 1024) {
 355         val = (ram_size - 16 * 1024 * 1024) / 65536;
 356     } else {
 357         val = 0;
 358     }
 359     if (val > 65535)
 360         val = 65535;
 361     rtc_set_memory(s, 0x34, val);
 362     rtc_set_memory(s, 0x35, val >> 8);
 363     /* memory above 4GiB */
 364     val = above_4g_mem_size / 65536;
 365     rtc_set_memory(s, 0x5b, val);
 366     rtc_set_memory(s, 0x5c, val >> 8);
 367     rtc_set_memory(s, 0x5d, val >> 16);
 368
 369     /* set the number of CPU */
 370     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 371
 372     /* set boot devices, and disable floppy signature check if requested */
 373     if (set_boot_dev(s, boot_device, fd_bootchk)) {
 374         exit(1);
 375     }
 376
 377     /* floppy type */
 378     if (floppy) {
 379         for (i = 0; i < 2; i++) {
 380             fd_type[i] = isa_fdc_get_drive_type(floppy, i);
 381         }
 382     }
 383     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
 384         cmos_get_fd_drive_type(fd_type[1]);
 385     rtc_set_memory(s, 0x10, val);
 386
 387     val = 0;
 388     nb = 0;
 389     if (fd_type[0] < FDRIVE_DRV_NONE) {
 390         nb++;
 391     }
 392     if (fd_type[1] < FDRIVE_DRV_NONE) {
 393         nb++;
 394     }
 395     switch (nb) {
 396     case 0:
 397         break;
 398     case 1:
 399         val |= 0x01; /* 1 drive, ready for boot */
 400         break;
 401     case 2:
 402         val |= 0x41; /* 2 drives, ready for boot */
 403         break;
 404     }
 405     val |= 0x02; /* FPU is there */
 406     val |= 0x04; /* PS/2 mouse installed */
 407     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 408
 409     /* hard drives */
 410     arg.rtc_state = s;
 411     arg.idebus[0] = idebus0;
 412     arg.idebus[1] = idebus1;
 413     qemu_register_reset(pc_cmos_init_late, &arg);
 414 }
 415
 416 /* port 92 stuff: could be split off */
 417 typedef struct Port92State {
 418     ISADevice dev;
 419     MemoryRegion io;
 420     uint8_t outport;
 421     qemu_irq *a20_out;
 422 } Port92State;
 423
 424 static void port92_write(void *opaque, hwaddr addr, uint64_t val,
 425                          unsigned size)
 426 {
 427     Port92State *s = opaque;
 428
 429     DPRINTF("port92: write 0x%02x\n", val);
 430     s->outport = val;
 431     qemu_set_irq(*s->a20_out, (val >> 1) & 1);
 432     if (val & 1) {
 433         qemu_system_reset_request();
 434     }
 435 }
 436
 437 static uint64_t port92_read(void *opaque, hwaddr addr,
 438                             unsigned size)
 439 {
 440     Port92State *s = opaque;
 441     uint32_t ret;
 442
 443     ret = s->outport;
 444     DPRINTF("port92: read 0x%02x\n", ret);
 445     return ret;
 446 }
 447
 448 static void port92_init(ISADevice *dev, qemu_irq *a20_out)
 449 {
 450     Port92State *s = DO_UPCAST(Port92State, dev, dev);
 451
 452     s->a20_out = a20_out;
 453 }
 454
 455 static const VMStateDescription vmstate_port92_isa = {
 456     .name = "port92",
 457     .version_id = 1,
 458     .minimum_version_id = 1,
 459     .minimum_version_id_old = 1,
 460     .fields      = (VMStateField []) {
 461         VMSTATE_UINT8(outport, Port92State),
 462         VMSTATE_END_OF_LIST()
 463     }
 464 };
 465
 466 static void port92_reset(DeviceState *d)
 467 {
 468     Port92State *s = container_of(d, Port92State, dev.qdev);
 469
 470     s->outport &= ~1;
 471 }
 472
 473 static const MemoryRegionOps port92_ops = {
 474     .read = port92_read,
 475     .write = port92_write,
 476     .impl = {
 477         .min_access_size = 1,
 478         .max_access_size = 1,
 479     },
 480     .endianness = DEVICE_LITTLE_ENDIAN,
 481 };
 482
 483 static int port92_initfn(ISADevice *dev)
 484 {
 485     Port92State *s = DO_UPCAST(Port92State, dev, dev);
 486
 487     memory_region_init_io(&s->io, &port92_ops, s, "port92", 1);
 488     isa_register_ioport(dev, &s->io, 0x92);
 489
 490     s->outport = 0;
 491     return 0;
 492 }
 493
 494 static void port92_class_initfn(ObjectClass *klass, void *data)
 495 {
 496     DeviceClass *dc = DEVICE_CLASS(klass);
 497     ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
 498     ic->init = port92_initfn;
 499     dc->no_user = 1;
 500     dc->reset = port92_reset;
 501     dc->vmsd = &vmstate_port92_isa;
 502 }
 503
 504 static TypeInfo port92_info = {
 505     .name          = "port92",
 506     .parent        = TYPE_ISA_DEVICE,
 507     .instance_size = sizeof(Port92State),
 508     .class_init    = port92_class_initfn,
 509 };
 510
 511 static void port92_register_types(void)
 512 {
 513     type_register_static(&port92_info);
 514 }
 515
 516 type_init(port92_register_types)
 517
 518 static void handle_a20_line_change(void *opaque, int irq, int level)
 519 {
 520     CPUX86State *cpu = opaque;
 521
 522     /* XXX: send to all CPUs ? */
 523     /* XXX: add logic to handle multiple A20 line sources */
 524     cpu_x86_set_a20(cpu, level);
 525 }
 526
 527 /***********************************************************/
 528 /* Bochs BIOS debug ports */
 529
 530 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 531 {
 532     static const char shutdown_str[8] = "Shutdown";
 533     static int shutdown_index = 0;
 534
 535     switch(addr) {
 536     case 0x8900:
 537         /* same as Bochs power off */
 538         if (val == shutdown_str[shutdown_index]) {
 539             shutdown_index++;
 540             if (shutdown_index == 8) {
 541                 shutdown_index = 0;
 542                 qemu_system_shutdown_request();
 543             }
 544         } else {
 545             shutdown_index = 0;
 546         }
 547         break;
 548
 549     case 0x501:
 550     case 0x502:
 551         exit((val << 1) | 1);
 552     }
 553 }
 554
 555 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 556 {
 557     int index = le32_to_cpu(e820_table.count);
 558     struct e820_entry *entry;
 559
 560     if (index >= E820_NR_ENTRIES)
 561         return -EBUSY;
 562     entry = &e820_table.entry[index++];
 563
 564     entry->address = cpu_to_le64(address);
 565     entry->length = cpu_to_le64(length);
 566     entry->type = cpu_to_le32(type);
 567
 568     e820_table.count = cpu_to_le32(index);
 569     return index;
 570 }
 571
 572 static void *bochs_bios_init(void)
 573 {
 574     void *fw_cfg;
 575     uint8_t *smbios_table;
 576     size_t smbios_len;
 577     uint64_t *numa_fw_cfg;
 578     int i, j;
 579
 580     register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
 581
 582     register_ioport_write(0x501, 1, 1, bochs_bios_write, NULL);
 583     register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
 584     register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
 585
 586     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 587
 588     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 589     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 590     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
 591                      acpi_tables_len);
 592     fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
 593
 594     smbios_table = smbios_get_table(&smbios_len);
 595     if (smbios_table)
 596         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 597                          smbios_table, smbios_len);
 598     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
 599                      sizeof(struct e820_table));
 600
 601     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg,
 602                      sizeof(struct hpet_fw_config));
 603     /* allocate memory for the NUMA channel: one (64bit) word for the number
 604      * of nodes, one word for each VCPU->node and one word for each node to
 605      * hold the amount of memory.
 606      */
 607     numa_fw_cfg = g_malloc0((1 + max_cpus + nb_numa_nodes) * 8);
 608     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 609     for (i = 0; i < max_cpus; i++) {
 610         for (j = 0; j < nb_numa_nodes; j++) {
 611             if (test_bit(i, node_cpumask[j])) {
 612                 numa_fw_cfg[i + 1] = cpu_to_le64(j);
 613                 break;
 614             }
 615         }
 616     }
 617     for (i = 0; i < nb_numa_nodes; i++) {
 618         numa_fw_cfg[max_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
 619     }
 620     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
 621                      (1 + max_cpus + nb_numa_nodes) * 8);
 622
 623     return fw_cfg;
 624 }
 625
 626 static long get_file_size(FILE *f)
 627 {
 628     long where, size;
 629
 630     /* XXX: on Unix systems, using fstat() probably makes more sense */
 631
 632     where = ftell(f);
 633     fseek(f, 0, SEEK_END);
 634     size = ftell(f);
 635     fseek(f, where, SEEK_SET);
 636
 637     return size;
 638 }
 639
 640 static void load_linux(void *fw_cfg,
 641                        const char *kernel_filename,
 642                        const char *initrd_filename,
 643                        const char *kernel_cmdline,
 644                        hwaddr max_ram_size)
 645 {
 646     uint16_t protocol;
 647     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 648     uint32_t initrd_max;
 649     uint8_t header[8192], *setup, *kernel, *initrd_data;
 650     hwaddr real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 651     FILE *f;
 652     char *vmode;
 653
 654     /* Align to 16 bytes as a paranoia measure */
 655     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 656
 657     /* load the kernel header */
 658     f = fopen(kernel_filename, "rb");
 659     if (!f || !(kernel_size = get_file_size(f)) ||
 660         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 661         MIN(ARRAY_SIZE(header), kernel_size)) {
 662         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 663                 kernel_filename, strerror(errno));
 664         exit(1);
 665     }
 666
 667     /* kernel protocol version */
 668 #if 0
 669     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 670 #endif
 671     if (ldl_p(header+0x202) == 0x53726448)
 672         protocol = lduw_p(header+0x206);
 673     else {
 674         /* This looks like a multiboot kernel. If it is, let's stop
 675            treating it like a Linux kernel. */
 676         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 677                            kernel_cmdline, kernel_size, header))
 678             return;
 679         protocol = 0;
 680     }
 681
 682     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 683         /* Low kernel */
 684         real_addr    = 0x90000;
 685         cmdline_addr = 0x9a000 - cmdline_size;
 686         prot_addr    = 0x10000;
 687     } else if (protocol < 0x202) {
 688         /* High but ancient kernel */
 689         real_addr    = 0x90000;
 690         cmdline_addr = 0x9a000 - cmdline_size;
 691         prot_addr    = 0x100000;
 692     } else {
 693         /* High and recent kernel */
 694         real_addr    = 0x10000;
 695         cmdline_addr = 0x20000;
 696         prot_addr    = 0x100000;
 697     }
 698
 699 #if 0
 700     fprintf(stderr,
 701             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 702             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 703             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 704             real_addr,
 705             cmdline_addr,
 706             prot_addr);
 707 #endif
 708
 709     /* highest address for loading the initrd */
 710     if (protocol >= 0x203)
 711         initrd_max = ldl_p(header+0x22c);
 712     else
 713         initrd_max = 0x37ffffff;
 714
 715     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 716         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 717
 718     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 719     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 720     fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 721                      (uint8_t*)strdup(kernel_cmdline),
 722                      strlen(kernel_cmdline)+1);
 723
 724     if (protocol >= 0x202) {
 725         stl_p(header+0x228, cmdline_addr);
 726     } else {
 727         stw_p(header+0x20, 0xA33F);
 728         stw_p(header+0x22, cmdline_addr-real_addr);
 729     }
 730
 731     /* handle vga= parameter */
 732     vmode = strstr(kernel_cmdline, "vga=");
 733     if (vmode) {
 734         unsigned int video_mode;
 735         /* skip "vga=" */
 736         vmode += 4;
 737         if (!strncmp(vmode, "normal", 6)) {
 738             video_mode = 0xffff;
 739         } else if (!strncmp(vmode, "ext", 3)) {
 740             video_mode = 0xfffe;
 741         } else if (!strncmp(vmode, "ask", 3)) {
 742             video_mode = 0xfffd;
 743         } else {
 744             video_mode = strtol(vmode, NULL, 0);
 745         }
 746         stw_p(header+0x1fa, video_mode);
 747     }
 748
 749     /* loader type */
 750     /* High nybble = B reserved for QEMU; low nybble is revision number.
 751        If this code is substantially changed, you may want to consider
 752        incrementing the revision. */
 753     if (protocol >= 0x200)
 754         header[0x210] = 0xB0;
 755
 756     /* heap */
 757     if (protocol >= 0x201) {
 758         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 759         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 760     }
 761
 762     /* load initrd */
 763     if (initrd_filename) {
 764         if (protocol < 0x200) {
 765             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 766             exit(1);
 767         }
 768
 769         initrd_size = get_image_size(initrd_filename);
 770         if (initrd_size < 0) {
 771             fprintf(stderr, "qemu: error reading initrd %s\n",
 772                     initrd_filename);
 773             exit(1);
 774         }
 775
 776         initrd_addr = (initrd_max-initrd_size) & ~4095;
 777
 778         initrd_data = g_malloc(initrd_size);
 779         load_image(initrd_filename, initrd_data);
 780
 781         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 782         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 783         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 784
 785         stl_p(header+0x218, initrd_addr);
 786         stl_p(header+0x21c, initrd_size);
 787     }
 788
 789     /* load kernel and setup */
 790     setup_size = header[0x1f1];
 791     if (setup_size == 0)
 792         setup_size = 4;
 793     setup_size = (setup_size+1)*512;
 794     kernel_size -= setup_size;
 795
 796     setup  = g_malloc(setup_size);
 797     kernel = g_malloc(kernel_size);
 798     fseek(f, 0, SEEK_SET);
 799     if (fread(setup, 1, setup_size, f) != setup_size) {
 800         fprintf(stderr, "fread() failed\n");
 801         exit(1);
 802     }
 803     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 804         fprintf(stderr, "fread() failed\n");
 805         exit(1);
 806     }
 807     fclose(f);
 808     memcpy(setup, header, MIN(sizeof(header), setup_size));
 809
 810     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 811     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 812     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 813
 814     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 815     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 816     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 817
 818     option_rom[nb_option_roms].name = "linuxboot.bin";
 819     option_rom[nb_option_roms].bootindex = 0;
 820     nb_option_roms++;
 821 }
 822
 823 #define NE2000_NB_MAX 6
 824
 825 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 826                                               0x280, 0x380 };
 827 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 828
 829 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 830 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 831
 832 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
 833 {
 834     static int nb_ne2k = 0;
 835
 836     if (nb_ne2k == NE2000_NB_MAX)
 837         return;
 838     isa_ne2000_init(bus, ne2000_io[nb_ne2k],
 839                     ne2000_irq[nb_ne2k], nd);
 840     nb_ne2k++;
 841 }
 842
 843 DeviceState *cpu_get_current_apic(void)
 844 {
 845     if (cpu_single_env) {
 846         return cpu_single_env->apic_state;
 847     } else {
 848         return NULL;
 849     }
 850 }
 851
 852 static DeviceState *apic_init(void *env, uint8_t apic_id)
 853 {
 854     DeviceState *dev;
 855     static int apic_mapped;
 856
 857     if (kvm_irqchip_in_kernel()) {
 858         dev = qdev_create(NULL, "kvm-apic");
 859     } else if (xen_enabled()) {
 860         dev = qdev_create(NULL, "xen-apic");
 861     } else {
 862         dev = qdev_create(NULL, "apic");
 863     }
 864
 865     qdev_prop_set_uint8(dev, "id", apic_id);
 866     qdev_prop_set_ptr(dev, "cpu_env", env);
 867     qdev_init_nofail(dev);
 868
 869     /* XXX: mapping more APICs at the same memory location */
 870     if (apic_mapped == 0) {
 871         /* NOTE: the APIC is directly connected to the CPU - it is not
 872            on the global memory bus. */
 873         /* XXX: what if the base changes? */
 874         sysbus_mmio_map(sysbus_from_qdev(dev), 0, MSI_ADDR_BASE);
 875         apic_mapped = 1;
 876     }
 877
 878     return dev;
 879 }
 880
 881 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
 882 {
 883     CPUX86State *s = opaque;
 884
 885     if (level) {
 886         cpu_interrupt(s, CPU_INTERRUPT_SMI);
 887     }
 888 }
 889
 890 static X86CPU *pc_new_cpu(const char *cpu_model)
 891 {
 892     X86CPU *cpu;
 893     CPUX86State *env;
 894
 895     cpu = cpu_x86_init(cpu_model);
 896     if (cpu == NULL) {
 897         fprintf(stderr, "Unable to find x86 CPU definition\n");
 898         exit(1);
 899     }
 900     env = &cpu->env;
 901     if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
 902         env->apic_state = apic_init(env, env->cpuid_apic_id);
 903     }
 904     cpu_reset(CPU(cpu));
 905     return cpu;
 906 }
 907
 908 void pc_cpus_init(const char *cpu_model)
 909 {
 910     int i;
 911
 912     /* init CPUs */
 913     if (cpu_model == NULL) {
 914 #ifdef TARGET_X86_64
 915         cpu_model = "qemu64";
 916 #else
 917         cpu_model = "qemu32";
 918 #endif
 919     }
 920
 921     for(i = 0; i < smp_cpus; i++) {
 922         pc_new_cpu(cpu_model);
 923     }
 924 }
 925
 926 void *pc_memory_init(MemoryRegion *system_memory,
 927                     const char *kernel_filename,
 928                     const char *kernel_cmdline,
 929                     const char *initrd_filename,
 930                     ram_addr_t below_4g_mem_size,
 931                     ram_addr_t above_4g_mem_size,
 932                     MemoryRegion *rom_memory,
 933                     MemoryRegion **ram_memory)
 934 {
 935     int linux_boot, i;
 936     MemoryRegion *ram, *option_rom_mr;
 937     MemoryRegion *ram_below_4g, *ram_above_4g;
 938     void *fw_cfg;
 939
 940     linux_boot = (kernel_filename != NULL);
 941
 942     /* Allocate RAM.  We allocate it as a single memory region and use
 943      * aliases to address portions of it, mostly for backwards compatibility
 944      * with older qemus that used qemu_ram_alloc().
 945      */
 946     ram = g_malloc(sizeof(*ram));
 947     memory_region_init_ram(ram, "pc.ram",
 948                            below_4g_mem_size + above_4g_mem_size);
 949     vmstate_register_ram_global(ram);
 950     *ram_memory = ram;
 951     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
 952     memory_region_init_alias(ram_below_4g, "ram-below-4g", ram,
 953                              0, below_4g_mem_size);
 954     memory_region_add_subregion(system_memory, 0, ram_below_4g);
 955     if (above_4g_mem_size > 0) {
 956         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
 957         memory_region_init_alias(ram_above_4g, "ram-above-4g", ram,
 958                                  below_4g_mem_size, above_4g_mem_size);
 959         memory_region_add_subregion(system_memory, 0x100000000ULL,
 960                                     ram_above_4g);
 961     }
 962
 963
 964     /* Initialize PC system firmware */
 965     pc_system_firmware_init(rom_memory);
 966
 967     option_rom_mr = g_malloc(sizeof(*option_rom_mr));
 968     memory_region_init_ram(option_rom_mr, "pc.rom", PC_ROM_SIZE);
 969     vmstate_register_ram_global(option_rom_mr);
 970     memory_region_add_subregion_overlap(rom_memory,
 971                                         PC_ROM_MIN_VGA,
 972                                         option_rom_mr,
 973                                         1);
 974
 975     fw_cfg = bochs_bios_init();
 976     rom_set_fw(fw_cfg);
 977
 978     if (linux_boot) {
 979         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
 980     }
 981
 982     for (i = 0; i < nb_option_roms; i++) {
 983         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
 984     }
 985     return fw_cfg;
 986 }
 987
 988 qemu_irq *pc_allocate_cpu_irq(void)
 989 {
 990     return qemu_allocate_irqs(pic_irq_request, NULL, 1);
 991 }
 992
 993 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
 994 {
 995     DeviceState *dev = NULL;
 996
 997     if (pci_bus) {
 998         PCIDevice *pcidev = pci_vga_init(pci_bus);
 999         dev = pcidev ? &pcidev->qdev : NULL;
1000     } else if (isa_bus) {
1001         ISADevice *isadev = isa_vga_init(isa_bus);
1002         dev = isadev ? &isadev->qdev : NULL;
1003     }
1004     return dev;
1005 }
1006
1007 static void cpu_request_exit(void *opaque, int irq, int level)
1008 {
1009     CPUX86State *env = cpu_single_env;
1010
1011     if (env && level) {
1012         cpu_exit(env);
1013     }
1014 }
1015
1016 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1017                           ISADevice **rtc_state,
1018                           ISADevice **floppy,
1019                           bool no_vmport)
1020 {
1021     int i;
1022     DriveInfo *fd[MAX_FD];
1023     DeviceState *hpet = NULL;
1024     int pit_isa_irq = 0;
1025     qemu_irq pit_alt_irq = NULL;
1026     qemu_irq rtc_irq = NULL;
1027     qemu_irq *a20_line;
1028     ISADevice *i8042, *port92, *vmmouse, *pit = NULL;
1029     qemu_irq *cpu_exit_irq;
1030
1031     register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
1032
1033     register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1034
1035     /*
1036      * Check if an HPET shall be created.
1037      *
1038      * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1039      * when the HPET wants to take over. Thus we have to disable the latter.
1040      */
1041     if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1042         hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL);
1043
1044         if (hpet) {
1045             for (i = 0; i < GSI_NUM_PINS; i++) {
1046                 sysbus_connect_irq(sysbus_from_qdev(hpet), i, gsi[i]);
1047             }
1048             pit_isa_irq = -1;
1049             pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1050             rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1051         }
1052     }
1053     *rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
1054
1055     qemu_register_boot_set(pc_boot_set, *rtc_state);
1056
1057     if (!xen_enabled()) {
1058         if (kvm_irqchip_in_kernel()) {
1059             pit = kvm_pit_init(isa_bus, 0x40);
1060         } else {
1061             pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1062         }
1063         if (hpet) {
1064             /* connect PIT to output control line of the HPET */
1065             qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(&pit->qdev, 0));
1066         }
1067         pcspk_init(isa_bus, pit);
1068     }
1069
1070     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1071         if (serial_hds[i]) {
1072             serial_isa_init(isa_bus, i, serial_hds[i]);
1073         }
1074     }
1075
1076     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1077         if (parallel_hds[i]) {
1078             parallel_init(isa_bus, i, parallel_hds[i]);
1079         }
1080     }
1081
1082     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1083     i8042 = isa_create_simple(isa_bus, "i8042");
1084     i8042_setup_a20_line(i8042, &a20_line[0]);
1085     if (!no_vmport) {
1086         vmport_init(isa_bus);
1087         vmmouse = isa_try_create(isa_bus, "vmmouse");
1088     } else {
1089         vmmouse = NULL;
1090     }
1091     if (vmmouse) {
1092         qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042);
1093         qdev_init_nofail(&vmmouse->qdev);
1094     }
1095     port92 = isa_create_simple(isa_bus, "port92");
1096     port92_init(port92, &a20_line[1]);
1097
1098     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1099     DMA_init(0, cpu_exit_irq);
1100
1101     for(i = 0; i < MAX_FD; i++) {
1102         fd[i] = drive_get(IF_FLOPPY, 0, i);
1103     }
1104     *floppy = fdctrl_init_isa(isa_bus, fd);
1105 }
1106
1107 void pc_pci_device_init(PCIBus *pci_bus)
1108 {
1109     int max_bus;
1110     int bus;
1111
1112     max_bus = drive_get_max_bus(IF_SCSI);
1113     for (bus = 0; bus <= max_bus; bus++) {
1114         pci_create_simple(pci_bus, -1, "lsi53c895a");
1115     }
1116 }