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target-mips: redefine Integer Multiply and Divide instructions
[qemu-kvm.git] / disas / mips.c
blob16cb2acd8116a1887fd0c27b29394684d359bd71
1 /* Print mips instructions for GDB, the GNU debugger, or for objdump.
2 Copyright 1989, 1991, 1992, 1993, 1994, 1995, 1996, 1997, 1998, 1999,
3 2000, 2001, 2002, 2003
4 Free Software Foundation, Inc.
5 Contributed by Nobuyuki Hikichi(hikichi@sra.co.jp).
6
7 This file is part of GDB, GAS, and the GNU binutils.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 2 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program; if not, see <http://www.gnu.org/licenses/>. */
21
22 #include "disas/bfd.h"
23
24 /* mips.h. Mips opcode list for GDB, the GNU debugger.
25 Copyright 1993, 1994, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2003
26 Free Software Foundation, Inc.
27 Contributed by Ralph Campbell and OSF
28 Commented and modified by Ian Lance Taylor, Cygnus Support
29
30 This file is part of GDB, GAS, and the GNU binutils.
31
32 GDB, GAS, and the GNU binutils are free software; you can redistribute
33 them and/or modify them under the terms of the GNU General Public
34 License as published by the Free Software Foundation; either version
35 1, or (at your option) any later version.
36
37 GDB, GAS, and the GNU binutils are distributed in the hope that they
38 will be useful, but WITHOUT ANY WARRANTY; without even the implied
39 warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See
40 the GNU General Public License for more details.
41
42 You should have received a copy of the GNU General Public License
43 along with this file; see the file COPYING. If not,
44 see <http://www.gnu.org/licenses/>. */
45
46 /* These are bit masks and shift counts to use to access the various
47 fields of an instruction. To retrieve the X field of an
48 instruction, use the expression
49 (i >> OP_SH_X) & OP_MASK_X
50 To set the same field (to j), use
51 i = (i &~ (OP_MASK_X << OP_SH_X)) | (j << OP_SH_X)
52
53 Make sure you use fields that are appropriate for the instruction,
54 of course.
55
56 The 'i' format uses OP, RS, RT and IMMEDIATE.
57
58 The 'j' format uses OP and TARGET.
59
60 The 'r' format uses OP, RS, RT, RD, SHAMT and FUNCT.
61
62 The 'b' format uses OP, RS, RT and DELTA.
63
64 The floating point 'i' format uses OP, RS, RT and IMMEDIATE.
65
66 The floating point 'r' format uses OP, FMT, FT, FS, FD and FUNCT.
67
68 A breakpoint instruction uses OP, CODE and SPEC (10 bits of the
69 breakpoint instruction are not defined; Kane says the breakpoint
70 code field in BREAK is 20 bits; yet MIPS assemblers and debuggers
71 only use ten bits). An optional two-operand form of break/sdbbp
72 allows the lower ten bits to be set too, and MIPS32 and later
73 architectures allow 20 bits to be set with a signal operand
74 (using CODE20).
75
76 The syscall instruction uses CODE20.
77
78 The general coprocessor instructions use COPZ. */
79
80 #define OP_MASK_OP 0x3f
81 #define OP_SH_OP 26
82 #define OP_MASK_RS 0x1f
83 #define OP_SH_RS 21
84 #define OP_MASK_FR 0x1f
85 #define OP_SH_FR 21
86 #define OP_MASK_FMT 0x1f
87 #define OP_SH_FMT 21
88 #define OP_MASK_BCC 0x7
89 #define OP_SH_BCC 18
90 #define OP_MASK_CODE 0x3ff
91 #define OP_SH_CODE 16
92 #define OP_MASK_CODE2 0x3ff
93 #define OP_SH_CODE2 6
94 #define OP_MASK_RT 0x1f
95 #define OP_SH_RT 16
96 #define OP_MASK_FT 0x1f
97 #define OP_SH_FT 16
98 #define OP_MASK_CACHE 0x1f
99 #define OP_SH_CACHE 16
100 #define OP_MASK_RD 0x1f
101 #define OP_SH_RD 11
102 #define OP_MASK_FS 0x1f
103 #define OP_SH_FS 11
104 #define OP_MASK_PREFX 0x1f
105 #define OP_SH_PREFX 11
106 #define OP_MASK_CCC 0x7
107 #define OP_SH_CCC 8
108 #define OP_MASK_CODE20 0xfffff /* 20 bit syscall/breakpoint code. */
109 #define OP_SH_CODE20 6
110 #define OP_MASK_SHAMT 0x1f
111 #define OP_SH_SHAMT 6
112 #define OP_MASK_FD 0x1f
113 #define OP_SH_FD 6
114 #define OP_MASK_TARGET 0x3ffffff
115 #define OP_SH_TARGET 0
116 #define OP_MASK_COPZ 0x1ffffff
117 #define OP_SH_COPZ 0
118 #define OP_MASK_IMMEDIATE 0xffff
119 #define OP_SH_IMMEDIATE 0
120 #define OP_MASK_DELTA 0xffff
121 #define OP_SH_DELTA 0
122 #define OP_MASK_DELTA_R6 0x1ff
123 #define OP_SH_DELTA_R6 7
124 #define OP_MASK_FUNCT 0x3f
125 #define OP_SH_FUNCT 0
126 #define OP_MASK_SPEC 0x3f
127 #define OP_SH_SPEC 0
128 #define OP_SH_LOCC 8 /* FP condition code. */
129 #define OP_SH_HICC 18 /* FP condition code. */
130 #define OP_MASK_CC 0x7
131 #define OP_SH_COP1NORM 25 /* Normal COP1 encoding. */
132 #define OP_MASK_COP1NORM 0x1 /* a single bit. */
133 #define OP_SH_COP1SPEC 21 /* COP1 encodings. */
134 #define OP_MASK_COP1SPEC 0xf
135 #define OP_MASK_COP1SCLR 0x4
136 #define OP_MASK_COP1CMP 0x3
137 #define OP_SH_COP1CMP 4
138 #define OP_SH_FORMAT 21 /* FP short format field. */
139 #define OP_MASK_FORMAT 0x7
140 #define OP_SH_TRUE 16
141 #define OP_MASK_TRUE 0x1
142 #define OP_SH_GE 17
143 #define OP_MASK_GE 0x01
144 #define OP_SH_UNSIGNED 16
145 #define OP_MASK_UNSIGNED 0x1
146 #define OP_SH_HINT 16
147 #define OP_MASK_HINT 0x1f
148 #define OP_SH_MMI 0 /* Multimedia (parallel) op. */
149 #define OP_MASK_MMI 0x3f
150 #define OP_SH_MMISUB 6
151 #define OP_MASK_MMISUB 0x1f
152 #define OP_MASK_PERFREG 0x1f /* Performance monitoring. */
153 #define OP_SH_PERFREG 1
154 #define OP_SH_SEL 0 /* Coprocessor select field. */
155 #define OP_MASK_SEL 0x7 /* The sel field of mfcZ and mtcZ. */
156 #define OP_SH_CODE19 6 /* 19 bit wait code. */
157 #define OP_MASK_CODE19 0x7ffff
158 #define OP_SH_ALN 21
159 #define OP_MASK_ALN 0x7
160 #define OP_SH_VSEL 21
161 #define OP_MASK_VSEL 0x1f
162 #define OP_MASK_VECBYTE 0x7 /* Selector field is really 4 bits,
163 but 0x8-0xf don't select bytes. */
164 #define OP_SH_VECBYTE 22
165 #define OP_MASK_VECALIGN 0x7 /* Vector byte-align (alni.ob) op. */
166 #define OP_SH_VECALIGN 21
167 #define OP_MASK_INSMSB 0x1f /* "ins" MSB. */
168 #define OP_SH_INSMSB 11
169 #define OP_MASK_EXTMSBD 0x1f /* "ext" MSBD. */
170 #define OP_SH_EXTMSBD 11
171
172 #define OP_OP_COP0 0x10
173 #define OP_OP_COP1 0x11
174 #define OP_OP_COP2 0x12
175 #define OP_OP_COP3 0x13
176 #define OP_OP_LWC1 0x31
177 #define OP_OP_LWC2 0x32
178 #define OP_OP_LWC3 0x33 /* a.k.a. pref */
179 #define OP_OP_LDC1 0x35
180 #define OP_OP_LDC2 0x36
181 #define OP_OP_LDC3 0x37 /* a.k.a. ld */
182 #define OP_OP_SWC1 0x39
183 #define OP_OP_SWC2 0x3a
184 #define OP_OP_SWC3 0x3b
185 #define OP_OP_SDC1 0x3d
186 #define OP_OP_SDC2 0x3e
187 #define OP_OP_SDC3 0x3f /* a.k.a. sd */
188
189 /* MIPS DSP ASE */
190 #define OP_SH_DSPACC 11
191 #define OP_MASK_DSPACC 0x3
192 #define OP_SH_DSPACC_S 21
193 #define OP_MASK_DSPACC_S 0x3
194 #define OP_SH_DSPSFT 20
195 #define OP_MASK_DSPSFT 0x3f
196 #define OP_SH_DSPSFT_7 19
197 #define OP_MASK_DSPSFT_7 0x7f
198 #define OP_SH_SA3 21
199 #define OP_MASK_SA3 0x7
200 #define OP_SH_SA4 21
201 #define OP_MASK_SA4 0xf
202 #define OP_SH_IMM8 16
203 #define OP_MASK_IMM8 0xff
204 #define OP_SH_IMM10 16
205 #define OP_MASK_IMM10 0x3ff
206 #define OP_SH_WRDSP 11
207 #define OP_MASK_WRDSP 0x3f
208 #define OP_SH_RDDSP 16
209 #define OP_MASK_RDDSP 0x3f
210 #define OP_SH_BP 11
211 #define OP_MASK_BP 0x3
212
213 /* MIPS MT ASE */
214 #define OP_SH_MT_U 5
215 #define OP_MASK_MT_U 0x1
216 #define OP_SH_MT_H 4
217 #define OP_MASK_MT_H 0x1
218 #define OP_SH_MTACC_T 18
219 #define OP_MASK_MTACC_T 0x3
220 #define OP_SH_MTACC_D 13
221 #define OP_MASK_MTACC_D 0x3
222
223 #define OP_OP_COP0 0x10
224 #define OP_OP_COP1 0x11
225 #define OP_OP_COP2 0x12
226 #define OP_OP_COP3 0x13
227 #define OP_OP_LWC1 0x31
228 #define OP_OP_LWC2 0x32
229 #define OP_OP_LWC3 0x33 /* a.k.a. pref */
230 #define OP_OP_LDC1 0x35
231 #define OP_OP_LDC2 0x36
232 #define OP_OP_LDC3 0x37 /* a.k.a. ld */
233 #define OP_OP_SWC1 0x39
234 #define OP_OP_SWC2 0x3a
235 #define OP_OP_SWC3 0x3b
236 #define OP_OP_SDC1 0x3d
237 #define OP_OP_SDC2 0x3e
238 #define OP_OP_SDC3 0x3f /* a.k.a. sd */
239
240 /* Values in the 'VSEL' field. */
241 #define MDMX_FMTSEL_IMM_QH 0x1d
242 #define MDMX_FMTSEL_IMM_OB 0x1e
243 #define MDMX_FMTSEL_VEC_QH 0x15
244 #define MDMX_FMTSEL_VEC_OB 0x16
245
246 /* UDI */
247 #define OP_SH_UDI1 6
248 #define OP_MASK_UDI1 0x1f
249 #define OP_SH_UDI2 6
250 #define OP_MASK_UDI2 0x3ff
251 #define OP_SH_UDI3 6
252 #define OP_MASK_UDI3 0x7fff
253 #define OP_SH_UDI4 6
254 #define OP_MASK_UDI4 0xfffff
255 /* This structure holds information for a particular instruction. */
256
257 struct mips_opcode
258 {
259 /* The name of the instruction. */
260 const char *name;
261 /* A string describing the arguments for this instruction. */
262 const char *args;
263 /* The basic opcode for the instruction. When assembling, this
264 opcode is modified by the arguments to produce the actual opcode
265 that is used. If pinfo is INSN_MACRO, then this is 0. */
266 unsigned long match;
267 /* If pinfo is not INSN_MACRO, then this is a bit mask for the
268 relevant portions of the opcode when disassembling. If the
269 actual opcode anded with the match field equals the opcode field,
270 then we have found the correct instruction. If pinfo is
271 INSN_MACRO, then this field is the macro identifier. */
272 unsigned long mask;
273 /* For a macro, this is INSN_MACRO. Otherwise, it is a collection
274 of bits describing the instruction, notably any relevant hazard
275 information. */
276 unsigned long pinfo;
277 /* A collection of additional bits describing the instruction. */
278 unsigned long pinfo2;
279 /* A collection of bits describing the instruction sets of which this
280 instruction or macro is a member. */
281 unsigned long membership;
282 };
283
284 /* These are the characters which may appear in the args field of an
285 instruction. They appear in the order in which the fields appear
286 when the instruction is used. Commas and parentheses in the args
287 string are ignored when assembling, and written into the output
288 when disassembling.
289
290 Each of these characters corresponds to a mask field defined above.
291
292 "<" 5 bit shift amount (OP_*_SHAMT)
293 ">" shift amount between 32 and 63, stored after subtracting 32 (OP_*_SHAMT)
294 "a" 26 bit target address (OP_*_TARGET)
295 "b" 5 bit base register (OP_*_RS)
296 "c" 10 bit breakpoint code (OP_*_CODE)
297 "d" 5 bit destination register specifier (OP_*_RD)
298 "h" 5 bit prefx hint (OP_*_PREFX)
299 "i" 16 bit unsigned immediate (OP_*_IMMEDIATE)
300 "j" 16 bit signed immediate (OP_*_DELTA)
301 "k" 5 bit cache opcode in target register position (OP_*_CACHE)
302 Also used for immediate operands in vr5400 vector insns.
303 "o" 16 bit signed offset (OP_*_DELTA)
304 "p" 16 bit PC relative branch target address (OP_*_DELTA)
305 "q" 10 bit extra breakpoint code (OP_*_CODE2)
306 "r" 5 bit same register used as both source and target (OP_*_RS)
307 "s" 5 bit source register specifier (OP_*_RS)
308 "t" 5 bit target register (OP_*_RT)
309 "u" 16 bit upper 16 bits of address (OP_*_IMMEDIATE)
310 "v" 5 bit same register used as both source and destination (OP_*_RS)
311 "w" 5 bit same register used as both target and destination (OP_*_RT)
312 "U" 5 bit same destination register in both OP_*_RD and OP_*_RT
313 (used by clo and clz)
314 "C" 25 bit coprocessor function code (OP_*_COPZ)
315 "B" 20 bit syscall/breakpoint function code (OP_*_CODE20)
316 "J" 19 bit wait function code (OP_*_CODE19)
317 "x" accept and ignore register name
318 "z" must be zero register
319 "K" 5 bit Hardware Register (rdhwr instruction) (OP_*_RD)
320 "+A" 5 bit ins/ext/dins/dext/dinsm/dextm position, which becomes
321 LSB (OP_*_SHAMT).
322 Enforces: 0 <= pos < 32.
323 "+B" 5 bit ins/dins size, which becomes MSB (OP_*_INSMSB).
324 Requires that "+A" or "+E" occur first to set position.
325 Enforces: 0 < (pos+size) <= 32.
326 "+C" 5 bit ext/dext size, which becomes MSBD (OP_*_EXTMSBD).
327 Requires that "+A" or "+E" occur first to set position.
328 Enforces: 0 < (pos+size) <= 32.
329 (Also used by "dext" w/ different limits, but limits for
330 that are checked by the M_DEXT macro.)
331 "+E" 5 bit dinsu/dextu position, which becomes LSB-32 (OP_*_SHAMT).
332 Enforces: 32 <= pos < 64.
333 "+F" 5 bit "dinsm/dinsu" size, which becomes MSB-32 (OP_*_INSMSB).
334 Requires that "+A" or "+E" occur first to set position.
335 Enforces: 32 < (pos+size) <= 64.
336 "+G" 5 bit "dextm" size, which becomes MSBD-32 (OP_*_EXTMSBD).
337 Requires that "+A" or "+E" occur first to set position.
338 Enforces: 32 < (pos+size) <= 64.
339 "+H" 5 bit "dextu" size, which becomes MSBD (OP_*_EXTMSBD).
340 Requires that "+A" or "+E" occur first to set position.
341 Enforces: 32 < (pos+size) <= 64.
342
343 Floating point instructions:
344 "D" 5 bit destination register (OP_*_FD)
345 "M" 3 bit compare condition code (OP_*_CCC) (only used for mips4 and up)
346 "N" 3 bit branch condition code (OP_*_BCC) (only used for mips4 and up)
347 "S" 5 bit fs source 1 register (OP_*_FS)
348 "T" 5 bit ft source 2 register (OP_*_FT)
349 "R" 5 bit fr source 3 register (OP_*_FR)
350 "V" 5 bit same register used as floating source and destination (OP_*_FS)
351 "W" 5 bit same register used as floating target and destination (OP_*_FT)
352
353 Coprocessor instructions:
354 "E" 5 bit target register (OP_*_RT)
355 "G" 5 bit destination register (OP_*_RD)
356 "H" 3 bit sel field for (d)mtc* and (d)mfc* (OP_*_SEL)
357 "P" 5 bit performance-monitor register (OP_*_PERFREG)
358 "e" 5 bit vector register byte specifier (OP_*_VECBYTE)
359 "%" 3 bit immediate vr5400 vector alignment operand (OP_*_VECALIGN)
360 see also "k" above
361 "+D" Combined destination register ("G") and sel ("H") for CP0 ops,
362 for pretty-printing in disassembly only.
363
364 Macro instructions:
365 "A" General 32 bit expression
366 "I" 32 bit immediate (value placed in imm_expr).
367 "+I" 32 bit immediate (value placed in imm2_expr).
368 "F" 64 bit floating point constant in .rdata
369 "L" 64 bit floating point constant in .lit8
370 "f" 32 bit floating point constant
371 "l" 32 bit floating point constant in .lit4
372
373 MDMX instruction operands (note that while these use the FP register
374 fields, they accept both $fN and $vN names for the registers):
375 "O" MDMX alignment offset (OP_*_ALN)
376 "Q" MDMX vector/scalar/immediate source (OP_*_VSEL and OP_*_FT)
377 "X" MDMX destination register (OP_*_FD)
378 "Y" MDMX source register (OP_*_FS)
379 "Z" MDMX source register (OP_*_FT)
380
381 DSP ASE usage:
382 "2" 2 bit unsigned immediate for byte align (OP_*_BP)
383 "3" 3 bit unsigned immediate (OP_*_SA3)
384 "4" 4 bit unsigned immediate (OP_*_SA4)
385 "5" 8 bit unsigned immediate (OP_*_IMM8)
386 "6" 5 bit unsigned immediate (OP_*_RS)
387 "7" 2 bit dsp accumulator register (OP_*_DSPACC)
388 "8" 6 bit unsigned immediate (OP_*_WRDSP)
389 "9" 2 bit dsp accumulator register (OP_*_DSPACC_S)
390 "0" 6 bit signed immediate (OP_*_DSPSFT)
391 ":" 7 bit signed immediate (OP_*_DSPSFT_7)
392 "'" 6 bit unsigned immediate (OP_*_RDDSP)
393 "@" 10 bit signed immediate (OP_*_IMM10)
394
395 MT ASE usage:
396 "!" 1 bit usermode flag (OP_*_MT_U)
397 "$" 1 bit load high flag (OP_*_MT_H)
398 "*" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_T)
399 "&" 2 bit dsp/smartmips accumulator register (OP_*_MTACC_D)
400 "g" 5 bit coprocessor 1 and 2 destination register (OP_*_RD)
401 "+t" 5 bit coprocessor 0 destination register (OP_*_RT)
402 "+T" 5 bit coprocessor 0 destination register (OP_*_RT) - disassembly only
403
404 UDI immediates:
405 "+1" UDI immediate bits 6-10
406 "+2" UDI immediate bits 6-15
407 "+3" UDI immediate bits 6-20
408 "+4" UDI immediate bits 6-25
409
410 Other:
411 "()" parens surrounding optional value
412 "," separates operands
413 "[]" brackets around index for vector-op scalar operand specifier (vr5400)
414 "+" Start of extension sequence.
415
416 Characters used so far, for quick reference when adding more:
417 "234567890"
418 "%[]<>(),+:'@!$*&"
419 "ABCDEFGHIJKLMNOPQRSTUVWXYZ"
420 "abcdefghijklopqrstuvwxz"
421
422 Extension character sequences used so far ("+" followed by the
423 following), for quick reference when adding more:
424 "1234"
425 "ABCDEFGHIT"
426 "t"
427 */
428
429 /* These are the bits which may be set in the pinfo field of an
430 instructions, if it is not equal to INSN_MACRO. */
431
432 /* Modifies the general purpose register in OP_*_RD. */
433 #define INSN_WRITE_GPR_D 0x00000001
434 /* Modifies the general purpose register in OP_*_RT. */
435 #define INSN_WRITE_GPR_T 0x00000002
436 /* Modifies general purpose register 31. */
437 #define INSN_WRITE_GPR_31 0x00000004
438 /* Modifies the floating point register in OP_*_FD. */
439 #define INSN_WRITE_FPR_D 0x00000008
440 /* Modifies the floating point register in OP_*_FS. */
441 #define INSN_WRITE_FPR_S 0x00000010
442 /* Modifies the floating point register in OP_*_FT. */
443 #define INSN_WRITE_FPR_T 0x00000020
444 /* Reads the general purpose register in OP_*_RS. */
445 #define INSN_READ_GPR_S 0x00000040
446 /* Reads the general purpose register in OP_*_RT. */
447 #define INSN_READ_GPR_T 0x00000080
448 /* Reads the floating point register in OP_*_FS. */
449 #define INSN_READ_FPR_S 0x00000100
450 /* Reads the floating point register in OP_*_FT. */
451 #define INSN_READ_FPR_T 0x00000200
452 /* Reads the floating point register in OP_*_FR. */
453 #define INSN_READ_FPR_R 0x00000400
454 /* Modifies coprocessor condition code. */
455 #define INSN_WRITE_COND_CODE 0x00000800
456 /* Reads coprocessor condition code. */
457 #define INSN_READ_COND_CODE 0x00001000
458 /* TLB operation. */
459 #define INSN_TLB 0x00002000
460 /* Reads coprocessor register other than floating point register. */
461 #define INSN_COP 0x00004000
462 /* Instruction loads value from memory, requiring delay. */
463 #define INSN_LOAD_MEMORY_DELAY 0x00008000
464 /* Instruction loads value from coprocessor, requiring delay. */
465 #define INSN_LOAD_COPROC_DELAY 0x00010000
466 /* Instruction has unconditional branch delay slot. */
467 #define INSN_UNCOND_BRANCH_DELAY 0x00020000
468 /* Instruction has conditional branch delay slot. */
469 #define INSN_COND_BRANCH_DELAY 0x00040000
470 /* Conditional branch likely: if branch not taken, insn nullified. */
471 #define INSN_COND_BRANCH_LIKELY 0x00080000
472 /* Moves to coprocessor register, requiring delay. */
473 #define INSN_COPROC_MOVE_DELAY 0x00100000
474 /* Loads coprocessor register from memory, requiring delay. */
475 #define INSN_COPROC_MEMORY_DELAY 0x00200000
476 /* Reads the HI register. */
477 #define INSN_READ_HI 0x00400000
478 /* Reads the LO register. */
479 #define INSN_READ_LO 0x00800000
480 /* Modifies the HI register. */
481 #define INSN_WRITE_HI 0x01000000
482 /* Modifies the LO register. */
483 #define INSN_WRITE_LO 0x02000000
484 /* Takes a trap (easier to keep out of delay slot). */
485 #define INSN_TRAP 0x04000000
486 /* Instruction stores value into memory. */
487 #define INSN_STORE_MEMORY 0x08000000
488 /* Instruction uses single precision floating point. */
489 #define FP_S 0x10000000
490 /* Instruction uses double precision floating point. */
491 #define FP_D 0x20000000
492 /* Instruction is part of the tx39's integer multiply family. */
493 #define INSN_MULT 0x40000000
494 /* Instruction synchronize shared memory. */
495 #define INSN_SYNC 0x80000000
496
497 /* These are the bits which may be set in the pinfo2 field of an
498 instruction. */
499
500 /* Instruction is a simple alias (I.E. "move" for daddu/addu/or) */
501 #define INSN2_ALIAS 0x00000001
502 /* Instruction reads MDMX accumulator. */
503 #define INSN2_READ_MDMX_ACC 0x00000002
504 /* Instruction writes MDMX accumulator. */
505 #define INSN2_WRITE_MDMX_ACC 0x00000004
506
507 /* Instruction is actually a macro. It should be ignored by the
508 disassembler, and requires special treatment by the assembler. */
509 #define INSN_MACRO 0xffffffff
510
511 /* Masks used to mark instructions to indicate which MIPS ISA level
512 they were introduced in. ISAs, as defined below, are logical
513 ORs of these bits, indicating that they support the instructions
514 defined at the given level. */
515
516 #define INSN_ISA_MASK 0x00000fff
517 #define INSN_ISA1 0x00000001
518 #define INSN_ISA2 0x00000002
519 #define INSN_ISA3 0x00000004
520 #define INSN_ISA4 0x00000008
521 #define INSN_ISA5 0x00000010
522 #define INSN_ISA32 0x00000020
523 #define INSN_ISA64 0x00000040
524 #define INSN_ISA32R2 0x00000080
525 #define INSN_ISA64R2 0x00000100
526 #define INSN_ISA32R6 0x00000200
527 #define INSN_ISA64R6 0x00000400
528
529 /* Masks used for MIPS-defined ASEs. */
530 #define INSN_ASE_MASK 0x0000f000
531
532 /* DSP ASE */
533 #define INSN_DSP 0x00001000
534 #define INSN_DSP64 0x00002000
535 /* MIPS 16 ASE */
536 #define INSN_MIPS16 0x00004000
537 /* MIPS-3D ASE */
538 #define INSN_MIPS3D 0x00008000
539
540 /* Chip specific instructions. These are bitmasks. */
541
542 /* MIPS R4650 instruction. */
543 #define INSN_4650 0x00010000
544 /* LSI R4010 instruction. */
545 #define INSN_4010 0x00020000
546 /* NEC VR4100 instruction. */
547 #define INSN_4100 0x00040000
548 /* Toshiba R3900 instruction. */
549 #define INSN_3900 0x00080000
550 /* MIPS R10000 instruction. */
551 #define INSN_10000 0x00100000
552 /* Broadcom SB-1 instruction. */
553 #define INSN_SB1 0x00200000
554 /* NEC VR4111/VR4181 instruction. */
555 #define INSN_4111 0x00400000
556 /* NEC VR4120 instruction. */
557 #define INSN_4120 0x00800000
558 /* NEC VR5400 instruction. */
559 #define INSN_5400 0x01000000
560 /* NEC VR5500 instruction. */
561 #define INSN_5500 0x02000000
562
563 /* MDMX ASE */
564 #define INSN_MDMX 0x04000000
565 /* MT ASE */
566 #define INSN_MT 0x08000000
567 /* SmartMIPS ASE */
568 #define INSN_SMARTMIPS 0x10000000
569 /* DSP R2 ASE */
570 #define INSN_DSPR2 0x20000000
571
572 /* ST Microelectronics Loongson 2E. */
573 #define INSN_LOONGSON_2E 0x40000000
574 /* ST Microelectronics Loongson 2F. */
575 #define INSN_LOONGSON_2F 0x80000000
576
577 /* MIPS ISA defines, use instead of hardcoding ISA level. */
578
579 #define ISA_UNKNOWN 0 /* Gas internal use. */
580 #define ISA_MIPS1 (INSN_ISA1)
581 #define ISA_MIPS2 (ISA_MIPS1 | INSN_ISA2)
582 #define ISA_MIPS3 (ISA_MIPS2 | INSN_ISA3)
583 #define ISA_MIPS4 (ISA_MIPS3 | INSN_ISA4)
584 #define ISA_MIPS5 (ISA_MIPS4 | INSN_ISA5)
585
586 #define ISA_MIPS32 (ISA_MIPS2 | INSN_ISA32)
587 #define ISA_MIPS64 (ISA_MIPS5 | INSN_ISA32 | INSN_ISA64)
588
589 #define ISA_MIPS32R2 (ISA_MIPS32 | INSN_ISA32R2)
590 #define ISA_MIPS64R2 (ISA_MIPS64 | INSN_ISA32R2 | INSN_ISA64R2)
591
592 #define ISA_MIPS32R6 (ISA_MIPS32R2 | INSN_ISA32R6)
593 #define ISA_MIPS64R6 (ISA_MIPS64R2 | INSN_ISA32R6 | INSN_ISA64R6)
594
595 /* CPU defines, use instead of hardcoding processor number. Keep this
596 in sync with bfd/archures.c in order for machine selection to work. */
597 #define CPU_UNKNOWN 0 /* Gas internal use. */
598 #define CPU_R3000 3000
599 #define CPU_R3900 3900
600 #define CPU_R4000 4000
601 #define CPU_R4010 4010
602 #define CPU_VR4100 4100
603 #define CPU_R4111 4111
604 #define CPU_VR4120 4120
605 #define CPU_R4300 4300
606 #define CPU_R4400 4400
607 #define CPU_R4600 4600
608 #define CPU_R4650 4650
609 #define CPU_R5000 5000
610 #define CPU_VR5400 5400
611 #define CPU_VR5500 5500
612 #define CPU_R6000 6000
613 #define CPU_RM7000 7000
614 #define CPU_R8000 8000
615 #define CPU_R10000 10000
616 #define CPU_R12000 12000
617 #define CPU_MIPS16 16
618 #define CPU_MIPS32 32
619 #define CPU_MIPS32R2 33
620 #define CPU_MIPS5 5
621 #define CPU_MIPS64 64
622 #define CPU_MIPS64R2 65
623 #define CPU_SB1 12310201 /* octal 'SB', 01. */
624
625 /* Test for membership in an ISA including chip specific ISAs. INSN
626 is pointer to an element of the opcode table; ISA is the specified
627 ISA/ASE bitmask to test against; and CPU is the CPU specific ISA to
628 test, or zero if no CPU specific ISA test is desired. */
629
630 #if 0
631 #define OPCODE_IS_MEMBER(insn, isa, cpu) \
632 (((insn)->membership & isa) != 0 \
633 || (cpu == CPU_R4650 && ((insn)->membership & INSN_4650) != 0) \
634 || (cpu == CPU_RM7000 && ((insn)->membership & INSN_4650) != 0) \
635 || (cpu == CPU_RM9000 && ((insn)->membership & INSN_4650) != 0) \
636 || (cpu == CPU_R4010 && ((insn)->membership & INSN_4010) != 0) \
637 || (cpu == CPU_VR4100 && ((insn)->membership & INSN_4100) != 0) \
638 || (cpu == CPU_R3900 && ((insn)->membership & INSN_3900) != 0) \
639 || ((cpu == CPU_R10000 || cpu == CPU_R12000) \
640 && ((insn)->membership & INSN_10000) != 0) \
641 || (cpu == CPU_SB1 && ((insn)->membership & INSN_SB1) != 0) \
642 || (cpu == CPU_R4111 && ((insn)->membership & INSN_4111) != 0) \
643 || (cpu == CPU_VR4120 && ((insn)->membership & INSN_4120) != 0) \
644 || (cpu == CPU_VR5400 && ((insn)->membership & INSN_5400) != 0) \
645 || (cpu == CPU_VR5500 && ((insn)->membership & INSN_5500) != 0) \
646 || 0) /* Please keep this term for easier source merging. */
647 #else
648 #define OPCODE_IS_MEMBER(insn, isa, cpu) \
649 (1 != 0)
650 #endif
651
652 /* This is a list of macro expanded instructions.
653
654 _I appended means immediate
655 _A appended means address
656 _AB appended means address with base register
657 _D appended means 64 bit floating point constant
658 _S appended means 32 bit floating point constant. */
659
660 enum
661 {
662 M_ABS,
663 M_ADD_I,
664 M_ADDU_I,
665 M_AND_I,
666 M_BALIGN,
667 M_BEQ,
668 M_BEQ_I,
669 M_BEQL_I,
670 M_BGE,
671 M_BGEL,
672 M_BGE_I,
673 M_BGEL_I,
674 M_BGEU,
675 M_BGEUL,
676 M_BGEU_I,
677 M_BGEUL_I,
678 M_BGT,
679 M_BGTL,
680 M_BGT_I,
681 M_BGTL_I,
682 M_BGTU,
683 M_BGTUL,
684 M_BGTU_I,
685 M_BGTUL_I,
686 M_BLE,
687 M_BLEL,
688 M_BLE_I,
689 M_BLEL_I,
690 M_BLEU,
691 M_BLEUL,
692 M_BLEU_I,
693 M_BLEUL_I,
694 M_BLT,
695 M_BLTL,
696 M_BLT_I,
697 M_BLTL_I,
698 M_BLTU,
699 M_BLTUL,
700 M_BLTU_I,
701 M_BLTUL_I,
702 M_BNE,
703 M_BNE_I,
704 M_BNEL_I,
705 M_CACHE_AB,
706 M_DABS,
707 M_DADD_I,
708 M_DADDU_I,
709 M_DDIV_3,
710 M_DDIV_3I,
711 M_DDIVU_3,
712 M_DDIVU_3I,
713 M_DEXT,
714 M_DINS,
715 M_DIV_3,
716 M_DIV_3I,
717 M_DIVU_3,
718 M_DIVU_3I,
719 M_DLA_AB,
720 M_DLCA_AB,
721 M_DLI,
722 M_DMUL,
723 M_DMUL_I,
724 M_DMULO,
725 M_DMULO_I,
726 M_DMULOU,
727 M_DMULOU_I,
728 M_DREM_3,
729 M_DREM_3I,
730 M_DREMU_3,
731 M_DREMU_3I,
732 M_DSUB_I,
733 M_DSUBU_I,
734 M_DSUBU_I_2,
735 M_J_A,
736 M_JAL_1,
737 M_JAL_2,
738 M_JAL_A,
739 M_L_DOB,
740 M_L_DAB,
741 M_LA_AB,
742 M_LB_A,
743 M_LB_AB,
744 M_LBU_A,
745 M_LBU_AB,
746 M_LCA_AB,
747 M_LD_A,
748 M_LD_OB,
749 M_LD_AB,
750 M_LDC1_AB,
751 M_LDC2_AB,
752 M_LDC3_AB,
753 M_LDL_AB,
754 M_LDR_AB,
755 M_LH_A,
756 M_LH_AB,
757 M_LHU_A,
758 M_LHU_AB,
759 M_LI,
760 M_LI_D,
761 M_LI_DD,
762 M_LI_S,
763 M_LI_SS,
764 M_LL_AB,
765 M_LLD_AB,
766 M_LS_A,
767 M_LW_A,
768 M_LW_AB,
769 M_LWC0_A,
770 M_LWC0_AB,
771 M_LWC1_A,
772 M_LWC1_AB,
773 M_LWC2_A,
774 M_LWC2_AB,
775 M_LWC3_A,
776 M_LWC3_AB,
777 M_LWL_A,
778 M_LWL_AB,
779 M_LWR_A,
780 M_LWR_AB,
781 M_LWU_AB,
782 M_MOVE,
783 M_MUL,
784 M_MUL_I,
785 M_MULO,
786 M_MULO_I,
787 M_MULOU,
788 M_MULOU_I,
789 M_NOR_I,
790 M_OR_I,
791 M_REM_3,
792 M_REM_3I,
793 M_REMU_3,
794 M_REMU_3I,
795 M_DROL,
796 M_ROL,
797 M_DROL_I,
798 M_ROL_I,
799 M_DROR,
800 M_ROR,
801 M_DROR_I,
802 M_ROR_I,
803 M_S_DA,
804 M_S_DOB,
805 M_S_DAB,
806 M_S_S,
807 M_SC_AB,
808 M_SCD_AB,
809 M_SD_A,
810 M_SD_OB,
811 M_SD_AB,
812 M_SDC1_AB,
813 M_SDC2_AB,
814 M_SDC3_AB,
815 M_SDL_AB,
816 M_SDR_AB,
817 M_SEQ,
818 M_SEQ_I,
819 M_SGE,
820 M_SGE_I,
821 M_SGEU,
822 M_SGEU_I,
823 M_SGT,
824 M_SGT_I,
825 M_SGTU,
826 M_SGTU_I,
827 M_SLE,
828 M_SLE_I,
829 M_SLEU,
830 M_SLEU_I,
831 M_SLT_I,
832 M_SLTU_I,
833 M_SNE,
834 M_SNE_I,
835 M_SB_A,
836 M_SB_AB,
837 M_SH_A,
838 M_SH_AB,
839 M_SW_A,
840 M_SW_AB,
841 M_SWC0_A,
842 M_SWC0_AB,
843 M_SWC1_A,
844 M_SWC1_AB,
845 M_SWC2_A,
846 M_SWC2_AB,
847 M_SWC3_A,
848 M_SWC3_AB,
849 M_SWL_A,
850 M_SWL_AB,
851 M_SWR_A,
852 M_SWR_AB,
853 M_SUB_I,
854 M_SUBU_I,
855 M_SUBU_I_2,
856 M_TEQ_I,
857 M_TGE_I,
858 M_TGEU_I,
859 M_TLT_I,
860 M_TLTU_I,
861 M_TNE_I,
862 M_TRUNCWD,
863 M_TRUNCWS,
864 M_ULD,
865 M_ULD_A,
866 M_ULH,
867 M_ULH_A,
868 M_ULHU,
869 M_ULHU_A,
870 M_ULW,
871 M_ULW_A,
872 M_USH,
873 M_USH_A,
874 M_USW,
875 M_USW_A,
876 M_USD,
877 M_USD_A,
878 M_XOR_I,
879 M_COP0,
880 M_COP1,
881 M_COP2,
882 M_COP3,
883 M_NUM_MACROS
884 };
885
886
887 /* The order of overloaded instructions matters. Label arguments and
888 register arguments look the same. Instructions that can have either
889 for arguments must apear in the correct order in this table for the
890 assembler to pick the right one. In other words, entries with
891 immediate operands must apear after the same instruction with
892 registers.
893
894 Many instructions are short hand for other instructions (i.e., The
895 jal <register> instruction is short for jalr <register>). */
896
897 extern const struct mips_opcode mips_builtin_opcodes[];
898 extern const int bfd_mips_num_builtin_opcodes;
899 extern struct mips_opcode *mips_opcodes;
900 extern int bfd_mips_num_opcodes;
901 #define NUMOPCODES bfd_mips_num_opcodes
902
903 \f
904 /* The rest of this file adds definitions for the mips16 TinyRISC
905 processor. */
906
907 /* These are the bitmasks and shift counts used for the different
908 fields in the instruction formats. Other than OP, no masks are
909 provided for the fixed portions of an instruction, since they are
910 not needed.
911
912 The I format uses IMM11.
913
914 The RI format uses RX and IMM8.
915
916 The RR format uses RX, and RY.
917
918 The RRI format uses RX, RY, and IMM5.
919
920 The RRR format uses RX, RY, and RZ.
921
922 The RRI_A format uses RX, RY, and IMM4.
923
924 The SHIFT format uses RX, RY, and SHAMT.
925
926 The I8 format uses IMM8.
927
928 The I8_MOVR32 format uses RY and REGR32.
929
930 The IR_MOV32R format uses REG32R and MOV32Z.
931
932 The I64 format uses IMM8.
933
934 The RI64 format uses RY and IMM5.
935 */
936
937 #define MIPS16OP_MASK_OP 0x1f
938 #define MIPS16OP_SH_OP 11
939 #define MIPS16OP_MASK_IMM11 0x7ff
940 #define MIPS16OP_SH_IMM11 0
941 #define MIPS16OP_MASK_RX 0x7
942 #define MIPS16OP_SH_RX 8
943 #define MIPS16OP_MASK_IMM8 0xff
944 #define MIPS16OP_SH_IMM8 0
945 #define MIPS16OP_MASK_RY 0x7
946 #define MIPS16OP_SH_RY 5
947 #define MIPS16OP_MASK_IMM5 0x1f
948 #define MIPS16OP_SH_IMM5 0
949 #define MIPS16OP_MASK_RZ 0x7
950 #define MIPS16OP_SH_RZ 2
951 #define MIPS16OP_MASK_IMM4 0xf
952 #define MIPS16OP_SH_IMM4 0
953 #define MIPS16OP_MASK_REGR32 0x1f
954 #define MIPS16OP_SH_REGR32 0
955 #define MIPS16OP_MASK_REG32R 0x1f
956 #define MIPS16OP_SH_REG32R 3
957 #define MIPS16OP_EXTRACT_REG32R(i) ((((i) >> 5) & 7) | ((i) & 0x18))
958 #define MIPS16OP_MASK_MOVE32Z 0x7
959 #define MIPS16OP_SH_MOVE32Z 0
960 #define MIPS16OP_MASK_IMM6 0x3f
961 #define MIPS16OP_SH_IMM6 5
962
963 /* These are the characters which may appears in the args field of an
964 instruction. They appear in the order in which the fields appear
965 when the instruction is used. Commas and parentheses in the args
966 string are ignored when assembling, and written into the output
967 when disassembling.
968
969 "y" 3 bit register (MIPS16OP_*_RY)
970 "x" 3 bit register (MIPS16OP_*_RX)
971 "z" 3 bit register (MIPS16OP_*_RZ)
972 "Z" 3 bit register (MIPS16OP_*_MOVE32Z)
973 "v" 3 bit same register as source and destination (MIPS16OP_*_RX)
974 "w" 3 bit same register as source and destination (MIPS16OP_*_RY)
975 "0" zero register ($0)
976 "S" stack pointer ($sp or $29)
977 "P" program counter
978 "R" return address register ($ra or $31)
979 "X" 5 bit MIPS register (MIPS16OP_*_REGR32)
980 "Y" 5 bit MIPS register (MIPS16OP_*_REG32R)
981 "6" 6 bit unsigned break code (MIPS16OP_*_IMM6)
982 "a" 26 bit jump address
983 "e" 11 bit extension value
984 "l" register list for entry instruction
985 "L" register list for exit instruction
986
987 The remaining codes may be extended. Except as otherwise noted,
988 the full extended operand is a 16 bit signed value.
989 "<" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 5 bit unsigned)
990 ">" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 5 bit unsigned)
991 "[" 3 bit unsigned shift count * 0 (MIPS16OP_*_RZ) (full 6 bit unsigned)
992 "]" 3 bit unsigned shift count * 0 (MIPS16OP_*_RX) (full 6 bit unsigned)
993 "4" 4 bit signed immediate * 0 (MIPS16OP_*_IMM4) (full 15 bit signed)
994 "5" 5 bit unsigned immediate * 0 (MIPS16OP_*_IMM5)
995 "H" 5 bit unsigned immediate * 2 (MIPS16OP_*_IMM5)
996 "W" 5 bit unsigned immediate * 4 (MIPS16OP_*_IMM5)
997 "D" 5 bit unsigned immediate * 8 (MIPS16OP_*_IMM5)
998 "j" 5 bit signed immediate * 0 (MIPS16OP_*_IMM5)
999 "8" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8)
1000 "V" 8 bit unsigned immediate * 4 (MIPS16OP_*_IMM8)
1001 "C" 8 bit unsigned immediate * 8 (MIPS16OP_*_IMM8)
1002 "U" 8 bit unsigned immediate * 0 (MIPS16OP_*_IMM8) (full 16 bit unsigned)
1003 "k" 8 bit signed immediate * 0 (MIPS16OP_*_IMM8)
1004 "K" 8 bit signed immediate * 8 (MIPS16OP_*_IMM8)
1005 "p" 8 bit conditional branch address (MIPS16OP_*_IMM8)
1006 "q" 11 bit branch address (MIPS16OP_*_IMM11)
1007 "A" 8 bit PC relative address * 4 (MIPS16OP_*_IMM8)
1008 "B" 5 bit PC relative address * 8 (MIPS16OP_*_IMM5)
1009 "E" 5 bit PC relative address * 4 (MIPS16OP_*_IMM5)
1010 */
1011
1012 /* Save/restore encoding for the args field when all 4 registers are
1013 either saved as arguments or saved/restored as statics. */
1014 #define MIPS16_ALL_ARGS 0xe
1015 #define MIPS16_ALL_STATICS 0xb
1016
1017 /* For the mips16, we use the same opcode table format and a few of
1018 the same flags. However, most of the flags are different. */
1019
1020 /* Modifies the register in MIPS16OP_*_RX. */
1021 #define MIPS16_INSN_WRITE_X 0x00000001
1022 /* Modifies the register in MIPS16OP_*_RY. */
1023 #define MIPS16_INSN_WRITE_Y 0x00000002
1024 /* Modifies the register in MIPS16OP_*_RZ. */
1025 #define MIPS16_INSN_WRITE_Z 0x00000004
1026 /* Modifies the T ($24) register. */
1027 #define MIPS16_INSN_WRITE_T 0x00000008
1028 /* Modifies the SP ($29) register. */
1029 #define MIPS16_INSN_WRITE_SP 0x00000010
1030 /* Modifies the RA ($31) register. */
1031 #define MIPS16_INSN_WRITE_31 0x00000020
1032 /* Modifies the general purpose register in MIPS16OP_*_REG32R. */
1033 #define MIPS16_INSN_WRITE_GPR_Y 0x00000040
1034 /* Reads the register in MIPS16OP_*_RX. */
1035 #define MIPS16_INSN_READ_X 0x00000080
1036 /* Reads the register in MIPS16OP_*_RY. */
1037 #define MIPS16_INSN_READ_Y 0x00000100
1038 /* Reads the register in MIPS16OP_*_MOVE32Z. */
1039 #define MIPS16_INSN_READ_Z 0x00000200
1040 /* Reads the T ($24) register. */
1041 #define MIPS16_INSN_READ_T 0x00000400
1042 /* Reads the SP ($29) register. */
1043 #define MIPS16_INSN_READ_SP 0x00000800
1044 /* Reads the RA ($31) register. */
1045 #define MIPS16_INSN_READ_31 0x00001000
1046 /* Reads the program counter. */
1047 #define MIPS16_INSN_READ_PC 0x00002000
1048 /* Reads the general purpose register in MIPS16OP_*_REGR32. */
1049 #define MIPS16_INSN_READ_GPR_X 0x00004000
1050 /* Is a branch insn. */
1051 #define MIPS16_INSN_BRANCH 0x00010000
1052
1053 /* The following flags have the same value for the mips16 opcode
1054 table:
1055 INSN_UNCOND_BRANCH_DELAY
1056 INSN_COND_BRANCH_DELAY
1057 INSN_COND_BRANCH_LIKELY (never used)
1058 INSN_READ_HI
1059 INSN_READ_LO
1060 INSN_WRITE_HI
1061 INSN_WRITE_LO
1062 INSN_TRAP
1063 INSN_ISA3
1064 */
1065
1066 extern const struct mips_opcode mips16_opcodes[];
1067 extern const int bfd_mips16_num_opcodes;
1068
1069 /* Short hand so the lines aren't too long. */
1070
1071 #define LDD INSN_LOAD_MEMORY_DELAY
1072 #define LCD INSN_LOAD_COPROC_DELAY
1073 #define UBD INSN_UNCOND_BRANCH_DELAY
1074 #define CBD INSN_COND_BRANCH_DELAY
1075 #define COD INSN_COPROC_MOVE_DELAY
1076 #define CLD INSN_COPROC_MEMORY_DELAY
1077 #define CBL INSN_COND_BRANCH_LIKELY
1078 #define TRAP INSN_TRAP
1079 #define SM INSN_STORE_MEMORY
1080
1081 #define WR_d INSN_WRITE_GPR_D
1082 #define WR_t INSN_WRITE_GPR_T
1083 #define WR_31 INSN_WRITE_GPR_31
1084 #define WR_D INSN_WRITE_FPR_D
1085 #define WR_T INSN_WRITE_FPR_T
1086 #define WR_S INSN_WRITE_FPR_S
1087 #define RD_s INSN_READ_GPR_S
1088 #define RD_b INSN_READ_GPR_S
1089 #define RD_t INSN_READ_GPR_T
1090 #define RD_S INSN_READ_FPR_S
1091 #define RD_T INSN_READ_FPR_T
1092 #define RD_R INSN_READ_FPR_R
1093 #define WR_CC INSN_WRITE_COND_CODE
1094 #define RD_CC INSN_READ_COND_CODE
1095 #define RD_C0 INSN_COP
1096 #define RD_C1 INSN_COP
1097 #define RD_C2 INSN_COP
1098 #define RD_C3 INSN_COP
1099 #define WR_C0 INSN_COP
1100 #define WR_C1 INSN_COP
1101 #define WR_C2 INSN_COP
1102 #define WR_C3 INSN_COP
1103
1104 #define WR_HI INSN_WRITE_HI
1105 #define RD_HI INSN_READ_HI
1106 #define MOD_HI WR_HI|RD_HI
1107
1108 #define WR_LO INSN_WRITE_LO
1109 #define RD_LO INSN_READ_LO
1110 #define MOD_LO WR_LO|RD_LO
1111
1112 #define WR_HILO WR_HI|WR_LO
1113 #define RD_HILO RD_HI|RD_LO
1114 #define MOD_HILO WR_HILO|RD_HILO
1115
1116 #define IS_M INSN_MULT
1117
1118 #define WR_MACC INSN2_WRITE_MDMX_ACC
1119 #define RD_MACC INSN2_READ_MDMX_ACC
1120
1121 #define I1 INSN_ISA1
1122 #define I2 INSN_ISA2
1123 #define I3 INSN_ISA3
1124 #define I4 INSN_ISA4
1125 #define I5 INSN_ISA5
1126 #define I32 INSN_ISA32
1127 #define I64 INSN_ISA64
1128 #define I33 INSN_ISA32R2
1129 #define I65 INSN_ISA64R2
1130 #define I32R6 INSN_ISA32R6
1131 #define I64R6 INSN_ISA64R6
1132
1133 /* MIPS64 MIPS-3D ASE support. */
1134 #define I16 INSN_MIPS16
1135
1136 /* MIPS32 SmartMIPS ASE support. */
1137 #define SMT INSN_SMARTMIPS
1138
1139 /* MIPS64 MIPS-3D ASE support. */
1140 #define M3D INSN_MIPS3D
1141
1142 /* MIPS64 MDMX ASE support. */
1143 #define MX INSN_MDMX
1144
1145 #define IL2E (INSN_LOONGSON_2E)
1146 #define IL2F (INSN_LOONGSON_2F)
1147
1148 #define P3 INSN_4650
1149 #define L1 INSN_4010
1150 #define V1 (INSN_4100 | INSN_4111 | INSN_4120)
1151 #define T3 INSN_3900
1152 #define M1 INSN_10000
1153 #define SB1 INSN_SB1
1154 #define N411 INSN_4111
1155 #define N412 INSN_4120
1156 #define N5 (INSN_5400 | INSN_5500)
1157 #define N54 INSN_5400
1158 #define N55 INSN_5500
1159
1160 #define G1 (T3 \
1161 )
1162
1163 #define G2 (T3 \
1164 )
1165
1166 #define G3 (I4 \
1167 )
1168
1169 /* MIPS DSP ASE support.
1170 NOTE:
1171 1. MIPS DSP ASE includes 4 accumulators ($ac0 - $ac3). $ac0 is the pair
1172 of original HI and LO. $ac1, $ac2 and $ac3 are new registers, and have
1173 the same structure as $ac0 (HI + LO). For DSP instructions that write or
1174 read accumulators (that may be $ac0), we add WR_a (WR_HILO) or RD_a
1175 (RD_HILO) attributes, such that HILO dependencies are maintained
1176 conservatively.
1177
1178 2. For some mul. instructions that use integer registers as destinations
1179 but destroy HI+LO as side-effect, we add WR_HILO to their attributes.
1180
1181 3. MIPS DSP ASE includes a new DSP control register, which has 6 fields
1182 (ccond, outflag, EFI, c, scount, pos). Many DSP instructions read or write
1183 certain fields of the DSP control register. For simplicity, we decide not
1184 to track dependencies of these fields.
1185 However, "bposge32" is a branch instruction that depends on the "pos"
1186 field. In order to make sure that GAS does not reorder DSP instructions
1187 that writes the "pos" field and "bposge32", we add DSP_VOLA (INSN_TRAP)
1188 attribute to those instructions that write the "pos" field. */
1189
1190 #define WR_a WR_HILO /* Write dsp accumulators (reuse WR_HILO) */
1191 #define RD_a RD_HILO /* Read dsp accumulators (reuse RD_HILO) */
1192 #define MOD_a WR_a|RD_a
1193 #define DSP_VOLA INSN_TRAP
1194 #define D32 INSN_DSP
1195 #define D33 INSN_DSPR2
1196 #define D64 INSN_DSP64
1197
1198 /* MIPS MT ASE support. */
1199 #define MT32 INSN_MT
1200
1201 /* The order of overloaded instructions matters. Label arguments and
1202 register arguments look the same. Instructions that can have either
1203 for arguments must apear in the correct order in this table for the
1204 assembler to pick the right one. In other words, entries with
1205 immediate operands must apear after the same instruction with
1206 registers.
1207
1208 Because of the lookup algorithm used, entries with the same opcode
1209 name must be contiguous.
1210
1211 Many instructions are short hand for other instructions (i.e., The
1212 jal <register> instruction is short for jalr <register>). */
1213
1214 const struct mips_opcode mips_builtin_opcodes[] =
1215 {
1216 /* These instructions appear first so that the disassembler will find
1217 them first. The assemblers uses a hash table based on the
1218 instruction name anyhow. */
1219 /* name, args, match, mask, pinfo, membership */
1220 {"mul", "d,s,t", 0x00000098, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1221 {"muh", "d,s,t", 0x000000d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1222 {"mulu", "d,s,t", 0x00000099, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1223 {"muhu", "d,s,t", 0x000000d9, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1224 {"div", "d,s,t", 0x0000009a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1225 {"mod", "d,s,t", 0x000000da, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1226 {"divu", "d,s,t", 0x0000009b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1227 {"modu", "d,s,t", 0x000000db, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1228 {"dmul", "d,s,t", 0x0000009c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
1229 {"dmuh", "d,s,t", 0x000000dc, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
1230 {"dmulu", "d,s,t", 0x0000009d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
1231 {"dmuhu", "d,s,t", 0x000000dd, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
1232 {"ddiv", "d,s,t", 0x0000009e, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
1233 {"dmod", "d,s,t", 0x000000de, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
1234 {"ddivu", "d,s,t", 0x0000009f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
1235 {"dmodu", "d,s,t", 0x000000df, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I64R6},
1236 {"ll", "t,o(b)", 0x7c000036, 0xfc00007f, LDD|RD_b|WR_t, 0, I32R6},
1237 {"sc", "t,o(b)", 0x7c000026, 0xfc00007f, LDD|RD_b|WR_t, 0, I32R6},
1238 {"lld", "t,o(b)", 0x7c000037, 0xfc00007f, LDD|RD_b|WR_t, 0, I64R6},
1239 {"scd", "t,o(b)", 0x7c000027, 0xfc00007f, LDD|RD_b|WR_t, 0, I64R6},
1240 {"pref", "h,o(b)", 0x7c000035, 0xfc00007f, RD_b, 0, I32R6},
1241 {"cache", "k,o(b)", 0x7c000025, 0xfc00007f, RD_b, 0, I32R6},
1242 {"seleqz", "d,v,t", 0x00000035, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1243 {"selnez", "d,v,t", 0x00000037, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I32R6},
1244 {"pref", "k,o(b)", 0xcc000000, 0xfc000000, RD_b, 0, I4|I32|G3 },
1245 {"prefx", "h,t(b)", 0x4c00000f, 0xfc0007ff, RD_b|RD_t, 0, I4|I33 },
1246 {"nop", "", 0x00000000, 0xffffffff, 0, INSN2_ALIAS, I1 }, /* sll */
1247 {"ssnop", "", 0x00000040, 0xffffffff, 0, INSN2_ALIAS, I32|N55 }, /* sll */
1248 {"ehb", "", 0x000000c0, 0xffffffff, 0, INSN2_ALIAS, I33 }, /* sll */
1249 {"li", "t,j", 0x24000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* addiu */
1250 {"li", "t,i", 0x34000000, 0xffe00000, WR_t, INSN2_ALIAS, I1 }, /* ori */
1251 {"li", "t,I", 0, (int) M_LI, INSN_MACRO, 0, I1 },
1252 {"move", "d,s", 0, (int) M_MOVE, INSN_MACRO, 0, I1 },
1253 {"move", "d,s", 0x0000002d, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I3 },/* daddu */
1254 {"move", "d,s", 0x00000021, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* addu */
1255 {"move", "d,s", 0x00000025, 0xfc1f07ff, WR_d|RD_s, INSN2_ALIAS, I1 },/* or */
1256 {"b", "p", 0x10000000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* beq 0,0 */
1257 {"b", "p", 0x04010000, 0xffff0000, UBD, INSN2_ALIAS, I1 },/* bgez 0 */
1258 {"bal", "p", 0x04110000, 0xffff0000, UBD|WR_31, INSN2_ALIAS, I1 },/* bgezal 0*/
1259
1260 {"abs", "d,v", 0, (int) M_ABS, INSN_MACRO, 0, I1 },
1261 {"abs.s", "D,V", 0x46000005, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
1262 {"abs.d", "D,V", 0x46200005, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 },
1263 {"abs.ps", "D,V", 0x46c00005, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 },
1264 {"add", "d,v,t", 0x00000020, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
1265 {"add", "t,r,I", 0, (int) M_ADD_I, INSN_MACRO, 0, I1 },
1266 {"add.s", "D,V,T", 0x46000000, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
1267 {"add.d", "D,V,T", 0x46200000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
1268 {"add.ob", "X,Y,Q", 0x7800000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
1269 {"add.ob", "D,S,T", 0x4ac0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1270 {"add.ob", "D,S,T[e]", 0x4800000b, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
1271 {"add.ob", "D,S,k", 0x4bc0000b, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1272 {"add.ps", "D,V,T", 0x46c00000, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
1273 {"add.qh", "X,Y,Q", 0x7820000b, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
1274 {"adda.ob", "Y,Q", 0x78000037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
1275 {"adda.qh", "Y,Q", 0x78200037, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
1276 {"addi", "t,r,j", 0x20000000, 0xfc000000, WR_t|RD_s, 0, I1 },
1277 {"addiu", "t,r,j", 0x24000000, 0xfc000000, WR_t|RD_s, 0, I1 },
1278 {"addl.ob", "Y,Q", 0x78000437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
1279 {"addl.qh", "Y,Q", 0x78200437, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
1280 {"addr.ps", "D,S,T", 0x46c00018, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D },
1281 {"addu", "d,v,t", 0x00000021, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
1282 {"addu", "t,r,I", 0, (int) M_ADDU_I, INSN_MACRO, 0, I1 },
1283 {"alni.ob", "X,Y,Z,O", 0x78000018, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
1284 {"alni.ob", "D,S,T,%", 0x48000018, 0xff00003f, WR_D|RD_S|RD_T, 0, N54 },
1285 {"alni.qh", "X,Y,Z,O", 0x7800001a, 0xff00003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
1286 {"alnv.ps", "D,V,T,s", 0x4c00001e, 0xfc00003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
1287 {"alnv.ob", "X,Y,Z,s", 0x78000019, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX|SB1 },
1288 {"alnv.qh", "X,Y,Z,s", 0x7800001b, 0xfc00003f, WR_D|RD_S|RD_T|RD_s|FP_D, 0, MX },
1289 {"and", "d,v,t", 0x00000024, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
1290 {"and", "t,r,I", 0, (int) M_AND_I, INSN_MACRO, 0, I1 },
1291 {"and.ob", "X,Y,Q", 0x7800000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
1292 {"and.ob", "D,S,T", 0x4ac0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1293 {"and.ob", "D,S,T[e]", 0x4800000c, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
1294 {"and.ob", "D,S,k", 0x4bc0000c, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1295 {"and.qh", "X,Y,Q", 0x7820000c, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
1296 {"andi", "t,r,i", 0x30000000, 0xfc000000, WR_t|RD_s, 0, I1 },
1297 /* b is at the top of the table. */
1298 /* bal is at the top of the table. */
1299 /* bc0[tf]l? are at the bottom of the table. */
1300 {"bc1any2f", "N,p", 0x45200000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
1301 {"bc1any2t", "N,p", 0x45210000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
1302 {"bc1any4f", "N,p", 0x45400000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
1303 {"bc1any4t", "N,p", 0x45410000, 0xffe30000, CBD|RD_CC|FP_S, 0, M3D },
1304 {"bc1f", "p", 0x45000000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 },
1305 {"bc1f", "N,p", 0x45000000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4|I32 },
1306 {"bc1fl", "p", 0x45020000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 },
1307 {"bc1fl", "N,p", 0x45020000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4|I32 },
1308 {"bc1t", "p", 0x45010000, 0xffff0000, CBD|RD_CC|FP_S, 0, I1 },
1309 {"bc1t", "N,p", 0x45010000, 0xffe30000, CBD|RD_CC|FP_S, 0, I4|I32 },
1310 {"bc1tl", "p", 0x45030000, 0xffff0000, CBL|RD_CC|FP_S, 0, I2|T3 },
1311 {"bc1tl", "N,p", 0x45030000, 0xffe30000, CBL|RD_CC|FP_S, 0, I4|I32 },
1312 /* bc2* are at the bottom of the table. */
1313 /* bc3* are at the bottom of the table. */
1314 {"beqz", "s,p", 0x10000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
1315 {"beqzl", "s,p", 0x50000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
1316 {"beq", "s,t,p", 0x10000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 },
1317 {"beq", "s,I,p", 0, (int) M_BEQ_I, INSN_MACRO, 0, I1 },
1318 {"beql", "s,t,p", 0x50000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 },
1319 {"beql", "s,I,p", 0, (int) M_BEQL_I, INSN_MACRO, 0, I2|T3 },
1320 {"bge", "s,t,p", 0, (int) M_BGE, INSN_MACRO, 0, I1 },
1321 {"bge", "s,I,p", 0, (int) M_BGE_I, INSN_MACRO, 0, I1 },
1322 {"bgel", "s,t,p", 0, (int) M_BGEL, INSN_MACRO, 0, I2|T3 },
1323 {"bgel", "s,I,p", 0, (int) M_BGEL_I, INSN_MACRO, 0, I2|T3 },
1324 {"bgeu", "s,t,p", 0, (int) M_BGEU, INSN_MACRO, 0, I1 },
1325 {"bgeu", "s,I,p", 0, (int) M_BGEU_I, INSN_MACRO, 0, I1 },
1326 {"bgeul", "s,t,p", 0, (int) M_BGEUL, INSN_MACRO, 0, I2|T3 },
1327 {"bgeul", "s,I,p", 0, (int) M_BGEUL_I, INSN_MACRO, 0, I2|T3 },
1328 {"bgez", "s,p", 0x04010000, 0xfc1f0000, CBD|RD_s, 0, I1 },
1329 {"bgezl", "s,p", 0x04030000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
1330 {"bgezal", "s,p", 0x04110000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 },
1331 {"bgezall", "s,p", 0x04130000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 },
1332 {"bgt", "s,t,p", 0, (int) M_BGT, INSN_MACRO, 0, I1 },
1333 {"bgt", "s,I,p", 0, (int) M_BGT_I, INSN_MACRO, 0, I1 },
1334 {"bgtl", "s,t,p", 0, (int) M_BGTL, INSN_MACRO, 0, I2|T3 },
1335 {"bgtl", "s,I,p", 0, (int) M_BGTL_I, INSN_MACRO, 0, I2|T3 },
1336 {"bgtu", "s,t,p", 0, (int) M_BGTU, INSN_MACRO, 0, I1 },
1337 {"bgtu", "s,I,p", 0, (int) M_BGTU_I, INSN_MACRO, 0, I1 },
1338 {"bgtul", "s,t,p", 0, (int) M_BGTUL, INSN_MACRO, 0, I2|T3 },
1339 {"bgtul", "s,I,p", 0, (int) M_BGTUL_I, INSN_MACRO, 0, I2|T3 },
1340 {"bgtz", "s,p", 0x1c000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
1341 {"bgtzl", "s,p", 0x5c000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
1342 {"ble", "s,t,p", 0, (int) M_BLE, INSN_MACRO, 0, I1 },
1343 {"ble", "s,I,p", 0, (int) M_BLE_I, INSN_MACRO, 0, I1 },
1344 {"blel", "s,t,p", 0, (int) M_BLEL, INSN_MACRO, 0, I2|T3 },
1345 {"blel", "s,I,p", 0, (int) M_BLEL_I, INSN_MACRO, 0, I2|T3 },
1346 {"bleu", "s,t,p", 0, (int) M_BLEU, INSN_MACRO, 0, I1 },
1347 {"bleu", "s,I,p", 0, (int) M_BLEU_I, INSN_MACRO, 0, I1 },
1348 {"bleul", "s,t,p", 0, (int) M_BLEUL, INSN_MACRO, 0, I2|T3 },
1349 {"bleul", "s,I,p", 0, (int) M_BLEUL_I, INSN_MACRO, 0, I2|T3 },
1350 {"blez", "s,p", 0x18000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
1351 {"blezl", "s,p", 0x58000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
1352 {"blt", "s,t,p", 0, (int) M_BLT, INSN_MACRO, 0, I1 },
1353 {"blt", "s,I,p", 0, (int) M_BLT_I, INSN_MACRO, 0, I1 },
1354 {"bltl", "s,t,p", 0, (int) M_BLTL, INSN_MACRO, 0, I2|T3 },
1355 {"bltl", "s,I,p", 0, (int) M_BLTL_I, INSN_MACRO, 0, I2|T3 },
1356 {"bltu", "s,t,p", 0, (int) M_BLTU, INSN_MACRO, 0, I1 },
1357 {"bltu", "s,I,p", 0, (int) M_BLTU_I, INSN_MACRO, 0, I1 },
1358 {"bltul", "s,t,p", 0, (int) M_BLTUL, INSN_MACRO, 0, I2|T3 },
1359 {"bltul", "s,I,p", 0, (int) M_BLTUL_I, INSN_MACRO, 0, I2|T3 },
1360 {"bltz", "s,p", 0x04000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
1361 {"bltzl", "s,p", 0x04020000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
1362 {"bltzal", "s,p", 0x04100000, 0xfc1f0000, CBD|RD_s|WR_31, 0, I1 },
1363 {"bltzall", "s,p", 0x04120000, 0xfc1f0000, CBL|RD_s|WR_31, 0, I2|T3 },
1364 {"bnez", "s,p", 0x14000000, 0xfc1f0000, CBD|RD_s, 0, I1 },
1365 {"bnezl", "s,p", 0x54000000, 0xfc1f0000, CBL|RD_s, 0, I2|T3 },
1366 {"bne", "s,t,p", 0x14000000, 0xfc000000, CBD|RD_s|RD_t, 0, I1 },
1367 {"bne", "s,I,p", 0, (int) M_BNE_I, INSN_MACRO, 0, I1 },
1368 {"bnel", "s,t,p", 0x54000000, 0xfc000000, CBL|RD_s|RD_t, 0, I2|T3 },
1369 {"bnel", "s,I,p", 0, (int) M_BNEL_I, INSN_MACRO, 0, I2|T3 },
1370 {"break", "", 0x0000000d, 0xffffffff, TRAP, 0, I1 },
1371 {"break", "c", 0x0000000d, 0xfc00ffff, TRAP, 0, I1 },
1372 {"break", "c,q", 0x0000000d, 0xfc00003f, TRAP, 0, I1 },
1373 {"c.f.d", "S,T", 0x46200030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1374 {"c.f.d", "M,S,T", 0x46200030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1375 {"c.f.s", "S,T", 0x46000030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1376 {"c.f.s", "M,S,T", 0x46000030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1377 {"c.f.ps", "S,T", 0x46c00030, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1378 {"c.f.ps", "M,S,T", 0x46c00030, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1379 {"c.un.d", "S,T", 0x46200031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1380 {"c.un.d", "M,S,T", 0x46200031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1381 {"c.un.s", "S,T", 0x46000031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1382 {"c.un.s", "M,S,T", 0x46000031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1383 {"c.un.ps", "S,T", 0x46c00031, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1384 {"c.un.ps", "M,S,T", 0x46c00031, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1385 {"c.eq.d", "S,T", 0x46200032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1386 {"c.eq.d", "M,S,T", 0x46200032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1387 {"c.eq.s", "S,T", 0x46000032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1388 {"c.eq.s", "M,S,T", 0x46000032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1389 {"c.eq.ob", "Y,Q", 0x78000001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 },
1390 {"c.eq.ob", "S,T", 0x4ac00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1391 {"c.eq.ob", "S,T[e]", 0x48000001, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
1392 {"c.eq.ob", "S,k", 0x4bc00001, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1393 {"c.eq.ps", "S,T", 0x46c00032, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1394 {"c.eq.ps", "M,S,T", 0x46c00032, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1395 {"c.eq.qh", "Y,Q", 0x78200001, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX },
1396 {"c.ueq.d", "S,T", 0x46200033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1397 {"c.ueq.d", "M,S,T", 0x46200033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1398 {"c.ueq.s", "S,T", 0x46000033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1399 {"c.ueq.s", "M,S,T", 0x46000033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1400 {"c.ueq.ps","S,T", 0x46c00033, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1401 {"c.ueq.ps","M,S,T", 0x46c00033, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1402 {"c.olt.d", "S,T", 0x46200034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1403 {"c.olt.d", "M,S,T", 0x46200034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1404 {"c.olt.s", "S,T", 0x46000034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1405 {"c.olt.s", "M,S,T", 0x46000034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1406 {"c.olt.ps","S,T", 0x46c00034, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1407 {"c.olt.ps","M,S,T", 0x46c00034, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1408 {"c.ult.d", "S,T", 0x46200035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1409 {"c.ult.d", "M,S,T", 0x46200035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1410 {"c.ult.s", "S,T", 0x46000035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1411 {"c.ult.s", "M,S,T", 0x46000035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1412 {"c.ult.ps","S,T", 0x46c00035, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1413 {"c.ult.ps","M,S,T", 0x46c00035, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1414 {"c.ole.d", "S,T", 0x46200036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1415 {"c.ole.d", "M,S,T", 0x46200036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1416 {"c.ole.s", "S,T", 0x46000036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1417 {"c.ole.s", "M,S,T", 0x46000036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1418 {"c.ole.ps","S,T", 0x46c00036, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1419 {"c.ole.ps","M,S,T", 0x46c00036, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1420 {"c.ule.d", "S,T", 0x46200037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1421 {"c.ule.d", "M,S,T", 0x46200037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1422 {"c.ule.s", "S,T", 0x46000037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1423 {"c.ule.s", "M,S,T", 0x46000037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1424 {"c.ule.ps","S,T", 0x46c00037, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1425 {"c.ule.ps","M,S,T", 0x46c00037, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1426 {"c.sf.d", "S,T", 0x46200038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1427 {"c.sf.d", "M,S,T", 0x46200038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1428 {"c.sf.s", "S,T", 0x46000038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1429 {"c.sf.s", "M,S,T", 0x46000038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1430 {"c.sf.ps", "S,T", 0x46c00038, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1431 {"c.sf.ps", "M,S,T", 0x46c00038, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1432 {"c.ngle.d","S,T", 0x46200039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1433 {"c.ngle.d","M,S,T", 0x46200039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1434 {"c.ngle.s","S,T", 0x46000039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1435 {"c.ngle.s","M,S,T", 0x46000039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1436 {"c.ngle.ps","S,T", 0x46c00039, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1437 {"c.ngle.ps","M,S,T", 0x46c00039, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1438 {"c.seq.d", "S,T", 0x4620003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1439 {"c.seq.d", "M,S,T", 0x4620003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1440 {"c.seq.s", "S,T", 0x4600003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1441 {"c.seq.s", "M,S,T", 0x4600003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1442 {"c.seq.ps","S,T", 0x46c0003a, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1443 {"c.seq.ps","M,S,T", 0x46c0003a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1444 {"c.ngl.d", "S,T", 0x4620003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1445 {"c.ngl.d", "M,S,T", 0x4620003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1446 {"c.ngl.s", "S,T", 0x4600003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1447 {"c.ngl.s", "M,S,T", 0x4600003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1448 {"c.ngl.ps","S,T", 0x46c0003b, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1449 {"c.ngl.ps","M,S,T", 0x46c0003b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1450 {"c.lt.d", "S,T", 0x4620003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1451 {"c.lt.d", "M,S,T", 0x4620003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1452 {"c.lt.s", "S,T", 0x4600003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1453 {"c.lt.s", "M,S,T", 0x4600003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1454 {"c.lt.ob", "Y,Q", 0x78000004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 },
1455 {"c.lt.ob", "S,T", 0x4ac00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1456 {"c.lt.ob", "S,T[e]", 0x48000004, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
1457 {"c.lt.ob", "S,k", 0x4bc00004, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1458 {"c.lt.ps", "S,T", 0x46c0003c, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1459 {"c.lt.ps", "M,S,T", 0x46c0003c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1460 {"c.lt.qh", "Y,Q", 0x78200004, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX },
1461 {"c.nge.d", "S,T", 0x4620003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1462 {"c.nge.d", "M,S,T", 0x4620003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1463 {"c.nge.s", "S,T", 0x4600003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1464 {"c.nge.s", "M,S,T", 0x4600003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1465 {"c.nge.ps","S,T", 0x46c0003d, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1466 {"c.nge.ps","M,S,T", 0x46c0003d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1467 {"c.le.d", "S,T", 0x4620003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1468 {"c.le.d", "M,S,T", 0x4620003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1469 {"c.le.s", "S,T", 0x4600003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1470 {"c.le.s", "M,S,T", 0x4600003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1471 {"c.le.ob", "Y,Q", 0x78000005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX|SB1 },
1472 {"c.le.ob", "S,T", 0x4ac00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1473 {"c.le.ob", "S,T[e]", 0x48000005, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
1474 {"c.le.ob", "S,k", 0x4bc00005, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1475 {"c.le.ps", "S,T", 0x46c0003e, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1476 {"c.le.ps", "M,S,T", 0x46c0003e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1477 {"c.le.qh", "Y,Q", 0x78200005, 0xfc2007ff, WR_CC|RD_S|RD_T|FP_D, 0, MX },
1478 {"c.ngt.d", "S,T", 0x4620003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I1 },
1479 {"c.ngt.d", "M,S,T", 0x4620003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I4|I32 },
1480 {"c.ngt.s", "S,T", 0x4600003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_S, 0, I1 },
1481 {"c.ngt.s", "M,S,T", 0x4600003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, I4|I32 },
1482 {"c.ngt.ps","S,T", 0x46c0003f, 0xffe007ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1483 {"c.ngt.ps","M,S,T", 0x46c0003f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, I5|I33 },
1484 {"cabs.eq.d", "M,S,T", 0x46200072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1485 {"cabs.eq.ps", "M,S,T", 0x46c00072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1486 {"cabs.eq.s", "M,S,T", 0x46000072, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1487 {"cabs.f.d", "M,S,T", 0x46200070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1488 {"cabs.f.ps", "M,S,T", 0x46c00070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1489 {"cabs.f.s", "M,S,T", 0x46000070, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1490 {"cabs.le.d", "M,S,T", 0x4620007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1491 {"cabs.le.ps", "M,S,T", 0x46c0007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1492 {"cabs.le.s", "M,S,T", 0x4600007e, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1493 {"cabs.lt.d", "M,S,T", 0x4620007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1494 {"cabs.lt.ps", "M,S,T", 0x46c0007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1495 {"cabs.lt.s", "M,S,T", 0x4600007c, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1496 {"cabs.nge.d", "M,S,T", 0x4620007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1497 {"cabs.nge.ps","M,S,T", 0x46c0007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1498 {"cabs.nge.s", "M,S,T", 0x4600007d, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1499 {"cabs.ngl.d", "M,S,T", 0x4620007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1500 {"cabs.ngl.ps","M,S,T", 0x46c0007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1501 {"cabs.ngl.s", "M,S,T", 0x4600007b, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1502 {"cabs.ngle.d","M,S,T", 0x46200079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1503 {"cabs.ngle.ps","M,S,T",0x46c00079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1504 {"cabs.ngle.s","M,S,T", 0x46000079, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1505 {"cabs.ngt.d", "M,S,T", 0x4620007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1506 {"cabs.ngt.ps","M,S,T", 0x46c0007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1507 {"cabs.ngt.s", "M,S,T", 0x4600007f, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1508 {"cabs.ole.d", "M,S,T", 0x46200076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1509 {"cabs.ole.ps","M,S,T", 0x46c00076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1510 {"cabs.ole.s", "M,S,T", 0x46000076, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1511 {"cabs.olt.d", "M,S,T", 0x46200074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1512 {"cabs.olt.ps","M,S,T", 0x46c00074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1513 {"cabs.olt.s", "M,S,T", 0x46000074, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1514 {"cabs.seq.d", "M,S,T", 0x4620007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1515 {"cabs.seq.ps","M,S,T", 0x46c0007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1516 {"cabs.seq.s", "M,S,T", 0x4600007a, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1517 {"cabs.sf.d", "M,S,T", 0x46200078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1518 {"cabs.sf.ps", "M,S,T", 0x46c00078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1519 {"cabs.sf.s", "M,S,T", 0x46000078, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1520 {"cabs.ueq.d", "M,S,T", 0x46200073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1521 {"cabs.ueq.ps","M,S,T", 0x46c00073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1522 {"cabs.ueq.s", "M,S,T", 0x46000073, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1523 {"cabs.ule.d", "M,S,T", 0x46200077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1524 {"cabs.ule.ps","M,S,T", 0x46c00077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1525 {"cabs.ule.s", "M,S,T", 0x46000077, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1526 {"cabs.ult.d", "M,S,T", 0x46200075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1527 {"cabs.ult.ps","M,S,T", 0x46c00075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1528 {"cabs.ult.s", "M,S,T", 0x46000075, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1529 {"cabs.un.d", "M,S,T", 0x46200071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1530 {"cabs.un.ps", "M,S,T", 0x46c00071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_D, 0, M3D },
1531 {"cabs.un.s", "M,S,T", 0x46000071, 0xffe000ff, RD_S|RD_T|WR_CC|FP_S, 0, M3D },
1532 /* CW4010 instructions which are aliases for the cache instruction. */
1533 {"flushi", "", 0xbc010000, 0xffffffff, 0, 0, L1 },
1534 {"flushd", "", 0xbc020000, 0xffffffff, 0, 0, L1 },
1535 {"flushid", "", 0xbc030000, 0xffffffff, 0, 0, L1 },
1536 {"wb", "o(b)", 0xbc040000, 0xfc1f0000, SM|RD_b, 0, L1 },
1537 {"cache", "k,o(b)", 0xbc000000, 0xfc000000, RD_b, 0, I3|I32|T3},
1538 {"cache", "k,A(b)", 0, (int) M_CACHE_AB, INSN_MACRO, 0, I3|I32|T3},
1539 {"ceil.l.d", "D,S", 0x4620000a, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
1540 {"ceil.l.s", "D,S", 0x4600000a, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
1541 {"ceil.w.d", "D,S", 0x4620000e, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
1542 {"ceil.w.s", "D,S", 0x4600000e, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
1543 {"cfc0", "t,G", 0x40400000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 },
1544 {"cfc1", "t,G", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 },
1545 {"cfc1", "t,S", 0x44400000, 0xffe007ff, LCD|WR_t|RD_C1|FP_S, 0, I1 },
1546 /* cfc2 is at the bottom of the table. */
1547 /* cfc3 is at the bottom of the table. */
1548 {"cftc1", "d,E", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
1549 {"cftc1", "d,T", 0x41000023, 0xffe007ff, TRAP|LCD|WR_d|RD_C1|FP_S, 0, MT32 },
1550 {"cftc2", "d,E", 0x41000025, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
1551 {"clo", "U,s", 0x70000021, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
1552 {"clz", "U,s", 0x70000020, 0xfc0007ff, WR_d|WR_t|RD_s, 0, I32|N55 },
1553 {"ctc0", "t,G", 0x40c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
1554 {"ctc1", "t,G", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
1555 {"ctc1", "t,S", 0x44c00000, 0xffe007ff, COD|RD_t|WR_CC|FP_S, 0, I1 },
1556 /* ctc2 is at the bottom of the table. */
1557 /* ctc3 is at the bottom of the table. */
1558 {"cttc1", "t,g", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
1559 {"cttc1", "t,S", 0x41800023, 0xffe007ff, TRAP|COD|RD_t|WR_CC|FP_S, 0, MT32 },
1560 {"cttc2", "t,g", 0x41800025, 0xffe007ff, TRAP|COD|RD_t|WR_CC, 0, MT32 },
1561 {"cvt.d.l", "D,S", 0x46a00021, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
1562 {"cvt.d.s", "D,S", 0x46000021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
1563 {"cvt.d.w", "D,S", 0x46800021, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
1564 {"cvt.l.d", "D,S", 0x46200025, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
1565 {"cvt.l.s", "D,S", 0x46000025, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
1566 {"cvt.s.l", "D,S", 0x46a00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
1567 {"cvt.s.d", "D,S", 0x46200020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
1568 {"cvt.s.w", "D,S", 0x46800020, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
1569 {"cvt.s.pl","D,S", 0x46c00028, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5|I33 },
1570 {"cvt.s.pu","D,S", 0x46c00020, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I5|I33 },
1571 {"cvt.w.d", "D,S", 0x46200024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I1 },
1572 {"cvt.w.s", "D,S", 0x46000024, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
1573 {"cvt.ps.pw", "D,S", 0x46800026, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D },
1574 {"cvt.ps.s","D,V,T", 0x46000026, 0xffe0003f, WR_D|RD_S|RD_T|FP_S|FP_D, 0, I5|I33 },
1575 {"cvt.pw.ps", "D,S", 0x46c00024, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, M3D },
1576 {"dabs", "d,v", 0, (int) M_DABS, INSN_MACRO, 0, I3 },
1577 {"dadd", "d,v,t", 0x0000002c, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
1578 {"dadd", "t,r,I", 0, (int) M_DADD_I, INSN_MACRO, 0, I3 },
1579 {"daddi", "t,r,j", 0x60000000, 0xfc000000, WR_t|RD_s, 0, I3 },
1580 {"daddiu", "t,r,j", 0x64000000, 0xfc000000, WR_t|RD_s, 0, I3 },
1581 {"daddu", "d,v,t", 0x0000002d, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
1582 {"daddu", "t,r,I", 0, (int) M_DADDU_I, INSN_MACRO, 0, I3 },
1583 {"dbreak", "", 0x7000003f, 0xffffffff, 0, 0, N5 },
1584 {"dclo", "U,s", 0x70000025, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
1585 {"dclz", "U,s", 0x70000024, 0xfc0007ff, RD_s|WR_d|WR_t, 0, I64|N55 },
1586 /* dctr and dctw are used on the r5000. */
1587 {"dctr", "o(b)", 0xbc050000, 0xfc1f0000, RD_b, 0, I3 },
1588 {"dctw", "o(b)", 0xbc090000, 0xfc1f0000, RD_b, 0, I3 },
1589 {"deret", "", 0x4200001f, 0xffffffff, 0, 0, I32|G2 },
1590 {"dext", "t,r,I,+I", 0, (int) M_DEXT, INSN_MACRO, 0, I65 },
1591 {"dext", "t,r,+A,+C", 0x7c000003, 0xfc00003f, WR_t|RD_s, 0, I65 },
1592 {"dextm", "t,r,+A,+G", 0x7c000001, 0xfc00003f, WR_t|RD_s, 0, I65 },
1593 {"dextu", "t,r,+E,+H", 0x7c000002, 0xfc00003f, WR_t|RD_s, 0, I65 },
1594 /* For ddiv, see the comments about div. */
1595 {"ddiv", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
1596 {"ddiv", "d,v,t", 0, (int) M_DDIV_3, INSN_MACRO, 0, I3 },
1597 {"ddiv", "d,v,I", 0, (int) M_DDIV_3I, INSN_MACRO, 0, I3 },
1598 /* For ddivu, see the comments about div. */
1599 {"ddivu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
1600 {"ddivu", "d,v,t", 0, (int) M_DDIVU_3, INSN_MACRO, 0, I3 },
1601 {"ddivu", "d,v,I", 0, (int) M_DDIVU_3I, INSN_MACRO, 0, I3 },
1602 {"di", "", 0x41606000, 0xffffffff, WR_t|WR_C0, 0, I33 },
1603 {"di", "t", 0x41606000, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
1604 {"dins", "t,r,I,+I", 0, (int) M_DINS, INSN_MACRO, 0, I65 },
1605 {"dins", "t,r,+A,+B", 0x7c000007, 0xfc00003f, WR_t|RD_s, 0, I65 },
1606 {"dinsm", "t,r,+A,+F", 0x7c000005, 0xfc00003f, WR_t|RD_s, 0, I65 },
1607 {"dinsu", "t,r,+E,+F", 0x7c000006, 0xfc00003f, WR_t|RD_s, 0, I65 },
1608 /* The MIPS assembler treats the div opcode with two operands as
1609 though the first operand appeared twice (the first operand is both
1610 a source and a destination). To get the div machine instruction,
1611 you must use an explicit destination of $0. */
1612 {"div", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
1613 {"div", "z,t", 0x0000001a, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 },
1614 {"div", "d,v,t", 0, (int) M_DIV_3, INSN_MACRO, 0, I1 },
1615 {"div", "d,v,I", 0, (int) M_DIV_3I, INSN_MACRO, 0, I1 },
1616 {"div.d", "D,V,T", 0x46200003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
1617 {"div.s", "D,V,T", 0x46000003, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
1618 {"div.ps", "D,V,T", 0x46c00003, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 },
1619 /* For divu, see the comments about div. */
1620 {"divu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
1621 {"divu", "z,t", 0x0000001b, 0xffe0ffff, RD_s|RD_t|WR_HILO, 0, I1 },
1622 {"divu", "d,v,t", 0, (int) M_DIVU_3, INSN_MACRO, 0, I1 },
1623 {"divu", "d,v,I", 0, (int) M_DIVU_3I, INSN_MACRO, 0, I1 },
1624 {"dla", "t,A(b)", 0, (int) M_DLA_AB, INSN_MACRO, 0, I3 },
1625 {"dlca", "t,A(b)", 0, (int) M_DLCA_AB, INSN_MACRO, 0, I3 },
1626 {"dli", "t,j", 0x24000000, 0xffe00000, WR_t, 0, I3 }, /* addiu */
1627 {"dli", "t,i", 0x34000000, 0xffe00000, WR_t, 0, I3 }, /* ori */
1628 {"dli", "t,I", 0, (int) M_DLI, INSN_MACRO, 0, I3 },
1629 {"dmacc", "d,s,t", 0x00000029, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1630 {"dmacchi", "d,s,t", 0x00000229, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1631 {"dmacchis", "d,s,t", 0x00000629, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1632 {"dmacchiu", "d,s,t", 0x00000269, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1633 {"dmacchius", "d,s,t", 0x00000669, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1634 {"dmaccs", "d,s,t", 0x00000429, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1635 {"dmaccu", "d,s,t", 0x00000069, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1636 {"dmaccus", "d,s,t", 0x00000469, 0xfc0007ff, RD_s|RD_t|WR_LO|WR_d, 0, N412 },
1637 {"dmadd16", "s,t", 0x00000029, 0xfc00ffff, RD_s|RD_t|MOD_LO, 0, N411 },
1638 {"dmfc0", "t,G", 0x40200000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I3 },
1639 {"dmfc0", "t,+D", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
1640 {"dmfc0", "t,G,H", 0x40200000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I64 },
1641 {"dmt", "", 0x41600bc1, 0xffffffff, TRAP, 0, MT32 },
1642 {"dmt", "t", 0x41600bc1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
1643 {"dmtc0", "t,G", 0x40a00000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I3 },
1644 {"dmtc0", "t,+D", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
1645 {"dmtc0", "t,G,H", 0x40a00000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I64 },
1646 {"dmfc1", "t,S", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 },
1647 {"dmfc1", "t,G", 0x44200000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I3 },
1648 {"dmtc1", "t,S", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 },
1649 {"dmtc1", "t,G", 0x44a00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I3 },
1650 /* dmfc2 is at the bottom of the table. */
1651 /* dmtc2 is at the bottom of the table. */
1652 /* dmfc3 is at the bottom of the table. */
1653 /* dmtc3 is at the bottom of the table. */
1654 {"dmul", "d,v,t", 0, (int) M_DMUL, INSN_MACRO, 0, I3 },
1655 {"dmul", "d,v,I", 0, (int) M_DMUL_I, INSN_MACRO, 0, I3 },
1656 {"dmulo", "d,v,t", 0, (int) M_DMULO, INSN_MACRO, 0, I3 },
1657 {"dmulo", "d,v,I", 0, (int) M_DMULO_I, INSN_MACRO, 0, I3 },
1658 {"dmulou", "d,v,t", 0, (int) M_DMULOU, INSN_MACRO, 0, I3 },
1659 {"dmulou", "d,v,I", 0, (int) M_DMULOU_I, INSN_MACRO, 0, I3 },
1660 {"dmult", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
1661 {"dmultu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
1662 {"dneg", "d,w", 0x0000002e, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsub 0 */
1663 {"dnegu", "d,w", 0x0000002f, 0xffe007ff, WR_d|RD_t, 0, I3 }, /* dsubu 0*/
1664 {"drem", "z,s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
1665 {"drem", "d,v,t", 3, (int) M_DREM_3, INSN_MACRO, 0, I3 },
1666 {"drem", "d,v,I", 3, (int) M_DREM_3I, INSN_MACRO, 0, I3 },
1667 {"dremu", "z,s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I3 },
1668 {"dremu", "d,v,t", 3, (int) M_DREMU_3, INSN_MACRO, 0, I3 },
1669 {"dremu", "d,v,I", 3, (int) M_DREMU_3I, INSN_MACRO, 0, I3 },
1670 {"dret", "", 0x7000003e, 0xffffffff, 0, 0, N5 },
1671 {"drol", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I3 },
1672 {"drol", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I3 },
1673 {"dror", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I3 },
1674 {"dror", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I3 },
1675 {"dror", "d,w,<", 0x0020003a, 0xffe0003f, WR_d|RD_t, 0, N5|I65 },
1676 {"drorv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I65 },
1677 {"dror32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, N5|I65 },
1678 {"drotl", "d,v,t", 0, (int) M_DROL, INSN_MACRO, 0, I65 },
1679 {"drotl", "d,v,I", 0, (int) M_DROL_I, INSN_MACRO, 0, I65 },
1680 {"drotr", "d,v,t", 0, (int) M_DROR, INSN_MACRO, 0, I65 },
1681 {"drotr", "d,v,I", 0, (int) M_DROR_I, INSN_MACRO, 0, I65 },
1682 {"drotrv", "d,t,s", 0x00000056, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I65 },
1683 {"drotr32", "d,w,<", 0x0020003e, 0xffe0003f, WR_d|RD_t, 0, I65 },
1684 {"dsbh", "d,w", 0x7c0000a4, 0xffe007ff, WR_d|RD_t, 0, I65 },
1685 {"dshd", "d,w", 0x7c000164, 0xffe007ff, WR_d|RD_t, 0, I65 },
1686 {"dsllv", "d,t,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
1687 {"dsll32", "d,w,<", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 },
1688 {"dsll", "d,w,s", 0x00000014, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsllv */
1689 {"dsll", "d,w,>", 0x0000003c, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsll32 */
1690 {"dsll", "d,w,<", 0x00000038, 0xffe0003f, WR_d|RD_t, 0, I3 },
1691 {"dsrav", "d,t,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
1692 {"dsra32", "d,w,<", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 },
1693 {"dsra", "d,w,s", 0x00000017, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrav */
1694 {"dsra", "d,w,>", 0x0000003f, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsra32 */
1695 {"dsra", "d,w,<", 0x0000003b, 0xffe0003f, WR_d|RD_t, 0, I3 },
1696 {"dsrlv", "d,t,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 },
1697 {"dsrl32", "d,w,<", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 },
1698 {"dsrl", "d,w,s", 0x00000016, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I3 }, /* dsrlv */
1699 {"dsrl", "d,w,>", 0x0000003e, 0xffe0003f, WR_d|RD_t, 0, I3 }, /* dsrl32 */
1700 {"dsrl", "d,w,<", 0x0000003a, 0xffe0003f, WR_d|RD_t, 0, I3 },
1701 {"dsub", "d,v,t", 0x0000002e, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
1702 {"dsub", "d,v,I", 0, (int) M_DSUB_I, INSN_MACRO, 0, I3 },
1703 {"dsubu", "d,v,t", 0x0000002f, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I3 },
1704 {"dsubu", "d,v,I", 0, (int) M_DSUBU_I, INSN_MACRO, 0, I3 },
1705 {"dvpe", "", 0x41600001, 0xffffffff, TRAP, 0, MT32 },
1706 {"dvpe", "t", 0x41600001, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
1707 {"ei", "", 0x41606020, 0xffffffff, WR_t|WR_C0, 0, I33 },
1708 {"ei", "t", 0x41606020, 0xffe0ffff, WR_t|WR_C0, 0, I33 },
1709 {"emt", "", 0x41600be1, 0xffffffff, TRAP, 0, MT32 },
1710 {"emt", "t", 0x41600be1, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
1711 {"eret", "", 0x42000018, 0xffffffff, 0, 0, I3|I32 },
1712 {"evpe", "", 0x41600021, 0xffffffff, TRAP, 0, MT32 },
1713 {"evpe", "t", 0x41600021, 0xffe0ffff, TRAP|WR_t, 0, MT32 },
1714 {"ext", "t,r,+A,+C", 0x7c000000, 0xfc00003f, WR_t|RD_s, 0, I33 },
1715 {"floor.l.d", "D,S", 0x4620000b, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
1716 {"floor.l.s", "D,S", 0x4600000b, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
1717 {"floor.w.d", "D,S", 0x4620000f, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
1718 {"floor.w.s", "D,S", 0x4600000f, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
1719 {"hibernate","", 0x42000023, 0xffffffff, 0, 0, V1 },
1720 {"ins", "t,r,+A,+B", 0x7c000004, 0xfc00003f, WR_t|RD_s, 0, I33 },
1721 {"jr", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 },
1722 /* jr.hb is officially MIPS{32,64}R2, but it works on R1 as jr with
1723 the same hazard barrier effect. */
1724 {"jr.hb", "s", 0x00000408, 0xfc1fffff, UBD|RD_s, 0, I32 },
1725 {"j", "s", 0x00000008, 0xfc1fffff, UBD|RD_s, 0, I1 }, /* jr */
1726 /* SVR4 PIC code requires special handling for j, so it must be a
1727 macro. */
1728 {"j", "a", 0, (int) M_J_A, INSN_MACRO, 0, I1 },
1729 /* This form of j is used by the disassembler and internally by the
1730 assembler, but will never match user input (because the line above
1731 will match first). */
1732 {"j", "a", 0x08000000, 0xfc000000, UBD, 0, I1 },
1733 {"jalr", "s", 0x0000f809, 0xfc1fffff, UBD|RD_s|WR_d, 0, I1 },
1734 {"jalr", "d,s", 0x00000009, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I1 },
1735 /* jalr.hb is officially MIPS{32,64}R2, but it works on R1 as jalr
1736 with the same hazard barrier effect. */
1737 {"jalr.hb", "s", 0x0000fc09, 0xfc1fffff, UBD|RD_s|WR_d, 0, I32 },
1738 {"jalr.hb", "d,s", 0x00000409, 0xfc1f07ff, UBD|RD_s|WR_d, 0, I32 },
1739 /* SVR4 PIC code requires special handling for jal, so it must be a
1740 macro. */
1741 {"jal", "d,s", 0, (int) M_JAL_2, INSN_MACRO, 0, I1 },
1742 {"jal", "s", 0, (int) M_JAL_1, INSN_MACRO, 0, I1 },
1743 {"jal", "a", 0, (int) M_JAL_A, INSN_MACRO, 0, I1 },
1744 /* This form of jal is used by the disassembler and internally by the
1745 assembler, but will never match user input (because the line above
1746 will match first). */
1747 {"jal", "a", 0x0c000000, 0xfc000000, UBD|WR_31, 0, I1 },
1748 {"jalx", "a", 0x74000000, 0xfc000000, UBD|WR_31, 0, I16 },
1749 {"la", "t,A(b)", 0, (int) M_LA_AB, INSN_MACRO, 0, I1 },
1750 {"lb", "t,o(b)", 0x80000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1751 {"lb", "t,A(b)", 0, (int) M_LB_AB, INSN_MACRO, 0, I1 },
1752 {"lbu", "t,o(b)", 0x90000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1753 {"lbu", "t,A(b)", 0, (int) M_LBU_AB, INSN_MACRO, 0, I1 },
1754 {"lca", "t,A(b)", 0, (int) M_LCA_AB, INSN_MACRO, 0, I1 },
1755 {"ld", "t,o(b)", 0xdc000000, 0xfc000000, WR_t|RD_b, 0, I3 },
1756 {"ld", "t,o(b)", 0, (int) M_LD_OB, INSN_MACRO, 0, I1 },
1757 {"ld", "t,A(b)", 0, (int) M_LD_AB, INSN_MACRO, 0, I1 },
1758 {"ldc1", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
1759 {"ldc1", "E,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 },
1760 {"ldc1", "T,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 },
1761 {"ldc1", "E,A(b)", 0, (int) M_LDC1_AB, INSN_MACRO, 0, I2 },
1762 {"l.d", "T,o(b)", 0xd4000000, 0xfc000000, CLD|RD_b|WR_T|FP_D, 0, I2 }, /* ldc1 */
1763 {"l.d", "T,o(b)", 0, (int) M_L_DOB, INSN_MACRO, 0, I1 },
1764 {"l.d", "T,A(b)", 0, (int) M_L_DAB, INSN_MACRO, 0, I1 },
1765 {"ldc2", "E,o(b)", 0xd8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
1766 {"ldc2", "E,A(b)", 0, (int) M_LDC2_AB, INSN_MACRO, 0, I2 },
1767 {"ldc3", "E,o(b)", 0xdc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I2 },
1768 {"ldc3", "E,A(b)", 0, (int) M_LDC3_AB, INSN_MACRO, 0, I2 },
1769 {"ldl", "t,o(b)", 0x68000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 },
1770 {"ldl", "t,A(b)", 0, (int) M_LDL_AB, INSN_MACRO, 0, I3 },
1771 {"ldr", "t,o(b)", 0x6c000000, 0xfc000000, LDD|WR_t|RD_b, 0, I3 },
1772 {"ldr", "t,A(b)", 0, (int) M_LDR_AB, INSN_MACRO, 0, I3 },
1773 {"ldxc1", "D,t(b)", 0x4c000001, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4|I33 },
1774 {"lh", "t,o(b)", 0x84000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1775 {"lh", "t,A(b)", 0, (int) M_LH_AB, INSN_MACRO, 0, I1 },
1776 {"lhu", "t,o(b)", 0x94000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1777 {"lhu", "t,A(b)", 0, (int) M_LHU_AB, INSN_MACRO, 0, I1 },
1778 /* li is at the start of the table. */
1779 {"li.d", "t,F", 0, (int) M_LI_D, INSN_MACRO, 0, I1 },
1780 {"li.d", "T,L", 0, (int) M_LI_DD, INSN_MACRO, 0, I1 },
1781 {"li.s", "t,f", 0, (int) M_LI_S, INSN_MACRO, 0, I1 },
1782 {"li.s", "T,l", 0, (int) M_LI_SS, INSN_MACRO, 0, I1 },
1783 {"ll", "t,o(b)", 0xc0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 },
1784 {"ll", "t,A(b)", 0, (int) M_LL_AB, INSN_MACRO, 0, I2 },
1785 {"lld", "t,o(b)", 0xd0000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 },
1786 {"lld", "t,A(b)", 0, (int) M_LLD_AB, INSN_MACRO, 0, I3 },
1787 {"lui", "t,u", 0x3c000000, 0xffe00000, WR_t, 0, I1 },
1788 {"luxc1", "D,t(b)", 0x4c000005, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I5|I33|N55},
1789 {"lw", "t,o(b)", 0x8c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1790 {"lw", "t,A(b)", 0, (int) M_LW_AB, INSN_MACRO, 0, I1 },
1791 {"lwc0", "E,o(b)", 0xc0000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
1792 {"lwc0", "E,A(b)", 0, (int) M_LWC0_AB, INSN_MACRO, 0, I1 },
1793 {"lwc1", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 },
1794 {"lwc1", "E,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 },
1795 {"lwc1", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 },
1796 {"lwc1", "E,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 },
1797 {"l.s", "T,o(b)", 0xc4000000, 0xfc000000, CLD|RD_b|WR_T|FP_S, 0, I1 }, /* lwc1 */
1798 {"l.s", "T,A(b)", 0, (int) M_LWC1_AB, INSN_MACRO, 0, I1 },
1799 {"lwc2", "E,o(b)", 0xc8000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
1800 {"lwc2", "E,A(b)", 0, (int) M_LWC2_AB, INSN_MACRO, 0, I1 },
1801 {"lwc3", "E,o(b)", 0xcc000000, 0xfc000000, CLD|RD_b|WR_CC, 0, I1 },
1802 {"lwc3", "E,A(b)", 0, (int) M_LWC3_AB, INSN_MACRO, 0, I1 },
1803 {"lwl", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1804 {"lwl", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I1 },
1805 {"lcache", "t,o(b)", 0x88000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */
1806 {"lcache", "t,A(b)", 0, (int) M_LWL_AB, INSN_MACRO, 0, I2 }, /* as lwl */
1807 {"lwr", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I1 },
1808 {"lwr", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I1 },
1809 {"flush", "t,o(b)", 0x98000000, 0xfc000000, LDD|RD_b|WR_t, 0, I2 }, /* same */
1810 {"flush", "t,A(b)", 0, (int) M_LWR_AB, INSN_MACRO, 0, I2 }, /* as lwr */
1811 {"fork", "d,s,t", 0x7c000008, 0xfc0007ff, TRAP|WR_d|RD_s|RD_t, 0, MT32 },
1812 {"lwu", "t,o(b)", 0x9c000000, 0xfc000000, LDD|RD_b|WR_t, 0, I3 },
1813 {"lwu", "t,A(b)", 0, (int) M_LWU_AB, INSN_MACRO, 0, I3 },
1814 {"lwxc1", "D,t(b)", 0x4c000000, 0xfc00f83f, LDD|WR_D|RD_t|RD_b|FP_D, 0, I4|I33 },
1815 {"lwxs", "d,t(b)", 0x70000088, 0xfc0007ff, LDD|RD_b|RD_t|WR_d, 0, SMT },
1816 {"macc", "d,s,t", 0x00000028, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1817 {"macc", "d,s,t", 0x00000158, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1818 {"maccs", "d,s,t", 0x00000428, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1819 {"macchi", "d,s,t", 0x00000228, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1820 {"macchi", "d,s,t", 0x00000358, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1821 {"macchis", "d,s,t", 0x00000628, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1822 {"macchiu", "d,s,t", 0x00000268, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1823 {"macchiu", "d,s,t", 0x00000359, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1824 {"macchius","d,s,t", 0x00000668, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1825 {"maccu", "d,s,t", 0x00000068, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1826 {"maccu", "d,s,t", 0x00000159, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1827 {"maccus", "d,s,t", 0x00000468, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N412 },
1828 {"mad", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 },
1829 {"madu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, P3 },
1830 {"madd.d", "D,R,S,T", 0x4c000021, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 },
1831 {"madd.s", "D,R,S,T", 0x4c000020, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 },
1832 {"madd.ps", "D,R,S,T", 0x4c000026, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 },
1833 {"madd", "s,t", 0x0000001c, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
1834 {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
1835 {"madd", "s,t", 0x70000000, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 },
1836 {"madd", "7,s,t", 0x70000000, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
1837 {"madd", "d,s,t", 0x70000000, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
1838 {"maddp", "s,t", 0x70000441, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT },
1839 {"maddu", "s,t", 0x0000001d, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
1840 {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
1841 {"maddu", "s,t", 0x70000001, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, G1 },
1842 {"maddu", "7,s,t", 0x70000001, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
1843 {"maddu", "d,s,t", 0x70000001, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
1844 {"madd16", "s,t", 0x00000028, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, N411 },
1845 {"max.ob", "X,Y,Q", 0x78000007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
1846 {"max.ob", "D,S,T", 0x4ac00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1847 {"max.ob", "D,S,T[e]", 0x48000007, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
1848 {"max.ob", "D,S,k", 0x4bc00007, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1849 {"max.qh", "X,Y,Q", 0x78200007, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
1850 {"mfpc", "t,P", 0x4000c801, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 },
1851 {"mfps", "t,P", 0x4000c800, 0xffe0ffc1, LCD|WR_t|RD_C0, 0, M1|N5 },
1852 {"mftacx", "d", 0x41020021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
1853 {"mftacx", "d,*", 0x41020021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
1854 {"mftc0", "d,+t", 0x41000000, 0xffe007ff, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
1855 {"mftc0", "d,+T", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
1856 {"mftc0", "d,E,H", 0x41000000, 0xffe007f8, TRAP|LCD|WR_d|RD_C0, 0, MT32 },
1857 {"mftc1", "d,T", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 },
1858 {"mftc1", "d,E", 0x41000022, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_S, 0, MT32 },
1859 {"mftc2", "d,E", 0x41000024, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
1860 {"mftdsp", "d", 0x41100021, 0xffff07ff, TRAP|WR_d, 0, MT32 },
1861 {"mftgpr", "d,t", 0x41000020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 },
1862 {"mfthc1", "d,T", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 },
1863 {"mfthc1", "d,E", 0x41000032, 0xffe007ff, TRAP|LCD|WR_d|RD_T|FP_D, 0, MT32 },
1864 {"mfthc2", "d,E", 0x41000034, 0xffe007ff, TRAP|LCD|WR_d|RD_C2, 0, MT32 },
1865 {"mfthi", "d", 0x41010021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
1866 {"mfthi", "d,*", 0x41010021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
1867 {"mftlo", "d", 0x41000021, 0xffff07ff, TRAP|WR_d|RD_a, 0, MT32 },
1868 {"mftlo", "d,*", 0x41000021, 0xfff307ff, TRAP|WR_d|RD_a, 0, MT32 },
1869 {"mftr", "d,t,!,H,$", 0x41000000, 0xffe007c8, TRAP|WR_d, 0, MT32 },
1870 {"mfc0", "t,G", 0x40000000, 0xffe007ff, LCD|WR_t|RD_C0, 0, I1 },
1871 {"mfc0", "t,+D", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
1872 {"mfc0", "t,G,H", 0x40000000, 0xffe007f8, LCD|WR_t|RD_C0, 0, I32 },
1873 {"mfc1", "t,S", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 },
1874 {"mfc1", "t,G", 0x44000000, 0xffe007ff, LCD|WR_t|RD_S|FP_S, 0, I1 },
1875 {"mfhc1", "t,S", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 },
1876 {"mfhc1", "t,G", 0x44600000, 0xffe007ff, LCD|WR_t|RD_S|FP_D, 0, I33 },
1877 /* mfc2 is at the bottom of the table. */
1878 /* mfhc2 is at the bottom of the table. */
1879 /* mfc3 is at the bottom of the table. */
1880 {"mfdr", "t,G", 0x7000003d, 0xffe007ff, LCD|WR_t|RD_C0, 0, N5 },
1881 {"mfhi", "d", 0x00000010, 0xffff07ff, WR_d|RD_HI, 0, I1 },
1882 {"mfhi", "d,9", 0x00000010, 0xff9f07ff, WR_d|RD_HI, 0, D32 },
1883 {"mflo", "d", 0x00000012, 0xffff07ff, WR_d|RD_LO, 0, I1 },
1884 {"mflo", "d,9", 0x00000012, 0xff9f07ff, WR_d|RD_LO, 0, D32 },
1885 {"mflhxu", "d", 0x00000052, 0xffff07ff, WR_d|MOD_HILO, 0, SMT },
1886 {"min.ob", "X,Y,Q", 0x78000006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
1887 {"min.ob", "D,S,T", 0x4ac00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1888 {"min.ob", "D,S,T[e]", 0x48000006, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
1889 {"min.ob", "D,S,k", 0x4bc00006, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1890 {"min.qh", "X,Y,Q", 0x78200006, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
1891 {"mov.d", "D,S", 0x46200006, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 },
1892 {"mov.s", "D,S", 0x46000006, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
1893 {"mov.ps", "D,S", 0x46c00006, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 },
1894 {"movf", "d,s,N", 0x00000001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4|I32 },
1895 {"movf.d", "D,S,N", 0x46200011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4|I32 },
1896 {"movf.l", "D,S,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
1897 {"movf.l", "X,Y,N", 0x46a00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
1898 {"movf.s", "D,S,N", 0x46000011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 },
1899 {"movf.ps", "D,S,N", 0x46c00011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 },
1900 {"movn", "d,v,t", 0x0000000b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 },
1901 {"ffc", "d,v", 0x0000000b, 0xfc1f07ff, WR_d|RD_s, 0, L1 },
1902 {"movn.d", "D,S,t", 0x46200013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 },
1903 {"movn.l", "D,S,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
1904 {"movn.l", "X,Y,t", 0x46a00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
1905 {"movn.s", "D,S,t", 0x46000013, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4|I32 },
1906 {"movn.ps", "D,S,t", 0x46c00013, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5|I33 },
1907 {"movt", "d,s,N", 0x00010001, 0xfc0307ff, WR_d|RD_s|RD_CC|FP_S|FP_D, 0, I4|I32 },
1908 {"movt.d", "D,S,N", 0x46210011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I4|I32 },
1909 {"movt.l", "D,S,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
1910 {"movt.l", "X,Y,N", 0x46a10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, MX|SB1 },
1911 {"movt.s", "D,S,N", 0x46010011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_S, 0, I4|I32 },
1912 {"movt.ps", "D,S,N", 0x46c10011, 0xffe3003f, WR_D|RD_S|RD_CC|FP_D, 0, I5|I33 },
1913 {"movz", "d,v,t", 0x0000000a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I4|I32 },
1914 {"ffs", "d,v", 0x0000000a, 0xfc1f07ff, WR_d|RD_s, 0, L1 },
1915 {"movz.d", "D,S,t", 0x46200012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I4|I32 },
1916 {"movz.l", "D,S,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
1917 {"movz.l", "X,Y,t", 0x46a00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, MX|SB1 },
1918 {"movz.s", "D,S,t", 0x46000012, 0xffe0003f, WR_D|RD_S|RD_t|FP_S, 0, I4|I32 },
1919 {"movz.ps", "D,S,t", 0x46c00012, 0xffe0003f, WR_D|RD_S|RD_t|FP_D, 0, I5|I33 },
1920 {"msac", "d,s,t", 0x000001d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1921 {"msacu", "d,s,t", 0x000001d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1922 {"msachi", "d,s,t", 0x000003d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1923 {"msachiu", "d,s,t", 0x000003d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1924 /* move is at the top of the table. */
1925 {"msgn.qh", "X,Y,Q", 0x78200000, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
1926 {"msub.d", "D,R,S,T", 0x4c000029, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 },
1927 {"msub.s", "D,R,S,T", 0x4c000028, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 },
1928 {"msub.ps", "D,R,S,T", 0x4c00002e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 },
1929 {"msub", "s,t", 0x0000001e, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
1930 {"msub", "s,t", 0x70000004, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
1931 {"msub", "7,s,t", 0x70000004, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
1932 {"msubu", "s,t", 0x0000001f, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, L1 },
1933 {"msubu", "s,t", 0x70000005, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, I32|N55 },
1934 {"msubu", "7,s,t", 0x70000005, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
1935 {"mtpc", "t,P", 0x4080c801, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
1936 {"mtps", "t,P", 0x4080c800, 0xffe0ffc1, COD|RD_t|WR_C0, 0, M1|N5 },
1937 {"mtc0", "t,G", 0x40800000, 0xffe007ff, COD|RD_t|WR_C0|WR_CC, 0, I1 },
1938 {"mtc0", "t,+D", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 },
1939 {"mtc0", "t,G,H", 0x40800000, 0xffe007f8, COD|RD_t|WR_C0|WR_CC, 0, I32 },
1940 {"mtc1", "t,S", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 },
1941 {"mtc1", "t,G", 0x44800000, 0xffe007ff, COD|RD_t|WR_S|FP_S, 0, I1 },
1942 {"mthc1", "t,S", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 },
1943 {"mthc1", "t,G", 0x44e00000, 0xffe007ff, COD|RD_t|WR_S|FP_D, 0, I33 },
1944 /* mtc2 is at the bottom of the table. */
1945 /* mthc2 is at the bottom of the table. */
1946 /* mtc3 is at the bottom of the table. */
1947 {"mtdr", "t,G", 0x7080003d, 0xffe007ff, COD|RD_t|WR_C0, 0, N5 },
1948 {"mthi", "s", 0x00000011, 0xfc1fffff, RD_s|WR_HI, 0, I1 },
1949 {"mthi", "s,7", 0x00000011, 0xfc1fe7ff, RD_s|WR_HI, 0, D32 },
1950 {"mtlo", "s", 0x00000013, 0xfc1fffff, RD_s|WR_LO, 0, I1 },
1951 {"mtlo", "s,7", 0x00000013, 0xfc1fe7ff, RD_s|WR_LO, 0, D32 },
1952 {"mtlhx", "s", 0x00000053, 0xfc1fffff, RD_s|MOD_HILO, 0, SMT },
1953 {"mttc0", "t,G", 0x41800000, 0xffe007ff, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
1954 {"mttc0", "t,+D", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
1955 {"mttc0", "t,G,H", 0x41800000, 0xffe007f8, TRAP|COD|RD_t|WR_C0|WR_CC, 0, MT32 },
1956 {"mttc1", "t,S", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 },
1957 {"mttc1", "t,G", 0x41800022, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_S, 0, MT32 },
1958 {"mttc2", "t,g", 0x41800024, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 },
1959 {"mttacx", "t", 0x41801021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
1960 {"mttacx", "t,&", 0x41801021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
1961 {"mttdsp", "t", 0x41808021, 0xffe0ffff, TRAP|RD_t, 0, MT32 },
1962 {"mttgpr", "t,d", 0x41800020, 0xffe007ff, TRAP|WR_d|RD_t, 0, MT32 },
1963 {"mtthc1", "t,S", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 },
1964 {"mtthc1", "t,G", 0x41800032, 0xffe007ff, TRAP|COD|RD_t|WR_S|FP_D, 0, MT32 },
1965 {"mtthc2", "t,g", 0x41800034, 0xffe007ff, TRAP|COD|RD_t|WR_C2|WR_CC, 0, MT32 },
1966 {"mtthi", "t", 0x41800821, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
1967 {"mtthi", "t,&", 0x41800821, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
1968 {"mttlo", "t", 0x41800021, 0xffe0ffff, TRAP|WR_a|RD_t, 0, MT32 },
1969 {"mttlo", "t,&", 0x41800021, 0xffe09fff, TRAP|WR_a|RD_t, 0, MT32 },
1970 {"mttr", "t,d,!,H,$", 0x41800000, 0xffe007c8, TRAP|RD_t, 0, MT32 },
1971 {"mul.d", "D,V,T", 0x46200002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
1972 {"mul.s", "D,V,T", 0x46000002, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
1973 {"mul.ob", "X,Y,Q", 0x78000030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
1974 {"mul.ob", "D,S,T", 0x4ac00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1975 {"mul.ob", "D,S,T[e]", 0x48000030, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
1976 {"mul.ob", "D,S,k", 0x4bc00030, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
1977 {"mul.ps", "D,V,T", 0x46c00002, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
1978 {"mul.qh", "X,Y,Q", 0x78200030, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
1979 {"mul", "d,v,t", 0x70000002, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, I32|P3|N55},
1980 {"mul", "d,s,t", 0x00000058, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N54 },
1981 {"mul", "d,v,t", 0, (int) M_MUL, INSN_MACRO, 0, I1 },
1982 {"mul", "d,v,I", 0, (int) M_MUL_I, INSN_MACRO, 0, I1 },
1983 {"mula.ob", "Y,Q", 0x78000033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
1984 {"mula.ob", "S,T", 0x4ac00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1985 {"mula.ob", "S,T[e]", 0x48000033, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
1986 {"mula.ob", "S,k", 0x4bc00033, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1987 {"mula.qh", "Y,Q", 0x78200033, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
1988 {"mulhi", "d,s,t", 0x00000258, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1989 {"mulhiu", "d,s,t", 0x00000259, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
1990 {"mull.ob", "Y,Q", 0x78000433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
1991 {"mull.ob", "S,T", 0x4ac00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1992 {"mull.ob", "S,T[e]", 0x48000433, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
1993 {"mull.ob", "S,k", 0x4bc00433, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
1994 {"mull.qh", "Y,Q", 0x78200433, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
1995 {"mulo", "d,v,t", 0, (int) M_MULO, INSN_MACRO, 0, I1 },
1996 {"mulo", "d,v,I", 0, (int) M_MULO_I, INSN_MACRO, 0, I1 },
1997 {"mulou", "d,v,t", 0, (int) M_MULOU, INSN_MACRO, 0, I1 },
1998 {"mulou", "d,v,I", 0, (int) M_MULOU_I, INSN_MACRO, 0, I1 },
1999 {"mulr.ps", "D,S,T", 0x46c0001a, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D },
2000 {"muls", "d,s,t", 0x000000d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2001 {"mulsu", "d,s,t", 0x000000d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2002 {"mulshi", "d,s,t", 0x000002d8, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2003 {"mulshiu", "d,s,t", 0x000002d9, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2004 {"muls.ob", "Y,Q", 0x78000032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
2005 {"muls.ob", "S,T", 0x4ac00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
2006 {"muls.ob", "S,T[e]", 0x48000032, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
2007 {"muls.ob", "S,k", 0x4bc00032, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
2008 {"muls.qh", "Y,Q", 0x78200032, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
2009 {"mulsl.ob", "Y,Q", 0x78000432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
2010 {"mulsl.ob", "S,T", 0x4ac00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
2011 {"mulsl.ob", "S,T[e]", 0x48000432, 0xfe2007ff, WR_CC|RD_S|RD_T, 0, N54 },
2012 {"mulsl.ob", "S,k", 0x4bc00432, 0xffe007ff, WR_CC|RD_S|RD_T, 0, N54 },
2013 {"mulsl.qh", "Y,Q", 0x78200432, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
2014 {"mult", "s,t", 0x00000018, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 },
2015 {"mult", "7,s,t", 0x00000018, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 },
2016 {"mult", "d,s,t", 0x00000018, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
2017 {"multp", "s,t", 0x00000459, 0xfc00ffff, RD_s|RD_t|MOD_HILO, 0, SMT },
2018 {"multu", "s,t", 0x00000019, 0xfc00ffff, RD_s|RD_t|WR_HILO|IS_M, 0, I1 },
2019 {"multu", "7,s,t", 0x00000019, 0xfc00e7ff, WR_a|RD_s|RD_t, 0, D33 },
2020 {"multu", "d,s,t", 0x00000019, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d|IS_M, 0, G1 },
2021 {"mulu", "d,s,t", 0x00000059, 0xfc0007ff, RD_s|RD_t|WR_HILO|WR_d, 0, N5 },
2022 {"neg", "d,w", 0x00000022, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* sub 0 */
2023 {"negu", "d,w", 0x00000023, 0xffe007ff, WR_d|RD_t, 0, I1 }, /* subu 0 */
2024 {"neg.d", "D,V", 0x46200007, 0xffff003f, WR_D|RD_S|FP_D, 0, I1 },
2025 {"neg.s", "D,V", 0x46000007, 0xffff003f, WR_D|RD_S|FP_S, 0, I1 },
2026 {"neg.ps", "D,V", 0x46c00007, 0xffff003f, WR_D|RD_S|FP_D, 0, I5|I33 },
2027 {"nmadd.d", "D,R,S,T", 0x4c000031, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 },
2028 {"nmadd.s", "D,R,S,T", 0x4c000030, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 },
2029 {"nmadd.ps","D,R,S,T", 0x4c000036, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 },
2030 {"nmsub.d", "D,R,S,T", 0x4c000039, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I4|I33 },
2031 {"nmsub.s", "D,R,S,T", 0x4c000038, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_S, 0, I4|I33 },
2032 {"nmsub.ps","D,R,S,T", 0x4c00003e, 0xfc00003f, RD_R|RD_S|RD_T|WR_D|FP_D, 0, I5|I33 },
2033 /* nop is at the start of the table. */
2034 {"nor", "d,v,t", 0x00000027, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2035 {"nor", "t,r,I", 0, (int) M_NOR_I, INSN_MACRO, 0, I1 },
2036 {"nor.ob", "X,Y,Q", 0x7800000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2037 {"nor.ob", "D,S,T", 0x4ac0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2038 {"nor.ob", "D,S,T[e]", 0x4800000f, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2039 {"nor.ob", "D,S,k", 0x4bc0000f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2040 {"nor.qh", "X,Y,Q", 0x7820000f, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2041 {"not", "d,v", 0x00000027, 0xfc1f07ff, WR_d|RD_s|RD_t, 0, I1 },/*nor d,s,0*/
2042 {"or", "d,v,t", 0x00000025, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2043 {"or", "t,r,I", 0, (int) M_OR_I, INSN_MACRO, 0, I1 },
2044 {"or.ob", "X,Y,Q", 0x7800000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2045 {"or.ob", "D,S,T", 0x4ac0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2046 {"or.ob", "D,S,T[e]", 0x4800000e, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2047 {"or.ob", "D,S,k", 0x4bc0000e, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2048 {"or.qh", "X,Y,Q", 0x7820000e, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2049 {"ori", "t,r,i", 0x34000000, 0xfc000000, WR_t|RD_s, 0, I1 },
2050 {"pabsdiff.ob", "X,Y,Q",0x78000009, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 },
2051 {"pabsdiffc.ob", "Y,Q", 0x78000035, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, SB1 },
2052 {"pavg.ob", "X,Y,Q", 0x78000008, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, SB1 },
2053 {"pickf.ob", "X,Y,Q", 0x78000002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2054 {"pickf.ob", "D,S,T", 0x4ac00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2055 {"pickf.ob", "D,S,T[e]",0x48000002, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2056 {"pickf.ob", "D,S,k", 0x4bc00002, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2057 {"pickf.qh", "X,Y,Q", 0x78200002, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2058 {"pickt.ob", "X,Y,Q", 0x78000003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2059 {"pickt.ob", "D,S,T", 0x4ac00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2060 {"pickt.ob", "D,S,T[e]",0x48000003, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2061 {"pickt.ob", "D,S,k", 0x4bc00003, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2062 {"pickt.qh", "X,Y,Q", 0x78200003, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2063 {"pll.ps", "D,V,T", 0x46c0002c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
2064 {"plu.ps", "D,V,T", 0x46c0002d, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
2065 /* pref and prefx are at the start of the table. */
2066 {"pul.ps", "D,V,T", 0x46c0002e, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
2067 {"puu.ps", "D,V,T", 0x46c0002f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
2068 {"pperm", "s,t", 0x70000481, 0xfc00ffff, MOD_HILO|RD_s|RD_t, 0, SMT },
2069 {"rach.ob", "X", 0x7a00003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 },
2070 {"rach.ob", "D", 0x4a00003f, 0xfffff83f, WR_D, 0, N54 },
2071 {"rach.qh", "X", 0x7a20003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX },
2072 {"racl.ob", "X", 0x7800003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 },
2073 {"racl.ob", "D", 0x4800003f, 0xfffff83f, WR_D, 0, N54 },
2074 {"racl.qh", "X", 0x7820003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX },
2075 {"racm.ob", "X", 0x7900003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX|SB1 },
2076 {"racm.ob", "D", 0x4900003f, 0xfffff83f, WR_D, 0, N54 },
2077 {"racm.qh", "X", 0x7920003f, 0xfffff83f, WR_D|FP_D, RD_MACC, MX },
2078 {"recip.d", "D,S", 0x46200015, 0xffff003f, WR_D|RD_S|FP_D, 0, I4|I33 },
2079 {"recip.ps","D,S", 0x46c00015, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 },
2080 {"recip.s", "D,S", 0x46000015, 0xffff003f, WR_D|RD_S|FP_S, 0, I4|I33 },
2081 {"recip1.d", "D,S", 0x4620001d, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D },
2082 {"recip1.ps", "D,S", 0x46c0001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D },
2083 {"recip1.s", "D,S", 0x4600001d, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D },
2084 {"recip2.d", "D,S,T", 0x4620001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D },
2085 {"recip2.ps", "D,S,T", 0x46c0001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D },
2086 {"recip2.s", "D,S,T", 0x4600001c, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D },
2087 {"rem", "z,s,t", 0x0000001a, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
2088 {"rem", "d,v,t", 0, (int) M_REM_3, INSN_MACRO, 0, I1 },
2089 {"rem", "d,v,I", 0, (int) M_REM_3I, INSN_MACRO, 0, I1 },
2090 {"remu", "z,s,t", 0x0000001b, 0xfc00ffff, RD_s|RD_t|WR_HILO, 0, I1 },
2091 {"remu", "d,v,t", 0, (int) M_REMU_3, INSN_MACRO, 0, I1 },
2092 {"remu", "d,v,I", 0, (int) M_REMU_3I, INSN_MACRO, 0, I1 },
2093 {"rdhwr", "t,K", 0x7c00003b, 0xffe007ff, WR_t, 0, I33 },
2094 {"rdpgpr", "d,w", 0x41400000, 0xffe007ff, WR_d, 0, I33 },
2095 {"rfe", "", 0x42000010, 0xffffffff, 0, 0, I1|T3 },
2096 {"rnas.qh", "X,Q", 0x78200025, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2097 {"rnau.ob", "X,Q", 0x78000021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 },
2098 {"rnau.qh", "X,Q", 0x78200021, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2099 {"rnes.qh", "X,Q", 0x78200026, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2100 {"rneu.ob", "X,Q", 0x78000022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 },
2101 {"rneu.qh", "X,Q", 0x78200022, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2102 {"rol", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I1 },
2103 {"rol", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I1 },
2104 {"ror", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I1 },
2105 {"ror", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I1 },
2106 {"ror", "d,w,<", 0x00200002, 0xffe0003f, WR_d|RD_t, 0, N5|I33|SMT },
2107 {"rorv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, N5|I33|SMT },
2108 {"rotl", "d,v,t", 0, (int) M_ROL, INSN_MACRO, 0, I33|SMT },
2109 {"rotl", "d,v,I", 0, (int) M_ROL_I, INSN_MACRO, 0, I33|SMT },
2110 {"rotr", "d,v,t", 0, (int) M_ROR, INSN_MACRO, 0, I33|SMT },
2111 {"rotr", "d,v,I", 0, (int) M_ROR_I, INSN_MACRO, 0, I33|SMT },
2112 {"rotrv", "d,t,s", 0x00000046, 0xfc0007ff, RD_t|RD_s|WR_d, 0, I33|SMT },
2113 {"round.l.d", "D,S", 0x46200008, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
2114 {"round.l.s", "D,S", 0x46000008, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
2115 {"round.w.d", "D,S", 0x4620000c, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
2116 {"round.w.s", "D,S", 0x4600000c, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
2117 {"rsqrt.d", "D,S", 0x46200016, 0xffff003f, WR_D|RD_S|FP_D, 0, I4|I33 },
2118 {"rsqrt.ps","D,S", 0x46c00016, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 },
2119 {"rsqrt.s", "D,S", 0x46000016, 0xffff003f, WR_D|RD_S|FP_S, 0, I4|I33 },
2120 {"rsqrt1.d", "D,S", 0x4620001e, 0xffff003f, WR_D|RD_S|FP_D, 0, M3D },
2121 {"rsqrt1.ps", "D,S", 0x46c0001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D },
2122 {"rsqrt1.s", "D,S", 0x4600001e, 0xffff003f, WR_D|RD_S|FP_S, 0, M3D },
2123 {"rsqrt2.d", "D,S,T", 0x4620001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, M3D },
2124 {"rsqrt2.ps", "D,S,T", 0x46c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D },
2125 {"rsqrt2.s", "D,S,T", 0x4600001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, M3D },
2126 {"rzs.qh", "X,Q", 0x78200024, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2127 {"rzu.ob", "X,Q", 0x78000020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX|SB1 },
2128 {"rzu.ob", "D,k", 0x4bc00020, 0xffe0f83f, WR_D|RD_S|RD_T, 0, N54 },
2129 {"rzu.qh", "X,Q", 0x78200020, 0xfc20f83f, WR_D|RD_T|FP_D, RD_MACC, MX },
2130 {"sb", "t,o(b)", 0xa0000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
2131 {"sb", "t,A(b)", 0, (int) M_SB_AB, INSN_MACRO, 0, I1 },
2132 {"sc", "t,o(b)", 0xe0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I2 },
2133 {"sc", "t,A(b)", 0, (int) M_SC_AB, INSN_MACRO, 0, I2 },
2134 {"scd", "t,o(b)", 0xf0000000, 0xfc000000, SM|RD_t|WR_t|RD_b, 0, I3 },
2135 {"scd", "t,A(b)", 0, (int) M_SCD_AB, INSN_MACRO, 0, I3 },
2136 {"sd", "t,o(b)", 0xfc000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
2137 {"sd", "t,o(b)", 0, (int) M_SD_OB, INSN_MACRO, 0, I1 },
2138 {"sd", "t,A(b)", 0, (int) M_SD_AB, INSN_MACRO, 0, I1 },
2139 {"sdbbp", "", 0x0000000e, 0xffffffff, TRAP, 0, G2 },
2140 {"sdbbp", "c", 0x0000000e, 0xfc00ffff, TRAP, 0, G2 },
2141 {"sdbbp", "c,q", 0x0000000e, 0xfc00003f, TRAP, 0, G2 },
2142 {"sdbbp", "", 0x7000003f, 0xffffffff, TRAP, 0, I32 },
2143 {"sdbbp", "B", 0x7000003f, 0xfc00003f, TRAP, 0, I32 },
2144 {"sdc1", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
2145 {"sdc1", "E,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
2146 {"sdc1", "T,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 },
2147 {"sdc1", "E,A(b)", 0, (int) M_SDC1_AB, INSN_MACRO, 0, I2 },
2148 {"sdc2", "E,o(b)", 0xf8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I2 },
2149 {"sdc2", "E,A(b)", 0, (int) M_SDC2_AB, INSN_MACRO, 0, I2 },
2150 {"sdc3", "E,o(b)", 0xfc000000, 0xfc000000, SM|RD_C3|RD_b, 0, I2 },
2151 {"sdc3", "E,A(b)", 0, (int) M_SDC3_AB, INSN_MACRO, 0, I2 },
2152 {"s.d", "T,o(b)", 0xf4000000, 0xfc000000, SM|RD_T|RD_b|FP_D, 0, I2 },
2153 {"s.d", "T,o(b)", 0, (int) M_S_DOB, INSN_MACRO, 0, I1 },
2154 {"s.d", "T,A(b)", 0, (int) M_S_DAB, INSN_MACRO, 0, I1 },
2155 {"sdl", "t,o(b)", 0xb0000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
2156 {"sdl", "t,A(b)", 0, (int) M_SDL_AB, INSN_MACRO, 0, I3 },
2157 {"sdr", "t,o(b)", 0xb4000000, 0xfc000000, SM|RD_t|RD_b, 0, I3 },
2158 {"sdr", "t,A(b)", 0, (int) M_SDR_AB, INSN_MACRO, 0, I3 },
2159 {"sdxc1", "S,t(b)", 0x4c000009, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_D, 0, I4|I33 },
2160 {"seb", "d,w", 0x7c000420, 0xffe007ff, WR_d|RD_t, 0, I33 },
2161 {"seh", "d,w", 0x7c000620, 0xffe007ff, WR_d|RD_t, 0, I33 },
2162 {"selsl", "d,v,t", 0x00000005, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 },
2163 {"selsr", "d,v,t", 0x00000001, 0xfc0007ff, WR_d|RD_s|RD_t, 0, L1 },
2164 {"seq", "d,v,t", 0, (int) M_SEQ, INSN_MACRO, 0, I1 },
2165 {"seq", "d,v,I", 0, (int) M_SEQ_I, INSN_MACRO, 0, I1 },
2166 {"sge", "d,v,t", 0, (int) M_SGE, INSN_MACRO, 0, I1 },
2167 {"sge", "d,v,I", 0, (int) M_SGE_I, INSN_MACRO, 0, I1 },
2168 {"sgeu", "d,v,t", 0, (int) M_SGEU, INSN_MACRO, 0, I1 },
2169 {"sgeu", "d,v,I", 0, (int) M_SGEU_I, INSN_MACRO, 0, I1 },
2170 {"sgt", "d,v,t", 0, (int) M_SGT, INSN_MACRO, 0, I1 },
2171 {"sgt", "d,v,I", 0, (int) M_SGT_I, INSN_MACRO, 0, I1 },
2172 {"sgtu", "d,v,t", 0, (int) M_SGTU, INSN_MACRO, 0, I1 },
2173 {"sgtu", "d,v,I", 0, (int) M_SGTU_I, INSN_MACRO, 0, I1 },
2174 {"sh", "t,o(b)", 0xa4000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
2175 {"sh", "t,A(b)", 0, (int) M_SH_AB, INSN_MACRO, 0, I1 },
2176 {"shfl.bfla.qh", "X,Y,Z", 0x7a20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2177 {"shfl.mixh.ob", "X,Y,Z", 0x7980001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2178 {"shfl.mixh.ob", "D,S,T", 0x4980001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2179 {"shfl.mixh.qh", "X,Y,Z", 0x7820001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2180 {"shfl.mixl.ob", "X,Y,Z", 0x79c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2181 {"shfl.mixl.ob", "D,S,T", 0x49c0001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2182 {"shfl.mixl.qh", "X,Y,Z", 0x78a0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2183 {"shfl.pach.ob", "X,Y,Z", 0x7900001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2184 {"shfl.pach.ob", "D,S,T", 0x4900001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2185 {"shfl.pach.qh", "X,Y,Z", 0x7920001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2186 {"shfl.pacl.ob", "D,S,T", 0x4940001f, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2187 {"shfl.repa.qh", "X,Y,Z", 0x7b20001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2188 {"shfl.repb.qh", "X,Y,Z", 0x7ba0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2189 {"shfl.upsl.ob", "X,Y,Z", 0x78c0001f, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2190 {"sle", "d,v,t", 0, (int) M_SLE, INSN_MACRO, 0, I1 },
2191 {"sle", "d,v,I", 0, (int) M_SLE_I, INSN_MACRO, 0, I1 },
2192 {"sleu", "d,v,t", 0, (int) M_SLEU, INSN_MACRO, 0, I1 },
2193 {"sleu", "d,v,I", 0, (int) M_SLEU_I, INSN_MACRO, 0, I1 },
2194 {"sllv", "d,t,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
2195 {"sll", "d,w,s", 0x00000004, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* sllv */
2196 {"sll", "d,w,<", 0x00000000, 0xffe0003f, WR_d|RD_t, 0, I1 },
2197 {"sll.ob", "X,Y,Q", 0x78000010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2198 {"sll.ob", "D,S,T[e]", 0x48000010, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2199 {"sll.ob", "D,S,k", 0x4bc00010, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2200 {"sll.qh", "X,Y,Q", 0x78200010, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2201 {"slt", "d,v,t", 0x0000002a, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2202 {"slt", "d,v,I", 0, (int) M_SLT_I, INSN_MACRO, 0, I1 },
2203 {"slti", "t,r,j", 0x28000000, 0xfc000000, WR_t|RD_s, 0, I1 },
2204 {"sltiu", "t,r,j", 0x2c000000, 0xfc000000, WR_t|RD_s, 0, I1 },
2205 {"sltu", "d,v,t", 0x0000002b, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2206 {"sltu", "d,v,I", 0, (int) M_SLTU_I, INSN_MACRO, 0, I1 },
2207 {"sne", "d,v,t", 0, (int) M_SNE, INSN_MACRO, 0, I1 },
2208 {"sne", "d,v,I", 0, (int) M_SNE_I, INSN_MACRO, 0, I1 },
2209 {"sqrt.d", "D,S", 0x46200004, 0xffff003f, WR_D|RD_S|FP_D, 0, I2 },
2210 {"sqrt.s", "D,S", 0x46000004, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
2211 {"sqrt.ps", "D,S", 0x46c00004, 0xffff003f, WR_D|RD_S|FP_D, 0, SB1 },
2212 {"srav", "d,t,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
2213 {"sra", "d,w,s", 0x00000007, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srav */
2214 {"sra", "d,w,<", 0x00000003, 0xffe0003f, WR_d|RD_t, 0, I1 },
2215 {"sra.qh", "X,Y,Q", 0x78200013, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2216 {"srlv", "d,t,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 },
2217 {"srl", "d,w,s", 0x00000006, 0xfc0007ff, WR_d|RD_t|RD_s, 0, I1 }, /* srlv */
2218 {"srl", "d,w,<", 0x00000002, 0xffe0003f, WR_d|RD_t, 0, I1 },
2219 {"srl.ob", "X,Y,Q", 0x78000012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2220 {"srl.ob", "D,S,T[e]", 0x48000012, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2221 {"srl.ob", "D,S,k", 0x4bc00012, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2222 {"srl.qh", "X,Y,Q", 0x78200012, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2223 /* ssnop is at the start of the table. */
2224 {"standby", "", 0x42000021, 0xffffffff, 0, 0, V1 },
2225 {"sub", "d,v,t", 0x00000022, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2226 {"sub", "d,v,I", 0, (int) M_SUB_I, INSN_MACRO, 0, I1 },
2227 {"sub.d", "D,V,T", 0x46200001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I1 },
2228 {"sub.s", "D,V,T", 0x46000001, 0xffe0003f, WR_D|RD_S|RD_T|FP_S, 0, I1 },
2229 {"sub.ob", "X,Y,Q", 0x7800000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2230 {"sub.ob", "D,S,T", 0x4ac0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2231 {"sub.ob", "D,S,T[e]", 0x4800000a, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2232 {"sub.ob", "D,S,k", 0x4bc0000a, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2233 {"sub.ps", "D,V,T", 0x46c00001, 0xffe0003f, WR_D|RD_S|RD_T|FP_D, 0, I5|I33 },
2234 {"sub.qh", "X,Y,Q", 0x7820000a, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2235 {"suba.ob", "Y,Q", 0x78000036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
2236 {"suba.qh", "Y,Q", 0x78200036, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
2237 {"subl.ob", "Y,Q", 0x78000436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
2238 {"subl.qh", "Y,Q", 0x78200436, 0xfc2007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
2239 {"subu", "d,v,t", 0x00000023, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2240 {"subu", "d,v,I", 0, (int) M_SUBU_I, INSN_MACRO, 0, I1 },
2241 {"suspend", "", 0x42000022, 0xffffffff, 0, 0, V1 },
2242 {"suxc1", "S,t(b)", 0x4c00000d, 0xfc0007ff, SM|RD_S|RD_t|RD_b, 0, I5|I33|N55},
2243 {"sw", "t,o(b)", 0xac000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
2244 {"sw", "t,A(b)", 0, (int) M_SW_AB, INSN_MACRO, 0, I1 },
2245 {"swc0", "E,o(b)", 0xe0000000, 0xfc000000, SM|RD_C0|RD_b, 0, I1 },
2246 {"swc0", "E,A(b)", 0, (int) M_SWC0_AB, INSN_MACRO, 0, I1 },
2247 {"swc1", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
2248 {"swc1", "E,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 },
2249 {"swc1", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 },
2250 {"swc1", "E,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 },
2251 {"s.s", "T,o(b)", 0xe4000000, 0xfc000000, SM|RD_T|RD_b|FP_S, 0, I1 }, /* swc1 */
2252 {"s.s", "T,A(b)", 0, (int) M_SWC1_AB, INSN_MACRO, 0, I1 },
2253 {"swc2", "E,o(b)", 0xe8000000, 0xfc000000, SM|RD_C2|RD_b, 0, I1 },
2254 {"swc2", "E,A(b)", 0, (int) M_SWC2_AB, INSN_MACRO, 0, I1 },
2255 {"swc3", "E,o(b)", 0xec000000, 0xfc000000, SM|RD_C3|RD_b, 0, I1 },
2256 {"swc3", "E,A(b)", 0, (int) M_SWC3_AB, INSN_MACRO, 0, I1 },
2257 {"swl", "t,o(b)", 0xa8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
2258 {"swl", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I1 },
2259 {"scache", "t,o(b)", 0xa8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */
2260 {"scache", "t,A(b)", 0, (int) M_SWL_AB, INSN_MACRO, 0, I2 }, /* as swl */
2261 {"swr", "t,o(b)", 0xb8000000, 0xfc000000, SM|RD_t|RD_b, 0, I1 },
2262 {"swr", "t,A(b)", 0, (int) M_SWR_AB, INSN_MACRO, 0, I1 },
2263 {"invalidate", "t,o(b)",0xb8000000, 0xfc000000, RD_t|RD_b, 0, I2 }, /* same */
2264 {"invalidate", "t,A(b)",0, (int) M_SWR_AB, INSN_MACRO, 0, I2 }, /* as swr */
2265 {"swxc1", "S,t(b)", 0x4c000008, 0xfc0007ff, SM|RD_S|RD_t|RD_b|FP_S, 0, I4|I33 },
2266 {"sync", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2|G1 },
2267 {"sync.p", "", 0x0000040f, 0xffffffff, INSN_SYNC, 0, I2 },
2268 {"sync.l", "", 0x0000000f, 0xffffffff, INSN_SYNC, 0, I2 },
2269 {"synci", "o(b)", 0x041f0000, 0xfc1f0000, SM|RD_b, 0, I33 },
2270 {"syscall", "", 0x0000000c, 0xffffffff, TRAP, 0, I1 },
2271 {"syscall", "B", 0x0000000c, 0xfc00003f, TRAP, 0, I1 },
2272 {"teqi", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
2273 {"teq", "s,t", 0x00000034, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
2274 {"teq", "s,t,q", 0x00000034, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
2275 {"teq", "s,j", 0x040c0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* teqi */
2276 {"teq", "s,I", 0, (int) M_TEQ_I, INSN_MACRO, 0, I2 },
2277 {"tgei", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
2278 {"tge", "s,t", 0x00000030, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
2279 {"tge", "s,t,q", 0x00000030, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
2280 {"tge", "s,j", 0x04080000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgei */
2281 {"tge", "s,I", 0, (int) M_TGE_I, INSN_MACRO, 0, I2 },
2282 {"tgeiu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
2283 {"tgeu", "s,t", 0x00000031, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
2284 {"tgeu", "s,t,q", 0x00000031, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
2285 {"tgeu", "s,j", 0x04090000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tgeiu */
2286 {"tgeu", "s,I", 0, (int) M_TGEU_I, INSN_MACRO, 0, I2 },
2287 {"tlbp", "", 0x42000008, 0xffffffff, INSN_TLB, 0, I1 },
2288 {"tlbr", "", 0x42000001, 0xffffffff, INSN_TLB, 0, I1 },
2289 {"tlbwi", "", 0x42000002, 0xffffffff, INSN_TLB, 0, I1 },
2290 {"tlbwr", "", 0x42000006, 0xffffffff, INSN_TLB, 0, I1 },
2291 {"tlti", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
2292 {"tlt", "s,t", 0x00000032, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
2293 {"tlt", "s,t,q", 0x00000032, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
2294 {"tlt", "s,j", 0x040a0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tlti */
2295 {"tlt", "s,I", 0, (int) M_TLT_I, INSN_MACRO, 0, I2 },
2296 {"tltiu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
2297 {"tltu", "s,t", 0x00000033, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
2298 {"tltu", "s,t,q", 0x00000033, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
2299 {"tltu", "s,j", 0x040b0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tltiu */
2300 {"tltu", "s,I", 0, (int) M_TLTU_I, INSN_MACRO, 0, I2 },
2301 {"tnei", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 },
2302 {"tne", "s,t", 0x00000036, 0xfc00ffff, RD_s|RD_t|TRAP, 0, I2 },
2303 {"tne", "s,t,q", 0x00000036, 0xfc00003f, RD_s|RD_t|TRAP, 0, I2 },
2304 {"tne", "s,j", 0x040e0000, 0xfc1f0000, RD_s|TRAP, 0, I2 }, /* tnei */
2305 {"tne", "s,I", 0, (int) M_TNE_I, INSN_MACRO, 0, I2 },
2306 {"trunc.l.d", "D,S", 0x46200009, 0xffff003f, WR_D|RD_S|FP_D, 0, I3|I33 },
2307 {"trunc.l.s", "D,S", 0x46000009, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I3|I33 },
2308 {"trunc.w.d", "D,S", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
2309 {"trunc.w.d", "D,S,x", 0x4620000d, 0xffff003f, WR_D|RD_S|FP_S|FP_D, 0, I2 },
2310 {"trunc.w.d", "D,S,t", 0, (int) M_TRUNCWD, INSN_MACRO, 0, I1 },
2311 {"trunc.w.s", "D,S", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
2312 {"trunc.w.s", "D,S,x", 0x4600000d, 0xffff003f, WR_D|RD_S|FP_S, 0, I2 },
2313 {"trunc.w.s", "D,S,t", 0, (int) M_TRUNCWS, INSN_MACRO, 0, I1 },
2314 {"uld", "t,o(b)", 0, (int) M_ULD, INSN_MACRO, 0, I3 },
2315 {"uld", "t,A(b)", 0, (int) M_ULD_A, INSN_MACRO, 0, I3 },
2316 {"ulh", "t,o(b)", 0, (int) M_ULH, INSN_MACRO, 0, I1 },
2317 {"ulh", "t,A(b)", 0, (int) M_ULH_A, INSN_MACRO, 0, I1 },
2318 {"ulhu", "t,o(b)", 0, (int) M_ULHU, INSN_MACRO, 0, I1 },
2319 {"ulhu", "t,A(b)", 0, (int) M_ULHU_A, INSN_MACRO, 0, I1 },
2320 {"ulw", "t,o(b)", 0, (int) M_ULW, INSN_MACRO, 0, I1 },
2321 {"ulw", "t,A(b)", 0, (int) M_ULW_A, INSN_MACRO, 0, I1 },
2322 {"usd", "t,o(b)", 0, (int) M_USD, INSN_MACRO, 0, I3 },
2323 {"usd", "t,A(b)", 0, (int) M_USD_A, INSN_MACRO, 0, I3 },
2324 {"ush", "t,o(b)", 0, (int) M_USH, INSN_MACRO, 0, I1 },
2325 {"ush", "t,A(b)", 0, (int) M_USH_A, INSN_MACRO, 0, I1 },
2326 {"usw", "t,o(b)", 0, (int) M_USW, INSN_MACRO, 0, I1 },
2327 {"usw", "t,A(b)", 0, (int) M_USW_A, INSN_MACRO, 0, I1 },
2328 {"wach.ob", "Y", 0x7a00003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX|SB1 },
2329 {"wach.ob", "S", 0x4a00003e, 0xffff07ff, RD_S, 0, N54 },
2330 {"wach.qh", "Y", 0x7a20003e, 0xffff07ff, RD_S|FP_D, WR_MACC, MX },
2331 {"wacl.ob", "Y,Z", 0x7800003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX|SB1 },
2332 {"wacl.ob", "S,T", 0x4800003e, 0xffe007ff, RD_S|RD_T, 0, N54 },
2333 {"wacl.qh", "Y,Z", 0x7820003e, 0xffe007ff, RD_S|RD_T|FP_D, WR_MACC, MX },
2334 {"wait", "", 0x42000020, 0xffffffff, TRAP, 0, I3|I32 },
2335 {"wait", "J", 0x42000020, 0xfe00003f, TRAP, 0, I32|N55 },
2336 {"waiti", "", 0x42000020, 0xffffffff, TRAP, 0, L1 },
2337 {"wrpgpr", "d,w", 0x41c00000, 0xffe007ff, RD_t, 0, I33 },
2338 {"wsbh", "d,w", 0x7c0000a0, 0xffe007ff, WR_d|RD_t, 0, I33 },
2339 {"xor", "d,v,t", 0x00000026, 0xfc0007ff, WR_d|RD_s|RD_t, 0, I1 },
2340 {"xor", "t,r,I", 0, (int) M_XOR_I, INSN_MACRO, 0, I1 },
2341 {"xor.ob", "X,Y,Q", 0x7800000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX|SB1 },
2342 {"xor.ob", "D,S,T", 0x4ac0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2343 {"xor.ob", "D,S,T[e]", 0x4800000d, 0xfe20003f, WR_D|RD_S|RD_T, 0, N54 },
2344 {"xor.ob", "D,S,k", 0x4bc0000d, 0xffe0003f, WR_D|RD_S|RD_T, 0, N54 },
2345 {"xor.qh", "X,Y,Q", 0x7820000d, 0xfc20003f, WR_D|RD_S|RD_T|FP_D, 0, MX },
2346 {"xori", "t,r,i", 0x38000000, 0xfc000000, WR_t|RD_s, 0, I1 },
2347 {"yield", "s", 0x7c000009, 0xfc1fffff, TRAP|RD_s, 0, MT32 },
2348 {"yield", "d,s", 0x7c000009, 0xfc1f07ff, TRAP|WR_d|RD_s, 0, MT32 },
2349
2350 /* User Defined Instruction. */
2351 {"udi0", "s,t,d,+1",0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2352 {"udi0", "s,t,+2", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2353 {"udi0", "s,+3", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2354 {"udi0", "+4", 0x70000010, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2355 {"udi1", "s,t,d,+1",0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2356 {"udi1", "s,t,+2", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2357 {"udi1", "s,+3", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2358 {"udi1", "+4", 0x70000011, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2359 {"udi2", "s,t,d,+1",0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2360 {"udi2", "s,t,+2", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2361 {"udi2", "s,+3", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2362 {"udi2", "+4", 0x70000012, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2363 {"udi3", "s,t,d,+1",0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2364 {"udi3", "s,t,+2", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2365 {"udi3", "s,+3", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2366 {"udi3", "+4", 0x70000013, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2367 {"udi4", "s,t,d,+1",0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2368 {"udi4", "s,t,+2", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2369 {"udi4", "s,+3", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2370 {"udi4", "+4", 0x70000014, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2371 {"udi5", "s,t,d,+1",0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2372 {"udi5", "s,t,+2", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2373 {"udi5", "s,+3", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2374 {"udi5", "+4", 0x70000015, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2375 {"udi6", "s,t,d,+1",0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2376 {"udi6", "s,t,+2", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2377 {"udi6", "s,+3", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2378 {"udi6", "+4", 0x70000016, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2379 {"udi7", "s,t,d,+1",0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2380 {"udi7", "s,t,+2", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2381 {"udi7", "s,+3", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2382 {"udi7", "+4", 0x70000017, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2383 {"udi8", "s,t,d,+1",0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2384 {"udi8", "s,t,+2", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2385 {"udi8", "s,+3", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2386 {"udi8", "+4", 0x70000018, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2387 {"udi9", "s,t,d,+1",0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2388 {"udi9", "s,t,+2", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2389 {"udi9", "s,+3", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2390 {"udi9", "+4", 0x70000019, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2391 {"udi10", "s,t,d,+1",0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2392 {"udi10", "s,t,+2", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2393 {"udi10", "s,+3", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2394 {"udi10", "+4", 0x7000001a, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2395 {"udi11", "s,t,d,+1",0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2396 {"udi11", "s,t,+2", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2397 {"udi11", "s,+3", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2398 {"udi11", "+4", 0x7000001b, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2399 {"udi12", "s,t,d,+1",0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2400 {"udi12", "s,t,+2", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2401 {"udi12", "s,+3", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2402 {"udi12", "+4", 0x7000001c, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2403 {"udi13", "s,t,d,+1",0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2404 {"udi13", "s,t,+2", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2405 {"udi13", "s,+3", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2406 {"udi13", "+4", 0x7000001d, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2407 {"udi14", "s,t,d,+1",0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2408 {"udi14", "s,t,+2", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2409 {"udi14", "s,+3", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2410 {"udi14", "+4", 0x7000001e, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2411 {"udi15", "s,t,d,+1",0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2412 {"udi15", "s,t,+2", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2413 {"udi15", "s,+3", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2414 {"udi15", "+4", 0x7000001f, 0xfc00003f, WR_d|RD_s|RD_t, 0, I33 },
2415
2416 /* Coprocessor 2 move/branch operations overlap with VR5400 .ob format
2417 instructions so they are here for the latters to take precedence. */
2418 {"bc2f", "p", 0x49000000, 0xffff0000, CBD|RD_CC, 0, I1 },
2419 {"bc2f", "N,p", 0x49000000, 0xffe30000, CBD|RD_CC, 0, I32 },
2420 {"bc2fl", "p", 0x49020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
2421 {"bc2fl", "N,p", 0x49020000, 0xffe30000, CBL|RD_CC, 0, I32 },
2422 {"bc2t", "p", 0x49010000, 0xffff0000, CBD|RD_CC, 0, I1 },
2423 {"bc2t", "N,p", 0x49010000, 0xffe30000, CBD|RD_CC, 0, I32 },
2424 {"bc2tl", "p", 0x49030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
2425 {"bc2tl", "N,p", 0x49030000, 0xffe30000, CBL|RD_CC, 0, I32 },
2426 {"cfc2", "t,G", 0x48400000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 },
2427 {"ctc2", "t,G", 0x48c00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
2428 {"dmfc2", "t,G", 0x48200000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I3 },
2429 {"dmfc2", "t,G,H", 0x48200000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I64 },
2430 {"dmtc2", "t,G", 0x48a00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I3 },
2431 {"dmtc2", "t,G,H", 0x48a00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I64 },
2432 {"mfc2", "t,G", 0x48000000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I1 },
2433 {"mfc2", "t,G,H", 0x48000000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I32 },
2434 {"mfhc2", "t,G", 0x48600000, 0xffe007ff, LCD|WR_t|RD_C2, 0, I33 },
2435 {"mfhc2", "t,G,H", 0x48600000, 0xffe007f8, LCD|WR_t|RD_C2, 0, I33 },
2436 {"mfhc2", "t,i", 0x48600000, 0xffe00000, LCD|WR_t|RD_C2, 0, I33 },
2437 {"mtc2", "t,G", 0x48800000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I1 },
2438 {"mtc2", "t,G,H", 0x48800000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I32 },
2439 {"mthc2", "t,G", 0x48e00000, 0xffe007ff, COD|RD_t|WR_C2|WR_CC, 0, I33 },
2440 {"mthc2", "t,G,H", 0x48e00000, 0xffe007f8, COD|RD_t|WR_C2|WR_CC, 0, I33 },
2441 {"mthc2", "t,i", 0x48e00000, 0xffe00000, COD|RD_t|WR_C2|WR_CC, 0, I33 },
2442
2443 /* Coprocessor 3 move/branch operations overlap with MIPS IV COP1X
2444 instructions, so they are here for the latters to take precedence. */
2445 {"bc3f", "p", 0x4d000000, 0xffff0000, CBD|RD_CC, 0, I1 },
2446 {"bc3fl", "p", 0x4d020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
2447 {"bc3t", "p", 0x4d010000, 0xffff0000, CBD|RD_CC, 0, I1 },
2448 {"bc3tl", "p", 0x4d030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
2449 {"cfc3", "t,G", 0x4c400000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 },
2450 {"ctc3", "t,G", 0x4cc00000, 0xffe007ff, COD|RD_t|WR_CC, 0, I1 },
2451 {"dmfc3", "t,G", 0x4c200000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I3 },
2452 {"dmtc3", "t,G", 0x4ca00000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I3 },
2453 {"mfc3", "t,G", 0x4c000000, 0xffe007ff, LCD|WR_t|RD_C3, 0, I1 },
2454 {"mfc3", "t,G,H", 0x4c000000, 0xffe007f8, LCD|WR_t|RD_C3, 0, I32 },
2455 {"mtc3", "t,G", 0x4c800000, 0xffe007ff, COD|RD_t|WR_C3|WR_CC, 0, I1 },
2456 {"mtc3", "t,G,H", 0x4c800000, 0xffe007f8, COD|RD_t|WR_C3|WR_CC, 0, I32 },
2457
2458 /* No hazard protection on coprocessor instructions--they shouldn't
2459 change the state of the processor and if they do it's up to the
2460 user to put in nops as necessary. These are at the end so that the
2461 disassembler recognizes more specific versions first. */
2462 {"c0", "C", 0x42000000, 0xfe000000, 0, 0, I1 },
2463 {"c1", "C", 0x46000000, 0xfe000000, 0, 0, I1 },
2464 {"c2", "C", 0x4a000000, 0xfe000000, 0, 0, I1 },
2465 {"c3", "C", 0x4e000000, 0xfe000000, 0, 0, I1 },
2466 {"cop0", "C", 0, (int) M_COP0, INSN_MACRO, 0, I1 },
2467 {"cop1", "C", 0, (int) M_COP1, INSN_MACRO, 0, I1 },
2468 {"cop2", "C", 0, (int) M_COP2, INSN_MACRO, 0, I1 },
2469 {"cop3", "C", 0, (int) M_COP3, INSN_MACRO, 0, I1 },
2470 /* Conflicts with the 4650's "mul" instruction. Nobody's using the
2471 4010 any more, so move this insn out of the way. If the object
2472 format gave us more info, we could do this right. */
2473 {"addciu", "t,r,j", 0x70000000, 0xfc000000, WR_t|RD_s, 0, L1 },
2474 /* MIPS DSP ASE */
2475 {"absq_s.ph", "d,t", 0x7c000252, 0xffe007ff, WR_d|RD_t, 0, D32 },
2476 {"absq_s.pw", "d,t", 0x7c000456, 0xffe007ff, WR_d|RD_t, 0, D64 },
2477 {"absq_s.qh", "d,t", 0x7c000256, 0xffe007ff, WR_d|RD_t, 0, D64 },
2478 {"absq_s.w", "d,t", 0x7c000452, 0xffe007ff, WR_d|RD_t, 0, D32 },
2479 {"addq.ph", "d,s,t", 0x7c000290, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2480 {"addq.pw", "d,s,t", 0x7c000494, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2481 {"addq.qh", "d,s,t", 0x7c000294, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2482 {"addq_s.ph", "d,s,t", 0x7c000390, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2483 {"addq_s.pw", "d,s,t", 0x7c000594, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2484 {"addq_s.qh", "d,s,t", 0x7c000394, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2485 {"addq_s.w", "d,s,t", 0x7c000590, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2486 {"addsc", "d,s,t", 0x7c000410, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2487 {"addu.ob", "d,s,t", 0x7c000014, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2488 {"addu.qb", "d,s,t", 0x7c000010, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2489 {"addu_s.ob", "d,s,t", 0x7c000114, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2490 {"addu_s.qb", "d,s,t", 0x7c000110, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2491 {"addwc", "d,s,t", 0x7c000450, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2492 {"bitrev", "d,t", 0x7c0006d2, 0xffe007ff, WR_d|RD_t, 0, D32 },
2493 {"bposge32", "p", 0x041c0000, 0xffff0000, CBD, 0, D32 },
2494 {"bposge64", "p", 0x041d0000, 0xffff0000, CBD, 0, D64 },
2495 {"cmp.eq.ph", "s,t", 0x7c000211, 0xfc00ffff, RD_s|RD_t, 0, D32 },
2496 {"cmp.eq.pw", "s,t", 0x7c000415, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2497 {"cmp.eq.qh", "s,t", 0x7c000215, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2498 {"cmpgu.eq.ob", "d,s,t", 0x7c000115, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2499 {"cmpgu.eq.qb", "d,s,t", 0x7c000111, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2500 {"cmpgu.le.ob", "d,s,t", 0x7c000195, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2501 {"cmpgu.le.qb", "d,s,t", 0x7c000191, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2502 {"cmpgu.lt.ob", "d,s,t", 0x7c000155, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2503 {"cmpgu.lt.qb", "d,s,t", 0x7c000151, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2504 {"cmp.le.ph", "s,t", 0x7c000291, 0xfc00ffff, RD_s|RD_t, 0, D32 },
2505 {"cmp.le.pw", "s,t", 0x7c000495, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2506 {"cmp.le.qh", "s,t", 0x7c000295, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2507 {"cmp.lt.ph", "s,t", 0x7c000251, 0xfc00ffff, RD_s|RD_t, 0, D32 },
2508 {"cmp.lt.pw", "s,t", 0x7c000455, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2509 {"cmp.lt.qh", "s,t", 0x7c000255, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2510 {"cmpu.eq.ob", "s,t", 0x7c000015, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2511 {"cmpu.eq.qb", "s,t", 0x7c000011, 0xfc00ffff, RD_s|RD_t, 0, D32 },
2512 {"cmpu.le.ob", "s,t", 0x7c000095, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2513 {"cmpu.le.qb", "s,t", 0x7c000091, 0xfc00ffff, RD_s|RD_t, 0, D32 },
2514 {"cmpu.lt.ob", "s,t", 0x7c000055, 0xfc00ffff, RD_s|RD_t, 0, D64 },
2515 {"cmpu.lt.qb", "s,t", 0x7c000051, 0xfc00ffff, RD_s|RD_t, 0, D32 },
2516 {"dextpdp", "t,7,6", 0x7c0002bc, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D64 },
2517 {"dextpdpv", "t,7,s", 0x7c0002fc, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D64 },
2518 {"dextp", "t,7,6", 0x7c0000bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2519 {"dextpv", "t,7,s", 0x7c0000fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2520 {"dextr.l", "t,7,6", 0x7c00043c, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2521 {"dextr_r.l", "t,7,6", 0x7c00053c, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2522 {"dextr_rs.l", "t,7,6", 0x7c0005bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2523 {"dextr_rs.w", "t,7,6", 0x7c0001bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2524 {"dextr_r.w", "t,7,6", 0x7c00013c, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2525 {"dextr_s.h", "t,7,6", 0x7c0003bc, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2526 {"dextrv.l", "t,7,s", 0x7c00047c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2527 {"dextrv_r.l", "t,7,s", 0x7c00057c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2528 {"dextrv_rs.l", "t,7,s", 0x7c0005fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2529 {"dextrv_rs.w", "t,7,s", 0x7c0001fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2530 {"dextrv_r.w", "t,7,s", 0x7c00017c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2531 {"dextrv_s.h", "t,7,s", 0x7c0003fc, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2532 {"dextrv.w", "t,7,s", 0x7c00007c, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D64 },
2533 {"dextr.w", "t,7,6", 0x7c00003c, 0xfc00e7ff, WR_t|RD_a, 0, D64 },
2534 {"dinsv", "t,s", 0x7c00000d, 0xfc00ffff, WR_t|RD_s, 0, D64 },
2535 {"dmadd", "7,s,t", 0x7c000674, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2536 {"dmaddu", "7,s,t", 0x7c000774, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2537 {"dmsub", "7,s,t", 0x7c0006f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2538 {"dmsubu", "7,s,t", 0x7c0007f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2539 {"dmthlip", "s,7", 0x7c0007fc, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D64 },
2540 {"dpaq_sa.l.pw", "7,s,t", 0x7c000334, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2541 {"dpaq_sa.l.w", "7,s,t", 0x7c000330, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2542 {"dpaq_s.w.ph", "7,s,t", 0x7c000130, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2543 {"dpaq_s.w.qh", "7,s,t", 0x7c000134, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2544 {"dpau.h.obl", "7,s,t", 0x7c0000f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2545 {"dpau.h.obr", "7,s,t", 0x7c0001f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2546 {"dpau.h.qbl", "7,s,t", 0x7c0000f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2547 {"dpau.h.qbr", "7,s,t", 0x7c0001f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2548 {"dpsq_sa.l.pw", "7,s,t", 0x7c000374, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2549 {"dpsq_sa.l.w", "7,s,t", 0x7c000370, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2550 {"dpsq_s.w.ph", "7,s,t", 0x7c000170, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2551 {"dpsq_s.w.qh", "7,s,t", 0x7c000174, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2552 {"dpsu.h.obl", "7,s,t", 0x7c0002f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2553 {"dpsu.h.obr", "7,s,t", 0x7c0003f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2554 {"dpsu.h.qbl", "7,s,t", 0x7c0002f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2555 {"dpsu.h.qbr", "7,s,t", 0x7c0003f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2556 {"dshilo", "7,:", 0x7c0006bc, 0xfc07e7ff, MOD_a, 0, D64 },
2557 {"dshilov", "7,s", 0x7c0006fc, 0xfc1fe7ff, MOD_a|RD_s, 0, D64 },
2558 {"extpdp", "t,7,6", 0x7c0002b8, 0xfc00e7ff, WR_t|RD_a|DSP_VOLA, 0, D32 },
2559 {"extpdpv", "t,7,s", 0x7c0002f8, 0xfc00e7ff, WR_t|RD_a|RD_s|DSP_VOLA, 0, D32 },
2560 {"extp", "t,7,6", 0x7c0000b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 },
2561 {"extpv", "t,7,s", 0x7c0000f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 },
2562 {"extr_rs.w", "t,7,6", 0x7c0001b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 },
2563 {"extr_r.w", "t,7,6", 0x7c000138, 0xfc00e7ff, WR_t|RD_a, 0, D32 },
2564 {"extr_s.h", "t,7,6", 0x7c0003b8, 0xfc00e7ff, WR_t|RD_a, 0, D32 },
2565 {"extrv_rs.w", "t,7,s", 0x7c0001f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 },
2566 {"extrv_r.w", "t,7,s", 0x7c000178, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 },
2567 {"extrv_s.h", "t,7,s", 0x7c0003f8, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 },
2568 {"extrv.w", "t,7,s", 0x7c000078, 0xfc00e7ff, WR_t|RD_a|RD_s, 0, D32 },
2569 {"extr.w", "t,7,6", 0x7c000038, 0xfc00e7ff, WR_t|RD_a, 0, D32 },
2570 {"insv", "t,s", 0x7c00000c, 0xfc00ffff, WR_t|RD_s, 0, D32 },
2571 {"lbux", "d,t(b)", 0x7c00018a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 },
2572 {"ldx", "d,t(b)", 0x7c00020a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D64 },
2573 {"lhx", "d,t(b)", 0x7c00010a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 },
2574 {"lwx", "d,t(b)", 0x7c00000a, 0xfc0007ff, LDD|WR_d|RD_t|RD_b, 0, D32 },
2575 {"maq_sa.w.phl", "7,s,t", 0x7c000430, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2576 {"maq_sa.w.phr", "7,s,t", 0x7c0004b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2577 {"maq_sa.w.qhll", "7,s,t", 0x7c000434, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2578 {"maq_sa.w.qhlr", "7,s,t", 0x7c000474, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2579 {"maq_sa.w.qhrl", "7,s,t", 0x7c0004b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2580 {"maq_sa.w.qhrr", "7,s,t", 0x7c0004f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2581 {"maq_s.l.pwl", "7,s,t", 0x7c000734, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2582 {"maq_s.l.pwr", "7,s,t", 0x7c0007b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2583 {"maq_s.w.phl", "7,s,t", 0x7c000530, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2584 {"maq_s.w.phr", "7,s,t", 0x7c0005b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2585 {"maq_s.w.qhll", "7,s,t", 0x7c000534, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2586 {"maq_s.w.qhlr", "7,s,t", 0x7c000574, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2587 {"maq_s.w.qhrl", "7,s,t", 0x7c0005b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2588 {"maq_s.w.qhrr", "7,s,t", 0x7c0005f4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2589 {"modsub", "d,s,t", 0x7c000490, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2590 {"mthlip", "s,7", 0x7c0007f8, 0xfc1fe7ff, RD_s|MOD_a|DSP_VOLA, 0, D32 },
2591 {"muleq_s.pw.qhl", "d,s,t", 0x7c000714, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 },
2592 {"muleq_s.pw.qhr", "d,s,t", 0x7c000754, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 },
2593 {"muleq_s.w.phl", "d,s,t", 0x7c000710, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
2594 {"muleq_s.w.phr", "d,s,t", 0x7c000750, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
2595 {"muleu_s.ph.qbl", "d,s,t", 0x7c000190, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
2596 {"muleu_s.ph.qbr", "d,s,t", 0x7c0001d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
2597 {"muleu_s.qh.obl", "d,s,t", 0x7c000194, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 },
2598 {"muleu_s.qh.obr", "d,s,t", 0x7c0001d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 },
2599 {"mulq_rs.ph", "d,s,t", 0x7c0007d0, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D32 },
2600 {"mulq_rs.qh", "d,s,t", 0x7c0007d4, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D64 },
2601 {"mulsaq_s.l.pw", "7,s,t", 0x7c0003b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2602 {"mulsaq_s.w.ph", "7,s,t", 0x7c0001b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D32 },
2603 {"mulsaq_s.w.qh", "7,s,t", 0x7c0001b4, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D64 },
2604 {"packrl.ph", "d,s,t", 0x7c000391, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2605 {"packrl.pw", "d,s,t", 0x7c000395, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2606 {"pick.ob", "d,s,t", 0x7c0000d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2607 {"pick.ph", "d,s,t", 0x7c0002d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2608 {"pick.pw", "d,s,t", 0x7c0004d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2609 {"pick.qb", "d,s,t", 0x7c0000d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2610 {"pick.qh", "d,s,t", 0x7c0002d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2611 {"preceq.pw.qhla", "d,t", 0x7c000396, 0xffe007ff, WR_d|RD_t, 0, D64 },
2612 {"preceq.pw.qhl", "d,t", 0x7c000316, 0xffe007ff, WR_d|RD_t, 0, D64 },
2613 {"preceq.pw.qhra", "d,t", 0x7c0003d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
2614 {"preceq.pw.qhr", "d,t", 0x7c000356, 0xffe007ff, WR_d|RD_t, 0, D64 },
2615 {"preceq.s.l.pwl", "d,t", 0x7c000516, 0xffe007ff, WR_d|RD_t, 0, D64 },
2616 {"preceq.s.l.pwr", "d,t", 0x7c000556, 0xffe007ff, WR_d|RD_t, 0, D64 },
2617 {"precequ.ph.qbla", "d,t", 0x7c000192, 0xffe007ff, WR_d|RD_t, 0, D32 },
2618 {"precequ.ph.qbl", "d,t", 0x7c000112, 0xffe007ff, WR_d|RD_t, 0, D32 },
2619 {"precequ.ph.qbra", "d,t", 0x7c0001d2, 0xffe007ff, WR_d|RD_t, 0, D32 },
2620 {"precequ.ph.qbr", "d,t", 0x7c000152, 0xffe007ff, WR_d|RD_t, 0, D32 },
2621 {"precequ.pw.qhla", "d,t", 0x7c000196, 0xffe007ff, WR_d|RD_t, 0, D64 },
2622 {"precequ.pw.qhl", "d,t", 0x7c000116, 0xffe007ff, WR_d|RD_t, 0, D64 },
2623 {"precequ.pw.qhra", "d,t", 0x7c0001d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
2624 {"precequ.pw.qhr", "d,t", 0x7c000156, 0xffe007ff, WR_d|RD_t, 0, D64 },
2625 {"preceq.w.phl", "d,t", 0x7c000312, 0xffe007ff, WR_d|RD_t, 0, D32 },
2626 {"preceq.w.phr", "d,t", 0x7c000352, 0xffe007ff, WR_d|RD_t, 0, D32 },
2627 {"preceu.ph.qbla", "d,t", 0x7c000792, 0xffe007ff, WR_d|RD_t, 0, D32 },
2628 {"preceu.ph.qbl", "d,t", 0x7c000712, 0xffe007ff, WR_d|RD_t, 0, D32 },
2629 {"preceu.ph.qbra", "d,t", 0x7c0007d2, 0xffe007ff, WR_d|RD_t, 0, D32 },
2630 {"preceu.ph.qbr", "d,t", 0x7c000752, 0xffe007ff, WR_d|RD_t, 0, D32 },
2631 {"preceu.qh.obla", "d,t", 0x7c000796, 0xffe007ff, WR_d|RD_t, 0, D64 },
2632 {"preceu.qh.obl", "d,t", 0x7c000716, 0xffe007ff, WR_d|RD_t, 0, D64 },
2633 {"preceu.qh.obra", "d,t", 0x7c0007d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
2634 {"preceu.qh.obr", "d,t", 0x7c000756, 0xffe007ff, WR_d|RD_t, 0, D64 },
2635 {"precrq.ob.qh", "d,s,t", 0x7c000315, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2636 {"precrq.ph.w", "d,s,t", 0x7c000511, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2637 {"precrq.pw.l", "d,s,t", 0x7c000715, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2638 {"precrq.qb.ph", "d,s,t", 0x7c000311, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2639 {"precrq.qh.pw", "d,s,t", 0x7c000515, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2640 {"precrq_rs.ph.w", "d,s,t", 0x7c000551, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2641 {"precrq_rs.qh.pw", "d,s,t", 0x7c000555, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2642 {"precrqu_s.ob.qh", "d,s,t", 0x7c0003d5, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2643 {"precrqu_s.qb.ph", "d,s,t", 0x7c0003d1, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2644 {"raddu.l.ob", "d,s", 0x7c000514, 0xfc1f07ff, WR_d|RD_s, 0, D64 },
2645 {"raddu.w.qb", "d,s", 0x7c000510, 0xfc1f07ff, WR_d|RD_s, 0, D32 },
2646 {"rddsp", "d", 0x7fff04b8, 0xffff07ff, WR_d, 0, D32 },
2647 {"rddsp", "d,'", 0x7c0004b8, 0xffc007ff, WR_d, 0, D32 },
2648 {"repl.ob", "d,5", 0x7c000096, 0xff0007ff, WR_d, 0, D64 },
2649 {"repl.ph", "d,@", 0x7c000292, 0xfc0007ff, WR_d, 0, D32 },
2650 {"repl.pw", "d,@", 0x7c000496, 0xfc0007ff, WR_d, 0, D64 },
2651 {"repl.qb", "d,5", 0x7c000092, 0xff0007ff, WR_d, 0, D32 },
2652 {"repl.qh", "d,@", 0x7c000296, 0xfc0007ff, WR_d, 0, D64 },
2653 {"replv.ob", "d,t", 0x7c0000d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
2654 {"replv.ph", "d,t", 0x7c0002d2, 0xffe007ff, WR_d|RD_t, 0, D32 },
2655 {"replv.pw", "d,t", 0x7c0004d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
2656 {"replv.qb", "d,t", 0x7c0000d2, 0xffe007ff, WR_d|RD_t, 0, D32 },
2657 {"replv.qh", "d,t", 0x7c0002d6, 0xffe007ff, WR_d|RD_t, 0, D64 },
2658 {"shilo", "7,0", 0x7c0006b8, 0xfc0fe7ff, MOD_a, 0, D32 },
2659 {"shilov", "7,s", 0x7c0006f8, 0xfc1fe7ff, MOD_a|RD_s, 0, D32 },
2660 {"shll.ob", "d,t,3", 0x7c000017, 0xff0007ff, WR_d|RD_t, 0, D64 },
2661 {"shll.ph", "d,t,4", 0x7c000213, 0xfe0007ff, WR_d|RD_t, 0, D32 },
2662 {"shll.pw", "d,t,6", 0x7c000417, 0xfc0007ff, WR_d|RD_t, 0, D64 },
2663 {"shll.qb", "d,t,3", 0x7c000013, 0xff0007ff, WR_d|RD_t, 0, D32 },
2664 {"shll.qh", "d,t,4", 0x7c000217, 0xfe0007ff, WR_d|RD_t, 0, D64 },
2665 {"shll_s.ph", "d,t,4", 0x7c000313, 0xfe0007ff, WR_d|RD_t, 0, D32 },
2666 {"shll_s.pw", "d,t,6", 0x7c000517, 0xfc0007ff, WR_d|RD_t, 0, D64 },
2667 {"shll_s.qh", "d,t,4", 0x7c000317, 0xfe0007ff, WR_d|RD_t, 0, D64 },
2668 {"shll_s.w", "d,t,6", 0x7c000513, 0xfc0007ff, WR_d|RD_t, 0, D32 },
2669 {"shllv.ob", "d,t,s", 0x7c000097, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2670 {"shllv.ph", "d,t,s", 0x7c000293, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2671 {"shllv.pw", "d,t,s", 0x7c000497, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2672 {"shllv.qb", "d,t,s", 0x7c000093, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2673 {"shllv.qh", "d,t,s", 0x7c000297, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2674 {"shllv_s.ph", "d,t,s", 0x7c000393, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2675 {"shllv_s.pw", "d,t,s", 0x7c000597, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2676 {"shllv_s.qh", "d,t,s", 0x7c000397, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2677 {"shllv_s.w", "d,t,s", 0x7c000593, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2678 {"shra.ph", "d,t,4", 0x7c000253, 0xfe0007ff, WR_d|RD_t, 0, D32 },
2679 {"shra.pw", "d,t,6", 0x7c000457, 0xfc0007ff, WR_d|RD_t, 0, D64 },
2680 {"shra.qh", "d,t,4", 0x7c000257, 0xfe0007ff, WR_d|RD_t, 0, D64 },
2681 {"shra_r.ph", "d,t,4", 0x7c000353, 0xfe0007ff, WR_d|RD_t, 0, D32 },
2682 {"shra_r.pw", "d,t,6", 0x7c000557, 0xfc0007ff, WR_d|RD_t, 0, D64 },
2683 {"shra_r.qh", "d,t,4", 0x7c000357, 0xfe0007ff, WR_d|RD_t, 0, D64 },
2684 {"shra_r.w", "d,t,6", 0x7c000553, 0xfc0007ff, WR_d|RD_t, 0, D32 },
2685 {"shrav.ph", "d,t,s", 0x7c0002d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2686 {"shrav.pw", "d,t,s", 0x7c0004d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2687 {"shrav.qh", "d,t,s", 0x7c0002d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2688 {"shrav_r.ph", "d,t,s", 0x7c0003d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2689 {"shrav_r.pw", "d,t,s", 0x7c0005d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2690 {"shrav_r.qh", "d,t,s", 0x7c0003d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2691 {"shrav_r.w", "d,t,s", 0x7c0005d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2692 {"shrl.ob", "d,t,3", 0x7c000057, 0xff0007ff, WR_d|RD_t, 0, D64 },
2693 {"shrl.qb", "d,t,3", 0x7c000053, 0xff0007ff, WR_d|RD_t, 0, D32 },
2694 {"shrlv.ob", "d,t,s", 0x7c0000d7, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2695 {"shrlv.qb", "d,t,s", 0x7c0000d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2696 {"subq.ph", "d,s,t", 0x7c0002d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2697 {"subq.pw", "d,s,t", 0x7c0004d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2698 {"subq.qh", "d,s,t", 0x7c0002d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2699 {"subq_s.ph", "d,s,t", 0x7c0003d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2700 {"subq_s.pw", "d,s,t", 0x7c0005d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2701 {"subq_s.qh", "d,s,t", 0x7c0003d4, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2702 {"subq_s.w", "d,s,t", 0x7c0005d0, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2703 {"subu.ob", "d,s,t", 0x7c000054, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2704 {"subu.qb", "d,s,t", 0x7c000050, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2705 {"subu_s.ob", "d,s,t", 0x7c000154, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D64 },
2706 {"subu_s.qb", "d,s,t", 0x7c000150, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D32 },
2707 {"wrdsp", "s", 0x7c1ffcf8, 0xfc1fffff, RD_s|DSP_VOLA, 0, D32 },
2708 {"wrdsp", "s,8", 0x7c0004f8, 0xfc1e07ff, RD_s|DSP_VOLA, 0, D32 },
2709 /* MIPS DSP ASE Rev2 */
2710 {"absq_s.qb", "d,t", 0x7c000052, 0xffe007ff, WR_d|RD_t, 0, D33 },
2711 {"addu.ph", "d,s,t", 0x7c000210, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2712 {"addu_s.ph", "d,s,t", 0x7c000310, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2713 {"adduh.qb", "d,s,t", 0x7c000018, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2714 {"adduh_r.qb", "d,s,t", 0x7c000098, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2715 {"append", "t,s,h", 0x7c000031, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
2716 {"balign", "t,s,I", 0, (int) M_BALIGN, INSN_MACRO, 0, D33 },
2717 {"balign", "t,s,2", 0x7c000431, 0xfc00e7ff, WR_t|RD_t|RD_s, 0, D33 },
2718 {"cmpgdu.eq.qb", "d,s,t", 0x7c000611, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2719 {"cmpgdu.lt.qb", "d,s,t", 0x7c000651, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2720 {"cmpgdu.le.qb", "d,s,t", 0x7c000691, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2721 {"dpa.w.ph", "7,s,t", 0x7c000030, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2722 {"dps.w.ph", "7,s,t", 0x7c000070, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2723 {"mul.ph", "d,s,t", 0x7c000318, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
2724 {"mul_s.ph", "d,s,t", 0x7c000398, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
2725 {"mulq_rs.w", "d,s,t", 0x7c0005d8, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
2726 {"mulq_s.ph", "d,s,t", 0x7c000790, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
2727 {"mulq_s.w", "d,s,t", 0x7c000598, 0xfc0007ff, WR_d|RD_s|RD_t|WR_HILO, 0, D33 },
2728 {"mulsa.w.ph", "7,s,t", 0x7c0000b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2729 {"precr.qb.ph", "d,s,t", 0x7c000351, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2730 {"precr_sra.ph.w", "t,s,h", 0x7c000791, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
2731 {"precr_sra_r.ph.w", "t,s,h", 0x7c0007d1, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
2732 {"prepend", "t,s,h", 0x7c000071, 0xfc0007ff, WR_t|RD_t|RD_s, 0, D33 },
2733 {"shra.qb", "d,t,3", 0x7c000113, 0xff0007ff, WR_d|RD_t, 0, D33 },
2734 {"shra_r.qb", "d,t,3", 0x7c000153, 0xff0007ff, WR_d|RD_t, 0, D33 },
2735 {"shrav.qb", "d,t,s", 0x7c000193, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2736 {"shrav_r.qb", "d,t,s", 0x7c0001d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2737 {"shrl.ph", "d,t,4", 0x7c000653, 0xfe0007ff, WR_d|RD_t, 0, D33 },
2738 {"shrlv.ph", "d,t,s", 0x7c0006d3, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2739 {"subu.ph", "d,s,t", 0x7c000250, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2740 {"subu_s.ph", "d,s,t", 0x7c000350, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2741 {"subuh.qb", "d,s,t", 0x7c000058, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2742 {"subuh_r.qb", "d,s,t", 0x7c0000d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2743 {"addqh.ph", "d,s,t", 0x7c000218, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2744 {"addqh_r.ph", "d,s,t", 0x7c000298, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2745 {"addqh.w", "d,s,t", 0x7c000418, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2746 {"addqh_r.w", "d,s,t", 0x7c000498, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2747 {"subqh.ph", "d,s,t", 0x7c000258, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2748 {"subqh_r.ph", "d,s,t", 0x7c0002d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2749 {"subqh.w", "d,s,t", 0x7c000458, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2750 {"subqh_r.w", "d,s,t", 0x7c0004d8, 0xfc0007ff, WR_d|RD_s|RD_t, 0, D33 },
2751 {"dpax.w.ph", "7,s,t", 0x7c000230, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2752 {"dpsx.w.ph", "7,s,t", 0x7c000270, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2753 {"dpaqx_s.w.ph", "7,s,t", 0x7c000630, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2754 {"dpaqx_sa.w.ph", "7,s,t", 0x7c0006b0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2755 {"dpsqx_s.w.ph", "7,s,t", 0x7c000670, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2756 {"dpsqx_sa.w.ph", "7,s,t", 0x7c0006f0, 0xfc00e7ff, MOD_a|RD_s|RD_t, 0, D33 },
2757 /* Move bc0* after mftr and mttr to avoid opcode collision. */
2758 {"bc0f", "p", 0x41000000, 0xffff0000, CBD|RD_CC, 0, I1 },
2759 {"bc0fl", "p", 0x41020000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
2760 {"bc0t", "p", 0x41010000, 0xffff0000, CBD|RD_CC, 0, I1 },
2761 {"bc0tl", "p", 0x41030000, 0xffff0000, CBL|RD_CC, 0, I2|T3 },
2762 /* ST Microelectronics Loongson-2E and -2F. */
2763 {"mult.g", "d,s,t", 0x7c000018, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
2764 {"mult.g", "d,s,t", 0x70000010, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
2765 {"multu.g", "d,s,t", 0x7c000019, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
2766 {"multu.g", "d,s,t", 0x70000012, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
2767 {"dmult.g", "d,s,t", 0x7c00001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
2768 {"dmult.g", "d,s,t", 0x70000011, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
2769 {"dmultu.g", "d,s,t", 0x7c00001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
2770 {"dmultu.g", "d,s,t", 0x70000013, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
2771 {"div.g", "d,s,t", 0x7c00001a, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
2772 {"div.g", "d,s,t", 0x70000014, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
2773 {"divu.g", "d,s,t", 0x7c00001b, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
2774 {"divu.g", "d,s,t", 0x70000016, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
2775 {"ddiv.g", "d,s,t", 0x7c00001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
2776 {"ddiv.g", "d,s,t", 0x70000015, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
2777 {"ddivu.g", "d,s,t", 0x7c00001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
2778 {"ddivu.g", "d,s,t", 0x70000017, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
2779 {"mod.g", "d,s,t", 0x7c000022, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
2780 {"mod.g", "d,s,t", 0x7000001c, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
2781 {"modu.g", "d,s,t", 0x7c000023, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
2782 {"modu.g", "d,s,t", 0x7000001e, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
2783 {"dmod.g", "d,s,t", 0x7c000026, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
2784 {"dmod.g", "d,s,t", 0x7000001d, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
2785 {"dmodu.g", "d,s,t", 0x7c000027, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2E },
2786 {"dmodu.g", "d,s,t", 0x7000001f, 0xfc0007ff, RD_s|RD_t|WR_d, 0, IL2F },
2787 };
2788
2789 #define MIPS_NUM_OPCODES \
2790 ((sizeof mips_builtin_opcodes) / (sizeof (mips_builtin_opcodes[0])))
2791 const int bfd_mips_num_builtin_opcodes = MIPS_NUM_OPCODES;
2792
2793 /* const removed from the following to allow for dynamic extensions to the
2794 * built-in instruction set. */
2795 struct mips_opcode *mips_opcodes =
2796 (struct mips_opcode *) mips_builtin_opcodes;
2797 int bfd_mips_num_opcodes = MIPS_NUM_OPCODES;
2798 #undef MIPS_NUM_OPCODES
2799
2800 /* Mips instructions are at maximum this many bytes long. */
2801 #define INSNLEN 4
2802
2803 \f
2804 /* FIXME: These should be shared with gdb somehow. */
2805
2806 struct mips_cp0sel_name
2807 {
2808 unsigned int cp0reg;
2809 unsigned int sel;
2810 const char * const name;
2811 };
2812
2813 /* The mips16 registers. */
2814 static const unsigned int mips16_to_32_reg_map[] =
2815 {
2816 16, 17, 2, 3, 4, 5, 6, 7
2817 };
2818
2819 #define mips16_reg_names(rn) mips_gpr_names[mips16_to_32_reg_map[rn]]
2820
2821
2822 static const char * const mips_gpr_names_numeric[32] =
2823 {
2824 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
2825 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
2826 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
2827 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
2828 };
2829
2830 static const char * const mips_gpr_names_oldabi[32] =
2831 {
2832 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
2833 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
2834 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
2835 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
2836 };
2837
2838 static const char * const mips_gpr_names_newabi[32] =
2839 {
2840 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
2841 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
2842 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
2843 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
2844 };
2845
2846 static const char * const mips_fpr_names_numeric[32] =
2847 {
2848 "$f0", "$f1", "$f2", "$f3", "$f4", "$f5", "$f6", "$f7",
2849 "$f8", "$f9", "$f10", "$f11", "$f12", "$f13", "$f14", "$f15",
2850 "$f16", "$f17", "$f18", "$f19", "$f20", "$f21", "$f22", "$f23",
2851 "$f24", "$f25", "$f26", "$f27", "$f28", "$f29", "$f30", "$f31"
2852 };
2853
2854 static const char * const mips_fpr_names_32[32] =
2855 {
2856 "fv0", "fv0f", "fv1", "fv1f", "ft0", "ft0f", "ft1", "ft1f",
2857 "ft2", "ft2f", "ft3", "ft3f", "fa0", "fa0f", "fa1", "fa1f",
2858 "ft4", "ft4f", "ft5", "ft5f", "fs0", "fs0f", "fs1", "fs1f",
2859 "fs2", "fs2f", "fs3", "fs3f", "fs4", "fs4f", "fs5", "fs5f"
2860 };
2861
2862 static const char * const mips_fpr_names_n32[32] =
2863 {
2864 "fv0", "ft14", "fv1", "ft15", "ft0", "ft1", "ft2", "ft3",
2865 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
2866 "fa4", "fa5", "fa6", "fa7", "fs0", "ft8", "fs1", "ft9",
2867 "fs2", "ft10", "fs3", "ft11", "fs4", "ft12", "fs5", "ft13"
2868 };
2869
2870 static const char * const mips_fpr_names_64[32] =
2871 {
2872 "fv0", "ft12", "fv1", "ft13", "ft0", "ft1", "ft2", "ft3",
2873 "ft4", "ft5", "ft6", "ft7", "fa0", "fa1", "fa2", "fa3",
2874 "fa4", "fa5", "fa6", "fa7", "ft8", "ft9", "ft10", "ft11",
2875 "fs0", "fs1", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7"
2876 };
2877
2878 static const char * const mips_cp0_names_numeric[32] =
2879 {
2880 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
2881 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
2882 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
2883 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
2884 };
2885
2886 static const char * const mips_cp0_names_mips3264[32] =
2887 {
2888 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
2889 "c0_context", "c0_pagemask", "c0_wired", "$7",
2890 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
2891 "c0_status", "c0_cause", "c0_epc", "c0_prid",
2892 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
2893 "c0_xcontext", "$21", "$22", "c0_debug",
2894 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
2895 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
2896 };
2897
2898 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264[] =
2899 {
2900 { 4, 1, "c0_contextconfig" },
2901 { 0, 1, "c0_mvpcontrol" },
2902 { 0, 2, "c0_mvpconf0" },
2903 { 0, 3, "c0_mvpconf1" },
2904 { 1, 1, "c0_vpecontrol" },
2905 { 1, 2, "c0_vpeconf0" },
2906 { 1, 3, "c0_vpeconf1" },
2907 { 1, 4, "c0_yqmask" },
2908 { 1, 5, "c0_vpeschedule" },
2909 { 1, 6, "c0_vpeschefback" },
2910 { 2, 1, "c0_tcstatus" },
2911 { 2, 2, "c0_tcbind" },
2912 { 2, 3, "c0_tcrestart" },
2913 { 2, 4, "c0_tchalt" },
2914 { 2, 5, "c0_tccontext" },
2915 { 2, 6, "c0_tcschedule" },
2916 { 2, 7, "c0_tcschefback" },
2917 { 5, 1, "c0_pagegrain" },
2918 { 6, 1, "c0_srsconf0" },
2919 { 6, 2, "c0_srsconf1" },
2920 { 6, 3, "c0_srsconf2" },
2921 { 6, 4, "c0_srsconf3" },
2922 { 6, 5, "c0_srsconf4" },
2923 { 12, 1, "c0_intctl" },
2924 { 12, 2, "c0_srsctl" },
2925 { 12, 3, "c0_srsmap" },
2926 { 15, 1, "c0_ebase" },
2927 { 16, 1, "c0_config1" },
2928 { 16, 2, "c0_config2" },
2929 { 16, 3, "c0_config3" },
2930 { 18, 1, "c0_watchlo,1" },
2931 { 18, 2, "c0_watchlo,2" },
2932 { 18, 3, "c0_watchlo,3" },
2933 { 18, 4, "c0_watchlo,4" },
2934 { 18, 5, "c0_watchlo,5" },
2935 { 18, 6, "c0_watchlo,6" },
2936 { 18, 7, "c0_watchlo,7" },
2937 { 19, 1, "c0_watchhi,1" },
2938 { 19, 2, "c0_watchhi,2" },
2939 { 19, 3, "c0_watchhi,3" },
2940 { 19, 4, "c0_watchhi,4" },
2941 { 19, 5, "c0_watchhi,5" },
2942 { 19, 6, "c0_watchhi,6" },
2943 { 19, 7, "c0_watchhi,7" },
2944 { 23, 1, "c0_tracecontrol" },
2945 { 23, 2, "c0_tracecontrol2" },
2946 { 23, 3, "c0_usertracedata" },
2947 { 23, 4, "c0_tracebpc" },
2948 { 25, 1, "c0_perfcnt,1" },
2949 { 25, 2, "c0_perfcnt,2" },
2950 { 25, 3, "c0_perfcnt,3" },
2951 { 25, 4, "c0_perfcnt,4" },
2952 { 25, 5, "c0_perfcnt,5" },
2953 { 25, 6, "c0_perfcnt,6" },
2954 { 25, 7, "c0_perfcnt,7" },
2955 { 27, 1, "c0_cacheerr,1" },
2956 { 27, 2, "c0_cacheerr,2" },
2957 { 27, 3, "c0_cacheerr,3" },
2958 { 28, 1, "c0_datalo" },
2959 { 28, 2, "c0_taglo1" },
2960 { 28, 3, "c0_datalo1" },
2961 { 28, 4, "c0_taglo2" },
2962 { 28, 5, "c0_datalo2" },
2963 { 28, 6, "c0_taglo3" },
2964 { 28, 7, "c0_datalo3" },
2965 { 29, 1, "c0_datahi" },
2966 { 29, 2, "c0_taghi1" },
2967 { 29, 3, "c0_datahi1" },
2968 { 29, 4, "c0_taghi2" },
2969 { 29, 5, "c0_datahi2" },
2970 { 29, 6, "c0_taghi3" },
2971 { 29, 7, "c0_datahi3" },
2972 };
2973
2974 static const char * const mips_cp0_names_mips3264r2[32] =
2975 {
2976 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
2977 "c0_context", "c0_pagemask", "c0_wired", "c0_hwrena",
2978 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
2979 "c0_status", "c0_cause", "c0_epc", "c0_prid",
2980 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
2981 "c0_xcontext", "$21", "$22", "c0_debug",
2982 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr",
2983 "c0_taglo", "c0_taghi", "c0_errorepc", "c0_desave",
2984 };
2985
2986 static const struct mips_cp0sel_name mips_cp0sel_names_mips3264r2[] =
2987 {
2988 { 4, 1, "c0_contextconfig" },
2989 { 5, 1, "c0_pagegrain" },
2990 { 12, 1, "c0_intctl" },
2991 { 12, 2, "c0_srsctl" },
2992 { 12, 3, "c0_srsmap" },
2993 { 15, 1, "c0_ebase" },
2994 { 16, 1, "c0_config1" },
2995 { 16, 2, "c0_config2" },
2996 { 16, 3, "c0_config3" },
2997 { 18, 1, "c0_watchlo,1" },
2998 { 18, 2, "c0_watchlo,2" },
2999 { 18, 3, "c0_watchlo,3" },
3000 { 18, 4, "c0_watchlo,4" },
3001 { 18, 5, "c0_watchlo,5" },
3002 { 18, 6, "c0_watchlo,6" },
3003 { 18, 7, "c0_watchlo,7" },
3004 { 19, 1, "c0_watchhi,1" },
3005 { 19, 2, "c0_watchhi,2" },
3006 { 19, 3, "c0_watchhi,3" },
3007 { 19, 4, "c0_watchhi,4" },
3008 { 19, 5, "c0_watchhi,5" },
3009 { 19, 6, "c0_watchhi,6" },
3010 { 19, 7, "c0_watchhi,7" },
3011 { 23, 1, "c0_tracecontrol" },
3012 { 23, 2, "c0_tracecontrol2" },
3013 { 23, 3, "c0_usertracedata" },
3014 { 23, 4, "c0_tracebpc" },
3015 { 25, 1, "c0_perfcnt,1" },
3016 { 25, 2, "c0_perfcnt,2" },
3017 { 25, 3, "c0_perfcnt,3" },
3018 { 25, 4, "c0_perfcnt,4" },
3019 { 25, 5, "c0_perfcnt,5" },
3020 { 25, 6, "c0_perfcnt,6" },
3021 { 25, 7, "c0_perfcnt,7" },
3022 { 27, 1, "c0_cacheerr,1" },
3023 { 27, 2, "c0_cacheerr,2" },
3024 { 27, 3, "c0_cacheerr,3" },
3025 { 28, 1, "c0_datalo" },
3026 { 28, 2, "c0_taglo1" },
3027 { 28, 3, "c0_datalo1" },
3028 { 28, 4, "c0_taglo2" },
3029 { 28, 5, "c0_datalo2" },
3030 { 28, 6, "c0_taglo3" },
3031 { 28, 7, "c0_datalo3" },
3032 { 29, 1, "c0_datahi" },
3033 { 29, 2, "c0_taghi1" },
3034 { 29, 3, "c0_datahi1" },
3035 { 29, 4, "c0_taghi2" },
3036 { 29, 5, "c0_datahi2" },
3037 { 29, 6, "c0_taghi3" },
3038 { 29, 7, "c0_datahi3" },
3039 };
3040
3041 /* SB-1: MIPS64 (mips_cp0_names_mips3264) with minor mods. */
3042 static const char * const mips_cp0_names_sb1[32] =
3043 {
3044 "c0_index", "c0_random", "c0_entrylo0", "c0_entrylo1",
3045 "c0_context", "c0_pagemask", "c0_wired", "$7",
3046 "c0_badvaddr", "c0_count", "c0_entryhi", "c0_compare",
3047 "c0_status", "c0_cause", "c0_epc", "c0_prid",
3048 "c0_config", "c0_lladdr", "c0_watchlo", "c0_watchhi",
3049 "c0_xcontext", "$21", "$22", "c0_debug",
3050 "c0_depc", "c0_perfcnt", "c0_errctl", "c0_cacheerr_i",
3051 "c0_taglo_i", "c0_taghi_i", "c0_errorepc", "c0_desave",
3052 };
3053
3054 static const struct mips_cp0sel_name mips_cp0sel_names_sb1[] =
3055 {
3056 { 16, 1, "c0_config1" },
3057 { 18, 1, "c0_watchlo,1" },
3058 { 19, 1, "c0_watchhi,1" },
3059 { 22, 0, "c0_perftrace" },
3060 { 23, 3, "c0_edebug" },
3061 { 25, 1, "c0_perfcnt,1" },
3062 { 25, 2, "c0_perfcnt,2" },
3063 { 25, 3, "c0_perfcnt,3" },
3064 { 25, 4, "c0_perfcnt,4" },
3065 { 25, 5, "c0_perfcnt,5" },
3066 { 25, 6, "c0_perfcnt,6" },
3067 { 25, 7, "c0_perfcnt,7" },
3068 { 26, 1, "c0_buserr_pa" },
3069 { 27, 1, "c0_cacheerr_d" },
3070 { 27, 3, "c0_cacheerr_d_pa" },
3071 { 28, 1, "c0_datalo_i" },
3072 { 28, 2, "c0_taglo_d" },
3073 { 28, 3, "c0_datalo_d" },
3074 { 29, 1, "c0_datahi_i" },
3075 { 29, 2, "c0_taghi_d" },
3076 { 29, 3, "c0_datahi_d" },
3077 };
3078
3079 static const char * const mips_hwr_names_numeric[32] =
3080 {
3081 "$0", "$1", "$2", "$3", "$4", "$5", "$6", "$7",
3082 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
3083 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
3084 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
3085 };
3086
3087 static const char * const mips_hwr_names_mips3264r2[32] =
3088 {
3089 "hwr_cpunum", "hwr_synci_step", "hwr_cc", "hwr_ccres",
3090 "$4", "$5", "$6", "$7",
3091 "$8", "$9", "$10", "$11", "$12", "$13", "$14", "$15",
3092 "$16", "$17", "$18", "$19", "$20", "$21", "$22", "$23",
3093 "$24", "$25", "$26", "$27", "$28", "$29", "$30", "$31"
3094 };
3095
3096 struct mips_abi_choice
3097 {
3098 const char *name;
3099 const char * const *gpr_names;
3100 const char * const *fpr_names;
3101 };
3102
3103 static struct mips_abi_choice mips_abi_choices[] =
3104 {
3105 { "numeric", mips_gpr_names_numeric, mips_fpr_names_numeric },
3106 { "32", mips_gpr_names_oldabi, mips_fpr_names_32 },
3107 { "n32", mips_gpr_names_newabi, mips_fpr_names_n32 },
3108 { "64", mips_gpr_names_newabi, mips_fpr_names_64 },
3109 };
3110
3111 struct mips_arch_choice
3112 {
3113 const char *name;
3114 int bfd_mach_valid;
3115 unsigned long bfd_mach;
3116 int processor;
3117 int isa;
3118 const char * const *cp0_names;
3119 const struct mips_cp0sel_name *cp0sel_names;
3120 unsigned int cp0sel_names_len;
3121 const char * const *hwr_names;
3122 };
3123
3124 #define bfd_mach_mips3000 3000
3125 #define bfd_mach_mips3900 3900
3126 #define bfd_mach_mips4000 4000
3127 #define bfd_mach_mips4010 4010
3128 #define bfd_mach_mips4100 4100
3129 #define bfd_mach_mips4111 4111
3130 #define bfd_mach_mips4120 4120
3131 #define bfd_mach_mips4300 4300
3132 #define bfd_mach_mips4400 4400
3133 #define bfd_mach_mips4600 4600
3134 #define bfd_mach_mips4650 4650
3135 #define bfd_mach_mips5000 5000
3136 #define bfd_mach_mips5400 5400
3137 #define bfd_mach_mips5500 5500
3138 #define bfd_mach_mips6000 6000
3139 #define bfd_mach_mips7000 7000
3140 #define bfd_mach_mips8000 8000
3141 #define bfd_mach_mips9000 9000
3142 #define bfd_mach_mips10000 10000
3143 #define bfd_mach_mips12000 12000
3144 #define bfd_mach_mips16 16
3145 #define bfd_mach_mips5 5
3146 #define bfd_mach_mips_sb1 12310201 /* octal 'SB', 01 */
3147 #define bfd_mach_mipsisa32 32
3148 #define bfd_mach_mipsisa32r2 33
3149 #define bfd_mach_mipsisa64 64
3150 #define bfd_mach_mipsisa64r2 65
3151
3152 static const struct mips_arch_choice mips_arch_choices[] =
3153 {
3154 { "numeric", 0, 0, 0, 0,
3155 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3156
3157 { "r3000", 1, bfd_mach_mips3000, CPU_R3000, ISA_MIPS1,
3158 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3159 { "r3900", 1, bfd_mach_mips3900, CPU_R3900, ISA_MIPS1,
3160 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3161 { "r4000", 1, bfd_mach_mips4000, CPU_R4000, ISA_MIPS3,
3162 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3163 { "r4010", 1, bfd_mach_mips4010, CPU_R4010, ISA_MIPS2,
3164 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3165 { "vr4100", 1, bfd_mach_mips4100, CPU_VR4100, ISA_MIPS3,
3166 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3167 { "vr4111", 1, bfd_mach_mips4111, CPU_R4111, ISA_MIPS3,
3168 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3169 { "vr4120", 1, bfd_mach_mips4120, CPU_VR4120, ISA_MIPS3,
3170 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3171 { "r4300", 1, bfd_mach_mips4300, CPU_R4300, ISA_MIPS3,
3172 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3173 { "r4400", 1, bfd_mach_mips4400, CPU_R4400, ISA_MIPS3,
3174 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3175 { "r4600", 1, bfd_mach_mips4600, CPU_R4600, ISA_MIPS3,
3176 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3177 { "r4650", 1, bfd_mach_mips4650, CPU_R4650, ISA_MIPS3,
3178 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3179 { "r5000", 1, bfd_mach_mips5000, CPU_R5000, ISA_MIPS4,
3180 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3181 { "vr5400", 1, bfd_mach_mips5400, CPU_VR5400, ISA_MIPS4,
3182 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3183 { "vr5500", 1, bfd_mach_mips5500, CPU_VR5500, ISA_MIPS4,
3184 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3185 { "r6000", 1, bfd_mach_mips6000, CPU_R6000, ISA_MIPS2,
3186 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3187 { "rm7000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
3188 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3189 { "rm9000", 1, bfd_mach_mips7000, CPU_RM7000, ISA_MIPS4,
3190 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3191 { "r8000", 1, bfd_mach_mips8000, CPU_R8000, ISA_MIPS4,
3192 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3193 { "r10000", 1, bfd_mach_mips10000, CPU_R10000, ISA_MIPS4,
3194 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3195 { "r12000", 1, bfd_mach_mips12000, CPU_R12000, ISA_MIPS4,
3196 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3197 { "mips5", 1, bfd_mach_mips5, CPU_MIPS5, ISA_MIPS5,
3198 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3199
3200 /* For stock MIPS32, disassemble all applicable MIPS-specified ASEs.
3201 Note that MIPS-3D and MDMX are not applicable to MIPS32. (See
3202 _MIPS32 Architecture For Programmers Volume I: Introduction to the
3203 MIPS32 Architecture_ (MIPS Document Number MD00082, Revision 0.95),
3204 page 1. */
3205 { "mips32", 1, bfd_mach_mipsisa32, CPU_MIPS32,
3206 ISA_MIPS32 | INSN_MIPS16 | INSN_SMARTMIPS,
3207 mips_cp0_names_mips3264,
3208 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
3209 mips_hwr_names_numeric },
3210
3211 { "mips32r2", 1, bfd_mach_mipsisa32r2, CPU_MIPS32R2,
3212 (ISA_MIPS32R2 | INSN_MIPS16 | INSN_SMARTMIPS | INSN_DSP | INSN_DSPR2
3213 | INSN_MIPS3D | INSN_MT),
3214 mips_cp0_names_mips3264r2,
3215 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
3216 mips_hwr_names_mips3264r2 },
3217
3218 /* For stock MIPS64, disassemble all applicable MIPS-specified ASEs. */
3219 { "mips64", 1, bfd_mach_mipsisa64, CPU_MIPS64,
3220 ISA_MIPS64 | INSN_MIPS16 | INSN_MIPS3D | INSN_MDMX,
3221 mips_cp0_names_mips3264,
3222 mips_cp0sel_names_mips3264, ARRAY_SIZE (mips_cp0sel_names_mips3264),
3223 mips_hwr_names_numeric },
3224
3225 { "mips64r2", 1, bfd_mach_mipsisa64r2, CPU_MIPS64R2,
3226 (ISA_MIPS64R2 | INSN_MIPS16 | INSN_MIPS3D | INSN_DSP | INSN_DSPR2
3227 | INSN_DSP64 | INSN_MT | INSN_MDMX),
3228 mips_cp0_names_mips3264r2,
3229 mips_cp0sel_names_mips3264r2, ARRAY_SIZE (mips_cp0sel_names_mips3264r2),
3230 mips_hwr_names_mips3264r2 },
3231
3232 { "sb1", 1, bfd_mach_mips_sb1, CPU_SB1,
3233 ISA_MIPS64 | INSN_MIPS3D | INSN_SB1,
3234 mips_cp0_names_sb1,
3235 mips_cp0sel_names_sb1, ARRAY_SIZE (mips_cp0sel_names_sb1),
3236 mips_hwr_names_numeric },
3237
3238 /* This entry, mips16, is here only for ISA/processor selection; do
3239 not print its name. */
3240 { "", 1, bfd_mach_mips16, CPU_MIPS16, ISA_MIPS3 | INSN_MIPS16,
3241 mips_cp0_names_numeric, NULL, 0, mips_hwr_names_numeric },
3242 };
3243
3244 /* ISA and processor type to disassemble for, and register names to use.
3245 set_default_mips_dis_options and parse_mips_dis_options fill in these
3246 values. */
3247 static int mips_processor;
3248 static int mips_isa;
3249 static const char * const *mips_gpr_names;
3250 static const char * const *mips_fpr_names;
3251 static const char * const *mips_cp0_names;
3252 static const struct mips_cp0sel_name *mips_cp0sel_names;
3253 static int mips_cp0sel_names_len;
3254 static const char * const *mips_hwr_names;
3255
3256 /* Other options */
3257 static int no_aliases; /* If set disassemble as most general inst. */
3258 \f
3259 static const struct mips_abi_choice *
3260 choose_abi_by_name (const char *name, unsigned int namelen)
3261 {
3262 const struct mips_abi_choice *c;
3263 unsigned int i;
3264
3265 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_abi_choices) && c == NULL; i++)
3266 if (strncmp (mips_abi_choices[i].name, name, namelen) == 0
3267 && strlen (mips_abi_choices[i].name) == namelen)
3268 c = &mips_abi_choices[i];
3269
3270 return c;
3271 }
3272
3273 static const struct mips_arch_choice *
3274 choose_arch_by_name (const char *name, unsigned int namelen)
3275 {
3276 const struct mips_arch_choice *c = NULL;
3277 unsigned int i;
3278
3279 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
3280 if (strncmp (mips_arch_choices[i].name, name, namelen) == 0
3281 && strlen (mips_arch_choices[i].name) == namelen)
3282 c = &mips_arch_choices[i];
3283
3284 return c;
3285 }
3286
3287 static const struct mips_arch_choice *
3288 choose_arch_by_number (unsigned long mach)
3289 {
3290 static unsigned long hint_bfd_mach;
3291 static const struct mips_arch_choice *hint_arch_choice;
3292 const struct mips_arch_choice *c;
3293 unsigned int i;
3294
3295 /* We optimize this because even if the user specifies no
3296 flags, this will be done for every instruction! */
3297 if (hint_bfd_mach == mach
3298 && hint_arch_choice != NULL
3299 && hint_arch_choice->bfd_mach == hint_bfd_mach)
3300 return hint_arch_choice;
3301
3302 for (i = 0, c = NULL; i < ARRAY_SIZE (mips_arch_choices) && c == NULL; i++)
3303 {
3304 if (mips_arch_choices[i].bfd_mach_valid
3305 && mips_arch_choices[i].bfd_mach == mach)
3306 {
3307 c = &mips_arch_choices[i];
3308 hint_bfd_mach = mach;
3309 hint_arch_choice = c;
3310 }
3311 }
3312 return c;
3313 }
3314
3315 static void
3316 set_default_mips_dis_options (struct disassemble_info *info)
3317 {
3318 const struct mips_arch_choice *chosen_arch;
3319
3320 /* Defaults: mipsIII/r3000 (?!), (o)32-style ("oldabi") GPR names,
3321 and numeric FPR, CP0 register, and HWR names. */
3322 mips_isa = ISA_MIPS3;
3323 mips_processor = CPU_R3000;
3324 mips_gpr_names = mips_gpr_names_oldabi;
3325 mips_fpr_names = mips_fpr_names_numeric;
3326 mips_cp0_names = mips_cp0_names_numeric;
3327 mips_cp0sel_names = NULL;
3328 mips_cp0sel_names_len = 0;
3329 mips_hwr_names = mips_hwr_names_numeric;
3330 no_aliases = 0;
3331
3332 /* If an ELF "newabi" binary, use the n32/(n)64 GPR names. */
3333 #if 0
3334 if (info->flavour == bfd_target_elf_flavour && info->section != NULL)
3335 {
3336 Elf_Internal_Ehdr *header;
3337
3338 header = elf_elfheader (info->section->owner);
3339 if (is_newabi (header))
3340 mips_gpr_names = mips_gpr_names_newabi;
3341 }
3342 #endif
3343
3344 /* Set ISA, architecture, and cp0 register names as best we can. */
3345 #if !defined(SYMTAB_AVAILABLE) && 0
3346 /* This is running out on a target machine, not in a host tool.
3347 FIXME: Where does mips_target_info come from? */
3348 target_processor = mips_target_info.processor;
3349 mips_isa = mips_target_info.isa;
3350 #else
3351 chosen_arch = choose_arch_by_number (info->mach);
3352 if (chosen_arch != NULL)
3353 {
3354 mips_processor = chosen_arch->processor;
3355 mips_isa = chosen_arch->isa;
3356 mips_cp0_names = chosen_arch->cp0_names;
3357 mips_cp0sel_names = chosen_arch->cp0sel_names;
3358 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
3359 mips_hwr_names = chosen_arch->hwr_names;
3360 }
3361 #endif
3362 }
3363
3364 static void
3365 parse_mips_dis_option (const char *option, unsigned int len)
3366 {
3367 unsigned int i, optionlen, vallen;
3368 const char *val;
3369 const struct mips_abi_choice *chosen_abi;
3370 const struct mips_arch_choice *chosen_arch;
3371
3372 /* Look for the = that delimits the end of the option name. */
3373 for (i = 0; i < len; i++)
3374 {
3375 if (option[i] == '=')
3376 break;
3377 }
3378 if (i == 0) /* Invalid option: no name before '='. */
3379 return;
3380 if (i == len) /* Invalid option: no '='. */
3381 return;
3382 if (i == (len - 1)) /* Invalid option: no value after '='. */
3383 return;
3384
3385 optionlen = i;
3386 val = option + (optionlen + 1);
3387 vallen = len - (optionlen + 1);
3388
3389 if (strncmp("gpr-names", option, optionlen) == 0
3390 && strlen("gpr-names") == optionlen)
3391 {
3392 chosen_abi = choose_abi_by_name (val, vallen);
3393 if (chosen_abi != NULL)
3394 mips_gpr_names = chosen_abi->gpr_names;
3395 return;
3396 }
3397
3398 if (strncmp("fpr-names", option, optionlen) == 0
3399 && strlen("fpr-names") == optionlen)
3400 {
3401 chosen_abi = choose_abi_by_name (val, vallen);
3402 if (chosen_abi != NULL)
3403 mips_fpr_names = chosen_abi->fpr_names;
3404 return;
3405 }
3406
3407 if (strncmp("cp0-names", option, optionlen) == 0
3408 && strlen("cp0-names") == optionlen)
3409 {
3410 chosen_arch = choose_arch_by_name (val, vallen);
3411 if (chosen_arch != NULL)
3412 {
3413 mips_cp0_names = chosen_arch->cp0_names;
3414 mips_cp0sel_names = chosen_arch->cp0sel_names;
3415 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
3416 }
3417 return;
3418 }
3419
3420 if (strncmp("hwr-names", option, optionlen) == 0
3421 && strlen("hwr-names") == optionlen)
3422 {
3423 chosen_arch = choose_arch_by_name (val, vallen);
3424 if (chosen_arch != NULL)
3425 mips_hwr_names = chosen_arch->hwr_names;
3426 return;
3427 }
3428
3429 if (strncmp("reg-names", option, optionlen) == 0
3430 && strlen("reg-names") == optionlen)
3431 {
3432 /* We check both ABI and ARCH here unconditionally, so
3433 that "numeric" will do the desirable thing: select
3434 numeric register names for all registers. Other than
3435 that, a given name probably won't match both. */
3436 chosen_abi = choose_abi_by_name (val, vallen);
3437 if (chosen_abi != NULL)
3438 {
3439 mips_gpr_names = chosen_abi->gpr_names;
3440 mips_fpr_names = chosen_abi->fpr_names;
3441 }
3442 chosen_arch = choose_arch_by_name (val, vallen);
3443 if (chosen_arch != NULL)
3444 {
3445 mips_cp0_names = chosen_arch->cp0_names;
3446 mips_cp0sel_names = chosen_arch->cp0sel_names;
3447 mips_cp0sel_names_len = chosen_arch->cp0sel_names_len;
3448 mips_hwr_names = chosen_arch->hwr_names;
3449 }
3450 return;
3451 }
3452
3453 /* Invalid option. */
3454 }
3455
3456 static void
3457 parse_mips_dis_options (const char *options)
3458 {
3459 const char *option_end;
3460
3461 if (options == NULL)
3462 return;
3463
3464 while (*options != '\0')
3465 {
3466 /* Skip empty options. */
3467 if (*options == ',')
3468 {
3469 options++;
3470 continue;
3471 }
3472
3473 /* We know that *options is neither NUL or a comma. */
3474 option_end = options + 1;
3475 while (*option_end != ',' && *option_end != '\0')
3476 option_end++;
3477
3478 parse_mips_dis_option (options, option_end - options);
3479
3480 /* Go on to the next one. If option_end points to a comma, it
3481 will be skipped above. */
3482 options = option_end;
3483 }
3484 }
3485
3486 static const struct mips_cp0sel_name *
3487 lookup_mips_cp0sel_name (const struct mips_cp0sel_name *names,
3488 unsigned int len,
3489 unsigned int cp0reg,
3490 unsigned int sel)
3491 {
3492 unsigned int i;
3493
3494 for (i = 0; i < len; i++)
3495 if (names[i].cp0reg == cp0reg && names[i].sel == sel)
3496 return &names[i];
3497 return NULL;
3498 }
3499 \f
3500 /* Print insn arguments for 32/64-bit code. */
3501
3502 static void
3503 print_insn_args (const char *d,
3504 register unsigned long int l,
3505 bfd_vma pc,
3506 struct disassemble_info *info,
3507 const struct mips_opcode *opp)
3508 {
3509 int op, delta;
3510 unsigned int lsb, msb, msbd;
3511
3512 lsb = 0;
3513
3514 for (; *d != '\0'; d++)
3515 {
3516 switch (*d)
3517 {
3518 case ',':
3519 case '(':
3520 case ')':
3521 case '[':
3522 case ']':
3523 (*info->fprintf_func) (info->stream, "%c", *d);
3524 break;
3525
3526 case '+':
3527 /* Extension character; switch for second char. */
3528 d++;
3529 switch (*d)
3530 {
3531 case '\0':
3532 /* xgettext:c-format */
3533 (*info->fprintf_func) (info->stream,
3534 _("# internal error, incomplete extension sequence (+)"));
3535 return;
3536
3537 case 'A':
3538 lsb = (l >> OP_SH_SHAMT) & OP_MASK_SHAMT;
3539 (*info->fprintf_func) (info->stream, "0x%x", lsb);
3540 break;
3541
3542 case 'B':
3543 msb = (l >> OP_SH_INSMSB) & OP_MASK_INSMSB;
3544 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
3545 break;
3546
3547 case '1':
3548 (*info->fprintf_func) (info->stream, "0x%lx",
3549 (l >> OP_SH_UDI1) & OP_MASK_UDI1);
3550 break;
3551
3552 case '2':
3553 (*info->fprintf_func) (info->stream, "0x%lx",
3554 (l >> OP_SH_UDI2) & OP_MASK_UDI2);
3555 break;
3556
3557 case '3':
3558 (*info->fprintf_func) (info->stream, "0x%lx",
3559 (l >> OP_SH_UDI3) & OP_MASK_UDI3);
3560 break;
3561
3562 case '4':
3563 (*info->fprintf_func) (info->stream, "0x%lx",
3564 (l >> OP_SH_UDI4) & OP_MASK_UDI4);
3565 break;
3566
3567 case 'C':
3568 case 'H':
3569 msbd = (l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD;
3570 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
3571 break;
3572
3573 case 'D':
3574 {
3575 const struct mips_cp0sel_name *n;
3576 unsigned int cp0reg, sel;
3577
3578 cp0reg = (l >> OP_SH_RD) & OP_MASK_RD;
3579 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
3580
3581 /* CP0 register including 'sel' code for mtcN (et al.), to be
3582 printed textually if known. If not known, print both
3583 CP0 register name and sel numerically since CP0 register
3584 with sel 0 may have a name unrelated to register being
3585 printed. */
3586 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
3587 mips_cp0sel_names_len, cp0reg, sel);
3588 if (n != NULL)
3589 (*info->fprintf_func) (info->stream, "%s", n->name);
3590 else
3591 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
3592 break;
3593 }
3594
3595 case 'E':
3596 lsb = ((l >> OP_SH_SHAMT) & OP_MASK_SHAMT) + 32;
3597 (*info->fprintf_func) (info->stream, "0x%x", lsb);
3598 break;
3599
3600 case 'F':
3601 msb = ((l >> OP_SH_INSMSB) & OP_MASK_INSMSB) + 32;
3602 (*info->fprintf_func) (info->stream, "0x%x", msb - lsb + 1);
3603 break;
3604
3605 case 'G':
3606 msbd = ((l >> OP_SH_EXTMSBD) & OP_MASK_EXTMSBD) + 32;
3607 (*info->fprintf_func) (info->stream, "0x%x", msbd + 1);
3608 break;
3609
3610 case 't': /* Coprocessor 0 reg name */
3611 (*info->fprintf_func) (info->stream, "%s",
3612 mips_cp0_names[(l >> OP_SH_RT) &
3613 OP_MASK_RT]);
3614 break;
3615
3616 case 'T': /* Coprocessor 0 reg name */
3617 {
3618 const struct mips_cp0sel_name *n;
3619 unsigned int cp0reg, sel;
3620
3621 cp0reg = (l >> OP_SH_RT) & OP_MASK_RT;
3622 sel = (l >> OP_SH_SEL) & OP_MASK_SEL;
3623
3624 /* CP0 register including 'sel' code for mftc0, to be
3625 printed textually if known. If not known, print both
3626 CP0 register name and sel numerically since CP0 register
3627 with sel 0 may have a name unrelated to register being
3628 printed. */
3629 n = lookup_mips_cp0sel_name(mips_cp0sel_names,
3630 mips_cp0sel_names_len, cp0reg, sel);
3631 if (n != NULL)
3632 (*info->fprintf_func) (info->stream, "%s", n->name);
3633 else
3634 (*info->fprintf_func) (info->stream, "$%d,%d", cp0reg, sel);
3635 break;
3636 }
3637
3638 default:
3639 /* xgettext:c-format */
3640 (*info->fprintf_func) (info->stream,
3641 _("# internal error, undefined extension sequence (+%c)"),
3642 *d);
3643 return;
3644 }
3645 break;
3646
3647 case '2':
3648 (*info->fprintf_func) (info->stream, "0x%lx",
3649 (l >> OP_SH_BP) & OP_MASK_BP);
3650 break;
3651
3652 case '3':
3653 (*info->fprintf_func) (info->stream, "0x%lx",
3654 (l >> OP_SH_SA3) & OP_MASK_SA3);
3655 break;
3656
3657 case '4':
3658 (*info->fprintf_func) (info->stream, "0x%lx",
3659 (l >> OP_SH_SA4) & OP_MASK_SA4);
3660 break;
3661
3662 case '5':
3663 (*info->fprintf_func) (info->stream, "0x%lx",
3664 (l >> OP_SH_IMM8) & OP_MASK_IMM8);
3665 break;
3666
3667 case '6':
3668 (*info->fprintf_func) (info->stream, "0x%lx",
3669 (l >> OP_SH_RS) & OP_MASK_RS);
3670 break;
3671
3672 case '7':
3673 (*info->fprintf_func) (info->stream, "$ac%ld",
3674 (l >> OP_SH_DSPACC) & OP_MASK_DSPACC);
3675 break;
3676
3677 case '8':
3678 (*info->fprintf_func) (info->stream, "0x%lx",
3679 (l >> OP_SH_WRDSP) & OP_MASK_WRDSP);
3680 break;
3681
3682 case '9':
3683 (*info->fprintf_func) (info->stream, "$ac%ld",
3684 (l >> OP_SH_DSPACC_S) & OP_MASK_DSPACC_S);
3685 break;
3686
3687 case '0': /* dsp 6-bit signed immediate in bit 20 */
3688 delta = ((l >> OP_SH_DSPSFT) & OP_MASK_DSPSFT);
3689 if (delta & 0x20) /* test sign bit */
3690 delta |= ~OP_MASK_DSPSFT;
3691 (*info->fprintf_func) (info->stream, "%d", delta);
3692 break;
3693
3694 case ':': /* dsp 7-bit signed immediate in bit 19 */
3695 delta = ((l >> OP_SH_DSPSFT_7) & OP_MASK_DSPSFT_7);
3696 if (delta & 0x40) /* test sign bit */
3697 delta |= ~OP_MASK_DSPSFT_7;
3698 (*info->fprintf_func) (info->stream, "%d", delta);
3699 break;
3700
3701 case '\'':
3702 (*info->fprintf_func) (info->stream, "0x%lx",
3703 (l >> OP_SH_RDDSP) & OP_MASK_RDDSP);
3704 break;
3705
3706 case '@': /* dsp 10-bit signed immediate in bit 16 */
3707 delta = ((l >> OP_SH_IMM10) & OP_MASK_IMM10);
3708 if (delta & 0x200) /* test sign bit */
3709 delta |= ~OP_MASK_IMM10;
3710 (*info->fprintf_func) (info->stream, "%d", delta);
3711 break;
3712
3713 case '!':
3714 (*info->fprintf_func) (info->stream, "%ld",
3715 (l >> OP_SH_MT_U) & OP_MASK_MT_U);
3716 break;
3717
3718 case '$':
3719 (*info->fprintf_func) (info->stream, "%ld",
3720 (l >> OP_SH_MT_H) & OP_MASK_MT_H);
3721 break;
3722
3723 case '*':
3724 (*info->fprintf_func) (info->stream, "$ac%ld",
3725 (l >> OP_SH_MTACC_T) & OP_MASK_MTACC_T);
3726 break;
3727
3728 case '&':
3729 (*info->fprintf_func) (info->stream, "$ac%ld",
3730 (l >> OP_SH_MTACC_D) & OP_MASK_MTACC_D);
3731 break;
3732
3733 case 'g':
3734 /* Coprocessor register for CTTC1, MTTC2, MTHC2, CTTC2. */
3735 (*info->fprintf_func) (info->stream, "$%ld",
3736 (l >> OP_SH_RD) & OP_MASK_RD);
3737 break;
3738
3739 case 's':
3740 case 'b':
3741 case 'r':
3742 case 'v':
3743 (*info->fprintf_func) (info->stream, "%s",
3744 mips_gpr_names[(l >> OP_SH_RS) & OP_MASK_RS]);
3745 break;
3746
3747 case 't':
3748 case 'w':
3749 (*info->fprintf_func) (info->stream, "%s",
3750 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
3751 break;
3752
3753 case 'i':
3754 case 'u':
3755 (*info->fprintf_func) (info->stream, "0x%lx",
3756 (l >> OP_SH_IMMEDIATE) & OP_MASK_IMMEDIATE);
3757 break;
3758
3759 case 'j': /* Same as i, but sign-extended. */
3760 case 'o':
3761 delta = (opp->membership == I32R6) ?
3762 (l >> OP_SH_DELTA_R6) & OP_MASK_DELTA_R6 :
3763 (l >> OP_SH_DELTA) & OP_MASK_DELTA;
3764
3765 if (delta & 0x8000)
3766 delta |= ~0xffff;
3767 (*info->fprintf_func) (info->stream, "%d",
3768 delta);
3769 break;
3770
3771 case 'h':
3772 (*info->fprintf_func) (info->stream, "0x%x",
3773 (unsigned int) ((l >> OP_SH_PREFX)
3774 & OP_MASK_PREFX));
3775 break;
3776
3777 case 'k':
3778 (*info->fprintf_func) (info->stream, "0x%x",
3779 (unsigned int) ((l >> OP_SH_CACHE)
3780 & OP_MASK_CACHE));
3781 break;
3782
3783 case 'a':
3784 info->target = (((pc + 4) & ~(bfd_vma) 0x0fffffff)
3785 | (((l >> OP_SH_TARGET) & OP_MASK_TARGET) << 2));
3786 /* For gdb disassembler, force odd address on jalx. */
3787 if (info->flavour == bfd_target_unknown_flavour
3788 && strcmp (opp->name, "jalx") == 0)
3789 info->target |= 1;
3790 (*info->print_address_func) (info->target, info);
3791 break;
3792
3793 case 'p':
3794 /* Sign extend the displacement. */
3795 delta = (l >> OP_SH_DELTA) & OP_MASK_DELTA;
3796 if (delta & 0x8000)
3797 delta |= ~0xffff;
3798 info->target = (delta << 2) + pc + INSNLEN;
3799 (*info->print_address_func) (info->target, info);
3800 break;
3801
3802 case 'd':
3803 (*info->fprintf_func) (info->stream, "%s",
3804 mips_gpr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
3805 break;
3806
3807 case 'U':
3808 {
3809 /* First check for both rd and rt being equal. */
3810 unsigned int reg = (l >> OP_SH_RD) & OP_MASK_RD;
3811 if (reg == ((l >> OP_SH_RT) & OP_MASK_RT))
3812 (*info->fprintf_func) (info->stream, "%s",
3813 mips_gpr_names[reg]);
3814 else
3815 {
3816 /* If one is zero use the other. */
3817 if (reg == 0)
3818 (*info->fprintf_func) (info->stream, "%s",
3819 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
3820 else if (((l >> OP_SH_RT) & OP_MASK_RT) == 0)
3821 (*info->fprintf_func) (info->stream, "%s",
3822 mips_gpr_names[reg]);
3823 else /* Bogus, result depends on processor. */
3824 (*info->fprintf_func) (info->stream, "%s or %s",
3825 mips_gpr_names[reg],
3826 mips_gpr_names[(l >> OP_SH_RT) & OP_MASK_RT]);
3827 }
3828 }
3829 break;
3830
3831 case 'z':
3832 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
3833 break;
3834
3835 case '<':
3836 (*info->fprintf_func) (info->stream, "0x%lx",
3837 (l >> OP_SH_SHAMT) & OP_MASK_SHAMT);
3838 break;
3839
3840 case 'c':
3841 (*info->fprintf_func) (info->stream, "0x%lx",
3842 (l >> OP_SH_CODE) & OP_MASK_CODE);
3843 break;
3844
3845 case 'q':
3846 (*info->fprintf_func) (info->stream, "0x%lx",
3847 (l >> OP_SH_CODE2) & OP_MASK_CODE2);
3848 break;
3849
3850 case 'C':
3851 (*info->fprintf_func) (info->stream, "0x%lx",
3852 (l >> OP_SH_COPZ) & OP_MASK_COPZ);
3853 break;
3854
3855 case 'B':
3856 (*info->fprintf_func) (info->stream, "0x%lx",
3857
3858 (l >> OP_SH_CODE20) & OP_MASK_CODE20);
3859 break;
3860
3861 case 'J':
3862 (*info->fprintf_func) (info->stream, "0x%lx",
3863 (l >> OP_SH_CODE19) & OP_MASK_CODE19);
3864 break;
3865
3866 case 'S':
3867 case 'V':
3868 (*info->fprintf_func) (info->stream, "%s",
3869 mips_fpr_names[(l >> OP_SH_FS) & OP_MASK_FS]);
3870 break;
3871
3872 case 'T':
3873 case 'W':
3874 (*info->fprintf_func) (info->stream, "%s",
3875 mips_fpr_names[(l >> OP_SH_FT) & OP_MASK_FT]);
3876 break;
3877
3878 case 'D':
3879 (*info->fprintf_func) (info->stream, "%s",
3880 mips_fpr_names[(l >> OP_SH_FD) & OP_MASK_FD]);
3881 break;
3882
3883 case 'R':
3884 (*info->fprintf_func) (info->stream, "%s",
3885 mips_fpr_names[(l >> OP_SH_FR) & OP_MASK_FR]);
3886 break;
3887
3888 case 'E':
3889 /* Coprocessor register for lwcN instructions, et al.
3890
3891 Note that there is no load/store cp0 instructions, and
3892 that FPU (cp1) instructions disassemble this field using
3893 'T' format. Therefore, until we gain understanding of
3894 cp2 register names, we can simply print the register
3895 numbers. */
3896 (*info->fprintf_func) (info->stream, "$%ld",
3897 (l >> OP_SH_RT) & OP_MASK_RT);
3898 break;
3899
3900 case 'G':
3901 /* Coprocessor register for mtcN instructions, et al. Note
3902 that FPU (cp1) instructions disassemble this field using
3903 'S' format. Therefore, we only need to worry about cp0,
3904 cp2, and cp3. */
3905 op = (l >> OP_SH_OP) & OP_MASK_OP;
3906 if (op == OP_OP_COP0)
3907 (*info->fprintf_func) (info->stream, "%s",
3908 mips_cp0_names[(l >> OP_SH_RD) & OP_MASK_RD]);
3909 else
3910 (*info->fprintf_func) (info->stream, "$%ld",
3911 (l >> OP_SH_RD) & OP_MASK_RD);
3912 break;
3913
3914 case 'K':
3915 (*info->fprintf_func) (info->stream, "%s",
3916 mips_hwr_names[(l >> OP_SH_RD) & OP_MASK_RD]);
3917 break;
3918
3919 case 'N':
3920 (*info->fprintf_func) (info->stream,
3921 ((opp->pinfo & (FP_D | FP_S)) != 0
3922 ? "$fcc%ld" : "$cc%ld"),
3923 (l >> OP_SH_BCC) & OP_MASK_BCC);
3924 break;
3925
3926 case 'M':
3927 (*info->fprintf_func) (info->stream, "$fcc%ld",
3928 (l >> OP_SH_CCC) & OP_MASK_CCC);
3929 break;
3930
3931 case 'P':
3932 (*info->fprintf_func) (info->stream, "%ld",
3933 (l >> OP_SH_PERFREG) & OP_MASK_PERFREG);
3934 break;
3935
3936 case 'e':
3937 (*info->fprintf_func) (info->stream, "%ld",
3938 (l >> OP_SH_VECBYTE) & OP_MASK_VECBYTE);
3939 break;
3940
3941 case '%':
3942 (*info->fprintf_func) (info->stream, "%ld",
3943 (l >> OP_SH_VECALIGN) & OP_MASK_VECALIGN);
3944 break;
3945
3946 case 'H':
3947 (*info->fprintf_func) (info->stream, "%ld",
3948 (l >> OP_SH_SEL) & OP_MASK_SEL);
3949 break;
3950
3951 case 'O':
3952 (*info->fprintf_func) (info->stream, "%ld",
3953 (l >> OP_SH_ALN) & OP_MASK_ALN);
3954 break;
3955
3956 case 'Q':
3957 {
3958 unsigned int vsel = (l >> OP_SH_VSEL) & OP_MASK_VSEL;
3959
3960 if ((vsel & 0x10) == 0)
3961 {
3962 int fmt;
3963
3964 vsel &= 0x0f;
3965 for (fmt = 0; fmt < 3; fmt++, vsel >>= 1)
3966 if ((vsel & 1) == 0)
3967 break;
3968 (*info->fprintf_func) (info->stream, "$v%ld[%d]",
3969 (l >> OP_SH_FT) & OP_MASK_FT,
3970 vsel >> 1);
3971 }
3972 else if ((vsel & 0x08) == 0)
3973 {
3974 (*info->fprintf_func) (info->stream, "$v%ld",
3975 (l >> OP_SH_FT) & OP_MASK_FT);
3976 }
3977 else
3978 {
3979 (*info->fprintf_func) (info->stream, "0x%lx",
3980 (l >> OP_SH_FT) & OP_MASK_FT);
3981 }
3982 }
3983 break;
3984
3985 case 'X':
3986 (*info->fprintf_func) (info->stream, "$v%ld",
3987 (l >> OP_SH_FD) & OP_MASK_FD);
3988 break;
3989
3990 case 'Y':
3991 (*info->fprintf_func) (info->stream, "$v%ld",
3992 (l >> OP_SH_FS) & OP_MASK_FS);
3993 break;
3994
3995 case 'Z':
3996 (*info->fprintf_func) (info->stream, "$v%ld",
3997 (l >> OP_SH_FT) & OP_MASK_FT);
3998 break;
3999
4000 default:
4001 /* xgettext:c-format */
4002 (*info->fprintf_func) (info->stream,
4003 _("# internal error, undefined modifier(%c)"),
4004 *d);
4005 return;
4006 }
4007 }
4008 }
4009 \f
4010 /* Check if the object uses NewABI conventions. */
4011 #if 0
4012 static int
4013 is_newabi (header)
4014 Elf_Internal_Ehdr *header;
4015 {
4016 /* There are no old-style ABIs which use 64-bit ELF. */
4017 if (header->e_ident[EI_CLASS] == ELFCLASS64)
4018 return 1;
4019
4020 /* If a 32-bit ELF file, n32 is a new-style ABI. */
4021 if ((header->e_flags & EF_MIPS_ABI2) != 0)
4022 return 1;
4023
4024 return 0;
4025 }
4026 #endif
4027 \f
4028 /* Print the mips instruction at address MEMADDR in debugged memory,
4029 on using INFO. Returns length of the instruction, in bytes, which is
4030 always INSNLEN. BIGENDIAN must be 1 if this is big-endian code, 0 if
4031 this is little-endian code. */
4032
4033 static int
4034 print_insn_mips (bfd_vma memaddr,
4035 unsigned long int word,
4036 struct disassemble_info *info)
4037 {
4038 const struct mips_opcode *op;
4039 static bfd_boolean init = 0;
4040 static const struct mips_opcode *mips_hash[OP_MASK_OP + 1];
4041
4042 /* Build a hash table to shorten the search time. */
4043 if (! init)
4044 {
4045 unsigned int i;
4046
4047 for (i = 0; i <= OP_MASK_OP; i++)
4048 {
4049 for (op = mips_opcodes; op < &mips_opcodes[NUMOPCODES]; op++)
4050 {
4051 if (op->pinfo == INSN_MACRO
4052 || (no_aliases && (op->pinfo2 & INSN2_ALIAS)))
4053 continue;
4054 if (i == ((op->match >> OP_SH_OP) & OP_MASK_OP))
4055 {
4056 mips_hash[i] = op;
4057 break;
4058 }
4059 }
4060 }
4061
4062 init = 1;
4063 }
4064
4065 info->bytes_per_chunk = INSNLEN;
4066 info->display_endian = info->endian;
4067 info->insn_info_valid = 1;
4068 info->branch_delay_insns = 0;
4069 info->data_size = 0;
4070 info->insn_type = dis_nonbranch;
4071 info->target = 0;
4072 info->target2 = 0;
4073
4074 op = mips_hash[(word >> OP_SH_OP) & OP_MASK_OP];
4075 if (op != NULL)
4076 {
4077 for (; op < &mips_opcodes[NUMOPCODES]; op++)
4078 {
4079 if (op->pinfo != INSN_MACRO
4080 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
4081 && (word & op->mask) == op->match)
4082 {
4083 const char *d;
4084
4085 /* We always allow to disassemble the jalx instruction. */
4086 if (! OPCODE_IS_MEMBER (op, mips_isa, mips_processor)
4087 && strcmp (op->name, "jalx"))
4088 continue;
4089
4090 /* Figure out instruction type and branch delay information. */
4091 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
4092 {
4093 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
4094 info->insn_type = dis_jsr;
4095 else
4096 info->insn_type = dis_branch;
4097 info->branch_delay_insns = 1;
4098 }
4099 else if ((op->pinfo & (INSN_COND_BRANCH_DELAY
4100 | INSN_COND_BRANCH_LIKELY)) != 0)
4101 {
4102 if ((info->insn_type & INSN_WRITE_GPR_31) != 0)
4103 info->insn_type = dis_condjsr;
4104 else
4105 info->insn_type = dis_condbranch;
4106 info->branch_delay_insns = 1;
4107 }
4108 else if ((op->pinfo & (INSN_STORE_MEMORY
4109 | INSN_LOAD_MEMORY_DELAY)) != 0)
4110 info->insn_type = dis_dref;
4111
4112 (*info->fprintf_func) (info->stream, "%s", op->name);
4113
4114 d = op->args;
4115 if (d != NULL && *d != '\0')
4116 {
4117 (*info->fprintf_func) (info->stream, "\t");
4118 print_insn_args (d, word, memaddr, info, op);
4119 }
4120
4121 return INSNLEN;
4122 }
4123 }
4124 }
4125
4126 /* Handle undefined instructions. */
4127 info->insn_type = dis_noninsn;
4128 (*info->fprintf_func) (info->stream, "0x%lx", word);
4129 return INSNLEN;
4130 }
4131 \f
4132 /* In an environment where we do not know the symbol type of the
4133 instruction we are forced to assume that the low order bit of the
4134 instructions' address may mark it as a mips16 instruction. If we
4135 are single stepping, or the pc is within the disassembled function,
4136 this works. Otherwise, we need a clue. Sometimes. */
4137
4138 static int
4139 _print_insn_mips (bfd_vma memaddr,
4140 struct disassemble_info *info,
4141 enum bfd_endian endianness)
4142 {
4143 bfd_byte buffer[INSNLEN];
4144 int status;
4145
4146 set_default_mips_dis_options (info);
4147 parse_mips_dis_options (info->disassembler_options);
4148
4149 #if 0
4150 #if 1
4151 /* FIXME: If odd address, this is CLEARLY a mips 16 instruction. */
4152 /* Only a few tools will work this way. */
4153 if (memaddr & 0x01)
4154 return print_insn_mips16 (memaddr, info);
4155 #endif
4156
4157 #if SYMTAB_AVAILABLE
4158 if (info->mach == bfd_mach_mips16
4159 || (info->flavour == bfd_target_elf_flavour
4160 && info->symbols != NULL
4161 && ((*(elf_symbol_type **) info->symbols)->internal_elf_sym.st_other
4162 == STO_MIPS16)))
4163 return print_insn_mips16 (memaddr, info);
4164 #endif
4165 #endif
4166
4167 status = (*info->read_memory_func) (memaddr, buffer, INSNLEN, info);
4168 if (status == 0)
4169 {
4170 unsigned long insn;
4171
4172 if (endianness == BFD_ENDIAN_BIG)
4173 insn = (unsigned long) bfd_getb32 (buffer);
4174 else
4175 insn = (unsigned long) bfd_getl32 (buffer);
4176
4177 return print_insn_mips (memaddr, insn, info);
4178 }
4179 else
4180 {
4181 (*info->memory_error_func) (status, memaddr, info);
4182 return -1;
4183 }
4184 }
4185
4186 int
4187 print_insn_big_mips (bfd_vma memaddr, struct disassemble_info *info)
4188 {
4189 return _print_insn_mips (memaddr, info, BFD_ENDIAN_BIG);
4190 }
4191
4192 int
4193 print_insn_little_mips (bfd_vma memaddr, struct disassemble_info *info)
4194 {
4195 return _print_insn_mips (memaddr, info, BFD_ENDIAN_LITTLE);
4196 }
4197 \f
4198 /* Disassemble mips16 instructions. */
4199 #if 0
4200 static int
4201 print_insn_mips16 (bfd_vma memaddr, struct disassemble_info *info)
4202 {
4203 int status;
4204 bfd_byte buffer[2];
4205 int length;
4206 int insn;
4207 bfd_boolean use_extend;
4208 int extend = 0;
4209 const struct mips_opcode *op, *opend;
4210
4211 info->bytes_per_chunk = 2;
4212 info->display_endian = info->endian;
4213 info->insn_info_valid = 1;
4214 info->branch_delay_insns = 0;
4215 info->data_size = 0;
4216 info->insn_type = dis_nonbranch;
4217 info->target = 0;
4218 info->target2 = 0;
4219
4220 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
4221 if (status != 0)
4222 {
4223 (*info->memory_error_func) (status, memaddr, info);
4224 return -1;
4225 }
4226
4227 length = 2;
4228
4229 if (info->endian == BFD_ENDIAN_BIG)
4230 insn = bfd_getb16 (buffer);
4231 else
4232 insn = bfd_getl16 (buffer);
4233
4234 /* Handle the extend opcode specially. */
4235 use_extend = FALSE;
4236 if ((insn & 0xf800) == 0xf000)
4237 {
4238 use_extend = TRUE;
4239 extend = insn & 0x7ff;
4240
4241 memaddr += 2;
4242
4243 status = (*info->read_memory_func) (memaddr, buffer, 2, info);
4244 if (status != 0)
4245 {
4246 (*info->fprintf_func) (info->stream, "extend 0x%x",
4247 (unsigned int) extend);
4248 (*info->memory_error_func) (status, memaddr, info);
4249 return -1;
4250 }
4251
4252 if (info->endian == BFD_ENDIAN_BIG)
4253 insn = bfd_getb16 (buffer);
4254 else
4255 insn = bfd_getl16 (buffer);
4256
4257 /* Check for an extend opcode followed by an extend opcode. */
4258 if ((insn & 0xf800) == 0xf000)
4259 {
4260 (*info->fprintf_func) (info->stream, "extend 0x%x",
4261 (unsigned int) extend);
4262 info->insn_type = dis_noninsn;
4263 return length;
4264 }
4265
4266 length += 2;
4267 }
4268
4269 /* FIXME: Should probably use a hash table on the major opcode here. */
4270
4271 opend = mips16_opcodes + bfd_mips16_num_opcodes;
4272 for (op = mips16_opcodes; op < opend; op++)
4273 {
4274 if (op->pinfo != INSN_MACRO
4275 && !(no_aliases && (op->pinfo2 & INSN2_ALIAS))
4276 && (insn & op->mask) == op->match)
4277 {
4278 const char *s;
4279
4280 if (strchr (op->args, 'a') != NULL)
4281 {
4282 if (use_extend)
4283 {
4284 (*info->fprintf_func) (info->stream, "extend 0x%x",
4285 (unsigned int) extend);
4286 info->insn_type = dis_noninsn;
4287 return length - 2;
4288 }
4289
4290 use_extend = FALSE;
4291
4292 memaddr += 2;
4293
4294 status = (*info->read_memory_func) (memaddr, buffer, 2,
4295 info);
4296 if (status == 0)
4297 {
4298 use_extend = TRUE;
4299 if (info->endian == BFD_ENDIAN_BIG)
4300 extend = bfd_getb16 (buffer);
4301 else
4302 extend = bfd_getl16 (buffer);
4303 length += 2;
4304 }
4305 }
4306
4307 (*info->fprintf_func) (info->stream, "%s", op->name);
4308 if (op->args[0] != '\0')
4309 (*info->fprintf_func) (info->stream, "\t");
4310
4311 for (s = op->args; *s != '\0'; s++)
4312 {
4313 if (*s == ','
4314 && s[1] == 'w'
4315 && (((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)
4316 == ((insn >> MIPS16OP_SH_RY) & MIPS16OP_MASK_RY)))
4317 {
4318 /* Skip the register and the comma. */
4319 ++s;
4320 continue;
4321 }
4322 if (*s == ','
4323 && s[1] == 'v'
4324 && (((insn >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ)
4325 == ((insn >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX)))
4326 {
4327 /* Skip the register and the comma. */
4328 ++s;
4329 continue;
4330 }
4331 print_mips16_insn_arg (*s, op, insn, use_extend, extend, memaddr,
4332 info);
4333 }
4334
4335 if ((op->pinfo & INSN_UNCOND_BRANCH_DELAY) != 0)
4336 {
4337 info->branch_delay_insns = 1;
4338 if (info->insn_type != dis_jsr)
4339 info->insn_type = dis_branch;
4340 }
4341
4342 return length;
4343 }
4344 }
4345
4346 if (use_extend)
4347 (*info->fprintf_func) (info->stream, "0x%x", extend | 0xf000);
4348 (*info->fprintf_func) (info->stream, "0x%x", insn);
4349 info->insn_type = dis_noninsn;
4350
4351 return length;
4352 }
4353
4354 /* Disassemble an operand for a mips16 instruction. */
4355
4356 static void
4357 print_mips16_insn_arg (char type,
4358 const struct mips_opcode *op,
4359 int l,
4360 bfd_boolean use_extend,
4361 int extend,
4362 bfd_vma memaddr,
4363 struct disassemble_info *info)
4364 {
4365 switch (type)
4366 {
4367 case ',':
4368 case '(':
4369 case ')':
4370 (*info->fprintf_func) (info->stream, "%c", type);
4371 break;
4372
4373 case 'y':
4374 case 'w':
4375 (*info->fprintf_func) (info->stream, "%s",
4376 mips16_reg_names(((l >> MIPS16OP_SH_RY)
4377 & MIPS16OP_MASK_RY)));
4378 break;
4379
4380 case 'x':
4381 case 'v':
4382 (*info->fprintf_func) (info->stream, "%s",
4383 mips16_reg_names(((l >> MIPS16OP_SH_RX)
4384 & MIPS16OP_MASK_RX)));
4385 break;
4386
4387 case 'z':
4388 (*info->fprintf_func) (info->stream, "%s",
4389 mips16_reg_names(((l >> MIPS16OP_SH_RZ)
4390 & MIPS16OP_MASK_RZ)));
4391 break;
4392
4393 case 'Z':
4394 (*info->fprintf_func) (info->stream, "%s",
4395 mips16_reg_names(((l >> MIPS16OP_SH_MOVE32Z)
4396 & MIPS16OP_MASK_MOVE32Z)));
4397 break;
4398
4399 case '0':
4400 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[0]);
4401 break;
4402
4403 case 'S':
4404 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[29]);
4405 break;
4406
4407 case 'P':
4408 (*info->fprintf_func) (info->stream, "$pc");
4409 break;
4410
4411 case 'R':
4412 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[31]);
4413 break;
4414
4415 case 'X':
4416 (*info->fprintf_func) (info->stream, "%s",
4417 mips_gpr_names[((l >> MIPS16OP_SH_REGR32)
4418 & MIPS16OP_MASK_REGR32)]);
4419 break;
4420
4421 case 'Y':
4422 (*info->fprintf_func) (info->stream, "%s",
4423 mips_gpr_names[MIPS16OP_EXTRACT_REG32R (l)]);
4424 break;
4425
4426 case '<':
4427 case '>':
4428 case '[':
4429 case ']':
4430 case '4':
4431 case '5':
4432 case 'H':
4433 case 'W':
4434 case 'D':
4435 case 'j':
4436 case '6':
4437 case '8':
4438 case 'V':
4439 case 'C':
4440 case 'U':
4441 case 'k':
4442 case 'K':
4443 case 'p':
4444 case 'q':
4445 case 'A':
4446 case 'B':
4447 case 'E':
4448 {
4449 int immed, nbits, shift, signedp, extbits, pcrel, extu, branch;
4450
4451 shift = 0;
4452 signedp = 0;
4453 extbits = 16;
4454 pcrel = 0;
4455 extu = 0;
4456 branch = 0;
4457 switch (type)
4458 {
4459 case '<':
4460 nbits = 3;
4461 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
4462 extbits = 5;
4463 extu = 1;
4464 break;
4465 case '>':
4466 nbits = 3;
4467 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
4468 extbits = 5;
4469 extu = 1;
4470 break;
4471 case '[':
4472 nbits = 3;
4473 immed = (l >> MIPS16OP_SH_RZ) & MIPS16OP_MASK_RZ;
4474 extbits = 6;
4475 extu = 1;
4476 break;
4477 case ']':
4478 nbits = 3;
4479 immed = (l >> MIPS16OP_SH_RX) & MIPS16OP_MASK_RX;
4480 extbits = 6;
4481 extu = 1;
4482 break;
4483 case '4':
4484 nbits = 4;
4485 immed = (l >> MIPS16OP_SH_IMM4) & MIPS16OP_MASK_IMM4;
4486 signedp = 1;
4487 extbits = 15;
4488 break;
4489 case '5':
4490 nbits = 5;
4491 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4492 info->insn_type = dis_dref;
4493 info->data_size = 1;
4494 break;
4495 case 'H':
4496 nbits = 5;
4497 shift = 1;
4498 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4499 info->insn_type = dis_dref;
4500 info->data_size = 2;
4501 break;
4502 case 'W':
4503 nbits = 5;
4504 shift = 2;
4505 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4506 if ((op->pinfo & MIPS16_INSN_READ_PC) == 0
4507 && (op->pinfo & MIPS16_INSN_READ_SP) == 0)
4508 {
4509 info->insn_type = dis_dref;
4510 info->data_size = 4;
4511 }
4512 break;
4513 case 'D':
4514 nbits = 5;
4515 shift = 3;
4516 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4517 info->insn_type = dis_dref;
4518 info->data_size = 8;
4519 break;
4520 case 'j':
4521 nbits = 5;
4522 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4523 signedp = 1;
4524 break;
4525 case '6':
4526 nbits = 6;
4527 immed = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
4528 break;
4529 case '8':
4530 nbits = 8;
4531 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4532 break;
4533 case 'V':
4534 nbits = 8;
4535 shift = 2;
4536 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4537 /* FIXME: This might be lw, or it might be addiu to $sp or
4538 $pc. We assume it's load. */
4539 info->insn_type = dis_dref;
4540 info->data_size = 4;
4541 break;
4542 case 'C':
4543 nbits = 8;
4544 shift = 3;
4545 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4546 info->insn_type = dis_dref;
4547 info->data_size = 8;
4548 break;
4549 case 'U':
4550 nbits = 8;
4551 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4552 extu = 1;
4553 break;
4554 case 'k':
4555 nbits = 8;
4556 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4557 signedp = 1;
4558 break;
4559 case 'K':
4560 nbits = 8;
4561 shift = 3;
4562 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4563 signedp = 1;
4564 break;
4565 case 'p':
4566 nbits = 8;
4567 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4568 signedp = 1;
4569 pcrel = 1;
4570 branch = 1;
4571 info->insn_type = dis_condbranch;
4572 break;
4573 case 'q':
4574 nbits = 11;
4575 immed = (l >> MIPS16OP_SH_IMM11) & MIPS16OP_MASK_IMM11;
4576 signedp = 1;
4577 pcrel = 1;
4578 branch = 1;
4579 info->insn_type = dis_branch;
4580 break;
4581 case 'A':
4582 nbits = 8;
4583 shift = 2;
4584 immed = (l >> MIPS16OP_SH_IMM8) & MIPS16OP_MASK_IMM8;
4585 pcrel = 1;
4586 /* FIXME: This can be lw or la. We assume it is lw. */
4587 info->insn_type = dis_dref;
4588 info->data_size = 4;
4589 break;
4590 case 'B':
4591 nbits = 5;
4592 shift = 3;
4593 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4594 pcrel = 1;
4595 info->insn_type = dis_dref;
4596 info->data_size = 8;
4597 break;
4598 case 'E':
4599 nbits = 5;
4600 shift = 2;
4601 immed = (l >> MIPS16OP_SH_IMM5) & MIPS16OP_MASK_IMM5;
4602 pcrel = 1;
4603 break;
4604 default:
4605 abort ();
4606 }
4607
4608 if (! use_extend)
4609 {
4610 if (signedp && immed >= (1 << (nbits - 1)))
4611 immed -= 1 << nbits;
4612 immed <<= shift;
4613 if ((type == '<' || type == '>' || type == '[' || type == ']')
4614 && immed == 0)
4615 immed = 8;
4616 }
4617 else
4618 {
4619 if (extbits == 16)
4620 immed |= ((extend & 0x1f) << 11) | (extend & 0x7e0);
4621 else if (extbits == 15)
4622 immed |= ((extend & 0xf) << 11) | (extend & 0x7f0);
4623 else
4624 immed = ((extend >> 6) & 0x1f) | (extend & 0x20);
4625 immed &= (1 << extbits) - 1;
4626 if (! extu && immed >= (1 << (extbits - 1)))
4627 immed -= 1 << extbits;
4628 }
4629
4630 if (! pcrel)
4631 (*info->fprintf_func) (info->stream, "%d", immed);
4632 else
4633 {
4634 bfd_vma baseaddr;
4635
4636 if (branch)
4637 {
4638 immed *= 2;
4639 baseaddr = memaddr + 2;
4640 }
4641 else if (use_extend)
4642 baseaddr = memaddr - 2;
4643 else
4644 {
4645 int status;
4646 bfd_byte buffer[2];
4647
4648 baseaddr = memaddr;
4649
4650 /* If this instruction is in the delay slot of a jr
4651 instruction, the base address is the address of the
4652 jr instruction. If it is in the delay slot of jalr
4653 instruction, the base address is the address of the
4654 jalr instruction. This test is unreliable: we have
4655 no way of knowing whether the previous word is
4656 instruction or data. */
4657 status = (*info->read_memory_func) (memaddr - 4, buffer, 2,
4658 info);
4659 if (status == 0
4660 && (((info->endian == BFD_ENDIAN_BIG
4661 ? bfd_getb16 (buffer)
4662 : bfd_getl16 (buffer))
4663 & 0xf800) == 0x1800))
4664 baseaddr = memaddr - 4;
4665 else
4666 {
4667 status = (*info->read_memory_func) (memaddr - 2, buffer,
4668 2, info);
4669 if (status == 0
4670 && (((info->endian == BFD_ENDIAN_BIG
4671 ? bfd_getb16 (buffer)
4672 : bfd_getl16 (buffer))
4673 & 0xf81f) == 0xe800))
4674 baseaddr = memaddr - 2;
4675 }
4676 }
4677 info->target = (baseaddr & ~((1 << shift) - 1)) + immed;
4678 if (pcrel && branch
4679 && info->flavour == bfd_target_unknown_flavour)
4680 /* For gdb disassembler, maintain odd address. */
4681 info->target |= 1;
4682 (*info->print_address_func) (info->target, info);
4683 }
4684 }
4685 break;
4686
4687 case 'a':
4688 {
4689 int jalx = l & 0x400;
4690
4691 if (! use_extend)
4692 extend = 0;
4693 l = ((l & 0x1f) << 23) | ((l & 0x3e0) << 13) | (extend << 2);
4694 if (!jalx && info->flavour == bfd_target_unknown_flavour)
4695 /* For gdb disassembler, maintain odd address. */
4696 l |= 1;
4697 }
4698 info->target = ((memaddr + 4) & ~(bfd_vma) 0x0fffffff) | l;
4699 (*info->print_address_func) (info->target, info);
4700 info->insn_type = dis_jsr;
4701 info->branch_delay_insns = 1;
4702 break;
4703
4704 case 'l':
4705 case 'L':
4706 {
4707 int need_comma, amask, smask;
4708
4709 need_comma = 0;
4710
4711 l = (l >> MIPS16OP_SH_IMM6) & MIPS16OP_MASK_IMM6;
4712
4713 amask = (l >> 3) & 7;
4714
4715 if (amask > 0 && amask < 5)
4716 {
4717 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
4718 if (amask > 1)
4719 (*info->fprintf_func) (info->stream, "-%s",
4720 mips_gpr_names[amask + 3]);
4721 need_comma = 1;
4722 }
4723
4724 smask = (l >> 1) & 3;
4725 if (smask == 3)
4726 {
4727 (*info->fprintf_func) (info->stream, "%s??",
4728 need_comma ? "," : "");
4729 need_comma = 1;
4730 }
4731 else if (smask > 0)
4732 {
4733 (*info->fprintf_func) (info->stream, "%s%s",
4734 need_comma ? "," : "",
4735 mips_gpr_names[16]);
4736 if (smask > 1)
4737 (*info->fprintf_func) (info->stream, "-%s",
4738 mips_gpr_names[smask + 15]);
4739 need_comma = 1;
4740 }
4741
4742 if (l & 1)
4743 {
4744 (*info->fprintf_func) (info->stream, "%s%s",
4745 need_comma ? "," : "",
4746 mips_gpr_names[31]);
4747 need_comma = 1;
4748 }
4749
4750 if (amask == 5 || amask == 6)
4751 {
4752 (*info->fprintf_func) (info->stream, "%s$f0",
4753 need_comma ? "," : "");
4754 if (amask == 6)
4755 (*info->fprintf_func) (info->stream, "-$f1");
4756 }
4757 }
4758 break;
4759
4760 case 'm':
4761 case 'M':
4762 /* MIPS16e save/restore. */
4763 {
4764 int need_comma = 0;
4765 int amask, args, statics;
4766 int nsreg, smask;
4767 int framesz;
4768 int i, j;
4769
4770 l = l & 0x7f;
4771 if (use_extend)
4772 l |= extend << 16;
4773
4774 amask = (l >> 16) & 0xf;
4775 if (amask == MIPS16_ALL_ARGS)
4776 {
4777 args = 4;
4778 statics = 0;
4779 }
4780 else if (amask == MIPS16_ALL_STATICS)
4781 {
4782 args = 0;
4783 statics = 4;
4784 }
4785 else
4786 {
4787 args = amask >> 2;
4788 statics = amask & 3;
4789 }
4790
4791 if (args > 0) {
4792 (*info->fprintf_func) (info->stream, "%s", mips_gpr_names[4]);
4793 if (args > 1)
4794 (*info->fprintf_func) (info->stream, "-%s",
4795 mips_gpr_names[4 + args - 1]);
4796 need_comma = 1;
4797 }
4798
4799 framesz = (((l >> 16) & 0xf0) | (l & 0x0f)) * 8;
4800 if (framesz == 0 && !use_extend)
4801 framesz = 128;
4802
4803 (*info->fprintf_func) (info->stream, "%s%d",
4804 need_comma ? "," : "",
4805 framesz);
4806
4807 if (l & 0x40) /* $ra */
4808 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[31]);
4809
4810 nsreg = (l >> 24) & 0x7;
4811 smask = 0;
4812 if (l & 0x20) /* $s0 */
4813 smask |= 1 << 0;
4814 if (l & 0x10) /* $s1 */
4815 smask |= 1 << 1;
4816 if (nsreg > 0) /* $s2-$s8 */
4817 smask |= ((1 << nsreg) - 1) << 2;
4818
4819 /* Find first set static reg bit. */
4820 for (i = 0; i < 9; i++)
4821 {
4822 if (smask & (1 << i))
4823 {
4824 (*info->fprintf_func) (info->stream, ",%s",
4825 mips_gpr_names[i == 8 ? 30 : (16 + i)]);
4826 /* Skip over string of set bits. */
4827 for (j = i; smask & (2 << j); j++)
4828 continue;
4829 if (j > i)
4830 (*info->fprintf_func) (info->stream, "-%s",
4831 mips_gpr_names[j == 8 ? 30 : (16 + j)]);
4832 i = j + 1;
4833 }
4834 }
4835
4836 /* Statics $ax - $a3. */
4837 if (statics == 1)
4838 (*info->fprintf_func) (info->stream, ",%s", mips_gpr_names[7]);
4839 else if (statics > 0)
4840 (*info->fprintf_func) (info->stream, ",%s-%s",
4841 mips_gpr_names[7 - statics + 1],
4842 mips_gpr_names[7]);
4843 }
4844 break;
4845
4846 default:
4847 /* xgettext:c-format */
4848 (*info->fprintf_func)
4849 (info->stream,
4850 _("# internal disassembler error, unrecognised modifier (%c)"),
4851 type);
4852 abort ();
4853 }
4854 }
4855
4856 void
4857 print_mips_disassembler_options (FILE *stream)
4858 {
4859 unsigned int i;
4860
4861 fprintf (stream, _("\n\
4862 The following MIPS specific disassembler options are supported for use\n\
4863 with the -M switch (multiple options should be separated by commas):\n"));
4864
4865 fprintf (stream, _("\n\
4866 gpr-names=ABI Print GPR names according to specified ABI.\n\
4867 Default: based on binary being disassembled.\n"));
4868
4869 fprintf (stream, _("\n\
4870 fpr-names=ABI Print FPR names according to specified ABI.\n\
4871 Default: numeric.\n"));
4872
4873 fprintf (stream, _("\n\
4874 cp0-names=ARCH Print CP0 register names according to\n\
4875 specified architecture.\n\
4876 Default: based on binary being disassembled.\n"));
4877
4878 fprintf (stream, _("\n\
4879 hwr-names=ARCH Print HWR names according to specified\n\
4880 architecture.\n\
4881 Default: based on binary being disassembled.\n"));
4882
4883 fprintf (stream, _("\n\
4884 reg-names=ABI Print GPR and FPR names according to\n\
4885 specified ABI.\n"));
4886
4887 fprintf (stream, _("\n\
4888 reg-names=ARCH Print CP0 register and HWR names according to\n\
4889 specified architecture.\n"));
4890
4891 fprintf (stream, _("\n\
4892 For the options above, the following values are supported for \"ABI\":\n\
4893 "));
4894 for (i = 0; i < ARRAY_SIZE (mips_abi_choices); i++)
4895 fprintf (stream, " %s", mips_abi_choices[i].name);
4896 fprintf (stream, _("\n"));
4897
4898 fprintf (stream, _("\n\
4899 For the options above, The following values are supported for \"ARCH\":\n\
4900 "));
4901 for (i = 0; i < ARRAY_SIZE (mips_arch_choices); i++)
4902 if (*mips_arch_choices[i].name != '\0')
4903 fprintf (stream, " %s", mips_arch_choices[i].name);
4904 fprintf (stream, _("\n"));
4905
4906 fprintf (stream, _("\n"));
4907 }
4908 #endif
QEMU modified to work with kvm