2 * QEMU USB EHCI Emulation
4 * Copyright(c) 2008 Emutex Ltd. (address@hidden)
6 * EHCI project was started by Mark Burkley, with contributions by
7 * Niels de Vos. David S. Ahern continued working on it. Kevin Wolf,
8 * Jan Kiszka and Vincent Palatin contributed bugfixes.
11 * This library is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU Lesser General Public
13 * License as published by the Free Software Foundation; either
14 * version 2 of the License, or(at your option) any later version.
16 * This library is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
19 * Lesser General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, see <http://www.gnu.org/licenses/>.
26 #include "qemu-timer.h"
36 #define DPRINTF printf
41 /* internal processing - reset HC to try and recover */
42 #define USB_RET_PROCERR (-99)
44 #define MMIO_SIZE 0x1000
46 /* Capability Registers Base Address - section 2.2 */
47 #define CAPREGBASE 0x0000
48 #define CAPLENGTH CAPREGBASE + 0x0000 // 1-byte, 0x0001 reserved
49 #define HCIVERSION CAPREGBASE + 0x0002 // 2-bytes, i/f version #
50 #define HCSPARAMS CAPREGBASE + 0x0004 // 4-bytes, structural params
51 #define HCCPARAMS CAPREGBASE + 0x0008 // 4-bytes, capability params
52 #define EECP HCCPARAMS + 1
53 #define HCSPPORTROUTE1 CAPREGBASE + 0x000c
54 #define HCSPPORTROUTE2 CAPREGBASE + 0x0010
56 #define OPREGBASE 0x0020 // Operational Registers Base Address
58 #define USBCMD OPREGBASE + 0x0000
59 #define USBCMD_RUNSTOP (1 << 0) // run / Stop
60 #define USBCMD_HCRESET (1 << 1) // HC Reset
61 #define USBCMD_FLS (3 << 2) // Frame List Size
62 #define USBCMD_FLS_SH 2 // Frame List Size Shift
63 #define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
64 #define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
65 #define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
66 #define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
67 #define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
68 #define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
69 #define USBCMD_ITC (0x7f << 16) // Int Threshold Control
70 #define USBCMD_ITC_SH 16 // Int Threshold Control Shift
72 #define USBSTS OPREGBASE + 0x0004
73 #define USBSTS_RO_MASK 0x0000003f
74 #define USBSTS_INT (1 << 0) // USB Interrupt
75 #define USBSTS_ERRINT (1 << 1) // Error Interrupt
76 #define USBSTS_PCD (1 << 2) // Port Change Detect
77 #define USBSTS_FLR (1 << 3) // Frame List Rollover
78 #define USBSTS_HSE (1 << 4) // Host System Error
79 #define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
80 #define USBSTS_HALT (1 << 12) // HC Halted
81 #define USBSTS_REC (1 << 13) // Reclamation
82 #define USBSTS_PSS (1 << 14) // Periodic Schedule Status
83 #define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
86 * Interrupt enable bits correspond to the interrupt active bits in USBSTS
87 * so no need to redefine here.
89 #define USBINTR OPREGBASE + 0x0008
90 #define USBINTR_MASK 0x0000003f
92 #define FRINDEX OPREGBASE + 0x000c
93 #define CTRLDSSEGMENT OPREGBASE + 0x0010
94 #define PERIODICLISTBASE OPREGBASE + 0x0014
95 #define ASYNCLISTADDR OPREGBASE + 0x0018
96 #define ASYNCLISTADDR_MASK 0xffffffe0
98 #define CONFIGFLAG OPREGBASE + 0x0040
100 #define PORTSC (OPREGBASE + 0x0044)
101 #define PORTSC_BEGIN PORTSC
102 #define PORTSC_END (PORTSC + 4 * NB_PORTS)
104 * Bits that are reserved or are read-only are masked out of values
105 * written to us by software
107 #define PORTSC_RO_MASK 0x007001c0
108 #define PORTSC_RWC_MASK 0x0000002a
109 #define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
110 #define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
111 #define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
112 #define PORTSC_PTC (15 << 16) // Port Test Control
113 #define PORTSC_PTC_SH 16 // Port Test Control shift
114 #define PORTSC_PIC (3 << 14) // Port Indicator Control
115 #define PORTSC_PIC_SH 14 // Port Indicator Control Shift
116 #define PORTSC_POWNER (1 << 13) // Port Owner
117 #define PORTSC_PPOWER (1 << 12) // Port Power
118 #define PORTSC_LINESTAT (3 << 10) // Port Line Status
119 #define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
120 #define PORTSC_PRESET (1 << 8) // Port Reset
121 #define PORTSC_SUSPEND (1 << 7) // Port Suspend
122 #define PORTSC_FPRES (1 << 6) // Force Port Resume
123 #define PORTSC_OCC (1 << 5) // Over Current Change
124 #define PORTSC_OCA (1 << 4) // Over Current Active
125 #define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
126 #define PORTSC_PED (1 << 2) // Port Enable/Disable
127 #define PORTSC_CSC (1 << 1) // Connect Status Change
128 #define PORTSC_CONNECT (1 << 0) // Current Connect Status
130 #define FRAME_TIMER_FREQ 1000
131 #define FRAME_TIMER_NS (1000000000 / FRAME_TIMER_FREQ)
133 #define NB_MAXINTRATE 8 // Max rate at which controller issues ints
134 #define NB_PORTS 6 // Number of downstream ports
135 #define BUFF_SIZE 5*4096 // Max bytes to transfer per transaction
136 #define MAX_QH 100 // Max allowable queue heads in a chain
138 /* Internal periodic / asynchronous schedule state machine states
145 /* The following states are internal to the state machine function
159 /* macros for accessing fields within next link pointer entry */
160 #define NLPTR_GET(x) ((x) & 0xffffffe0)
161 #define NLPTR_TYPE_GET(x) (((x) >> 1) & 3)
162 #define NLPTR_TBIT(x) ((x) & 1) // 1=invalid, 0=valid
164 /* link pointer types */
165 #define NLPTR_TYPE_ITD 0 // isoc xfer descriptor
166 #define NLPTR_TYPE_QH 1 // queue head
167 #define NLPTR_TYPE_STITD 2 // split xaction, isoc xfer descriptor
168 #define NLPTR_TYPE_FSTN 3 // frame span traversal node
171 /* EHCI spec version 1.0 Section 3.3
173 typedef struct EHCIitd
{
176 uint32_t transact
[8];
177 #define ITD_XACT_ACTIVE (1 << 31)
178 #define ITD_XACT_DBERROR (1 << 30)
179 #define ITD_XACT_BABBLE (1 << 29)
180 #define ITD_XACT_XACTERR (1 << 28)
181 #define ITD_XACT_LENGTH_MASK 0x0fff0000
182 #define ITD_XACT_LENGTH_SH 16
183 #define ITD_XACT_IOC (1 << 15)
184 #define ITD_XACT_PGSEL_MASK 0x00007000
185 #define ITD_XACT_PGSEL_SH 12
186 #define ITD_XACT_OFFSET_MASK 0x00000fff
189 #define ITD_BUFPTR_MASK 0xfffff000
190 #define ITD_BUFPTR_SH 12
191 #define ITD_BUFPTR_EP_MASK 0x00000f00
192 #define ITD_BUFPTR_EP_SH 8
193 #define ITD_BUFPTR_DEVADDR_MASK 0x0000007f
194 #define ITD_BUFPTR_DEVADDR_SH 0
195 #define ITD_BUFPTR_DIRECTION (1 << 11)
196 #define ITD_BUFPTR_MAXPKT_MASK 0x000007ff
197 #define ITD_BUFPTR_MAXPKT_SH 0
198 #define ITD_BUFPTR_MULT_MASK 0x00000003
199 #define ITD_BUFPTR_MULT_SH 0
202 /* EHCI spec version 1.0 Section 3.4
204 typedef struct EHCIsitd
{
205 uint32_t next
; // Standard next link pointer
207 #define SITD_EPCHAR_IO (1 << 31)
208 #define SITD_EPCHAR_PORTNUM_MASK 0x7f000000
209 #define SITD_EPCHAR_PORTNUM_SH 24
210 #define SITD_EPCHAR_HUBADD_MASK 0x007f0000
211 #define SITD_EPCHAR_HUBADDR_SH 16
212 #define SITD_EPCHAR_EPNUM_MASK 0x00000f00
213 #define SITD_EPCHAR_EPNUM_SH 8
214 #define SITD_EPCHAR_DEVADDR_MASK 0x0000007f
217 #define SITD_UFRAME_CMASK_MASK 0x0000ff00
218 #define SITD_UFRAME_CMASK_SH 8
219 #define SITD_UFRAME_SMASK_MASK 0x000000ff
222 #define SITD_RESULTS_IOC (1 << 31)
223 #define SITD_RESULTS_PGSEL (1 << 30)
224 #define SITD_RESULTS_TBYTES_MASK 0x03ff0000
225 #define SITD_RESULTS_TYBYTES_SH 16
226 #define SITD_RESULTS_CPROGMASK_MASK 0x0000ff00
227 #define SITD_RESULTS_CPROGMASK_SH 8
228 #define SITD_RESULTS_ACTIVE (1 << 7)
229 #define SITD_RESULTS_ERR (1 << 6)
230 #define SITD_RESULTS_DBERR (1 << 5)
231 #define SITD_RESULTS_BABBLE (1 << 4)
232 #define SITD_RESULTS_XACTERR (1 << 3)
233 #define SITD_RESULTS_MISSEDUF (1 << 2)
234 #define SITD_RESULTS_SPLITXSTATE (1 << 1)
237 #define SITD_BUFPTR_MASK 0xfffff000
238 #define SITD_BUFPTR_CURROFF_MASK 0x00000fff
239 #define SITD_BUFPTR_TPOS_MASK 0x00000018
240 #define SITD_BUFPTR_TPOS_SH 3
241 #define SITD_BUFPTR_TCNT_MASK 0x00000007
243 uint32_t backptr
; // Standard next link pointer
246 /* EHCI spec version 1.0 Section 3.5
248 typedef struct EHCIqtd
{
249 uint32_t next
; // Standard next link pointer
250 uint32_t altnext
; // Standard next link pointer
252 #define QTD_TOKEN_DTOGGLE (1 << 31)
253 #define QTD_TOKEN_TBYTES_MASK 0x7fff0000
254 #define QTD_TOKEN_TBYTES_SH 16
255 #define QTD_TOKEN_IOC (1 << 15)
256 #define QTD_TOKEN_CPAGE_MASK 0x00007000
257 #define QTD_TOKEN_CPAGE_SH 12
258 #define QTD_TOKEN_CERR_MASK 0x00000c00
259 #define QTD_TOKEN_CERR_SH 10
260 #define QTD_TOKEN_PID_MASK 0x00000300
261 #define QTD_TOKEN_PID_SH 8
262 #define QTD_TOKEN_ACTIVE (1 << 7)
263 #define QTD_TOKEN_HALT (1 << 6)
264 #define QTD_TOKEN_DBERR (1 << 5)
265 #define QTD_TOKEN_BABBLE (1 << 4)
266 #define QTD_TOKEN_XACTERR (1 << 3)
267 #define QTD_TOKEN_MISSEDUF (1 << 2)
268 #define QTD_TOKEN_SPLITXSTATE (1 << 1)
269 #define QTD_TOKEN_PING (1 << 0)
271 uint32_t bufptr
[5]; // Standard buffer pointer
272 #define QTD_BUFPTR_MASK 0xfffff000
273 #define QTD_BUFPTR_SH 12
276 /* EHCI spec version 1.0 Section 3.6
278 typedef struct EHCIqh
{
279 uint32_t next
; // Standard next link pointer
281 /* endpoint characteristics */
283 #define QH_EPCHAR_RL_MASK 0xf0000000
284 #define QH_EPCHAR_RL_SH 28
285 #define QH_EPCHAR_C (1 << 27)
286 #define QH_EPCHAR_MPLEN_MASK 0x07FF0000
287 #define QH_EPCHAR_MPLEN_SH 16
288 #define QH_EPCHAR_H (1 << 15)
289 #define QH_EPCHAR_DTC (1 << 14)
290 #define QH_EPCHAR_EPS_MASK 0x00003000
291 #define QH_EPCHAR_EPS_SH 12
292 #define EHCI_QH_EPS_FULL 0
293 #define EHCI_QH_EPS_LOW 1
294 #define EHCI_QH_EPS_HIGH 2
295 #define EHCI_QH_EPS_RESERVED 3
297 #define QH_EPCHAR_EP_MASK 0x00000f00
298 #define QH_EPCHAR_EP_SH 8
299 #define QH_EPCHAR_I (1 << 7)
300 #define QH_EPCHAR_DEVADDR_MASK 0x0000007f
301 #define QH_EPCHAR_DEVADDR_SH 0
303 /* endpoint capabilities */
305 #define QH_EPCAP_MULT_MASK 0xc0000000
306 #define QH_EPCAP_MULT_SH 30
307 #define QH_EPCAP_PORTNUM_MASK 0x3f800000
308 #define QH_EPCAP_PORTNUM_SH 23
309 #define QH_EPCAP_HUBADDR_MASK 0x007f0000
310 #define QH_EPCAP_HUBADDR_SH 16
311 #define QH_EPCAP_CMASK_MASK 0x0000ff00
312 #define QH_EPCAP_CMASK_SH 8
313 #define QH_EPCAP_SMASK_MASK 0x000000ff
314 #define QH_EPCAP_SMASK_SH 0
316 uint32_t current_qtd
; // Standard next link pointer
317 uint32_t next_qtd
; // Standard next link pointer
318 uint32_t altnext_qtd
;
319 #define QH_ALTNEXT_NAKCNT_MASK 0x0000001e
320 #define QH_ALTNEXT_NAKCNT_SH 1
322 uint32_t token
; // Same as QTD token
323 uint32_t bufptr
[5]; // Standard buffer pointer
324 #define BUFPTR_CPROGMASK_MASK 0x000000ff
325 #define BUFPTR_FRAMETAG_MASK 0x0000001f
326 #define BUFPTR_SBYTES_MASK 0x00000fe0
327 #define BUFPTR_SBYTES_SH 5
330 /* EHCI spec version 1.0 Section 3.7
332 typedef struct EHCIfstn
{
333 uint32_t next
; // Standard next link pointer
334 uint32_t backptr
; // Standard next link pointer
337 typedef struct EHCIPacket EHCIPacket
;
338 typedef struct EHCIQueue EHCIQueue
;
339 typedef struct EHCIState EHCIState
;
349 QTAILQ_ENTRY(EHCIPacket
) next
;
351 EHCIqtd qtd
; /* copy of current QTD (being worked on) */
352 uint32_t qtdaddr
; /* address QTD read from */
358 enum async_state async
;
364 QTAILQ_ENTRY(EHCIQueue
) next
;
370 /* cached data from guest - needs to be flushed
371 * when guest removes an entry (doorbell, handshake sequence)
373 EHCIqh qh
; /* copy of current QH (being worked on) */
374 uint32_t qhaddr
; /* address QH read from */
375 uint32_t qtdaddr
; /* address QTD read from */
377 QTAILQ_HEAD(, EHCIPacket
) packets
;
380 typedef QTAILQ_HEAD(EHCIQueueHead
, EHCIQueue
) EHCIQueueHead
;
393 * EHCI spec version 1.0 Section 2.3
394 * Host Controller Operational Registers
397 uint8_t mmio
[MMIO_SIZE
];
399 uint8_t cap
[OPREGBASE
];
404 uint32_t ctrldssegment
;
405 uint32_t periodiclistbase
;
406 uint32_t asynclistaddr
;
409 uint32_t portsc
[NB_PORTS
];
414 * Internal states, shadow registers, etc
416 QEMUTimer
*frame_timer
;
418 uint32_t astate
; /* Current state in asynchronous schedule */
419 uint32_t pstate
; /* Current state in periodic schedule */
420 USBPort ports
[NB_PORTS
];
421 USBPort
*companion_ports
[NB_PORTS
];
422 uint32_t usbsts_pending
;
423 uint32_t usbsts_frindex
;
424 EHCIQueueHead aqueues
;
425 EHCIQueueHead pqueues
;
427 /* which address to look at next */
428 uint32_t a_fetch_addr
;
429 uint32_t p_fetch_addr
;
434 uint64_t last_run_ns
;
435 uint32_t async_stepdown
;
438 #define SET_LAST_RUN_CLOCK(s) \
439 (s)->last_run_ns = qemu_get_clock_ns(vm_clock);
441 /* nifty macros from Arnon's EHCI version */
442 #define get_field(data, field) \
443 (((data) & field##_MASK) >> field##_SH)
445 #define set_field(data, newval, field) do { \
446 uint32_t val = *data; \
447 val &= ~ field##_MASK; \
448 val |= ((newval) << field##_SH) & field##_MASK; \
452 static const char *ehci_state_names
[] = {
453 [EST_INACTIVE
] = "INACTIVE",
454 [EST_ACTIVE
] = "ACTIVE",
455 [EST_EXECUTING
] = "EXECUTING",
456 [EST_SLEEPING
] = "SLEEPING",
457 [EST_WAITLISTHEAD
] = "WAITLISTHEAD",
458 [EST_FETCHENTRY
] = "FETCH ENTRY",
459 [EST_FETCHQH
] = "FETCH QH",
460 [EST_FETCHITD
] = "FETCH ITD",
461 [EST_ADVANCEQUEUE
] = "ADVANCEQUEUE",
462 [EST_FETCHQTD
] = "FETCH QTD",
463 [EST_EXECUTE
] = "EXECUTE",
464 [EST_WRITEBACK
] = "WRITEBACK",
465 [EST_HORIZONTALQH
] = "HORIZONTALQH",
468 static const char *ehci_mmio_names
[] = {
469 [CAPLENGTH
] = "CAPLENGTH",
470 [HCIVERSION
] = "HCIVERSION",
471 [HCSPARAMS
] = "HCSPARAMS",
472 [HCCPARAMS
] = "HCCPARAMS",
475 [USBINTR
] = "USBINTR",
476 [FRINDEX
] = "FRINDEX",
477 [PERIODICLISTBASE
] = "P-LIST BASE",
478 [ASYNCLISTADDR
] = "A-LIST ADDR",
479 [PORTSC_BEGIN
] = "PORTSC #0",
480 [PORTSC_BEGIN
+ 4] = "PORTSC #1",
481 [PORTSC_BEGIN
+ 8] = "PORTSC #2",
482 [PORTSC_BEGIN
+ 12] = "PORTSC #3",
483 [PORTSC_BEGIN
+ 16] = "PORTSC #4",
484 [PORTSC_BEGIN
+ 20] = "PORTSC #5",
485 [CONFIGFLAG
] = "CONFIGFLAG",
488 static const char *nr2str(const char **n
, size_t len
, uint32_t nr
)
490 if (nr
< len
&& n
[nr
] != NULL
) {
497 static const char *state2str(uint32_t state
)
499 return nr2str(ehci_state_names
, ARRAY_SIZE(ehci_state_names
), state
);
502 static const char *addr2str(target_phys_addr_t addr
)
504 return nr2str(ehci_mmio_names
, ARRAY_SIZE(ehci_mmio_names
), addr
);
507 static void ehci_trace_usbsts(uint32_t mask
, int state
)
510 if (mask
& USBSTS_INT
) {
511 trace_usb_ehci_usbsts("INT", state
);
513 if (mask
& USBSTS_ERRINT
) {
514 trace_usb_ehci_usbsts("ERRINT", state
);
516 if (mask
& USBSTS_PCD
) {
517 trace_usb_ehci_usbsts("PCD", state
);
519 if (mask
& USBSTS_FLR
) {
520 trace_usb_ehci_usbsts("FLR", state
);
522 if (mask
& USBSTS_HSE
) {
523 trace_usb_ehci_usbsts("HSE", state
);
525 if (mask
& USBSTS_IAA
) {
526 trace_usb_ehci_usbsts("IAA", state
);
530 if (mask
& USBSTS_HALT
) {
531 trace_usb_ehci_usbsts("HALT", state
);
533 if (mask
& USBSTS_REC
) {
534 trace_usb_ehci_usbsts("REC", state
);
536 if (mask
& USBSTS_PSS
) {
537 trace_usb_ehci_usbsts("PSS", state
);
539 if (mask
& USBSTS_ASS
) {
540 trace_usb_ehci_usbsts("ASS", state
);
544 static inline void ehci_set_usbsts(EHCIState
*s
, int mask
)
546 if ((s
->usbsts
& mask
) == mask
) {
549 ehci_trace_usbsts(mask
, 1);
553 static inline void ehci_clear_usbsts(EHCIState
*s
, int mask
)
555 if ((s
->usbsts
& mask
) == 0) {
558 ehci_trace_usbsts(mask
, 0);
562 /* update irq line */
563 static inline void ehci_update_irq(EHCIState
*s
)
567 if ((s
->usbsts
& USBINTR_MASK
) & s
->usbintr
) {
571 trace_usb_ehci_irq(level
, s
->frindex
, s
->usbsts
, s
->usbintr
);
572 qemu_set_irq(s
->irq
, level
);
575 /* flag interrupt condition */
576 static inline void ehci_raise_irq(EHCIState
*s
, int intr
)
578 s
->usbsts_pending
|= intr
;
582 * Commit pending interrupts (added via ehci_raise_irq),
583 * at the rate allowed by "Interrupt Threshold Control".
585 static inline void ehci_commit_irq(EHCIState
*s
)
589 if (!s
->usbsts_pending
) {
592 if (s
->usbsts_frindex
> s
->frindex
) {
596 itc
= (s
->usbcmd
>> 16) & 0xff;
597 s
->usbsts
|= s
->usbsts_pending
;
598 s
->usbsts_pending
= 0;
599 s
->usbsts_frindex
= s
->frindex
+ itc
;
603 static void ehci_update_halt(EHCIState
*s
)
605 if (s
->usbcmd
& USBCMD_RUNSTOP
) {
606 ehci_clear_usbsts(s
, USBSTS_HALT
);
608 if (s
->astate
== EST_INACTIVE
&& s
->pstate
== EST_INACTIVE
) {
609 ehci_set_usbsts(s
, USBSTS_HALT
);
614 static void ehci_set_state(EHCIState
*s
, int async
, int state
)
617 trace_usb_ehci_state("async", state2str(state
));
619 if (s
->astate
== EST_INACTIVE
) {
620 ehci_clear_usbsts(s
, USBSTS_ASS
);
623 ehci_set_usbsts(s
, USBSTS_ASS
);
626 trace_usb_ehci_state("periodic", state2str(state
));
628 if (s
->pstate
== EST_INACTIVE
) {
629 ehci_clear_usbsts(s
, USBSTS_PSS
);
632 ehci_set_usbsts(s
, USBSTS_PSS
);
637 static int ehci_get_state(EHCIState
*s
, int async
)
639 return async
? s
->astate
: s
->pstate
;
642 static void ehci_set_fetch_addr(EHCIState
*s
, int async
, uint32_t addr
)
645 s
->a_fetch_addr
= addr
;
647 s
->p_fetch_addr
= addr
;
651 static int ehci_get_fetch_addr(EHCIState
*s
, int async
)
653 return async
? s
->a_fetch_addr
: s
->p_fetch_addr
;
656 static void ehci_trace_qh(EHCIQueue
*q
, target_phys_addr_t addr
, EHCIqh
*qh
)
658 /* need three here due to argument count limits */
659 trace_usb_ehci_qh_ptrs(q
, addr
, qh
->next
,
660 qh
->current_qtd
, qh
->next_qtd
, qh
->altnext_qtd
);
661 trace_usb_ehci_qh_fields(addr
,
662 get_field(qh
->epchar
, QH_EPCHAR_RL
),
663 get_field(qh
->epchar
, QH_EPCHAR_MPLEN
),
664 get_field(qh
->epchar
, QH_EPCHAR_EPS
),
665 get_field(qh
->epchar
, QH_EPCHAR_EP
),
666 get_field(qh
->epchar
, QH_EPCHAR_DEVADDR
));
667 trace_usb_ehci_qh_bits(addr
,
668 (bool)(qh
->epchar
& QH_EPCHAR_C
),
669 (bool)(qh
->epchar
& QH_EPCHAR_H
),
670 (bool)(qh
->epchar
& QH_EPCHAR_DTC
),
671 (bool)(qh
->epchar
& QH_EPCHAR_I
));
674 static void ehci_trace_qtd(EHCIQueue
*q
, target_phys_addr_t addr
, EHCIqtd
*qtd
)
676 /* need three here due to argument count limits */
677 trace_usb_ehci_qtd_ptrs(q
, addr
, qtd
->next
, qtd
->altnext
);
678 trace_usb_ehci_qtd_fields(addr
,
679 get_field(qtd
->token
, QTD_TOKEN_TBYTES
),
680 get_field(qtd
->token
, QTD_TOKEN_CPAGE
),
681 get_field(qtd
->token
, QTD_TOKEN_CERR
),
682 get_field(qtd
->token
, QTD_TOKEN_PID
));
683 trace_usb_ehci_qtd_bits(addr
,
684 (bool)(qtd
->token
& QTD_TOKEN_IOC
),
685 (bool)(qtd
->token
& QTD_TOKEN_ACTIVE
),
686 (bool)(qtd
->token
& QTD_TOKEN_HALT
),
687 (bool)(qtd
->token
& QTD_TOKEN_BABBLE
),
688 (bool)(qtd
->token
& QTD_TOKEN_XACTERR
));
691 static void ehci_trace_itd(EHCIState
*s
, target_phys_addr_t addr
, EHCIitd
*itd
)
693 trace_usb_ehci_itd(addr
, itd
->next
,
694 get_field(itd
->bufptr
[1], ITD_BUFPTR_MAXPKT
),
695 get_field(itd
->bufptr
[2], ITD_BUFPTR_MULT
),
696 get_field(itd
->bufptr
[0], ITD_BUFPTR_EP
),
697 get_field(itd
->bufptr
[0], ITD_BUFPTR_DEVADDR
));
700 static void ehci_trace_sitd(EHCIState
*s
, target_phys_addr_t addr
,
703 trace_usb_ehci_sitd(addr
, sitd
->next
,
704 (bool)(sitd
->results
& SITD_RESULTS_ACTIVE
));
707 static inline bool ehci_enabled(EHCIState
*s
)
709 return s
->usbcmd
& USBCMD_RUNSTOP
;
712 static inline bool ehci_async_enabled(EHCIState
*s
)
714 return ehci_enabled(s
) && (s
->usbcmd
& USBCMD_ASE
);
717 static inline bool ehci_periodic_enabled(EHCIState
*s
)
719 return ehci_enabled(s
) && (s
->usbcmd
& USBCMD_PSE
);
722 /* packet management */
724 static EHCIPacket
*ehci_alloc_packet(EHCIQueue
*q
)
728 p
= g_new0(EHCIPacket
, 1);
730 usb_packet_init(&p
->packet
);
731 QTAILQ_INSERT_TAIL(&q
->packets
, p
, next
);
732 trace_usb_ehci_packet_action(p
->queue
, p
, "alloc");
736 static void ehci_free_packet(EHCIPacket
*p
)
738 trace_usb_ehci_packet_action(p
->queue
, p
, "free");
739 if (p
->async
== EHCI_ASYNC_INFLIGHT
) {
740 usb_cancel_packet(&p
->packet
);
742 QTAILQ_REMOVE(&p
->queue
->packets
, p
, next
);
743 usb_packet_cleanup(&p
->packet
);
747 /* queue management */
749 static EHCIQueue
*ehci_alloc_queue(EHCIState
*ehci
, uint32_t addr
, int async
)
751 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
754 q
= g_malloc0(sizeof(*q
));
758 QTAILQ_INIT(&q
->packets
);
759 QTAILQ_INSERT_HEAD(head
, q
, next
);
760 trace_usb_ehci_queue_action(q
, "alloc");
764 static void ehci_free_queue(EHCIQueue
*q
)
766 EHCIQueueHead
*head
= q
->async
? &q
->ehci
->aqueues
: &q
->ehci
->pqueues
;
769 trace_usb_ehci_queue_action(q
, "free");
770 while ((p
= QTAILQ_FIRST(&q
->packets
)) != NULL
) {
773 QTAILQ_REMOVE(head
, q
, next
);
777 static EHCIQueue
*ehci_find_queue_by_qh(EHCIState
*ehci
, uint32_t addr
,
780 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
783 QTAILQ_FOREACH(q
, head
, next
) {
784 if (addr
== q
->qhaddr
) {
791 static void ehci_queues_tag_unused_async(EHCIState
*ehci
)
795 QTAILQ_FOREACH(q
, &ehci
->aqueues
, next
) {
802 static void ehci_queues_rip_unused(EHCIState
*ehci
, int async
)
804 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
805 uint64_t maxage
= FRAME_TIMER_NS
* ehci
->maxframes
* 4;
808 QTAILQ_FOREACH_SAFE(q
, head
, next
, tmp
) {
811 q
->ts
= ehci
->last_run_ns
;
814 if (ehci
->last_run_ns
< q
->ts
+ maxage
) {
821 static void ehci_queues_rip_device(EHCIState
*ehci
, USBDevice
*dev
, int async
)
823 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
826 QTAILQ_FOREACH_SAFE(q
, head
, next
, tmp
) {
834 static void ehci_queues_rip_all(EHCIState
*ehci
, int async
)
836 EHCIQueueHead
*head
= async
? &ehci
->aqueues
: &ehci
->pqueues
;
839 QTAILQ_FOREACH_SAFE(q
, head
, next
, tmp
) {
844 /* Attach or detach a device on root hub */
846 static void ehci_attach(USBPort
*port
)
848 EHCIState
*s
= port
->opaque
;
849 uint32_t *portsc
= &s
->portsc
[port
->index
];
850 const char *owner
= (*portsc
& PORTSC_POWNER
) ? "comp" : "ehci";
852 trace_usb_ehci_port_attach(port
->index
, owner
, port
->dev
->product_desc
);
854 if (*portsc
& PORTSC_POWNER
) {
855 USBPort
*companion
= s
->companion_ports
[port
->index
];
856 companion
->dev
= port
->dev
;
857 companion
->ops
->attach(companion
);
861 *portsc
|= PORTSC_CONNECT
;
862 *portsc
|= PORTSC_CSC
;
864 ehci_raise_irq(s
, USBSTS_PCD
);
868 static void ehci_detach(USBPort
*port
)
870 EHCIState
*s
= port
->opaque
;
871 uint32_t *portsc
= &s
->portsc
[port
->index
];
872 const char *owner
= (*portsc
& PORTSC_POWNER
) ? "comp" : "ehci";
874 trace_usb_ehci_port_detach(port
->index
, owner
);
876 if (*portsc
& PORTSC_POWNER
) {
877 USBPort
*companion
= s
->companion_ports
[port
->index
];
878 companion
->ops
->detach(companion
);
879 companion
->dev
= NULL
;
881 * EHCI spec 4.2.2: "When a disconnect occurs... On the event,
882 * the port ownership is returned immediately to the EHCI controller."
884 *portsc
&= ~PORTSC_POWNER
;
888 ehci_queues_rip_device(s
, port
->dev
, 0);
889 ehci_queues_rip_device(s
, port
->dev
, 1);
891 *portsc
&= ~(PORTSC_CONNECT
|PORTSC_PED
);
892 *portsc
|= PORTSC_CSC
;
894 ehci_raise_irq(s
, USBSTS_PCD
);
898 static void ehci_child_detach(USBPort
*port
, USBDevice
*child
)
900 EHCIState
*s
= port
->opaque
;
901 uint32_t portsc
= s
->portsc
[port
->index
];
903 if (portsc
& PORTSC_POWNER
) {
904 USBPort
*companion
= s
->companion_ports
[port
->index
];
905 companion
->ops
->child_detach(companion
, child
);
909 ehci_queues_rip_device(s
, child
, 0);
910 ehci_queues_rip_device(s
, child
, 1);
913 static void ehci_wakeup(USBPort
*port
)
915 EHCIState
*s
= port
->opaque
;
916 uint32_t portsc
= s
->portsc
[port
->index
];
918 if (portsc
& PORTSC_POWNER
) {
919 USBPort
*companion
= s
->companion_ports
[port
->index
];
920 if (companion
->ops
->wakeup
) {
921 companion
->ops
->wakeup(companion
);
926 qemu_bh_schedule(s
->async_bh
);
929 static int ehci_register_companion(USBBus
*bus
, USBPort
*ports
[],
930 uint32_t portcount
, uint32_t firstport
)
932 EHCIState
*s
= container_of(bus
, EHCIState
, bus
);
935 if (firstport
+ portcount
> NB_PORTS
) {
936 qerror_report(QERR_INVALID_PARAMETER_VALUE
, "firstport",
937 "firstport on masterbus");
938 error_printf_unless_qmp(
939 "firstport value of %u makes companion take ports %u - %u, which "
940 "is outside of the valid range of 0 - %u\n", firstport
, firstport
,
941 firstport
+ portcount
- 1, NB_PORTS
- 1);
945 for (i
= 0; i
< portcount
; i
++) {
946 if (s
->companion_ports
[firstport
+ i
]) {
947 qerror_report(QERR_INVALID_PARAMETER_VALUE
, "masterbus",
949 error_printf_unless_qmp(
950 "port %u on masterbus %s already has a companion assigned\n",
951 firstport
+ i
, bus
->qbus
.name
);
956 for (i
= 0; i
< portcount
; i
++) {
957 s
->companion_ports
[firstport
+ i
] = ports
[i
];
958 s
->ports
[firstport
+ i
].speedmask
|=
959 USB_SPEED_MASK_LOW
| USB_SPEED_MASK_FULL
;
960 /* Ensure devs attached before the initial reset go to the companion */
961 s
->portsc
[firstport
+ i
] = PORTSC_POWNER
;
964 s
->companion_count
++;
965 s
->mmio
[0x05] = (s
->companion_count
<< 4) | portcount
;
970 static USBDevice
*ehci_find_device(EHCIState
*ehci
, uint8_t addr
)
976 for (i
= 0; i
< NB_PORTS
; i
++) {
977 port
= &ehci
->ports
[i
];
978 if (!(ehci
->portsc
[i
] & PORTSC_PED
)) {
979 DPRINTF("Port %d not enabled\n", i
);
982 dev
= usb_find_device(port
, addr
);
990 /* 4.1 host controller initialization */
991 static void ehci_reset(void *opaque
)
993 EHCIState
*s
= opaque
;
995 USBDevice
*devs
[NB_PORTS
];
997 trace_usb_ehci_reset();
1000 * Do the detach before touching portsc, so that it correctly gets send to
1001 * us or to our companion based on PORTSC_POWNER before the reset.
1003 for(i
= 0; i
< NB_PORTS
; i
++) {
1004 devs
[i
] = s
->ports
[i
].dev
;
1005 if (devs
[i
] && devs
[i
]->attached
) {
1006 usb_detach(&s
->ports
[i
]);
1010 memset(&s
->mmio
[OPREGBASE
], 0x00, MMIO_SIZE
- OPREGBASE
);
1012 s
->usbcmd
= NB_MAXINTRATE
<< USBCMD_ITC_SH
;
1013 s
->usbsts
= USBSTS_HALT
;
1014 s
->usbsts_pending
= 0;
1015 s
->usbsts_frindex
= 0;
1017 s
->astate
= EST_INACTIVE
;
1018 s
->pstate
= EST_INACTIVE
;
1020 for(i
= 0; i
< NB_PORTS
; i
++) {
1021 if (s
->companion_ports
[i
]) {
1022 s
->portsc
[i
] = PORTSC_POWNER
| PORTSC_PPOWER
;
1024 s
->portsc
[i
] = PORTSC_PPOWER
;
1026 if (devs
[i
] && devs
[i
]->attached
) {
1027 usb_attach(&s
->ports
[i
]);
1028 usb_device_reset(devs
[i
]);
1031 ehci_queues_rip_all(s
, 0);
1032 ehci_queues_rip_all(s
, 1);
1033 qemu_del_timer(s
->frame_timer
);
1034 qemu_bh_cancel(s
->async_bh
);
1037 static uint32_t ehci_mem_readb(void *ptr
, target_phys_addr_t addr
)
1042 val
= s
->mmio
[addr
];
1047 static uint32_t ehci_mem_readw(void *ptr
, target_phys_addr_t addr
)
1052 val
= s
->mmio
[addr
] | (s
->mmio
[addr
+1] << 8);
1057 static uint32_t ehci_mem_readl(void *ptr
, target_phys_addr_t addr
)
1062 val
= s
->mmio
[addr
] | (s
->mmio
[addr
+1] << 8) |
1063 (s
->mmio
[addr
+2] << 16) | (s
->mmio
[addr
+3] << 24);
1065 trace_usb_ehci_mmio_readl(addr
, addr2str(addr
), val
);
1069 static void ehci_mem_writeb(void *ptr
, target_phys_addr_t addr
, uint32_t val
)
1071 fprintf(stderr
, "EHCI doesn't handle byte writes to MMIO\n");
1075 static void ehci_mem_writew(void *ptr
, target_phys_addr_t addr
, uint32_t val
)
1077 fprintf(stderr
, "EHCI doesn't handle 16-bit writes to MMIO\n");
1081 static void handle_port_owner_write(EHCIState
*s
, int port
, uint32_t owner
)
1083 USBDevice
*dev
= s
->ports
[port
].dev
;
1084 uint32_t *portsc
= &s
->portsc
[port
];
1087 if (s
->companion_ports
[port
] == NULL
)
1090 owner
= owner
& PORTSC_POWNER
;
1091 orig
= *portsc
& PORTSC_POWNER
;
1093 if (!(owner
^ orig
)) {
1097 if (dev
&& dev
->attached
) {
1098 usb_detach(&s
->ports
[port
]);
1101 *portsc
&= ~PORTSC_POWNER
;
1104 if (dev
&& dev
->attached
) {
1105 usb_attach(&s
->ports
[port
]);
1109 static void handle_port_status_write(EHCIState
*s
, int port
, uint32_t val
)
1111 uint32_t *portsc
= &s
->portsc
[port
];
1112 USBDevice
*dev
= s
->ports
[port
].dev
;
1114 /* Clear rwc bits */
1115 *portsc
&= ~(val
& PORTSC_RWC_MASK
);
1116 /* The guest may clear, but not set the PED bit */
1117 *portsc
&= val
| ~PORTSC_PED
;
1118 /* POWNER is masked out by RO_MASK as it is RO when we've no companion */
1119 handle_port_owner_write(s
, port
, val
);
1120 /* And finally apply RO_MASK */
1121 val
&= PORTSC_RO_MASK
;
1123 if ((val
& PORTSC_PRESET
) && !(*portsc
& PORTSC_PRESET
)) {
1124 trace_usb_ehci_port_reset(port
, 1);
1127 if (!(val
& PORTSC_PRESET
) &&(*portsc
& PORTSC_PRESET
)) {
1128 trace_usb_ehci_port_reset(port
, 0);
1129 if (dev
&& dev
->attached
) {
1130 usb_port_reset(&s
->ports
[port
]);
1131 *portsc
&= ~PORTSC_CSC
;
1135 * Table 2.16 Set the enable bit(and enable bit change) to indicate
1136 * to SW that this port has a high speed device attached
1138 if (dev
&& dev
->attached
&& (dev
->speedmask
& USB_SPEED_MASK_HIGH
)) {
1143 *portsc
&= ~PORTSC_RO_MASK
;
1147 static void ehci_mem_writel(void *ptr
, target_phys_addr_t addr
, uint32_t val
)
1150 uint32_t *mmio
= (uint32_t *)(&s
->mmio
[addr
]);
1151 uint32_t old
= *mmio
;
1154 trace_usb_ehci_mmio_writel(addr
, addr2str(addr
), val
);
1156 /* Only aligned reads are allowed on OHCI */
1158 fprintf(stderr
, "usb-ehci: Mis-aligned write to addr 0x"
1159 TARGET_FMT_plx
"\n", addr
);
1163 if (addr
>= PORTSC
&& addr
< PORTSC
+ 4 * NB_PORTS
) {
1164 handle_port_status_write(s
, (addr
-PORTSC
)/4, val
);
1165 trace_usb_ehci_mmio_change(addr
, addr2str(addr
), *mmio
, old
);
1169 if (addr
< OPREGBASE
) {
1170 fprintf(stderr
, "usb-ehci: write attempt to read-only register"
1171 TARGET_FMT_plx
"\n", addr
);
1176 /* Do any register specific pre-write processing here. */
1179 if (val
& USBCMD_HCRESET
) {
1185 if (((USBCMD_RUNSTOP
| USBCMD_PSE
| USBCMD_ASE
) & val
) !=
1186 ((USBCMD_RUNSTOP
| USBCMD_PSE
| USBCMD_ASE
) & s
->usbcmd
)) {
1187 if (s
->pstate
== EST_INACTIVE
) {
1188 SET_LAST_RUN_CLOCK(s
);
1190 ehci_update_halt(s
);
1191 s
->async_stepdown
= 0;
1192 qemu_mod_timer(s
->frame_timer
, qemu_get_clock_ns(vm_clock
));
1195 /* not supporting dynamic frame list size at the moment */
1196 if ((val
& USBCMD_FLS
) && !(s
->usbcmd
& USBCMD_FLS
)) {
1197 fprintf(stderr
, "attempt to set frame list size -- value %d\n",
1204 val
&= USBSTS_RO_MASK
; // bits 6 through 31 are RO
1205 ehci_clear_usbsts(s
, val
); // bits 0 through 5 are R/WC
1211 val
&= USBINTR_MASK
;
1215 val
&= 0x00003ff8; /* frindex is 14bits and always a multiple of 8 */
1221 for(i
= 0; i
< NB_PORTS
; i
++)
1222 handle_port_owner_write(s
, i
, 0);
1226 case PERIODICLISTBASE
:
1227 if (ehci_periodic_enabled(s
)) {
1229 "ehci: PERIODIC list base register set while periodic schedule\n"
1230 " is enabled and HC is enabled\n");
1235 if (ehci_async_enabled(s
)) {
1237 "ehci: ASYNC list address register set while async schedule\n"
1238 " is enabled and HC is enabled\n");
1244 trace_usb_ehci_mmio_change(addr
, addr2str(addr
), *mmio
, old
);
1248 // TODO : Put in common header file, duplication from usb-ohci.c
1250 /* Get an array of dwords from main memory */
1251 static inline int get_dwords(EHCIState
*ehci
, uint32_t addr
,
1252 uint32_t *buf
, int num
)
1256 for(i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
1257 pci_dma_read(&ehci
->dev
, addr
, buf
, sizeof(*buf
));
1258 *buf
= le32_to_cpu(*buf
);
1264 /* Put an array of dwords in to main memory */
1265 static inline int put_dwords(EHCIState
*ehci
, uint32_t addr
,
1266 uint32_t *buf
, int num
)
1270 for(i
= 0; i
< num
; i
++, buf
++, addr
+= sizeof(*buf
)) {
1271 uint32_t tmp
= cpu_to_le32(*buf
);
1272 pci_dma_write(&ehci
->dev
, addr
, &tmp
, sizeof(tmp
));
1279 * Write the qh back to guest physical memory. This step isn't
1280 * in the EHCI spec but we need to do it since we don't share
1281 * physical memory with our guest VM.
1283 * The first three dwords are read-only for the EHCI, so skip them
1284 * when writing back the qh.
1286 static void ehci_flush_qh(EHCIQueue
*q
)
1288 uint32_t *qh
= (uint32_t *) &q
->qh
;
1289 uint32_t dwords
= sizeof(EHCIqh
) >> 2;
1290 uint32_t addr
= NLPTR_GET(q
->qhaddr
);
1292 put_dwords(q
->ehci
, addr
+ 3 * sizeof(uint32_t), qh
+ 3, dwords
- 3);
1297 static int ehci_qh_do_overlay(EHCIQueue
*q
)
1299 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
1307 assert(p
->qtdaddr
== q
->qtdaddr
);
1309 // remember values in fields to preserve in qh after overlay
1311 dtoggle
= q
->qh
.token
& QTD_TOKEN_DTOGGLE
;
1312 ping
= q
->qh
.token
& QTD_TOKEN_PING
;
1314 q
->qh
.current_qtd
= p
->qtdaddr
;
1315 q
->qh
.next_qtd
= p
->qtd
.next
;
1316 q
->qh
.altnext_qtd
= p
->qtd
.altnext
;
1317 q
->qh
.token
= p
->qtd
.token
;
1320 eps
= get_field(q
->qh
.epchar
, QH_EPCHAR_EPS
);
1321 if (eps
== EHCI_QH_EPS_HIGH
) {
1322 q
->qh
.token
&= ~QTD_TOKEN_PING
;
1323 q
->qh
.token
|= ping
;
1326 reload
= get_field(q
->qh
.epchar
, QH_EPCHAR_RL
);
1327 set_field(&q
->qh
.altnext_qtd
, reload
, QH_ALTNEXT_NAKCNT
);
1329 for (i
= 0; i
< 5; i
++) {
1330 q
->qh
.bufptr
[i
] = p
->qtd
.bufptr
[i
];
1333 if (!(q
->qh
.epchar
& QH_EPCHAR_DTC
)) {
1334 // preserve QH DT bit
1335 q
->qh
.token
&= ~QTD_TOKEN_DTOGGLE
;
1336 q
->qh
.token
|= dtoggle
;
1339 q
->qh
.bufptr
[1] &= ~BUFPTR_CPROGMASK_MASK
;
1340 q
->qh
.bufptr
[2] &= ~BUFPTR_FRAMETAG_MASK
;
1347 static int ehci_init_transfer(EHCIPacket
*p
)
1349 uint32_t cpage
, offset
, bytes
, plen
;
1352 cpage
= get_field(p
->qtd
.token
, QTD_TOKEN_CPAGE
);
1353 bytes
= get_field(p
->qtd
.token
, QTD_TOKEN_TBYTES
);
1354 offset
= p
->qtd
.bufptr
[0] & ~QTD_BUFPTR_MASK
;
1355 pci_dma_sglist_init(&p
->sgl
, &p
->queue
->ehci
->dev
, 5);
1359 fprintf(stderr
, "cpage out of range (%d)\n", cpage
);
1360 return USB_RET_PROCERR
;
1363 page
= p
->qtd
.bufptr
[cpage
] & QTD_BUFPTR_MASK
;
1366 if (plen
> 4096 - offset
) {
1367 plen
= 4096 - offset
;
1372 qemu_sglist_add(&p
->sgl
, page
, plen
);
1378 static void ehci_finish_transfer(EHCIQueue
*q
, int status
)
1380 uint32_t cpage
, offset
;
1383 /* update cpage & offset */
1384 cpage
= get_field(q
->qh
.token
, QTD_TOKEN_CPAGE
);
1385 offset
= q
->qh
.bufptr
[0] & ~QTD_BUFPTR_MASK
;
1388 cpage
+= offset
>> QTD_BUFPTR_SH
;
1389 offset
&= ~QTD_BUFPTR_MASK
;
1391 set_field(&q
->qh
.token
, cpage
, QTD_TOKEN_CPAGE
);
1392 q
->qh
.bufptr
[0] &= QTD_BUFPTR_MASK
;
1393 q
->qh
.bufptr
[0] |= offset
;
1397 static void ehci_async_complete_packet(USBPort
*port
, USBPacket
*packet
)
1400 EHCIState
*s
= port
->opaque
;
1401 uint32_t portsc
= s
->portsc
[port
->index
];
1403 if (portsc
& PORTSC_POWNER
) {
1404 USBPort
*companion
= s
->companion_ports
[port
->index
];
1405 companion
->ops
->complete(companion
, packet
);
1409 p
= container_of(packet
, EHCIPacket
, packet
);
1410 trace_usb_ehci_packet_action(p
->queue
, p
, "wakeup");
1411 assert(p
->async
== EHCI_ASYNC_INFLIGHT
);
1412 p
->async
= EHCI_ASYNC_FINISHED
;
1413 p
->usb_status
= packet
->result
;
1415 if (p
->queue
->async
) {
1416 qemu_bh_schedule(p
->queue
->ehci
->async_bh
);
1420 static void ehci_execute_complete(EHCIQueue
*q
)
1422 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
1425 assert(p
->qtdaddr
== q
->qtdaddr
);
1426 assert(p
->async
!= EHCI_ASYNC_INFLIGHT
);
1427 p
->async
= EHCI_ASYNC_NONE
;
1429 DPRINTF("execute_complete: qhaddr 0x%x, next %x, qtdaddr 0x%x, status %d\n",
1430 q
->qhaddr
, q
->qh
.next
, q
->qtdaddr
, q
->usb_status
);
1432 if (p
->usb_status
< 0) {
1433 switch (p
->usb_status
) {
1434 case USB_RET_IOERROR
:
1436 q
->qh
.token
|= (QTD_TOKEN_HALT
| QTD_TOKEN_XACTERR
);
1437 set_field(&q
->qh
.token
, 0, QTD_TOKEN_CERR
);
1438 ehci_raise_irq(q
->ehci
, USBSTS_ERRINT
);
1441 q
->qh
.token
|= QTD_TOKEN_HALT
;
1442 ehci_raise_irq(q
->ehci
, USBSTS_ERRINT
);
1445 set_field(&q
->qh
.altnext_qtd
, 0, QH_ALTNEXT_NAKCNT
);
1446 return; /* We're not done yet with this transaction */
1447 case USB_RET_BABBLE
:
1448 q
->qh
.token
|= (QTD_TOKEN_HALT
| QTD_TOKEN_BABBLE
);
1449 ehci_raise_irq(q
->ehci
, USBSTS_ERRINT
);
1452 /* should not be triggerable */
1453 fprintf(stderr
, "USB invalid response %d\n", p
->usb_status
);
1457 } else if ((p
->usb_status
> p
->tbytes
) && (p
->pid
== USB_TOKEN_IN
)) {
1458 p
->usb_status
= USB_RET_BABBLE
;
1459 q
->qh
.token
|= (QTD_TOKEN_HALT
| QTD_TOKEN_BABBLE
);
1460 ehci_raise_irq(q
->ehci
, USBSTS_ERRINT
);
1462 // TODO check 4.12 for splits
1464 if (p
->tbytes
&& p
->pid
== USB_TOKEN_IN
) {
1465 p
->tbytes
-= p
->usb_status
;
1470 DPRINTF("updating tbytes to %d\n", p
->tbytes
);
1471 set_field(&q
->qh
.token
, p
->tbytes
, QTD_TOKEN_TBYTES
);
1473 ehci_finish_transfer(q
, p
->usb_status
);
1474 usb_packet_unmap(&p
->packet
, &p
->sgl
);
1475 qemu_sglist_destroy(&p
->sgl
);
1477 q
->qh
.token
^= QTD_TOKEN_DTOGGLE
;
1478 q
->qh
.token
&= ~QTD_TOKEN_ACTIVE
;
1480 if (q
->qh
.token
& QTD_TOKEN_IOC
) {
1481 ehci_raise_irq(q
->ehci
, USBSTS_INT
);
1487 static int ehci_execute(EHCIPacket
*p
, const char *action
)
1493 if (!(p
->qtd
.token
& QTD_TOKEN_ACTIVE
)) {
1494 fprintf(stderr
, "Attempting to execute inactive qtd\n");
1495 return USB_RET_PROCERR
;
1498 p
->tbytes
= (p
->qtd
.token
& QTD_TOKEN_TBYTES_MASK
) >> QTD_TOKEN_TBYTES_SH
;
1499 if (p
->tbytes
> BUFF_SIZE
) {
1500 fprintf(stderr
, "Request for more bytes than allowed\n");
1501 return USB_RET_PROCERR
;
1504 p
->pid
= (p
->qtd
.token
& QTD_TOKEN_PID_MASK
) >> QTD_TOKEN_PID_SH
;
1507 p
->pid
= USB_TOKEN_OUT
;
1510 p
->pid
= USB_TOKEN_IN
;
1513 p
->pid
= USB_TOKEN_SETUP
;
1516 fprintf(stderr
, "bad token\n");
1520 if (ehci_init_transfer(p
) != 0) {
1521 return USB_RET_PROCERR
;
1524 endp
= get_field(p
->queue
->qh
.epchar
, QH_EPCHAR_EP
);
1525 ep
= usb_ep_get(p
->queue
->dev
, p
->pid
, endp
);
1527 usb_packet_setup(&p
->packet
, p
->pid
, ep
);
1528 usb_packet_map(&p
->packet
, &p
->sgl
);
1530 trace_usb_ehci_packet_action(p
->queue
, p
, action
);
1531 ret
= usb_handle_packet(p
->queue
->dev
, &p
->packet
);
1532 DPRINTF("submit: qh %x next %x qtd %x pid %x len %zd "
1533 "(total %d) endp %x ret %d\n",
1534 q
->qhaddr
, q
->qh
.next
, q
->qtdaddr
, q
->pid
,
1535 q
->packet
.iov
.size
, q
->tbytes
, endp
, ret
);
1537 if (ret
> BUFF_SIZE
) {
1538 fprintf(stderr
, "ret from usb_handle_packet > BUFF_SIZE\n");
1539 return USB_RET_PROCERR
;
1548 static int ehci_process_itd(EHCIState
*ehci
,
1554 uint32_t i
, len
, pid
, dir
, devaddr
, endp
;
1555 uint32_t pg
, off
, ptr1
, ptr2
, max
, mult
;
1557 dir
=(itd
->bufptr
[1] & ITD_BUFPTR_DIRECTION
);
1558 devaddr
= get_field(itd
->bufptr
[0], ITD_BUFPTR_DEVADDR
);
1559 endp
= get_field(itd
->bufptr
[0], ITD_BUFPTR_EP
);
1560 max
= get_field(itd
->bufptr
[1], ITD_BUFPTR_MAXPKT
);
1561 mult
= get_field(itd
->bufptr
[2], ITD_BUFPTR_MULT
);
1563 for(i
= 0; i
< 8; i
++) {
1564 if (itd
->transact
[i
] & ITD_XACT_ACTIVE
) {
1565 pg
= get_field(itd
->transact
[i
], ITD_XACT_PGSEL
);
1566 off
= itd
->transact
[i
] & ITD_XACT_OFFSET_MASK
;
1567 ptr1
= (itd
->bufptr
[pg
] & ITD_BUFPTR_MASK
);
1568 ptr2
= (itd
->bufptr
[pg
+1] & ITD_BUFPTR_MASK
);
1569 len
= get_field(itd
->transact
[i
], ITD_XACT_LENGTH
);
1571 if (len
> max
* mult
) {
1575 if (len
> BUFF_SIZE
) {
1576 return USB_RET_PROCERR
;
1579 pci_dma_sglist_init(&ehci
->isgl
, &ehci
->dev
, 2);
1580 if (off
+ len
> 4096) {
1581 /* transfer crosses page border */
1582 uint32_t len2
= off
+ len
- 4096;
1583 uint32_t len1
= len
- len2
;
1584 qemu_sglist_add(&ehci
->isgl
, ptr1
+ off
, len1
);
1585 qemu_sglist_add(&ehci
->isgl
, ptr2
, len2
);
1587 qemu_sglist_add(&ehci
->isgl
, ptr1
+ off
, len
);
1590 pid
= dir
? USB_TOKEN_IN
: USB_TOKEN_OUT
;
1592 dev
= ehci_find_device(ehci
, devaddr
);
1593 ep
= usb_ep_get(dev
, pid
, endp
);
1594 if (ep
->type
== USB_ENDPOINT_XFER_ISOC
) {
1595 usb_packet_setup(&ehci
->ipacket
, pid
, ep
);
1596 usb_packet_map(&ehci
->ipacket
, &ehci
->isgl
);
1597 ret
= usb_handle_packet(dev
, &ehci
->ipacket
);
1598 assert(ret
!= USB_RET_ASYNC
);
1599 usb_packet_unmap(&ehci
->ipacket
, &ehci
->isgl
);
1601 DPRINTF("ISOCH: attempt to addess non-iso endpoint\n");
1604 qemu_sglist_destroy(&ehci
->isgl
);
1609 fprintf(stderr
, "Unexpected iso usb result: %d\n", ret
);
1611 case USB_RET_IOERROR
:
1613 /* 3.3.2: XACTERR is only allowed on IN transactions */
1615 itd
->transact
[i
] |= ITD_XACT_XACTERR
;
1616 ehci_raise_irq(ehci
, USBSTS_ERRINT
);
1619 case USB_RET_BABBLE
:
1620 itd
->transact
[i
] |= ITD_XACT_BABBLE
;
1621 ehci_raise_irq(ehci
, USBSTS_ERRINT
);
1624 /* no data for us, so do a zero-length transfer */
1632 set_field(&itd
->transact
[i
], len
- ret
, ITD_XACT_LENGTH
);
1635 set_field(&itd
->transact
[i
], ret
, ITD_XACT_LENGTH
);
1638 if (itd
->transact
[i
] & ITD_XACT_IOC
) {
1639 ehci_raise_irq(ehci
, USBSTS_INT
);
1641 itd
->transact
[i
] &= ~ITD_XACT_ACTIVE
;
1648 /* This state is the entry point for asynchronous schedule
1649 * processing. Entry here consitutes a EHCI start event state (4.8.5)
1651 static int ehci_state_waitlisthead(EHCIState
*ehci
, int async
)
1656 uint32_t entry
= ehci
->asynclistaddr
;
1658 /* set reclamation flag at start event (4.8.6) */
1660 ehci_set_usbsts(ehci
, USBSTS_REC
);
1663 ehci_queues_rip_unused(ehci
, async
);
1665 /* Find the head of the list (4.9.1.1) */
1666 for(i
= 0; i
< MAX_QH
; i
++) {
1667 get_dwords(ehci
, NLPTR_GET(entry
), (uint32_t *) &qh
,
1668 sizeof(EHCIqh
) >> 2);
1669 ehci_trace_qh(NULL
, NLPTR_GET(entry
), &qh
);
1671 if (qh
.epchar
& QH_EPCHAR_H
) {
1673 entry
|= (NLPTR_TYPE_QH
<< 1);
1676 ehci_set_fetch_addr(ehci
, async
, entry
);
1677 ehci_set_state(ehci
, async
, EST_FETCHENTRY
);
1683 if (entry
== ehci
->asynclistaddr
) {
1688 /* no head found for list. */
1690 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1697 /* This state is the entry point for periodic schedule processing as
1698 * well as being a continuation state for async processing.
1700 static int ehci_state_fetchentry(EHCIState
*ehci
, int async
)
1703 uint32_t entry
= ehci_get_fetch_addr(ehci
, async
);
1705 if (NLPTR_TBIT(entry
)) {
1706 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1710 /* section 4.8, only QH in async schedule */
1711 if (async
&& (NLPTR_TYPE_GET(entry
) != NLPTR_TYPE_QH
)) {
1712 fprintf(stderr
, "non queue head request in async schedule\n");
1716 switch (NLPTR_TYPE_GET(entry
)) {
1718 ehci_set_state(ehci
, async
, EST_FETCHQH
);
1722 case NLPTR_TYPE_ITD
:
1723 ehci_set_state(ehci
, async
, EST_FETCHITD
);
1727 case NLPTR_TYPE_STITD
:
1728 ehci_set_state(ehci
, async
, EST_FETCHSITD
);
1733 /* TODO: handle FSTN type */
1734 fprintf(stderr
, "FETCHENTRY: entry at %X is of type %d "
1735 "which is not supported yet\n", entry
, NLPTR_TYPE_GET(entry
));
1743 static EHCIQueue
*ehci_state_fetchqh(EHCIState
*ehci
, int async
)
1746 uint32_t entry
, devaddr
;
1750 entry
= ehci_get_fetch_addr(ehci
, async
);
1751 q
= ehci_find_queue_by_qh(ehci
, entry
, async
);
1753 q
= ehci_alloc_queue(ehci
, entry
, async
);
1755 p
= QTAILQ_FIRST(&q
->packets
);
1759 /* we are going in circles -- stop processing */
1760 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1765 get_dwords(ehci
, NLPTR_GET(q
->qhaddr
),
1766 (uint32_t *) &qh
, sizeof(EHCIqh
) >> 2);
1767 if (q
->revalidate
&& (q
->qh
.epchar
!= qh
.epchar
||
1768 q
->qh
.epcap
!= qh
.epcap
||
1769 q
->qh
.current_qtd
!= qh
.current_qtd
)) {
1771 q
= ehci_alloc_queue(ehci
, entry
, async
);
1777 ehci_trace_qh(q
, NLPTR_GET(q
->qhaddr
), &q
->qh
);
1779 devaddr
= get_field(q
->qh
.epchar
, QH_EPCHAR_DEVADDR
);
1780 if (q
->dev
!= NULL
&& q
->dev
->addr
!= devaddr
) {
1781 if (!QTAILQ_EMPTY(&q
->packets
)) {
1782 /* should not happen (guest bug) */
1783 while ((p
= QTAILQ_FIRST(&q
->packets
)) != NULL
) {
1784 ehci_free_packet(p
);
1789 if (q
->dev
== NULL
) {
1790 q
->dev
= ehci_find_device(q
->ehci
, devaddr
);
1793 if (p
&& p
->async
== EHCI_ASYNC_INFLIGHT
) {
1794 /* I/O still in progress -- skip queue */
1795 ehci_set_state(ehci
, async
, EST_HORIZONTALQH
);
1798 if (p
&& p
->async
== EHCI_ASYNC_FINISHED
) {
1799 /* I/O finished -- continue processing queue */
1800 trace_usb_ehci_packet_action(p
->queue
, p
, "complete");
1801 ehci_set_state(ehci
, async
, EST_EXECUTING
);
1805 if (async
&& (q
->qh
.epchar
& QH_EPCHAR_H
)) {
1807 /* EHCI spec version 1.0 Section 4.8.3 & 4.10.1 */
1808 if (ehci
->usbsts
& USBSTS_REC
) {
1809 ehci_clear_usbsts(ehci
, USBSTS_REC
);
1811 DPRINTF("FETCHQH: QH 0x%08x. H-bit set, reclamation status reset"
1812 " - done processing\n", q
->qhaddr
);
1813 ehci_set_state(ehci
, async
, EST_ACTIVE
);
1820 if (q
->qhaddr
!= q
->qh
.next
) {
1821 DPRINTF("FETCHQH: QH 0x%08x (h %x halt %x active %x) next 0x%08x\n",
1823 q
->qh
.epchar
& QH_EPCHAR_H
,
1824 q
->qh
.token
& QTD_TOKEN_HALT
,
1825 q
->qh
.token
& QTD_TOKEN_ACTIVE
,
1830 if (q
->qh
.token
& QTD_TOKEN_HALT
) {
1831 ehci_set_state(ehci
, async
, EST_HORIZONTALQH
);
1833 } else if ((q
->qh
.token
& QTD_TOKEN_ACTIVE
) &&
1834 (NLPTR_TBIT(q
->qh
.current_qtd
) == 0)) {
1835 q
->qtdaddr
= q
->qh
.current_qtd
;
1836 ehci_set_state(ehci
, async
, EST_FETCHQTD
);
1839 /* EHCI spec version 1.0 Section 4.10.2 */
1840 ehci_set_state(ehci
, async
, EST_ADVANCEQUEUE
);
1847 static int ehci_state_fetchitd(EHCIState
*ehci
, int async
)
1853 entry
= ehci_get_fetch_addr(ehci
, async
);
1855 get_dwords(ehci
, NLPTR_GET(entry
), (uint32_t *) &itd
,
1856 sizeof(EHCIitd
) >> 2);
1857 ehci_trace_itd(ehci
, entry
, &itd
);
1859 if (ehci_process_itd(ehci
, &itd
) != 0) {
1863 put_dwords(ehci
, NLPTR_GET(entry
), (uint32_t *) &itd
,
1864 sizeof(EHCIitd
) >> 2);
1865 ehci_set_fetch_addr(ehci
, async
, itd
.next
);
1866 ehci_set_state(ehci
, async
, EST_FETCHENTRY
);
1871 static int ehci_state_fetchsitd(EHCIState
*ehci
, int async
)
1877 entry
= ehci_get_fetch_addr(ehci
, async
);
1879 get_dwords(ehci
, NLPTR_GET(entry
), (uint32_t *)&sitd
,
1880 sizeof(EHCIsitd
) >> 2);
1881 ehci_trace_sitd(ehci
, entry
, &sitd
);
1883 if (!(sitd
.results
& SITD_RESULTS_ACTIVE
)) {
1884 /* siTD is not active, nothing to do */;
1886 /* TODO: split transfers are not implemented */
1887 fprintf(stderr
, "WARNING: Skipping active siTD\n");
1890 ehci_set_fetch_addr(ehci
, async
, sitd
.next
);
1891 ehci_set_state(ehci
, async
, EST_FETCHENTRY
);
1895 /* Section 4.10.2 - paragraph 3 */
1896 static int ehci_state_advqueue(EHCIQueue
*q
)
1899 /* TO-DO: 4.10.2 - paragraph 2
1900 * if I-bit is set to 1 and QH is not active
1901 * go to horizontal QH
1904 ehci_set_state(ehci
, async
, EST_HORIZONTALQH
);
1910 * want data and alt-next qTD is valid
1912 if (((q
->qh
.token
& QTD_TOKEN_TBYTES_MASK
) != 0) &&
1913 (NLPTR_TBIT(q
->qh
.altnext_qtd
) == 0)) {
1914 q
->qtdaddr
= q
->qh
.altnext_qtd
;
1915 ehci_set_state(q
->ehci
, q
->async
, EST_FETCHQTD
);
1920 } else if (NLPTR_TBIT(q
->qh
.next_qtd
) == 0) {
1921 q
->qtdaddr
= q
->qh
.next_qtd
;
1922 ehci_set_state(q
->ehci
, q
->async
, EST_FETCHQTD
);
1925 * no valid qTD, try next QH
1928 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
1934 /* Section 4.10.2 - paragraph 4 */
1935 static int ehci_state_fetchqtd(EHCIQueue
*q
)
1941 get_dwords(q
->ehci
, NLPTR_GET(q
->qtdaddr
), (uint32_t *) &qtd
,
1942 sizeof(EHCIqtd
) >> 2);
1943 ehci_trace_qtd(q
, NLPTR_GET(q
->qtdaddr
), &qtd
);
1945 p
= QTAILQ_FIRST(&q
->packets
);
1946 while (p
!= NULL
&& p
->qtdaddr
!= q
->qtdaddr
) {
1947 /* should not happen (guest bug) */
1948 ehci_free_packet(p
);
1949 p
= QTAILQ_FIRST(&q
->packets
);
1952 ehci_qh_do_overlay(q
);
1954 if (p
->async
== EHCI_ASYNC_INFLIGHT
) {
1955 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
1957 ehci_set_state(q
->ehci
, q
->async
, EST_EXECUTING
);
1960 } else if (qtd
.token
& QTD_TOKEN_ACTIVE
) {
1961 p
= ehci_alloc_packet(q
);
1962 p
->qtdaddr
= q
->qtdaddr
;
1964 ehci_set_state(q
->ehci
, q
->async
, EST_EXECUTE
);
1967 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
1974 static int ehci_state_horizqh(EHCIQueue
*q
)
1978 if (ehci_get_fetch_addr(q
->ehci
, q
->async
) != q
->qh
.next
) {
1979 ehci_set_fetch_addr(q
->ehci
, q
->async
, q
->qh
.next
);
1980 ehci_set_state(q
->ehci
, q
->async
, EST_FETCHENTRY
);
1983 ehci_set_state(q
->ehci
, q
->async
, EST_ACTIVE
);
1989 static void ehci_fill_queue(EHCIPacket
*p
)
1991 EHCIQueue
*q
= p
->queue
;
1992 EHCIqtd qtd
= p
->qtd
;
1996 if (NLPTR_TBIT(qtd
.altnext
) == 0) {
1999 if (NLPTR_TBIT(qtd
.next
) != 0) {
2003 get_dwords(q
->ehci
, NLPTR_GET(qtdaddr
),
2004 (uint32_t *) &qtd
, sizeof(EHCIqtd
) >> 2);
2005 ehci_trace_qtd(q
, NLPTR_GET(qtdaddr
), &qtd
);
2006 if (!(qtd
.token
& QTD_TOKEN_ACTIVE
)) {
2009 p
= ehci_alloc_packet(q
);
2010 p
->qtdaddr
= qtdaddr
;
2012 p
->usb_status
= ehci_execute(p
, "queue");
2013 assert(p
->usb_status
= USB_RET_ASYNC
);
2014 p
->async
= EHCI_ASYNC_INFLIGHT
;
2018 static int ehci_state_execute(EHCIQueue
*q
)
2020 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
2024 assert(p
->qtdaddr
== q
->qtdaddr
);
2026 if (ehci_qh_do_overlay(q
) != 0) {
2030 // TODO verify enough time remains in the uframe as in 4.4.1.1
2031 // TODO write back ptr to async list when done or out of time
2032 // TODO Windows does not seem to ever set the MULT field
2035 int transactCtr
= get_field(q
->qh
.epcap
, QH_EPCAP_MULT
);
2037 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
2044 ehci_set_usbsts(q
->ehci
, USBSTS_REC
);
2047 p
->usb_status
= ehci_execute(p
, "process");
2048 if (p
->usb_status
== USB_RET_PROCERR
) {
2052 if (p
->usb_status
== USB_RET_ASYNC
) {
2054 trace_usb_ehci_packet_action(p
->queue
, p
, "async");
2055 p
->async
= EHCI_ASYNC_INFLIGHT
;
2056 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
2062 ehci_set_state(q
->ehci
, q
->async
, EST_EXECUTING
);
2069 static int ehci_state_executing(EHCIQueue
*q
)
2071 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
2075 assert(p
->qtdaddr
== q
->qtdaddr
);
2077 ehci_execute_complete(q
);
2078 if (p
->usb_status
== USB_RET_ASYNC
) {
2081 if (p
->usb_status
== USB_RET_PROCERR
) {
2088 int transactCtr
= get_field(q
->qh
.epcap
, QH_EPCAP_MULT
);
2090 set_field(&q
->qh
.epcap
, transactCtr
, QH_EPCAP_MULT
);
2091 // 4.10.3, bottom of page 82, should exit this state when transaction
2092 // counter decrements to 0
2096 if (p
->usb_status
== USB_RET_NAK
) {
2097 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
2099 ehci_set_state(q
->ehci
, q
->async
, EST_WRITEBACK
);
2110 static int ehci_state_writeback(EHCIQueue
*q
)
2112 EHCIPacket
*p
= QTAILQ_FIRST(&q
->packets
);
2113 uint32_t *qtd
, addr
;
2116 /* Write back the QTD from the QH area */
2118 assert(p
->qtdaddr
== q
->qtdaddr
);
2120 ehci_trace_qtd(q
, NLPTR_GET(p
->qtdaddr
), (EHCIqtd
*) &q
->qh
.next_qtd
);
2121 qtd
= (uint32_t *) &q
->qh
.next_qtd
;
2122 addr
= NLPTR_GET(p
->qtdaddr
);
2123 put_dwords(q
->ehci
, addr
+ 2 * sizeof(uint32_t), qtd
+ 2, 2);
2124 ehci_free_packet(p
);
2127 * EHCI specs say go horizontal here.
2129 * We can also advance the queue here for performance reasons. We
2130 * need to take care to only take that shortcut in case we've
2131 * processed the qtd just written back without errors, i.e. halt
2134 if (q
->qh
.token
& QTD_TOKEN_HALT
) {
2135 ehci_set_state(q
->ehci
, q
->async
, EST_HORIZONTALQH
);
2138 ehci_set_state(q
->ehci
, q
->async
, EST_ADVANCEQUEUE
);
2145 * This is the state machine that is common to both async and periodic
2148 static void ehci_advance_state(EHCIState
*ehci
, int async
)
2150 EHCIQueue
*q
= NULL
;
2154 switch(ehci_get_state(ehci
, async
)) {
2155 case EST_WAITLISTHEAD
:
2156 again
= ehci_state_waitlisthead(ehci
, async
);
2159 case EST_FETCHENTRY
:
2160 again
= ehci_state_fetchentry(ehci
, async
);
2164 q
= ehci_state_fetchqh(ehci
, async
);
2166 assert(q
->async
== async
);
2174 again
= ehci_state_fetchitd(ehci
, async
);
2178 again
= ehci_state_fetchsitd(ehci
, async
);
2181 case EST_ADVANCEQUEUE
:
2182 again
= ehci_state_advqueue(q
);
2186 again
= ehci_state_fetchqtd(q
);
2189 case EST_HORIZONTALQH
:
2190 again
= ehci_state_horizqh(q
);
2194 again
= ehci_state_execute(q
);
2196 ehci
->async_stepdown
= 0;
2203 ehci
->async_stepdown
= 0;
2205 again
= ehci_state_executing(q
);
2210 again
= ehci_state_writeback(q
);
2214 fprintf(stderr
, "Bad state!\n");
2221 fprintf(stderr
, "processing error - resetting ehci HC\n");
2229 static void ehci_advance_async_state(EHCIState
*ehci
)
2231 const int async
= 1;
2233 switch(ehci_get_state(ehci
, async
)) {
2235 if (!ehci_async_enabled(ehci
)) {
2238 ehci_set_state(ehci
, async
, EST_ACTIVE
);
2239 // No break, fall through to ACTIVE
2242 if (!ehci_async_enabled(ehci
)) {
2243 ehci_queues_rip_all(ehci
, async
);
2244 ehci_set_state(ehci
, async
, EST_INACTIVE
);
2248 /* make sure guest has acknowledged the doorbell interrupt */
2249 /* TO-DO: is this really needed? */
2250 if (ehci
->usbsts
& USBSTS_IAA
) {
2251 DPRINTF("IAA status bit still set.\n");
2255 /* check that address register has been set */
2256 if (ehci
->asynclistaddr
== 0) {
2260 ehci_set_state(ehci
, async
, EST_WAITLISTHEAD
);
2261 ehci_advance_state(ehci
, async
);
2263 /* If the doorbell is set, the guest wants to make a change to the
2264 * schedule. The host controller needs to release cached data.
2267 if (ehci
->usbcmd
& USBCMD_IAAD
) {
2268 /* Remove all unseen qhs from the async qhs queue */
2269 ehci_queues_tag_unused_async(ehci
);
2270 DPRINTF("ASYNC: doorbell request acknowledged\n");
2271 ehci
->usbcmd
&= ~USBCMD_IAAD
;
2272 ehci_raise_irq(ehci
, USBSTS_IAA
);
2277 /* this should only be due to a developer mistake */
2278 fprintf(stderr
, "ehci: Bad asynchronous state %d. "
2279 "Resetting to active\n", ehci
->astate
);
2284 static void ehci_advance_periodic_state(EHCIState
*ehci
)
2288 const int async
= 0;
2292 switch(ehci_get_state(ehci
, async
)) {
2294 if (!(ehci
->frindex
& 7) && ehci_periodic_enabled(ehci
)) {
2295 ehci_set_state(ehci
, async
, EST_ACTIVE
);
2296 // No break, fall through to ACTIVE
2301 if (!(ehci
->frindex
& 7) && !ehci_periodic_enabled(ehci
)) {
2302 ehci_queues_rip_all(ehci
, async
);
2303 ehci_set_state(ehci
, async
, EST_INACTIVE
);
2307 list
= ehci
->periodiclistbase
& 0xfffff000;
2308 /* check that register has been set */
2312 list
|= ((ehci
->frindex
& 0x1ff8) >> 1);
2314 pci_dma_read(&ehci
->dev
, list
, &entry
, sizeof entry
);
2315 entry
= le32_to_cpu(entry
);
2317 DPRINTF("PERIODIC state adv fr=%d. [%08X] -> %08X\n",
2318 ehci
->frindex
/ 8, list
, entry
);
2319 ehci_set_fetch_addr(ehci
, async
,entry
);
2320 ehci_set_state(ehci
, async
, EST_FETCHENTRY
);
2321 ehci_advance_state(ehci
, async
);
2322 ehci_queues_rip_unused(ehci
, async
);
2326 /* this should only be due to a developer mistake */
2327 fprintf(stderr
, "ehci: Bad periodic state %d. "
2328 "Resetting to active\n", ehci
->pstate
);
2333 static void ehci_update_frindex(EHCIState
*ehci
, int frames
)
2337 if (!ehci_enabled(ehci
)) {
2341 for (i
= 0; i
< frames
; i
++) {
2344 if (ehci
->frindex
== 0x00002000) {
2345 ehci_raise_irq(ehci
, USBSTS_FLR
);
2348 if (ehci
->frindex
== 0x00004000) {
2349 ehci_raise_irq(ehci
, USBSTS_FLR
);
2351 if (ehci
->usbsts_frindex
> 0x00004000) {
2352 ehci
->usbsts_frindex
-= 0x00004000;
2354 ehci
->usbsts_frindex
= 0;
2360 static void ehci_frame_timer(void *opaque
)
2362 EHCIState
*ehci
= opaque
;
2364 int64_t expire_time
, t_now
;
2365 uint64_t ns_elapsed
;
2366 int frames
, skipped_frames
;
2369 t_now
= qemu_get_clock_ns(vm_clock
);
2370 ns_elapsed
= t_now
- ehci
->last_run_ns
;
2371 frames
= ns_elapsed
/ FRAME_TIMER_NS
;
2373 if (ehci_periodic_enabled(ehci
) || ehci
->pstate
!= EST_INACTIVE
) {
2375 ehci
->async_stepdown
= 0;
2377 if (frames
> ehci
->maxframes
) {
2378 skipped_frames
= frames
- ehci
->maxframes
;
2379 ehci_update_frindex(ehci
, skipped_frames
);
2380 ehci
->last_run_ns
+= FRAME_TIMER_NS
* skipped_frames
;
2381 frames
-= skipped_frames
;
2382 DPRINTF("WARNING - EHCI skipped %d frames\n", skipped_frames
);
2385 for (i
= 0; i
< frames
; i
++) {
2386 ehci_update_frindex(ehci
, 1);
2387 ehci_advance_periodic_state(ehci
);
2388 ehci
->last_run_ns
+= FRAME_TIMER_NS
;
2391 if (ehci
->async_stepdown
< ehci
->maxframes
/ 2) {
2392 ehci
->async_stepdown
++;
2394 ehci_update_frindex(ehci
, frames
);
2395 ehci
->last_run_ns
+= FRAME_TIMER_NS
* frames
;
2398 /* Async is not inside loop since it executes everything it can once
2401 if (ehci_async_enabled(ehci
) || ehci
->astate
!= EST_INACTIVE
) {
2403 ehci_advance_async_state(ehci
);
2406 ehci_commit_irq(ehci
);
2407 if (ehci
->usbsts_pending
) {
2409 ehci
->async_stepdown
= 0;
2413 expire_time
= t_now
+ (get_ticks_per_sec()
2414 * (ehci
->async_stepdown
+1) / FRAME_TIMER_FREQ
);
2415 qemu_mod_timer(ehci
->frame_timer
, expire_time
);
2419 static void ehci_async_bh(void *opaque
)
2421 EHCIState
*ehci
= opaque
;
2422 ehci_advance_async_state(ehci
);
2425 static const MemoryRegionOps ehci_mem_ops
= {
2427 .read
= { ehci_mem_readb
, ehci_mem_readw
, ehci_mem_readl
},
2428 .write
= { ehci_mem_writeb
, ehci_mem_writew
, ehci_mem_writel
},
2430 .endianness
= DEVICE_LITTLE_ENDIAN
,
2433 static int usb_ehci_initfn(PCIDevice
*dev
);
2435 static USBPortOps ehci_port_ops
= {
2436 .attach
= ehci_attach
,
2437 .detach
= ehci_detach
,
2438 .child_detach
= ehci_child_detach
,
2439 .wakeup
= ehci_wakeup
,
2440 .complete
= ehci_async_complete_packet
,
2443 static USBBusOps ehci_bus_ops
= {
2444 .register_companion
= ehci_register_companion
,
2447 static int usb_ehci_post_load(void *opaque
, int version_id
)
2449 EHCIState
*s
= opaque
;
2452 for (i
= 0; i
< NB_PORTS
; i
++) {
2453 USBPort
*companion
= s
->companion_ports
[i
];
2454 if (companion
== NULL
) {
2457 if (s
->portsc
[i
] & PORTSC_POWNER
) {
2458 companion
->dev
= s
->ports
[i
].dev
;
2460 companion
->dev
= NULL
;
2467 static const VMStateDescription vmstate_ehci
= {
2470 .post_load
= usb_ehci_post_load
,
2471 .fields
= (VMStateField
[]) {
2472 VMSTATE_PCI_DEVICE(dev
, EHCIState
),
2473 /* mmio registers */
2474 VMSTATE_UINT32(usbcmd
, EHCIState
),
2475 VMSTATE_UINT32(usbsts
, EHCIState
),
2476 VMSTATE_UINT32(usbintr
, EHCIState
),
2477 VMSTATE_UINT32(frindex
, EHCIState
),
2478 VMSTATE_UINT32(ctrldssegment
, EHCIState
),
2479 VMSTATE_UINT32(periodiclistbase
, EHCIState
),
2480 VMSTATE_UINT32(asynclistaddr
, EHCIState
),
2481 VMSTATE_UINT32(configflag
, EHCIState
),
2482 VMSTATE_UINT32(portsc
[0], EHCIState
),
2483 VMSTATE_UINT32(portsc
[1], EHCIState
),
2484 VMSTATE_UINT32(portsc
[2], EHCIState
),
2485 VMSTATE_UINT32(portsc
[3], EHCIState
),
2486 VMSTATE_UINT32(portsc
[4], EHCIState
),
2487 VMSTATE_UINT32(portsc
[5], EHCIState
),
2489 VMSTATE_TIMER(frame_timer
, EHCIState
),
2490 VMSTATE_UINT64(last_run_ns
, EHCIState
),
2491 VMSTATE_UINT32(async_stepdown
, EHCIState
),
2492 /* schedule state */
2493 VMSTATE_UINT32(astate
, EHCIState
),
2494 VMSTATE_UINT32(pstate
, EHCIState
),
2495 VMSTATE_UINT32(a_fetch_addr
, EHCIState
),
2496 VMSTATE_UINT32(p_fetch_addr
, EHCIState
),
2497 VMSTATE_END_OF_LIST()
2501 static Property ehci_properties
[] = {
2502 DEFINE_PROP_UINT32("maxframes", EHCIState
, maxframes
, 128),
2503 DEFINE_PROP_END_OF_LIST(),
2506 static void ehci_class_init(ObjectClass
*klass
, void *data
)
2508 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2509 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2511 k
->init
= usb_ehci_initfn
;
2512 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
2513 k
->device_id
= PCI_DEVICE_ID_INTEL_82801D
; /* ich4 */
2515 k
->class_id
= PCI_CLASS_SERIAL_USB
;
2516 dc
->vmsd
= &vmstate_ehci
;
2517 dc
->props
= ehci_properties
;
2520 static TypeInfo ehci_info
= {
2522 .parent
= TYPE_PCI_DEVICE
,
2523 .instance_size
= sizeof(EHCIState
),
2524 .class_init
= ehci_class_init
,
2527 static void ich9_ehci_class_init(ObjectClass
*klass
, void *data
)
2529 DeviceClass
*dc
= DEVICE_CLASS(klass
);
2530 PCIDeviceClass
*k
= PCI_DEVICE_CLASS(klass
);
2532 k
->init
= usb_ehci_initfn
;
2533 k
->vendor_id
= PCI_VENDOR_ID_INTEL
;
2534 k
->device_id
= PCI_DEVICE_ID_INTEL_82801I_EHCI1
;
2536 k
->class_id
= PCI_CLASS_SERIAL_USB
;
2537 dc
->vmsd
= &vmstate_ehci
;
2538 dc
->props
= ehci_properties
;
2541 static TypeInfo ich9_ehci_info
= {
2542 .name
= "ich9-usb-ehci1",
2543 .parent
= TYPE_PCI_DEVICE
,
2544 .instance_size
= sizeof(EHCIState
),
2545 .class_init
= ich9_ehci_class_init
,
2548 static int usb_ehci_initfn(PCIDevice
*dev
)
2550 EHCIState
*s
= DO_UPCAST(EHCIState
, dev
, dev
);
2551 uint8_t *pci_conf
= s
->dev
.config
;
2554 pci_set_byte(&pci_conf
[PCI_CLASS_PROG
], 0x20);
2556 /* capabilities pointer */
2557 pci_set_byte(&pci_conf
[PCI_CAPABILITY_LIST
], 0x00);
2558 //pci_set_byte(&pci_conf[PCI_CAPABILITY_LIST], 0x50);
2560 pci_set_byte(&pci_conf
[PCI_INTERRUPT_PIN
], 4); /* interrupt pin D */
2561 pci_set_byte(&pci_conf
[PCI_MIN_GNT
], 0);
2562 pci_set_byte(&pci_conf
[PCI_MAX_LAT
], 0);
2564 // pci_conf[0x50] = 0x01; // power management caps
2566 pci_set_byte(&pci_conf
[USB_SBRN
], USB_RELEASE_2
); // release number (2.1.4)
2567 pci_set_byte(&pci_conf
[0x61], 0x20); // frame length adjustment (2.1.5)
2568 pci_set_word(&pci_conf
[0x62], 0x00); // port wake up capability (2.1.6)
2570 pci_conf
[0x64] = 0x00;
2571 pci_conf
[0x65] = 0x00;
2572 pci_conf
[0x66] = 0x00;
2573 pci_conf
[0x67] = 0x00;
2574 pci_conf
[0x68] = 0x01;
2575 pci_conf
[0x69] = 0x00;
2576 pci_conf
[0x6a] = 0x00;
2577 pci_conf
[0x6b] = 0x00; // USBLEGSUP
2578 pci_conf
[0x6c] = 0x00;
2579 pci_conf
[0x6d] = 0x00;
2580 pci_conf
[0x6e] = 0x00;
2581 pci_conf
[0x6f] = 0xc0; // USBLEFCTLSTS
2583 // 2.2 host controller interface version
2584 s
->mmio
[0x00] = (uint8_t) OPREGBASE
;
2585 s
->mmio
[0x01] = 0x00;
2586 s
->mmio
[0x02] = 0x00;
2587 s
->mmio
[0x03] = 0x01; // HC version
2588 s
->mmio
[0x04] = NB_PORTS
; // Number of downstream ports
2589 s
->mmio
[0x05] = 0x00; // No companion ports at present
2590 s
->mmio
[0x06] = 0x00;
2591 s
->mmio
[0x07] = 0x00;
2592 s
->mmio
[0x08] = 0x80; // We can cache whole frame, not 64-bit capable
2593 s
->mmio
[0x09] = 0x68; // EECP
2594 s
->mmio
[0x0a] = 0x00;
2595 s
->mmio
[0x0b] = 0x00;
2597 s
->irq
= s
->dev
.irq
[3];
2599 usb_bus_new(&s
->bus
, &ehci_bus_ops
, &s
->dev
.qdev
);
2600 for(i
= 0; i
< NB_PORTS
; i
++) {
2601 usb_register_port(&s
->bus
, &s
->ports
[i
], s
, i
, &ehci_port_ops
,
2602 USB_SPEED_MASK_HIGH
);
2603 s
->ports
[i
].dev
= 0;
2606 s
->frame_timer
= qemu_new_timer_ns(vm_clock
, ehci_frame_timer
, s
);
2607 s
->async_bh
= qemu_bh_new(ehci_async_bh
, s
);
2608 QTAILQ_INIT(&s
->aqueues
);
2609 QTAILQ_INIT(&s
->pqueues
);
2610 usb_packet_init(&s
->ipacket
);
2612 qemu_register_reset(ehci_reset
, s
);
2614 memory_region_init_io(&s
->mem
, &ehci_mem_ops
, s
, "ehci", MMIO_SIZE
);
2615 pci_register_bar(&s
->dev
, 0, PCI_BASE_ADDRESS_SPACE_MEMORY
, &s
->mem
);
2620 static void ehci_register_types(void)
2622 type_register_static(&ehci_info
);
2623 type_register_static(&ich9_ehci_info
);
2626 type_init(ehci_register_types
)
2629 * vim: expandtab ts=4