Merge remote-tracking branch 'bonzini/scsi-next' into staging
[qemu-kvm.git] / hw / pl031.c
blob9602664da6ad8fd177a34d0126dc532ad3d0adc9
1 /*
2 * ARM AMBA PrimeCell PL031 RTC
4 * Copyright (c) 2007 CodeSourcery
6 * This file is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * Contributions after 2012-01-13 are licensed under the terms of the
11 * GNU GPL, version 2 or (at your option) any later version.
14 #include "sysbus.h"
15 #include "qemu-timer.h"
16 #include "sysemu.h"
18 //#define DEBUG_PL031
20 #ifdef DEBUG_PL031
21 #define DPRINTF(fmt, ...) \
22 do { printf("pl031: " fmt , ## __VA_ARGS__); } while (0)
23 #else
24 #define DPRINTF(fmt, ...) do {} while(0)
25 #endif
27 #define RTC_DR 0x00 /* Data read register */
28 #define RTC_MR 0x04 /* Match register */
29 #define RTC_LR 0x08 /* Data load register */
30 #define RTC_CR 0x0c /* Control register */
31 #define RTC_IMSC 0x10 /* Interrupt mask and set register */
32 #define RTC_RIS 0x14 /* Raw interrupt status register */
33 #define RTC_MIS 0x18 /* Masked interrupt status register */
34 #define RTC_ICR 0x1c /* Interrupt clear register */
36 typedef struct {
37 SysBusDevice busdev;
38 MemoryRegion iomem;
39 QEMUTimer *timer;
40 qemu_irq irq;
42 /* Needed to preserve the tick_count across migration, even if the
43 * absolute value of the rtc_clock is different on the source and
44 * destination.
46 uint32_t tick_offset_vmstate;
47 uint32_t tick_offset;
49 uint32_t mr;
50 uint32_t lr;
51 uint32_t cr;
52 uint32_t im;
53 uint32_t is;
54 } pl031_state;
56 static const unsigned char pl031_id[] = {
57 0x31, 0x10, 0x14, 0x00, /* Device ID */
58 0x0d, 0xf0, 0x05, 0xb1 /* Cell ID */
61 static void pl031_update(pl031_state *s)
63 qemu_set_irq(s->irq, s->is & s->im);
66 static void pl031_interrupt(void * opaque)
68 pl031_state *s = (pl031_state *)opaque;
70 s->is = 1;
71 DPRINTF("Alarm raised\n");
72 pl031_update(s);
75 static uint32_t pl031_get_count(pl031_state *s)
77 int64_t now = qemu_get_clock_ns(rtc_clock);
78 return s->tick_offset + now / get_ticks_per_sec();
81 static void pl031_set_alarm(pl031_state *s)
83 uint32_t ticks;
85 /* The timer wraps around. This subtraction also wraps in the same way,
86 and gives correct results when alarm < now_ticks. */
87 ticks = s->mr - pl031_get_count(s);
88 DPRINTF("Alarm set in %ud ticks\n", ticks);
89 if (ticks == 0) {
90 qemu_del_timer(s->timer);
91 pl031_interrupt(s);
92 } else {
93 int64_t now = qemu_get_clock_ns(rtc_clock);
94 qemu_mod_timer(s->timer, now + (int64_t)ticks * get_ticks_per_sec());
98 static uint64_t pl031_read(void *opaque, target_phys_addr_t offset,
99 unsigned size)
101 pl031_state *s = (pl031_state *)opaque;
103 if (offset >= 0xfe0 && offset < 0x1000)
104 return pl031_id[(offset - 0xfe0) >> 2];
106 switch (offset) {
107 case RTC_DR:
108 return pl031_get_count(s);
109 case RTC_MR:
110 return s->mr;
111 case RTC_IMSC:
112 return s->im;
113 case RTC_RIS:
114 return s->is;
115 case RTC_LR:
116 return s->lr;
117 case RTC_CR:
118 /* RTC is permanently enabled. */
119 return 1;
120 case RTC_MIS:
121 return s->is & s->im;
122 case RTC_ICR:
123 fprintf(stderr, "qemu: pl031_read: Unexpected offset 0x%x\n",
124 (int)offset);
125 break;
126 default:
127 hw_error("pl031_read: Bad offset 0x%x\n", (int)offset);
128 break;
131 return 0;
134 static void pl031_write(void * opaque, target_phys_addr_t offset,
135 uint64_t value, unsigned size)
137 pl031_state *s = (pl031_state *)opaque;
140 switch (offset) {
141 case RTC_LR:
142 s->tick_offset += value - pl031_get_count(s);
143 pl031_set_alarm(s);
144 break;
145 case RTC_MR:
146 s->mr = value;
147 pl031_set_alarm(s);
148 break;
149 case RTC_IMSC:
150 s->im = value & 1;
151 DPRINTF("Interrupt mask %d\n", s->im);
152 pl031_update(s);
153 break;
154 case RTC_ICR:
155 /* The PL031 documentation (DDI0224B) states that the interrupt is
156 cleared when bit 0 of the written value is set. However the
157 arm926e documentation (DDI0287B) states that the interrupt is
158 cleared when any value is written. */
159 DPRINTF("Interrupt cleared");
160 s->is = 0;
161 pl031_update(s);
162 break;
163 case RTC_CR:
164 /* Written value is ignored. */
165 break;
167 case RTC_DR:
168 case RTC_MIS:
169 case RTC_RIS:
170 fprintf(stderr, "qemu: pl031_write: Unexpected offset 0x%x\n",
171 (int)offset);
172 break;
174 default:
175 hw_error("pl031_write: Bad offset 0x%x\n", (int)offset);
176 break;
180 static const MemoryRegionOps pl031_ops = {
181 .read = pl031_read,
182 .write = pl031_write,
183 .endianness = DEVICE_NATIVE_ENDIAN,
186 static int pl031_init(SysBusDevice *dev)
188 pl031_state *s = FROM_SYSBUS(pl031_state, dev);
189 struct tm tm;
191 memory_region_init_io(&s->iomem, &pl031_ops, s, "pl031", 0x1000);
192 sysbus_init_mmio(dev, &s->iomem);
194 sysbus_init_irq(dev, &s->irq);
195 qemu_get_timedate(&tm, 0);
196 s->tick_offset = mktimegm(&tm) - qemu_get_clock_ns(rtc_clock) / get_ticks_per_sec();
198 s->timer = qemu_new_timer_ns(rtc_clock, pl031_interrupt, s);
199 return 0;
202 static void pl031_pre_save(void *opaque)
204 pl031_state *s = opaque;
206 /* tick_offset is base_time - rtc_clock base time. Instead, we want to
207 * store the base time relative to the vm_clock for backwards-compatibility. */
208 int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock);
209 s->tick_offset_vmstate = s->tick_offset + delta / get_ticks_per_sec();
212 static int pl031_post_load(void *opaque, int version_id)
214 pl031_state *s = opaque;
216 int64_t delta = qemu_get_clock_ns(rtc_clock) - qemu_get_clock_ns(vm_clock);
217 s->tick_offset = s->tick_offset_vmstate - delta / get_ticks_per_sec();
218 pl031_set_alarm(s);
219 return 0;
222 static const VMStateDescription vmstate_pl031 = {
223 .name = "pl031",
224 .version_id = 1,
225 .minimum_version_id = 1,
226 .pre_save = pl031_pre_save,
227 .post_load = pl031_post_load,
228 .fields = (VMStateField[]) {
229 VMSTATE_UINT32(tick_offset_vmstate, pl031_state),
230 VMSTATE_UINT32(mr, pl031_state),
231 VMSTATE_UINT32(lr, pl031_state),
232 VMSTATE_UINT32(cr, pl031_state),
233 VMSTATE_UINT32(im, pl031_state),
234 VMSTATE_UINT32(is, pl031_state),
235 VMSTATE_END_OF_LIST()
239 static void pl031_class_init(ObjectClass *klass, void *data)
241 DeviceClass *dc = DEVICE_CLASS(klass);
242 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
244 k->init = pl031_init;
245 dc->no_user = 1;
246 dc->vmsd = &vmstate_pl031;
249 static TypeInfo pl031_info = {
250 .name = "pl031",
251 .parent = TYPE_SYS_BUS_DEVICE,
252 .instance_size = sizeof(pl031_state),
253 .class_init = pl031_class_init,
256 static void pl031_register_types(void)
258 type_register_static(&pl031_info);
261 type_init(pl031_register_types)