2 * QEMU TCX Frame buffer
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
27 #include "pixel_ops.h"
29 #include "qdev-addr.h"
33 #define TCX_DAC_NREGS 16
34 #define TCX_THC_NREGS_8 0x081c
35 #define TCX_THC_NREGS_24 0x1000
36 #define TCX_TEC_NREGS 0x1000
38 typedef struct TCXState
{
40 target_phys_addr_t addr
;
43 uint32_t *vram24
, *cplane
;
44 ram_addr_t vram_offset
, vram24_offset
, cplane_offset
;
46 uint16_t width
, height
, depth
;
47 uint8_t r
[256], g
[256], b
[256];
48 uint32_t palette
[256];
49 uint8_t dac_index
, dac_state
;
52 static void tcx_screen_dump(void *opaque
, const char *filename
);
53 static void tcx24_screen_dump(void *opaque
, const char *filename
);
55 static void tcx_set_dirty(TCXState
*s
)
59 for (i
= 0; i
< MAXX
* MAXY
; i
+= TARGET_PAGE_SIZE
) {
60 cpu_physical_memory_set_dirty(s
->vram_offset
+ i
);
64 static void tcx24_set_dirty(TCXState
*s
)
68 for (i
= 0; i
< MAXX
* MAXY
* 4; i
+= TARGET_PAGE_SIZE
) {
69 cpu_physical_memory_set_dirty(s
->vram24_offset
+ i
);
70 cpu_physical_memory_set_dirty(s
->cplane_offset
+ i
);
74 static void update_palette_entries(TCXState
*s
, int start
, int end
)
77 for(i
= start
; i
< end
; i
++) {
78 switch(ds_get_bits_per_pixel(s
->ds
)) {
81 s
->palette
[i
] = rgb_to_pixel8(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
84 s
->palette
[i
] = rgb_to_pixel15(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
87 s
->palette
[i
] = rgb_to_pixel16(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
90 if (is_surface_bgr(s
->ds
->surface
))
91 s
->palette
[i
] = rgb_to_pixel32bgr(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
93 s
->palette
[i
] = rgb_to_pixel32(s
->r
[i
], s
->g
[i
], s
->b
[i
]);
104 static void tcx_draw_line32(TCXState
*s1
, uint8_t *d
,
105 const uint8_t *s
, int width
)
109 uint32_t *p
= (uint32_t *)d
;
111 for(x
= 0; x
< width
; x
++) {
113 *p
++ = s1
->palette
[val
];
117 static void tcx_draw_line16(TCXState
*s1
, uint8_t *d
,
118 const uint8_t *s
, int width
)
122 uint16_t *p
= (uint16_t *)d
;
124 for(x
= 0; x
< width
; x
++) {
126 *p
++ = s1
->palette
[val
];
130 static void tcx_draw_line8(TCXState
*s1
, uint8_t *d
,
131 const uint8_t *s
, int width
)
136 for(x
= 0; x
< width
; x
++) {
138 *d
++ = s1
->palette
[val
];
143 XXX Could be much more optimal:
144 * detect if line/page/whole screen is in 24 bit mode
145 * if destination is also BGR, use memcpy
147 static inline void tcx24_draw_line32(TCXState
*s1
, uint8_t *d
,
148 const uint8_t *s
, int width
,
149 const uint32_t *cplane
,
154 uint32_t *p
= (uint32_t *)d
;
157 bgr
= is_surface_bgr(s1
->ds
->surface
);
158 for(x
= 0; x
< width
; x
++, s
++, s24
++) {
159 if ((be32_to_cpu(*cplane
++) & 0xff000000) == 0x03000000) {
160 // 24-bit direct, BGR order
167 dval
= rgb_to_pixel32bgr(r
, g
, b
);
169 dval
= rgb_to_pixel32(r
, g
, b
);
172 dval
= s1
->palette
[val
];
178 static inline int check_dirty(ram_addr_t page
, ram_addr_t page24
,
184 ret
= cpu_physical_memory_get_dirty(page
, VGA_DIRTY_FLAG
);
185 for (off
= 0; off
< TARGET_PAGE_SIZE
* 4; off
+= TARGET_PAGE_SIZE
) {
186 ret
|= cpu_physical_memory_get_dirty(page24
+ off
, VGA_DIRTY_FLAG
);
187 ret
|= cpu_physical_memory_get_dirty(cpage
+ off
, VGA_DIRTY_FLAG
);
192 static inline void reset_dirty(TCXState
*ts
, ram_addr_t page_min
,
193 ram_addr_t page_max
, ram_addr_t page24
,
196 cpu_physical_memory_reset_dirty(page_min
, page_max
+ TARGET_PAGE_SIZE
,
198 page_min
-= ts
->vram_offset
;
199 page_max
-= ts
->vram_offset
;
200 cpu_physical_memory_reset_dirty(page24
+ page_min
* 4,
201 page24
+ page_max
* 4 + TARGET_PAGE_SIZE
,
203 cpu_physical_memory_reset_dirty(cpage
+ page_min
* 4,
204 cpage
+ page_max
* 4 + TARGET_PAGE_SIZE
,
208 /* Fixed line length 1024 allows us to do nice tricks not possible on
210 static void tcx_update_display(void *opaque
)
212 TCXState
*ts
= opaque
;
213 ram_addr_t page
, page_min
, page_max
;
214 int y
, y_start
, dd
, ds
;
216 void (*f
)(TCXState
*s1
, uint8_t *dst
, const uint8_t *src
, int width
);
218 if (ds_get_bits_per_pixel(ts
->ds
) == 0)
220 page
= ts
->vram_offset
;
224 d
= ds_get_data(ts
->ds
);
226 dd
= ds_get_linesize(ts
->ds
);
229 switch (ds_get_bits_per_pixel(ts
->ds
)) {
245 for(y
= 0; y
< ts
->height
; y
+= 4, page
+= TARGET_PAGE_SIZE
) {
246 if (cpu_physical_memory_get_dirty(page
, VGA_DIRTY_FLAG
)) {
253 f(ts
, d
, s
, ts
->width
);
256 f(ts
, d
, s
, ts
->width
);
259 f(ts
, d
, s
, ts
->width
);
262 f(ts
, d
, s
, ts
->width
);
267 /* flush to display */
268 dpy_update(ts
->ds
, 0, y_start
,
269 ts
->width
, y
- y_start
);
277 /* flush to display */
278 dpy_update(ts
->ds
, 0, y_start
,
279 ts
->width
, y
- y_start
);
281 /* reset modified pages */
282 if (page_max
>= page_min
) {
283 cpu_physical_memory_reset_dirty(page_min
, page_max
+ TARGET_PAGE_SIZE
,
288 static void tcx24_update_display(void *opaque
)
290 TCXState
*ts
= opaque
;
291 ram_addr_t page
, page_min
, page_max
, cpage
, page24
;
292 int y
, y_start
, dd
, ds
;
294 uint32_t *cptr
, *s24
;
296 if (ds_get_bits_per_pixel(ts
->ds
) != 32)
298 page
= ts
->vram_offset
;
299 page24
= ts
->vram24_offset
;
300 cpage
= ts
->cplane_offset
;
304 d
= ds_get_data(ts
->ds
);
308 dd
= ds_get_linesize(ts
->ds
);
311 for(y
= 0; y
< ts
->height
; y
+= 4, page
+= TARGET_PAGE_SIZE
,
312 page24
+= TARGET_PAGE_SIZE
, cpage
+= TARGET_PAGE_SIZE
) {
313 if (check_dirty(page
, page24
, cpage
)) {
320 tcx24_draw_line32(ts
, d
, s
, ts
->width
, cptr
, s24
);
325 tcx24_draw_line32(ts
, d
, s
, ts
->width
, cptr
, s24
);
330 tcx24_draw_line32(ts
, d
, s
, ts
->width
, cptr
, s24
);
335 tcx24_draw_line32(ts
, d
, s
, ts
->width
, cptr
, s24
);
342 /* flush to display */
343 dpy_update(ts
->ds
, 0, y_start
,
344 ts
->width
, y
- y_start
);
354 /* flush to display */
355 dpy_update(ts
->ds
, 0, y_start
,
356 ts
->width
, y
- y_start
);
358 /* reset modified pages */
359 if (page_max
>= page_min
) {
360 reset_dirty(ts
, page_min
, page_max
, page24
, cpage
);
364 static void tcx_invalidate_display(void *opaque
)
366 TCXState
*s
= opaque
;
369 qemu_console_resize(s
->ds
, s
->width
, s
->height
);
372 static void tcx24_invalidate_display(void *opaque
)
374 TCXState
*s
= opaque
;
378 qemu_console_resize(s
->ds
, s
->width
, s
->height
);
381 static void tcx_save(QEMUFile
*f
, void *opaque
)
383 TCXState
*s
= opaque
;
385 qemu_put_be16s(f
, &s
->height
);
386 qemu_put_be16s(f
, &s
->width
);
387 qemu_put_be16s(f
, &s
->depth
);
388 qemu_put_buffer(f
, s
->r
, 256);
389 qemu_put_buffer(f
, s
->g
, 256);
390 qemu_put_buffer(f
, s
->b
, 256);
391 qemu_put_8s(f
, &s
->dac_index
);
392 qemu_put_8s(f
, &s
->dac_state
);
395 static int tcx_load(QEMUFile
*f
, void *opaque
, int version_id
)
397 TCXState
*s
= opaque
;
400 if (version_id
!= 3 && version_id
!= 4)
403 if (version_id
== 3) {
404 qemu_get_be32s(f
, &dummy
);
405 qemu_get_be32s(f
, &dummy
);
406 qemu_get_be32s(f
, &dummy
);
408 qemu_get_be16s(f
, &s
->height
);
409 qemu_get_be16s(f
, &s
->width
);
410 qemu_get_be16s(f
, &s
->depth
);
411 qemu_get_buffer(f
, s
->r
, 256);
412 qemu_get_buffer(f
, s
->g
, 256);
413 qemu_get_buffer(f
, s
->b
, 256);
414 qemu_get_8s(f
, &s
->dac_index
);
415 qemu_get_8s(f
, &s
->dac_state
);
416 update_palette_entries(s
, 0, 256);
417 if (s
->depth
== 24) {
426 static void tcx_reset(void *opaque
)
428 TCXState
*s
= opaque
;
430 /* Initialize palette */
431 memset(s
->r
, 0, 256);
432 memset(s
->g
, 0, 256);
433 memset(s
->b
, 0, 256);
434 s
->r
[255] = s
->g
[255] = s
->b
[255] = 255;
435 update_palette_entries(s
, 0, 256);
436 memset(s
->vram
, 0, MAXX
*MAXY
);
437 cpu_physical_memory_reset_dirty(s
->vram_offset
, s
->vram_offset
+
438 MAXX
* MAXY
* (1 + 4 + 4), VGA_DIRTY_FLAG
);
443 static uint32_t tcx_dac_readl(void *opaque
, target_phys_addr_t addr
)
448 static void tcx_dac_writel(void *opaque
, target_phys_addr_t addr
, uint32_t val
)
450 TCXState
*s
= opaque
;
454 s
->dac_index
= val
>> 24;
458 switch (s
->dac_state
) {
460 s
->r
[s
->dac_index
] = val
>> 24;
461 update_palette_entries(s
, s
->dac_index
, s
->dac_index
+ 1);
465 s
->g
[s
->dac_index
] = val
>> 24;
466 update_palette_entries(s
, s
->dac_index
, s
->dac_index
+ 1);
470 s
->b
[s
->dac_index
] = val
>> 24;
471 update_palette_entries(s
, s
->dac_index
, s
->dac_index
+ 1);
472 s
->dac_index
= (s
->dac_index
+ 1) & 255; // Index autoincrement
484 static CPUReadMemoryFunc
*tcx_dac_read
[3] = {
490 static CPUWriteMemoryFunc
*tcx_dac_write
[3] = {
496 static uint32_t tcx_dummy_readl(void *opaque
, target_phys_addr_t addr
)
501 static void tcx_dummy_writel(void *opaque
, target_phys_addr_t addr
,
506 static CPUReadMemoryFunc
*tcx_dummy_read
[3] = {
512 static CPUWriteMemoryFunc
*tcx_dummy_write
[3] = {
518 static void tcx_init1(SysBusDevice
*dev
)
520 TCXState
*s
= FROM_SYSBUS(TCXState
, dev
);
521 int io_memory
, dummy_memory
;
522 ram_addr_t vram_offset
;
526 vram_offset
= qemu_ram_alloc(s
->vram_size
* (1 + 4 + 4));
527 vram_base
= qemu_get_ram_ptr(vram_offset
);
528 s
->vram_offset
= vram_offset
;
533 sysbus_init_mmio(dev
, size
, s
->vram_offset
);
538 io_memory
= cpu_register_io_memory(tcx_dac_read
, tcx_dac_write
, s
);
539 sysbus_init_mmio(dev
, TCX_DAC_NREGS
, io_memory
);
542 dummy_memory
= cpu_register_io_memory(tcx_dummy_read
, tcx_dummy_write
,
544 sysbus_init_mmio(dev
, TCX_TEC_NREGS
, dummy_memory
);
545 /* THC: NetBSD writes here even with 8-bit display: dummy */
546 sysbus_init_mmio(dev
, TCX_THC_NREGS_24
, dummy_memory
);
548 if (s
->depth
== 24) {
550 size
= s
->vram_size
* 4;
551 s
->vram24
= (uint32_t *)vram_base
;
552 s
->vram24_offset
= vram_offset
;
553 sysbus_init_mmio(dev
, size
, vram_offset
);
558 size
= s
->vram_size
* 4;
559 s
->cplane
= (uint32_t *)vram_base
;
560 s
->cplane_offset
= vram_offset
;
561 sysbus_init_mmio(dev
, size
, vram_offset
);
563 s
->ds
= graphic_console_init(tcx24_update_display
,
564 tcx24_invalidate_display
,
565 tcx24_screen_dump
, NULL
, s
);
567 /* THC 8 bit (dummy) */
568 sysbus_init_mmio(dev
, TCX_THC_NREGS_8
, dummy_memory
);
570 s
->ds
= graphic_console_init(tcx_update_display
,
571 tcx_invalidate_display
,
572 tcx_screen_dump
, NULL
, s
);
575 register_savevm("tcx", -1, 4, tcx_save
, tcx_load
, s
);
576 qemu_register_reset(tcx_reset
, s
);
578 qemu_console_resize(s
->ds
, s
->width
, s
->height
);
581 static void tcx_screen_dump(void *opaque
, const char *filename
)
583 TCXState
*s
= opaque
;
588 f
= fopen(filename
, "wb");
591 fprintf(f
, "P6\n%d %d\n%d\n", s
->width
, s
->height
, 255);
593 for(y
= 0; y
< s
->height
; y
++) {
595 for(x
= 0; x
< s
->width
; x
++) {
608 static void tcx24_screen_dump(void *opaque
, const char *filename
)
610 TCXState
*s
= opaque
;
613 uint32_t *s24
, *cptr
, dval
;
616 f
= fopen(filename
, "wb");
619 fprintf(f
, "P6\n%d %d\n%d\n", s
->width
, s
->height
, 255);
623 for(y
= 0; y
< s
->height
; y
++) {
625 for(x
= 0; x
< s
->width
; x
++, d
++, s24
++) {
626 if ((*cptr
++ & 0xff000000) == 0x03000000) { // 24-bit direct
627 dval
= *s24
& 0x00ffffff;
628 fputc((dval
>> 16) & 0xff, f
);
629 fputc((dval
>> 8) & 0xff, f
);
630 fputc(dval
& 0xff, f
);
644 static SysBusDeviceInfo tcx_info
= {
646 .qdev
.name
= "SUNW,tcx",
647 .qdev
.size
= sizeof(TCXState
),
648 .qdev
.props
= (Property
[]) {
651 .info
= &qdev_prop_taddr
,
652 .offset
= offsetof(TCXState
, addr
),
653 .defval
= (target_phys_addr_t
[]) { -1 },
656 .info
= &qdev_prop_hex32
,
657 .offset
= offsetof(TCXState
, vram_size
),
658 .defval
= (uint32_t[]) { -1 },
661 .info
= &qdev_prop_uint16
,
662 .offset
= offsetof(TCXState
, width
),
663 .defval
= (uint16_t[]) { -1 },
666 .info
= &qdev_prop_uint16
,
667 .offset
= offsetof(TCXState
, height
),
668 .defval
= (uint16_t[]) { -1 },
671 .info
= &qdev_prop_uint16
,
672 .offset
= offsetof(TCXState
, depth
),
673 .defval
= (uint16_t[]) { -1 },
679 static void tcx_register_devices(void)
681 sysbus_register_withprop(&tcx_info
);
684 device_init(tcx_register_devices
)