4 * Copyright (c) 2006 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License version 2 as published by the Free Software Foundation.
10 * This library is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
13 * Lesser General Public License for more details.
15 * You should have received a copy of the GNU Lesser General Public
16 * License along with this library; if not, see <http://www.gnu.org/licenses/>
21 #include "qemu-timer.h"
29 /* i82731AB (PIIX4) compatible power management function */
30 #define PM_FREQ 3579545
32 #define ACPI_DBG_IO_ADDR 0xb044
34 typedef struct PIIX4PMState
{
42 int64_t tmr_overflow_time
;
55 #define RSM_STS (1 << 15)
56 #define PWRBTN_STS (1 << 8)
57 #define RTC_EN (1 << 10)
58 #define PWRBTN_EN (1 << 8)
59 #define GBL_EN (1 << 5)
60 #define TMROF_EN (1 << 0)
62 #define SCI_EN (1 << 0)
64 #define SUS_EN (1 << 13)
66 #define ACPI_ENABLE 0xf1
67 #define ACPI_DISABLE 0xf0
69 #define SMBHSTSTS 0x00
70 #define SMBHSTCNT 0x02
71 #define SMBHSTCMD 0x03
72 #define SMBHSTADD 0x04
73 #define SMBHSTDAT0 0x05
74 #define SMBHSTDAT1 0x06
75 #define SMBBLKDAT 0x07
77 static PIIX4PMState
*pm_state
;
79 static uint32_t get_pmtmr(PIIX4PMState
*s
)
82 d
= muldiv64(qemu_get_clock(vm_clock
), PM_FREQ
, ticks_per_sec
);
86 static int get_pmsts(PIIX4PMState
*s
)
91 d
= muldiv64(qemu_get_clock(vm_clock
), PM_FREQ
, ticks_per_sec
);
92 if (d
>= s
->tmr_overflow_time
)
97 static void pm_update_sci(PIIX4PMState
*s
)
102 pmsts
= get_pmsts(s
);
103 sci_level
= (((pmsts
& s
->pmen
) &
104 (RTC_EN
| PWRBTN_EN
| GBL_EN
| TMROF_EN
)) != 0);
105 qemu_set_irq(s
->irq
, sci_level
);
106 /* schedule a timer interruption if needed */
107 if ((s
->pmen
& TMROF_EN
) && !(pmsts
& TMROF_EN
)) {
108 expire_time
= muldiv64(s
->tmr_overflow_time
, ticks_per_sec
, PM_FREQ
);
109 qemu_mod_timer(s
->tmr_timer
, expire_time
);
111 qemu_del_timer(s
->tmr_timer
);
115 static void pm_tmr_timer(void *opaque
)
117 PIIX4PMState
*s
= opaque
;
121 static void pm_ioport_writew(void *opaque
, uint32_t addr
, uint32_t val
)
123 PIIX4PMState
*s
= opaque
;
130 pmsts
= get_pmsts(s
);
131 if (pmsts
& val
& TMROF_EN
) {
132 /* if TMRSTS is reset, then compute the new overflow time */
133 d
= muldiv64(qemu_get_clock(vm_clock
), PM_FREQ
, ticks_per_sec
);
134 s
->tmr_overflow_time
= (d
+ 0x800000LL
) & ~0x7fffffLL
;
147 s
->pmcntrl
= val
& ~(SUS_EN
);
149 /* change suspend type */
150 sus_typ
= (val
>> 10) & 7;
152 case 0: /* soft power off */
153 qemu_system_shutdown_request();
156 /* RSM_STS should be set on resume. Pretend that resume
157 was caused by power button */
158 s
->pmsts
|= (RSM_STS
| PWRBTN_STS
);
159 qemu_system_reset_request();
160 #if defined(TARGET_I386)
161 cmos_set_s3_resume();
173 printf("PM writew port=0x%04x val=0x%04x\n", addr
, val
);
177 static uint32_t pm_ioport_readw(void *opaque
, uint32_t addr
)
179 PIIX4PMState
*s
= opaque
;
198 printf("PM readw port=0x%04x val=0x%04x\n", addr
, val
);
203 static void pm_ioport_writel(void *opaque
, uint32_t addr
, uint32_t val
)
205 // PIIX4PMState *s = opaque;
208 printf("PM writel port=0x%04x val=0x%08x\n", addr
, val
);
212 static uint32_t pm_ioport_readl(void *opaque
, uint32_t addr
)
214 PIIX4PMState
*s
= opaque
;
227 printf("PM readl port=0x%04x val=0x%08x\n", addr
, val
);
232 static void pm_smi_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
234 PIIX4PMState
*s
= opaque
;
237 printf("pm_smi_writeb addr=0x%x val=0x%02x\n", addr
, val
);
242 /* ACPI specs 3.0, 4.7.2.5 */
243 if (val
== ACPI_ENABLE
) {
244 s
->pmcntrl
|= SCI_EN
;
245 } else if (val
== ACPI_DISABLE
) {
246 s
->pmcntrl
&= ~SCI_EN
;
249 if (s
->dev
.config
[0x5b] & (1 << 1)) {
250 cpu_interrupt(first_cpu
, CPU_INTERRUPT_SMI
);
257 static uint32_t pm_smi_readb(void *opaque
, uint32_t addr
)
259 PIIX4PMState
*s
= opaque
;
269 printf("pm_smi_readb addr=0x%x val=0x%02x\n", addr
, val
);
274 static void acpi_dbg_writel(void *opaque
, uint32_t addr
, uint32_t val
)
277 printf("ACPI: DBG: 0x%08x\n", val
);
281 static void smb_transaction(PIIX4PMState
*s
)
283 uint8_t prot
= (s
->smb_ctl
>> 2) & 0x07;
284 uint8_t read
= s
->smb_addr
& 0x01;
285 uint8_t cmd
= s
->smb_cmd
;
286 uint8_t addr
= s
->smb_addr
>> 1;
287 i2c_bus
*bus
= s
->smbus
;
290 printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr
, prot
);
294 smbus_quick_command(bus
, addr
, read
);
298 s
->smb_data0
= smbus_receive_byte(bus
, addr
);
300 smbus_send_byte(bus
, addr
, cmd
);
305 s
->smb_data0
= smbus_read_byte(bus
, addr
, cmd
);
307 smbus_write_byte(bus
, addr
, cmd
, s
->smb_data0
);
313 val
= smbus_read_word(bus
, addr
, cmd
);
315 s
->smb_data1
= val
>> 8;
317 smbus_write_word(bus
, addr
, cmd
, (s
->smb_data1
<< 8) | s
->smb_data0
);
322 s
->smb_data0
= smbus_read_block(bus
, addr
, cmd
, s
->smb_data
);
324 smbus_write_block(bus
, addr
, cmd
, s
->smb_data
, s
->smb_data0
);
336 static void smb_ioport_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
338 PIIX4PMState
*s
= opaque
;
341 printf("SMB writeb port=0x%04x val=0x%02x\n", addr
, val
);
366 s
->smb_data
[s
->smb_index
++] = val
;
367 if (s
->smb_index
> 31)
375 static uint32_t smb_ioport_readb(void *opaque
, uint32_t addr
)
377 PIIX4PMState
*s
= opaque
;
387 val
= s
->smb_ctl
& 0x1f;
402 val
= s
->smb_data
[s
->smb_index
++];
403 if (s
->smb_index
> 31)
411 printf("SMB readb port=0x%04x val=0x%02x\n", addr
, val
);
416 static void pm_io_space_update(PIIX4PMState
*s
)
420 if (s
->dev
.config
[0x80] & 1) {
421 pm_io_base
= le32_to_cpu(*(uint32_t *)(s
->dev
.config
+ 0x40));
422 pm_io_base
&= 0xffc0;
424 /* XXX: need to improve memory and ioport allocation */
426 printf("PM: mapping to 0x%x\n", pm_io_base
);
428 register_ioport_write(pm_io_base
, 64, 2, pm_ioport_writew
, s
);
429 register_ioport_read(pm_io_base
, 64, 2, pm_ioport_readw
, s
);
430 register_ioport_write(pm_io_base
, 64, 4, pm_ioport_writel
, s
);
431 register_ioport_read(pm_io_base
, 64, 4, pm_ioport_readl
, s
);
435 static void pm_write_config(PCIDevice
*d
,
436 uint32_t address
, uint32_t val
, int len
)
438 pci_default_write_config(d
, address
, val
, len
);
440 pm_io_space_update((PIIX4PMState
*)d
);
443 static void pm_save(QEMUFile
* f
,void *opaque
)
445 PIIX4PMState
*s
= opaque
;
447 pci_device_save(&s
->dev
, f
);
449 qemu_put_be16s(f
, &s
->pmsts
);
450 qemu_put_be16s(f
, &s
->pmen
);
451 qemu_put_be16s(f
, &s
->pmcntrl
);
452 qemu_put_8s(f
, &s
->apmc
);
453 qemu_put_8s(f
, &s
->apms
);
454 qemu_put_timer(f
, s
->tmr_timer
);
455 qemu_put_be64(f
, s
->tmr_overflow_time
);
458 static int pm_load(QEMUFile
* f
,void* opaque
,int version_id
)
460 PIIX4PMState
*s
= opaque
;
466 ret
= pci_device_load(&s
->dev
, f
);
470 qemu_get_be16s(f
, &s
->pmsts
);
471 qemu_get_be16s(f
, &s
->pmen
);
472 qemu_get_be16s(f
, &s
->pmcntrl
);
473 qemu_get_8s(f
, &s
->apmc
);
474 qemu_get_8s(f
, &s
->apms
);
475 qemu_get_timer(f
, s
->tmr_timer
);
476 s
->tmr_overflow_time
=qemu_get_be64(f
);
478 pm_io_space_update(s
);
483 static void piix4_reset(void *opaque
)
485 PIIX4PMState
*s
= opaque
;
486 uint8_t *pci_conf
= s
->dev
.config
;
494 /* Mark SMM as already inited (until KVM supports SMM). */
495 pci_conf
[0x5B] = 0x02;
499 static void piix4_powerdown(void *opaque
, int irq
, int power_failing
)
501 #if defined(TARGET_I386)
502 PIIX4PMState
*s
= opaque
;
505 qemu_system_shutdown_request();
506 } else if (s
->pmen
& PWRBTN_EN
) {
507 s
->pmsts
|= PWRBTN_EN
;
513 i2c_bus
*piix4_pm_init(PCIBus
*bus
, int devfn
, uint32_t smb_io_base
,
519 s
= (PIIX4PMState
*)pci_register_device(bus
,
520 "PM", sizeof(PIIX4PMState
),
521 devfn
, NULL
, pm_write_config
);
523 pci_conf
= s
->dev
.config
;
524 pci_config_set_vendor_id(pci_conf
, PCI_VENDOR_ID_INTEL
);
525 pci_config_set_device_id(pci_conf
, PCI_DEVICE_ID_INTEL_82371AB_3
);
526 pci_conf
[0x06] = 0x80;
527 pci_conf
[0x07] = 0x02;
528 pci_conf
[0x08] = 0x03; // revision number
529 pci_conf
[0x09] = 0x00;
530 pci_config_set_class(pci_conf
, PCI_CLASS_BRIDGE_OTHER
);
531 pci_conf
[PCI_HEADER_TYPE
] = PCI_HEADER_TYPE_NORMAL
; // header_type
532 pci_conf
[0x3d] = 0x01; // interrupt pin 1
534 pci_conf
[0x40] = 0x01; /* PM io base read only bit */
536 register_ioport_write(0xb2, 2, 1, pm_smi_writeb
, s
);
537 register_ioport_read(0xb2, 2, 1, pm_smi_readb
, s
);
539 register_ioport_write(ACPI_DBG_IO_ADDR
, 4, 4, acpi_dbg_writel
, s
);
542 /* Mark SMM as already inited to prevent SMM from running. KVM does not
543 * support SMM mode. */
544 pci_conf
[0x5B] = 0x02;
547 /* XXX: which specification is used ? The i82731AB has different
549 pci_conf
[0x5f] = (parallel_hds
[0] != NULL
? 0x80 : 0) | 0x10;
550 pci_conf
[0x63] = 0x60;
551 pci_conf
[0x67] = (serial_hds
[0] != NULL
? 0x08 : 0) |
552 (serial_hds
[1] != NULL
? 0x90 : 0);
554 pci_conf
[0x90] = smb_io_base
| 1;
555 pci_conf
[0x91] = smb_io_base
>> 8;
556 pci_conf
[0xd2] = 0x09;
557 register_ioport_write(smb_io_base
, 64, 1, smb_ioport_writeb
, s
);
558 register_ioport_read(smb_io_base
, 64, 1, smb_ioport_readb
, s
);
560 s
->tmr_timer
= qemu_new_timer(vm_clock
, pm_tmr_timer
, s
);
562 qemu_system_powerdown
= *qemu_allocate_irqs(piix4_powerdown
, s
, 1);
564 register_savevm("piix4_pm", 0, 1, pm_save
, pm_load
, s
);
566 s
->smbus
= i2c_init_bus(NULL
, "i2c");
568 qemu_register_reset(piix4_reset
, s
);
573 #define GPE_BASE 0xafe0
574 #define PCI_BASE 0xae00
575 #define PCI_EJ_BASE 0xae08
578 uint16_t sts
; /* status */
579 uint16_t en
; /* enabled */
587 static struct gpe_regs gpe
;
588 static struct pci_status pci0_status
;
590 static uint32_t gpe_read_val(uint16_t val
, uint32_t addr
)
593 return (val
>> 8) & 0xff;
597 static uint32_t gpe_readb(void *opaque
, uint32_t addr
)
600 struct gpe_regs
*g
= opaque
;
604 val
= gpe_read_val(g
->sts
, addr
);
608 val
= gpe_read_val(g
->en
, addr
);
615 printf("gpe read %x == %x\n", addr
, val
);
620 static void gpe_write_val(uint16_t *cur
, int addr
, uint32_t val
)
623 *cur
= (*cur
& 0xff) | (val
<< 8);
625 *cur
= (*cur
& 0xff00) | (val
& 0xff);
628 static void gpe_reset_val(uint16_t *cur
, int addr
, uint32_t val
)
630 uint16_t x1
, x0
= val
& 0xff;
631 int shift
= (addr
& 1) ? 8 : 0;
633 x1
= (*cur
>> shift
) & 0xff;
637 *cur
= (*cur
& (0xff << (8 - shift
))) | (x1
<< shift
);
640 static void gpe_writeb(void *opaque
, uint32_t addr
, uint32_t val
)
642 struct gpe_regs
*g
= opaque
;
646 gpe_reset_val(&g
->sts
, addr
, val
);
650 gpe_write_val(&g
->en
, addr
, val
);
657 printf("gpe write %x <== %d\n", addr
, val
);
661 static uint32_t pcihotplug_read(void *opaque
, uint32_t addr
)
664 struct pci_status
*g
= opaque
;
677 printf("pcihotplug read %x == %x\n", addr
, val
);
682 static void pcihotplug_write(void *opaque
, uint32_t addr
, uint32_t val
)
684 struct pci_status
*g
= opaque
;
695 printf("pcihotplug write %x <== %d\n", addr
, val
);
699 static uint32_t pciej_read(void *opaque
, uint32_t addr
)
702 printf("pciej read %x\n", addr
);
707 static void pciej_write(void *opaque
, uint32_t addr
, uint32_t val
)
709 #if defined (TARGET_I386)
710 int slot
= ffs(val
) - 1;
712 pci_device_hot_remove_success(0, slot
);
716 printf("pciej write %x <== %d\n", addr
, val
);
720 static void piix4_device_hot_add(int bus
, int slot
, int state
);
722 void piix4_acpi_system_hot_add_init(void)
724 register_ioport_write(GPE_BASE
, 4, 1, gpe_writeb
, &gpe
);
725 register_ioport_read(GPE_BASE
, 4, 1, gpe_readb
, &gpe
);
727 register_ioport_write(PCI_BASE
, 8, 4, pcihotplug_write
, &pci0_status
);
728 register_ioport_read(PCI_BASE
, 8, 4, pcihotplug_read
, &pci0_status
);
730 register_ioport_write(PCI_EJ_BASE
, 4, 4, pciej_write
, NULL
);
731 register_ioport_read(PCI_EJ_BASE
, 4, 4, pciej_read
, NULL
);
733 qemu_system_device_hot_add_register(piix4_device_hot_add
);
736 static void enable_device(struct pci_status
*p
, struct gpe_regs
*g
, int slot
)
739 p
->up
|= (1 << slot
);
742 static void disable_device(struct pci_status
*p
, struct gpe_regs
*g
, int slot
)
745 p
->down
|= (1 << slot
);
748 static void piix4_device_hot_add(int bus
, int slot
, int state
)
751 pci0_status
.down
= 0;
753 enable_device(&pci0_status
, &gpe
, slot
);
755 disable_device(&pci0_status
, &gpe
, slot
);
757 qemu_set_irq(pm_state
->irq
, 1);
758 qemu_set_irq(pm_state
->irq
, 0);
762 static qemu_system_device_hot_add_t device_hot_add_callback
;
763 void qemu_system_device_hot_add_register(qemu_system_device_hot_add_t callback
)
765 device_hot_add_callback
= callback
;
768 void qemu_system_device_hot_add(int pcibus
, int slot
, int state
)
770 if (device_hot_add_callback
)
771 device_hot_add_callback(pcibus
, slot
, state
);
774 struct acpi_table_header
776 char signature
[4]; /* ACPI signature (4 ASCII characters) */
777 uint32_t length
; /* Length of table, in bytes, including header */
778 uint8_t revision
; /* ACPI Specification minor version # */
779 uint8_t checksum
; /* To make sum of entire table == 0 */
780 char oem_id
[6]; /* OEM identification */
781 char oem_table_id
[8]; /* OEM table identification */
782 uint32_t oem_revision
; /* OEM revision number */
783 char asl_compiler_id
[4]; /* ASL compiler vendor ID */
784 uint32_t asl_compiler_revision
; /* ASL compiler revision number */
785 } __attribute__((packed
));
788 size_t acpi_tables_len
;
790 static int acpi_checksum(const uint8_t *data
, int len
)
794 for(i
= 0; i
< len
; i
++)
796 return (-sum
) & 0xff;
799 int acpi_table_add(const char *t
)
801 static const char *dfl_id
= "QEMUQEMU";
802 char buf
[1024], *p
, *f
;
803 struct acpi_table_header acpi_hdr
;
807 memset(&acpi_hdr
, 0, sizeof(acpi_hdr
));
809 if (get_param_value(buf
, sizeof(buf
), "sig", t
)) {
810 strncpy(acpi_hdr
.signature
, buf
, 4);
812 strncpy(acpi_hdr
.signature
, dfl_id
, 4);
814 if (get_param_value(buf
, sizeof(buf
), "rev", t
)) {
815 val
= strtoul(buf
, &p
, 10);
816 if (val
> 255 || *p
!= '\0')
821 acpi_hdr
.revision
= (int8_t)val
;
823 if (get_param_value(buf
, sizeof(buf
), "oem_id", t
)) {
824 strncpy(acpi_hdr
.oem_id
, buf
, 6);
826 strncpy(acpi_hdr
.oem_id
, dfl_id
, 6);
829 if (get_param_value(buf
, sizeof(buf
), "oem_table_id", t
)) {
830 strncpy(acpi_hdr
.oem_table_id
, buf
, 8);
832 strncpy(acpi_hdr
.oem_table_id
, dfl_id
, 8);
835 if (get_param_value(buf
, sizeof(buf
), "oem_rev", t
)) {
836 val
= strtol(buf
, &p
, 10);
842 acpi_hdr
.oem_revision
= cpu_to_le32(val
);
844 if (get_param_value(buf
, sizeof(buf
), "asl_compiler_id", t
)) {
845 strncpy(acpi_hdr
.asl_compiler_id
, buf
, 4);
847 strncpy(acpi_hdr
.asl_compiler_id
, dfl_id
, 4);
850 if (get_param_value(buf
, sizeof(buf
), "asl_compiler_rev", t
)) {
851 val
= strtol(buf
, &p
, 10);
857 acpi_hdr
.asl_compiler_revision
= cpu_to_le32(val
);
859 if (!get_param_value(buf
, sizeof(buf
), "data", t
)) {
863 acpi_hdr
.length
= sizeof(acpi_hdr
);
868 char *n
= strchr(f
, ':');
871 if(stat(f
, &s
) < 0) {
872 fprintf(stderr
, "Can't stat file '%s': %s\n", f
, strerror(errno
));
875 acpi_hdr
.length
+= s
.st_size
;
883 acpi_tables_len
= sizeof(uint16_t);
884 acpi_tables
= qemu_mallocz(acpi_tables_len
);
886 p
= acpi_tables
+ acpi_tables_len
;
887 acpi_tables_len
+= sizeof(uint16_t) + acpi_hdr
.length
;
888 acpi_tables
= qemu_realloc(acpi_tables
, acpi_tables_len
);
890 acpi_hdr
.length
= cpu_to_le32(acpi_hdr
.length
);
891 *(uint16_t*)p
= acpi_hdr
.length
;
892 p
+= sizeof(uint16_t);
893 memcpy(p
, &acpi_hdr
, sizeof(acpi_hdr
));
894 off
= sizeof(acpi_hdr
);
900 char *n
= strchr(f
, ':');
903 fd
= open(f
, O_RDONLY
);
907 if(fstat(fd
, &s
) < 0) {
914 r
= read(fd
, p
+ off
, s
.st_size
);
918 } else if ((r
< 0 && errno
!= EINTR
) || r
== 0) {
930 ((struct acpi_table_header
*)p
)->checksum
= acpi_checksum((uint8_t*)p
, off
);
931 /* increase number of tables */
932 (*(uint16_t*)acpi_tables
) =
933 cpu_to_le32(le32_to_cpu(*(uint16_t*)acpi_tables
) + 1);