target-mips/op_helper.c

   1 /*
   2  *  MIPS emulation helpers for qemu.
   3  *
   4  *  Copyright (c) 2004-2005 Jocelyn Mayer
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see <http://www.gnu.org/licenses/>.
  18  */
  19 #include <stdlib.h>
  20 #include "cpu.h"
  21 #include "qemu/host-utils.h"
  22 #include "exec/helper-proto.h"
  23 #include "exec/cpu_ldst.h"
  24 #include "sysemu/kvm.h"
  25
  26 #ifndef CONFIG_USER_ONLY
  27 static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global);
  28 #endif
  29
  30 /*****************************************************************************/
  31 /* Exceptions processing helpers */
  32
  33 static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env,
  34                                                         uint32_t exception,
  35                                                         int error_code,
  36                                                         uintptr_t pc)
  37 {
  38     CPUState *cs = CPU(mips_env_get_cpu(env));
  39
  40     if (exception < EXCP_SC) {
  41         qemu_log("%s: %d %d\n", __func__, exception, error_code);
  42     }
  43     cs->exception_index = exception;
  44     env->error_code = error_code;
  45
  46     if (pc) {
  47         /* now we have a real cpu fault */
  48         cpu_restore_state(cs, pc);
  49     }
  50
  51     cpu_loop_exit(cs);
  52 }
  53
  54 static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env,
  55                                                     uint32_t exception,
  56                                                     uintptr_t pc)
  57 {
  58     do_raise_exception_err(env, exception, 0, pc);
  59 }
  60
  61 void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception,
  62                                 int error_code)
  63 {
  64     do_raise_exception_err(env, exception, error_code, 0);
  65 }
  66
  67 void helper_raise_exception(CPUMIPSState *env, uint32_t exception)
  68 {
  69     do_raise_exception(env, exception, 0);
  70 }
  71
  72 #if defined(CONFIG_USER_ONLY)
  73 #define HELPER_LD(name, insn, type)                                     \
  74 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  75                              int mem_idx)                               \
  76 {                                                                       \
  77     return (type) insn##_raw(addr);                                     \
  78 }
  79 #else
  80 #define HELPER_LD(name, insn, type)                                     \
  81 static inline type do_##name(CPUMIPSState *env, target_ulong addr,      \
  82                              int mem_idx)                               \
  83 {                                                                       \
  84     switch (mem_idx)                                                    \
  85     {                                                                   \
  86     case 0: return (type) cpu_##insn##_kernel(env, addr); break;        \
  87     case 1: return (type) cpu_##insn##_super(env, addr); break;         \
  88     default:                                                            \
  89     case 2: return (type) cpu_##insn##_user(env, addr); break;          \
  90     }                                                                   \
  91 }
  92 #endif
  93 HELPER_LD(lw, ldl, int32_t)
  94 #ifdef TARGET_MIPS64
  95 HELPER_LD(ld, ldq, int64_t)
  96 #endif
  97 #undef HELPER_LD
  98
  99 #if defined(CONFIG_USER_ONLY)
 100 #define HELPER_ST(name, insn, type)                                     \
 101 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 102                              type val, int mem_idx)                     \
 103 {                                                                       \
 104     insn##_raw(addr, val);                                              \
 105 }
 106 #else
 107 #define HELPER_ST(name, insn, type)                                     \
 108 static inline void do_##name(CPUMIPSState *env, target_ulong addr,      \
 109                              type val, int mem_idx)                     \
 110 {                                                                       \
 111     switch (mem_idx)                                                    \
 112     {                                                                   \
 113     case 0: cpu_##insn##_kernel(env, addr, val); break;                 \
 114     case 1: cpu_##insn##_super(env, addr, val); break;                  \
 115     default:                                                            \
 116     case 2: cpu_##insn##_user(env, addr, val); break;                   \
 117     }                                                                   \
 118 }
 119 #endif
 120 HELPER_ST(sb, stb, uint8_t)
 121 HELPER_ST(sw, stl, uint32_t)
 122 #ifdef TARGET_MIPS64
 123 HELPER_ST(sd, stq, uint64_t)
 124 #endif
 125 #undef HELPER_ST
 126
 127 target_ulong helper_clo (target_ulong arg1)
 128 {
 129     return clo32(arg1);
 130 }
 131
 132 target_ulong helper_clz (target_ulong arg1)
 133 {
 134     return clz32(arg1);
 135 }
 136
 137 #if defined(TARGET_MIPS64)
 138 target_ulong helper_dclo (target_ulong arg1)
 139 {
 140     return clo64(arg1);
 141 }
 142
 143 target_ulong helper_dclz (target_ulong arg1)
 144 {
 145     return clz64(arg1);
 146 }
 147 #endif /* TARGET_MIPS64 */
 148
 149 /* 64 bits arithmetic for 32 bits hosts */
 150 static inline uint64_t get_HILO(CPUMIPSState *env)
 151 {
 152     return ((uint64_t)(env->active_tc.HI[0]) << 32) | (uint32_t)env->active_tc.LO[0];
 153 }
 154
 155 static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO)
 156 {
 157     target_ulong tmp;
 158     env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 159     tmp = env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 160     return tmp;
 161 }
 162
 163 static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO)
 164 {
 165     target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF);
 166     env->active_tc.HI[0] = (int32_t)(HILO >> 32);
 167     return tmp;
 168 }
 169
 170 /* Multiplication variants of the vr54xx. */
 171 target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1,
 172                          target_ulong arg2)
 173 {
 174     return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 *
 175                                  (int64_t)(int32_t)arg2));
 176 }
 177
 178 target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1,
 179                           target_ulong arg2)
 180 {
 181     return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 *
 182                        (uint64_t)(uint32_t)arg2);
 183 }
 184
 185 target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1,
 186                          target_ulong arg2)
 187 {
 188     return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 189                        (int64_t)(int32_t)arg2);
 190 }
 191
 192 target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1,
 193                            target_ulong arg2)
 194 {
 195     return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 *
 196                        (int64_t)(int32_t)arg2);
 197 }
 198
 199 target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1,
 200                           target_ulong arg2)
 201 {
 202     return set_HI_LOT0(env, (uint64_t)get_HILO(env) +
 203                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 204 }
 205
 206 target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1,
 207                             target_ulong arg2)
 208 {
 209     return set_HIT0_LO(env, (uint64_t)get_HILO(env) +
 210                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 211 }
 212
 213 target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1,
 214                          target_ulong arg2)
 215 {
 216     return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 217                        (int64_t)(int32_t)arg2);
 218 }
 219
 220 target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1,
 221                            target_ulong arg2)
 222 {
 223     return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 *
 224                        (int64_t)(int32_t)arg2);
 225 }
 226
 227 target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1,
 228                           target_ulong arg2)
 229 {
 230     return set_HI_LOT0(env, (uint64_t)get_HILO(env) -
 231                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 232 }
 233
 234 target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1,
 235                             target_ulong arg2)
 236 {
 237     return set_HIT0_LO(env, (uint64_t)get_HILO(env) -
 238                        (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2);
 239 }
 240
 241 target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1,
 242                           target_ulong arg2)
 243 {
 244     return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2);
 245 }
 246
 247 target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1,
 248                            target_ulong arg2)
 249 {
 250     return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 *
 251                        (uint64_t)(uint32_t)arg2);
 252 }
 253
 254 target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1,
 255                            target_ulong arg2)
 256 {
 257     return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 *
 258                        (int64_t)(int32_t)arg2);
 259 }
 260
 261 target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1,
 262                             target_ulong arg2)
 263 {
 264     return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 *
 265                        (uint64_t)(uint32_t)arg2);
 266 }
 267
 268 static inline target_ulong bitswap(target_ulong v)
 269 {
 270     v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) |
 271               ((v & (target_ulong)0x5555555555555555ULL) << 1);
 272     v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) |
 273               ((v & (target_ulong)0x3333333333333333ULL) << 2);
 274     v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) |
 275               ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4);
 276     return v;
 277 }
 278
 279 #ifdef TARGET_MIPS64
 280 target_ulong helper_dbitswap(target_ulong rt)
 281 {
 282     return bitswap(rt);
 283 }
 284 #endif
 285
 286 target_ulong helper_bitswap(target_ulong rt)
 287 {
 288     return (int32_t)bitswap(rt);
 289 }
 290
 291 #ifndef CONFIG_USER_ONLY
 292
 293 static inline hwaddr do_translate_address(CPUMIPSState *env,
 294                                                       target_ulong address,
 295                                                       int rw)
 296 {
 297     hwaddr lladdr;
 298
 299     lladdr = cpu_mips_translate_address(env, address, rw);
 300
 301     if (lladdr == -1LL) {
 302         cpu_loop_exit(CPU(mips_env_get_cpu(env)));
 303     } else {
 304         return lladdr;
 305     }
 306 }
 307
 308 #define HELPER_LD_ATOMIC(name, insn)                                          \
 309 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx)  \
 310 {                                                                             \
 311     env->lladdr = do_translate_address(env, arg, 0);                          \
 312     env->llval = do_##insn(env, arg, mem_idx);                                \
 313     return env->llval;                                                        \
 314 }
 315 HELPER_LD_ATOMIC(ll, lw)
 316 #ifdef TARGET_MIPS64
 317 HELPER_LD_ATOMIC(lld, ld)
 318 #endif
 319 #undef HELPER_LD_ATOMIC
 320
 321 #define HELPER_ST_ATOMIC(name, ld_insn, st_insn, almask)                      \
 322 target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1,              \
 323                            target_ulong arg2, int mem_idx)                    \
 324 {                                                                             \
 325     target_long tmp;                                                          \
 326                                                                               \
 327     if (arg2 & almask) {                                                      \
 328         env->CP0_BadVAddr = arg2;                                             \
 329         helper_raise_exception(env, EXCP_AdES);                               \
 330     }                                                                         \
 331     if (do_translate_address(env, arg2, 1) == env->lladdr) {                  \
 332         tmp = do_##ld_insn(env, arg2, mem_idx);                               \
 333         if (tmp == env->llval) {                                              \
 334             do_##st_insn(env, arg2, arg1, mem_idx);                           \
 335             return 1;                                                         \
 336         }                                                                     \
 337     }                                                                         \
 338     return 0;                                                                 \
 339 }
 340 HELPER_ST_ATOMIC(sc, lw, sw, 0x3)
 341 #ifdef TARGET_MIPS64
 342 HELPER_ST_ATOMIC(scd, ld, sd, 0x7)
 343 #endif
 344 #undef HELPER_ST_ATOMIC
 345 #endif
 346
 347 #ifdef TARGET_WORDS_BIGENDIAN
 348 #define GET_LMASK(v) ((v) & 3)
 349 #define GET_OFFSET(addr, offset) (addr + (offset))
 350 #else
 351 #define GET_LMASK(v) (((v) & 3) ^ 3)
 352 #define GET_OFFSET(addr, offset) (addr - (offset))
 353 #endif
 354
 355 void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 356                 int mem_idx)
 357 {
 358     do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx);
 359
 360     if (GET_LMASK(arg2) <= 2)
 361         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx);
 362
 363     if (GET_LMASK(arg2) <= 1)
 364         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx);
 365
 366     if (GET_LMASK(arg2) == 0)
 367         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx);
 368 }
 369
 370 void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 371                 int mem_idx)
 372 {
 373     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 374
 375     if (GET_LMASK(arg2) >= 1)
 376         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 377
 378     if (GET_LMASK(arg2) >= 2)
 379         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 380
 381     if (GET_LMASK(arg2) == 3)
 382         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 383 }
 384
 385 #if defined(TARGET_MIPS64)
 386 /* "half" load and stores.  We must do the memory access inline,
 387    or fault handling won't work.  */
 388
 389 #ifdef TARGET_WORDS_BIGENDIAN
 390 #define GET_LMASK64(v) ((v) & 7)
 391 #else
 392 #define GET_LMASK64(v) (((v) & 7) ^ 7)
 393 #endif
 394
 395 void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 396                 int mem_idx)
 397 {
 398     do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx);
 399
 400     if (GET_LMASK64(arg2) <= 6)
 401         do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx);
 402
 403     if (GET_LMASK64(arg2) <= 5)
 404         do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx);
 405
 406     if (GET_LMASK64(arg2) <= 4)
 407         do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx);
 408
 409     if (GET_LMASK64(arg2) <= 3)
 410         do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx);
 411
 412     if (GET_LMASK64(arg2) <= 2)
 413         do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx);
 414
 415     if (GET_LMASK64(arg2) <= 1)
 416         do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx);
 417
 418     if (GET_LMASK64(arg2) <= 0)
 419         do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx);
 420 }
 421
 422 void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2,
 423                 int mem_idx)
 424 {
 425     do_sb(env, arg2, (uint8_t)arg1, mem_idx);
 426
 427     if (GET_LMASK64(arg2) >= 1)
 428         do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx);
 429
 430     if (GET_LMASK64(arg2) >= 2)
 431         do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx);
 432
 433     if (GET_LMASK64(arg2) >= 3)
 434         do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx);
 435
 436     if (GET_LMASK64(arg2) >= 4)
 437         do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx);
 438
 439     if (GET_LMASK64(arg2) >= 5)
 440         do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx);
 441
 442     if (GET_LMASK64(arg2) >= 6)
 443         do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx);
 444
 445     if (GET_LMASK64(arg2) == 7)
 446         do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx);
 447 }
 448 #endif /* TARGET_MIPS64 */
 449
 450 static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 };
 451
 452 void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 453                 uint32_t mem_idx)
 454 {
 455     target_ulong base_reglist = reglist & 0xf;
 456     target_ulong do_r31 = reglist & 0x10;
 457
 458     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 459         target_ulong i;
 460
 461         for (i = 0; i < base_reglist; i++) {
 462             env->active_tc.gpr[multiple_regs[i]] =
 463                 (target_long)do_lw(env, addr, mem_idx);
 464             addr += 4;
 465         }
 466     }
 467
 468     if (do_r31) {
 469         env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx);
 470     }
 471 }
 472
 473 void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 474                 uint32_t mem_idx)
 475 {
 476     target_ulong base_reglist = reglist & 0xf;
 477     target_ulong do_r31 = reglist & 0x10;
 478
 479     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 480         target_ulong i;
 481
 482         for (i = 0; i < base_reglist; i++) {
 483             do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 484             addr += 4;
 485         }
 486     }
 487
 488     if (do_r31) {
 489         do_sw(env, addr, env->active_tc.gpr[31], mem_idx);
 490     }
 491 }
 492
 493 #if defined(TARGET_MIPS64)
 494 void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 495                 uint32_t mem_idx)
 496 {
 497     target_ulong base_reglist = reglist & 0xf;
 498     target_ulong do_r31 = reglist & 0x10;
 499
 500     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 501         target_ulong i;
 502
 503         for (i = 0; i < base_reglist; i++) {
 504             env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx);
 505             addr += 8;
 506         }
 507     }
 508
 509     if (do_r31) {
 510         env->active_tc.gpr[31] = do_ld(env, addr, mem_idx);
 511     }
 512 }
 513
 514 void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist,
 515                 uint32_t mem_idx)
 516 {
 517     target_ulong base_reglist = reglist & 0xf;
 518     target_ulong do_r31 = reglist & 0x10;
 519
 520     if (base_reglist > 0 && base_reglist <= ARRAY_SIZE (multiple_regs)) {
 521         target_ulong i;
 522
 523         for (i = 0; i < base_reglist; i++) {
 524             do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx);
 525             addr += 8;
 526         }
 527     }
 528
 529     if (do_r31) {
 530         do_sd(env, addr, env->active_tc.gpr[31], mem_idx);
 531     }
 532 }
 533 #endif
 534
 535 #ifndef CONFIG_USER_ONLY
 536 /* SMP helpers.  */
 537 static bool mips_vpe_is_wfi(MIPSCPU *c)
 538 {
 539     CPUState *cpu = CPU(c);
 540     CPUMIPSState *env = &c->env;
 541
 542     /* If the VPE is halted but otherwise active, it means it's waiting for
 543        an interrupt.  */
 544     return cpu->halted && mips_vpe_active(env);
 545 }
 546
 547 static inline void mips_vpe_wake(MIPSCPU *c)
 548 {
 549     /* Dont set ->halted = 0 directly, let it be done via cpu_has_work
 550        because there might be other conditions that state that c should
 551        be sleeping.  */
 552     cpu_interrupt(CPU(c), CPU_INTERRUPT_WAKE);
 553 }
 554
 555 static inline void mips_vpe_sleep(MIPSCPU *cpu)
 556 {
 557     CPUState *cs = CPU(cpu);
 558
 559     /* The VPE was shut off, really go to bed.
 560        Reset any old _WAKE requests.  */
 561     cs->halted = 1;
 562     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
 563 }
 564
 565 static inline void mips_tc_wake(MIPSCPU *cpu, int tc)
 566 {
 567     CPUMIPSState *c = &cpu->env;
 568
 569     /* FIXME: TC reschedule.  */
 570     if (mips_vpe_active(c) && !mips_vpe_is_wfi(cpu)) {
 571         mips_vpe_wake(cpu);
 572     }
 573 }
 574
 575 static inline void mips_tc_sleep(MIPSCPU *cpu, int tc)
 576 {
 577     CPUMIPSState *c = &cpu->env;
 578
 579     /* FIXME: TC reschedule.  */
 580     if (!mips_vpe_active(c)) {
 581         mips_vpe_sleep(cpu);
 582     }
 583 }
 584
 585 /**
 586  * mips_cpu_map_tc:
 587  * @env: CPU from which mapping is performed.
 588  * @tc: Should point to an int with the value of the global TC index.
 589  *
 590  * This function will transform @tc into a local index within the
 591  * returned #CPUMIPSState.
 592  */
 593 /* FIXME: This code assumes that all VPEs have the same number of TCs,
 594           which depends on runtime setup. Can probably be fixed by
 595           walking the list of CPUMIPSStates.  */
 596 static CPUMIPSState *mips_cpu_map_tc(CPUMIPSState *env, int *tc)
 597 {
 598     MIPSCPU *cpu;
 599     CPUState *cs;
 600     CPUState *other_cs;
 601     int vpe_idx;
 602     int tc_idx = *tc;
 603
 604     if (!(env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))) {
 605         /* Not allowed to address other CPUs.  */
 606         *tc = env->current_tc;
 607         return env;
 608     }
 609
 610     cs = CPU(mips_env_get_cpu(env));
 611     vpe_idx = tc_idx / cs->nr_threads;
 612     *tc = tc_idx % cs->nr_threads;
 613     other_cs = qemu_get_cpu(vpe_idx);
 614     if (other_cs == NULL) {
 615         return env;
 616     }
 617     cpu = MIPS_CPU(other_cs);
 618     return &cpu->env;
 619 }
 620
 621 /* The per VPE CP0_Status register shares some fields with the per TC
 622    CP0_TCStatus registers. These fields are wired to the same registers,
 623    so changes to either of them should be reflected on both registers.
 624
 625    Also, EntryHi shares the bottom 8 bit ASID with TCStauts.
 626
 627    These helper call synchronizes the regs for a given cpu.  */
 628
 629 /* Called for updates to CP0_Status.  */
 630 static void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc)
 631 {
 632     int32_t tcstatus, *tcst;
 633     uint32_t v = cpu->CP0_Status;
 634     uint32_t cu, mx, asid, ksu;
 635     uint32_t mask = ((1 << CP0TCSt_TCU3)
 636                        | (1 << CP0TCSt_TCU2)
 637                        | (1 << CP0TCSt_TCU1)
 638                        | (1 << CP0TCSt_TCU0)
 639                        | (1 << CP0TCSt_TMX)
 640                        | (3 << CP0TCSt_TKSU)
 641                        | (0xff << CP0TCSt_TASID));
 642
 643     cu = (v >> CP0St_CU0) & 0xf;
 644     mx = (v >> CP0St_MX) & 0x1;
 645     ksu = (v >> CP0St_KSU) & 0x3;
 646     asid = env->CP0_EntryHi & 0xff;
 647
 648     tcstatus = cu << CP0TCSt_TCU0;
 649     tcstatus |= mx << CP0TCSt_TMX;
 650     tcstatus |= ksu << CP0TCSt_TKSU;
 651     tcstatus |= asid;
 652
 653     if (tc == cpu->current_tc) {
 654         tcst = &cpu->active_tc.CP0_TCStatus;
 655     } else {
 656         tcst = &cpu->tcs[tc].CP0_TCStatus;
 657     }
 658
 659     *tcst &= ~mask;
 660     *tcst |= tcstatus;
 661     compute_hflags(cpu);
 662 }
 663
 664 /* Called for updates to CP0_TCStatus.  */
 665 static void sync_c0_tcstatus(CPUMIPSState *cpu, int tc,
 666                              target_ulong v)
 667 {
 668     uint32_t status;
 669     uint32_t tcu, tmx, tasid, tksu;
 670     uint32_t mask = ((1U << CP0St_CU3)
 671                        | (1 << CP0St_CU2)
 672                        | (1 << CP0St_CU1)
 673                        | (1 << CP0St_CU0)
 674                        | (1 << CP0St_MX)
 675                        | (3 << CP0St_KSU));
 676
 677     tcu = (v >> CP0TCSt_TCU0) & 0xf;
 678     tmx = (v >> CP0TCSt_TMX) & 0x1;
 679     tasid = v & 0xff;
 680     tksu = (v >> CP0TCSt_TKSU) & 0x3;
 681
 682     status = tcu << CP0St_CU0;
 683     status |= tmx << CP0St_MX;
 684     status |= tksu << CP0St_KSU;
 685
 686     cpu->CP0_Status &= ~mask;
 687     cpu->CP0_Status |= status;
 688
 689     /* Sync the TASID with EntryHi.  */
 690     cpu->CP0_EntryHi &= ~0xff;
 691     cpu->CP0_EntryHi = tasid;
 692
 693     compute_hflags(cpu);
 694 }
 695
 696 /* Called for updates to CP0_EntryHi.  */
 697 static void sync_c0_entryhi(CPUMIPSState *cpu, int tc)
 698 {
 699     int32_t *tcst;
 700     uint32_t asid, v = cpu->CP0_EntryHi;
 701
 702     asid = v & 0xff;
 703
 704     if (tc == cpu->current_tc) {
 705         tcst = &cpu->active_tc.CP0_TCStatus;
 706     } else {
 707         tcst = &cpu->tcs[tc].CP0_TCStatus;
 708     }
 709
 710     *tcst &= ~0xff;
 711     *tcst |= asid;
 712 }
 713
 714 /* CP0 helpers */
 715 target_ulong helper_mfc0_mvpcontrol(CPUMIPSState *env)
 716 {
 717     return env->mvp->CP0_MVPControl;
 718 }
 719
 720 target_ulong helper_mfc0_mvpconf0(CPUMIPSState *env)
 721 {
 722     return env->mvp->CP0_MVPConf0;
 723 }
 724
 725 target_ulong helper_mfc0_mvpconf1(CPUMIPSState *env)
 726 {
 727     return env->mvp->CP0_MVPConf1;
 728 }
 729
 730 target_ulong helper_mfc0_random(CPUMIPSState *env)
 731 {
 732     return (int32_t)cpu_mips_get_random(env);
 733 }
 734
 735 target_ulong helper_mfc0_tcstatus(CPUMIPSState *env)
 736 {
 737     return env->active_tc.CP0_TCStatus;
 738 }
 739
 740 target_ulong helper_mftc0_tcstatus(CPUMIPSState *env)
 741 {
 742     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 743     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 744
 745     if (other_tc == other->current_tc)
 746         return other->active_tc.CP0_TCStatus;
 747     else
 748         return other->tcs[other_tc].CP0_TCStatus;
 749 }
 750
 751 target_ulong helper_mfc0_tcbind(CPUMIPSState *env)
 752 {
 753     return env->active_tc.CP0_TCBind;
 754 }
 755
 756 target_ulong helper_mftc0_tcbind(CPUMIPSState *env)
 757 {
 758     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 759     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 760
 761     if (other_tc == other->current_tc)
 762         return other->active_tc.CP0_TCBind;
 763     else
 764         return other->tcs[other_tc].CP0_TCBind;
 765 }
 766
 767 target_ulong helper_mfc0_tcrestart(CPUMIPSState *env)
 768 {
 769     return env->active_tc.PC;
 770 }
 771
 772 target_ulong helper_mftc0_tcrestart(CPUMIPSState *env)
 773 {
 774     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 775     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 776
 777     if (other_tc == other->current_tc)
 778         return other->active_tc.PC;
 779     else
 780         return other->tcs[other_tc].PC;
 781 }
 782
 783 target_ulong helper_mfc0_tchalt(CPUMIPSState *env)
 784 {
 785     return env->active_tc.CP0_TCHalt;
 786 }
 787
 788 target_ulong helper_mftc0_tchalt(CPUMIPSState *env)
 789 {
 790     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 791     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 792
 793     if (other_tc == other->current_tc)
 794         return other->active_tc.CP0_TCHalt;
 795     else
 796         return other->tcs[other_tc].CP0_TCHalt;
 797 }
 798
 799 target_ulong helper_mfc0_tccontext(CPUMIPSState *env)
 800 {
 801     return env->active_tc.CP0_TCContext;
 802 }
 803
 804 target_ulong helper_mftc0_tccontext(CPUMIPSState *env)
 805 {
 806     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 807     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 808
 809     if (other_tc == other->current_tc)
 810         return other->active_tc.CP0_TCContext;
 811     else
 812         return other->tcs[other_tc].CP0_TCContext;
 813 }
 814
 815 target_ulong helper_mfc0_tcschedule(CPUMIPSState *env)
 816 {
 817     return env->active_tc.CP0_TCSchedule;
 818 }
 819
 820 target_ulong helper_mftc0_tcschedule(CPUMIPSState *env)
 821 {
 822     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 823     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 824
 825     if (other_tc == other->current_tc)
 826         return other->active_tc.CP0_TCSchedule;
 827     else
 828         return other->tcs[other_tc].CP0_TCSchedule;
 829 }
 830
 831 target_ulong helper_mfc0_tcschefback(CPUMIPSState *env)
 832 {
 833     return env->active_tc.CP0_TCScheFBack;
 834 }
 835
 836 target_ulong helper_mftc0_tcschefback(CPUMIPSState *env)
 837 {
 838     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 839     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 840
 841     if (other_tc == other->current_tc)
 842         return other->active_tc.CP0_TCScheFBack;
 843     else
 844         return other->tcs[other_tc].CP0_TCScheFBack;
 845 }
 846
 847 target_ulong helper_mfc0_count(CPUMIPSState *env)
 848 {
 849     return (int32_t)cpu_mips_get_count(env);
 850 }
 851
 852 target_ulong helper_mftc0_entryhi(CPUMIPSState *env)
 853 {
 854     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 855     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 856
 857     return other->CP0_EntryHi;
 858 }
 859
 860 target_ulong helper_mftc0_cause(CPUMIPSState *env)
 861 {
 862     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 863     int32_t tccause;
 864     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 865
 866     if (other_tc == other->current_tc) {
 867         tccause = other->CP0_Cause;
 868     } else {
 869         tccause = other->CP0_Cause;
 870     }
 871
 872     return tccause;
 873 }
 874
 875 target_ulong helper_mftc0_status(CPUMIPSState *env)
 876 {
 877     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 878     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 879
 880     return other->CP0_Status;
 881 }
 882
 883 target_ulong helper_mfc0_lladdr(CPUMIPSState *env)
 884 {
 885     return (int32_t)(env->lladdr >> env->CP0_LLAddr_shift);
 886 }
 887
 888 target_ulong helper_mfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 889 {
 890     return (int32_t)env->CP0_WatchLo[sel];
 891 }
 892
 893 target_ulong helper_mfc0_watchhi(CPUMIPSState *env, uint32_t sel)
 894 {
 895     return env->CP0_WatchHi[sel];
 896 }
 897
 898 target_ulong helper_mfc0_debug(CPUMIPSState *env)
 899 {
 900     target_ulong t0 = env->CP0_Debug;
 901     if (env->hflags & MIPS_HFLAG_DM)
 902         t0 |= 1 << CP0DB_DM;
 903
 904     return t0;
 905 }
 906
 907 target_ulong helper_mftc0_debug(CPUMIPSState *env)
 908 {
 909     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
 910     int32_t tcstatus;
 911     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
 912
 913     if (other_tc == other->current_tc)
 914         tcstatus = other->active_tc.CP0_Debug_tcstatus;
 915     else
 916         tcstatus = other->tcs[other_tc].CP0_Debug_tcstatus;
 917
 918     /* XXX: Might be wrong, check with EJTAG spec. */
 919     return (other->CP0_Debug & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
 920             (tcstatus & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
 921 }
 922
 923 #if defined(TARGET_MIPS64)
 924 target_ulong helper_dmfc0_tcrestart(CPUMIPSState *env)
 925 {
 926     return env->active_tc.PC;
 927 }
 928
 929 target_ulong helper_dmfc0_tchalt(CPUMIPSState *env)
 930 {
 931     return env->active_tc.CP0_TCHalt;
 932 }
 933
 934 target_ulong helper_dmfc0_tccontext(CPUMIPSState *env)
 935 {
 936     return env->active_tc.CP0_TCContext;
 937 }
 938
 939 target_ulong helper_dmfc0_tcschedule(CPUMIPSState *env)
 940 {
 941     return env->active_tc.CP0_TCSchedule;
 942 }
 943
 944 target_ulong helper_dmfc0_tcschefback(CPUMIPSState *env)
 945 {
 946     return env->active_tc.CP0_TCScheFBack;
 947 }
 948
 949 target_ulong helper_dmfc0_lladdr(CPUMIPSState *env)
 950 {
 951     return env->lladdr >> env->CP0_LLAddr_shift;
 952 }
 953
 954 target_ulong helper_dmfc0_watchlo(CPUMIPSState *env, uint32_t sel)
 955 {
 956     return env->CP0_WatchLo[sel];
 957 }
 958 #endif /* TARGET_MIPS64 */
 959
 960 void helper_mtc0_index(CPUMIPSState *env, target_ulong arg1)
 961 {
 962     int num = 1;
 963     unsigned int tmp = env->tlb->nb_tlb;
 964
 965     do {
 966         tmp >>= 1;
 967         num <<= 1;
 968     } while (tmp);
 969     env->CP0_Index = (env->CP0_Index & 0x80000000) | (arg1 & (num - 1));
 970 }
 971
 972 void helper_mtc0_mvpcontrol(CPUMIPSState *env, target_ulong arg1)
 973 {
 974     uint32_t mask = 0;
 975     uint32_t newval;
 976
 977     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP))
 978         mask |= (1 << CP0MVPCo_CPA) | (1 << CP0MVPCo_VPC) |
 979                 (1 << CP0MVPCo_EVP);
 980     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
 981         mask |= (1 << CP0MVPCo_STLB);
 982     newval = (env->mvp->CP0_MVPControl & ~mask) | (arg1 & mask);
 983
 984     // TODO: Enable/disable shared TLB, enable/disable VPEs.
 985
 986     env->mvp->CP0_MVPControl = newval;
 987 }
 988
 989 void helper_mtc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
 990 {
 991     uint32_t mask;
 992     uint32_t newval;
 993
 994     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
 995            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
 996     newval = (env->CP0_VPEControl & ~mask) | (arg1 & mask);
 997
 998     /* Yield scheduler intercept not implemented. */
 999     /* Gating storage scheduler intercept not implemented. */
1000
1001     // TODO: Enable/disable TCs.
1002
1003     env->CP0_VPEControl = newval;
1004 }
1005
1006 void helper_mttc0_vpecontrol(CPUMIPSState *env, target_ulong arg1)
1007 {
1008     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1009     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1010     uint32_t mask;
1011     uint32_t newval;
1012
1013     mask = (1 << CP0VPECo_YSI) | (1 << CP0VPECo_GSI) |
1014            (1 << CP0VPECo_TE) | (0xff << CP0VPECo_TargTC);
1015     newval = (other->CP0_VPEControl & ~mask) | (arg1 & mask);
1016
1017     /* TODO: Enable/disable TCs.  */
1018
1019     other->CP0_VPEControl = newval;
1020 }
1021
1022 target_ulong helper_mftc0_vpecontrol(CPUMIPSState *env)
1023 {
1024     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1025     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1026     /* FIXME: Mask away return zero on read bits.  */
1027     return other->CP0_VPEControl;
1028 }
1029
1030 target_ulong helper_mftc0_vpeconf0(CPUMIPSState *env)
1031 {
1032     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1033     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1034
1035     return other->CP0_VPEConf0;
1036 }
1037
1038 void helper_mtc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1039 {
1040     uint32_t mask = 0;
1041     uint32_t newval;
1042
1043     if (env->CP0_VPEConf0 & (1 << CP0VPEC0_MVP)) {
1044         if (env->CP0_VPEConf0 & (1 << CP0VPEC0_VPA))
1045             mask |= (0xff << CP0VPEC0_XTC);
1046         mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1047     }
1048     newval = (env->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1049
1050     // TODO: TC exclusive handling due to ERL/EXL.
1051
1052     env->CP0_VPEConf0 = newval;
1053 }
1054
1055 void helper_mttc0_vpeconf0(CPUMIPSState *env, target_ulong arg1)
1056 {
1057     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1058     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1059     uint32_t mask = 0;
1060     uint32_t newval;
1061
1062     mask |= (1 << CP0VPEC0_MVP) | (1 << CP0VPEC0_VPA);
1063     newval = (other->CP0_VPEConf0 & ~mask) | (arg1 & mask);
1064
1065     /* TODO: TC exclusive handling due to ERL/EXL.  */
1066     other->CP0_VPEConf0 = newval;
1067 }
1068
1069 void helper_mtc0_vpeconf1(CPUMIPSState *env, target_ulong arg1)
1070 {
1071     uint32_t mask = 0;
1072     uint32_t newval;
1073
1074     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1075         mask |= (0xff << CP0VPEC1_NCX) | (0xff << CP0VPEC1_NCP2) |
1076                 (0xff << CP0VPEC1_NCP1);
1077     newval = (env->CP0_VPEConf1 & ~mask) | (arg1 & mask);
1078
1079     /* UDI not implemented. */
1080     /* CP2 not implemented. */
1081
1082     // TODO: Handle FPU (CP1) binding.
1083
1084     env->CP0_VPEConf1 = newval;
1085 }
1086
1087 void helper_mtc0_yqmask(CPUMIPSState *env, target_ulong arg1)
1088 {
1089     /* Yield qualifier inputs not implemented. */
1090     env->CP0_YQMask = 0x00000000;
1091 }
1092
1093 void helper_mtc0_vpeopt(CPUMIPSState *env, target_ulong arg1)
1094 {
1095     env->CP0_VPEOpt = arg1 & 0x0000ffff;
1096 }
1097
1098 void helper_mtc0_entrylo0(CPUMIPSState *env, target_ulong arg1)
1099 {
1100     /* Large physaddr (PABITS) not implemented */
1101     /* 1k pages not implemented */
1102     target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1103     env->CP0_EntryLo0 = (arg1 & 0x3FFFFFFF) | (rxi << (CP0EnLo_XI - 30));
1104 }
1105
1106 #if defined(TARGET_MIPS64)
1107 void helper_dmtc0_entrylo0(CPUMIPSState *env, uint64_t arg1)
1108 {
1109     uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1110     env->CP0_EntryLo0 = (arg1 & 0x3FFFFFFF) | rxi;
1111 }
1112 #endif
1113
1114 void helper_mtc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1115 {
1116     uint32_t mask = env->CP0_TCStatus_rw_bitmask;
1117     uint32_t newval;
1118
1119     newval = (env->active_tc.CP0_TCStatus & ~mask) | (arg1 & mask);
1120
1121     env->active_tc.CP0_TCStatus = newval;
1122     sync_c0_tcstatus(env, env->current_tc, newval);
1123 }
1124
1125 void helper_mttc0_tcstatus(CPUMIPSState *env, target_ulong arg1)
1126 {
1127     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1128     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1129
1130     if (other_tc == other->current_tc)
1131         other->active_tc.CP0_TCStatus = arg1;
1132     else
1133         other->tcs[other_tc].CP0_TCStatus = arg1;
1134     sync_c0_tcstatus(other, other_tc, arg1);
1135 }
1136
1137 void helper_mtc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1138 {
1139     uint32_t mask = (1 << CP0TCBd_TBE);
1140     uint32_t newval;
1141
1142     if (env->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1143         mask |= (1 << CP0TCBd_CurVPE);
1144     newval = (env->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1145     env->active_tc.CP0_TCBind = newval;
1146 }
1147
1148 void helper_mttc0_tcbind(CPUMIPSState *env, target_ulong arg1)
1149 {
1150     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1151     uint32_t mask = (1 << CP0TCBd_TBE);
1152     uint32_t newval;
1153     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1154
1155     if (other->mvp->CP0_MVPControl & (1 << CP0MVPCo_VPC))
1156         mask |= (1 << CP0TCBd_CurVPE);
1157     if (other_tc == other->current_tc) {
1158         newval = (other->active_tc.CP0_TCBind & ~mask) | (arg1 & mask);
1159         other->active_tc.CP0_TCBind = newval;
1160     } else {
1161         newval = (other->tcs[other_tc].CP0_TCBind & ~mask) | (arg1 & mask);
1162         other->tcs[other_tc].CP0_TCBind = newval;
1163     }
1164 }
1165
1166 void helper_mtc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1167 {
1168     env->active_tc.PC = arg1;
1169     env->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1170     env->lladdr = 0ULL;
1171     /* MIPS16 not implemented. */
1172 }
1173
1174 void helper_mttc0_tcrestart(CPUMIPSState *env, target_ulong arg1)
1175 {
1176     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1177     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1178
1179     if (other_tc == other->current_tc) {
1180         other->active_tc.PC = arg1;
1181         other->active_tc.CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1182         other->lladdr = 0ULL;
1183         /* MIPS16 not implemented. */
1184     } else {
1185         other->tcs[other_tc].PC = arg1;
1186         other->tcs[other_tc].CP0_TCStatus &= ~(1 << CP0TCSt_TDS);
1187         other->lladdr = 0ULL;
1188         /* MIPS16 not implemented. */
1189     }
1190 }
1191
1192 void helper_mtc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1193 {
1194     MIPSCPU *cpu = mips_env_get_cpu(env);
1195
1196     env->active_tc.CP0_TCHalt = arg1 & 0x1;
1197
1198     // TODO: Halt TC / Restart (if allocated+active) TC.
1199     if (env->active_tc.CP0_TCHalt & 1) {
1200         mips_tc_sleep(cpu, env->current_tc);
1201     } else {
1202         mips_tc_wake(cpu, env->current_tc);
1203     }
1204 }
1205
1206 void helper_mttc0_tchalt(CPUMIPSState *env, target_ulong arg1)
1207 {
1208     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1209     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1210     MIPSCPU *other_cpu = mips_env_get_cpu(other);
1211
1212     // TODO: Halt TC / Restart (if allocated+active) TC.
1213
1214     if (other_tc == other->current_tc)
1215         other->active_tc.CP0_TCHalt = arg1;
1216     else
1217         other->tcs[other_tc].CP0_TCHalt = arg1;
1218
1219     if (arg1 & 1) {
1220         mips_tc_sleep(other_cpu, other_tc);
1221     } else {
1222         mips_tc_wake(other_cpu, other_tc);
1223     }
1224 }
1225
1226 void helper_mtc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1227 {
1228     env->active_tc.CP0_TCContext = arg1;
1229 }
1230
1231 void helper_mttc0_tccontext(CPUMIPSState *env, target_ulong arg1)
1232 {
1233     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1234     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1235
1236     if (other_tc == other->current_tc)
1237         other->active_tc.CP0_TCContext = arg1;
1238     else
1239         other->tcs[other_tc].CP0_TCContext = arg1;
1240 }
1241
1242 void helper_mtc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1243 {
1244     env->active_tc.CP0_TCSchedule = arg1;
1245 }
1246
1247 void helper_mttc0_tcschedule(CPUMIPSState *env, target_ulong arg1)
1248 {
1249     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1250     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1251
1252     if (other_tc == other->current_tc)
1253         other->active_tc.CP0_TCSchedule = arg1;
1254     else
1255         other->tcs[other_tc].CP0_TCSchedule = arg1;
1256 }
1257
1258 void helper_mtc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1259 {
1260     env->active_tc.CP0_TCScheFBack = arg1;
1261 }
1262
1263 void helper_mttc0_tcschefback(CPUMIPSState *env, target_ulong arg1)
1264 {
1265     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1266     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1267
1268     if (other_tc == other->current_tc)
1269         other->active_tc.CP0_TCScheFBack = arg1;
1270     else
1271         other->tcs[other_tc].CP0_TCScheFBack = arg1;
1272 }
1273
1274 void helper_mtc0_entrylo1(CPUMIPSState *env, target_ulong arg1)
1275 {
1276     /* Large physaddr (PABITS) not implemented */
1277     /* 1k pages not implemented */
1278     target_ulong rxi = arg1 & (env->CP0_PageGrain & (3u << CP0PG_XIE));
1279     env->CP0_EntryLo1 = (arg1 & 0x3FFFFFFF) | (rxi << (CP0EnLo_XI - 30));
1280 }
1281
1282 #if defined(TARGET_MIPS64)
1283 void helper_dmtc0_entrylo1(CPUMIPSState *env, uint64_t arg1)
1284 {
1285     uint64_t rxi = arg1 & ((env->CP0_PageGrain & (3ull << CP0PG_XIE)) << 32);
1286     env->CP0_EntryLo1 = (arg1 & 0x3FFFFFFF) | rxi;
1287 }
1288 #endif
1289
1290 void helper_mtc0_context(CPUMIPSState *env, target_ulong arg1)
1291 {
1292     env->CP0_Context = (env->CP0_Context & 0x007FFFFF) | (arg1 & ~0x007FFFFF);
1293 }
1294
1295 void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1)
1296 {
1297     /* 1k pages not implemented */
1298     env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1));
1299 }
1300
1301 void helper_mtc0_pagegrain(CPUMIPSState *env, target_ulong arg1)
1302 {
1303     /* SmartMIPS not implemented */
1304     /* Large physaddr (PABITS) not implemented */
1305     /* 1k pages not implemented */
1306     env->CP0_PageGrain = (arg1 & env->CP0_PageGrain_rw_bitmask) |
1307                          (env->CP0_PageGrain & ~env->CP0_PageGrain_rw_bitmask);
1308 }
1309
1310 void helper_mtc0_wired(CPUMIPSState *env, target_ulong arg1)
1311 {
1312     env->CP0_Wired = arg1 % env->tlb->nb_tlb;
1313 }
1314
1315 void helper_mtc0_srsconf0(CPUMIPSState *env, target_ulong arg1)
1316 {
1317     env->CP0_SRSConf0 |= arg1 & env->CP0_SRSConf0_rw_bitmask;
1318 }
1319
1320 void helper_mtc0_srsconf1(CPUMIPSState *env, target_ulong arg1)
1321 {
1322     env->CP0_SRSConf1 |= arg1 & env->CP0_SRSConf1_rw_bitmask;
1323 }
1324
1325 void helper_mtc0_srsconf2(CPUMIPSState *env, target_ulong arg1)
1326 {
1327     env->CP0_SRSConf2 |= arg1 & env->CP0_SRSConf2_rw_bitmask;
1328 }
1329
1330 void helper_mtc0_srsconf3(CPUMIPSState *env, target_ulong arg1)
1331 {
1332     env->CP0_SRSConf3 |= arg1 & env->CP0_SRSConf3_rw_bitmask;
1333 }
1334
1335 void helper_mtc0_srsconf4(CPUMIPSState *env, target_ulong arg1)
1336 {
1337     env->CP0_SRSConf4 |= arg1 & env->CP0_SRSConf4_rw_bitmask;
1338 }
1339
1340 void helper_mtc0_hwrena(CPUMIPSState *env, target_ulong arg1)
1341 {
1342     uint32_t mask = 0x0000000F;
1343
1344     if (env->CP0_Config3 & (1 << CP0C3_ULRI)) {
1345         mask |= (1 << 29);
1346
1347         if (arg1 & (1 << 29)) {
1348             env->hflags |= MIPS_HFLAG_HWRENA_ULR;
1349         } else {
1350             env->hflags &= ~MIPS_HFLAG_HWRENA_ULR;
1351         }
1352     }
1353
1354     env->CP0_HWREna = arg1 & mask;
1355 }
1356
1357 void helper_mtc0_count(CPUMIPSState *env, target_ulong arg1)
1358 {
1359     cpu_mips_store_count(env, arg1);
1360 }
1361
1362 void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1363 {
1364     target_ulong old, val, mask;
1365     mask = (TARGET_PAGE_MASK << 1) | 0xFF;
1366     if (((env->CP0_Config4 >> CP0C4_IE) & 0x3) >= 2) {
1367         mask |= 1 << CP0EnHi_EHINV;
1368     }
1369
1370     /* 1k pages not implemented */
1371     val = arg1 & mask;
1372 #if defined(TARGET_MIPS64)
1373     val &= env->SEGMask;
1374 #endif
1375     old = env->CP0_EntryHi;
1376     env->CP0_EntryHi = val;
1377     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1378         sync_c0_entryhi(env, env->current_tc);
1379     }
1380     /* If the ASID changes, flush qemu's TLB.  */
1381     if ((old & 0xFF) != (val & 0xFF))
1382         cpu_mips_tlb_flush(env, 1);
1383 }
1384
1385 void helper_mttc0_entryhi(CPUMIPSState *env, target_ulong arg1)
1386 {
1387     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1388     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1389
1390     other->CP0_EntryHi = arg1;
1391     sync_c0_entryhi(other, other_tc);
1392 }
1393
1394 void helper_mtc0_compare(CPUMIPSState *env, target_ulong arg1)
1395 {
1396     cpu_mips_store_compare(env, arg1);
1397 }
1398
1399 void helper_mtc0_status(CPUMIPSState *env, target_ulong arg1)
1400 {
1401     MIPSCPU *cpu = mips_env_get_cpu(env);
1402     uint32_t val, old;
1403     uint32_t mask = env->CP0_Status_rw_bitmask;
1404
1405     val = arg1 & mask;
1406     old = env->CP0_Status;
1407     env->CP0_Status = (env->CP0_Status & ~mask) | val;
1408     if (env->CP0_Config3 & (1 << CP0C3_MT)) {
1409         sync_c0_status(env, env, env->current_tc);
1410     } else {
1411         compute_hflags(env);
1412     }
1413
1414     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
1415         qemu_log("Status %08x (%08x) => %08x (%08x) Cause %08x",
1416                 old, old & env->CP0_Cause & CP0Ca_IP_mask,
1417                 val, val & env->CP0_Cause & CP0Ca_IP_mask,
1418                 env->CP0_Cause);
1419         switch (env->hflags & MIPS_HFLAG_KSU) {
1420         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
1421         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
1422         case MIPS_HFLAG_KM: qemu_log("\n"); break;
1423         default:
1424             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
1425             break;
1426         }
1427     }
1428 }
1429
1430 void helper_mttc0_status(CPUMIPSState *env, target_ulong arg1)
1431 {
1432     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1433     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1434
1435     other->CP0_Status = arg1 & ~0xf1000018;
1436     sync_c0_status(env, other, other_tc);
1437 }
1438
1439 void helper_mtc0_intctl(CPUMIPSState *env, target_ulong arg1)
1440 {
1441     /* vectored interrupts not implemented, no performance counters. */
1442     env->CP0_IntCtl = (env->CP0_IntCtl & ~0x000003e0) | (arg1 & 0x000003e0);
1443 }
1444
1445 void helper_mtc0_srsctl(CPUMIPSState *env, target_ulong arg1)
1446 {
1447     uint32_t mask = (0xf << CP0SRSCtl_ESS) | (0xf << CP0SRSCtl_PSS);
1448     env->CP0_SRSCtl = (env->CP0_SRSCtl & ~mask) | (arg1 & mask);
1449 }
1450
1451 static void mtc0_cause(CPUMIPSState *cpu, target_ulong arg1)
1452 {
1453     uint32_t mask = 0x00C00300;
1454     uint32_t old = cpu->CP0_Cause;
1455     int i;
1456
1457     if (cpu->insn_flags & ISA_MIPS32R2) {
1458         mask |= 1 << CP0Ca_DC;
1459     }
1460
1461     cpu->CP0_Cause = (cpu->CP0_Cause & ~mask) | (arg1 & mask);
1462
1463     if ((old ^ cpu->CP0_Cause) & (1 << CP0Ca_DC)) {
1464         if (cpu->CP0_Cause & (1 << CP0Ca_DC)) {
1465             cpu_mips_stop_count(cpu);
1466         } else {
1467             cpu_mips_start_count(cpu);
1468         }
1469     }
1470
1471     /* Set/reset software interrupts */
1472     for (i = 0 ; i < 2 ; i++) {
1473         if ((old ^ cpu->CP0_Cause) & (1 << (CP0Ca_IP + i))) {
1474             cpu_mips_soft_irq(cpu, i, cpu->CP0_Cause & (1 << (CP0Ca_IP + i)));
1475         }
1476     }
1477 }
1478
1479 void helper_mtc0_cause(CPUMIPSState *env, target_ulong arg1)
1480 {
1481     mtc0_cause(env, arg1);
1482 }
1483
1484 void helper_mttc0_cause(CPUMIPSState *env, target_ulong arg1)
1485 {
1486     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1487     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1488
1489     mtc0_cause(other, arg1);
1490 }
1491
1492 target_ulong helper_mftc0_epc(CPUMIPSState *env)
1493 {
1494     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1495     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1496
1497     return other->CP0_EPC;
1498 }
1499
1500 target_ulong helper_mftc0_ebase(CPUMIPSState *env)
1501 {
1502     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1503     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1504
1505     return other->CP0_EBase;
1506 }
1507
1508 void helper_mtc0_ebase(CPUMIPSState *env, target_ulong arg1)
1509 {
1510     /* vectored interrupts not implemented */
1511     env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1512 }
1513
1514 void helper_mttc0_ebase(CPUMIPSState *env, target_ulong arg1)
1515 {
1516     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1517     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1518     other->CP0_EBase = (other->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000);
1519 }
1520
1521 target_ulong helper_mftc0_configx(CPUMIPSState *env, target_ulong idx)
1522 {
1523     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1524     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1525
1526     switch (idx) {
1527     case 0: return other->CP0_Config0;
1528     case 1: return other->CP0_Config1;
1529     case 2: return other->CP0_Config2;
1530     case 3: return other->CP0_Config3;
1531     /* 4 and 5 are reserved.  */
1532     case 6: return other->CP0_Config6;
1533     case 7: return other->CP0_Config7;
1534     default:
1535         break;
1536     }
1537     return 0;
1538 }
1539
1540 void helper_mtc0_config0(CPUMIPSState *env, target_ulong arg1)
1541 {
1542     env->CP0_Config0 = (env->CP0_Config0 & 0x81FFFFF8) | (arg1 & 0x00000007);
1543 }
1544
1545 void helper_mtc0_config2(CPUMIPSState *env, target_ulong arg1)
1546 {
1547     /* tertiary/secondary caches not implemented */
1548     env->CP0_Config2 = (env->CP0_Config2 & 0x8FFF0FFF);
1549 }
1550
1551 void helper_mtc0_config4(CPUMIPSState *env, target_ulong arg1)
1552 {
1553     env->CP0_Config4 = (env->CP0_Config4 & (~env->CP0_Config4_rw_bitmask)) |
1554                        (arg1 & env->CP0_Config4_rw_bitmask);
1555 }
1556
1557 void helper_mtc0_config5(CPUMIPSState *env, target_ulong arg1)
1558 {
1559     env->CP0_Config5 = (env->CP0_Config5 & (~env->CP0_Config5_rw_bitmask)) |
1560                        (arg1 & env->CP0_Config5_rw_bitmask);
1561 }
1562
1563 void helper_mtc0_lladdr(CPUMIPSState *env, target_ulong arg1)
1564 {
1565     target_long mask = env->CP0_LLAddr_rw_bitmask;
1566     arg1 = arg1 << env->CP0_LLAddr_shift;
1567     env->lladdr = (env->lladdr & ~mask) | (arg1 & mask);
1568 }
1569
1570 void helper_mtc0_watchlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1571 {
1572     /* Watch exceptions for instructions, data loads, data stores
1573        not implemented. */
1574     env->CP0_WatchLo[sel] = (arg1 & ~0x7);
1575 }
1576
1577 void helper_mtc0_watchhi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1578 {
1579     env->CP0_WatchHi[sel] = (arg1 & 0x40FF0FF8);
1580     env->CP0_WatchHi[sel] &= ~(env->CP0_WatchHi[sel] & arg1 & 0x7);
1581 }
1582
1583 void helper_mtc0_xcontext(CPUMIPSState *env, target_ulong arg1)
1584 {
1585     target_ulong mask = (1ULL << (env->SEGBITS - 7)) - 1;
1586     env->CP0_XContext = (env->CP0_XContext & mask) | (arg1 & ~mask);
1587 }
1588
1589 void helper_mtc0_framemask(CPUMIPSState *env, target_ulong arg1)
1590 {
1591     env->CP0_Framemask = arg1; /* XXX */
1592 }
1593
1594 void helper_mtc0_debug(CPUMIPSState *env, target_ulong arg1)
1595 {
1596     env->CP0_Debug = (env->CP0_Debug & 0x8C03FC1F) | (arg1 & 0x13300120);
1597     if (arg1 & (1 << CP0DB_DM))
1598         env->hflags |= MIPS_HFLAG_DM;
1599     else
1600         env->hflags &= ~MIPS_HFLAG_DM;
1601 }
1602
1603 void helper_mttc0_debug(CPUMIPSState *env, target_ulong arg1)
1604 {
1605     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1606     uint32_t val = arg1 & ((1 << CP0DB_SSt) | (1 << CP0DB_Halt));
1607     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1608
1609     /* XXX: Might be wrong, check with EJTAG spec. */
1610     if (other_tc == other->current_tc)
1611         other->active_tc.CP0_Debug_tcstatus = val;
1612     else
1613         other->tcs[other_tc].CP0_Debug_tcstatus = val;
1614     other->CP0_Debug = (other->CP0_Debug &
1615                      ((1 << CP0DB_SSt) | (1 << CP0DB_Halt))) |
1616                      (arg1 & ~((1 << CP0DB_SSt) | (1 << CP0DB_Halt)));
1617 }
1618
1619 void helper_mtc0_performance0(CPUMIPSState *env, target_ulong arg1)
1620 {
1621     env->CP0_Performance0 = arg1 & 0x000007ff;
1622 }
1623
1624 void helper_mtc0_taglo(CPUMIPSState *env, target_ulong arg1)
1625 {
1626     env->CP0_TagLo = arg1 & 0xFFFFFCF6;
1627 }
1628
1629 void helper_mtc0_datalo(CPUMIPSState *env, target_ulong arg1)
1630 {
1631     env->CP0_DataLo = arg1; /* XXX */
1632 }
1633
1634 void helper_mtc0_taghi(CPUMIPSState *env, target_ulong arg1)
1635 {
1636     env->CP0_TagHi = arg1; /* XXX */
1637 }
1638
1639 void helper_mtc0_datahi(CPUMIPSState *env, target_ulong arg1)
1640 {
1641     env->CP0_DataHi = arg1; /* XXX */
1642 }
1643
1644 /* MIPS MT functions */
1645 target_ulong helper_mftgpr(CPUMIPSState *env, uint32_t sel)
1646 {
1647     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1648     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1649
1650     if (other_tc == other->current_tc)
1651         return other->active_tc.gpr[sel];
1652     else
1653         return other->tcs[other_tc].gpr[sel];
1654 }
1655
1656 target_ulong helper_mftlo(CPUMIPSState *env, uint32_t sel)
1657 {
1658     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1659     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1660
1661     if (other_tc == other->current_tc)
1662         return other->active_tc.LO[sel];
1663     else
1664         return other->tcs[other_tc].LO[sel];
1665 }
1666
1667 target_ulong helper_mfthi(CPUMIPSState *env, uint32_t sel)
1668 {
1669     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1670     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1671
1672     if (other_tc == other->current_tc)
1673         return other->active_tc.HI[sel];
1674     else
1675         return other->tcs[other_tc].HI[sel];
1676 }
1677
1678 target_ulong helper_mftacx(CPUMIPSState *env, uint32_t sel)
1679 {
1680     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1681     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1682
1683     if (other_tc == other->current_tc)
1684         return other->active_tc.ACX[sel];
1685     else
1686         return other->tcs[other_tc].ACX[sel];
1687 }
1688
1689 target_ulong helper_mftdsp(CPUMIPSState *env)
1690 {
1691     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1692     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1693
1694     if (other_tc == other->current_tc)
1695         return other->active_tc.DSPControl;
1696     else
1697         return other->tcs[other_tc].DSPControl;
1698 }
1699
1700 void helper_mttgpr(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1701 {
1702     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1703     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1704
1705     if (other_tc == other->current_tc)
1706         other->active_tc.gpr[sel] = arg1;
1707     else
1708         other->tcs[other_tc].gpr[sel] = arg1;
1709 }
1710
1711 void helper_mttlo(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1712 {
1713     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1714     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1715
1716     if (other_tc == other->current_tc)
1717         other->active_tc.LO[sel] = arg1;
1718     else
1719         other->tcs[other_tc].LO[sel] = arg1;
1720 }
1721
1722 void helper_mtthi(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1723 {
1724     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1725     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1726
1727     if (other_tc == other->current_tc)
1728         other->active_tc.HI[sel] = arg1;
1729     else
1730         other->tcs[other_tc].HI[sel] = arg1;
1731 }
1732
1733 void helper_mttacx(CPUMIPSState *env, target_ulong arg1, uint32_t sel)
1734 {
1735     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1736     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1737
1738     if (other_tc == other->current_tc)
1739         other->active_tc.ACX[sel] = arg1;
1740     else
1741         other->tcs[other_tc].ACX[sel] = arg1;
1742 }
1743
1744 void helper_mttdsp(CPUMIPSState *env, target_ulong arg1)
1745 {
1746     int other_tc = env->CP0_VPEControl & (0xff << CP0VPECo_TargTC);
1747     CPUMIPSState *other = mips_cpu_map_tc(env, &other_tc);
1748
1749     if (other_tc == other->current_tc)
1750         other->active_tc.DSPControl = arg1;
1751     else
1752         other->tcs[other_tc].DSPControl = arg1;
1753 }
1754
1755 /* MIPS MT functions */
1756 target_ulong helper_dmt(void)
1757 {
1758     // TODO
1759      return 0;
1760 }
1761
1762 target_ulong helper_emt(void)
1763 {
1764     // TODO
1765     return 0;
1766 }
1767
1768 target_ulong helper_dvpe(CPUMIPSState *env)
1769 {
1770     CPUState *other_cs = first_cpu;
1771     target_ulong prev = env->mvp->CP0_MVPControl;
1772
1773     CPU_FOREACH(other_cs) {
1774         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1775         /* Turn off all VPEs except the one executing the dvpe.  */
1776         if (&other_cpu->env != env) {
1777             other_cpu->env.mvp->CP0_MVPControl &= ~(1 << CP0MVPCo_EVP);
1778             mips_vpe_sleep(other_cpu);
1779         }
1780     }
1781     return prev;
1782 }
1783
1784 target_ulong helper_evpe(CPUMIPSState *env)
1785 {
1786     CPUState *other_cs = first_cpu;
1787     target_ulong prev = env->mvp->CP0_MVPControl;
1788
1789     CPU_FOREACH(other_cs) {
1790         MIPSCPU *other_cpu = MIPS_CPU(other_cs);
1791
1792         if (&other_cpu->env != env
1793             /* If the VPE is WFI, don't disturb its sleep.  */
1794             && !mips_vpe_is_wfi(other_cpu)) {
1795             /* Enable the VPE.  */
1796             other_cpu->env.mvp->CP0_MVPControl |= (1 << CP0MVPCo_EVP);
1797             mips_vpe_wake(other_cpu); /* And wake it up.  */
1798         }
1799     }
1800     return prev;
1801 }
1802 #endif /* !CONFIG_USER_ONLY */
1803
1804 void helper_fork(target_ulong arg1, target_ulong arg2)
1805 {
1806     // arg1 = rt, arg2 = rs
1807     // TODO: store to TC register
1808 }
1809
1810 target_ulong helper_yield(CPUMIPSState *env, target_ulong arg)
1811 {
1812     target_long arg1 = arg;
1813
1814     if (arg1 < 0) {
1815         /* No scheduling policy implemented. */
1816         if (arg1 != -2) {
1817             if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) &&
1818                 env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) {
1819                 env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1820                 env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT;
1821                 helper_raise_exception(env, EXCP_THREAD);
1822             }
1823         }
1824     } else if (arg1 == 0) {
1825         if (0 /* TODO: TC underflow */) {
1826             env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1827             helper_raise_exception(env, EXCP_THREAD);
1828         } else {
1829             // TODO: Deallocate TC
1830         }
1831     } else if (arg1 > 0) {
1832         /* Yield qualifier inputs not implemented. */
1833         env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT);
1834         env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT;
1835         helper_raise_exception(env, EXCP_THREAD);
1836     }
1837     return env->CP0_YQMask;
1838 }
1839
1840 #ifndef CONFIG_USER_ONLY
1841 /* TLB management */
1842 static void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global)
1843 {
1844     MIPSCPU *cpu = mips_env_get_cpu(env);
1845
1846     /* Flush qemu's TLB and discard all shadowed entries.  */
1847     tlb_flush(CPU(cpu), flush_global);
1848     env->tlb->tlb_in_use = env->tlb->nb_tlb;
1849 }
1850
1851 static void r4k_mips_tlb_flush_extra (CPUMIPSState *env, int first)
1852 {
1853     /* Discard entries from env->tlb[first] onwards.  */
1854     while (env->tlb->tlb_in_use > first) {
1855         r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0);
1856     }
1857 }
1858
1859 static void r4k_fill_tlb(CPUMIPSState *env, int idx)
1860 {
1861     r4k_tlb_t *tlb;
1862
1863     /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */
1864     tlb = &env->tlb->mmu.r4k.tlb[idx];
1865     if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) {
1866         tlb->EHINV = 1;
1867         return;
1868     }
1869     tlb->EHINV = 0;
1870     tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1871 #if defined(TARGET_MIPS64)
1872     tlb->VPN &= env->SEGMask;
1873 #endif
1874     tlb->ASID = env->CP0_EntryHi & 0xFF;
1875     tlb->PageMask = env->CP0_PageMask;
1876     tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1877     tlb->V0 = (env->CP0_EntryLo0 & 2) != 0;
1878     tlb->D0 = (env->CP0_EntryLo0 & 4) != 0;
1879     tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7;
1880     tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1;
1881     tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1;
1882     tlb->PFN[0] = (env->CP0_EntryLo0 >> 6) << 12;
1883     tlb->V1 = (env->CP0_EntryLo1 & 2) != 0;
1884     tlb->D1 = (env->CP0_EntryLo1 & 4) != 0;
1885     tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7;
1886     tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1;
1887     tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1;
1888     tlb->PFN[1] = (env->CP0_EntryLo1 >> 6) << 12;
1889 }
1890
1891 void r4k_helper_tlbinv(CPUMIPSState *env)
1892 {
1893     int idx;
1894     r4k_tlb_t *tlb;
1895     uint8_t ASID = env->CP0_EntryHi & 0xFF;
1896
1897     for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
1898         tlb = &env->tlb->mmu.r4k.tlb[idx];
1899         if (!tlb->G && tlb->ASID == ASID) {
1900             tlb->EHINV = 1;
1901         }
1902     }
1903     cpu_mips_tlb_flush(env, 1);
1904 }
1905
1906 void r4k_helper_tlbinvf(CPUMIPSState *env)
1907 {
1908     int idx;
1909
1910     for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
1911         env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
1912     }
1913     cpu_mips_tlb_flush(env, 1);
1914 }
1915
1916 void r4k_helper_tlbwi(CPUMIPSState *env)
1917 {
1918     r4k_tlb_t *tlb;
1919     int idx;
1920     target_ulong VPN;
1921     uint8_t ASID;
1922     bool G, V0, D0, V1, D1;
1923
1924     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
1925     tlb = &env->tlb->mmu.r4k.tlb[idx];
1926     VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1);
1927 #if defined(TARGET_MIPS64)
1928     VPN &= env->SEGMask;
1929 #endif
1930     ASID = env->CP0_EntryHi & 0xff;
1931     G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1;
1932     V0 = (env->CP0_EntryLo0 & 2) != 0;
1933     D0 = (env->CP0_EntryLo0 & 4) != 0;
1934     V1 = (env->CP0_EntryLo1 & 2) != 0;
1935     D1 = (env->CP0_EntryLo1 & 4) != 0;
1936
1937     /* Discard cached TLB entries, unless tlbwi is just upgrading access
1938        permissions on the current entry. */
1939     if (tlb->VPN != VPN || tlb->ASID != ASID || tlb->G != G ||
1940         (tlb->V0 && !V0) || (tlb->D0 && !D0) ||
1941         (tlb->V1 && !V1) || (tlb->D1 && !D1)) {
1942         r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
1943     }
1944
1945     r4k_invalidate_tlb(env, idx, 0);
1946     r4k_fill_tlb(env, idx);
1947 }
1948
1949 void r4k_helper_tlbwr(CPUMIPSState *env)
1950 {
1951     int r = cpu_mips_get_random(env);
1952
1953     r4k_invalidate_tlb(env, r, 1);
1954     r4k_fill_tlb(env, r);
1955 }
1956
1957 void r4k_helper_tlbp(CPUMIPSState *env)
1958 {
1959     r4k_tlb_t *tlb;
1960     target_ulong mask;
1961     target_ulong tag;
1962     target_ulong VPN;
1963     uint8_t ASID;
1964     int i;
1965
1966     ASID = env->CP0_EntryHi & 0xFF;
1967     for (i = 0; i < env->tlb->nb_tlb; i++) {
1968         tlb = &env->tlb->mmu.r4k.tlb[i];
1969         /* 1k pages are not supported. */
1970         mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1971         tag = env->CP0_EntryHi & ~mask;
1972         VPN = tlb->VPN & ~mask;
1973 #if defined(TARGET_MIPS64)
1974         tag &= env->SEGMask;
1975 #endif
1976         /* Check ASID, virtual page number & size */
1977         if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag && !tlb->EHINV) {
1978             /* TLB match */
1979             env->CP0_Index = i;
1980             break;
1981         }
1982     }
1983     if (i == env->tlb->nb_tlb) {
1984         /* No match.  Discard any shadow entries, if any of them match.  */
1985         for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) {
1986             tlb = &env->tlb->mmu.r4k.tlb[i];
1987             /* 1k pages are not supported. */
1988             mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1);
1989             tag = env->CP0_EntryHi & ~mask;
1990             VPN = tlb->VPN & ~mask;
1991 #if defined(TARGET_MIPS64)
1992             tag &= env->SEGMask;
1993 #endif
1994             /* Check ASID, virtual page number & size */
1995             if ((tlb->G == 1 || tlb->ASID == ASID) && VPN == tag) {
1996                 r4k_mips_tlb_flush_extra (env, i);
1997                 break;
1998             }
1999         }
2000
2001         env->CP0_Index |= 0x80000000;
2002     }
2003 }
2004
2005 void r4k_helper_tlbr(CPUMIPSState *env)
2006 {
2007     r4k_tlb_t *tlb;
2008     uint8_t ASID;
2009     int idx;
2010
2011     ASID = env->CP0_EntryHi & 0xFF;
2012     idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb;
2013     tlb = &env->tlb->mmu.r4k.tlb[idx];
2014
2015     /* If this will change the current ASID, flush qemu's TLB.  */
2016     if (ASID != tlb->ASID)
2017         cpu_mips_tlb_flush (env, 1);
2018
2019     r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb);
2020
2021     if (tlb->EHINV) {
2022         env->CP0_EntryHi = 1 << CP0EnHi_EHINV;
2023         env->CP0_PageMask = 0;
2024         env->CP0_EntryLo0 = 0;
2025         env->CP0_EntryLo1 = 0;
2026     } else {
2027         env->CP0_EntryHi = tlb->VPN | tlb->ASID;
2028         env->CP0_PageMask = tlb->PageMask;
2029         env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) |
2030                         ((target_ulong)tlb->RI0 << CP0EnLo_RI) |
2031                         ((target_ulong)tlb->XI0 << CP0EnLo_XI) |
2032                         (tlb->C0 << 3) | (tlb->PFN[0] >> 6);
2033         env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) |
2034                         ((target_ulong)tlb->RI1 << CP0EnLo_RI) |
2035                         ((target_ulong)tlb->XI1 << CP0EnLo_XI) |
2036                         (tlb->C1 << 3) | (tlb->PFN[1] >> 6);
2037     }
2038 }
2039
2040 void helper_tlbwi(CPUMIPSState *env)
2041 {
2042     env->tlb->helper_tlbwi(env);
2043 }
2044
2045 void helper_tlbwr(CPUMIPSState *env)
2046 {
2047     env->tlb->helper_tlbwr(env);
2048 }
2049
2050 void helper_tlbp(CPUMIPSState *env)
2051 {
2052     env->tlb->helper_tlbp(env);
2053 }
2054
2055 void helper_tlbr(CPUMIPSState *env)
2056 {
2057     env->tlb->helper_tlbr(env);
2058 }
2059
2060 void helper_tlbinv(CPUMIPSState *env)
2061 {
2062     env->tlb->helper_tlbinv(env);
2063 }
2064
2065 void helper_tlbinvf(CPUMIPSState *env)
2066 {
2067     env->tlb->helper_tlbinvf(env);
2068 }
2069
2070 /* Specials */
2071 target_ulong helper_di(CPUMIPSState *env)
2072 {
2073     target_ulong t0 = env->CP0_Status;
2074
2075     env->CP0_Status = t0 & ~(1 << CP0St_IE);
2076     return t0;
2077 }
2078
2079 target_ulong helper_ei(CPUMIPSState *env)
2080 {
2081     target_ulong t0 = env->CP0_Status;
2082
2083     env->CP0_Status = t0 | (1 << CP0St_IE);
2084     return t0;
2085 }
2086
2087 static void debug_pre_eret(CPUMIPSState *env)
2088 {
2089     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2090         qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2091                 env->active_tc.PC, env->CP0_EPC);
2092         if (env->CP0_Status & (1 << CP0St_ERL))
2093             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2094         if (env->hflags & MIPS_HFLAG_DM)
2095             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2096         qemu_log("\n");
2097     }
2098 }
2099
2100 static void debug_post_eret(CPUMIPSState *env)
2101 {
2102     MIPSCPU *cpu = mips_env_get_cpu(env);
2103
2104     if (qemu_loglevel_mask(CPU_LOG_EXEC)) {
2105         qemu_log("  =>  PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx,
2106                 env->active_tc.PC, env->CP0_EPC);
2107         if (env->CP0_Status & (1 << CP0St_ERL))
2108             qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC);
2109         if (env->hflags & MIPS_HFLAG_DM)
2110             qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC);
2111         switch (env->hflags & MIPS_HFLAG_KSU) {
2112         case MIPS_HFLAG_UM: qemu_log(", UM\n"); break;
2113         case MIPS_HFLAG_SM: qemu_log(", SM\n"); break;
2114         case MIPS_HFLAG_KM: qemu_log("\n"); break;
2115         default:
2116             cpu_abort(CPU(cpu), "Invalid MMU mode!\n");
2117             break;
2118         }
2119     }
2120 }
2121
2122 static void set_pc(CPUMIPSState *env, target_ulong error_pc)
2123 {
2124     env->active_tc.PC = error_pc & ~(target_ulong)1;
2125     if (error_pc & 1) {
2126         env->hflags |= MIPS_HFLAG_M16;
2127     } else {
2128         env->hflags &= ~(MIPS_HFLAG_M16);
2129     }
2130 }
2131
2132 void helper_eret(CPUMIPSState *env)
2133 {
2134     debug_pre_eret(env);
2135     if (env->CP0_Status & (1 << CP0St_ERL)) {
2136         set_pc(env, env->CP0_ErrorEPC);
2137         env->CP0_Status &= ~(1 << CP0St_ERL);
2138     } else {
2139         set_pc(env, env->CP0_EPC);
2140         env->CP0_Status &= ~(1 << CP0St_EXL);
2141     }
2142     compute_hflags(env);
2143     debug_post_eret(env);
2144     env->lladdr = 1;
2145 }
2146
2147 void helper_deret(CPUMIPSState *env)
2148 {
2149     debug_pre_eret(env);
2150     set_pc(env, env->CP0_DEPC);
2151
2152     env->hflags &= MIPS_HFLAG_DM;
2153     compute_hflags(env);
2154     debug_post_eret(env);
2155     env->lladdr = 1;
2156 }
2157 #endif /* !CONFIG_USER_ONLY */
2158
2159 target_ulong helper_rdhwr_cpunum(CPUMIPSState *env)
2160 {
2161     if ((env->hflags & MIPS_HFLAG_CP0) ||
2162         (env->CP0_HWREna & (1 << 0)))
2163         return env->CP0_EBase & 0x3ff;
2164     else
2165         helper_raise_exception(env, EXCP_RI);
2166
2167     return 0;
2168 }
2169
2170 target_ulong helper_rdhwr_synci_step(CPUMIPSState *env)
2171 {
2172     if ((env->hflags & MIPS_HFLAG_CP0) ||
2173         (env->CP0_HWREna & (1 << 1)))
2174         return env->SYNCI_Step;
2175     else
2176         helper_raise_exception(env, EXCP_RI);
2177
2178     return 0;
2179 }
2180
2181 target_ulong helper_rdhwr_cc(CPUMIPSState *env)
2182 {
2183     if ((env->hflags & MIPS_HFLAG_CP0) ||
2184         (env->CP0_HWREna & (1 << 2)))
2185         return env->CP0_Count;
2186     else
2187         helper_raise_exception(env, EXCP_RI);
2188
2189     return 0;
2190 }
2191
2192 target_ulong helper_rdhwr_ccres(CPUMIPSState *env)
2193 {
2194     if ((env->hflags & MIPS_HFLAG_CP0) ||
2195         (env->CP0_HWREna & (1 << 3)))
2196         return env->CCRes;
2197     else
2198         helper_raise_exception(env, EXCP_RI);
2199
2200     return 0;
2201 }
2202
2203 void helper_pmon(CPUMIPSState *env, int function)
2204 {
2205     function /= 2;
2206     switch (function) {
2207     case 2: /* TODO: char inbyte(int waitflag); */
2208         if (env->active_tc.gpr[4] == 0)
2209             env->active_tc.gpr[2] = -1;
2210         /* Fall through */
2211     case 11: /* TODO: char inbyte (void); */
2212         env->active_tc.gpr[2] = -1;
2213         break;
2214     case 3:
2215     case 12:
2216         printf("%c", (char)(env->active_tc.gpr[4] & 0xFF));
2217         break;
2218     case 17:
2219         break;
2220     case 158:
2221         {
2222             unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4];
2223             printf("%s", fmt);
2224         }
2225         break;
2226     }
2227 }
2228
2229 void helper_wait(CPUMIPSState *env)
2230 {
2231     CPUState *cs = CPU(mips_env_get_cpu(env));
2232
2233     cs->halted = 1;
2234     cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE);
2235     helper_raise_exception(env, EXCP_HLT);
2236 }
2237
2238 #if !defined(CONFIG_USER_ONLY)
2239
2240 void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
2241                                   int access_type, int is_user,
2242                                   uintptr_t retaddr)
2243 {
2244     MIPSCPU *cpu = MIPS_CPU(cs);
2245     CPUMIPSState *env = &cpu->env;
2246     int error_code = 0;
2247     int excp;
2248
2249     env->CP0_BadVAddr = addr;
2250
2251     if (access_type == MMU_DATA_STORE) {
2252         excp = EXCP_AdES;
2253     } else {
2254         excp = EXCP_AdEL;
2255         if (access_type == MMU_INST_FETCH) {
2256             error_code |= EXCP_INST_NOTAVAIL;
2257         }
2258     }
2259
2260     do_raise_exception_err(env, excp, error_code, retaddr);
2261 }
2262
2263 void tlb_fill(CPUState *cs, target_ulong addr, int is_write, int mmu_idx,
2264               uintptr_t retaddr)
2265 {
2266     int ret;
2267
2268     ret = mips_cpu_handle_mmu_fault(cs, addr, is_write, mmu_idx);
2269     if (ret) {
2270         MIPSCPU *cpu = MIPS_CPU(cs);
2271         CPUMIPSState *env = &cpu->env;
2272
2273         do_raise_exception_err(env, cs->exception_index,
2274                                env->error_code, retaddr);
2275     }
2276 }
2277
2278 void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr,
2279                                 bool is_write, bool is_exec, int unused,
2280                                 unsigned size)
2281 {
2282     MIPSCPU *cpu = MIPS_CPU(cs);
2283     CPUMIPSState *env = &cpu->env;
2284
2285     /*
2286      * Raising an exception with KVM enabled will crash because it won't be from
2287      * the main execution loop so the longjmp won't have a matching setjmp.
2288      * Until we can trigger a bus error exception through KVM lets just ignore
2289      * the access.
2290      */
2291     if (kvm_enabled()) {
2292         return;
2293     }
2294
2295     if (is_exec) {
2296         helper_raise_exception(env, EXCP_IBE);
2297     } else {
2298         helper_raise_exception(env, EXCP_DBE);
2299     }
2300 }
2301 #endif /* !CONFIG_USER_ONLY */
2302
2303 /* Complex FPU operations which may need stack space. */
2304
2305 #define FLOAT_TWO32 make_float32(1 << 30)
2306 #define FLOAT_TWO64 make_float64(1ULL << 62)
2307 #define FP_TO_INT32_OVERFLOW 0x7fffffff
2308 #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL
2309
2310 /* convert MIPS rounding mode in FCR31 to IEEE library */
2311 static unsigned int ieee_rm[] = {
2312     float_round_nearest_even,
2313     float_round_to_zero,
2314     float_round_up,
2315     float_round_down
2316 };
2317
2318 static inline void restore_rounding_mode(CPUMIPSState *env)
2319 {
2320     set_float_rounding_mode(ieee_rm[env->active_fpu.fcr31 & 3],
2321                             &env->active_fpu.fp_status);
2322 }
2323
2324 static inline void restore_flush_mode(CPUMIPSState *env)
2325 {
2326     set_flush_to_zero((env->active_fpu.fcr31 & (1 << 24)) != 0,
2327                       &env->active_fpu.fp_status);
2328 }
2329
2330 target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg)
2331 {
2332     target_ulong arg1 = 0;
2333
2334     switch (reg) {
2335     case 0:
2336         arg1 = (int32_t)env->active_fpu.fcr0;
2337         break;
2338     case 1:
2339         /* UFR Support - Read Status FR */
2340         if (env->active_fpu.fcr0 & (1 << FCR0_UFRP)) {
2341             if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2342                 arg1 = (int32_t)
2343                        ((env->CP0_Status & (1  << CP0St_FR)) >> CP0St_FR);
2344             } else {
2345                 helper_raise_exception(env, EXCP_RI);
2346             }
2347         }
2348         break;
2349     case 25:
2350         arg1 = ((env->active_fpu.fcr31 >> 24) & 0xfe) | ((env->active_fpu.fcr31 >> 23) & 0x1);
2351         break;
2352     case 26:
2353         arg1 = env->active_fpu.fcr31 & 0x0003f07c;
2354         break;
2355     case 28:
2356         arg1 = (env->active_fpu.fcr31 & 0x00000f83) | ((env->active_fpu.fcr31 >> 22) & 0x4);
2357         break;
2358     default:
2359         arg1 = (int32_t)env->active_fpu.fcr31;
2360         break;
2361     }
2362
2363     return arg1;
2364 }
2365
2366 void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt)
2367 {
2368     switch (fs) {
2369     case 1:
2370         /* UFR Alias - Reset Status FR */
2371         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2372             return;
2373         }
2374         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2375             env->CP0_Status &= ~(1 << CP0St_FR);
2376             compute_hflags(env);
2377         } else {
2378             helper_raise_exception(env, EXCP_RI);
2379         }
2380         break;
2381     case 4:
2382         /* UNFR Alias - Set Status FR */
2383         if (!((env->active_fpu.fcr0 & (1 << FCR0_UFRP)) && (rt == 0))) {
2384             return;
2385         }
2386         if (env->CP0_Config5 & (1 << CP0C5_UFR)) {
2387             env->CP0_Status |= (1 << CP0St_FR);
2388             compute_hflags(env);
2389         } else {
2390             helper_raise_exception(env, EXCP_RI);
2391         }
2392         break;
2393     case 25:
2394         if (arg1 & 0xffffff00)
2395             return;
2396         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0x017fffff) | ((arg1 & 0xfe) << 24) |
2397                      ((arg1 & 0x1) << 23);
2398         break;
2399     case 26:
2400         if (arg1 & 0x007c0000)
2401             return;
2402         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfffc0f83) | (arg1 & 0x0003f07c);
2403         break;
2404     case 28:
2405         if (arg1 & 0x007c0000)
2406             return;
2407         env->active_fpu.fcr31 = (env->active_fpu.fcr31 & 0xfefff07c) | (arg1 & 0x00000f83) |
2408                      ((arg1 & 0x4) << 22);
2409         break;
2410     case 31:
2411         if (arg1 & 0x007c0000)
2412             return;
2413         env->active_fpu.fcr31 = arg1;
2414         break;
2415     default:
2416         return;
2417     }
2418     /* set rounding mode */
2419     restore_rounding_mode(env);
2420     /* set flush-to-zero mode */
2421     restore_flush_mode(env);
2422     set_float_exception_flags(0, &env->active_fpu.fp_status);
2423     if ((GET_FP_ENABLE(env->active_fpu.fcr31) | 0x20) & GET_FP_CAUSE(env->active_fpu.fcr31))
2424         do_raise_exception(env, EXCP_FPE, GETPC());
2425 }
2426
2427 static inline int ieee_ex_to_mips(int xcpt)
2428 {
2429     int ret = 0;
2430     if (xcpt) {
2431         if (xcpt & float_flag_invalid) {
2432             ret |= FP_INVALID;
2433         }
2434         if (xcpt & float_flag_overflow) {
2435             ret |= FP_OVERFLOW;
2436         }
2437         if (xcpt & float_flag_underflow) {
2438             ret |= FP_UNDERFLOW;
2439         }
2440         if (xcpt & float_flag_divbyzero) {
2441             ret |= FP_DIV0;
2442         }
2443         if (xcpt & float_flag_inexact) {
2444             ret |= FP_INEXACT;
2445         }
2446     }
2447     return ret;
2448 }
2449
2450 static inline void update_fcr31(CPUMIPSState *env, uintptr_t pc)
2451 {
2452     int tmp = ieee_ex_to_mips(get_float_exception_flags(&env->active_fpu.fp_status));
2453
2454     SET_FP_CAUSE(env->active_fpu.fcr31, tmp);
2455
2456     if (tmp) {
2457         set_float_exception_flags(0, &env->active_fpu.fp_status);
2458
2459         if (GET_FP_ENABLE(env->active_fpu.fcr31) & tmp) {
2460             do_raise_exception(env, EXCP_FPE, pc);
2461         } else {
2462             UPDATE_FP_FLAGS(env->active_fpu.fcr31, tmp);
2463         }
2464     }
2465 }
2466
2467 /* Float support.
2468    Single precition routines have a "s" suffix, double precision a
2469    "d" suffix, 32bit integer "w", 64bit integer "l", paired single "ps",
2470    paired single lower "pl", paired single upper "pu".  */
2471
2472 /* unary operations, modifying fp status  */
2473 uint64_t helper_float_sqrt_d(CPUMIPSState *env, uint64_t fdt0)
2474 {
2475     fdt0 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
2476     update_fcr31(env, GETPC());
2477     return fdt0;
2478 }
2479
2480 uint32_t helper_float_sqrt_s(CPUMIPSState *env, uint32_t fst0)
2481 {
2482     fst0 = float32_sqrt(fst0, &env->active_fpu.fp_status);
2483     update_fcr31(env, GETPC());
2484     return fst0;
2485 }
2486
2487 uint64_t helper_float_cvtd_s(CPUMIPSState *env, uint32_t fst0)
2488 {
2489     uint64_t fdt2;
2490
2491     fdt2 = float32_to_float64(fst0, &env->active_fpu.fp_status);
2492     update_fcr31(env, GETPC());
2493     return fdt2;
2494 }
2495
2496 uint64_t helper_float_cvtd_w(CPUMIPSState *env, uint32_t wt0)
2497 {
2498     uint64_t fdt2;
2499
2500     fdt2 = int32_to_float64(wt0, &env->active_fpu.fp_status);
2501     update_fcr31(env, GETPC());
2502     return fdt2;
2503 }
2504
2505 uint64_t helper_float_cvtd_l(CPUMIPSState *env, uint64_t dt0)
2506 {
2507     uint64_t fdt2;
2508
2509     fdt2 = int64_to_float64(dt0, &env->active_fpu.fp_status);
2510     update_fcr31(env, GETPC());
2511     return fdt2;
2512 }
2513
2514 uint64_t helper_float_cvtl_d(CPUMIPSState *env, uint64_t fdt0)
2515 {
2516     uint64_t dt2;
2517
2518     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2519     if (get_float_exception_flags(&env->active_fpu.fp_status)
2520         & (float_flag_invalid | float_flag_overflow)) {
2521         dt2 = FP_TO_INT64_OVERFLOW;
2522     }
2523     update_fcr31(env, GETPC());
2524     return dt2;
2525 }
2526
2527 uint64_t helper_float_cvtl_s(CPUMIPSState *env, uint32_t fst0)
2528 {
2529     uint64_t dt2;
2530
2531     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2532     if (get_float_exception_flags(&env->active_fpu.fp_status)
2533         & (float_flag_invalid | float_flag_overflow)) {
2534         dt2 = FP_TO_INT64_OVERFLOW;
2535     }
2536     update_fcr31(env, GETPC());
2537     return dt2;
2538 }
2539
2540 uint64_t helper_float_cvtps_pw(CPUMIPSState *env, uint64_t dt0)
2541 {
2542     uint32_t fst2;
2543     uint32_t fsth2;
2544
2545     fst2 = int32_to_float32(dt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2546     fsth2 = int32_to_float32(dt0 >> 32, &env->active_fpu.fp_status);
2547     update_fcr31(env, GETPC());
2548     return ((uint64_t)fsth2 << 32) | fst2;
2549 }
2550
2551 uint64_t helper_float_cvtpw_ps(CPUMIPSState *env, uint64_t fdt0)
2552 {
2553     uint32_t wt2;
2554     uint32_t wth2;
2555     int excp, excph;
2556
2557     wt2 = float32_to_int32(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
2558     excp = get_float_exception_flags(&env->active_fpu.fp_status);
2559     if (excp & (float_flag_overflow | float_flag_invalid)) {
2560         wt2 = FP_TO_INT32_OVERFLOW;
2561     }
2562
2563     set_float_exception_flags(0, &env->active_fpu.fp_status);
2564     wth2 = float32_to_int32(fdt0 >> 32, &env->active_fpu.fp_status);
2565     excph = get_float_exception_flags(&env->active_fpu.fp_status);
2566     if (excph & (float_flag_overflow | float_flag_invalid)) {
2567         wth2 = FP_TO_INT32_OVERFLOW;
2568     }
2569
2570     set_float_exception_flags(excp | excph, &env->active_fpu.fp_status);
2571     update_fcr31(env, GETPC());
2572
2573     return ((uint64_t)wth2 << 32) | wt2;
2574 }
2575
2576 uint32_t helper_float_cvts_d(CPUMIPSState *env, uint64_t fdt0)
2577 {
2578     uint32_t fst2;
2579
2580     fst2 = float64_to_float32(fdt0, &env->active_fpu.fp_status);
2581     update_fcr31(env, GETPC());
2582     return fst2;
2583 }
2584
2585 uint32_t helper_float_cvts_w(CPUMIPSState *env, uint32_t wt0)
2586 {
2587     uint32_t fst2;
2588
2589     fst2 = int32_to_float32(wt0, &env->active_fpu.fp_status);
2590     update_fcr31(env, GETPC());
2591     return fst2;
2592 }
2593
2594 uint32_t helper_float_cvts_l(CPUMIPSState *env, uint64_t dt0)
2595 {
2596     uint32_t fst2;
2597
2598     fst2 = int64_to_float32(dt0, &env->active_fpu.fp_status);
2599     update_fcr31(env, GETPC());
2600     return fst2;
2601 }
2602
2603 uint32_t helper_float_cvts_pl(CPUMIPSState *env, uint32_t wt0)
2604 {
2605     uint32_t wt2;
2606
2607     wt2 = wt0;
2608     update_fcr31(env, GETPC());
2609     return wt2;
2610 }
2611
2612 uint32_t helper_float_cvts_pu(CPUMIPSState *env, uint32_t wth0)
2613 {
2614     uint32_t wt2;
2615
2616     wt2 = wth0;
2617     update_fcr31(env, GETPC());
2618     return wt2;
2619 }
2620
2621 uint32_t helper_float_cvtw_s(CPUMIPSState *env, uint32_t fst0)
2622 {
2623     uint32_t wt2;
2624
2625     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2626     update_fcr31(env, GETPC());
2627     if (get_float_exception_flags(&env->active_fpu.fp_status)
2628         & (float_flag_invalid | float_flag_overflow)) {
2629         wt2 = FP_TO_INT32_OVERFLOW;
2630     }
2631     return wt2;
2632 }
2633
2634 uint32_t helper_float_cvtw_d(CPUMIPSState *env, uint64_t fdt0)
2635 {
2636     uint32_t wt2;
2637
2638     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2639     if (get_float_exception_flags(&env->active_fpu.fp_status)
2640         & (float_flag_invalid | float_flag_overflow)) {
2641         wt2 = FP_TO_INT32_OVERFLOW;
2642     }
2643     update_fcr31(env, GETPC());
2644     return wt2;
2645 }
2646
2647 uint64_t helper_float_roundl_d(CPUMIPSState *env, uint64_t fdt0)
2648 {
2649     uint64_t dt2;
2650
2651     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2652     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2653     restore_rounding_mode(env);
2654     if (get_float_exception_flags(&env->active_fpu.fp_status)
2655         & (float_flag_invalid | float_flag_overflow)) {
2656         dt2 = FP_TO_INT64_OVERFLOW;
2657     }
2658     update_fcr31(env, GETPC());
2659     return dt2;
2660 }
2661
2662 uint64_t helper_float_roundl_s(CPUMIPSState *env, uint32_t fst0)
2663 {
2664     uint64_t dt2;
2665
2666     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2667     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2668     restore_rounding_mode(env);
2669     if (get_float_exception_flags(&env->active_fpu.fp_status)
2670         & (float_flag_invalid | float_flag_overflow)) {
2671         dt2 = FP_TO_INT64_OVERFLOW;
2672     }
2673     update_fcr31(env, GETPC());
2674     return dt2;
2675 }
2676
2677 uint32_t helper_float_roundw_d(CPUMIPSState *env, uint64_t fdt0)
2678 {
2679     uint32_t wt2;
2680
2681     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2682     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2683     restore_rounding_mode(env);
2684     if (get_float_exception_flags(&env->active_fpu.fp_status)
2685         & (float_flag_invalid | float_flag_overflow)) {
2686         wt2 = FP_TO_INT32_OVERFLOW;
2687     }
2688     update_fcr31(env, GETPC());
2689     return wt2;
2690 }
2691
2692 uint32_t helper_float_roundw_s(CPUMIPSState *env, uint32_t fst0)
2693 {
2694     uint32_t wt2;
2695
2696     set_float_rounding_mode(float_round_nearest_even, &env->active_fpu.fp_status);
2697     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2698     restore_rounding_mode(env);
2699     if (get_float_exception_flags(&env->active_fpu.fp_status)
2700         & (float_flag_invalid | float_flag_overflow)) {
2701         wt2 = FP_TO_INT32_OVERFLOW;
2702     }
2703     update_fcr31(env, GETPC());
2704     return wt2;
2705 }
2706
2707 uint64_t helper_float_truncl_d(CPUMIPSState *env, uint64_t fdt0)
2708 {
2709     uint64_t dt2;
2710
2711     dt2 = float64_to_int64_round_to_zero(fdt0, &env->active_fpu.fp_status);
2712     if (get_float_exception_flags(&env->active_fpu.fp_status)
2713         & (float_flag_invalid | float_flag_overflow)) {
2714         dt2 = FP_TO_INT64_OVERFLOW;
2715     }
2716     update_fcr31(env, GETPC());
2717     return dt2;
2718 }
2719
2720 uint64_t helper_float_truncl_s(CPUMIPSState *env, uint32_t fst0)
2721 {
2722     uint64_t dt2;
2723
2724     dt2 = float32_to_int64_round_to_zero(fst0, &env->active_fpu.fp_status);
2725     if (get_float_exception_flags(&env->active_fpu.fp_status)
2726         & (float_flag_invalid | float_flag_overflow)) {
2727         dt2 = FP_TO_INT64_OVERFLOW;
2728     }
2729     update_fcr31(env, GETPC());
2730     return dt2;
2731 }
2732
2733 uint32_t helper_float_truncw_d(CPUMIPSState *env, uint64_t fdt0)
2734 {
2735     uint32_t wt2;
2736
2737     wt2 = float64_to_int32_round_to_zero(fdt0, &env->active_fpu.fp_status);
2738     if (get_float_exception_flags(&env->active_fpu.fp_status)
2739         & (float_flag_invalid | float_flag_overflow)) {
2740         wt2 = FP_TO_INT32_OVERFLOW;
2741     }
2742     update_fcr31(env, GETPC());
2743     return wt2;
2744 }
2745
2746 uint32_t helper_float_truncw_s(CPUMIPSState *env, uint32_t fst0)
2747 {
2748     uint32_t wt2;
2749
2750     wt2 = float32_to_int32_round_to_zero(fst0, &env->active_fpu.fp_status);
2751     if (get_float_exception_flags(&env->active_fpu.fp_status)
2752         & (float_flag_invalid | float_flag_overflow)) {
2753         wt2 = FP_TO_INT32_OVERFLOW;
2754     }
2755     update_fcr31(env, GETPC());
2756     return wt2;
2757 }
2758
2759 uint64_t helper_float_ceill_d(CPUMIPSState *env, uint64_t fdt0)
2760 {
2761     uint64_t dt2;
2762
2763     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2764     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2765     restore_rounding_mode(env);
2766     if (get_float_exception_flags(&env->active_fpu.fp_status)
2767         & (float_flag_invalid | float_flag_overflow)) {
2768         dt2 = FP_TO_INT64_OVERFLOW;
2769     }
2770     update_fcr31(env, GETPC());
2771     return dt2;
2772 }
2773
2774 uint64_t helper_float_ceill_s(CPUMIPSState *env, uint32_t fst0)
2775 {
2776     uint64_t dt2;
2777
2778     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2779     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2780     restore_rounding_mode(env);
2781     if (get_float_exception_flags(&env->active_fpu.fp_status)
2782         & (float_flag_invalid | float_flag_overflow)) {
2783         dt2 = FP_TO_INT64_OVERFLOW;
2784     }
2785     update_fcr31(env, GETPC());
2786     return dt2;
2787 }
2788
2789 uint32_t helper_float_ceilw_d(CPUMIPSState *env, uint64_t fdt0)
2790 {
2791     uint32_t wt2;
2792
2793     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2794     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2795     restore_rounding_mode(env);
2796     if (get_float_exception_flags(&env->active_fpu.fp_status)
2797         & (float_flag_invalid | float_flag_overflow)) {
2798         wt2 = FP_TO_INT32_OVERFLOW;
2799     }
2800     update_fcr31(env, GETPC());
2801     return wt2;
2802 }
2803
2804 uint32_t helper_float_ceilw_s(CPUMIPSState *env, uint32_t fst0)
2805 {
2806     uint32_t wt2;
2807
2808     set_float_rounding_mode(float_round_up, &env->active_fpu.fp_status);
2809     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2810     restore_rounding_mode(env);
2811     if (get_float_exception_flags(&env->active_fpu.fp_status)
2812         & (float_flag_invalid | float_flag_overflow)) {
2813         wt2 = FP_TO_INT32_OVERFLOW;
2814     }
2815     update_fcr31(env, GETPC());
2816     return wt2;
2817 }
2818
2819 uint64_t helper_float_floorl_d(CPUMIPSState *env, uint64_t fdt0)
2820 {
2821     uint64_t dt2;
2822
2823     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2824     dt2 = float64_to_int64(fdt0, &env->active_fpu.fp_status);
2825     restore_rounding_mode(env);
2826     if (get_float_exception_flags(&env->active_fpu.fp_status)
2827         & (float_flag_invalid | float_flag_overflow)) {
2828         dt2 = FP_TO_INT64_OVERFLOW;
2829     }
2830     update_fcr31(env, GETPC());
2831     return dt2;
2832 }
2833
2834 uint64_t helper_float_floorl_s(CPUMIPSState *env, uint32_t fst0)
2835 {
2836     uint64_t dt2;
2837
2838     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2839     dt2 = float32_to_int64(fst0, &env->active_fpu.fp_status);
2840     restore_rounding_mode(env);
2841     if (get_float_exception_flags(&env->active_fpu.fp_status)
2842         & (float_flag_invalid | float_flag_overflow)) {
2843         dt2 = FP_TO_INT64_OVERFLOW;
2844     }
2845     update_fcr31(env, GETPC());
2846     return dt2;
2847 }
2848
2849 uint32_t helper_float_floorw_d(CPUMIPSState *env, uint64_t fdt0)
2850 {
2851     uint32_t wt2;
2852
2853     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2854     wt2 = float64_to_int32(fdt0, &env->active_fpu.fp_status);
2855     restore_rounding_mode(env);
2856     if (get_float_exception_flags(&env->active_fpu.fp_status)
2857         & (float_flag_invalid | float_flag_overflow)) {
2858         wt2 = FP_TO_INT32_OVERFLOW;
2859     }
2860     update_fcr31(env, GETPC());
2861     return wt2;
2862 }
2863
2864 uint32_t helper_float_floorw_s(CPUMIPSState *env, uint32_t fst0)
2865 {
2866     uint32_t wt2;
2867
2868     set_float_rounding_mode(float_round_down, &env->active_fpu.fp_status);
2869     wt2 = float32_to_int32(fst0, &env->active_fpu.fp_status);
2870     restore_rounding_mode(env);
2871     if (get_float_exception_flags(&env->active_fpu.fp_status)
2872         & (float_flag_invalid | float_flag_overflow)) {
2873         wt2 = FP_TO_INT32_OVERFLOW;
2874     }
2875     update_fcr31(env, GETPC());
2876     return wt2;
2877 }
2878
2879 /* unary operations, not modifying fp status  */
2880 #define FLOAT_UNOP(name)                                       \
2881 uint64_t helper_float_ ## name ## _d(uint64_t fdt0)                \
2882 {                                                              \
2883     return float64_ ## name(fdt0);                             \
2884 }                                                              \
2885 uint32_t helper_float_ ## name ## _s(uint32_t fst0)                \
2886 {                                                              \
2887     return float32_ ## name(fst0);                             \
2888 }                                                              \
2889 uint64_t helper_float_ ## name ## _ps(uint64_t fdt0)               \
2890 {                                                              \
2891     uint32_t wt0;                                              \
2892     uint32_t wth0;                                             \
2893                                                                \
2894     wt0 = float32_ ## name(fdt0 & 0XFFFFFFFF);                 \
2895     wth0 = float32_ ## name(fdt0 >> 32);                       \
2896     return ((uint64_t)wth0 << 32) | wt0;                       \
2897 }
2898 FLOAT_UNOP(abs)
2899 FLOAT_UNOP(chs)
2900 #undef FLOAT_UNOP
2901
2902 #define FLOAT_FMADDSUB(name, bits, muladd_arg)                          \
2903 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,            \
2904                                           uint ## bits ## _t fs,        \
2905                                           uint ## bits ## _t ft,        \
2906                                           uint ## bits ## _t fd)        \
2907 {                                                                       \
2908     uint ## bits ## _t fdret;                                           \
2909                                                                         \
2910     fdret = float ## bits ## _muladd(fs, ft, fd, muladd_arg,            \
2911                                      &env->active_fpu.fp_status);       \
2912     update_fcr31(env, GETPC());                                         \
2913     return fdret;                                                       \
2914 }
2915
2916 FLOAT_FMADDSUB(maddf_s, 32, 0)
2917 FLOAT_FMADDSUB(maddf_d, 64, 0)
2918 FLOAT_FMADDSUB(msubf_s, 32, float_muladd_negate_product)
2919 FLOAT_FMADDSUB(msubf_d, 64, float_muladd_negate_product)
2920 #undef FLOAT_FMADDSUB
2921
2922 #define FLOAT_MINMAX(name, bits, minmaxfunc)                            \
2923 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,            \
2924                                           uint ## bits ## _t fs,        \
2925                                           uint ## bits ## _t ft)        \
2926 {                                                                       \
2927     uint ## bits ## _t fdret;                                           \
2928                                                                         \
2929     fdret = float ## bits ## _ ## minmaxfunc(fs, ft,                    \
2930                                            &env->active_fpu.fp_status); \
2931     update_fcr31(env, GETPC());                                         \
2932     return fdret;                                                       \
2933 }
2934
2935 FLOAT_MINMAX(max_s, 32, maxnum)
2936 FLOAT_MINMAX(max_d, 64, maxnum)
2937 FLOAT_MINMAX(maxa_s, 32, maxnummag)
2938 FLOAT_MINMAX(maxa_d, 64, maxnummag)
2939
2940 FLOAT_MINMAX(min_s, 32, minnum)
2941 FLOAT_MINMAX(min_d, 64, minnum)
2942 FLOAT_MINMAX(mina_s, 32, minnummag)
2943 FLOAT_MINMAX(mina_d, 64, minnummag)
2944 #undef FLOAT_MINMAX
2945
2946 #define FLOAT_RINT(name, bits)                                              \
2947 uint ## bits ## _t helper_float_ ## name (CPUMIPSState *env,                \
2948                                           uint ## bits ## _t fs)            \
2949 {                                                                           \
2950     uint ## bits ## _t fdret;                                               \
2951                                                                             \
2952     fdret = float ## bits ## _round_to_int(fs, &env->active_fpu.fp_status); \
2953     update_fcr31(env, GETPC());                                             \
2954     return fdret;                                                           \
2955 }
2956
2957 FLOAT_RINT(rint_s, 32)
2958 FLOAT_RINT(rint_d, 64)
2959 #undef FLOAT_RINT
2960
2961 #define FLOAT_CLASS_SIGNALING_NAN      0x001
2962 #define FLOAT_CLASS_QUIET_NAN          0x002
2963 #define FLOAT_CLASS_NEGATIVE_INFINITY  0x004
2964 #define FLOAT_CLASS_NEGATIVE_NORMAL    0x008
2965 #define FLOAT_CLASS_NEGATIVE_SUBNORMAL 0x010
2966 #define FLOAT_CLASS_NEGATIVE_ZERO      0x020
2967 #define FLOAT_CLASS_POSITIVE_INFINITY  0x040
2968 #define FLOAT_CLASS_POSITIVE_NORMAL    0x080
2969 #define FLOAT_CLASS_POSITIVE_SUBNORMAL 0x100
2970 #define FLOAT_CLASS_POSITIVE_ZERO      0x200
2971
2972 #define FLOAT_CLASS(name, bits)                                      \
2973 uint ## bits ## _t helper_float_ ## name (uint ## bits ## _t arg)    \
2974 {                                                                    \
2975     if (float ## bits ## _is_signaling_nan(arg)) {                   \
2976         return FLOAT_CLASS_SIGNALING_NAN;                            \
2977     } else if (float ## bits ## _is_quiet_nan(arg)) {                \
2978         return FLOAT_CLASS_QUIET_NAN;                                \
2979     } else if (float ## bits ## _is_neg(arg)) {                      \
2980         if (float ## bits ## _is_infinity(arg)) {                    \
2981             return FLOAT_CLASS_NEGATIVE_INFINITY;                    \
2982         } else if (float ## bits ## _is_zero(arg)) {                 \
2983             return FLOAT_CLASS_NEGATIVE_ZERO;                        \
2984         } else if (float ## bits ## _is_zero_or_denormal(arg)) {     \
2985             return FLOAT_CLASS_NEGATIVE_SUBNORMAL;                   \
2986         } else {                                                     \
2987             return FLOAT_CLASS_NEGATIVE_NORMAL;                      \
2988         }                                                            \
2989     } else {                                                         \
2990         if (float ## bits ## _is_infinity(arg)) {                    \
2991             return FLOAT_CLASS_POSITIVE_INFINITY;                    \
2992         } else if (float ## bits ## _is_zero(arg)) {                 \
2993             return FLOAT_CLASS_POSITIVE_ZERO;                        \
2994         } else if (float ## bits ## _is_zero_or_denormal(arg)) {     \
2995             return FLOAT_CLASS_POSITIVE_SUBNORMAL;                   \
2996         } else {                                                     \
2997             return FLOAT_CLASS_POSITIVE_NORMAL;                      \
2998         }                                                            \
2999     }                                                                \
3000 }
3001
3002 FLOAT_CLASS(class_s, 32)
3003 FLOAT_CLASS(class_d, 64)
3004 #undef FLOAT_CLASS
3005
3006 /* MIPS specific unary operations */
3007 uint64_t helper_float_recip_d(CPUMIPSState *env, uint64_t fdt0)
3008 {
3009     uint64_t fdt2;
3010
3011     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3012     update_fcr31(env, GETPC());
3013     return fdt2;
3014 }
3015
3016 uint32_t helper_float_recip_s(CPUMIPSState *env, uint32_t fst0)
3017 {
3018     uint32_t fst2;
3019
3020     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3021     update_fcr31(env, GETPC());
3022     return fst2;
3023 }
3024
3025 uint64_t helper_float_rsqrt_d(CPUMIPSState *env, uint64_t fdt0)
3026 {
3027     uint64_t fdt2;
3028
3029     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3030     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3031     update_fcr31(env, GETPC());
3032     return fdt2;
3033 }
3034
3035 uint32_t helper_float_rsqrt_s(CPUMIPSState *env, uint32_t fst0)
3036 {
3037     uint32_t fst2;
3038
3039     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3040     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3041     update_fcr31(env, GETPC());
3042     return fst2;
3043 }
3044
3045 uint64_t helper_float_recip1_d(CPUMIPSState *env, uint64_t fdt0)
3046 {
3047     uint64_t fdt2;
3048
3049     fdt2 = float64_div(float64_one, fdt0, &env->active_fpu.fp_status);
3050     update_fcr31(env, GETPC());
3051     return fdt2;
3052 }
3053
3054 uint32_t helper_float_recip1_s(CPUMIPSState *env, uint32_t fst0)
3055 {
3056     uint32_t fst2;
3057
3058     fst2 = float32_div(float32_one, fst0, &env->active_fpu.fp_status);
3059     update_fcr31(env, GETPC());
3060     return fst2;
3061 }
3062
3063 uint64_t helper_float_recip1_ps(CPUMIPSState *env, uint64_t fdt0)
3064 {
3065     uint32_t fst2;
3066     uint32_t fsth2;
3067
3068     fst2 = float32_div(float32_one, fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3069     fsth2 = float32_div(float32_one, fdt0 >> 32, &env->active_fpu.fp_status);
3070     update_fcr31(env, GETPC());
3071     return ((uint64_t)fsth2 << 32) | fst2;
3072 }
3073
3074 uint64_t helper_float_rsqrt1_d(CPUMIPSState *env, uint64_t fdt0)
3075 {
3076     uint64_t fdt2;
3077
3078     fdt2 = float64_sqrt(fdt0, &env->active_fpu.fp_status);
3079     fdt2 = float64_div(float64_one, fdt2, &env->active_fpu.fp_status);
3080     update_fcr31(env, GETPC());
3081     return fdt2;
3082 }
3083
3084 uint32_t helper_float_rsqrt1_s(CPUMIPSState *env, uint32_t fst0)
3085 {
3086     uint32_t fst2;
3087
3088     fst2 = float32_sqrt(fst0, &env->active_fpu.fp_status);
3089     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3090     update_fcr31(env, GETPC());
3091     return fst2;
3092 }
3093
3094 uint64_t helper_float_rsqrt1_ps(CPUMIPSState *env, uint64_t fdt0)
3095 {
3096     uint32_t fst2;
3097     uint32_t fsth2;
3098
3099     fst2 = float32_sqrt(fdt0 & 0XFFFFFFFF, &env->active_fpu.fp_status);
3100     fsth2 = float32_sqrt(fdt0 >> 32, &env->active_fpu.fp_status);
3101     fst2 = float32_div(float32_one, fst2, &env->active_fpu.fp_status);
3102     fsth2 = float32_div(float32_one, fsth2, &env->active_fpu.fp_status);
3103     update_fcr31(env, GETPC());
3104     return ((uint64_t)fsth2 << 32) | fst2;
3105 }
3106
3107 #define FLOAT_OP(name, p) void helper_float_##name##_##p(CPUMIPSState *env)
3108
3109 /* binary operations */
3110 #define FLOAT_BINOP(name)                                          \
3111 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,            \
3112                                      uint64_t fdt0, uint64_t fdt1) \
3113 {                                                                  \
3114     uint64_t dt2;                                                  \
3115                                                                    \
3116     dt2 = float64_ ## name (fdt0, fdt1, &env->active_fpu.fp_status);     \
3117     update_fcr31(env, GETPC());                                    \
3118     return dt2;                                                    \
3119 }                                                                  \
3120                                                                    \
3121 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,            \
3122                                      uint32_t fst0, uint32_t fst1) \
3123 {                                                                  \
3124     uint32_t wt2;                                                  \
3125                                                                    \
3126     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
3127     update_fcr31(env, GETPC());                                    \
3128     return wt2;                                                    \
3129 }                                                                  \
3130                                                                    \
3131 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,           \
3132                                       uint64_t fdt0,               \
3133                                       uint64_t fdt1)               \
3134 {                                                                  \
3135     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                             \
3136     uint32_t fsth0 = fdt0 >> 32;                                   \
3137     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                             \
3138     uint32_t fsth1 = fdt1 >> 32;                                   \
3139     uint32_t wt2;                                                  \
3140     uint32_t wth2;                                                 \
3141                                                                    \
3142     wt2 = float32_ ## name (fst0, fst1, &env->active_fpu.fp_status);     \
3143     wth2 = float32_ ## name (fsth0, fsth1, &env->active_fpu.fp_status);  \
3144     update_fcr31(env, GETPC());                                    \
3145     return ((uint64_t)wth2 << 32) | wt2;                           \
3146 }
3147
3148 FLOAT_BINOP(add)
3149 FLOAT_BINOP(sub)
3150 FLOAT_BINOP(mul)
3151 FLOAT_BINOP(div)
3152 #undef FLOAT_BINOP
3153
3154 #define UNFUSED_FMA(prefix, a, b, c, flags)                          \
3155 {                                                                    \
3156     a = prefix##_mul(a, b, &env->active_fpu.fp_status);              \
3157     if ((flags) & float_muladd_negate_c) {                           \
3158         a = prefix##_sub(a, c, &env->active_fpu.fp_status);          \
3159     } else {                                                         \
3160         a = prefix##_add(a, c, &env->active_fpu.fp_status);          \
3161     }                                                                \
3162     if ((flags) & float_muladd_negate_result) {                      \
3163         a = prefix##_chs(a);                                         \
3164     }                                                                \
3165 }
3166
3167 /* FMA based operations */
3168 #define FLOAT_FMA(name, type)                                        \
3169 uint64_t helper_float_ ## name ## _d(CPUMIPSState *env,              \
3170                                      uint64_t fdt0, uint64_t fdt1,   \
3171                                      uint64_t fdt2)                  \
3172 {                                                                    \
3173     UNFUSED_FMA(float64, fdt0, fdt1, fdt2, type);                    \
3174     update_fcr31(env, GETPC());                                      \
3175     return fdt0;                                                     \
3176 }                                                                    \
3177                                                                      \
3178 uint32_t helper_float_ ## name ## _s(CPUMIPSState *env,              \
3179                                      uint32_t fst0, uint32_t fst1,   \
3180                                      uint32_t fst2)                  \
3181 {                                                                    \
3182     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
3183     update_fcr31(env, GETPC());                                      \
3184     return fst0;                                                     \
3185 }                                                                    \
3186                                                                      \
3187 uint64_t helper_float_ ## name ## _ps(CPUMIPSState *env,             \
3188                                       uint64_t fdt0, uint64_t fdt1,  \
3189                                       uint64_t fdt2)                 \
3190 {                                                                    \
3191     uint32_t fst0 = fdt0 & 0XFFFFFFFF;                               \
3192     uint32_t fsth0 = fdt0 >> 32;                                     \
3193     uint32_t fst1 = fdt1 & 0XFFFFFFFF;                               \
3194     uint32_t fsth1 = fdt1 >> 32;                                     \
3195     uint32_t fst2 = fdt2 & 0XFFFFFFFF;                               \
3196     uint32_t fsth2 = fdt2 >> 32;                                     \
3197                                                                      \
3198     UNFUSED_FMA(float32, fst0, fst1, fst2, type);                    \
3199     UNFUSED_FMA(float32, fsth0, fsth1, fsth2, type);                 \
3200     update_fcr31(env, GETPC());                                      \
3201     return ((uint64_t)fsth0 << 32) | fst0;                           \
3202 }
3203 FLOAT_FMA(madd, 0)
3204 FLOAT_FMA(msub, float_muladd_negate_c)
3205 FLOAT_FMA(nmadd, float_muladd_negate_result)
3206 FLOAT_FMA(nmsub, float_muladd_negate_result | float_muladd_negate_c)
3207 #undef FLOAT_FMA
3208
3209 /* MIPS specific binary operations */
3210 uint64_t helper_float_recip2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3211 {
3212     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3213     fdt2 = float64_chs(float64_sub(fdt2, float64_one, &env->active_fpu.fp_status));
3214     update_fcr31(env, GETPC());
3215     return fdt2;
3216 }
3217
3218 uint32_t helper_float_recip2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3219 {
3220     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3221     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3222     update_fcr31(env, GETPC());
3223     return fst2;
3224 }
3225
3226 uint64_t helper_float_recip2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3227 {
3228     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3229     uint32_t fsth0 = fdt0 >> 32;
3230     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3231     uint32_t fsth2 = fdt2 >> 32;
3232
3233     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3234     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3235     fst2 = float32_chs(float32_sub(fst2, float32_one, &env->active_fpu.fp_status));
3236     fsth2 = float32_chs(float32_sub(fsth2, float32_one, &env->active_fpu.fp_status));
3237     update_fcr31(env, GETPC());
3238     return ((uint64_t)fsth2 << 32) | fst2;
3239 }
3240
3241 uint64_t helper_float_rsqrt2_d(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3242 {
3243     fdt2 = float64_mul(fdt0, fdt2, &env->active_fpu.fp_status);
3244     fdt2 = float64_sub(fdt2, float64_one, &env->active_fpu.fp_status);
3245     fdt2 = float64_chs(float64_div(fdt2, FLOAT_TWO64, &env->active_fpu.fp_status));
3246     update_fcr31(env, GETPC());
3247     return fdt2;
3248 }
3249
3250 uint32_t helper_float_rsqrt2_s(CPUMIPSState *env, uint32_t fst0, uint32_t fst2)
3251 {
3252     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3253     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3254     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3255     update_fcr31(env, GETPC());
3256     return fst2;
3257 }
3258
3259 uint64_t helper_float_rsqrt2_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt2)
3260 {
3261     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3262     uint32_t fsth0 = fdt0 >> 32;
3263     uint32_t fst2 = fdt2 & 0XFFFFFFFF;
3264     uint32_t fsth2 = fdt2 >> 32;
3265
3266     fst2 = float32_mul(fst0, fst2, &env->active_fpu.fp_status);
3267     fsth2 = float32_mul(fsth0, fsth2, &env->active_fpu.fp_status);
3268     fst2 = float32_sub(fst2, float32_one, &env->active_fpu.fp_status);
3269     fsth2 = float32_sub(fsth2, float32_one, &env->active_fpu.fp_status);
3270     fst2 = float32_chs(float32_div(fst2, FLOAT_TWO32, &env->active_fpu.fp_status));
3271     fsth2 = float32_chs(float32_div(fsth2, FLOAT_TWO32, &env->active_fpu.fp_status));
3272     update_fcr31(env, GETPC());
3273     return ((uint64_t)fsth2 << 32) | fst2;
3274 }
3275
3276 uint64_t helper_float_addr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3277 {
3278     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3279     uint32_t fsth0 = fdt0 >> 32;
3280     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3281     uint32_t fsth1 = fdt1 >> 32;
3282     uint32_t fst2;
3283     uint32_t fsth2;
3284
3285     fst2 = float32_add (fst0, fsth0, &env->active_fpu.fp_status);
3286     fsth2 = float32_add (fst1, fsth1, &env->active_fpu.fp_status);
3287     update_fcr31(env, GETPC());
3288     return ((uint64_t)fsth2 << 32) | fst2;
3289 }
3290
3291 uint64_t helper_float_mulr_ps(CPUMIPSState *env, uint64_t fdt0, uint64_t fdt1)
3292 {
3293     uint32_t fst0 = fdt0 & 0XFFFFFFFF;
3294     uint32_t fsth0 = fdt0 >> 32;
3295     uint32_t fst1 = fdt1 & 0XFFFFFFFF;
3296     uint32_t fsth1 = fdt1 >> 32;
3297     uint32_t fst2;
3298     uint32_t fsth2;
3299
3300     fst2 = float32_mul (fst0, fsth0, &env->active_fpu.fp_status);
3301     fsth2 = float32_mul (fst1, fsth1, &env->active_fpu.fp_status);
3302     update_fcr31(env, GETPC());
3303     return ((uint64_t)fsth2 << 32) | fst2;
3304 }
3305
3306 /* compare operations */
3307 #define FOP_COND_D(op, cond)                                   \
3308 void helper_cmp_d_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3309                          uint64_t fdt1, int cc)                \
3310 {                                                              \
3311     int c;                                                     \
3312     c = cond;                                                  \
3313     update_fcr31(env, GETPC());                                \
3314     if (c)                                                     \
3315         SET_FP_COND(cc, env->active_fpu);                      \
3316     else                                                       \
3317         CLEAR_FP_COND(cc, env->active_fpu);                    \
3318 }                                                              \
3319 void helper_cmpabs_d_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3320                             uint64_t fdt1, int cc)             \
3321 {                                                              \
3322     int c;                                                     \
3323     fdt0 = float64_abs(fdt0);                                  \
3324     fdt1 = float64_abs(fdt1);                                  \
3325     c = cond;                                                  \
3326     update_fcr31(env, GETPC());                                \
3327     if (c)                                                     \
3328         SET_FP_COND(cc, env->active_fpu);                      \
3329     else                                                       \
3330         CLEAR_FP_COND(cc, env->active_fpu);                    \
3331 }
3332
3333 /* NOTE: the comma operator will make "cond" to eval to false,
3334  * but float64_unordered_quiet() is still called. */
3335 FOP_COND_D(f,   (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3336 FOP_COND_D(un,  float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status))
3337 FOP_COND_D(eq,  float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3338 FOP_COND_D(ueq, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3339 FOP_COND_D(olt, float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3340 FOP_COND_D(ult, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3341 FOP_COND_D(ole, float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3342 FOP_COND_D(ule, float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status))
3343 /* NOTE: the comma operator will make "cond" to eval to false,
3344  * but float64_unordered() is still called. */
3345 FOP_COND_D(sf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3346 FOP_COND_D(ngle,float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status))
3347 FOP_COND_D(seq, float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3348 FOP_COND_D(ngl, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status))
3349 FOP_COND_D(lt,  float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3350 FOP_COND_D(nge, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status))
3351 FOP_COND_D(le,  float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3352 FOP_COND_D(ngt, float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)  || float64_le(fdt0, fdt1, &env->active_fpu.fp_status))
3353
3354 #define FOP_COND_S(op, cond)                                   \
3355 void helper_cmp_s_ ## op(CPUMIPSState *env, uint32_t fst0,     \
3356                          uint32_t fst1, int cc)                \
3357 {                                                              \
3358     int c;                                                     \
3359     c = cond;                                                  \
3360     update_fcr31(env, GETPC());                                \
3361     if (c)                                                     \
3362         SET_FP_COND(cc, env->active_fpu);                      \
3363     else                                                       \
3364         CLEAR_FP_COND(cc, env->active_fpu);                    \
3365 }                                                              \
3366 void helper_cmpabs_s_ ## op(CPUMIPSState *env, uint32_t fst0,  \
3367                             uint32_t fst1, int cc)             \
3368 {                                                              \
3369     int c;                                                     \
3370     fst0 = float32_abs(fst0);                                  \
3371     fst1 = float32_abs(fst1);                                  \
3372     c = cond;                                                  \
3373     update_fcr31(env, GETPC());                                \
3374     if (c)                                                     \
3375         SET_FP_COND(cc, env->active_fpu);                      \
3376     else                                                       \
3377         CLEAR_FP_COND(cc, env->active_fpu);                    \
3378 }
3379
3380 /* NOTE: the comma operator will make "cond" to eval to false,
3381  * but float32_unordered_quiet() is still called. */
3382 FOP_COND_S(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3383 FOP_COND_S(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status))
3384 FOP_COND_S(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3385 FOP_COND_S(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status))
3386 FOP_COND_S(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3387 FOP_COND_S(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status))
3388 FOP_COND_S(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3389 FOP_COND_S(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)  || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status))
3390 /* NOTE: the comma operator will make "cond" to eval to false,
3391  * but float32_unordered() is still called. */
3392 FOP_COND_S(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3393 FOP_COND_S(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status))
3394 FOP_COND_S(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3395 FOP_COND_S(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_eq(fst0, fst1, &env->active_fpu.fp_status))
3396 FOP_COND_S(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3397 FOP_COND_S(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_lt(fst0, fst1, &env->active_fpu.fp_status))
3398 FOP_COND_S(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status))
3399 FOP_COND_S(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)  || float32_le(fst0, fst1, &env->active_fpu.fp_status))
3400
3401 #define FOP_COND_PS(op, condl, condh)                           \
3402 void helper_cmp_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,     \
3403                           uint64_t fdt1, int cc)                \
3404 {                                                               \
3405     uint32_t fst0, fsth0, fst1, fsth1;                          \
3406     int ch, cl;                                                 \
3407     fst0 = fdt0 & 0XFFFFFFFF;                                   \
3408     fsth0 = fdt0 >> 32;                                         \
3409     fst1 = fdt1 & 0XFFFFFFFF;                                   \
3410     fsth1 = fdt1 >> 32;                                         \
3411     cl = condl;                                                 \
3412     ch = condh;                                                 \
3413     update_fcr31(env, GETPC());                                 \
3414     if (cl)                                                     \
3415         SET_FP_COND(cc, env->active_fpu);                       \
3416     else                                                        \
3417         CLEAR_FP_COND(cc, env->active_fpu);                     \
3418     if (ch)                                                     \
3419         SET_FP_COND(cc + 1, env->active_fpu);                   \
3420     else                                                        \
3421         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3422 }                                                               \
3423 void helper_cmpabs_ps_ ## op(CPUMIPSState *env, uint64_t fdt0,  \
3424                              uint64_t fdt1, int cc)             \
3425 {                                                               \
3426     uint32_t fst0, fsth0, fst1, fsth1;                          \
3427     int ch, cl;                                                 \
3428     fst0 = float32_abs(fdt0 & 0XFFFFFFFF);                      \
3429     fsth0 = float32_abs(fdt0 >> 32);                            \
3430     fst1 = float32_abs(fdt1 & 0XFFFFFFFF);                      \
3431     fsth1 = float32_abs(fdt1 >> 32);                            \
3432     cl = condl;                                                 \
3433     ch = condh;                                                 \
3434     update_fcr31(env, GETPC());                                 \
3435     if (cl)                                                     \
3436         SET_FP_COND(cc, env->active_fpu);                       \
3437     else                                                        \
3438         CLEAR_FP_COND(cc, env->active_fpu);                     \
3439     if (ch)                                                     \
3440         SET_FP_COND(cc + 1, env->active_fpu);                   \
3441     else                                                        \
3442         CLEAR_FP_COND(cc + 1, env->active_fpu);                 \
3443 }
3444
3445 /* NOTE: the comma operator will make "cond" to eval to false,
3446  * but float32_unordered_quiet() is still called. */
3447 FOP_COND_PS(f,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0),
3448                  (float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3449 FOP_COND_PS(un,  float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status),
3450                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status))
3451 FOP_COND_PS(eq,  float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3452                  float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3453 FOP_COND_PS(ueq, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status),
3454                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3455 FOP_COND_PS(olt, float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3456                  float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3457 FOP_COND_PS(ult, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status),
3458                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3459 FOP_COND_PS(ole, float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3460                  float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3461 FOP_COND_PS(ule, float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status),
3462                  float32_unordered_quiet(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le_quiet(fsth0, fsth1, &env->active_fpu.fp_status))
3463 /* NOTE: the comma operator will make "cond" to eval to false,
3464  * but float32_unordered() is still called. */
3465 FOP_COND_PS(sf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0),
3466                  (float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status), 0))
3467 FOP_COND_PS(ngle,float32_unordered(fst1, fst0, &env->active_fpu.fp_status),
3468                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status))
3469 FOP_COND_PS(seq, float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3470                  float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3471 FOP_COND_PS(ngl, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_eq(fst0, fst1, &env->active_fpu.fp_status),
3472                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_eq(fsth0, fsth1, &env->active_fpu.fp_status))
3473 FOP_COND_PS(lt,  float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3474                  float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3475 FOP_COND_PS(nge, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_lt(fst0, fst1, &env->active_fpu.fp_status),
3476                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_lt(fsth0, fsth1, &env->active_fpu.fp_status))
3477 FOP_COND_PS(le,  float32_le(fst0, fst1, &env->active_fpu.fp_status),
3478                  float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3479 FOP_COND_PS(ngt, float32_unordered(fst1, fst0, &env->active_fpu.fp_status)    || float32_le(fst0, fst1, &env->active_fpu.fp_status),
3480                  float32_unordered(fsth1, fsth0, &env->active_fpu.fp_status)  || float32_le(fsth0, fsth1, &env->active_fpu.fp_status))
3481
3482 /* R6 compare operations */
3483 #define FOP_CONDN_D(op, cond)                                       \
3484 uint64_t helper_r6_cmp_d_ ## op(CPUMIPSState * env, uint64_t fdt0,  \
3485                          uint64_t fdt1)                             \
3486 {                                                                   \
3487     uint64_t c;                                                     \
3488     c = cond;                                                       \
3489     update_fcr31(env, GETPC());                                     \
3490     if (c) {                                                        \
3491         return -1;                                                  \
3492     } else {                                                        \
3493         return 0;                                                   \
3494     }                                                               \
3495 }
3496
3497 /* NOTE: the comma operator will make "cond" to eval to false,
3498  * but float64_unordered_quiet() is still called. */
3499 FOP_CONDN_D(af,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3500 FOP_CONDN_D(un,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)))
3501 FOP_CONDN_D(eq,  (float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3502 FOP_CONDN_D(ueq, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3503                   || float64_eq_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3504 FOP_CONDN_D(lt,  (float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3505 FOP_CONDN_D(ult, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3506                   || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3507 FOP_CONDN_D(le,  (float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3508 FOP_CONDN_D(ule, (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3509                   || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3510 /* NOTE: the comma operator will make "cond" to eval to false,
3511  * but float64_unordered() is still called. */
3512 FOP_CONDN_D(saf,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status), 0))
3513 FOP_CONDN_D(sun,  (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)))
3514 FOP_CONDN_D(seq,  (float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3515 FOP_CONDN_D(sueq, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3516                    || float64_eq(fdt0, fdt1, &env->active_fpu.fp_status)))
3517 FOP_CONDN_D(slt,  (float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3518 FOP_CONDN_D(sult, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3519                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3520 FOP_CONDN_D(sle,  (float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3521 FOP_CONDN_D(sule, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3522                    || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3523 FOP_CONDN_D(or,   (float64_le_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3524                    || float64_le_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3525 FOP_CONDN_D(une,  (float64_unordered_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3526                    || float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3527                    || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3528 FOP_CONDN_D(ne,   (float64_lt_quiet(fdt1, fdt0, &env->active_fpu.fp_status)
3529                    || float64_lt_quiet(fdt0, fdt1, &env->active_fpu.fp_status)))
3530 FOP_CONDN_D(sor,  (float64_le(fdt1, fdt0, &env->active_fpu.fp_status)
3531                    || float64_le(fdt0, fdt1, &env->active_fpu.fp_status)))
3532 FOP_CONDN_D(sune, (float64_unordered(fdt1, fdt0, &env->active_fpu.fp_status)
3533                    || float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3534                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3535 FOP_CONDN_D(sne,  (float64_lt(fdt1, fdt0, &env->active_fpu.fp_status)
3536                    || float64_lt(fdt0, fdt1, &env->active_fpu.fp_status)))
3537
3538 #define FOP_CONDN_S(op, cond)                                       \
3539 uint32_t helper_r6_cmp_s_ ## op(CPUMIPSState * env, uint32_t fst0,  \
3540                          uint32_t fst1)                             \
3541 {                                                                   \
3542     uint64_t c;                                                     \
3543     c = cond;                                                       \
3544     update_fcr31(env, GETPC());                                     \
3545     if (c) {                                                        \
3546         return -1;                                                  \
3547     } else {                                                        \
3548         return 0;                                                   \
3549     }                                                               \
3550 }
3551
3552 /* NOTE: the comma operator will make "cond" to eval to false,
3553  * but float32_unordered_quiet() is still called. */
3554 FOP_CONDN_S(af,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status), 0))
3555 FOP_CONDN_S(un,   (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)))
3556 FOP_CONDN_S(eq,   (float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3557 FOP_CONDN_S(ueq,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3558                    || float32_eq_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3559 FOP_CONDN_S(lt,   (float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3560 FOP_CONDN_S(ult,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3561                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3562 FOP_CONDN_S(le,   (float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3563 FOP_CONDN_S(ule,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3564                    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3565 /* NOTE: the comma operator will make "cond" to eval to false,
3566  * but float32_unordered() is still called. */
3567 FOP_CONDN_S(saf,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status), 0))
3568 FOP_CONDN_S(sun,  (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)))
3569 FOP_CONDN_S(seq,  (float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3570 FOP_CONDN_S(sueq, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3571                    || float32_eq(fst0, fst1, &env->active_fpu.fp_status)))
3572 FOP_CONDN_S(slt,  (float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3573 FOP_CONDN_S(sult, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3574                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3575 FOP_CONDN_S(sle,  (float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3576 FOP_CONDN_S(sule, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3577                    || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3578 FOP_CONDN_S(or,   (float32_le_quiet(fst1, fst0, &env->active_fpu.fp_status)
3579                    || float32_le_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3580 FOP_CONDN_S(une,  (float32_unordered_quiet(fst1, fst0, &env->active_fpu.fp_status)
3581                    || float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3582                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3583 FOP_CONDN_S(ne,   (float32_lt_quiet(fst1, fst0, &env->active_fpu.fp_status)
3584                    || float32_lt_quiet(fst0, fst1, &env->active_fpu.fp_status)))
3585 FOP_CONDN_S(sor,  (float32_le(fst1, fst0, &env->active_fpu.fp_status)
3586                    || float32_le(fst0, fst1, &env->active_fpu.fp_status)))
3587 FOP_CONDN_S(sune, (float32_unordered(fst1, fst0, &env->active_fpu.fp_status)
3588                    || float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3589                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))
3590 FOP_CONDN_S(sne,  (float32_lt(fst1, fst0, &env->active_fpu.fp_status)
3591                    || float32_lt(fst0, fst1, &env->active_fpu.fp_status)))