petalogix-ml605: added SPI controller with n25q128
[qemu-kvm.git] / hw / qxl.c
blob33169f348add850e4089d05cb33d5cd1acb7bc71
1 /*
2 * Copyright (C) 2010 Red Hat, Inc.
4 * written by Yaniv Kamay, Izik Eidus, Gerd Hoffmann
5 * maintained by Gerd Hoffmann <kraxel@redhat.com>
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, see <http://www.gnu.org/licenses/>.
21 #include <zlib.h>
23 #include "qemu-common.h"
24 #include "qemu-timer.h"
25 #include "qemu-queue.h"
26 #include "monitor.h"
27 #include "sysemu.h"
28 #include "trace.h"
30 #include "qxl.h"
32 #ifndef CONFIG_QXL_IO_MONITORS_CONFIG_ASYNC
33 /* spice-protocol is too old, add missing definitions */
34 #define QXL_IO_MONITORS_CONFIG_ASYNC (QXL_IO_FLUSH_RELEASE + 1)
35 #endif
38 * NOTE: SPICE_RING_PROD_ITEM accesses memory on the pci bar and as
39 * such can be changed by the guest, so to avoid a guest trigerrable
40 * abort we just qxl_set_guest_bug and set the return to NULL. Still
41 * it may happen as a result of emulator bug as well.
43 #undef SPICE_RING_PROD_ITEM
44 #define SPICE_RING_PROD_ITEM(qxl, r, ret) { \
45 typeof(r) start = r; \
46 typeof(r) end = r + 1; \
47 uint32_t prod = (r)->prod & SPICE_RING_INDEX_MASK(r); \
48 typeof(&(r)->items[prod]) m_item = &(r)->items[prod]; \
49 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
50 qxl_set_guest_bug(qxl, "SPICE_RING_PROD_ITEM indices mismatch " \
51 "! %p <= %p < %p", (uint8_t *)start, \
52 (uint8_t *)m_item, (uint8_t *)end); \
53 ret = NULL; \
54 } else { \
55 ret = &m_item->el; \
56 } \
59 #undef SPICE_RING_CONS_ITEM
60 #define SPICE_RING_CONS_ITEM(qxl, r, ret) { \
61 typeof(r) start = r; \
62 typeof(r) end = r + 1; \
63 uint32_t cons = (r)->cons & SPICE_RING_INDEX_MASK(r); \
64 typeof(&(r)->items[cons]) m_item = &(r)->items[cons]; \
65 if (!((uint8_t*)m_item >= (uint8_t*)(start) && (uint8_t*)(m_item + 1) <= (uint8_t*)(end))) { \
66 qxl_set_guest_bug(qxl, "SPICE_RING_CONS_ITEM indices mismatch " \
67 "! %p <= %p < %p", (uint8_t *)start, \
68 (uint8_t *)m_item, (uint8_t *)end); \
69 ret = NULL; \
70 } else { \
71 ret = &m_item->el; \
72 } \
75 #undef ALIGN
76 #define ALIGN(a, b) (((a) + ((b) - 1)) & ~((b) - 1))
78 #define PIXEL_SIZE 0.2936875 //1280x1024 is 14.8" x 11.9"
80 #define QXL_MODE(_x, _y, _b, _o) \
81 { .x_res = _x, \
82 .y_res = _y, \
83 .bits = _b, \
84 .stride = (_x) * (_b) / 8, \
85 .x_mili = PIXEL_SIZE * (_x), \
86 .y_mili = PIXEL_SIZE * (_y), \
87 .orientation = _o, \
90 #define QXL_MODE_16_32(x_res, y_res, orientation) \
91 QXL_MODE(x_res, y_res, 16, orientation), \
92 QXL_MODE(x_res, y_res, 32, orientation)
94 #define QXL_MODE_EX(x_res, y_res) \
95 QXL_MODE_16_32(x_res, y_res, 0), \
96 QXL_MODE_16_32(y_res, x_res, 1), \
97 QXL_MODE_16_32(x_res, y_res, 2), \
98 QXL_MODE_16_32(y_res, x_res, 3)
100 static QXLMode qxl_modes[] = {
101 QXL_MODE_EX(640, 480),
102 QXL_MODE_EX(800, 480),
103 QXL_MODE_EX(800, 600),
104 QXL_MODE_EX(832, 624),
105 QXL_MODE_EX(960, 640),
106 QXL_MODE_EX(1024, 600),
107 QXL_MODE_EX(1024, 768),
108 QXL_MODE_EX(1152, 864),
109 QXL_MODE_EX(1152, 870),
110 QXL_MODE_EX(1280, 720),
111 QXL_MODE_EX(1280, 760),
112 QXL_MODE_EX(1280, 768),
113 QXL_MODE_EX(1280, 800),
114 QXL_MODE_EX(1280, 960),
115 QXL_MODE_EX(1280, 1024),
116 QXL_MODE_EX(1360, 768),
117 QXL_MODE_EX(1366, 768),
118 QXL_MODE_EX(1400, 1050),
119 QXL_MODE_EX(1440, 900),
120 QXL_MODE_EX(1600, 900),
121 QXL_MODE_EX(1600, 1200),
122 QXL_MODE_EX(1680, 1050),
123 QXL_MODE_EX(1920, 1080),
124 /* these modes need more than 8 MB video memory */
125 QXL_MODE_EX(1920, 1200),
126 QXL_MODE_EX(1920, 1440),
127 QXL_MODE_EX(2048, 1536),
128 QXL_MODE_EX(2560, 1440),
129 QXL_MODE_EX(2560, 1600),
130 /* these modes need more than 16 MB video memory */
131 QXL_MODE_EX(2560, 2048),
132 QXL_MODE_EX(2800, 2100),
133 QXL_MODE_EX(3200, 2400),
136 static PCIQXLDevice *qxl0;
138 static void qxl_send_events(PCIQXLDevice *d, uint32_t events);
139 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async);
140 static void qxl_reset_memslots(PCIQXLDevice *d);
141 static void qxl_reset_surfaces(PCIQXLDevice *d);
142 static void qxl_ring_set_dirty(PCIQXLDevice *qxl);
144 void qxl_set_guest_bug(PCIQXLDevice *qxl, const char *msg, ...)
146 trace_qxl_set_guest_bug(qxl->id);
147 qxl_send_events(qxl, QXL_INTERRUPT_ERROR);
148 qxl->guest_bug = 1;
149 if (qxl->guestdebug) {
150 va_list ap;
151 va_start(ap, msg);
152 fprintf(stderr, "qxl-%d: guest bug: ", qxl->id);
153 vfprintf(stderr, msg, ap);
154 fprintf(stderr, "\n");
155 va_end(ap);
159 static void qxl_clear_guest_bug(PCIQXLDevice *qxl)
161 qxl->guest_bug = 0;
164 void qxl_spice_update_area(PCIQXLDevice *qxl, uint32_t surface_id,
165 struct QXLRect *area, struct QXLRect *dirty_rects,
166 uint32_t num_dirty_rects,
167 uint32_t clear_dirty_region,
168 qxl_async_io async, struct QXLCookie *cookie)
170 trace_qxl_spice_update_area(qxl->id, surface_id, area->left, area->right,
171 area->top, area->bottom);
172 trace_qxl_spice_update_area_rest(qxl->id, num_dirty_rects,
173 clear_dirty_region);
174 if (async == QXL_SYNC) {
175 qxl->ssd.worker->update_area(qxl->ssd.worker, surface_id, area,
176 dirty_rects, num_dirty_rects, clear_dirty_region);
177 } else {
178 assert(cookie != NULL);
179 spice_qxl_update_area_async(&qxl->ssd.qxl, surface_id, area,
180 clear_dirty_region, (uintptr_t)cookie);
184 static void qxl_spice_destroy_surface_wait_complete(PCIQXLDevice *qxl,
185 uint32_t id)
187 trace_qxl_spice_destroy_surface_wait_complete(qxl->id, id);
188 qemu_mutex_lock(&qxl->track_lock);
189 qxl->guest_surfaces.cmds[id] = 0;
190 qxl->guest_surfaces.count--;
191 qemu_mutex_unlock(&qxl->track_lock);
194 static void qxl_spice_destroy_surface_wait(PCIQXLDevice *qxl, uint32_t id,
195 qxl_async_io async)
197 QXLCookie *cookie;
199 trace_qxl_spice_destroy_surface_wait(qxl->id, id, async);
200 if (async) {
201 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
202 QXL_IO_DESTROY_SURFACE_ASYNC);
203 cookie->u.surface_id = id;
204 spice_qxl_destroy_surface_async(&qxl->ssd.qxl, id, (uintptr_t)cookie);
205 } else {
206 qxl->ssd.worker->destroy_surface_wait(qxl->ssd.worker, id);
207 qxl_spice_destroy_surface_wait_complete(qxl, id);
211 static void qxl_spice_flush_surfaces_async(PCIQXLDevice *qxl)
213 trace_qxl_spice_flush_surfaces_async(qxl->id, qxl->guest_surfaces.count,
214 qxl->num_free_res);
215 spice_qxl_flush_surfaces_async(&qxl->ssd.qxl,
216 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
217 QXL_IO_FLUSH_SURFACES_ASYNC));
220 void qxl_spice_loadvm_commands(PCIQXLDevice *qxl, struct QXLCommandExt *ext,
221 uint32_t count)
223 trace_qxl_spice_loadvm_commands(qxl->id, ext, count);
224 qxl->ssd.worker->loadvm_commands(qxl->ssd.worker, ext, count);
227 void qxl_spice_oom(PCIQXLDevice *qxl)
229 trace_qxl_spice_oom(qxl->id);
230 qxl->ssd.worker->oom(qxl->ssd.worker);
233 void qxl_spice_reset_memslots(PCIQXLDevice *qxl)
235 trace_qxl_spice_reset_memslots(qxl->id);
236 qxl->ssd.worker->reset_memslots(qxl->ssd.worker);
239 static void qxl_spice_destroy_surfaces_complete(PCIQXLDevice *qxl)
241 trace_qxl_spice_destroy_surfaces_complete(qxl->id);
242 qemu_mutex_lock(&qxl->track_lock);
243 memset(qxl->guest_surfaces.cmds, 0,
244 sizeof(qxl->guest_surfaces.cmds) * qxl->ssd.num_surfaces);
245 qxl->guest_surfaces.count = 0;
246 qemu_mutex_unlock(&qxl->track_lock);
249 static void qxl_spice_destroy_surfaces(PCIQXLDevice *qxl, qxl_async_io async)
251 trace_qxl_spice_destroy_surfaces(qxl->id, async);
252 if (async) {
253 spice_qxl_destroy_surfaces_async(&qxl->ssd.qxl,
254 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
255 QXL_IO_DESTROY_ALL_SURFACES_ASYNC));
256 } else {
257 qxl->ssd.worker->destroy_surfaces(qxl->ssd.worker);
258 qxl_spice_destroy_surfaces_complete(qxl);
262 static void qxl_spice_monitors_config_async(PCIQXLDevice *qxl, int replay)
264 trace_qxl_spice_monitors_config(qxl->id);
265 /* 0x000b01 == 0.11.1 */
266 #if SPICE_SERVER_VERSION >= 0x000b01 && \
267 defined(CONFIG_QXL_IO_MONITORS_CONFIG_ASYNC)
268 if (replay) {
270 * don't use QXL_COOKIE_TYPE_IO:
271 * - we are not running yet (post_load), we will assert
272 * in send_events
273 * - this is not a guest io, but a reply, so async_io isn't set.
275 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
276 qxl->guest_monitors_config,
277 MEMSLOT_GROUP_GUEST,
278 (uintptr_t)qxl_cookie_new(
279 QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG,
280 0));
281 } else {
282 qxl->guest_monitors_config = qxl->ram->monitors_config;
283 spice_qxl_monitors_config_async(&qxl->ssd.qxl,
284 qxl->ram->monitors_config,
285 MEMSLOT_GROUP_GUEST,
286 (uintptr_t)qxl_cookie_new(QXL_COOKIE_TYPE_IO,
287 QXL_IO_MONITORS_CONFIG_ASYNC));
289 #else
290 fprintf(stderr, "qxl: too old spice-protocol/spice-server for "
291 "QXL_IO_MONITORS_CONFIG_ASYNC\n");
292 #endif
295 void qxl_spice_reset_image_cache(PCIQXLDevice *qxl)
297 trace_qxl_spice_reset_image_cache(qxl->id);
298 qxl->ssd.worker->reset_image_cache(qxl->ssd.worker);
301 void qxl_spice_reset_cursor(PCIQXLDevice *qxl)
303 trace_qxl_spice_reset_cursor(qxl->id);
304 qxl->ssd.worker->reset_cursor(qxl->ssd.worker);
305 qemu_mutex_lock(&qxl->track_lock);
306 qxl->guest_cursor = 0;
307 qemu_mutex_unlock(&qxl->track_lock);
311 static inline uint32_t msb_mask(uint32_t val)
313 uint32_t mask;
315 do {
316 mask = ~(val - 1) & val;
317 val &= ~mask;
318 } while (mask < val);
320 return mask;
323 static ram_addr_t qxl_rom_size(void)
325 uint32_t rom_size = sizeof(QXLRom) + sizeof(QXLModes) + sizeof(qxl_modes);
327 rom_size = MAX(rom_size, TARGET_PAGE_SIZE);
328 rom_size = msb_mask(rom_size * 2 - 1);
329 return rom_size;
332 static void init_qxl_rom(PCIQXLDevice *d)
334 QXLRom *rom = memory_region_get_ram_ptr(&d->rom_bar);
335 QXLModes *modes = (QXLModes *)(rom + 1);
336 uint32_t ram_header_size;
337 uint32_t surface0_area_size;
338 uint32_t num_pages;
339 uint32_t fb;
340 int i, n;
342 memset(rom, 0, d->rom_size);
344 rom->magic = cpu_to_le32(QXL_ROM_MAGIC);
345 rom->id = cpu_to_le32(d->id);
346 rom->log_level = cpu_to_le32(d->guestdebug);
347 rom->modes_offset = cpu_to_le32(sizeof(QXLRom));
349 rom->slot_gen_bits = MEMSLOT_GENERATION_BITS;
350 rom->slot_id_bits = MEMSLOT_SLOT_BITS;
351 rom->slots_start = 1;
352 rom->slots_end = NUM_MEMSLOTS - 1;
353 rom->n_surfaces = cpu_to_le32(d->ssd.num_surfaces);
355 for (i = 0, n = 0; i < ARRAY_SIZE(qxl_modes); i++) {
356 fb = qxl_modes[i].y_res * qxl_modes[i].stride;
357 if (fb > d->vgamem_size) {
358 continue;
360 modes->modes[n].id = cpu_to_le32(i);
361 modes->modes[n].x_res = cpu_to_le32(qxl_modes[i].x_res);
362 modes->modes[n].y_res = cpu_to_le32(qxl_modes[i].y_res);
363 modes->modes[n].bits = cpu_to_le32(qxl_modes[i].bits);
364 modes->modes[n].stride = cpu_to_le32(qxl_modes[i].stride);
365 modes->modes[n].x_mili = cpu_to_le32(qxl_modes[i].x_mili);
366 modes->modes[n].y_mili = cpu_to_le32(qxl_modes[i].y_mili);
367 modes->modes[n].orientation = cpu_to_le32(qxl_modes[i].orientation);
368 n++;
370 modes->n_modes = cpu_to_le32(n);
372 ram_header_size = ALIGN(sizeof(QXLRam), 4096);
373 surface0_area_size = ALIGN(d->vgamem_size, 4096);
374 num_pages = d->vga.vram_size;
375 num_pages -= ram_header_size;
376 num_pages -= surface0_area_size;
377 num_pages = num_pages / TARGET_PAGE_SIZE;
379 rom->draw_area_offset = cpu_to_le32(0);
380 rom->surface0_area_size = cpu_to_le32(surface0_area_size);
381 rom->pages_offset = cpu_to_le32(surface0_area_size);
382 rom->num_pages = cpu_to_le32(num_pages);
383 rom->ram_header_offset = cpu_to_le32(d->vga.vram_size - ram_header_size);
385 d->shadow_rom = *rom;
386 d->rom = rom;
387 d->modes = modes;
390 static void init_qxl_ram(PCIQXLDevice *d)
392 uint8_t *buf;
393 uint64_t *item;
395 buf = d->vga.vram_ptr;
396 d->ram = (QXLRam *)(buf + le32_to_cpu(d->shadow_rom.ram_header_offset));
397 d->ram->magic = cpu_to_le32(QXL_RAM_MAGIC);
398 d->ram->int_pending = cpu_to_le32(0);
399 d->ram->int_mask = cpu_to_le32(0);
400 d->ram->update_surface = 0;
401 SPICE_RING_INIT(&d->ram->cmd_ring);
402 SPICE_RING_INIT(&d->ram->cursor_ring);
403 SPICE_RING_INIT(&d->ram->release_ring);
404 SPICE_RING_PROD_ITEM(d, &d->ram->release_ring, item);
405 assert(item);
406 *item = 0;
407 qxl_ring_set_dirty(d);
410 /* can be called from spice server thread context */
411 static void qxl_set_dirty(MemoryRegion *mr, ram_addr_t addr, ram_addr_t end)
413 memory_region_set_dirty(mr, addr, end - addr);
416 static void qxl_rom_set_dirty(PCIQXLDevice *qxl)
418 qxl_set_dirty(&qxl->rom_bar, 0, qxl->rom_size);
421 /* called from spice server thread context only */
422 static void qxl_ram_set_dirty(PCIQXLDevice *qxl, void *ptr)
424 void *base = qxl->vga.vram_ptr;
425 intptr_t offset;
427 offset = ptr - base;
428 offset &= ~(TARGET_PAGE_SIZE-1);
429 assert(offset < qxl->vga.vram_size);
430 qxl_set_dirty(&qxl->vga.vram, offset, offset + TARGET_PAGE_SIZE);
433 /* can be called from spice server thread context */
434 static void qxl_ring_set_dirty(PCIQXLDevice *qxl)
436 ram_addr_t addr = qxl->shadow_rom.ram_header_offset;
437 ram_addr_t end = qxl->vga.vram_size;
438 qxl_set_dirty(&qxl->vga.vram, addr, end);
442 * keep track of some command state, for savevm/loadvm.
443 * called from spice server thread context only
445 static int qxl_track_command(PCIQXLDevice *qxl, struct QXLCommandExt *ext)
447 switch (le32_to_cpu(ext->cmd.type)) {
448 case QXL_CMD_SURFACE:
450 QXLSurfaceCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
452 if (!cmd) {
453 return 1;
455 uint32_t id = le32_to_cpu(cmd->surface_id);
457 if (id >= qxl->ssd.num_surfaces) {
458 qxl_set_guest_bug(qxl, "QXL_CMD_SURFACE id %d >= %d", id,
459 qxl->ssd.num_surfaces);
460 return 1;
462 qemu_mutex_lock(&qxl->track_lock);
463 if (cmd->type == QXL_SURFACE_CMD_CREATE) {
464 qxl->guest_surfaces.cmds[id] = ext->cmd.data;
465 qxl->guest_surfaces.count++;
466 if (qxl->guest_surfaces.max < qxl->guest_surfaces.count)
467 qxl->guest_surfaces.max = qxl->guest_surfaces.count;
469 if (cmd->type == QXL_SURFACE_CMD_DESTROY) {
470 qxl->guest_surfaces.cmds[id] = 0;
471 qxl->guest_surfaces.count--;
473 qemu_mutex_unlock(&qxl->track_lock);
474 break;
476 case QXL_CMD_CURSOR:
478 QXLCursorCmd *cmd = qxl_phys2virt(qxl, ext->cmd.data, ext->group_id);
480 if (!cmd) {
481 return 1;
483 if (cmd->type == QXL_CURSOR_SET) {
484 qemu_mutex_lock(&qxl->track_lock);
485 qxl->guest_cursor = ext->cmd.data;
486 qemu_mutex_unlock(&qxl->track_lock);
488 break;
491 return 0;
494 /* spice display interface callbacks */
496 static void interface_attach_worker(QXLInstance *sin, QXLWorker *qxl_worker)
498 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
500 trace_qxl_interface_attach_worker(qxl->id);
501 qxl->ssd.worker = qxl_worker;
504 static void interface_set_compression_level(QXLInstance *sin, int level)
506 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
508 trace_qxl_interface_set_compression_level(qxl->id, level);
509 qxl->shadow_rom.compression_level = cpu_to_le32(level);
510 qxl->rom->compression_level = cpu_to_le32(level);
511 qxl_rom_set_dirty(qxl);
514 static void interface_set_mm_time(QXLInstance *sin, uint32_t mm_time)
516 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
518 trace_qxl_interface_set_mm_time(qxl->id, mm_time);
519 qxl->shadow_rom.mm_clock = cpu_to_le32(mm_time);
520 qxl->rom->mm_clock = cpu_to_le32(mm_time);
521 qxl_rom_set_dirty(qxl);
524 static void interface_get_init_info(QXLInstance *sin, QXLDevInitInfo *info)
526 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
528 trace_qxl_interface_get_init_info(qxl->id);
529 info->memslot_gen_bits = MEMSLOT_GENERATION_BITS;
530 info->memslot_id_bits = MEMSLOT_SLOT_BITS;
531 info->num_memslots = NUM_MEMSLOTS;
532 info->num_memslots_groups = NUM_MEMSLOTS_GROUPS;
533 info->internal_groupslot_id = 0;
534 info->qxl_ram_size = le32_to_cpu(qxl->shadow_rom.num_pages) << TARGET_PAGE_BITS;
535 info->n_surfaces = qxl->ssd.num_surfaces;
538 static const char *qxl_mode_to_string(int mode)
540 switch (mode) {
541 case QXL_MODE_COMPAT:
542 return "compat";
543 case QXL_MODE_NATIVE:
544 return "native";
545 case QXL_MODE_UNDEFINED:
546 return "undefined";
547 case QXL_MODE_VGA:
548 return "vga";
550 return "INVALID";
553 static const char *io_port_to_string(uint32_t io_port)
555 if (io_port >= QXL_IO_RANGE_SIZE) {
556 return "out of range";
558 static const char *io_port_to_string[QXL_IO_RANGE_SIZE + 1] = {
559 [QXL_IO_NOTIFY_CMD] = "QXL_IO_NOTIFY_CMD",
560 [QXL_IO_NOTIFY_CURSOR] = "QXL_IO_NOTIFY_CURSOR",
561 [QXL_IO_UPDATE_AREA] = "QXL_IO_UPDATE_AREA",
562 [QXL_IO_UPDATE_IRQ] = "QXL_IO_UPDATE_IRQ",
563 [QXL_IO_NOTIFY_OOM] = "QXL_IO_NOTIFY_OOM",
564 [QXL_IO_RESET] = "QXL_IO_RESET",
565 [QXL_IO_SET_MODE] = "QXL_IO_SET_MODE",
566 [QXL_IO_LOG] = "QXL_IO_LOG",
567 [QXL_IO_MEMSLOT_ADD] = "QXL_IO_MEMSLOT_ADD",
568 [QXL_IO_MEMSLOT_DEL] = "QXL_IO_MEMSLOT_DEL",
569 [QXL_IO_DETACH_PRIMARY] = "QXL_IO_DETACH_PRIMARY",
570 [QXL_IO_ATTACH_PRIMARY] = "QXL_IO_ATTACH_PRIMARY",
571 [QXL_IO_CREATE_PRIMARY] = "QXL_IO_CREATE_PRIMARY",
572 [QXL_IO_DESTROY_PRIMARY] = "QXL_IO_DESTROY_PRIMARY",
573 [QXL_IO_DESTROY_SURFACE_WAIT] = "QXL_IO_DESTROY_SURFACE_WAIT",
574 [QXL_IO_DESTROY_ALL_SURFACES] = "QXL_IO_DESTROY_ALL_SURFACES",
575 [QXL_IO_UPDATE_AREA_ASYNC] = "QXL_IO_UPDATE_AREA_ASYNC",
576 [QXL_IO_MEMSLOT_ADD_ASYNC] = "QXL_IO_MEMSLOT_ADD_ASYNC",
577 [QXL_IO_CREATE_PRIMARY_ASYNC] = "QXL_IO_CREATE_PRIMARY_ASYNC",
578 [QXL_IO_DESTROY_PRIMARY_ASYNC] = "QXL_IO_DESTROY_PRIMARY_ASYNC",
579 [QXL_IO_DESTROY_SURFACE_ASYNC] = "QXL_IO_DESTROY_SURFACE_ASYNC",
580 [QXL_IO_DESTROY_ALL_SURFACES_ASYNC]
581 = "QXL_IO_DESTROY_ALL_SURFACES_ASYNC",
582 [QXL_IO_FLUSH_SURFACES_ASYNC] = "QXL_IO_FLUSH_SURFACES_ASYNC",
583 [QXL_IO_FLUSH_RELEASE] = "QXL_IO_FLUSH_RELEASE",
584 [QXL_IO_MONITORS_CONFIG_ASYNC] = "QXL_IO_MONITORS_CONFIG_ASYNC",
586 return io_port_to_string[io_port];
589 /* called from spice server thread context only */
590 static int interface_get_command(QXLInstance *sin, struct QXLCommandExt *ext)
592 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
593 SimpleSpiceUpdate *update;
594 QXLCommandRing *ring;
595 QXLCommand *cmd;
596 int notify, ret;
598 trace_qxl_ring_command_check(qxl->id, qxl_mode_to_string(qxl->mode));
600 switch (qxl->mode) {
601 case QXL_MODE_VGA:
602 ret = false;
603 qemu_mutex_lock(&qxl->ssd.lock);
604 update = QTAILQ_FIRST(&qxl->ssd.updates);
605 if (update != NULL) {
606 QTAILQ_REMOVE(&qxl->ssd.updates, update, next);
607 *ext = update->ext;
608 ret = true;
610 qemu_mutex_unlock(&qxl->ssd.lock);
611 if (ret) {
612 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
613 qxl_log_command(qxl, "vga", ext);
615 return ret;
616 case QXL_MODE_COMPAT:
617 case QXL_MODE_NATIVE:
618 case QXL_MODE_UNDEFINED:
619 ring = &qxl->ram->cmd_ring;
620 if (qxl->guest_bug || SPICE_RING_IS_EMPTY(ring)) {
621 return false;
623 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
624 if (!cmd) {
625 return false;
627 ext->cmd = *cmd;
628 ext->group_id = MEMSLOT_GROUP_GUEST;
629 ext->flags = qxl->cmdflags;
630 SPICE_RING_POP(ring, notify);
631 qxl_ring_set_dirty(qxl);
632 if (notify) {
633 qxl_send_events(qxl, QXL_INTERRUPT_DISPLAY);
635 qxl->guest_primary.commands++;
636 qxl_track_command(qxl, ext);
637 qxl_log_command(qxl, "cmd", ext);
638 trace_qxl_ring_command_get(qxl->id, qxl_mode_to_string(qxl->mode));
639 return true;
640 default:
641 return false;
645 /* called from spice server thread context only */
646 static int interface_req_cmd_notification(QXLInstance *sin)
648 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
649 int wait = 1;
651 trace_qxl_ring_command_req_notification(qxl->id);
652 switch (qxl->mode) {
653 case QXL_MODE_COMPAT:
654 case QXL_MODE_NATIVE:
655 case QXL_MODE_UNDEFINED:
656 SPICE_RING_CONS_WAIT(&qxl->ram->cmd_ring, wait);
657 qxl_ring_set_dirty(qxl);
658 break;
659 default:
660 /* nothing */
661 break;
663 return wait;
666 /* called from spice server thread context only */
667 static inline void qxl_push_free_res(PCIQXLDevice *d, int flush)
669 QXLReleaseRing *ring = &d->ram->release_ring;
670 uint64_t *item;
671 int notify;
673 #define QXL_FREE_BUNCH_SIZE 32
675 if (ring->prod - ring->cons + 1 == ring->num_items) {
676 /* ring full -- can't push */
677 return;
679 if (!flush && d->oom_running) {
680 /* collect everything from oom handler before pushing */
681 return;
683 if (!flush && d->num_free_res < QXL_FREE_BUNCH_SIZE) {
684 /* collect a bit more before pushing */
685 return;
688 SPICE_RING_PUSH(ring, notify);
689 trace_qxl_ring_res_push(d->id, qxl_mode_to_string(d->mode),
690 d->guest_surfaces.count, d->num_free_res,
691 d->last_release, notify ? "yes" : "no");
692 trace_qxl_ring_res_push_rest(d->id, ring->prod - ring->cons,
693 ring->num_items, ring->prod, ring->cons);
694 if (notify) {
695 qxl_send_events(d, QXL_INTERRUPT_DISPLAY);
697 SPICE_RING_PROD_ITEM(d, ring, item);
698 if (!item) {
699 return;
701 *item = 0;
702 d->num_free_res = 0;
703 d->last_release = NULL;
704 qxl_ring_set_dirty(d);
707 /* called from spice server thread context only */
708 static void interface_release_resource(QXLInstance *sin,
709 struct QXLReleaseInfoExt ext)
711 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
712 QXLReleaseRing *ring;
713 uint64_t *item, id;
715 if (ext.group_id == MEMSLOT_GROUP_HOST) {
716 /* host group -> vga mode update request */
717 qemu_spice_destroy_update(&qxl->ssd, (void *)(intptr_t)ext.info->id);
718 return;
722 * ext->info points into guest-visible memory
723 * pci bar 0, $command.release_info
725 ring = &qxl->ram->release_ring;
726 SPICE_RING_PROD_ITEM(qxl, ring, item);
727 if (!item) {
728 return;
730 if (*item == 0) {
731 /* stick head into the ring */
732 id = ext.info->id;
733 ext.info->next = 0;
734 qxl_ram_set_dirty(qxl, &ext.info->next);
735 *item = id;
736 qxl_ring_set_dirty(qxl);
737 } else {
738 /* append item to the list */
739 qxl->last_release->next = ext.info->id;
740 qxl_ram_set_dirty(qxl, &qxl->last_release->next);
741 ext.info->next = 0;
742 qxl_ram_set_dirty(qxl, &ext.info->next);
744 qxl->last_release = ext.info;
745 qxl->num_free_res++;
746 trace_qxl_ring_res_put(qxl->id, qxl->num_free_res);
747 qxl_push_free_res(qxl, 0);
750 /* called from spice server thread context only */
751 static int interface_get_cursor_command(QXLInstance *sin, struct QXLCommandExt *ext)
753 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
754 QXLCursorRing *ring;
755 QXLCommand *cmd;
756 int notify;
758 trace_qxl_ring_cursor_check(qxl->id, qxl_mode_to_string(qxl->mode));
760 switch (qxl->mode) {
761 case QXL_MODE_COMPAT:
762 case QXL_MODE_NATIVE:
763 case QXL_MODE_UNDEFINED:
764 ring = &qxl->ram->cursor_ring;
765 if (SPICE_RING_IS_EMPTY(ring)) {
766 return false;
768 SPICE_RING_CONS_ITEM(qxl, ring, cmd);
769 if (!cmd) {
770 return false;
772 ext->cmd = *cmd;
773 ext->group_id = MEMSLOT_GROUP_GUEST;
774 ext->flags = qxl->cmdflags;
775 SPICE_RING_POP(ring, notify);
776 qxl_ring_set_dirty(qxl);
777 if (notify) {
778 qxl_send_events(qxl, QXL_INTERRUPT_CURSOR);
780 qxl->guest_primary.commands++;
781 qxl_track_command(qxl, ext);
782 qxl_log_command(qxl, "csr", ext);
783 if (qxl->id == 0) {
784 qxl_render_cursor(qxl, ext);
786 trace_qxl_ring_cursor_get(qxl->id, qxl_mode_to_string(qxl->mode));
787 return true;
788 default:
789 return false;
793 /* called from spice server thread context only */
794 static int interface_req_cursor_notification(QXLInstance *sin)
796 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
797 int wait = 1;
799 trace_qxl_ring_cursor_req_notification(qxl->id);
800 switch (qxl->mode) {
801 case QXL_MODE_COMPAT:
802 case QXL_MODE_NATIVE:
803 case QXL_MODE_UNDEFINED:
804 SPICE_RING_CONS_WAIT(&qxl->ram->cursor_ring, wait);
805 qxl_ring_set_dirty(qxl);
806 break;
807 default:
808 /* nothing */
809 break;
811 return wait;
814 /* called from spice server thread context */
815 static void interface_notify_update(QXLInstance *sin, uint32_t update_id)
818 * Called by spice-server as a result of a QXL_CMD_UPDATE which is not in
819 * use by xf86-video-qxl and is defined out in the qxl windows driver.
820 * Probably was at some earlier version that is prior to git start (2009),
821 * and is still guest trigerrable.
823 fprintf(stderr, "%s: deprecated\n", __func__);
826 /* called from spice server thread context only */
827 static int interface_flush_resources(QXLInstance *sin)
829 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
830 int ret;
832 ret = qxl->num_free_res;
833 if (ret) {
834 qxl_push_free_res(qxl, 1);
836 return ret;
839 static void qxl_create_guest_primary_complete(PCIQXLDevice *d);
841 /* called from spice server thread context only */
842 static void interface_async_complete_io(PCIQXLDevice *qxl, QXLCookie *cookie)
844 uint32_t current_async;
846 qemu_mutex_lock(&qxl->async_lock);
847 current_async = qxl->current_async;
848 qxl->current_async = QXL_UNDEFINED_IO;
849 qemu_mutex_unlock(&qxl->async_lock);
851 trace_qxl_interface_async_complete_io(qxl->id, current_async, cookie);
852 if (!cookie) {
853 fprintf(stderr, "qxl: %s: error, cookie is NULL\n", __func__);
854 return;
856 if (cookie && current_async != cookie->io) {
857 fprintf(stderr,
858 "qxl: %s: error: current_async = %d != %"
859 PRId64 " = cookie->io\n", __func__, current_async, cookie->io);
861 switch (current_async) {
862 case QXL_IO_MEMSLOT_ADD_ASYNC:
863 case QXL_IO_DESTROY_PRIMARY_ASYNC:
864 case QXL_IO_UPDATE_AREA_ASYNC:
865 case QXL_IO_FLUSH_SURFACES_ASYNC:
866 case QXL_IO_MONITORS_CONFIG_ASYNC:
867 break;
868 case QXL_IO_CREATE_PRIMARY_ASYNC:
869 qxl_create_guest_primary_complete(qxl);
870 break;
871 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
872 qxl_spice_destroy_surfaces_complete(qxl);
873 break;
874 case QXL_IO_DESTROY_SURFACE_ASYNC:
875 qxl_spice_destroy_surface_wait_complete(qxl, cookie->u.surface_id);
876 break;
877 default:
878 fprintf(stderr, "qxl: %s: unexpected current_async %d\n", __func__,
879 current_async);
881 qxl_send_events(qxl, QXL_INTERRUPT_IO_CMD);
884 /* called from spice server thread context only */
885 static void interface_update_area_complete(QXLInstance *sin,
886 uint32_t surface_id,
887 QXLRect *dirty, uint32_t num_updated_rects)
889 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
890 int i;
891 int qxl_i;
893 qemu_mutex_lock(&qxl->ssd.lock);
894 if (surface_id != 0 || !qxl->render_update_cookie_num) {
895 qemu_mutex_unlock(&qxl->ssd.lock);
896 return;
898 trace_qxl_interface_update_area_complete(qxl->id, surface_id, dirty->left,
899 dirty->right, dirty->top, dirty->bottom);
900 trace_qxl_interface_update_area_complete_rest(qxl->id, num_updated_rects);
901 if (qxl->num_dirty_rects + num_updated_rects > QXL_NUM_DIRTY_RECTS) {
903 * overflow - treat this as a full update. Not expected to be common.
905 trace_qxl_interface_update_area_complete_overflow(qxl->id,
906 QXL_NUM_DIRTY_RECTS);
907 qxl->guest_primary.resized = 1;
909 if (qxl->guest_primary.resized) {
911 * Don't bother copying or scheduling the bh since we will flip
912 * the whole area anyway on completion of the update_area async call
914 qemu_mutex_unlock(&qxl->ssd.lock);
915 return;
917 qxl_i = qxl->num_dirty_rects;
918 for (i = 0; i < num_updated_rects; i++) {
919 qxl->dirty[qxl_i++] = dirty[i];
921 qxl->num_dirty_rects += num_updated_rects;
922 trace_qxl_interface_update_area_complete_schedule_bh(qxl->id,
923 qxl->num_dirty_rects);
924 qemu_bh_schedule(qxl->update_area_bh);
925 qemu_mutex_unlock(&qxl->ssd.lock);
928 /* called from spice server thread context only */
929 static void interface_async_complete(QXLInstance *sin, uint64_t cookie_token)
931 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
932 QXLCookie *cookie = (QXLCookie *)(uintptr_t)cookie_token;
934 switch (cookie->type) {
935 case QXL_COOKIE_TYPE_IO:
936 interface_async_complete_io(qxl, cookie);
937 g_free(cookie);
938 break;
939 case QXL_COOKIE_TYPE_RENDER_UPDATE_AREA:
940 qxl_render_update_area_done(qxl, cookie);
941 break;
942 case QXL_COOKIE_TYPE_POST_LOAD_MONITORS_CONFIG:
943 break;
944 default:
945 fprintf(stderr, "qxl: %s: unexpected cookie type %d\n",
946 __func__, cookie->type);
947 g_free(cookie);
951 #if SPICE_SERVER_VERSION >= 0x000b04
953 /* called from spice server thread context only */
954 static void interface_set_client_capabilities(QXLInstance *sin,
955 uint8_t client_present,
956 uint8_t caps[58])
958 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
960 if (runstate_check(RUN_STATE_INMIGRATE) ||
961 runstate_check(RUN_STATE_POSTMIGRATE)) {
962 return;
965 qxl->shadow_rom.client_present = client_present;
966 memcpy(qxl->shadow_rom.client_capabilities, caps, sizeof(caps));
967 qxl->rom->client_present = client_present;
968 memcpy(qxl->rom->client_capabilities, caps, sizeof(caps));
969 qxl_rom_set_dirty(qxl);
971 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT);
974 #endif
976 #if defined(CONFIG_QXL_CLIENT_MONITORS_CONFIG) \
977 && SPICE_SERVER_VERSION >= 0x000b05
979 static uint32_t qxl_crc32(const uint8_t *p, unsigned len)
982 * zlib xors the seed with 0xffffffff, and xors the result
983 * again with 0xffffffff; Both are not done with linux's crc32,
984 * which we want to be compatible with, so undo that.
986 return crc32(0xffffffff, p, len) ^ 0xffffffff;
989 /* called from main context only */
990 static int interface_client_monitors_config(QXLInstance *sin,
991 VDAgentMonitorsConfig *monitors_config)
993 PCIQXLDevice *qxl = container_of(sin, PCIQXLDevice, ssd.qxl);
994 QXLRom *rom = memory_region_get_ram_ptr(&qxl->rom_bar);
995 int i;
998 * Older windows drivers set int_mask to 0 when their ISR is called,
999 * then later set it to ~0. So it doesn't relate to the actual interrupts
1000 * handled. However, they are old, so clearly they don't support this
1001 * interrupt
1003 if (qxl->ram->int_mask == 0 || qxl->ram->int_mask == ~0 ||
1004 !(qxl->ram->int_mask & QXL_INTERRUPT_CLIENT_MONITORS_CONFIG)) {
1005 trace_qxl_client_monitors_config_unsupported_by_guest(qxl->id,
1006 qxl->ram->int_mask,
1007 monitors_config);
1008 return 0;
1010 if (!monitors_config) {
1011 return 1;
1013 memset(&rom->client_monitors_config, 0,
1014 sizeof(rom->client_monitors_config));
1015 rom->client_monitors_config.count = monitors_config->num_of_monitors;
1016 /* monitors_config->flags ignored */
1017 if (rom->client_monitors_config.count >=
1018 ARRAY_SIZE(rom->client_monitors_config.heads)) {
1019 trace_qxl_client_monitors_config_capped(qxl->id,
1020 monitors_config->num_of_monitors,
1021 ARRAY_SIZE(rom->client_monitors_config.heads));
1022 rom->client_monitors_config.count =
1023 ARRAY_SIZE(rom->client_monitors_config.heads);
1025 for (i = 0 ; i < rom->client_monitors_config.count ; ++i) {
1026 VDAgentMonConfig *monitor = &monitors_config->monitors[i];
1027 QXLURect *rect = &rom->client_monitors_config.heads[i];
1028 /* monitor->depth ignored */
1029 rect->left = monitor->x;
1030 rect->top = monitor->y;
1031 rect->right = monitor->x + monitor->width;
1032 rect->bottom = monitor->y + monitor->height;
1034 rom->client_monitors_config_crc = qxl_crc32(
1035 (const uint8_t *)&rom->client_monitors_config,
1036 sizeof(rom->client_monitors_config));
1037 trace_qxl_client_monitors_config_crc(qxl->id,
1038 sizeof(rom->client_monitors_config),
1039 rom->client_monitors_config_crc);
1041 trace_qxl_interrupt_client_monitors_config(qxl->id,
1042 rom->client_monitors_config.count,
1043 rom->client_monitors_config.heads);
1044 qxl_send_events(qxl, QXL_INTERRUPT_CLIENT_MONITORS_CONFIG);
1045 return 1;
1047 #endif
1049 static const QXLInterface qxl_interface = {
1050 .base.type = SPICE_INTERFACE_QXL,
1051 .base.description = "qxl gpu",
1052 .base.major_version = SPICE_INTERFACE_QXL_MAJOR,
1053 .base.minor_version = SPICE_INTERFACE_QXL_MINOR,
1055 .attache_worker = interface_attach_worker,
1056 .set_compression_level = interface_set_compression_level,
1057 .set_mm_time = interface_set_mm_time,
1058 .get_init_info = interface_get_init_info,
1060 /* the callbacks below are called from spice server thread context */
1061 .get_command = interface_get_command,
1062 .req_cmd_notification = interface_req_cmd_notification,
1063 .release_resource = interface_release_resource,
1064 .get_cursor_command = interface_get_cursor_command,
1065 .req_cursor_notification = interface_req_cursor_notification,
1066 .notify_update = interface_notify_update,
1067 .flush_resources = interface_flush_resources,
1068 .async_complete = interface_async_complete,
1069 .update_area_complete = interface_update_area_complete,
1070 #if SPICE_SERVER_VERSION >= 0x000b04
1071 .set_client_capabilities = interface_set_client_capabilities,
1072 #endif
1073 #if SPICE_SERVER_VERSION >= 0x000b05 && \
1074 defined(CONFIG_QXL_CLIENT_MONITORS_CONFIG)
1075 .client_monitors_config = interface_client_monitors_config,
1076 #endif
1079 static void qxl_enter_vga_mode(PCIQXLDevice *d)
1081 if (d->mode == QXL_MODE_VGA) {
1082 return;
1084 trace_qxl_enter_vga_mode(d->id);
1085 qemu_spice_create_host_primary(&d->ssd);
1086 d->mode = QXL_MODE_VGA;
1087 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
1088 vga_dirty_log_start(&d->vga);
1091 static void qxl_exit_vga_mode(PCIQXLDevice *d)
1093 if (d->mode != QXL_MODE_VGA) {
1094 return;
1096 trace_qxl_exit_vga_mode(d->id);
1097 vga_dirty_log_stop(&d->vga);
1098 qxl_destroy_primary(d, QXL_SYNC);
1101 static void qxl_update_irq(PCIQXLDevice *d)
1103 uint32_t pending = le32_to_cpu(d->ram->int_pending);
1104 uint32_t mask = le32_to_cpu(d->ram->int_mask);
1105 int level = !!(pending & mask);
1106 qemu_set_irq(d->pci.irq[0], level);
1107 qxl_ring_set_dirty(d);
1110 static void qxl_check_state(PCIQXLDevice *d)
1112 QXLRam *ram = d->ram;
1113 int spice_display_running = qemu_spice_display_is_running(&d->ssd);
1115 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cmd_ring));
1116 assert(!spice_display_running || SPICE_RING_IS_EMPTY(&ram->cursor_ring));
1119 static void qxl_reset_state(PCIQXLDevice *d)
1121 QXLRom *rom = d->rom;
1123 qxl_check_state(d);
1124 d->shadow_rom.update_id = cpu_to_le32(0);
1125 *rom = d->shadow_rom;
1126 qxl_rom_set_dirty(d);
1127 init_qxl_ram(d);
1128 d->num_free_res = 0;
1129 d->last_release = NULL;
1130 memset(&d->ssd.dirty, 0, sizeof(d->ssd.dirty));
1133 static void qxl_soft_reset(PCIQXLDevice *d)
1135 trace_qxl_soft_reset(d->id);
1136 qxl_check_state(d);
1137 qxl_clear_guest_bug(d);
1138 d->current_async = QXL_UNDEFINED_IO;
1140 if (d->id == 0) {
1141 qxl_enter_vga_mode(d);
1142 } else {
1143 d->mode = QXL_MODE_UNDEFINED;
1147 static void qxl_hard_reset(PCIQXLDevice *d, int loadvm)
1149 trace_qxl_hard_reset(d->id, loadvm);
1151 qxl_spice_reset_cursor(d);
1152 qxl_spice_reset_image_cache(d);
1153 qxl_reset_surfaces(d);
1154 qxl_reset_memslots(d);
1156 /* pre loadvm reset must not touch QXLRam. This lives in
1157 * device memory, is migrated together with RAM and thus
1158 * already loaded at this point */
1159 if (!loadvm) {
1160 qxl_reset_state(d);
1162 qemu_spice_create_host_memslot(&d->ssd);
1163 qxl_soft_reset(d);
1166 static void qxl_reset_handler(DeviceState *dev)
1168 PCIQXLDevice *d = DO_UPCAST(PCIQXLDevice, pci.qdev, dev);
1170 qxl_hard_reset(d, 0);
1173 static void qxl_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1175 VGACommonState *vga = opaque;
1176 PCIQXLDevice *qxl = container_of(vga, PCIQXLDevice, vga);
1178 trace_qxl_io_write_vga(qxl->id, qxl_mode_to_string(qxl->mode), addr, val);
1179 if (qxl->mode != QXL_MODE_VGA) {
1180 qxl_destroy_primary(qxl, QXL_SYNC);
1181 qxl_soft_reset(qxl);
1183 vga_ioport_write(opaque, addr, val);
1186 static const MemoryRegionPortio qxl_vga_portio_list[] = {
1187 { 0x04, 2, 1, .read = vga_ioport_read,
1188 .write = qxl_vga_ioport_write }, /* 3b4 */
1189 { 0x0a, 1, 1, .read = vga_ioport_read,
1190 .write = qxl_vga_ioport_write }, /* 3ba */
1191 { 0x10, 16, 1, .read = vga_ioport_read,
1192 .write = qxl_vga_ioport_write }, /* 3c0 */
1193 { 0x24, 2, 1, .read = vga_ioport_read,
1194 .write = qxl_vga_ioport_write }, /* 3d4 */
1195 { 0x2a, 1, 1, .read = vga_ioport_read,
1196 .write = qxl_vga_ioport_write }, /* 3da */
1197 PORTIO_END_OF_LIST(),
1200 static int qxl_add_memslot(PCIQXLDevice *d, uint32_t slot_id, uint64_t delta,
1201 qxl_async_io async)
1203 static const int regions[] = {
1204 QXL_RAM_RANGE_INDEX,
1205 QXL_VRAM_RANGE_INDEX,
1206 QXL_VRAM64_RANGE_INDEX,
1208 uint64_t guest_start;
1209 uint64_t guest_end;
1210 int pci_region;
1211 pcibus_t pci_start;
1212 pcibus_t pci_end;
1213 intptr_t virt_start;
1214 QXLDevMemSlot memslot;
1215 int i;
1217 guest_start = le64_to_cpu(d->guest_slots[slot_id].slot.mem_start);
1218 guest_end = le64_to_cpu(d->guest_slots[slot_id].slot.mem_end);
1220 trace_qxl_memslot_add_guest(d->id, slot_id, guest_start, guest_end);
1222 if (slot_id >= NUM_MEMSLOTS) {
1223 qxl_set_guest_bug(d, "%s: slot_id >= NUM_MEMSLOTS %d >= %d", __func__,
1224 slot_id, NUM_MEMSLOTS);
1225 return 1;
1227 if (guest_start > guest_end) {
1228 qxl_set_guest_bug(d, "%s: guest_start > guest_end 0x%" PRIx64
1229 " > 0x%" PRIx64, __func__, guest_start, guest_end);
1230 return 1;
1233 for (i = 0; i < ARRAY_SIZE(regions); i++) {
1234 pci_region = regions[i];
1235 pci_start = d->pci.io_regions[pci_region].addr;
1236 pci_end = pci_start + d->pci.io_regions[pci_region].size;
1237 /* mapped? */
1238 if (pci_start == -1) {
1239 continue;
1241 /* start address in range ? */
1242 if (guest_start < pci_start || guest_start > pci_end) {
1243 continue;
1245 /* end address in range ? */
1246 if (guest_end > pci_end) {
1247 continue;
1249 /* passed */
1250 break;
1252 if (i == ARRAY_SIZE(regions)) {
1253 qxl_set_guest_bug(d, "%s: finished loop without match", __func__);
1254 return 1;
1257 switch (pci_region) {
1258 case QXL_RAM_RANGE_INDEX:
1259 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vga.vram);
1260 break;
1261 case QXL_VRAM_RANGE_INDEX:
1262 case 4 /* vram 64bit */:
1263 virt_start = (intptr_t)memory_region_get_ram_ptr(&d->vram_bar);
1264 break;
1265 default:
1266 /* should not happen */
1267 qxl_set_guest_bug(d, "%s: pci_region = %d", __func__, pci_region);
1268 return 1;
1271 memslot.slot_id = slot_id;
1272 memslot.slot_group_id = MEMSLOT_GROUP_GUEST; /* guest group */
1273 memslot.virt_start = virt_start + (guest_start - pci_start);
1274 memslot.virt_end = virt_start + (guest_end - pci_start);
1275 memslot.addr_delta = memslot.virt_start - delta;
1276 memslot.generation = d->rom->slot_generation = 0;
1277 qxl_rom_set_dirty(d);
1279 qemu_spice_add_memslot(&d->ssd, &memslot, async);
1280 d->guest_slots[slot_id].ptr = (void*)memslot.virt_start;
1281 d->guest_slots[slot_id].size = memslot.virt_end - memslot.virt_start;
1282 d->guest_slots[slot_id].delta = delta;
1283 d->guest_slots[slot_id].active = 1;
1284 return 0;
1287 static void qxl_del_memslot(PCIQXLDevice *d, uint32_t slot_id)
1289 qemu_spice_del_memslot(&d->ssd, MEMSLOT_GROUP_HOST, slot_id);
1290 d->guest_slots[slot_id].active = 0;
1293 static void qxl_reset_memslots(PCIQXLDevice *d)
1295 qxl_spice_reset_memslots(d);
1296 memset(&d->guest_slots, 0, sizeof(d->guest_slots));
1299 static void qxl_reset_surfaces(PCIQXLDevice *d)
1301 trace_qxl_reset_surfaces(d->id);
1302 d->mode = QXL_MODE_UNDEFINED;
1303 qxl_spice_destroy_surfaces(d, QXL_SYNC);
1306 /* can be also called from spice server thread context */
1307 void *qxl_phys2virt(PCIQXLDevice *qxl, QXLPHYSICAL pqxl, int group_id)
1309 uint64_t phys = le64_to_cpu(pqxl);
1310 uint32_t slot = (phys >> (64 - 8)) & 0xff;
1311 uint64_t offset = phys & 0xffffffffffff;
1313 switch (group_id) {
1314 case MEMSLOT_GROUP_HOST:
1315 return (void *)(intptr_t)offset;
1316 case MEMSLOT_GROUP_GUEST:
1317 if (slot >= NUM_MEMSLOTS) {
1318 qxl_set_guest_bug(qxl, "slot too large %d >= %d", slot,
1319 NUM_MEMSLOTS);
1320 return NULL;
1322 if (!qxl->guest_slots[slot].active) {
1323 qxl_set_guest_bug(qxl, "inactive slot %d\n", slot);
1324 return NULL;
1326 if (offset < qxl->guest_slots[slot].delta) {
1327 qxl_set_guest_bug(qxl,
1328 "slot %d offset %"PRIu64" < delta %"PRIu64"\n",
1329 slot, offset, qxl->guest_slots[slot].delta);
1330 return NULL;
1332 offset -= qxl->guest_slots[slot].delta;
1333 if (offset > qxl->guest_slots[slot].size) {
1334 qxl_set_guest_bug(qxl,
1335 "slot %d offset %"PRIu64" > size %"PRIu64"\n",
1336 slot, offset, qxl->guest_slots[slot].size);
1337 return NULL;
1339 return qxl->guest_slots[slot].ptr + offset;
1341 return NULL;
1344 static void qxl_create_guest_primary_complete(PCIQXLDevice *qxl)
1346 /* for local rendering */
1347 qxl_render_resize(qxl);
1350 static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm,
1351 qxl_async_io async)
1353 QXLDevSurfaceCreate surface;
1354 QXLSurfaceCreate *sc = &qxl->guest_primary.surface;
1355 int size;
1356 int requested_height = le32_to_cpu(sc->height);
1357 int requested_stride = le32_to_cpu(sc->stride);
1359 size = abs(requested_stride) * requested_height;
1360 if (size > qxl->vgamem_size) {
1361 qxl_set_guest_bug(qxl, "%s: requested primary larger then framebuffer"
1362 " size", __func__);
1363 return;
1366 if (qxl->mode == QXL_MODE_NATIVE) {
1367 qxl_set_guest_bug(qxl, "%s: nop since already in QXL_MODE_NATIVE",
1368 __func__);
1370 qxl_exit_vga_mode(qxl);
1372 surface.format = le32_to_cpu(sc->format);
1373 surface.height = le32_to_cpu(sc->height);
1374 surface.mem = le64_to_cpu(sc->mem);
1375 surface.position = le32_to_cpu(sc->position);
1376 surface.stride = le32_to_cpu(sc->stride);
1377 surface.width = le32_to_cpu(sc->width);
1378 surface.type = le32_to_cpu(sc->type);
1379 surface.flags = le32_to_cpu(sc->flags);
1380 trace_qxl_create_guest_primary(qxl->id, sc->width, sc->height, sc->mem,
1381 sc->format, sc->position);
1382 trace_qxl_create_guest_primary_rest(qxl->id, sc->stride, sc->type,
1383 sc->flags);
1385 surface.mouse_mode = true;
1386 surface.group_id = MEMSLOT_GROUP_GUEST;
1387 if (loadvm) {
1388 surface.flags |= QXL_SURF_FLAG_KEEP_DATA;
1391 qxl->mode = QXL_MODE_NATIVE;
1392 qxl->cmdflags = 0;
1393 qemu_spice_create_primary_surface(&qxl->ssd, 0, &surface, async);
1395 if (async == QXL_SYNC) {
1396 qxl_create_guest_primary_complete(qxl);
1400 /* return 1 if surface destoy was initiated (in QXL_ASYNC case) or
1401 * done (in QXL_SYNC case), 0 otherwise. */
1402 static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async)
1404 if (d->mode == QXL_MODE_UNDEFINED) {
1405 return 0;
1407 trace_qxl_destroy_primary(d->id);
1408 d->mode = QXL_MODE_UNDEFINED;
1409 qemu_spice_destroy_primary_surface(&d->ssd, 0, async);
1410 qxl_spice_reset_cursor(d);
1411 return 1;
1414 static void qxl_set_mode(PCIQXLDevice *d, int modenr, int loadvm)
1416 pcibus_t start = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1417 pcibus_t end = d->pci.io_regions[QXL_RAM_RANGE_INDEX].size + start;
1418 QXLMode *mode = d->modes->modes + modenr;
1419 uint64_t devmem = d->pci.io_regions[QXL_RAM_RANGE_INDEX].addr;
1420 QXLMemSlot slot = {
1421 .mem_start = start,
1422 .mem_end = end
1424 QXLSurfaceCreate surface = {
1425 .width = mode->x_res,
1426 .height = mode->y_res,
1427 .stride = -mode->x_res * 4,
1428 .format = SPICE_SURFACE_FMT_32_xRGB,
1429 .flags = loadvm ? QXL_SURF_FLAG_KEEP_DATA : 0,
1430 .mouse_mode = true,
1431 .mem = devmem + d->shadow_rom.draw_area_offset,
1434 trace_qxl_set_mode(d->id, modenr, mode->x_res, mode->y_res, mode->bits,
1435 devmem);
1436 if (!loadvm) {
1437 qxl_hard_reset(d, 0);
1440 d->guest_slots[0].slot = slot;
1441 assert(qxl_add_memslot(d, 0, devmem, QXL_SYNC) == 0);
1443 d->guest_primary.surface = surface;
1444 qxl_create_guest_primary(d, 0, QXL_SYNC);
1446 d->mode = QXL_MODE_COMPAT;
1447 d->cmdflags = QXL_COMMAND_FLAG_COMPAT;
1448 if (mode->bits == 16) {
1449 d->cmdflags |= QXL_COMMAND_FLAG_COMPAT_16BPP;
1451 d->shadow_rom.mode = cpu_to_le32(modenr);
1452 d->rom->mode = cpu_to_le32(modenr);
1453 qxl_rom_set_dirty(d);
1456 static void ioport_write(void *opaque, target_phys_addr_t addr,
1457 uint64_t val, unsigned size)
1459 PCIQXLDevice *d = opaque;
1460 uint32_t io_port = addr;
1461 qxl_async_io async = QXL_SYNC;
1462 uint32_t orig_io_port = io_port;
1464 if (d->guest_bug && !io_port == QXL_IO_RESET) {
1465 return;
1468 if (d->revision <= QXL_REVISION_STABLE_V10 &&
1469 io_port >= QXL_IO_FLUSH_SURFACES_ASYNC) {
1470 qxl_set_guest_bug(d, "unsupported io %d for revision %d\n",
1471 io_port, d->revision);
1472 return;
1475 switch (io_port) {
1476 case QXL_IO_RESET:
1477 case QXL_IO_SET_MODE:
1478 case QXL_IO_MEMSLOT_ADD:
1479 case QXL_IO_MEMSLOT_DEL:
1480 case QXL_IO_CREATE_PRIMARY:
1481 case QXL_IO_UPDATE_IRQ:
1482 case QXL_IO_LOG:
1483 case QXL_IO_MEMSLOT_ADD_ASYNC:
1484 case QXL_IO_CREATE_PRIMARY_ASYNC:
1485 break;
1486 default:
1487 if (d->mode != QXL_MODE_VGA) {
1488 break;
1490 trace_qxl_io_unexpected_vga_mode(d->id,
1491 addr, val, io_port_to_string(io_port));
1492 /* be nice to buggy guest drivers */
1493 if (io_port >= QXL_IO_UPDATE_AREA_ASYNC &&
1494 io_port < QXL_IO_RANGE_SIZE) {
1495 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1497 return;
1500 /* we change the io_port to avoid ifdeffery in the main switch */
1501 orig_io_port = io_port;
1502 switch (io_port) {
1503 case QXL_IO_UPDATE_AREA_ASYNC:
1504 io_port = QXL_IO_UPDATE_AREA;
1505 goto async_common;
1506 case QXL_IO_MEMSLOT_ADD_ASYNC:
1507 io_port = QXL_IO_MEMSLOT_ADD;
1508 goto async_common;
1509 case QXL_IO_CREATE_PRIMARY_ASYNC:
1510 io_port = QXL_IO_CREATE_PRIMARY;
1511 goto async_common;
1512 case QXL_IO_DESTROY_PRIMARY_ASYNC:
1513 io_port = QXL_IO_DESTROY_PRIMARY;
1514 goto async_common;
1515 case QXL_IO_DESTROY_SURFACE_ASYNC:
1516 io_port = QXL_IO_DESTROY_SURFACE_WAIT;
1517 goto async_common;
1518 case QXL_IO_DESTROY_ALL_SURFACES_ASYNC:
1519 io_port = QXL_IO_DESTROY_ALL_SURFACES;
1520 goto async_common;
1521 case QXL_IO_FLUSH_SURFACES_ASYNC:
1522 case QXL_IO_MONITORS_CONFIG_ASYNC:
1523 async_common:
1524 async = QXL_ASYNC;
1525 qemu_mutex_lock(&d->async_lock);
1526 if (d->current_async != QXL_UNDEFINED_IO) {
1527 qxl_set_guest_bug(d, "%d async started before last (%d) complete",
1528 io_port, d->current_async);
1529 qemu_mutex_unlock(&d->async_lock);
1530 return;
1532 d->current_async = orig_io_port;
1533 qemu_mutex_unlock(&d->async_lock);
1534 break;
1535 default:
1536 break;
1538 trace_qxl_io_write(d->id, qxl_mode_to_string(d->mode), addr, val, size,
1539 async);
1541 switch (io_port) {
1542 case QXL_IO_UPDATE_AREA:
1544 QXLCookie *cookie = NULL;
1545 QXLRect update = d->ram->update_area;
1547 if (d->ram->update_surface > d->ssd.num_surfaces) {
1548 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: invalid surface id %d\n",
1549 d->ram->update_surface);
1550 return;
1552 if (update.left >= update.right || update.top >= update.bottom) {
1553 qxl_set_guest_bug(d,
1554 "QXL_IO_UPDATE_AREA: invalid area (%ux%u)x(%ux%u)\n",
1555 update.left, update.top, update.right, update.bottom);
1556 return;
1559 if (update.left < 0 || update.top < 0 || update.left >= update.right ||
1560 update.top >= update.bottom) {
1561 qxl_set_guest_bug(d, "QXL_IO_UPDATE_AREA: "
1562 "invalid area(%d,%d,%d,%d)\n", update.left,
1563 update.right, update.top, update.bottom);
1564 break;
1566 if (async == QXL_ASYNC) {
1567 cookie = qxl_cookie_new(QXL_COOKIE_TYPE_IO,
1568 QXL_IO_UPDATE_AREA_ASYNC);
1569 cookie->u.area = update;
1571 qxl_spice_update_area(d, d->ram->update_surface,
1572 cookie ? &cookie->u.area : &update,
1573 NULL, 0, 0, async, cookie);
1574 break;
1576 case QXL_IO_NOTIFY_CMD:
1577 qemu_spice_wakeup(&d->ssd);
1578 break;
1579 case QXL_IO_NOTIFY_CURSOR:
1580 qemu_spice_wakeup(&d->ssd);
1581 break;
1582 case QXL_IO_UPDATE_IRQ:
1583 qxl_update_irq(d);
1584 break;
1585 case QXL_IO_NOTIFY_OOM:
1586 if (!SPICE_RING_IS_EMPTY(&d->ram->release_ring)) {
1587 break;
1589 d->oom_running = 1;
1590 qxl_spice_oom(d);
1591 d->oom_running = 0;
1592 break;
1593 case QXL_IO_SET_MODE:
1594 qxl_set_mode(d, val, 0);
1595 break;
1596 case QXL_IO_LOG:
1597 trace_qxl_io_log(d->id, d->ram->log_buf);
1598 if (d->guestdebug) {
1599 fprintf(stderr, "qxl/guest-%d: %" PRId64 ": %s", d->id,
1600 qemu_get_clock_ns(vm_clock), d->ram->log_buf);
1602 break;
1603 case QXL_IO_RESET:
1604 qxl_hard_reset(d, 0);
1605 break;
1606 case QXL_IO_MEMSLOT_ADD:
1607 if (val >= NUM_MEMSLOTS) {
1608 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_ADD: val out of range");
1609 break;
1611 if (d->guest_slots[val].active) {
1612 qxl_set_guest_bug(d,
1613 "QXL_IO_MEMSLOT_ADD: memory slot already active");
1614 break;
1616 d->guest_slots[val].slot = d->ram->mem_slot;
1617 qxl_add_memslot(d, val, 0, async);
1618 break;
1619 case QXL_IO_MEMSLOT_DEL:
1620 if (val >= NUM_MEMSLOTS) {
1621 qxl_set_guest_bug(d, "QXL_IO_MEMSLOT_DEL: val out of range");
1622 break;
1624 qxl_del_memslot(d, val);
1625 break;
1626 case QXL_IO_CREATE_PRIMARY:
1627 if (val != 0) {
1628 qxl_set_guest_bug(d, "QXL_IO_CREATE_PRIMARY (async=%d): val != 0",
1629 async);
1630 goto cancel_async;
1632 d->guest_primary.surface = d->ram->create_surface;
1633 qxl_create_guest_primary(d, 0, async);
1634 break;
1635 case QXL_IO_DESTROY_PRIMARY:
1636 if (val != 0) {
1637 qxl_set_guest_bug(d, "QXL_IO_DESTROY_PRIMARY (async=%d): val != 0",
1638 async);
1639 goto cancel_async;
1641 if (!qxl_destroy_primary(d, async)) {
1642 trace_qxl_io_destroy_primary_ignored(d->id,
1643 qxl_mode_to_string(d->mode));
1644 goto cancel_async;
1646 break;
1647 case QXL_IO_DESTROY_SURFACE_WAIT:
1648 if (val >= d->ssd.num_surfaces) {
1649 qxl_set_guest_bug(d, "QXL_IO_DESTROY_SURFACE (async=%d):"
1650 "%" PRIu64 " >= NUM_SURFACES", async, val);
1651 goto cancel_async;
1653 qxl_spice_destroy_surface_wait(d, val, async);
1654 break;
1655 case QXL_IO_FLUSH_RELEASE: {
1656 QXLReleaseRing *ring = &d->ram->release_ring;
1657 if (ring->prod - ring->cons + 1 == ring->num_items) {
1658 fprintf(stderr,
1659 "ERROR: no flush, full release ring [p%d,%dc]\n",
1660 ring->prod, ring->cons);
1662 qxl_push_free_res(d, 1 /* flush */);
1663 break;
1665 case QXL_IO_FLUSH_SURFACES_ASYNC:
1666 qxl_spice_flush_surfaces_async(d);
1667 break;
1668 case QXL_IO_DESTROY_ALL_SURFACES:
1669 d->mode = QXL_MODE_UNDEFINED;
1670 qxl_spice_destroy_surfaces(d, async);
1671 break;
1672 case QXL_IO_MONITORS_CONFIG_ASYNC:
1673 qxl_spice_monitors_config_async(d, 0);
1674 break;
1675 default:
1676 qxl_set_guest_bug(d, "%s: unexpected ioport=0x%x\n", __func__, io_port);
1678 return;
1679 cancel_async:
1680 if (async) {
1681 qxl_send_events(d, QXL_INTERRUPT_IO_CMD);
1682 qemu_mutex_lock(&d->async_lock);
1683 d->current_async = QXL_UNDEFINED_IO;
1684 qemu_mutex_unlock(&d->async_lock);
1688 static uint64_t ioport_read(void *opaque, target_phys_addr_t addr,
1689 unsigned size)
1691 PCIQXLDevice *qxl = opaque;
1693 trace_qxl_io_read_unexpected(qxl->id);
1694 return 0xff;
1697 static const MemoryRegionOps qxl_io_ops = {
1698 .read = ioport_read,
1699 .write = ioport_write,
1700 .valid = {
1701 .min_access_size = 1,
1702 .max_access_size = 1,
1706 static void pipe_read(void *opaque)
1708 PCIQXLDevice *d = opaque;
1709 char dummy;
1710 int len;
1712 do {
1713 len = read(d->pipe[0], &dummy, sizeof(dummy));
1714 } while (len == sizeof(dummy));
1715 qxl_update_irq(d);
1718 static void qxl_send_events(PCIQXLDevice *d, uint32_t events)
1720 uint32_t old_pending;
1721 uint32_t le_events = cpu_to_le32(events);
1723 trace_qxl_send_events(d->id, events);
1724 assert(qemu_spice_display_is_running(&d->ssd));
1725 old_pending = __sync_fetch_and_or(&d->ram->int_pending, le_events);
1726 if ((old_pending & le_events) == le_events) {
1727 return;
1729 if (qemu_thread_is_self(&d->main)) {
1730 qxl_update_irq(d);
1731 } else {
1732 if (write(d->pipe[1], d, 1) != 1) {
1733 dprint(d, 1, "%s: write to pipe failed\n", __func__);
1738 static void init_pipe_signaling(PCIQXLDevice *d)
1740 if (pipe(d->pipe) < 0) {
1741 fprintf(stderr, "%s:%s: qxl pipe creation failed\n",
1742 __FILE__, __func__);
1743 exit(1);
1745 fcntl(d->pipe[0], F_SETFL, O_NONBLOCK);
1746 fcntl(d->pipe[1], F_SETFL, O_NONBLOCK);
1747 fcntl(d->pipe[0], F_SETOWN, getpid());
1749 qemu_thread_get_self(&d->main);
1750 qemu_set_fd_handler(d->pipe[0], pipe_read, NULL, d);
1753 /* graphics console */
1755 static void qxl_hw_update(void *opaque)
1757 PCIQXLDevice *qxl = opaque;
1758 VGACommonState *vga = &qxl->vga;
1760 switch (qxl->mode) {
1761 case QXL_MODE_VGA:
1762 vga->update(vga);
1763 break;
1764 case QXL_MODE_COMPAT:
1765 case QXL_MODE_NATIVE:
1766 qxl_render_update(qxl);
1767 break;
1768 default:
1769 break;
1773 static void qxl_hw_invalidate(void *opaque)
1775 PCIQXLDevice *qxl = opaque;
1776 VGACommonState *vga = &qxl->vga;
1778 vga->invalidate(vga);
1781 static void qxl_hw_screen_dump(void *opaque, const char *filename, bool cswitch,
1782 Error **errp)
1784 PCIQXLDevice *qxl = opaque;
1785 VGACommonState *vga = &qxl->vga;
1787 switch (qxl->mode) {
1788 case QXL_MODE_COMPAT:
1789 case QXL_MODE_NATIVE:
1790 qxl_render_update(qxl);
1791 ppm_save(filename, qxl->ssd.ds->surface, errp);
1792 break;
1793 case QXL_MODE_VGA:
1794 vga->screen_dump(vga, filename, cswitch, errp);
1795 break;
1796 default:
1797 break;
1801 static void qxl_hw_text_update(void *opaque, console_ch_t *chardata)
1803 PCIQXLDevice *qxl = opaque;
1804 VGACommonState *vga = &qxl->vga;
1806 if (qxl->mode == QXL_MODE_VGA) {
1807 vga->text_update(vga, chardata);
1808 return;
1812 static void qxl_dirty_surfaces(PCIQXLDevice *qxl)
1814 intptr_t vram_start;
1815 int i;
1817 if (qxl->mode != QXL_MODE_NATIVE && qxl->mode != QXL_MODE_COMPAT) {
1818 return;
1821 /* dirty the primary surface */
1822 qxl_set_dirty(&qxl->vga.vram, qxl->shadow_rom.draw_area_offset,
1823 qxl->shadow_rom.surface0_area_size);
1825 vram_start = (intptr_t)memory_region_get_ram_ptr(&qxl->vram_bar);
1827 /* dirty the off-screen surfaces */
1828 for (i = 0; i < qxl->ssd.num_surfaces; i++) {
1829 QXLSurfaceCmd *cmd;
1830 intptr_t surface_offset;
1831 int surface_size;
1833 if (qxl->guest_surfaces.cmds[i] == 0) {
1834 continue;
1837 cmd = qxl_phys2virt(qxl, qxl->guest_surfaces.cmds[i],
1838 MEMSLOT_GROUP_GUEST);
1839 assert(cmd);
1840 assert(cmd->type == QXL_SURFACE_CMD_CREATE);
1841 surface_offset = (intptr_t)qxl_phys2virt(qxl,
1842 cmd->u.surface_create.data,
1843 MEMSLOT_GROUP_GUEST);
1844 assert(surface_offset);
1845 surface_offset -= vram_start;
1846 surface_size = cmd->u.surface_create.height *
1847 abs(cmd->u.surface_create.stride);
1848 trace_qxl_surfaces_dirty(qxl->id, i, (int)surface_offset, surface_size);
1849 qxl_set_dirty(&qxl->vram_bar, surface_offset, surface_size);
1853 static void qxl_vm_change_state_handler(void *opaque, int running,
1854 RunState state)
1856 PCIQXLDevice *qxl = opaque;
1857 qemu_spice_vm_change_state_handler(&qxl->ssd, running, state);
1859 if (running) {
1861 * if qxl_send_events was called from spice server context before
1862 * migration ended, qxl_update_irq for these events might not have been
1863 * called
1865 qxl_update_irq(qxl);
1866 } else {
1867 /* make sure surfaces are saved before migration */
1868 qxl_dirty_surfaces(qxl);
1872 /* display change listener */
1874 static void display_update(struct DisplayState *ds, int x, int y, int w, int h)
1876 if (qxl0->mode == QXL_MODE_VGA) {
1877 qemu_spice_display_update(&qxl0->ssd, x, y, w, h);
1881 static void display_resize(struct DisplayState *ds)
1883 if (qxl0->mode == QXL_MODE_VGA) {
1884 qemu_spice_display_resize(&qxl0->ssd);
1888 static void display_refresh(struct DisplayState *ds)
1890 if (qxl0->mode == QXL_MODE_VGA) {
1891 qemu_spice_display_refresh(&qxl0->ssd);
1892 } else {
1893 qemu_mutex_lock(&qxl0->ssd.lock);
1894 qemu_spice_cursor_refresh_unlocked(&qxl0->ssd);
1895 qemu_mutex_unlock(&qxl0->ssd.lock);
1899 static DisplayChangeListener display_listener = {
1900 .dpy_update = display_update,
1901 .dpy_resize = display_resize,
1902 .dpy_refresh = display_refresh,
1905 static void qxl_init_ramsize(PCIQXLDevice *qxl)
1907 /* vga mode framebuffer / primary surface (bar 0, first part) */
1908 if (qxl->vgamem_size_mb < 8) {
1909 qxl->vgamem_size_mb = 8;
1911 qxl->vgamem_size = qxl->vgamem_size_mb * 1024 * 1024;
1913 /* vga ram (bar 0, total) */
1914 if (qxl->ram_size_mb != -1) {
1915 qxl->vga.vram_size = qxl->ram_size_mb * 1024 * 1024;
1917 if (qxl->vga.vram_size < qxl->vgamem_size * 2) {
1918 qxl->vga.vram_size = qxl->vgamem_size * 2;
1921 /* vram32 (surfaces, 32bit, bar 1) */
1922 if (qxl->vram32_size_mb != -1) {
1923 qxl->vram32_size = qxl->vram32_size_mb * 1024 * 1024;
1925 if (qxl->vram32_size < 4096) {
1926 qxl->vram32_size = 4096;
1929 /* vram (surfaces, 64bit, bar 4+5) */
1930 if (qxl->vram_size_mb != -1) {
1931 qxl->vram_size = qxl->vram_size_mb * 1024 * 1024;
1933 if (qxl->vram_size < qxl->vram32_size) {
1934 qxl->vram_size = qxl->vram32_size;
1937 if (qxl->revision == 1) {
1938 qxl->vram32_size = 4096;
1939 qxl->vram_size = 4096;
1941 qxl->vgamem_size = msb_mask(qxl->vgamem_size * 2 - 1);
1942 qxl->vga.vram_size = msb_mask(qxl->vga.vram_size * 2 - 1);
1943 qxl->vram32_size = msb_mask(qxl->vram32_size * 2 - 1);
1944 qxl->vram_size = msb_mask(qxl->vram_size * 2 - 1);
1947 static int qxl_init_common(PCIQXLDevice *qxl)
1949 uint8_t* config = qxl->pci.config;
1950 uint32_t pci_device_rev;
1951 uint32_t io_size;
1953 qxl->mode = QXL_MODE_UNDEFINED;
1954 qxl->generation = 1;
1955 qxl->num_memslots = NUM_MEMSLOTS;
1956 qemu_mutex_init(&qxl->track_lock);
1957 qemu_mutex_init(&qxl->async_lock);
1958 qxl->current_async = QXL_UNDEFINED_IO;
1959 qxl->guest_bug = 0;
1961 switch (qxl->revision) {
1962 case 1: /* spice 0.4 -- qxl-1 */
1963 pci_device_rev = QXL_REVISION_STABLE_V04;
1964 io_size = 8;
1965 break;
1966 case 2: /* spice 0.6 -- qxl-2 */
1967 pci_device_rev = QXL_REVISION_STABLE_V06;
1968 io_size = 16;
1969 break;
1970 case 3: /* qxl-3 */
1971 pci_device_rev = QXL_REVISION_STABLE_V10;
1972 io_size = 32; /* PCI region size must be pow2 */
1973 break;
1974 /* 0x000b01 == 0.11.1 */
1975 #if SPICE_SERVER_VERSION >= 0x000b01 && \
1976 defined(CONFIG_QXL_IO_MONITORS_CONFIG_ASYNC)
1977 case 4: /* qxl-4 */
1978 pci_device_rev = QXL_REVISION_STABLE_V12;
1979 io_size = msb_mask(QXL_IO_RANGE_SIZE * 2 - 1);
1980 break;
1981 #endif
1982 default:
1983 error_report("Invalid revision %d for qxl device (max %d)",
1984 qxl->revision, QXL_DEFAULT_REVISION);
1985 return -1;
1988 pci_set_byte(&config[PCI_REVISION_ID], pci_device_rev);
1989 pci_set_byte(&config[PCI_INTERRUPT_PIN], 1);
1991 qxl->rom_size = qxl_rom_size();
1992 memory_region_init_ram(&qxl->rom_bar, "qxl.vrom", qxl->rom_size);
1993 vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev);
1994 init_qxl_rom(qxl);
1995 init_qxl_ram(qxl);
1997 qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces);
1998 memory_region_init_ram(&qxl->vram_bar, "qxl.vram", qxl->vram_size);
1999 vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev);
2000 memory_region_init_alias(&qxl->vram32_bar, "qxl.vram32", &qxl->vram_bar,
2001 0, qxl->vram32_size);
2003 memory_region_init_io(&qxl->io_bar, &qxl_io_ops, qxl,
2004 "qxl-ioports", io_size);
2005 if (qxl->id == 0) {
2006 vga_dirty_log_start(&qxl->vga);
2008 memory_region_set_flush_coalesced(&qxl->io_bar);
2011 pci_register_bar(&qxl->pci, QXL_IO_RANGE_INDEX,
2012 PCI_BASE_ADDRESS_SPACE_IO, &qxl->io_bar);
2014 pci_register_bar(&qxl->pci, QXL_ROM_RANGE_INDEX,
2015 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->rom_bar);
2017 pci_register_bar(&qxl->pci, QXL_RAM_RANGE_INDEX,
2018 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vga.vram);
2020 pci_register_bar(&qxl->pci, QXL_VRAM_RANGE_INDEX,
2021 PCI_BASE_ADDRESS_SPACE_MEMORY, &qxl->vram32_bar);
2023 if (qxl->vram32_size < qxl->vram_size) {
2025 * Make the 64bit vram bar show up only in case it is
2026 * configured to be larger than the 32bit vram bar.
2028 pci_register_bar(&qxl->pci, QXL_VRAM64_RANGE_INDEX,
2029 PCI_BASE_ADDRESS_SPACE_MEMORY |
2030 PCI_BASE_ADDRESS_MEM_TYPE_64 |
2031 PCI_BASE_ADDRESS_MEM_PREFETCH,
2032 &qxl->vram_bar);
2035 /* print pci bar details */
2036 dprint(qxl, 1, "ram/%s: %d MB [region 0]\n",
2037 qxl->id == 0 ? "pri" : "sec",
2038 qxl->vga.vram_size / (1024*1024));
2039 dprint(qxl, 1, "vram/32: %d MB [region 1]\n",
2040 qxl->vram32_size / (1024*1024));
2041 dprint(qxl, 1, "vram/64: %d MB %s\n",
2042 qxl->vram_size / (1024*1024),
2043 qxl->vram32_size < qxl->vram_size ? "[region 4]" : "[unmapped]");
2045 qxl->ssd.qxl.base.sif = &qxl_interface.base;
2046 qxl->ssd.qxl.id = qxl->id;
2047 qemu_spice_add_interface(&qxl->ssd.qxl.base);
2048 qemu_add_vm_change_state_handler(qxl_vm_change_state_handler, qxl);
2050 init_pipe_signaling(qxl);
2051 qxl_reset_state(qxl);
2053 qxl->update_area_bh = qemu_bh_new(qxl_render_update_area_bh, qxl);
2055 return 0;
2058 static int qxl_init_primary(PCIDevice *dev)
2060 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
2061 VGACommonState *vga = &qxl->vga;
2062 PortioList *qxl_vga_port_list = g_new(PortioList, 1);
2064 qxl->id = 0;
2065 qxl_init_ramsize(qxl);
2066 vga->vram_size_mb = qxl->vga.vram_size >> 20;
2067 vga_common_init(vga);
2068 vga_init(vga, pci_address_space(dev), pci_address_space_io(dev), false);
2069 portio_list_init(qxl_vga_port_list, qxl_vga_portio_list, vga, "vga");
2070 portio_list_add(qxl_vga_port_list, pci_address_space_io(dev), 0x3b0);
2072 vga->ds = graphic_console_init(qxl_hw_update, qxl_hw_invalidate,
2073 qxl_hw_screen_dump, qxl_hw_text_update, qxl);
2074 qemu_spice_display_init_common(&qxl->ssd, vga->ds);
2076 qxl0 = qxl;
2077 register_displaychangelistener(vga->ds, &display_listener);
2079 return qxl_init_common(qxl);
2082 static int qxl_init_secondary(PCIDevice *dev)
2084 static int device_id = 1;
2085 PCIQXLDevice *qxl = DO_UPCAST(PCIQXLDevice, pci, dev);
2087 qxl->id = device_id++;
2088 qxl_init_ramsize(qxl);
2089 memory_region_init_ram(&qxl->vga.vram, "qxl.vgavram", qxl->vga.vram_size);
2090 vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev);
2091 qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram);
2093 return qxl_init_common(qxl);
2096 static void qxl_pre_save(void *opaque)
2098 PCIQXLDevice* d = opaque;
2099 uint8_t *ram_start = d->vga.vram_ptr;
2101 trace_qxl_pre_save(d->id);
2102 if (d->last_release == NULL) {
2103 d->last_release_offset = 0;
2104 } else {
2105 d->last_release_offset = (uint8_t *)d->last_release - ram_start;
2107 assert(d->last_release_offset < d->vga.vram_size);
2110 static int qxl_pre_load(void *opaque)
2112 PCIQXLDevice* d = opaque;
2114 trace_qxl_pre_load(d->id);
2115 qxl_hard_reset(d, 1);
2116 qxl_exit_vga_mode(d);
2117 return 0;
2120 static void qxl_create_memslots(PCIQXLDevice *d)
2122 int i;
2124 for (i = 0; i < NUM_MEMSLOTS; i++) {
2125 if (!d->guest_slots[i].active) {
2126 continue;
2128 qxl_add_memslot(d, i, 0, QXL_SYNC);
2132 static int qxl_post_load(void *opaque, int version)
2134 PCIQXLDevice* d = opaque;
2135 uint8_t *ram_start = d->vga.vram_ptr;
2136 QXLCommandExt *cmds;
2137 int in, out, newmode;
2139 assert(d->last_release_offset < d->vga.vram_size);
2140 if (d->last_release_offset == 0) {
2141 d->last_release = NULL;
2142 } else {
2143 d->last_release = (QXLReleaseInfo *)(ram_start + d->last_release_offset);
2146 d->modes = (QXLModes*)((uint8_t*)d->rom + d->rom->modes_offset);
2148 trace_qxl_post_load(d->id, qxl_mode_to_string(d->mode));
2149 newmode = d->mode;
2150 d->mode = QXL_MODE_UNDEFINED;
2152 switch (newmode) {
2153 case QXL_MODE_UNDEFINED:
2154 break;
2155 case QXL_MODE_VGA:
2156 qxl_create_memslots(d);
2157 qxl_enter_vga_mode(d);
2158 break;
2159 case QXL_MODE_NATIVE:
2160 qxl_create_memslots(d);
2161 qxl_create_guest_primary(d, 1, QXL_SYNC);
2163 /* replay surface-create and cursor-set commands */
2164 cmds = g_malloc0(sizeof(QXLCommandExt) * (d->ssd.num_surfaces + 1));
2165 for (in = 0, out = 0; in < d->ssd.num_surfaces; in++) {
2166 if (d->guest_surfaces.cmds[in] == 0) {
2167 continue;
2169 cmds[out].cmd.data = d->guest_surfaces.cmds[in];
2170 cmds[out].cmd.type = QXL_CMD_SURFACE;
2171 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2172 out++;
2174 if (d->guest_cursor) {
2175 cmds[out].cmd.data = d->guest_cursor;
2176 cmds[out].cmd.type = QXL_CMD_CURSOR;
2177 cmds[out].group_id = MEMSLOT_GROUP_GUEST;
2178 out++;
2180 qxl_spice_loadvm_commands(d, cmds, out);
2181 g_free(cmds);
2182 if (d->guest_monitors_config) {
2183 qxl_spice_monitors_config_async(d, 1);
2185 break;
2186 case QXL_MODE_COMPAT:
2187 /* note: no need to call qxl_create_memslots, qxl_set_mode
2188 * creates the mem slot. */
2189 qxl_set_mode(d, d->shadow_rom.mode, 1);
2190 break;
2192 return 0;
2195 #define QXL_SAVE_VERSION 21
2197 static bool qxl_monitors_config_needed(void *opaque)
2199 PCIQXLDevice *qxl = opaque;
2201 return qxl->guest_monitors_config != 0;
2205 static VMStateDescription qxl_memslot = {
2206 .name = "qxl-memslot",
2207 .version_id = QXL_SAVE_VERSION,
2208 .minimum_version_id = QXL_SAVE_VERSION,
2209 .fields = (VMStateField[]) {
2210 VMSTATE_UINT64(slot.mem_start, struct guest_slots),
2211 VMSTATE_UINT64(slot.mem_end, struct guest_slots),
2212 VMSTATE_UINT32(active, struct guest_slots),
2213 VMSTATE_END_OF_LIST()
2217 static VMStateDescription qxl_surface = {
2218 .name = "qxl-surface",
2219 .version_id = QXL_SAVE_VERSION,
2220 .minimum_version_id = QXL_SAVE_VERSION,
2221 .fields = (VMStateField[]) {
2222 VMSTATE_UINT32(width, QXLSurfaceCreate),
2223 VMSTATE_UINT32(height, QXLSurfaceCreate),
2224 VMSTATE_INT32(stride, QXLSurfaceCreate),
2225 VMSTATE_UINT32(format, QXLSurfaceCreate),
2226 VMSTATE_UINT32(position, QXLSurfaceCreate),
2227 VMSTATE_UINT32(mouse_mode, QXLSurfaceCreate),
2228 VMSTATE_UINT32(flags, QXLSurfaceCreate),
2229 VMSTATE_UINT32(type, QXLSurfaceCreate),
2230 VMSTATE_UINT64(mem, QXLSurfaceCreate),
2231 VMSTATE_END_OF_LIST()
2235 static VMStateDescription qxl_vmstate_monitors_config = {
2236 .name = "qxl/monitors-config",
2237 .version_id = 1,
2238 .minimum_version_id = 1,
2239 .fields = (VMStateField[]) {
2240 VMSTATE_UINT64(guest_monitors_config, PCIQXLDevice),
2241 VMSTATE_END_OF_LIST()
2245 static VMStateDescription qxl_vmstate = {
2246 .name = "qxl",
2247 .version_id = QXL_SAVE_VERSION,
2248 .minimum_version_id = QXL_SAVE_VERSION,
2249 .pre_save = qxl_pre_save,
2250 .pre_load = qxl_pre_load,
2251 .post_load = qxl_post_load,
2252 .fields = (VMStateField[]) {
2253 VMSTATE_PCI_DEVICE(pci, PCIQXLDevice),
2254 VMSTATE_STRUCT(vga, PCIQXLDevice, 0, vmstate_vga_common, VGACommonState),
2255 VMSTATE_UINT32(shadow_rom.mode, PCIQXLDevice),
2256 VMSTATE_UINT32(num_free_res, PCIQXLDevice),
2257 VMSTATE_UINT32(last_release_offset, PCIQXLDevice),
2258 VMSTATE_UINT32(mode, PCIQXLDevice),
2259 VMSTATE_UINT32(ssd.unique, PCIQXLDevice),
2260 VMSTATE_INT32_EQUAL(num_memslots, PCIQXLDevice),
2261 VMSTATE_STRUCT_ARRAY(guest_slots, PCIQXLDevice, NUM_MEMSLOTS, 0,
2262 qxl_memslot, struct guest_slots),
2263 VMSTATE_STRUCT(guest_primary.surface, PCIQXLDevice, 0,
2264 qxl_surface, QXLSurfaceCreate),
2265 VMSTATE_INT32_EQUAL(ssd.num_surfaces, PCIQXLDevice),
2266 VMSTATE_VARRAY_INT32(guest_surfaces.cmds, PCIQXLDevice,
2267 ssd.num_surfaces, 0,
2268 vmstate_info_uint64, uint64_t),
2269 VMSTATE_UINT64(guest_cursor, PCIQXLDevice),
2270 VMSTATE_END_OF_LIST()
2272 .subsections = (VMStateSubsection[]) {
2274 .vmsd = &qxl_vmstate_monitors_config,
2275 .needed = qxl_monitors_config_needed,
2276 }, {
2277 /* empty */
2282 static Property qxl_properties[] = {
2283 DEFINE_PROP_UINT32("ram_size", PCIQXLDevice, vga.vram_size,
2284 64 * 1024 * 1024),
2285 DEFINE_PROP_UINT32("vram_size", PCIQXLDevice, vram32_size,
2286 64 * 1024 * 1024),
2287 DEFINE_PROP_UINT32("revision", PCIQXLDevice, revision,
2288 QXL_DEFAULT_REVISION),
2289 DEFINE_PROP_UINT32("debug", PCIQXLDevice, debug, 0),
2290 DEFINE_PROP_UINT32("guestdebug", PCIQXLDevice, guestdebug, 0),
2291 DEFINE_PROP_UINT32("cmdlog", PCIQXLDevice, cmdlog, 0),
2292 DEFINE_PROP_UINT32("ram_size_mb", PCIQXLDevice, ram_size_mb, -1),
2293 DEFINE_PROP_UINT32("vram_size_mb", PCIQXLDevice, vram32_size_mb, -1),
2294 DEFINE_PROP_UINT32("vram64_size_mb", PCIQXLDevice, vram_size_mb, -1),
2295 DEFINE_PROP_UINT32("vgamem_mb", PCIQXLDevice, vgamem_size_mb, 16),
2296 DEFINE_PROP_INT32("surfaces", PCIQXLDevice, ssd.num_surfaces, 1024),
2297 DEFINE_PROP_END_OF_LIST(),
2300 static void qxl_primary_class_init(ObjectClass *klass, void *data)
2302 DeviceClass *dc = DEVICE_CLASS(klass);
2303 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2305 k->no_hotplug = 1;
2306 k->init = qxl_init_primary;
2307 k->romfile = "vgabios-qxl.bin";
2308 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2309 k->device_id = QXL_DEVICE_ID_STABLE;
2310 k->class_id = PCI_CLASS_DISPLAY_VGA;
2311 dc->desc = "Spice QXL GPU (primary, vga compatible)";
2312 dc->reset = qxl_reset_handler;
2313 dc->vmsd = &qxl_vmstate;
2314 dc->props = qxl_properties;
2317 static TypeInfo qxl_primary_info = {
2318 .name = "qxl-vga",
2319 .parent = TYPE_PCI_DEVICE,
2320 .instance_size = sizeof(PCIQXLDevice),
2321 .class_init = qxl_primary_class_init,
2324 static void qxl_secondary_class_init(ObjectClass *klass, void *data)
2326 DeviceClass *dc = DEVICE_CLASS(klass);
2327 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
2329 k->init = qxl_init_secondary;
2330 k->vendor_id = REDHAT_PCI_VENDOR_ID;
2331 k->device_id = QXL_DEVICE_ID_STABLE;
2332 k->class_id = PCI_CLASS_DISPLAY_OTHER;
2333 dc->desc = "Spice QXL GPU (secondary)";
2334 dc->reset = qxl_reset_handler;
2335 dc->vmsd = &qxl_vmstate;
2336 dc->props = qxl_properties;
2339 static TypeInfo qxl_secondary_info = {
2340 .name = "qxl",
2341 .parent = TYPE_PCI_DEVICE,
2342 .instance_size = sizeof(PCIQXLDevice),
2343 .class_init = qxl_secondary_class_init,
2346 static void qxl_register_types(void)
2348 type_register_static(&qxl_primary_info);
2349 type_register_static(&qxl_secondary_info);
2352 type_init(qxl_register_types)