hw/ppc_prep.c

   1 /*
   2  * QEMU PPC PREP hardware System Emulator
   3  *
   4  * Copyright (c) 2003-2007 Jocelyn Mayer
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "nvram.h"
  26 #include "pc.h"
  27 #include "fdc.h"
  28 #include "net.h"
  29 #include "sysemu.h"
  30 #include "isa.h"
  31 #include "pci.h"
  32 #include "pci_host.h"
  33 #include "ppc.h"
  34 #include "boards.h"
  35 #include "qemu-log.h"
  36 #include "ide.h"
  37 #include "loader.h"
  38 #include "mc146818rtc.h"
  39 #include "blockdev.h"
  40 #include "arch_init.h"
  41 #include "exec-memory.h"
  42
  43 //#define HARD_DEBUG_PPC_IO
  44 //#define DEBUG_PPC_IO
  45
  46 /* SMP is not enabled, for now */
  47 #define MAX_CPUS 1
  48
  49 #define MAX_IDE_BUS 2
  50
  51 #define BIOS_SIZE (1024 * 1024)
  52 #define BIOS_FILENAME "ppc_rom.bin"
  53 #define KERNEL_LOAD_ADDR 0x01000000
  54 #define INITRD_LOAD_ADDR 0x01800000
  55
  56 #if defined (HARD_DEBUG_PPC_IO) && !defined (DEBUG_PPC_IO)
  57 #define DEBUG_PPC_IO
  58 #endif
  59
  60 #if defined (HARD_DEBUG_PPC_IO)
  61 #define PPC_IO_DPRINTF(fmt, ...)                         \
  62 do {                                                     \
  63     if (qemu_loglevel_mask(CPU_LOG_IOPORT)) {            \
  64         qemu_log("%s: " fmt, __func__ , ## __VA_ARGS__); \
  65     } else {                                             \
  66         printf("%s : " fmt, __func__ , ## __VA_ARGS__);  \
  67     }                                                    \
  68 } while (0)
  69 #elif defined (DEBUG_PPC_IO)
  70 #define PPC_IO_DPRINTF(fmt, ...) \
  71 qemu_log_mask(CPU_LOG_IOPORT, fmt, ## __VA_ARGS__)
  72 #else
  73 #define PPC_IO_DPRINTF(fmt, ...) do { } while (0)
  74 #endif
  75
  76 /* Constants for devices init */
  77 static const int ide_iobase[2] = { 0x1f0, 0x170 };
  78 static const int ide_iobase2[2] = { 0x3f6, 0x376 };
  79 static const int ide_irq[2] = { 13, 13 };
  80
  81 #define NE2000_NB_MAX 6
  82
  83 static uint32_t ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360, 0x280, 0x380 };
  84 static int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
  85
  86 /* ISA IO ports bridge */
  87 #define PPC_IO_BASE 0x80000000
  88
  89 /* PowerPC control and status registers */
  90 #if 0 // Not used
  91 static struct {
  92     /* IDs */
  93     uint32_t veni_devi;
  94     uint32_t revi;
  95     /* Control and status */
  96     uint32_t gcsr;
  97     uint32_t xcfr;
  98     uint32_t ct32;
  99     uint32_t mcsr;
 100     /* General purpose registers */
 101     uint32_t gprg[6];
 102     /* Exceptions */
 103     uint32_t feen;
 104     uint32_t fest;
 105     uint32_t fema;
 106     uint32_t fecl;
 107     uint32_t eeen;
 108     uint32_t eest;
 109     uint32_t eecl;
 110     uint32_t eeint;
 111     uint32_t eemck0;
 112     uint32_t eemck1;
 113     /* Error diagnostic */
 114 } XCSR;
 115
 116 static void PPC_XCSR_writeb (void *opaque,
 117                              target_phys_addr_t addr, uint32_t value)
 118 {
 119     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 120            value);
 121 }
 122
 123 static void PPC_XCSR_writew (void *opaque,
 124                              target_phys_addr_t addr, uint32_t value)
 125 {
 126     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 127            value);
 128 }
 129
 130 static void PPC_XCSR_writel (void *opaque,
 131                              target_phys_addr_t addr, uint32_t value)
 132 {
 133     printf("%s: 0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", __func__, addr,
 134            value);
 135 }
 136
 137 static uint32_t PPC_XCSR_readb (void *opaque, target_phys_addr_t addr)
 138 {
 139     uint32_t retval = 0;
 140
 141     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 142            retval);
 143
 144     return retval;
 145 }
 146
 147 static uint32_t PPC_XCSR_readw (void *opaque, target_phys_addr_t addr)
 148 {
 149     uint32_t retval = 0;
 150
 151     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 152            retval);
 153
 154     return retval;
 155 }
 156
 157 static uint32_t PPC_XCSR_readl (void *opaque, target_phys_addr_t addr)
 158 {
 159     uint32_t retval = 0;
 160
 161     printf("%s: 0x" TARGET_FMT_plx " <= %08" PRIx32 "\n", __func__, addr,
 162            retval);
 163
 164     return retval;
 165 }
 166
 167 static const MemoryRegionOps PPC_XCSR_ops = {
 168     .old_mmio = {
 169         .read = { PPC_XCSR_readb, PPC_XCSR_readw, PPC_XCSR_readl, },
 170         .write = { PPC_XCSR_writeb, PPC_XCSR_writew, PPC_XCSR_writel, },
 171     },
 172     .endianness = DEVICE_LITTLE_ENDIAN,
 173 };
 174
 175 #endif
 176
 177 /* Fake super-io ports for PREP platform (Intel 82378ZB) */
 178 typedef struct sysctrl_t {
 179     qemu_irq reset_irq;
 180     M48t59State *nvram;
 181     uint8_t state;
 182     uint8_t syscontrol;
 183     uint8_t fake_io[2];
 184     int contiguous_map;
 185     int endian;
 186 } sysctrl_t;
 187
 188 enum {
 189     STATE_HARDFILE = 0x01,
 190 };
 191
 192 static sysctrl_t *sysctrl;
 193
 194 static void PREP_io_write (void *opaque, uint32_t addr, uint32_t val)
 195 {
 196     sysctrl_t *sysctrl = opaque;
 197
 198     PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
 199                    val);
 200     sysctrl->fake_io[addr - 0x0398] = val;
 201 }
 202
 203 static uint32_t PREP_io_read (void *opaque, uint32_t addr)
 204 {
 205     sysctrl_t *sysctrl = opaque;
 206
 207     PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n", addr - PPC_IO_BASE,
 208                    sysctrl->fake_io[addr - 0x0398]);
 209     return sysctrl->fake_io[addr - 0x0398];
 210 }
 211
 212 static void PREP_io_800_writeb (void *opaque, uint32_t addr, uint32_t val)
 213 {
 214     sysctrl_t *sysctrl = opaque;
 215
 216     PPC_IO_DPRINTF("0x%08" PRIx32 " => 0x%02" PRIx32 "\n",
 217                    addr - PPC_IO_BASE, val);
 218     switch (addr) {
 219     case 0x0092:
 220         /* Special port 92 */
 221         /* Check soft reset asked */
 222         if (val & 0x01) {
 223             qemu_irq_raise(sysctrl->reset_irq);
 224         } else {
 225             qemu_irq_lower(sysctrl->reset_irq);
 226         }
 227         /* Check LE mode */
 228         if (val & 0x02) {
 229             sysctrl->endian = 1;
 230         } else {
 231             sysctrl->endian = 0;
 232         }
 233         break;
 234     case 0x0800:
 235         /* Motorola CPU configuration register : read-only */
 236         break;
 237     case 0x0802:
 238         /* Motorola base module feature register : read-only */
 239         break;
 240     case 0x0803:
 241         /* Motorola base module status register : read-only */
 242         break;
 243     case 0x0808:
 244         /* Hardfile light register */
 245         if (val & 1)
 246             sysctrl->state |= STATE_HARDFILE;
 247         else
 248             sysctrl->state &= ~STATE_HARDFILE;
 249         break;
 250     case 0x0810:
 251         /* Password protect 1 register */
 252         if (sysctrl->nvram != NULL)
 253             m48t59_toggle_lock(sysctrl->nvram, 1);
 254         break;
 255     case 0x0812:
 256         /* Password protect 2 register */
 257         if (sysctrl->nvram != NULL)
 258             m48t59_toggle_lock(sysctrl->nvram, 2);
 259         break;
 260     case 0x0814:
 261         /* L2 invalidate register */
 262         //        tlb_flush(first_cpu, 1);
 263         break;
 264     case 0x081C:
 265         /* system control register */
 266         sysctrl->syscontrol = val & 0x0F;
 267         break;
 268     case 0x0850:
 269         /* I/O map type register */
 270         sysctrl->contiguous_map = val & 0x01;
 271         break;
 272     default:
 273         printf("ERROR: unaffected IO port write: %04" PRIx32
 274                " => %02" PRIx32"\n", addr, val);
 275         break;
 276     }
 277 }
 278
 279 static uint32_t PREP_io_800_readb (void *opaque, uint32_t addr)
 280 {
 281     sysctrl_t *sysctrl = opaque;
 282     uint32_t retval = 0xFF;
 283
 284     switch (addr) {
 285     case 0x0092:
 286         /* Special port 92 */
 287         retval = 0x00;
 288         break;
 289     case 0x0800:
 290         /* Motorola CPU configuration register */
 291         retval = 0xEF; /* MPC750 */
 292         break;
 293     case 0x0802:
 294         /* Motorola Base module feature register */
 295         retval = 0xAD; /* No ESCC, PMC slot neither ethernet */
 296         break;
 297     case 0x0803:
 298         /* Motorola base module status register */
 299         retval = 0xE0; /* Standard MPC750 */
 300         break;
 301     case 0x080C:
 302         /* Equipment present register:
 303          *  no L2 cache
 304          *  no upgrade processor
 305          *  no cards in PCI slots
 306          *  SCSI fuse is bad
 307          */
 308         retval = 0x3C;
 309         break;
 310     case 0x0810:
 311         /* Motorola base module extended feature register */
 312         retval = 0x39; /* No USB, CF and PCI bridge. NVRAM present */
 313         break;
 314     case 0x0814:
 315         /* L2 invalidate: don't care */
 316         break;
 317     case 0x0818:
 318         /* Keylock */
 319         retval = 0x00;
 320         break;
 321     case 0x081C:
 322         /* system control register
 323          * 7 - 6 / 1 - 0: L2 cache enable
 324          */
 325         retval = sysctrl->syscontrol;
 326         break;
 327     case 0x0823:
 328         /* */
 329         retval = 0x03; /* no L2 cache */
 330         break;
 331     case 0x0850:
 332         /* I/O map type register */
 333         retval = sysctrl->contiguous_map;
 334         break;
 335     default:
 336         printf("ERROR: unaffected IO port: %04" PRIx32 " read\n", addr);
 337         break;
 338     }
 339     PPC_IO_DPRINTF("0x%08" PRIx32 " <= 0x%02" PRIx32 "\n",
 340                    addr - PPC_IO_BASE, retval);
 341
 342     return retval;
 343 }
 344
 345 static inline target_phys_addr_t prep_IO_address(sysctrl_t *sysctrl,
 346                                                  target_phys_addr_t addr)
 347 {
 348     if (sysctrl->contiguous_map == 0) {
 349         /* 64 KB contiguous space for IOs */
 350         addr &= 0xFFFF;
 351     } else {
 352         /* 8 MB non-contiguous space for IOs */
 353         addr = (addr & 0x1F) | ((addr & 0x007FFF000) >> 7);
 354     }
 355
 356     return addr;
 357 }
 358
 359 static void PPC_prep_io_writeb (void *opaque, target_phys_addr_t addr,
 360                                 uint32_t value)
 361 {
 362     sysctrl_t *sysctrl = opaque;
 363
 364     addr = prep_IO_address(sysctrl, addr);
 365     cpu_outb(addr, value);
 366 }
 367
 368 static uint32_t PPC_prep_io_readb (void *opaque, target_phys_addr_t addr)
 369 {
 370     sysctrl_t *sysctrl = opaque;
 371     uint32_t ret;
 372
 373     addr = prep_IO_address(sysctrl, addr);
 374     ret = cpu_inb(addr);
 375
 376     return ret;
 377 }
 378
 379 static void PPC_prep_io_writew (void *opaque, target_phys_addr_t addr,
 380                                 uint32_t value)
 381 {
 382     sysctrl_t *sysctrl = opaque;
 383
 384     addr = prep_IO_address(sysctrl, addr);
 385     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
 386     cpu_outw(addr, value);
 387 }
 388
 389 static uint32_t PPC_prep_io_readw (void *opaque, target_phys_addr_t addr)
 390 {
 391     sysctrl_t *sysctrl = opaque;
 392     uint32_t ret;
 393
 394     addr = prep_IO_address(sysctrl, addr);
 395     ret = cpu_inw(addr);
 396     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
 397
 398     return ret;
 399 }
 400
 401 static void PPC_prep_io_writel (void *opaque, target_phys_addr_t addr,
 402                                 uint32_t value)
 403 {
 404     sysctrl_t *sysctrl = opaque;
 405
 406     addr = prep_IO_address(sysctrl, addr);
 407     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " => 0x%08" PRIx32 "\n", addr, value);
 408     cpu_outl(addr, value);
 409 }
 410
 411 static uint32_t PPC_prep_io_readl (void *opaque, target_phys_addr_t addr)
 412 {
 413     sysctrl_t *sysctrl = opaque;
 414     uint32_t ret;
 415
 416     addr = prep_IO_address(sysctrl, addr);
 417     ret = cpu_inl(addr);
 418     PPC_IO_DPRINTF("0x" TARGET_FMT_plx " <= 0x%08" PRIx32 "\n", addr, ret);
 419
 420     return ret;
 421 }
 422
 423 static const MemoryRegionOps PPC_prep_io_ops = {
 424     .old_mmio = {
 425         .read = { PPC_prep_io_readb, PPC_prep_io_readw, PPC_prep_io_readl },
 426         .write = { PPC_prep_io_writeb, PPC_prep_io_writew, PPC_prep_io_writel },
 427     },
 428     .endianness = DEVICE_LITTLE_ENDIAN,
 429 };
 430
 431 #define NVRAM_SIZE        0x2000
 432
 433 static void cpu_request_exit(void *opaque, int irq, int level)
 434 {
 435     CPUPPCState *env = cpu_single_env;
 436
 437     if (env && level) {
 438         cpu_exit(env);
 439     }
 440 }
 441
 442 static void ppc_prep_reset(void *opaque)
 443 {
 444     PowerPCCPU *cpu = opaque;
 445
 446     cpu_reset(CPU(cpu));
 447 }
 448
 449 /* PowerPC PREP hardware initialisation */
 450 static void ppc_prep_init (ram_addr_t ram_size,
 451                            const char *boot_device,
 452                            const char *kernel_filename,
 453                            const char *kernel_cmdline,
 454                            const char *initrd_filename,
 455                            const char *cpu_model)
 456 {
 457     MemoryRegion *sysmem = get_system_memory();
 458     PowerPCCPU *cpu = NULL;
 459     CPUPPCState *env = NULL;
 460     char *filename;
 461     nvram_t nvram;
 462     M48t59State *m48t59;
 463     MemoryRegion *PPC_io_memory = g_new(MemoryRegion, 1);
 464 #if 0
 465     MemoryRegion *xcsr = g_new(MemoryRegion, 1);
 466 #endif
 467     int linux_boot, i, nb_nics1, bios_size;
 468     MemoryRegion *ram = g_new(MemoryRegion, 1);
 469     MemoryRegion *bios = g_new(MemoryRegion, 1);
 470     uint32_t kernel_base, initrd_base;
 471     long kernel_size, initrd_size;
 472     DeviceState *dev;
 473     PCIHostState *pcihost;
 474     PCIBus *pci_bus;
 475     PCIDevice *pci;
 476     ISABus *isa_bus;
 477     qemu_irq *cpu_exit_irq;
 478     int ppc_boot_device;
 479     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 480     DriveInfo *fd[MAX_FD];
 481
 482     sysctrl = g_malloc0(sizeof(sysctrl_t));
 483
 484     linux_boot = (kernel_filename != NULL);
 485
 486     /* init CPUs */
 487     if (cpu_model == NULL)
 488         cpu_model = "602";
 489     for (i = 0; i < smp_cpus; i++) {
 490         cpu = cpu_ppc_init(cpu_model);
 491         if (cpu == NULL) {
 492             fprintf(stderr, "Unable to find PowerPC CPU definition\n");
 493             exit(1);
 494         }
 495         env = &cpu->env;
 496
 497         if (env->flags & POWERPC_FLAG_RTC_CLK) {
 498             /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */
 499             cpu_ppc_tb_init(env, 7812500UL);
 500         } else {
 501             /* Set time-base frequency to 100 Mhz */
 502             cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL);
 503         }
 504         qemu_register_reset(ppc_prep_reset, cpu);
 505     }
 506
 507     /* allocate RAM */
 508     memory_region_init_ram(ram, "ppc_prep.ram", ram_size);
 509     vmstate_register_ram_global(ram);
 510     memory_region_add_subregion(sysmem, 0, ram);
 511
 512     /* allocate and load BIOS */
 513     memory_region_init_ram(bios, "ppc_prep.bios", BIOS_SIZE);
 514     memory_region_set_readonly(bios, true);
 515     memory_region_add_subregion(sysmem, (uint32_t)(-BIOS_SIZE), bios);
 516     vmstate_register_ram_global(bios);
 517     if (bios_name == NULL)
 518         bios_name = BIOS_FILENAME;
 519     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 520     if (filename) {
 521         bios_size = get_image_size(filename);
 522     } else {
 523         bios_size = -1;
 524     }
 525     if (bios_size > 0 && bios_size <= BIOS_SIZE) {
 526         target_phys_addr_t bios_addr;
 527         bios_size = (bios_size + 0xfff) & ~0xfff;
 528         bios_addr = (uint32_t)(-bios_size);
 529         bios_size = load_image_targphys(filename, bios_addr, bios_size);
 530     }
 531     if (bios_size < 0 || bios_size > BIOS_SIZE) {
 532         hw_error("qemu: could not load PPC PREP bios '%s'\n", bios_name);
 533     }
 534     if (filename) {
 535         g_free(filename);
 536     }
 537
 538     if (linux_boot) {
 539         kernel_base = KERNEL_LOAD_ADDR;
 540         /* now we can load the kernel */
 541         kernel_size = load_image_targphys(kernel_filename, kernel_base,
 542                                           ram_size - kernel_base);
 543         if (kernel_size < 0) {
 544             hw_error("qemu: could not load kernel '%s'\n", kernel_filename);
 545             exit(1);
 546         }
 547         /* load initrd */
 548         if (initrd_filename) {
 549             initrd_base = INITRD_LOAD_ADDR;
 550             initrd_size = load_image_targphys(initrd_filename, initrd_base,
 551                                               ram_size - initrd_base);
 552             if (initrd_size < 0) {
 553                 hw_error("qemu: could not load initial ram disk '%s'\n",
 554                           initrd_filename);
 555             }
 556         } else {
 557             initrd_base = 0;
 558             initrd_size = 0;
 559         }
 560         ppc_boot_device = 'm';
 561     } else {
 562         kernel_base = 0;
 563         kernel_size = 0;
 564         initrd_base = 0;
 565         initrd_size = 0;
 566         ppc_boot_device = '\0';
 567         /* For now, OHW cannot boot from the network. */
 568         for (i = 0; boot_device[i] != '\0'; i++) {
 569             if (boot_device[i] >= 'a' && boot_device[i] <= 'f') {
 570                 ppc_boot_device = boot_device[i];
 571                 break;
 572             }
 573         }
 574         if (ppc_boot_device == '\0') {
 575             fprintf(stderr, "No valid boot device for Mac99 machine\n");
 576             exit(1);
 577         }
 578     }
 579
 580     if (PPC_INPUT(env) != PPC_FLAGS_INPUT_6xx) {
 581         hw_error("Only 6xx bus is supported on PREP machine\n");
 582     }
 583
 584     dev = qdev_create(NULL, "raven-pcihost");
 585     pcihost = PCI_HOST_BRIDGE(dev);
 586     pcihost->address_space = get_system_memory();
 587     object_property_add_child(qdev_get_machine(), "raven", OBJECT(dev), NULL);
 588     qdev_init_nofail(dev);
 589     pci_bus = (PCIBus *)qdev_get_child_bus(dev, "pci.0");
 590     if (pci_bus == NULL) {
 591         fprintf(stderr, "Couldn't create PCI host controller.\n");
 592         exit(1);
 593     }
 594
 595     /* PCI -> ISA bridge */
 596     pci = pci_create_simple(pci_bus, PCI_DEVFN(1, 0), "i82378");
 597     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
 598     qdev_connect_gpio_out(&pci->qdev, 0,
 599                           first_cpu->irq_inputs[PPC6xx_INPUT_INT]);
 600     qdev_connect_gpio_out(&pci->qdev, 1, *cpu_exit_irq);
 601     sysbus_connect_irq(&pcihost->busdev, 0, qdev_get_gpio_in(&pci->qdev, 9));
 602     sysbus_connect_irq(&pcihost->busdev, 1, qdev_get_gpio_in(&pci->qdev, 11));
 603     sysbus_connect_irq(&pcihost->busdev, 2, qdev_get_gpio_in(&pci->qdev, 9));
 604     sysbus_connect_irq(&pcihost->busdev, 3, qdev_get_gpio_in(&pci->qdev, 11));
 605     isa_bus = DO_UPCAST(ISABus, qbus, qdev_get_child_bus(&pci->qdev, "isa.0"));
 606
 607     /* Register 8 MB of ISA IO space (needed for non-contiguous map) */
 608     memory_region_init_io(PPC_io_memory, &PPC_prep_io_ops, sysctrl,
 609                           "ppc-io", 0x00800000);
 610     memory_region_add_subregion(sysmem, 0x80000000, PPC_io_memory);
 611
 612     /* init basic PC hardware */
 613     pci_vga_init(pci_bus);
 614
 615     if (serial_hds[0])
 616         serial_isa_init(isa_bus, 0, serial_hds[0]);
 617     nb_nics1 = nb_nics;
 618     if (nb_nics1 > NE2000_NB_MAX)
 619         nb_nics1 = NE2000_NB_MAX;
 620     for(i = 0; i < nb_nics1; i++) {
 621         if (nd_table[i].model == NULL) {
 622             nd_table[i].model = g_strdup("ne2k_isa");
 623         }
 624         if (strcmp(nd_table[i].model, "ne2k_isa") == 0) {
 625             isa_ne2000_init(isa_bus, ne2000_io[i], ne2000_irq[i],
 626                             &nd_table[i]);
 627         } else {
 628             pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 629         }
 630     }
 631
 632     ide_drive_get(hd, MAX_IDE_BUS);
 633     for(i = 0; i < MAX_IDE_BUS; i++) {
 634         isa_ide_init(isa_bus, ide_iobase[i], ide_iobase2[i], ide_irq[i],
 635                      hd[2 * i],
 636                      hd[2 * i + 1]);
 637     }
 638     isa_create_simple(isa_bus, "i8042");
 639
 640     //    SB16_init();
 641
 642     for(i = 0; i < MAX_FD; i++) {
 643         fd[i] = drive_get(IF_FLOPPY, 0, i);
 644     }
 645     fdctrl_init_isa(isa_bus, fd);
 646
 647     /* Register fake IO ports for PREP */
 648     sysctrl->reset_irq = first_cpu->irq_inputs[PPC6xx_INPUT_HRESET];
 649     register_ioport_read(0x398, 2, 1, &PREP_io_read, sysctrl);
 650     register_ioport_write(0x398, 2, 1, &PREP_io_write, sysctrl);
 651     /* System control ports */
 652     register_ioport_read(0x0092, 0x01, 1, &PREP_io_800_readb, sysctrl);
 653     register_ioport_write(0x0092, 0x01, 1, &PREP_io_800_writeb, sysctrl);
 654     register_ioport_read(0x0800, 0x52, 1, &PREP_io_800_readb, sysctrl);
 655     register_ioport_write(0x0800, 0x52, 1, &PREP_io_800_writeb, sysctrl);
 656     /* PowerPC control and status register group */
 657 #if 0
 658     memory_region_init_io(xcsr, &PPC_XCSR_ops, NULL, "ppc-xcsr", 0x1000);
 659     memory_region_add_subregion(sysmem, 0xFEFF0000, xcsr);
 660 #endif
 661
 662     if (usb_enabled) {
 663         pci_create_simple(pci_bus, -1, "pci-ohci");
 664     }
 665
 666     m48t59 = m48t59_init_isa(isa_bus, 0x0074, NVRAM_SIZE, 59);
 667     if (m48t59 == NULL)
 668         return;
 669     sysctrl->nvram = m48t59;
 670
 671     /* Initialise NVRAM */
 672     nvram.opaque = m48t59;
 673     nvram.read_fn = &m48t59_read;
 674     nvram.write_fn = &m48t59_write;
 675     PPC_NVRAM_set_params(&nvram, NVRAM_SIZE, "PREP", ram_size, ppc_boot_device,
 676                          kernel_base, kernel_size,
 677                          kernel_cmdline,
 678                          initrd_base, initrd_size,
 679                          /* XXX: need an option to load a NVRAM image */
 680                          0,
 681                          graphic_width, graphic_height, graphic_depth);
 682
 683     /* Special port to get debug messages from Open-Firmware */
 684     register_ioport_write(0x0F00, 4, 1, &PPC_debug_write, NULL);
 685
 686     /* Initialize audio subsystem */
 687     audio_init(isa_bus, pci_bus);
 688 }
 689
 690 static QEMUMachine prep_machine = {
 691     .name = "prep",
 692     .desc = "PowerPC PREP platform",
 693     .init = ppc_prep_init,
 694     .max_cpus = MAX_CPUS,
 695 };
 696
 697 static void prep_machine_init(void)
 698 {
 699     qemu_register_machine(&prep_machine);
 700 }
 701
 702 machine_init(prep_machine_init);