hw/pc.c

   1 /*
   2  * QEMU PC System Emulator
   3  *
   4  * Copyright (c) 2003-2004 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pc.h"
  26 #include "apic.h"
  27 #include "fdc.h"
  28 #include "ide.h"
  29 #include "pci.h"
  30 #include "monitor.h"
  31 #include "fw_cfg.h"
  32 #include "hpet_emul.h"
  33 #include "smbios.h"
  34 #include "loader.h"
  35 #include "elf.h"
  36 #include "multiboot.h"
  37 #include "mc146818rtc.h"
  38 #include "i8254.h"
  39 #include "pcspk.h"
  40 #include "msi.h"
  41 #include "sysbus.h"
  42 #include "sysemu.h"
  43 #include "kvm.h"
  44 #include "kvm_i386.h"
  45 #include "xen.h"
  46 #include "blockdev.h"
  47 #include "hw/block-common.h"
  48 #include "ui/qemu-spice.h"
  49 #include "memory.h"
  50 #include "exec-memory.h"
  51 #include "arch_init.h"
  52 #include "bitmap.h"
  53
  54 /* debug PC/ISA interrupts */
  55 //#define DEBUG_IRQ
  56
  57 #ifdef DEBUG_IRQ
  58 #define DPRINTF(fmt, ...)                                       \
  59     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  60 #else
  61 #define DPRINTF(fmt, ...)
  62 #endif
  63
  64 /* Leave a chunk of memory at the top of RAM for the BIOS ACPI tables.  */
  65 #define ACPI_DATA_SIZE       0x10000
  66 #define BIOS_CFG_IOPORT 0x510
  67 #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0)
  68 #define FW_CFG_SMBIOS_ENTRIES (FW_CFG_ARCH_LOCAL + 1)
  69 #define FW_CFG_IRQ0_OVERRIDE (FW_CFG_ARCH_LOCAL + 2)
  70 #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3)
  71 #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4)
  72
  73 #define MSI_ADDR_BASE 0xfee00000
  74
  75 #define E820_NR_ENTRIES         16
  76
  77 struct e820_entry {
  78     uint64_t address;
  79     uint64_t length;
  80     uint32_t type;
  81 } QEMU_PACKED __attribute((__aligned__(4)));
  82
  83 struct e820_table {
  84     uint32_t count;
  85     struct e820_entry entry[E820_NR_ENTRIES];
  86 } QEMU_PACKED __attribute((__aligned__(4)));
  87
  88 static struct e820_table e820_table;
  89 struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX};
  90
  91 void gsi_handler(void *opaque, int n, int level)
  92 {
  93     GSIState *s = opaque;
  94
  95     DPRINTF("pc: %s GSI %d\n", level ? "raising" : "lowering", n);
  96     if (n < ISA_NUM_IRQS) {
  97         qemu_set_irq(s->i8259_irq[n], level);
  98     }
  99     qemu_set_irq(s->ioapic_irq[n], level);
 100 }
 101
 102 static void ioport80_write(void *opaque, uint32_t addr, uint32_t data)
 103 {
 104 }
 105
 106 /* MSDOS compatibility mode FPU exception support */
 107 static qemu_irq ferr_irq;
 108
 109 void pc_register_ferr_irq(qemu_irq irq)
 110 {
 111     ferr_irq = irq;
 112 }
 113
 114 /* XXX: add IGNNE support */
 115 void cpu_set_ferr(CPUX86State *s)
 116 {
 117     qemu_irq_raise(ferr_irq);
 118 }
 119
 120 static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data)
 121 {
 122     qemu_irq_lower(ferr_irq);
 123 }
 124
 125 /* TSC handling */
 126 uint64_t cpu_get_tsc(CPUX86State *env)
 127 {
 128     return cpu_get_ticks();
 129 }
 130
 131 /* SMM support */
 132
 133 static cpu_set_smm_t smm_set;
 134 static void *smm_arg;
 135
 136 void cpu_smm_register(cpu_set_smm_t callback, void *arg)
 137 {
 138     assert(smm_set == NULL);
 139     assert(smm_arg == NULL);
 140     smm_set = callback;
 141     smm_arg = arg;
 142 }
 143
 144 void cpu_smm_update(CPUX86State *env)
 145 {
 146     if (smm_set && smm_arg && env == first_cpu)
 147         smm_set(!!(env->hflags & HF_SMM_MASK), smm_arg);
 148 }
 149
 150
 151 /* IRQ handling */
 152 int cpu_get_pic_interrupt(CPUX86State *env)
 153 {
 154     int intno;
 155
 156     intno = apic_get_interrupt(env->apic_state);
 157     if (intno >= 0) {
 158         return intno;
 159     }
 160     /* read the irq from the PIC */
 161     if (!apic_accept_pic_intr(env->apic_state)) {
 162         return -1;
 163     }
 164
 165     intno = pic_read_irq(isa_pic);
 166     return intno;
 167 }
 168
 169 static void pic_irq_request(void *opaque, int irq, int level)
 170 {
 171     CPUX86State *env = first_cpu;
 172
 173     DPRINTF("pic_irqs: %s irq %d\n", level? "raise" : "lower", irq);
 174     if (env->apic_state) {
 175         while (env) {
 176             if (apic_accept_pic_intr(env->apic_state)) {
 177                 apic_deliver_pic_intr(env->apic_state, level);
 178             }
 179             env = env->next_cpu;
 180         }
 181     } else {
 182         if (level)
 183             cpu_interrupt(env, CPU_INTERRUPT_HARD);
 184         else
 185             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 186     }
 187 }
 188
 189 /* PC cmos mappings */
 190
 191 #define REG_EQUIPMENT_BYTE          0x14
 192
 193 static int cmos_get_fd_drive_type(FDriveType fd0)
 194 {
 195     int val;
 196
 197     switch (fd0) {
 198     case FDRIVE_DRV_144:
 199         /* 1.44 Mb 3"5 drive */
 200         val = 4;
 201         break;
 202     case FDRIVE_DRV_288:
 203         /* 2.88 Mb 3"5 drive */
 204         val = 5;
 205         break;
 206     case FDRIVE_DRV_120:
 207         /* 1.2 Mb 5"5 drive */
 208         val = 2;
 209         break;
 210     case FDRIVE_DRV_NONE:
 211     default:
 212         val = 0;
 213         break;
 214     }
 215     return val;
 216 }
 217
 218 static void cmos_init_hd(ISADevice *s, int type_ofs, int info_ofs,
 219                          int16_t cylinders, int8_t heads, int8_t sectors)
 220 {
 221     rtc_set_memory(s, type_ofs, 47);
 222     rtc_set_memory(s, info_ofs, cylinders);
 223     rtc_set_memory(s, info_ofs + 1, cylinders >> 8);
 224     rtc_set_memory(s, info_ofs + 2, heads);
 225     rtc_set_memory(s, info_ofs + 3, 0xff);
 226     rtc_set_memory(s, info_ofs + 4, 0xff);
 227     rtc_set_memory(s, info_ofs + 5, 0xc0 | ((heads > 8) << 3));
 228     rtc_set_memory(s, info_ofs + 6, cylinders);
 229     rtc_set_memory(s, info_ofs + 7, cylinders >> 8);
 230     rtc_set_memory(s, info_ofs + 8, sectors);
 231 }
 232
 233 /* convert boot_device letter to something recognizable by the bios */
 234 static int boot_device2nibble(char boot_device)
 235 {
 236     switch(boot_device) {
 237     case 'a':
 238     case 'b':
 239         return 0x01; /* floppy boot */
 240     case 'c':
 241         return 0x02; /* hard drive boot */
 242     case 'd':
 243         return 0x03; /* CD-ROM boot */
 244     case 'n':
 245         return 0x04; /* Network boot */
 246     }
 247     return 0;
 248 }
 249
 250 static int set_boot_dev(ISADevice *s, const char *boot_device, int fd_bootchk)
 251 {
 252 #define PC_MAX_BOOT_DEVICES 3
 253     int nbds, bds[3] = { 0, };
 254     int i;
 255
 256     nbds = strlen(boot_device);
 257     if (nbds > PC_MAX_BOOT_DEVICES) {
 258         error_report("Too many boot devices for PC");
 259         return(1);
 260     }
 261     for (i = 0; i < nbds; i++) {
 262         bds[i] = boot_device2nibble(boot_device[i]);
 263         if (bds[i] == 0) {
 264             error_report("Invalid boot device for PC: '%c'",
 265                          boot_device[i]);
 266             return(1);
 267         }
 268     }
 269     rtc_set_memory(s, 0x3d, (bds[1] << 4) | bds[0]);
 270     rtc_set_memory(s, 0x38, (bds[2] << 4) | (fd_bootchk ? 0x0 : 0x1));
 271     return(0);
 272 }
 273
 274 static int pc_boot_set(void *opaque, const char *boot_device)
 275 {
 276     return set_boot_dev(opaque, boot_device, 0);
 277 }
 278
 279 typedef struct pc_cmos_init_late_arg {
 280     ISADevice *rtc_state;
 281     BusState *idebus[2];
 282 } pc_cmos_init_late_arg;
 283
 284 static void pc_cmos_init_late(void *opaque)
 285 {
 286     pc_cmos_init_late_arg *arg = opaque;
 287     ISADevice *s = arg->rtc_state;
 288     int16_t cylinders;
 289     int8_t heads, sectors;
 290     int val;
 291     int i, trans;
 292
 293     val = 0;
 294     if (ide_get_geometry(arg->idebus[0], 0,
 295                          &cylinders, &heads, &sectors) >= 0) {
 296         cmos_init_hd(s, 0x19, 0x1b, cylinders, heads, sectors);
 297         val |= 0xf0;
 298     }
 299     if (ide_get_geometry(arg->idebus[0], 1,
 300                          &cylinders, &heads, &sectors) >= 0) {
 301         cmos_init_hd(s, 0x1a, 0x24, cylinders, heads, sectors);
 302         val |= 0x0f;
 303     }
 304     rtc_set_memory(s, 0x12, val);
 305
 306     val = 0;
 307     for (i = 0; i < 4; i++) {
 308         /* NOTE: ide_get_geometry() returns the physical
 309            geometry.  It is always such that: 1 <= sects <= 63, 1
 310            <= heads <= 16, 1 <= cylinders <= 16383. The BIOS
 311            geometry can be different if a translation is done. */
 312         if (ide_get_geometry(arg->idebus[i / 2], i % 2,
 313                              &cylinders, &heads, &sectors) >= 0) {
 314             trans = ide_get_bios_chs_trans(arg->idebus[i / 2], i % 2) - 1;
 315             assert((trans & ~3) == 0);
 316             val |= trans << (i * 2);
 317         }
 318     }
 319     rtc_set_memory(s, 0x39, val);
 320
 321     qemu_unregister_reset(pc_cmos_init_late, opaque);
 322 }
 323
 324 void pc_cmos_init(ram_addr_t ram_size, ram_addr_t above_4g_mem_size,
 325                   const char *boot_device,
 326                   ISADevice *floppy, BusState *idebus0, BusState *idebus1,
 327                   ISADevice *s)
 328 {
 329     int val, nb, i;
 330     FDriveType fd_type[2] = { FDRIVE_DRV_NONE, FDRIVE_DRV_NONE };
 331     static pc_cmos_init_late_arg arg;
 332
 333     /* various important CMOS locations needed by PC/Bochs bios */
 334
 335     /* memory size */
 336     /* base memory (first MiB) */
 337     val = MIN(ram_size / 1024, 640);
 338     rtc_set_memory(s, 0x15, val);
 339     rtc_set_memory(s, 0x16, val >> 8);
 340     /* extended memory (next 64MiB) */
 341     if (ram_size > 1024 * 1024) {
 342         val = (ram_size - 1024 * 1024) / 1024;
 343     } else {
 344         val = 0;
 345     }
 346     if (val > 65535)
 347         val = 65535;
 348     rtc_set_memory(s, 0x17, val);
 349     rtc_set_memory(s, 0x18, val >> 8);
 350     rtc_set_memory(s, 0x30, val);
 351     rtc_set_memory(s, 0x31, val >> 8);
 352     /* memory between 16MiB and 4GiB */
 353     if (ram_size > 16 * 1024 * 1024) {
 354         val = (ram_size - 16 * 1024 * 1024) / 65536;
 355     } else {
 356         val = 0;
 357     }
 358     if (val > 65535)
 359         val = 65535;
 360     rtc_set_memory(s, 0x34, val);
 361     rtc_set_memory(s, 0x35, val >> 8);
 362     /* memory above 4GiB */
 363     val = above_4g_mem_size / 65536;
 364     rtc_set_memory(s, 0x5b, val);
 365     rtc_set_memory(s, 0x5c, val >> 8);
 366     rtc_set_memory(s, 0x5d, val >> 16);
 367
 368     /* set the number of CPU */
 369     rtc_set_memory(s, 0x5f, smp_cpus - 1);
 370
 371     /* set boot devices, and disable floppy signature check if requested */
 372     if (set_boot_dev(s, boot_device, fd_bootchk)) {
 373         exit(1);
 374     }
 375
 376     /* floppy type */
 377     if (floppy) {
 378         for (i = 0; i < 2; i++) {
 379             fd_type[i] = isa_fdc_get_drive_type(floppy, i);
 380         }
 381     }
 382     val = (cmos_get_fd_drive_type(fd_type[0]) << 4) |
 383         cmos_get_fd_drive_type(fd_type[1]);
 384     rtc_set_memory(s, 0x10, val);
 385
 386     val = 0;
 387     nb = 0;
 388     if (fd_type[0] < FDRIVE_DRV_NONE) {
 389         nb++;
 390     }
 391     if (fd_type[1] < FDRIVE_DRV_NONE) {
 392         nb++;
 393     }
 394     switch (nb) {
 395     case 0:
 396         break;
 397     case 1:
 398         val |= 0x01; /* 1 drive, ready for boot */
 399         break;
 400     case 2:
 401         val |= 0x41; /* 2 drives, ready for boot */
 402         break;
 403     }
 404     val |= 0x02; /* FPU is there */
 405     val |= 0x04; /* PS/2 mouse installed */
 406     rtc_set_memory(s, REG_EQUIPMENT_BYTE, val);
 407
 408     /* hard drives */
 409     arg.rtc_state = s;
 410     arg.idebus[0] = idebus0;
 411     arg.idebus[1] = idebus1;
 412     qemu_register_reset(pc_cmos_init_late, &arg);
 413 }
 414
 415 /* port 92 stuff: could be split off */
 416 typedef struct Port92State {
 417     ISADevice dev;
 418     MemoryRegion io;
 419     uint8_t outport;
 420     qemu_irq *a20_out;
 421 } Port92State;
 422
 423 static void port92_write(void *opaque, uint32_t addr, uint32_t val)
 424 {
 425     Port92State *s = opaque;
 426
 427     DPRINTF("port92: write 0x%02x\n", val);
 428     s->outport = val;
 429     qemu_set_irq(*s->a20_out, (val >> 1) & 1);
 430     if (val & 1) {
 431         qemu_system_reset_request();
 432     }
 433 }
 434
 435 static uint32_t port92_read(void *opaque, uint32_t addr)
 436 {
 437     Port92State *s = opaque;
 438     uint32_t ret;
 439
 440     ret = s->outport;
 441     DPRINTF("port92: read 0x%02x\n", ret);
 442     return ret;
 443 }
 444
 445 static void port92_init(ISADevice *dev, qemu_irq *a20_out)
 446 {
 447     Port92State *s = DO_UPCAST(Port92State, dev, dev);
 448
 449     s->a20_out = a20_out;
 450 }
 451
 452 static const VMStateDescription vmstate_port92_isa = {
 453     .name = "port92",
 454     .version_id = 1,
 455     .minimum_version_id = 1,
 456     .minimum_version_id_old = 1,
 457     .fields      = (VMStateField []) {
 458         VMSTATE_UINT8(outport, Port92State),
 459         VMSTATE_END_OF_LIST()
 460     }
 461 };
 462
 463 static void port92_reset(DeviceState *d)
 464 {
 465     Port92State *s = container_of(d, Port92State, dev.qdev);
 466
 467     s->outport &= ~1;
 468 }
 469
 470 static const MemoryRegionPortio port92_portio[] = {
 471     { 0, 1, 1, .read = port92_read, .write = port92_write },
 472     PORTIO_END_OF_LIST(),
 473 };
 474
 475 static const MemoryRegionOps port92_ops = {
 476     .old_portio = port92_portio
 477 };
 478
 479 static int port92_initfn(ISADevice *dev)
 480 {
 481     Port92State *s = DO_UPCAST(Port92State, dev, dev);
 482
 483     memory_region_init_io(&s->io, &port92_ops, s, "port92", 1);
 484     isa_register_ioport(dev, &s->io, 0x92);
 485
 486     s->outport = 0;
 487     return 0;
 488 }
 489
 490 static void port92_class_initfn(ObjectClass *klass, void *data)
 491 {
 492     DeviceClass *dc = DEVICE_CLASS(klass);
 493     ISADeviceClass *ic = ISA_DEVICE_CLASS(klass);
 494     ic->init = port92_initfn;
 495     dc->no_user = 1;
 496     dc->reset = port92_reset;
 497     dc->vmsd = &vmstate_port92_isa;
 498 }
 499
 500 static TypeInfo port92_info = {
 501     .name          = "port92",
 502     .parent        = TYPE_ISA_DEVICE,
 503     .instance_size = sizeof(Port92State),
 504     .class_init    = port92_class_initfn,
 505 };
 506
 507 static void port92_register_types(void)
 508 {
 509     type_register_static(&port92_info);
 510 }
 511
 512 type_init(port92_register_types)
 513
 514 static void handle_a20_line_change(void *opaque, int irq, int level)
 515 {
 516     CPUX86State *cpu = opaque;
 517
 518     /* XXX: send to all CPUs ? */
 519     /* XXX: add logic to handle multiple A20 line sources */
 520     cpu_x86_set_a20(cpu, level);
 521 }
 522
 523 /***********************************************************/
 524 /* Bochs BIOS debug ports */
 525
 526 static void bochs_bios_write(void *opaque, uint32_t addr, uint32_t val)
 527 {
 528     static const char shutdown_str[8] = "Shutdown";
 529     static int shutdown_index = 0;
 530
 531     switch(addr) {
 532     case 0x8900:
 533         /* same as Bochs power off */
 534         if (val == shutdown_str[shutdown_index]) {
 535             shutdown_index++;
 536             if (shutdown_index == 8) {
 537                 shutdown_index = 0;
 538                 qemu_system_shutdown_request();
 539             }
 540         } else {
 541             shutdown_index = 0;
 542         }
 543         break;
 544
 545     case 0x501:
 546     case 0x502:
 547         exit((val << 1) | 1);
 548     }
 549 }
 550
 551 int e820_add_entry(uint64_t address, uint64_t length, uint32_t type)
 552 {
 553     int index = le32_to_cpu(e820_table.count);
 554     struct e820_entry *entry;
 555
 556     if (index >= E820_NR_ENTRIES)
 557         return -EBUSY;
 558     entry = &e820_table.entry[index++];
 559
 560     entry->address = cpu_to_le64(address);
 561     entry->length = cpu_to_le64(length);
 562     entry->type = cpu_to_le32(type);
 563
 564     e820_table.count = cpu_to_le32(index);
 565     return index;
 566 }
 567
 568 static void *bochs_bios_init(void)
 569 {
 570     void *fw_cfg;
 571     uint8_t *smbios_table;
 572     size_t smbios_len;
 573     uint64_t *numa_fw_cfg;
 574     int i, j;
 575
 576     register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL);
 577
 578     register_ioport_write(0x501, 1, 1, bochs_bios_write, NULL);
 579     register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL);
 580     register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL);
 581
 582     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 583
 584     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 585     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 586     fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, (uint8_t *)acpi_tables,
 587                      acpi_tables_len);
 588     fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override());
 589
 590     smbios_table = smbios_get_table(&smbios_len);
 591     if (smbios_table)
 592         fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES,
 593                          smbios_table, smbios_len);
 594     fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, (uint8_t *)&e820_table,
 595                      sizeof(struct e820_table));
 596
 597     fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, (uint8_t *)&hpet_cfg,
 598                      sizeof(struct hpet_fw_config));
 599     /* allocate memory for the NUMA channel: one (64bit) word for the number
 600      * of nodes, one word for each VCPU->node and one word for each node to
 601      * hold the amount of memory.
 602      */
 603     numa_fw_cfg = g_malloc0((1 + max_cpus + nb_numa_nodes) * 8);
 604     numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes);
 605     for (i = 0; i < max_cpus; i++) {
 606         for (j = 0; j < nb_numa_nodes; j++) {
 607             if (test_bit(i, node_cpumask[j])) {
 608                 numa_fw_cfg[i + 1] = cpu_to_le64(j);
 609                 break;
 610             }
 611         }
 612     }
 613     for (i = 0; i < nb_numa_nodes; i++) {
 614         numa_fw_cfg[max_cpus + 1 + i] = cpu_to_le64(node_mem[i]);
 615     }
 616     fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, (uint8_t *)numa_fw_cfg,
 617                      (1 + max_cpus + nb_numa_nodes) * 8);
 618
 619     return fw_cfg;
 620 }
 621
 622 static long get_file_size(FILE *f)
 623 {
 624     long where, size;
 625
 626     /* XXX: on Unix systems, using fstat() probably makes more sense */
 627
 628     where = ftell(f);
 629     fseek(f, 0, SEEK_END);
 630     size = ftell(f);
 631     fseek(f, where, SEEK_SET);
 632
 633     return size;
 634 }
 635
 636 static void load_linux(void *fw_cfg,
 637                        const char *kernel_filename,
 638                        const char *initrd_filename,
 639                        const char *kernel_cmdline,
 640                        target_phys_addr_t max_ram_size)
 641 {
 642     uint16_t protocol;
 643     int setup_size, kernel_size, initrd_size = 0, cmdline_size;
 644     uint32_t initrd_max;
 645     uint8_t header[8192], *setup, *kernel, *initrd_data;
 646     target_phys_addr_t real_addr, prot_addr, cmdline_addr, initrd_addr = 0;
 647     FILE *f;
 648     char *vmode;
 649
 650     /* Align to 16 bytes as a paranoia measure */
 651     cmdline_size = (strlen(kernel_cmdline)+16) & ~15;
 652
 653     /* load the kernel header */
 654     f = fopen(kernel_filename, "rb");
 655     if (!f || !(kernel_size = get_file_size(f)) ||
 656         fread(header, 1, MIN(ARRAY_SIZE(header), kernel_size), f) !=
 657         MIN(ARRAY_SIZE(header), kernel_size)) {
 658         fprintf(stderr, "qemu: could not load kernel '%s': %s\n",
 659                 kernel_filename, strerror(errno));
 660         exit(1);
 661     }
 662
 663     /* kernel protocol version */
 664 #if 0
 665     fprintf(stderr, "header magic: %#x\n", ldl_p(header+0x202));
 666 #endif
 667     if (ldl_p(header+0x202) == 0x53726448)
 668         protocol = lduw_p(header+0x206);
 669     else {
 670         /* This looks like a multiboot kernel. If it is, let's stop
 671            treating it like a Linux kernel. */
 672         if (load_multiboot(fw_cfg, f, kernel_filename, initrd_filename,
 673                            kernel_cmdline, kernel_size, header))
 674             return;
 675         protocol = 0;
 676     }
 677
 678     if (protocol < 0x200 || !(header[0x211] & 0x01)) {
 679         /* Low kernel */
 680         real_addr    = 0x90000;
 681         cmdline_addr = 0x9a000 - cmdline_size;
 682         prot_addr    = 0x10000;
 683     } else if (protocol < 0x202) {
 684         /* High but ancient kernel */
 685         real_addr    = 0x90000;
 686         cmdline_addr = 0x9a000 - cmdline_size;
 687         prot_addr    = 0x100000;
 688     } else {
 689         /* High and recent kernel */
 690         real_addr    = 0x10000;
 691         cmdline_addr = 0x20000;
 692         prot_addr    = 0x100000;
 693     }
 694
 695 #if 0
 696     fprintf(stderr,
 697             "qemu: real_addr     = 0x" TARGET_FMT_plx "\n"
 698             "qemu: cmdline_addr  = 0x" TARGET_FMT_plx "\n"
 699             "qemu: prot_addr     = 0x" TARGET_FMT_plx "\n",
 700             real_addr,
 701             cmdline_addr,
 702             prot_addr);
 703 #endif
 704
 705     /* highest address for loading the initrd */
 706     if (protocol >= 0x203)
 707         initrd_max = ldl_p(header+0x22c);
 708     else
 709         initrd_max = 0x37ffffff;
 710
 711     if (initrd_max >= max_ram_size-ACPI_DATA_SIZE)
 712         initrd_max = max_ram_size-ACPI_DATA_SIZE-1;
 713
 714     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_ADDR, cmdline_addr);
 715     fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, strlen(kernel_cmdline)+1);
 716     fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 717                      (uint8_t*)strdup(kernel_cmdline),
 718                      strlen(kernel_cmdline)+1);
 719
 720     if (protocol >= 0x202) {
 721         stl_p(header+0x228, cmdline_addr);
 722     } else {
 723         stw_p(header+0x20, 0xA33F);
 724         stw_p(header+0x22, cmdline_addr-real_addr);
 725     }
 726
 727     /* handle vga= parameter */
 728     vmode = strstr(kernel_cmdline, "vga=");
 729     if (vmode) {
 730         unsigned int video_mode;
 731         /* skip "vga=" */
 732         vmode += 4;
 733         if (!strncmp(vmode, "normal", 6)) {
 734             video_mode = 0xffff;
 735         } else if (!strncmp(vmode, "ext", 3)) {
 736             video_mode = 0xfffe;
 737         } else if (!strncmp(vmode, "ask", 3)) {
 738             video_mode = 0xfffd;
 739         } else {
 740             video_mode = strtol(vmode, NULL, 0);
 741         }
 742         stw_p(header+0x1fa, video_mode);
 743     }
 744
 745     /* loader type */
 746     /* High nybble = B reserved for QEMU; low nybble is revision number.
 747        If this code is substantially changed, you may want to consider
 748        incrementing the revision. */
 749     if (protocol >= 0x200)
 750         header[0x210] = 0xB0;
 751
 752     /* heap */
 753     if (protocol >= 0x201) {
 754         header[0x211] |= 0x80;  /* CAN_USE_HEAP */
 755         stw_p(header+0x224, cmdline_addr-real_addr-0x200);
 756     }
 757
 758     /* load initrd */
 759     if (initrd_filename) {
 760         if (protocol < 0x200) {
 761             fprintf(stderr, "qemu: linux kernel too old to load a ram disk\n");
 762             exit(1);
 763         }
 764
 765         initrd_size = get_image_size(initrd_filename);
 766         if (initrd_size < 0) {
 767             fprintf(stderr, "qemu: error reading initrd %s\n",
 768                     initrd_filename);
 769             exit(1);
 770         }
 771
 772         initrd_addr = (initrd_max-initrd_size) & ~4095;
 773
 774         initrd_data = g_malloc(initrd_size);
 775         load_image(initrd_filename, initrd_data);
 776
 777         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, initrd_addr);
 778         fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 779         fw_cfg_add_bytes(fw_cfg, FW_CFG_INITRD_DATA, initrd_data, initrd_size);
 780
 781         stl_p(header+0x218, initrd_addr);
 782         stl_p(header+0x21c, initrd_size);
 783     }
 784
 785     /* load kernel and setup */
 786     setup_size = header[0x1f1];
 787     if (setup_size == 0)
 788         setup_size = 4;
 789     setup_size = (setup_size+1)*512;
 790     kernel_size -= setup_size;
 791
 792     setup  = g_malloc(setup_size);
 793     kernel = g_malloc(kernel_size);
 794     fseek(f, 0, SEEK_SET);
 795     if (fread(setup, 1, setup_size, f) != setup_size) {
 796         fprintf(stderr, "fread() failed\n");
 797         exit(1);
 798     }
 799     if (fread(kernel, 1, kernel_size, f) != kernel_size) {
 800         fprintf(stderr, "fread() failed\n");
 801         exit(1);
 802     }
 803     fclose(f);
 804     memcpy(setup, header, MIN(sizeof(header), setup_size));
 805
 806     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, prot_addr);
 807     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 808     fw_cfg_add_bytes(fw_cfg, FW_CFG_KERNEL_DATA, kernel, kernel_size);
 809
 810     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_ADDR, real_addr);
 811     fw_cfg_add_i32(fw_cfg, FW_CFG_SETUP_SIZE, setup_size);
 812     fw_cfg_add_bytes(fw_cfg, FW_CFG_SETUP_DATA, setup, setup_size);
 813
 814     option_rom[nb_option_roms].name = "linuxboot.bin";
 815     option_rom[nb_option_roms].bootindex = 0;
 816     nb_option_roms++;
 817 }
 818
 819 #define NE2000_NB_MAX 6
 820
 821 static const int ne2000_io[NE2000_NB_MAX] = { 0x300, 0x320, 0x340, 0x360,
 822                                               0x280, 0x380 };
 823 static const int ne2000_irq[NE2000_NB_MAX] = { 9, 10, 11, 3, 4, 5 };
 824
 825 static const int parallel_io[MAX_PARALLEL_PORTS] = { 0x378, 0x278, 0x3bc };
 826 static const int parallel_irq[MAX_PARALLEL_PORTS] = { 7, 7, 7 };
 827
 828 void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd)
 829 {
 830     static int nb_ne2k = 0;
 831
 832     if (nb_ne2k == NE2000_NB_MAX)
 833         return;
 834     isa_ne2000_init(bus, ne2000_io[nb_ne2k],
 835                     ne2000_irq[nb_ne2k], nd);
 836     nb_ne2k++;
 837 }
 838
 839 DeviceState *cpu_get_current_apic(void)
 840 {
 841     if (cpu_single_env) {
 842         return cpu_single_env->apic_state;
 843     } else {
 844         return NULL;
 845     }
 846 }
 847
 848 static DeviceState *apic_init(void *env, uint8_t apic_id)
 849 {
 850     DeviceState *dev;
 851     static int apic_mapped;
 852
 853     if (kvm_irqchip_in_kernel()) {
 854         dev = qdev_create(NULL, "kvm-apic");
 855     } else if (xen_enabled()) {
 856         dev = qdev_create(NULL, "xen-apic");
 857     } else {
 858         dev = qdev_create(NULL, "apic");
 859     }
 860
 861     qdev_prop_set_uint8(dev, "id", apic_id);
 862     qdev_prop_set_ptr(dev, "cpu_env", env);
 863     qdev_init_nofail(dev);
 864
 865     /* XXX: mapping more APICs at the same memory location */
 866     if (apic_mapped == 0) {
 867         /* NOTE: the APIC is directly connected to the CPU - it is not
 868            on the global memory bus. */
 869         /* XXX: what if the base changes? */
 870         sysbus_mmio_map(sysbus_from_qdev(dev), 0, MSI_ADDR_BASE);
 871         apic_mapped = 1;
 872     }
 873
 874     return dev;
 875 }
 876
 877 void pc_acpi_smi_interrupt(void *opaque, int irq, int level)
 878 {
 879     CPUX86State *s = opaque;
 880
 881     if (level) {
 882         cpu_interrupt(s, CPU_INTERRUPT_SMI);
 883     }
 884 }
 885
 886 static X86CPU *pc_new_cpu(const char *cpu_model)
 887 {
 888     X86CPU *cpu;
 889     CPUX86State *env;
 890
 891     cpu = cpu_x86_init(cpu_model);
 892     if (cpu == NULL) {
 893         fprintf(stderr, "Unable to find x86 CPU definition\n");
 894         exit(1);
 895     }
 896     env = &cpu->env;
 897     if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) {
 898         env->apic_state = apic_init(env, env->cpuid_apic_id);
 899     }
 900     cpu_reset(CPU(cpu));
 901     return cpu;
 902 }
 903
 904 void pc_cpus_init(const char *cpu_model)
 905 {
 906     int i;
 907
 908     /* init CPUs */
 909     if (cpu_model == NULL) {
 910 #ifdef TARGET_X86_64
 911         cpu_model = "qemu64";
 912 #else
 913         cpu_model = "qemu32";
 914 #endif
 915     }
 916
 917     for(i = 0; i < smp_cpus; i++) {
 918         pc_new_cpu(cpu_model);
 919     }
 920 }
 921
 922 void *pc_memory_init(MemoryRegion *system_memory,
 923                     const char *kernel_filename,
 924                     const char *kernel_cmdline,
 925                     const char *initrd_filename,
 926                     ram_addr_t below_4g_mem_size,
 927                     ram_addr_t above_4g_mem_size,
 928                     MemoryRegion *rom_memory,
 929                     MemoryRegion **ram_memory)
 930 {
 931     int linux_boot, i;
 932     MemoryRegion *ram, *option_rom_mr;
 933     MemoryRegion *ram_below_4g, *ram_above_4g;
 934     void *fw_cfg;
 935
 936     linux_boot = (kernel_filename != NULL);
 937
 938     /* Allocate RAM.  We allocate it as a single memory region and use
 939      * aliases to address portions of it, mostly for backwards compatibility
 940      * with older qemus that used qemu_ram_alloc().
 941      */
 942     ram = g_malloc(sizeof(*ram));
 943     memory_region_init_ram(ram, "pc.ram",
 944                            below_4g_mem_size + above_4g_mem_size);
 945     vmstate_register_ram_global(ram);
 946     *ram_memory = ram;
 947     ram_below_4g = g_malloc(sizeof(*ram_below_4g));
 948     memory_region_init_alias(ram_below_4g, "ram-below-4g", ram,
 949                              0, below_4g_mem_size);
 950     memory_region_add_subregion(system_memory, 0, ram_below_4g);
 951     if (above_4g_mem_size > 0) {
 952         ram_above_4g = g_malloc(sizeof(*ram_above_4g));
 953         memory_region_init_alias(ram_above_4g, "ram-above-4g", ram,
 954                                  below_4g_mem_size, above_4g_mem_size);
 955         memory_region_add_subregion(system_memory, 0x100000000ULL,
 956                                     ram_above_4g);
 957     }
 958
 959
 960     /* Initialize PC system firmware */
 961     pc_system_firmware_init(rom_memory);
 962
 963     option_rom_mr = g_malloc(sizeof(*option_rom_mr));
 964     memory_region_init_ram(option_rom_mr, "pc.rom", PC_ROM_SIZE);
 965     vmstate_register_ram_global(option_rom_mr);
 966     memory_region_add_subregion_overlap(rom_memory,
 967                                         PC_ROM_MIN_VGA,
 968                                         option_rom_mr,
 969                                         1);
 970
 971     fw_cfg = bochs_bios_init();
 972     rom_set_fw(fw_cfg);
 973
 974     if (linux_boot) {
 975         load_linux(fw_cfg, kernel_filename, initrd_filename, kernel_cmdline, below_4g_mem_size);
 976     }
 977
 978     for (i = 0; i < nb_option_roms; i++) {
 979         rom_add_option(option_rom[i].name, option_rom[i].bootindex);
 980     }
 981     return fw_cfg;
 982 }
 983
 984 qemu_irq *pc_allocate_cpu_irq(void)
 985 {
 986     return qemu_allocate_irqs(pic_irq_request, NULL, 1);
 987 }
 988
 989 DeviceState *pc_vga_init(ISABus *isa_bus, PCIBus *pci_bus)
 990 {
 991     DeviceState *dev = NULL;
 992
 993     if (pci_bus) {
 994         PCIDevice *pcidev = pci_vga_init(pci_bus);
 995         dev = pcidev ? &pcidev->qdev : NULL;
 996     } else if (isa_bus) {
 997         ISADevice *isadev = isa_vga_init(isa_bus);
 998         dev = isadev ? &isadev->qdev : NULL;
 999     }
1000     return dev;
1001 }
1002
1003 static void cpu_request_exit(void *opaque, int irq, int level)
1004 {
1005     CPUX86State *env = cpu_single_env;
1006
1007     if (env && level) {
1008         cpu_exit(env);
1009     }
1010 }
1011
1012 void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi,
1013                           ISADevice **rtc_state,
1014                           ISADevice **floppy,
1015                           bool no_vmport)
1016 {
1017     int i;
1018     DriveInfo *fd[MAX_FD];
1019     DeviceState *hpet = NULL;
1020     int pit_isa_irq = 0;
1021     qemu_irq pit_alt_irq = NULL;
1022     qemu_irq rtc_irq = NULL;
1023     qemu_irq *a20_line;
1024     ISADevice *i8042, *port92, *vmmouse, *pit = NULL;
1025     qemu_irq *cpu_exit_irq;
1026
1027     register_ioport_write(0x80, 1, 1, ioport80_write, NULL);
1028
1029     register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL);
1030
1031     /*
1032      * Check if an HPET shall be created.
1033      *
1034      * Without KVM_CAP_PIT_STATE2, we cannot switch off the in-kernel PIT
1035      * when the HPET wants to take over. Thus we have to disable the latter.
1036      */
1037     if (!no_hpet && (!kvm_irqchip_in_kernel() || kvm_has_pit_state2())) {
1038         hpet = sysbus_try_create_simple("hpet", HPET_BASE, NULL);
1039
1040         if (hpet) {
1041             for (i = 0; i < GSI_NUM_PINS; i++) {
1042                 sysbus_connect_irq(sysbus_from_qdev(hpet), i, gsi[i]);
1043             }
1044             pit_isa_irq = -1;
1045             pit_alt_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_PIT_INT);
1046             rtc_irq = qdev_get_gpio_in(hpet, HPET_LEGACY_RTC_INT);
1047         }
1048     }
1049     *rtc_state = rtc_init(isa_bus, 2000, rtc_irq);
1050
1051     qemu_register_boot_set(pc_boot_set, *rtc_state);
1052
1053     if (!xen_enabled()) {
1054         if (kvm_irqchip_in_kernel()) {
1055             pit = kvm_pit_init(isa_bus, 0x40);
1056         } else {
1057             pit = pit_init(isa_bus, 0x40, pit_isa_irq, pit_alt_irq);
1058         }
1059         if (hpet) {
1060             /* connect PIT to output control line of the HPET */
1061             qdev_connect_gpio_out(hpet, 0, qdev_get_gpio_in(&pit->qdev, 0));
1062         }
1063         pcspk_init(isa_bus, pit);
1064     }
1065
1066     for(i = 0; i < MAX_SERIAL_PORTS; i++) {
1067         if (serial_hds[i]) {
1068             serial_isa_init(isa_bus, i, serial_hds[i]);
1069         }
1070     }
1071
1072     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
1073         if (parallel_hds[i]) {
1074             parallel_init(isa_bus, i, parallel_hds[i]);
1075         }
1076     }
1077
1078     a20_line = qemu_allocate_irqs(handle_a20_line_change, first_cpu, 2);
1079     i8042 = isa_create_simple(isa_bus, "i8042");
1080     i8042_setup_a20_line(i8042, &a20_line[0]);
1081     if (!no_vmport) {
1082         vmport_init(isa_bus);
1083         vmmouse = isa_try_create(isa_bus, "vmmouse");
1084     } else {
1085         vmmouse = NULL;
1086     }
1087     if (vmmouse) {
1088         qdev_prop_set_ptr(&vmmouse->qdev, "ps2_mouse", i8042);
1089         qdev_init_nofail(&vmmouse->qdev);
1090     }
1091     port92 = isa_create_simple(isa_bus, "port92");
1092     port92_init(port92, &a20_line[1]);
1093
1094     cpu_exit_irq = qemu_allocate_irqs(cpu_request_exit, NULL, 1);
1095     DMA_init(0, cpu_exit_irq);
1096
1097     for(i = 0; i < MAX_FD; i++) {
1098         fd[i] = drive_get(IF_FLOPPY, 0, i);
1099     }
1100     *floppy = fdctrl_init_isa(isa_bus, fd);
1101 }
1102
1103 void pc_pci_device_init(PCIBus *pci_bus)
1104 {
1105     int max_bus;
1106     int bus;
1107
1108     max_bus = drive_get_max_bus(IF_SCSI);
1109     for (bus = 0; bus <= max_bus; bus++) {
1110         pci_create_simple(pci_bus, -1, "lsi53c895a");
1111     }
1112 }