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ide: Complete conversion from BlockDriverState to BlockBackend
[qemu-kvm.git] / hw / ide / core.c
blob44e3d502d4d0cce6275a1dc3f52a25fd630334e3
1 /*
2 * QEMU IDE disk and CD/DVD-ROM Emulator
3 *
4 * Copyright (c) 2003 Fabrice Bellard
5 * Copyright (c) 2006 Openedhand Ltd.
6 *
7 * Permission is hereby granted, free of charge, to any person obtaining a copy
8 * of this software and associated documentation files (the "Software"), to deal
9 * in the Software without restriction, including without limitation the rights
10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
11 * copies of the Software, and to permit persons to whom the Software is
12 * furnished to do so, subject to the following conditions:
13 *
14 * The above copyright notice and this permission notice shall be included in
15 * all copies or substantial portions of the Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
23 * THE SOFTWARE.
24 */
25 #include <hw/hw.h>
26 #include <hw/i386/pc.h>
27 #include <hw/pci/pci.h>
28 #include <hw/isa/isa.h>
29 #include "qemu/error-report.h"
30 #include "qemu/timer.h"
31 #include "sysemu/sysemu.h"
32 #include "sysemu/dma.h"
33 #include "hw/block/block.h"
34 #include "sysemu/block-backend.h"
35
36 #include <hw/ide/internal.h>
37
38 /* These values were based on a Seagate ST3500418AS but have been modified
39 to make more sense in QEMU */
40 static const int smart_attributes[][12] = {
41 /* id, flags, hflags, val, wrst, raw (6 bytes), threshold */
42 /* raw read error rate*/
43 { 0x01, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06},
44 /* spin up */
45 { 0x03, 0x03, 0x00, 0x64, 0x64, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
46 /* start stop count */
47 { 0x04, 0x02, 0x00, 0x64, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x14},
48 /* remapped sectors */
49 { 0x05, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x24},
50 /* power on hours */
51 { 0x09, 0x03, 0x00, 0x64, 0x64, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
52 /* power cycle count */
53 { 0x0c, 0x03, 0x00, 0x64, 0x64, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00},
54 /* airflow-temperature-celsius */
55 { 190, 0x03, 0x00, 0x45, 0x45, 0x1f, 0x00, 0x1f, 0x1f, 0x00, 0x00, 0x32},
56 };
57
58 static int ide_handle_rw_error(IDEState *s, int error, int op);
59 static void ide_dummy_transfer_stop(IDEState *s);
60
61 static void padstr(char *str, const char *src, int len)
62 {
63 int i, v;
64 for(i = 0; i < len; i++) {
65 if (*src)
66 v = *src++;
67 else
68 v = ' ';
69 str[i^1] = v;
70 }
71 }
72
73 static void put_le16(uint16_t *p, unsigned int v)
74 {
75 *p = cpu_to_le16(v);
76 }
77
78 static void ide_identify_size(IDEState *s)
79 {
80 uint16_t *p = (uint16_t *)s->identify_data;
81 put_le16(p + 60, s->nb_sectors);
82 put_le16(p + 61, s->nb_sectors >> 16);
83 put_le16(p + 100, s->nb_sectors);
84 put_le16(p + 101, s->nb_sectors >> 16);
85 put_le16(p + 102, s->nb_sectors >> 32);
86 put_le16(p + 103, s->nb_sectors >> 48);
87 }
88
89 static void ide_identify(IDEState *s)
90 {
91 uint16_t *p;
92 unsigned int oldsize;
93 IDEDevice *dev = s->unit ? s->bus->slave : s->bus->master;
94
95 p = (uint16_t *)s->identify_data;
96 if (s->identify_set) {
97 goto fill_buffer;
98 }
99 memset(p, 0, sizeof(s->identify_data));
100
101 put_le16(p + 0, 0x0040);
102 put_le16(p + 1, s->cylinders);
103 put_le16(p + 3, s->heads);
104 put_le16(p + 4, 512 * s->sectors); /* XXX: retired, remove ? */
105 put_le16(p + 5, 512); /* XXX: retired, remove ? */
106 put_le16(p + 6, s->sectors);
107 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
108 put_le16(p + 20, 3); /* XXX: retired, remove ? */
109 put_le16(p + 21, 512); /* cache size in sectors */
110 put_le16(p + 22, 4); /* ecc bytes */
111 padstr((char *)(p + 23), s->version, 8); /* firmware version */
112 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
113 #if MAX_MULT_SECTORS > 1
114 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
115 #endif
116 put_le16(p + 48, 1); /* dword I/O */
117 put_le16(p + 49, (1 << 11) | (1 << 9) | (1 << 8)); /* DMA and LBA supported */
118 put_le16(p + 51, 0x200); /* PIO transfer cycle */
119 put_le16(p + 52, 0x200); /* DMA transfer cycle */
120 put_le16(p + 53, 1 | (1 << 1) | (1 << 2)); /* words 54-58,64-70,88 are valid */
121 put_le16(p + 54, s->cylinders);
122 put_le16(p + 55, s->heads);
123 put_le16(p + 56, s->sectors);
124 oldsize = s->cylinders * s->heads * s->sectors;
125 put_le16(p + 57, oldsize);
126 put_le16(p + 58, oldsize >> 16);
127 if (s->mult_sectors)
128 put_le16(p + 59, 0x100 | s->mult_sectors);
129 /* *(p + 60) := nb_sectors -- see ide_identify_size */
130 /* *(p + 61) := nb_sectors >> 16 -- see ide_identify_size */
131 put_le16(p + 62, 0x07); /* single word dma0-2 supported */
132 put_le16(p + 63, 0x07); /* mdma0-2 supported */
133 put_le16(p + 64, 0x03); /* pio3-4 supported */
134 put_le16(p + 65, 120);
135 put_le16(p + 66, 120);
136 put_le16(p + 67, 120);
137 put_le16(p + 68, 120);
138 if (dev && dev->conf.discard_granularity) {
139 put_le16(p + 69, (1 << 14)); /* determinate TRIM behavior */
140 }
141
142 if (s->ncq_queues) {
143 put_le16(p + 75, s->ncq_queues - 1);
144 /* NCQ supported */
145 put_le16(p + 76, (1 << 8));
146 }
147
148 put_le16(p + 80, 0xf0); /* ata3 -> ata6 supported */
149 put_le16(p + 81, 0x16); /* conforms to ata5 */
150 /* 14=NOP supported, 5=WCACHE supported, 0=SMART supported */
151 put_le16(p + 82, (1 << 14) | (1 << 5) | 1);
152 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
153 put_le16(p + 83, (1 << 14) | (1 << 13) | (1 <<12) | (1 << 10));
154 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
155 if (s->wwn) {
156 put_le16(p + 84, (1 << 14) | (1 << 8) | 0);
157 } else {
158 put_le16(p + 84, (1 << 14) | 0);
159 }
160 /* 14 = NOP supported, 5=WCACHE enabled, 0=SMART feature set enabled */
161 if (blk_enable_write_cache(s->blk)) {
162 put_le16(p + 85, (1 << 14) | (1 << 5) | 1);
163 } else {
164 put_le16(p + 85, (1 << 14) | 1);
165 }
166 /* 13=flush_cache_ext,12=flush_cache,10=lba48 */
167 put_le16(p + 86, (1 << 13) | (1 <<12) | (1 << 10));
168 /* 14=set to 1, 8=has WWN, 1=SMART self test, 0=SMART error logging */
169 if (s->wwn) {
170 put_le16(p + 87, (1 << 14) | (1 << 8) | 0);
171 } else {
172 put_le16(p + 87, (1 << 14) | 0);
173 }
174 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
175 put_le16(p + 93, 1 | (1 << 14) | 0x2000);
176 /* *(p + 100) := nb_sectors -- see ide_identify_size */
177 /* *(p + 101) := nb_sectors >> 16 -- see ide_identify_size */
178 /* *(p + 102) := nb_sectors >> 32 -- see ide_identify_size */
179 /* *(p + 103) := nb_sectors >> 48 -- see ide_identify_size */
180
181 if (dev && dev->conf.physical_block_size)
182 put_le16(p + 106, 0x6000 | get_physical_block_exp(&dev->conf));
183 if (s->wwn) {
184 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
185 put_le16(p + 108, s->wwn >> 48);
186 put_le16(p + 109, s->wwn >> 32);
187 put_le16(p + 110, s->wwn >> 16);
188 put_le16(p + 111, s->wwn);
189 }
190 if (dev && dev->conf.discard_granularity) {
191 put_le16(p + 169, 1); /* TRIM support */
192 }
193
194 ide_identify_size(s);
195 s->identify_set = 1;
196
197 fill_buffer:
198 memcpy(s->io_buffer, p, sizeof(s->identify_data));
199 }
200
201 static void ide_atapi_identify(IDEState *s)
202 {
203 uint16_t *p;
204
205 p = (uint16_t *)s->identify_data;
206 if (s->identify_set) {
207 goto fill_buffer;
208 }
209 memset(p, 0, sizeof(s->identify_data));
210
211 /* Removable CDROM, 50us response, 12 byte packets */
212 put_le16(p + 0, (2 << 14) | (5 << 8) | (1 << 7) | (2 << 5) | (0 << 0));
213 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
214 put_le16(p + 20, 3); /* buffer type */
215 put_le16(p + 21, 512); /* cache size in sectors */
216 put_le16(p + 22, 4); /* ecc bytes */
217 padstr((char *)(p + 23), s->version, 8); /* firmware version */
218 padstr((char *)(p + 27), s->drive_model_str, 40); /* model */
219 put_le16(p + 48, 1); /* dword I/O (XXX: should not be set on CDROM) */
220 #ifdef USE_DMA_CDROM
221 put_le16(p + 49, 1 << 9 | 1 << 8); /* DMA and LBA supported */
222 put_le16(p + 53, 7); /* words 64-70, 54-58, 88 valid */
223 put_le16(p + 62, 7); /* single word dma0-2 supported */
224 put_le16(p + 63, 7); /* mdma0-2 supported */
225 #else
226 put_le16(p + 49, 1 << 9); /* LBA supported, no DMA */
227 put_le16(p + 53, 3); /* words 64-70, 54-58 valid */
228 put_le16(p + 63, 0x103); /* DMA modes XXX: may be incorrect */
229 #endif
230 put_le16(p + 64, 3); /* pio3-4 supported */
231 put_le16(p + 65, 0xb4); /* minimum DMA multiword tx cycle time */
232 put_le16(p + 66, 0xb4); /* recommended DMA multiword tx cycle time */
233 put_le16(p + 67, 0x12c); /* minimum PIO cycle time without flow control */
234 put_le16(p + 68, 0xb4); /* minimum PIO cycle time with IORDY flow control */
235
236 put_le16(p + 71, 30); /* in ns */
237 put_le16(p + 72, 30); /* in ns */
238
239 if (s->ncq_queues) {
240 put_le16(p + 75, s->ncq_queues - 1);
241 /* NCQ supported */
242 put_le16(p + 76, (1 << 8));
243 }
244
245 put_le16(p + 80, 0x1e); /* support up to ATA/ATAPI-4 */
246 if (s->wwn) {
247 put_le16(p + 84, (1 << 8)); /* supports WWN for words 108-111 */
248 put_le16(p + 87, (1 << 8)); /* WWN enabled */
249 }
250
251 #ifdef USE_DMA_CDROM
252 put_le16(p + 88, 0x3f | (1 << 13)); /* udma5 set and supported */
253 #endif
254
255 if (s->wwn) {
256 /* LE 16-bit words 111-108 contain 64-bit World Wide Name */
257 put_le16(p + 108, s->wwn >> 48);
258 put_le16(p + 109, s->wwn >> 32);
259 put_le16(p + 110, s->wwn >> 16);
260 put_le16(p + 111, s->wwn);
261 }
262
263 s->identify_set = 1;
264
265 fill_buffer:
266 memcpy(s->io_buffer, p, sizeof(s->identify_data));
267 }
268
269 static void ide_cfata_identify_size(IDEState *s)
270 {
271 uint16_t *p = (uint16_t *)s->identify_data;
272 put_le16(p + 7, s->nb_sectors >> 16); /* Sectors per card */
273 put_le16(p + 8, s->nb_sectors); /* Sectors per card */
274 put_le16(p + 60, s->nb_sectors); /* Total LBA sectors */
275 put_le16(p + 61, s->nb_sectors >> 16); /* Total LBA sectors */
276 }
277
278 static void ide_cfata_identify(IDEState *s)
279 {
280 uint16_t *p;
281 uint32_t cur_sec;
282
283 p = (uint16_t *)s->identify_data;
284 if (s->identify_set) {
285 goto fill_buffer;
286 }
287 memset(p, 0, sizeof(s->identify_data));
288
289 cur_sec = s->cylinders * s->heads * s->sectors;
290
291 put_le16(p + 0, 0x848a); /* CF Storage Card signature */
292 put_le16(p + 1, s->cylinders); /* Default cylinders */
293 put_le16(p + 3, s->heads); /* Default heads */
294 put_le16(p + 6, s->sectors); /* Default sectors per track */
295 /* *(p + 7) := nb_sectors >> 16 -- see ide_cfata_identify_size */
296 /* *(p + 8) := nb_sectors -- see ide_cfata_identify_size */
297 padstr((char *)(p + 10), s->drive_serial_str, 20); /* serial number */
298 put_le16(p + 22, 0x0004); /* ECC bytes */
299 padstr((char *) (p + 23), s->version, 8); /* Firmware Revision */
300 padstr((char *) (p + 27), s->drive_model_str, 40);/* Model number */
301 #if MAX_MULT_SECTORS > 1
302 put_le16(p + 47, 0x8000 | MAX_MULT_SECTORS);
303 #else
304 put_le16(p + 47, 0x0000);
305 #endif
306 put_le16(p + 49, 0x0f00); /* Capabilities */
307 put_le16(p + 51, 0x0002); /* PIO cycle timing mode */
308 put_le16(p + 52, 0x0001); /* DMA cycle timing mode */
309 put_le16(p + 53, 0x0003); /* Translation params valid */
310 put_le16(p + 54, s->cylinders); /* Current cylinders */
311 put_le16(p + 55, s->heads); /* Current heads */
312 put_le16(p + 56, s->sectors); /* Current sectors */
313 put_le16(p + 57, cur_sec); /* Current capacity */
314 put_le16(p + 58, cur_sec >> 16); /* Current capacity */
315 if (s->mult_sectors) /* Multiple sector setting */
316 put_le16(p + 59, 0x100 | s->mult_sectors);
317 /* *(p + 60) := nb_sectors -- see ide_cfata_identify_size */
318 /* *(p + 61) := nb_sectors >> 16 -- see ide_cfata_identify_size */
319 put_le16(p + 63, 0x0203); /* Multiword DMA capability */
320 put_le16(p + 64, 0x0001); /* Flow Control PIO support */
321 put_le16(p + 65, 0x0096); /* Min. Multiword DMA cycle */
322 put_le16(p + 66, 0x0096); /* Rec. Multiword DMA cycle */
323 put_le16(p + 68, 0x00b4); /* Min. PIO cycle time */
324 put_le16(p + 82, 0x400c); /* Command Set supported */
325 put_le16(p + 83, 0x7068); /* Command Set supported */
326 put_le16(p + 84, 0x4000); /* Features supported */
327 put_le16(p + 85, 0x000c); /* Command Set enabled */
328 put_le16(p + 86, 0x7044); /* Command Set enabled */
329 put_le16(p + 87, 0x4000); /* Features enabled */
330 put_le16(p + 91, 0x4060); /* Current APM level */
331 put_le16(p + 129, 0x0002); /* Current features option */
332 put_le16(p + 130, 0x0005); /* Reassigned sectors */
333 put_le16(p + 131, 0x0001); /* Initial power mode */
334 put_le16(p + 132, 0x0000); /* User signature */
335 put_le16(p + 160, 0x8100); /* Power requirement */
336 put_le16(p + 161, 0x8001); /* CF command set */
337
338 ide_cfata_identify_size(s);
339 s->identify_set = 1;
340
341 fill_buffer:
342 memcpy(s->io_buffer, p, sizeof(s->identify_data));
343 }
344
345 static void ide_set_signature(IDEState *s)
346 {
347 s->select &= 0xf0; /* clear head */
348 /* put signature */
349 s->nsector = 1;
350 s->sector = 1;
351 if (s->drive_kind == IDE_CD) {
352 s->lcyl = 0x14;
353 s->hcyl = 0xeb;
354 } else if (s->blk) {
355 s->lcyl = 0;
356 s->hcyl = 0;
357 } else {
358 s->lcyl = 0xff;
359 s->hcyl = 0xff;
360 }
361 }
362
363 typedef struct TrimAIOCB {
364 BlockAIOCB common;
365 BlockBackend *blk;
366 QEMUBH *bh;
367 int ret;
368 QEMUIOVector *qiov;
369 BlockAIOCB *aiocb;
370 int i, j;
371 } TrimAIOCB;
372
373 static void trim_aio_cancel(BlockAIOCB *acb)
374 {
375 TrimAIOCB *iocb = container_of(acb, TrimAIOCB, common);
376
377 /* Exit the loop so ide_issue_trim_cb will not continue */
378 iocb->j = iocb->qiov->niov - 1;
379 iocb->i = (iocb->qiov->iov[iocb->j].iov_len / 8) - 1;
380
381 iocb->ret = -ECANCELED;
382
383 if (iocb->aiocb) {
384 blk_aio_cancel_async(iocb->aiocb);
385 iocb->aiocb = NULL;
386 }
387 }
388
389 static const AIOCBInfo trim_aiocb_info = {
390 .aiocb_size = sizeof(TrimAIOCB),
391 .cancel_async = trim_aio_cancel,
392 };
393
394 static void ide_trim_bh_cb(void *opaque)
395 {
396 TrimAIOCB *iocb = opaque;
397
398 iocb->common.cb(iocb->common.opaque, iocb->ret);
399
400 qemu_bh_delete(iocb->bh);
401 iocb->bh = NULL;
402 qemu_aio_unref(iocb);
403 }
404
405 static void ide_issue_trim_cb(void *opaque, int ret)
406 {
407 TrimAIOCB *iocb = opaque;
408 if (ret >= 0) {
409 while (iocb->j < iocb->qiov->niov) {
410 int j = iocb->j;
411 while (++iocb->i < iocb->qiov->iov[j].iov_len / 8) {
412 int i = iocb->i;
413 uint64_t *buffer = iocb->qiov->iov[j].iov_base;
414
415 /* 6-byte LBA + 2-byte range per entry */
416 uint64_t entry = le64_to_cpu(buffer[i]);
417 uint64_t sector = entry & 0x0000ffffffffffffULL;
418 uint16_t count = entry >> 48;
419
420 if (count == 0) {
421 continue;
422 }
423
424 /* Got an entry! Submit and exit. */
425 iocb->aiocb = blk_aio_discard(iocb->blk, sector, count,
426 ide_issue_trim_cb, opaque);
427 return;
428 }
429
430 iocb->j++;
431 iocb->i = -1;
432 }
433 } else {
434 iocb->ret = ret;
435 }
436
437 iocb->aiocb = NULL;
438 if (iocb->bh) {
439 qemu_bh_schedule(iocb->bh);
440 }
441 }
442
443 BlockAIOCB *ide_issue_trim(BlockBackend *blk,
444 int64_t sector_num, QEMUIOVector *qiov, int nb_sectors,
445 BlockCompletionFunc *cb, void *opaque)
446 {
447 TrimAIOCB *iocb;
448
449 iocb = blk_aio_get(&trim_aiocb_info, blk, cb, opaque);
450 iocb->blk = blk;
451 iocb->bh = qemu_bh_new(ide_trim_bh_cb, iocb);
452 iocb->ret = 0;
453 iocb->qiov = qiov;
454 iocb->i = -1;
455 iocb->j = 0;
456 ide_issue_trim_cb(iocb, 0);
457 return &iocb->common;
458 }
459
460 static inline void ide_abort_command(IDEState *s)
461 {
462 ide_transfer_stop(s);
463 s->status = READY_STAT | ERR_STAT;
464 s->error = ABRT_ERR;
465 }
466
467 /* prepare data transfer and tell what to do after */
468 void ide_transfer_start(IDEState *s, uint8_t *buf, int size,
469 EndTransferFunc *end_transfer_func)
470 {
471 s->end_transfer_func = end_transfer_func;
472 s->data_ptr = buf;
473 s->data_end = buf + size;
474 if (!(s->status & ERR_STAT)) {
475 s->status |= DRQ_STAT;
476 }
477 if (s->bus->dma->ops->start_transfer) {
478 s->bus->dma->ops->start_transfer(s->bus->dma);
479 }
480 }
481
482 static void ide_cmd_done(IDEState *s)
483 {
484 if (s->bus->dma->ops->cmd_done) {
485 s->bus->dma->ops->cmd_done(s->bus->dma);
486 }
487 }
488
489 void ide_transfer_stop(IDEState *s)
490 {
491 s->end_transfer_func = ide_transfer_stop;
492 s->data_ptr = s->io_buffer;
493 s->data_end = s->io_buffer;
494 s->status &= ~DRQ_STAT;
495 ide_cmd_done(s);
496 }
497
498 int64_t ide_get_sector(IDEState *s)
499 {
500 int64_t sector_num;
501 if (s->select & 0x40) {
502 /* lba */
503 if (!s->lba48) {
504 sector_num = ((s->select & 0x0f) << 24) | (s->hcyl << 16) |
505 (s->lcyl << 8) | s->sector;
506 } else {
507 sector_num = ((int64_t)s->hob_hcyl << 40) |
508 ((int64_t) s->hob_lcyl << 32) |
509 ((int64_t) s->hob_sector << 24) |
510 ((int64_t) s->hcyl << 16) |
511 ((int64_t) s->lcyl << 8) | s->sector;
512 }
513 } else {
514 sector_num = ((s->hcyl << 8) | s->lcyl) * s->heads * s->sectors +
515 (s->select & 0x0f) * s->sectors + (s->sector - 1);
516 }
517 return sector_num;
518 }
519
520 void ide_set_sector(IDEState *s, int64_t sector_num)
521 {
522 unsigned int cyl, r;
523 if (s->select & 0x40) {
524 if (!s->lba48) {
525 s->select = (s->select & 0xf0) | (sector_num >> 24);
526 s->hcyl = (sector_num >> 16);
527 s->lcyl = (sector_num >> 8);
528 s->sector = (sector_num);
529 } else {
530 s->sector = sector_num;
531 s->lcyl = sector_num >> 8;
532 s->hcyl = sector_num >> 16;
533 s->hob_sector = sector_num >> 24;
534 s->hob_lcyl = sector_num >> 32;
535 s->hob_hcyl = sector_num >> 40;
536 }
537 } else {
538 cyl = sector_num / (s->heads * s->sectors);
539 r = sector_num % (s->heads * s->sectors);
540 s->hcyl = cyl >> 8;
541 s->lcyl = cyl;
542 s->select = (s->select & 0xf0) | ((r / s->sectors) & 0x0f);
543 s->sector = (r % s->sectors) + 1;
544 }
545 }
546
547 static void ide_rw_error(IDEState *s) {
548 ide_abort_command(s);
549 ide_set_irq(s->bus);
550 }
551
552 static bool ide_sect_range_ok(IDEState *s,
553 uint64_t sector, uint64_t nb_sectors)
554 {
555 uint64_t total_sectors;
556
557 blk_get_geometry(s->blk, &total_sectors);
558 if (sector > total_sectors || nb_sectors > total_sectors - sector) {
559 return false;
560 }
561 return true;
562 }
563
564 static void ide_sector_read_cb(void *opaque, int ret)
565 {
566 IDEState *s = opaque;
567 int n;
568
569 s->pio_aiocb = NULL;
570 s->status &= ~BUSY_STAT;
571
572 if (ret == -ECANCELED) {
573 return;
574 }
575 block_acct_done(blk_get_stats(s->blk), &s->acct);
576 if (ret != 0) {
577 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO |
578 IDE_RETRY_READ)) {
579 return;
580 }
581 }
582
583 n = s->nsector;
584 if (n > s->req_nb_sectors) {
585 n = s->req_nb_sectors;
586 }
587
588 /* Allow the guest to read the io_buffer */
589 ide_transfer_start(s, s->io_buffer, n * BDRV_SECTOR_SIZE, ide_sector_read);
590
591 ide_set_irq(s->bus);
592
593 ide_set_sector(s, ide_get_sector(s) + n);
594 s->nsector -= n;
595 }
596
597 void ide_sector_read(IDEState *s)
598 {
599 int64_t sector_num;
600 int n;
601
602 s->status = READY_STAT | SEEK_STAT;
603 s->error = 0; /* not needed by IDE spec, but needed by Windows */
604 sector_num = ide_get_sector(s);
605 n = s->nsector;
606
607 if (n == 0) {
608 ide_transfer_stop(s);
609 return;
610 }
611
612 s->status |= BUSY_STAT;
613
614 if (n > s->req_nb_sectors) {
615 n = s->req_nb_sectors;
616 }
617
618 #if defined(DEBUG_IDE)
619 printf("sector=%" PRId64 "\n", sector_num);
620 #endif
621
622 if (!ide_sect_range_ok(s, sector_num, n)) {
623 ide_rw_error(s);
624 return;
625 }
626
627 s->iov.iov_base = s->io_buffer;
628 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
629 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
630
631 block_acct_start(blk_get_stats(s->blk), &s->acct,
632 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
633 s->pio_aiocb = blk_aio_readv(s->blk, sector_num, &s->qiov, n,
634 ide_sector_read_cb, s);
635 }
636
637 static void dma_buf_commit(IDEState *s)
638 {
639 qemu_sglist_destroy(&s->sg);
640 }
641
642 void ide_set_inactive(IDEState *s, bool more)
643 {
644 s->bus->dma->aiocb = NULL;
645 if (s->bus->dma->ops->set_inactive) {
646 s->bus->dma->ops->set_inactive(s->bus->dma, more);
647 }
648 ide_cmd_done(s);
649 }
650
651 void ide_dma_error(IDEState *s)
652 {
653 ide_abort_command(s);
654 ide_set_inactive(s, false);
655 ide_set_irq(s->bus);
656 }
657
658 static int ide_handle_rw_error(IDEState *s, int error, int op)
659 {
660 bool is_read = (op & IDE_RETRY_READ) != 0;
661 BlockErrorAction action = blk_get_error_action(s->blk, is_read, error);
662
663 if (action == BLOCK_ERROR_ACTION_STOP) {
664 s->bus->dma->ops->set_unit(s->bus->dma, s->unit);
665 s->bus->error_status = op;
666 } else if (action == BLOCK_ERROR_ACTION_REPORT) {
667 if (op & IDE_RETRY_DMA) {
668 dma_buf_commit(s);
669 ide_dma_error(s);
670 } else {
671 ide_rw_error(s);
672 }
673 }
674 blk_error_action(s->blk, action, is_read, error);
675 return action != BLOCK_ERROR_ACTION_IGNORE;
676 }
677
678 void ide_dma_cb(void *opaque, int ret)
679 {
680 IDEState *s = opaque;
681 int n;
682 int64_t sector_num;
683 bool stay_active = false;
684
685 if (ret == -ECANCELED) {
686 return;
687 }
688 if (ret < 0) {
689 int op = IDE_RETRY_DMA;
690
691 if (s->dma_cmd == IDE_DMA_READ)
692 op |= IDE_RETRY_READ;
693 else if (s->dma_cmd == IDE_DMA_TRIM)
694 op |= IDE_RETRY_TRIM;
695
696 if (ide_handle_rw_error(s, -ret, op)) {
697 return;
698 }
699 }
700
701 n = s->io_buffer_size >> 9;
702 if (n > s->nsector) {
703 /* The PRDs were longer than needed for this request. Shorten them so
704 * we don't get a negative remainder. The Active bit must remain set
705 * after the request completes. */
706 n = s->nsector;
707 stay_active = true;
708 }
709
710 sector_num = ide_get_sector(s);
711 if (n > 0) {
712 dma_buf_commit(s);
713 sector_num += n;
714 ide_set_sector(s, sector_num);
715 s->nsector -= n;
716 }
717
718 /* end of transfer ? */
719 if (s->nsector == 0) {
720 s->status = READY_STAT | SEEK_STAT;
721 ide_set_irq(s->bus);
722 goto eot;
723 }
724
725 /* launch next transfer */
726 n = s->nsector;
727 s->io_buffer_index = 0;
728 s->io_buffer_size = n * 512;
729 if (s->bus->dma->ops->prepare_buf(s->bus->dma, ide_cmd_is_read(s)) == 0) {
730 /* The PRDs were too short. Reset the Active bit, but don't raise an
731 * interrupt. */
732 s->status = READY_STAT | SEEK_STAT;
733 goto eot;
734 }
735
736 #ifdef DEBUG_AIO
737 printf("ide_dma_cb: sector_num=%" PRId64 " n=%d, cmd_cmd=%d\n",
738 sector_num, n, s->dma_cmd);
739 #endif
740
741 if ((s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) &&
742 !ide_sect_range_ok(s, sector_num, n)) {
743 dma_buf_commit(s);
744 ide_dma_error(s);
745 return;
746 }
747
748 switch (s->dma_cmd) {
749 case IDE_DMA_READ:
750 s->bus->dma->aiocb = dma_blk_read(s->blk, &s->sg, sector_num,
751 ide_dma_cb, s);
752 break;
753 case IDE_DMA_WRITE:
754 s->bus->dma->aiocb = dma_blk_write(s->blk, &s->sg, sector_num,
755 ide_dma_cb, s);
756 break;
757 case IDE_DMA_TRIM:
758 s->bus->dma->aiocb = dma_blk_io(s->blk, &s->sg, sector_num,
759 ide_issue_trim, ide_dma_cb, s,
760 DMA_DIRECTION_TO_DEVICE);
761 break;
762 }
763 return;
764
765 eot:
766 if (s->dma_cmd == IDE_DMA_READ || s->dma_cmd == IDE_DMA_WRITE) {
767 block_acct_done(blk_get_stats(s->blk), &s->acct);
768 }
769 ide_set_inactive(s, stay_active);
770 }
771
772 static void ide_sector_start_dma(IDEState *s, enum ide_dma_cmd dma_cmd)
773 {
774 s->status = READY_STAT | SEEK_STAT | DRQ_STAT | BUSY_STAT;
775 s->io_buffer_index = 0;
776 s->io_buffer_size = 0;
777 s->dma_cmd = dma_cmd;
778
779 switch (dma_cmd) {
780 case IDE_DMA_READ:
781 block_acct_start(blk_get_stats(s->blk), &s->acct,
782 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
783 break;
784 case IDE_DMA_WRITE:
785 block_acct_start(blk_get_stats(s->blk), &s->acct,
786 s->nsector * BDRV_SECTOR_SIZE, BLOCK_ACCT_WRITE);
787 break;
788 default:
789 break;
790 }
791
792 ide_start_dma(s, ide_dma_cb);
793 }
794
795 void ide_start_dma(IDEState *s, BlockCompletionFunc *cb)
796 {
797 if (s->bus->dma->ops->start_dma) {
798 s->bus->dma->ops->start_dma(s->bus->dma, s, cb);
799 }
800 }
801
802 static void ide_sector_write_timer_cb(void *opaque)
803 {
804 IDEState *s = opaque;
805 ide_set_irq(s->bus);
806 }
807
808 static void ide_sector_write_cb(void *opaque, int ret)
809 {
810 IDEState *s = opaque;
811 int n;
812
813 if (ret == -ECANCELED) {
814 return;
815 }
816 block_acct_done(blk_get_stats(s->blk), &s->acct);
817
818 s->pio_aiocb = NULL;
819 s->status &= ~BUSY_STAT;
820
821 if (ret != 0) {
822 if (ide_handle_rw_error(s, -ret, IDE_RETRY_PIO)) {
823 return;
824 }
825 }
826
827 n = s->nsector;
828 if (n > s->req_nb_sectors) {
829 n = s->req_nb_sectors;
830 }
831 s->nsector -= n;
832 if (s->nsector == 0) {
833 /* no more sectors to write */
834 ide_transfer_stop(s);
835 } else {
836 int n1 = s->nsector;
837 if (n1 > s->req_nb_sectors) {
838 n1 = s->req_nb_sectors;
839 }
840 ide_transfer_start(s, s->io_buffer, n1 * BDRV_SECTOR_SIZE,
841 ide_sector_write);
842 }
843 ide_set_sector(s, ide_get_sector(s) + n);
844
845 if (win2k_install_hack && ((++s->irq_count % 16) == 0)) {
846 /* It seems there is a bug in the Windows 2000 installer HDD
847 IDE driver which fills the disk with empty logs when the
848 IDE write IRQ comes too early. This hack tries to correct
849 that at the expense of slower write performances. Use this
850 option _only_ to install Windows 2000. You must disable it
851 for normal use. */
852 timer_mod(s->sector_write_timer,
853 qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + (get_ticks_per_sec() / 1000));
854 } else {
855 ide_set_irq(s->bus);
856 }
857 }
858
859 void ide_sector_write(IDEState *s)
860 {
861 int64_t sector_num;
862 int n;
863
864 s->status = READY_STAT | SEEK_STAT | BUSY_STAT;
865 sector_num = ide_get_sector(s);
866 #if defined(DEBUG_IDE)
867 printf("sector=%" PRId64 "\n", sector_num);
868 #endif
869 n = s->nsector;
870 if (n > s->req_nb_sectors) {
871 n = s->req_nb_sectors;
872 }
873
874 if (!ide_sect_range_ok(s, sector_num, n)) {
875 ide_rw_error(s);
876 return;
877 }
878
879 s->iov.iov_base = s->io_buffer;
880 s->iov.iov_len = n * BDRV_SECTOR_SIZE;
881 qemu_iovec_init_external(&s->qiov, &s->iov, 1);
882
883 block_acct_start(blk_get_stats(s->blk), &s->acct,
884 n * BDRV_SECTOR_SIZE, BLOCK_ACCT_READ);
885 s->pio_aiocb = blk_aio_writev(s->blk, sector_num, &s->qiov, n,
886 ide_sector_write_cb, s);
887 }
888
889 static void ide_flush_cb(void *opaque, int ret)
890 {
891 IDEState *s = opaque;
892
893 s->pio_aiocb = NULL;
894
895 if (ret == -ECANCELED) {
896 return;
897 }
898 if (ret < 0) {
899 /* XXX: What sector number to set here? */
900 if (ide_handle_rw_error(s, -ret, IDE_RETRY_FLUSH)) {
901 return;
902 }
903 }
904
905 if (s->blk) {
906 block_acct_done(blk_get_stats(s->blk), &s->acct);
907 }
908 s->status = READY_STAT | SEEK_STAT;
909 ide_cmd_done(s);
910 ide_set_irq(s->bus);
911 }
912
913 void ide_flush_cache(IDEState *s)
914 {
915 if (s->blk == NULL) {
916 ide_flush_cb(s, 0);
917 return;
918 }
919
920 s->status |= BUSY_STAT;
921 block_acct_start(blk_get_stats(s->blk), &s->acct, 0, BLOCK_ACCT_FLUSH);
922 s->pio_aiocb = blk_aio_flush(s->blk, ide_flush_cb, s);
923 }
924
925 static void ide_cfata_metadata_inquiry(IDEState *s)
926 {
927 uint16_t *p;
928 uint32_t spd;
929
930 p = (uint16_t *) s->io_buffer;
931 memset(p, 0, 0x200);
932 spd = ((s->mdata_size - 1) >> 9) + 1;
933
934 put_le16(p + 0, 0x0001); /* Data format revision */
935 put_le16(p + 1, 0x0000); /* Media property: silicon */
936 put_le16(p + 2, s->media_changed); /* Media status */
937 put_le16(p + 3, s->mdata_size & 0xffff); /* Capacity in bytes (low) */
938 put_le16(p + 4, s->mdata_size >> 16); /* Capacity in bytes (high) */
939 put_le16(p + 5, spd & 0xffff); /* Sectors per device (low) */
940 put_le16(p + 6, spd >> 16); /* Sectors per device (high) */
941 }
942
943 static void ide_cfata_metadata_read(IDEState *s)
944 {
945 uint16_t *p;
946
947 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
948 s->status = ERR_STAT;
949 s->error = ABRT_ERR;
950 return;
951 }
952
953 p = (uint16_t *) s->io_buffer;
954 memset(p, 0, 0x200);
955
956 put_le16(p + 0, s->media_changed); /* Media status */
957 memcpy(p + 1, s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
958 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
959 s->nsector << 9), 0x200 - 2));
960 }
961
962 static void ide_cfata_metadata_write(IDEState *s)
963 {
964 if (((s->hcyl << 16) | s->lcyl) << 9 > s->mdata_size + 2) {
965 s->status = ERR_STAT;
966 s->error = ABRT_ERR;
967 return;
968 }
969
970 s->media_changed = 0;
971
972 memcpy(s->mdata_storage + (((s->hcyl << 16) | s->lcyl) << 9),
973 s->io_buffer + 2,
974 MIN(MIN(s->mdata_size - (((s->hcyl << 16) | s->lcyl) << 9),
975 s->nsector << 9), 0x200 - 2));
976 }
977
978 /* called when the inserted state of the media has changed */
979 static void ide_cd_change_cb(void *opaque, bool load)
980 {
981 IDEState *s = opaque;
982 uint64_t nb_sectors;
983
984 s->tray_open = !load;
985 blk_get_geometry(s->blk, &nb_sectors);
986 s->nb_sectors = nb_sectors;
987
988 /*
989 * First indicate to the guest that a CD has been removed. That's
990 * done on the next command the guest sends us.
991 *
992 * Then we set UNIT_ATTENTION, by which the guest will
993 * detect a new CD in the drive. See ide_atapi_cmd() for details.
994 */
995 s->cdrom_changed = 1;
996 s->events.new_media = true;
997 s->events.eject_request = false;
998 ide_set_irq(s->bus);
999 }
1000
1001 static void ide_cd_eject_request_cb(void *opaque, bool force)
1002 {
1003 IDEState *s = opaque;
1004
1005 s->events.eject_request = true;
1006 if (force) {
1007 s->tray_locked = false;
1008 }
1009 ide_set_irq(s->bus);
1010 }
1011
1012 static void ide_cmd_lba48_transform(IDEState *s, int lba48)
1013 {
1014 s->lba48 = lba48;
1015
1016 /* handle the 'magic' 0 nsector count conversion here. to avoid
1017 * fiddling with the rest of the read logic, we just store the
1018 * full sector count in ->nsector and ignore ->hob_nsector from now
1019 */
1020 if (!s->lba48) {
1021 if (!s->nsector)
1022 s->nsector = 256;
1023 } else {
1024 if (!s->nsector && !s->hob_nsector)
1025 s->nsector = 65536;
1026 else {
1027 int lo = s->nsector;
1028 int hi = s->hob_nsector;
1029
1030 s->nsector = (hi << 8) | lo;
1031 }
1032 }
1033 }
1034
1035 static void ide_clear_hob(IDEBus *bus)
1036 {
1037 /* any write clears HOB high bit of device control register */
1038 bus->ifs[0].select &= ~(1 << 7);
1039 bus->ifs[1].select &= ~(1 << 7);
1040 }
1041
1042 void ide_ioport_write(void *opaque, uint32_t addr, uint32_t val)
1043 {
1044 IDEBus *bus = opaque;
1045
1046 #ifdef DEBUG_IDE
1047 printf("IDE: write addr=0x%x val=0x%02x\n", addr, val);
1048 #endif
1049
1050 addr &= 7;
1051
1052 /* ignore writes to command block while busy with previous command */
1053 if (addr != 7 && (idebus_active_if(bus)->status & (BUSY_STAT|DRQ_STAT)))
1054 return;
1055
1056 switch(addr) {
1057 case 0:
1058 break;
1059 case 1:
1060 ide_clear_hob(bus);
1061 /* NOTE: data is written to the two drives */
1062 bus->ifs[0].hob_feature = bus->ifs[0].feature;
1063 bus->ifs[1].hob_feature = bus->ifs[1].feature;
1064 bus->ifs[0].feature = val;
1065 bus->ifs[1].feature = val;
1066 break;
1067 case 2:
1068 ide_clear_hob(bus);
1069 bus->ifs[0].hob_nsector = bus->ifs[0].nsector;
1070 bus->ifs[1].hob_nsector = bus->ifs[1].nsector;
1071 bus->ifs[0].nsector = val;
1072 bus->ifs[1].nsector = val;
1073 break;
1074 case 3:
1075 ide_clear_hob(bus);
1076 bus->ifs[0].hob_sector = bus->ifs[0].sector;
1077 bus->ifs[1].hob_sector = bus->ifs[1].sector;
1078 bus->ifs[0].sector = val;
1079 bus->ifs[1].sector = val;
1080 break;
1081 case 4:
1082 ide_clear_hob(bus);
1083 bus->ifs[0].hob_lcyl = bus->ifs[0].lcyl;
1084 bus->ifs[1].hob_lcyl = bus->ifs[1].lcyl;
1085 bus->ifs[0].lcyl = val;
1086 bus->ifs[1].lcyl = val;
1087 break;
1088 case 5:
1089 ide_clear_hob(bus);
1090 bus->ifs[0].hob_hcyl = bus->ifs[0].hcyl;
1091 bus->ifs[1].hob_hcyl = bus->ifs[1].hcyl;
1092 bus->ifs[0].hcyl = val;
1093 bus->ifs[1].hcyl = val;
1094 break;
1095 case 6:
1096 /* FIXME: HOB readback uses bit 7 */
1097 bus->ifs[0].select = (val & ~0x10) | 0xa0;
1098 bus->ifs[1].select = (val | 0x10) | 0xa0;
1099 /* select drive */
1100 bus->unit = (val >> 4) & 1;
1101 break;
1102 default:
1103 case 7:
1104 /* command */
1105 ide_exec_cmd(bus, val);
1106 break;
1107 }
1108 }
1109
1110 static bool cmd_nop(IDEState *s, uint8_t cmd)
1111 {
1112 return true;
1113 }
1114
1115 static bool cmd_data_set_management(IDEState *s, uint8_t cmd)
1116 {
1117 switch (s->feature) {
1118 case DSM_TRIM:
1119 if (s->blk) {
1120 ide_sector_start_dma(s, IDE_DMA_TRIM);
1121 return false;
1122 }
1123 break;
1124 }
1125
1126 ide_abort_command(s);
1127 return true;
1128 }
1129
1130 static bool cmd_identify(IDEState *s, uint8_t cmd)
1131 {
1132 if (s->blk && s->drive_kind != IDE_CD) {
1133 if (s->drive_kind != IDE_CFATA) {
1134 ide_identify(s);
1135 } else {
1136 ide_cfata_identify(s);
1137 }
1138 s->status = READY_STAT | SEEK_STAT;
1139 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1140 ide_set_irq(s->bus);
1141 return false;
1142 } else {
1143 if (s->drive_kind == IDE_CD) {
1144 ide_set_signature(s);
1145 }
1146 ide_abort_command(s);
1147 }
1148
1149 return true;
1150 }
1151
1152 static bool cmd_verify(IDEState *s, uint8_t cmd)
1153 {
1154 bool lba48 = (cmd == WIN_VERIFY_EXT);
1155
1156 /* do sector number check ? */
1157 ide_cmd_lba48_transform(s, lba48);
1158
1159 return true;
1160 }
1161
1162 static bool cmd_set_multiple_mode(IDEState *s, uint8_t cmd)
1163 {
1164 if (s->drive_kind == IDE_CFATA && s->nsector == 0) {
1165 /* Disable Read and Write Multiple */
1166 s->mult_sectors = 0;
1167 } else if ((s->nsector & 0xff) != 0 &&
1168 ((s->nsector & 0xff) > MAX_MULT_SECTORS ||
1169 (s->nsector & (s->nsector - 1)) != 0)) {
1170 ide_abort_command(s);
1171 } else {
1172 s->mult_sectors = s->nsector & 0xff;
1173 }
1174
1175 return true;
1176 }
1177
1178 static bool cmd_read_multiple(IDEState *s, uint8_t cmd)
1179 {
1180 bool lba48 = (cmd == WIN_MULTREAD_EXT);
1181
1182 if (!s->blk || !s->mult_sectors) {
1183 ide_abort_command(s);
1184 return true;
1185 }
1186
1187 ide_cmd_lba48_transform(s, lba48);
1188 s->req_nb_sectors = s->mult_sectors;
1189 ide_sector_read(s);
1190 return false;
1191 }
1192
1193 static bool cmd_write_multiple(IDEState *s, uint8_t cmd)
1194 {
1195 bool lba48 = (cmd == WIN_MULTWRITE_EXT);
1196 int n;
1197
1198 if (!s->blk || !s->mult_sectors) {
1199 ide_abort_command(s);
1200 return true;
1201 }
1202
1203 ide_cmd_lba48_transform(s, lba48);
1204
1205 s->req_nb_sectors = s->mult_sectors;
1206 n = MIN(s->nsector, s->req_nb_sectors);
1207
1208 s->status = SEEK_STAT | READY_STAT;
1209 ide_transfer_start(s, s->io_buffer, 512 * n, ide_sector_write);
1210
1211 s->media_changed = 1;
1212
1213 return false;
1214 }
1215
1216 static bool cmd_read_pio(IDEState *s, uint8_t cmd)
1217 {
1218 bool lba48 = (cmd == WIN_READ_EXT);
1219
1220 if (s->drive_kind == IDE_CD) {
1221 ide_set_signature(s); /* odd, but ATA4 8.27.5.2 requires it */
1222 ide_abort_command(s);
1223 return true;
1224 }
1225
1226 if (!s->blk) {
1227 ide_abort_command(s);
1228 return true;
1229 }
1230
1231 ide_cmd_lba48_transform(s, lba48);
1232 s->req_nb_sectors = 1;
1233 ide_sector_read(s);
1234
1235 return false;
1236 }
1237
1238 static bool cmd_write_pio(IDEState *s, uint8_t cmd)
1239 {
1240 bool lba48 = (cmd == WIN_WRITE_EXT);
1241
1242 if (!s->blk) {
1243 ide_abort_command(s);
1244 return true;
1245 }
1246
1247 ide_cmd_lba48_transform(s, lba48);
1248
1249 s->req_nb_sectors = 1;
1250 s->status = SEEK_STAT | READY_STAT;
1251 ide_transfer_start(s, s->io_buffer, 512, ide_sector_write);
1252
1253 s->media_changed = 1;
1254
1255 return false;
1256 }
1257
1258 static bool cmd_read_dma(IDEState *s, uint8_t cmd)
1259 {
1260 bool lba48 = (cmd == WIN_READDMA_EXT);
1261
1262 if (!s->blk) {
1263 ide_abort_command(s);
1264 return true;
1265 }
1266
1267 ide_cmd_lba48_transform(s, lba48);
1268 ide_sector_start_dma(s, IDE_DMA_READ);
1269
1270 return false;
1271 }
1272
1273 static bool cmd_write_dma(IDEState *s, uint8_t cmd)
1274 {
1275 bool lba48 = (cmd == WIN_WRITEDMA_EXT);
1276
1277 if (!s->blk) {
1278 ide_abort_command(s);
1279 return true;
1280 }
1281
1282 ide_cmd_lba48_transform(s, lba48);
1283 ide_sector_start_dma(s, IDE_DMA_WRITE);
1284
1285 s->media_changed = 1;
1286
1287 return false;
1288 }
1289
1290 static bool cmd_flush_cache(IDEState *s, uint8_t cmd)
1291 {
1292 ide_flush_cache(s);
1293 return false;
1294 }
1295
1296 static bool cmd_seek(IDEState *s, uint8_t cmd)
1297 {
1298 /* XXX: Check that seek is within bounds */
1299 return true;
1300 }
1301
1302 static bool cmd_read_native_max(IDEState *s, uint8_t cmd)
1303 {
1304 bool lba48 = (cmd == WIN_READ_NATIVE_MAX_EXT);
1305
1306 /* Refuse if no sectors are addressable (e.g. medium not inserted) */
1307 if (s->nb_sectors == 0) {
1308 ide_abort_command(s);
1309 return true;
1310 }
1311
1312 ide_cmd_lba48_transform(s, lba48);
1313 ide_set_sector(s, s->nb_sectors - 1);
1314
1315 return true;
1316 }
1317
1318 static bool cmd_check_power_mode(IDEState *s, uint8_t cmd)
1319 {
1320 s->nsector = 0xff; /* device active or idle */
1321 return true;
1322 }
1323
1324 static bool cmd_set_features(IDEState *s, uint8_t cmd)
1325 {
1326 uint16_t *identify_data;
1327
1328 if (!s->blk) {
1329 ide_abort_command(s);
1330 return true;
1331 }
1332
1333 /* XXX: valid for CDROM ? */
1334 switch (s->feature) {
1335 case 0x02: /* write cache enable */
1336 blk_set_enable_write_cache(s->blk, true);
1337 identify_data = (uint16_t *)s->identify_data;
1338 put_le16(identify_data + 85, (1 << 14) | (1 << 5) | 1);
1339 return true;
1340 case 0x82: /* write cache disable */
1341 blk_set_enable_write_cache(s->blk, false);
1342 identify_data = (uint16_t *)s->identify_data;
1343 put_le16(identify_data + 85, (1 << 14) | 1);
1344 ide_flush_cache(s);
1345 return false;
1346 case 0xcc: /* reverting to power-on defaults enable */
1347 case 0x66: /* reverting to power-on defaults disable */
1348 case 0xaa: /* read look-ahead enable */
1349 case 0x55: /* read look-ahead disable */
1350 case 0x05: /* set advanced power management mode */
1351 case 0x85: /* disable advanced power management mode */
1352 case 0x69: /* NOP */
1353 case 0x67: /* NOP */
1354 case 0x96: /* NOP */
1355 case 0x9a: /* NOP */
1356 case 0x42: /* enable Automatic Acoustic Mode */
1357 case 0xc2: /* disable Automatic Acoustic Mode */
1358 return true;
1359 case 0x03: /* set transfer mode */
1360 {
1361 uint8_t val = s->nsector & 0x07;
1362 identify_data = (uint16_t *)s->identify_data;
1363
1364 switch (s->nsector >> 3) {
1365 case 0x00: /* pio default */
1366 case 0x01: /* pio mode */
1367 put_le16(identify_data + 62, 0x07);
1368 put_le16(identify_data + 63, 0x07);
1369 put_le16(identify_data + 88, 0x3f);
1370 break;
1371 case 0x02: /* sigle word dma mode*/
1372 put_le16(identify_data + 62, 0x07 | (1 << (val + 8)));
1373 put_le16(identify_data + 63, 0x07);
1374 put_le16(identify_data + 88, 0x3f);
1375 break;
1376 case 0x04: /* mdma mode */
1377 put_le16(identify_data + 62, 0x07);
1378 put_le16(identify_data + 63, 0x07 | (1 << (val + 8)));
1379 put_le16(identify_data + 88, 0x3f);
1380 break;
1381 case 0x08: /* udma mode */
1382 put_le16(identify_data + 62, 0x07);
1383 put_le16(identify_data + 63, 0x07);
1384 put_le16(identify_data + 88, 0x3f | (1 << (val + 8)));
1385 break;
1386 default:
1387 goto abort_cmd;
1388 }
1389 return true;
1390 }
1391 }
1392
1393 abort_cmd:
1394 ide_abort_command(s);
1395 return true;
1396 }
1397
1398
1399 /*** ATAPI commands ***/
1400
1401 static bool cmd_identify_packet(IDEState *s, uint8_t cmd)
1402 {
1403 ide_atapi_identify(s);
1404 s->status = READY_STAT | SEEK_STAT;
1405 ide_transfer_start(s, s->io_buffer, 512, ide_transfer_stop);
1406 ide_set_irq(s->bus);
1407 return false;
1408 }
1409
1410 static bool cmd_exec_dev_diagnostic(IDEState *s, uint8_t cmd)
1411 {
1412 ide_set_signature(s);
1413
1414 if (s->drive_kind == IDE_CD) {
1415 s->status = 0; /* ATAPI spec (v6) section 9.10 defines packet
1416 * devices to return a clear status register
1417 * with READY_STAT *not* set. */
1418 s->error = 0x01;
1419 } else {
1420 s->status = READY_STAT | SEEK_STAT;
1421 /* The bits of the error register are not as usual for this command!
1422 * They are part of the regular output (this is why ERR_STAT isn't set)
1423 * Device 0 passed, Device 1 passed or not present. */
1424 s->error = 0x01;
1425 ide_set_irq(s->bus);
1426 }
1427
1428 return false;
1429 }
1430
1431 static bool cmd_device_reset(IDEState *s, uint8_t cmd)
1432 {
1433 ide_set_signature(s);
1434 s->status = 0x00; /* NOTE: READY is _not_ set */
1435 s->error = 0x01;
1436
1437 return false;
1438 }
1439
1440 static bool cmd_packet(IDEState *s, uint8_t cmd)
1441 {
1442 /* overlapping commands not supported */
1443 if (s->feature & 0x02) {
1444 ide_abort_command(s);
1445 return true;
1446 }
1447
1448 s->status = READY_STAT | SEEK_STAT;
1449 s->atapi_dma = s->feature & 1;
1450 s->nsector = 1;
1451 ide_transfer_start(s, s->io_buffer, ATAPI_PACKET_SIZE,
1452 ide_atapi_cmd);
1453 return false;
1454 }
1455
1456
1457 /*** CF-ATA commands ***/
1458
1459 static bool cmd_cfa_req_ext_error_code(IDEState *s, uint8_t cmd)
1460 {
1461 s->error = 0x09; /* miscellaneous error */
1462 s->status = READY_STAT | SEEK_STAT;
1463 ide_set_irq(s->bus);
1464
1465 return false;
1466 }
1467
1468 static bool cmd_cfa_erase_sectors(IDEState *s, uint8_t cmd)
1469 {
1470 /* WIN_SECURITY_FREEZE_LOCK has the same ID as CFA_WEAR_LEVEL and is
1471 * required for Windows 8 to work with AHCI */
1472
1473 if (cmd == CFA_WEAR_LEVEL) {
1474 s->nsector = 0;
1475 }
1476
1477 if (cmd == CFA_ERASE_SECTORS) {
1478 s->media_changed = 1;
1479 }
1480
1481 return true;
1482 }
1483
1484 static bool cmd_cfa_translate_sector(IDEState *s, uint8_t cmd)
1485 {
1486 s->status = READY_STAT | SEEK_STAT;
1487
1488 memset(s->io_buffer, 0, 0x200);
1489 s->io_buffer[0x00] = s->hcyl; /* Cyl MSB */
1490 s->io_buffer[0x01] = s->lcyl; /* Cyl LSB */
1491 s->io_buffer[0x02] = s->select; /* Head */
1492 s->io_buffer[0x03] = s->sector; /* Sector */
1493 s->io_buffer[0x04] = ide_get_sector(s) >> 16; /* LBA MSB */
1494 s->io_buffer[0x05] = ide_get_sector(s) >> 8; /* LBA */
1495 s->io_buffer[0x06] = ide_get_sector(s) >> 0; /* LBA LSB */
1496 s->io_buffer[0x13] = 0x00; /* Erase flag */
1497 s->io_buffer[0x18] = 0x00; /* Hot count */
1498 s->io_buffer[0x19] = 0x00; /* Hot count */
1499 s->io_buffer[0x1a] = 0x01; /* Hot count */
1500
1501 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1502 ide_set_irq(s->bus);
1503
1504 return false;
1505 }
1506
1507 static bool cmd_cfa_access_metadata_storage(IDEState *s, uint8_t cmd)
1508 {
1509 switch (s->feature) {
1510 case 0x02: /* Inquiry Metadata Storage */
1511 ide_cfata_metadata_inquiry(s);
1512 break;
1513 case 0x03: /* Read Metadata Storage */
1514 ide_cfata_metadata_read(s);
1515 break;
1516 case 0x04: /* Write Metadata Storage */
1517 ide_cfata_metadata_write(s);
1518 break;
1519 default:
1520 ide_abort_command(s);
1521 return true;
1522 }
1523
1524 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1525 s->status = 0x00; /* NOTE: READY is _not_ set */
1526 ide_set_irq(s->bus);
1527
1528 return false;
1529 }
1530
1531 static bool cmd_ibm_sense_condition(IDEState *s, uint8_t cmd)
1532 {
1533 switch (s->feature) {
1534 case 0x01: /* sense temperature in device */
1535 s->nsector = 0x50; /* +20 C */
1536 break;
1537 default:
1538 ide_abort_command(s);
1539 return true;
1540 }
1541
1542 return true;
1543 }
1544
1545
1546 /*** SMART commands ***/
1547
1548 static bool cmd_smart(IDEState *s, uint8_t cmd)
1549 {
1550 int n;
1551
1552 if (s->hcyl != 0xc2 || s->lcyl != 0x4f) {
1553 goto abort_cmd;
1554 }
1555
1556 if (!s->smart_enabled && s->feature != SMART_ENABLE) {
1557 goto abort_cmd;
1558 }
1559
1560 switch (s->feature) {
1561 case SMART_DISABLE:
1562 s->smart_enabled = 0;
1563 return true;
1564
1565 case SMART_ENABLE:
1566 s->smart_enabled = 1;
1567 return true;
1568
1569 case SMART_ATTR_AUTOSAVE:
1570 switch (s->sector) {
1571 case 0x00:
1572 s->smart_autosave = 0;
1573 break;
1574 case 0xf1:
1575 s->smart_autosave = 1;
1576 break;
1577 default:
1578 goto abort_cmd;
1579 }
1580 return true;
1581
1582 case SMART_STATUS:
1583 if (!s->smart_errors) {
1584 s->hcyl = 0xc2;
1585 s->lcyl = 0x4f;
1586 } else {
1587 s->hcyl = 0x2c;
1588 s->lcyl = 0xf4;
1589 }
1590 return true;
1591
1592 case SMART_READ_THRESH:
1593 memset(s->io_buffer, 0, 0x200);
1594 s->io_buffer[0] = 0x01; /* smart struct version */
1595
1596 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1597 s->io_buffer[2 + 0 + (n * 12)] = smart_attributes[n][0];
1598 s->io_buffer[2 + 1 + (n * 12)] = smart_attributes[n][11];
1599 }
1600
1601 /* checksum */
1602 for (n = 0; n < 511; n++) {
1603 s->io_buffer[511] += s->io_buffer[n];
1604 }
1605 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1606
1607 s->status = READY_STAT | SEEK_STAT;
1608 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1609 ide_set_irq(s->bus);
1610 return false;
1611
1612 case SMART_READ_DATA:
1613 memset(s->io_buffer, 0, 0x200);
1614 s->io_buffer[0] = 0x01; /* smart struct version */
1615
1616 for (n = 0; n < ARRAY_SIZE(smart_attributes); n++) {
1617 int i;
1618 for (i = 0; i < 11; i++) {
1619 s->io_buffer[2 + i + (n * 12)] = smart_attributes[n][i];
1620 }
1621 }
1622
1623 s->io_buffer[362] = 0x02 | (s->smart_autosave ? 0x80 : 0x00);
1624 if (s->smart_selftest_count == 0) {
1625 s->io_buffer[363] = 0;
1626 } else {
1627 s->io_buffer[363] =
1628 s->smart_selftest_data[3 +
1629 (s->smart_selftest_count - 1) *
1630 24];
1631 }
1632 s->io_buffer[364] = 0x20;
1633 s->io_buffer[365] = 0x01;
1634 /* offline data collection capacity: execute + self-test*/
1635 s->io_buffer[367] = (1 << 4 | 1 << 3 | 1);
1636 s->io_buffer[368] = 0x03; /* smart capability (1) */
1637 s->io_buffer[369] = 0x00; /* smart capability (2) */
1638 s->io_buffer[370] = 0x01; /* error logging supported */
1639 s->io_buffer[372] = 0x02; /* minutes for poll short test */
1640 s->io_buffer[373] = 0x36; /* minutes for poll ext test */
1641 s->io_buffer[374] = 0x01; /* minutes for poll conveyance */
1642
1643 for (n = 0; n < 511; n++) {
1644 s->io_buffer[511] += s->io_buffer[n];
1645 }
1646 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1647
1648 s->status = READY_STAT | SEEK_STAT;
1649 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1650 ide_set_irq(s->bus);
1651 return false;
1652
1653 case SMART_READ_LOG:
1654 switch (s->sector) {
1655 case 0x01: /* summary smart error log */
1656 memset(s->io_buffer, 0, 0x200);
1657 s->io_buffer[0] = 0x01;
1658 s->io_buffer[1] = 0x00; /* no error entries */
1659 s->io_buffer[452] = s->smart_errors & 0xff;
1660 s->io_buffer[453] = (s->smart_errors & 0xff00) >> 8;
1661
1662 for (n = 0; n < 511; n++) {
1663 s->io_buffer[511] += s->io_buffer[n];
1664 }
1665 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1666 break;
1667 case 0x06: /* smart self test log */
1668 memset(s->io_buffer, 0, 0x200);
1669 s->io_buffer[0] = 0x01;
1670 if (s->smart_selftest_count == 0) {
1671 s->io_buffer[508] = 0;
1672 } else {
1673 s->io_buffer[508] = s->smart_selftest_count;
1674 for (n = 2; n < 506; n++) {
1675 s->io_buffer[n] = s->smart_selftest_data[n];
1676 }
1677 }
1678
1679 for (n = 0; n < 511; n++) {
1680 s->io_buffer[511] += s->io_buffer[n];
1681 }
1682 s->io_buffer[511] = 0x100 - s->io_buffer[511];
1683 break;
1684 default:
1685 goto abort_cmd;
1686 }
1687 s->status = READY_STAT | SEEK_STAT;
1688 ide_transfer_start(s, s->io_buffer, 0x200, ide_transfer_stop);
1689 ide_set_irq(s->bus);
1690 return false;
1691
1692 case SMART_EXECUTE_OFFLINE:
1693 switch (s->sector) {
1694 case 0: /* off-line routine */
1695 case 1: /* short self test */
1696 case 2: /* extended self test */
1697 s->smart_selftest_count++;
1698 if (s->smart_selftest_count > 21) {
1699 s->smart_selftest_count = 1;
1700 }
1701 n = 2 + (s->smart_selftest_count - 1) * 24;
1702 s->smart_selftest_data[n] = s->sector;
1703 s->smart_selftest_data[n + 1] = 0x00; /* OK and finished */
1704 s->smart_selftest_data[n + 2] = 0x34; /* hour count lsb */
1705 s->smart_selftest_data[n + 3] = 0x12; /* hour count msb */
1706 break;
1707 default:
1708 goto abort_cmd;
1709 }
1710 return true;
1711 }
1712
1713 abort_cmd:
1714 ide_abort_command(s);
1715 return true;
1716 }
1717
1718 #define HD_OK (1u << IDE_HD)
1719 #define CD_OK (1u << IDE_CD)
1720 #define CFA_OK (1u << IDE_CFATA)
1721 #define HD_CFA_OK (HD_OK | CFA_OK)
1722 #define ALL_OK (HD_OK | CD_OK | CFA_OK)
1723
1724 /* Set the Disk Seek Completed status bit during completion */
1725 #define SET_DSC (1u << 8)
1726
1727 /* See ACS-2 T13/2015-D Table B.2 Command codes */
1728 static const struct {
1729 /* Returns true if the completion code should be run */
1730 bool (*handler)(IDEState *s, uint8_t cmd);
1731 int flags;
1732 } ide_cmd_table[0x100] = {
1733 /* NOP not implemented, mandatory for CD */
1734 [CFA_REQ_EXT_ERROR_CODE] = { cmd_cfa_req_ext_error_code, CFA_OK },
1735 [WIN_DSM] = { cmd_data_set_management, ALL_OK },
1736 [WIN_DEVICE_RESET] = { cmd_device_reset, CD_OK },
1737 [WIN_RECAL] = { cmd_nop, HD_CFA_OK | SET_DSC},
1738 [WIN_READ] = { cmd_read_pio, ALL_OK },
1739 [WIN_READ_ONCE] = { cmd_read_pio, ALL_OK },
1740 [WIN_READ_EXT] = { cmd_read_pio, HD_CFA_OK },
1741 [WIN_READDMA_EXT] = { cmd_read_dma, HD_CFA_OK },
1742 [WIN_READ_NATIVE_MAX_EXT] = { cmd_read_native_max, HD_CFA_OK | SET_DSC },
1743 [WIN_MULTREAD_EXT] = { cmd_read_multiple, HD_CFA_OK },
1744 [WIN_WRITE] = { cmd_write_pio, HD_CFA_OK },
1745 [WIN_WRITE_ONCE] = { cmd_write_pio, HD_CFA_OK },
1746 [WIN_WRITE_EXT] = { cmd_write_pio, HD_CFA_OK },
1747 [WIN_WRITEDMA_EXT] = { cmd_write_dma, HD_CFA_OK },
1748 [CFA_WRITE_SECT_WO_ERASE] = { cmd_write_pio, CFA_OK },
1749 [WIN_MULTWRITE_EXT] = { cmd_write_multiple, HD_CFA_OK },
1750 [WIN_WRITE_VERIFY] = { cmd_write_pio, HD_CFA_OK },
1751 [WIN_VERIFY] = { cmd_verify, HD_CFA_OK | SET_DSC },
1752 [WIN_VERIFY_ONCE] = { cmd_verify, HD_CFA_OK | SET_DSC },
1753 [WIN_VERIFY_EXT] = { cmd_verify, HD_CFA_OK | SET_DSC },
1754 [WIN_SEEK] = { cmd_seek, HD_CFA_OK | SET_DSC },
1755 [CFA_TRANSLATE_SECTOR] = { cmd_cfa_translate_sector, CFA_OK },
1756 [WIN_DIAGNOSE] = { cmd_exec_dev_diagnostic, ALL_OK },
1757 [WIN_SPECIFY] = { cmd_nop, HD_CFA_OK | SET_DSC },
1758 [WIN_STANDBYNOW2] = { cmd_nop, ALL_OK },
1759 [WIN_IDLEIMMEDIATE2] = { cmd_nop, ALL_OK },
1760 [WIN_STANDBY2] = { cmd_nop, ALL_OK },
1761 [WIN_SETIDLE2] = { cmd_nop, ALL_OK },
1762 [WIN_CHECKPOWERMODE2] = { cmd_check_power_mode, ALL_OK | SET_DSC },
1763 [WIN_SLEEPNOW2] = { cmd_nop, ALL_OK },
1764 [WIN_PACKETCMD] = { cmd_packet, CD_OK },
1765 [WIN_PIDENTIFY] = { cmd_identify_packet, CD_OK },
1766 [WIN_SMART] = { cmd_smart, HD_CFA_OK | SET_DSC },
1767 [CFA_ACCESS_METADATA_STORAGE] = { cmd_cfa_access_metadata_storage, CFA_OK },
1768 [CFA_ERASE_SECTORS] = { cmd_cfa_erase_sectors, CFA_OK | SET_DSC },
1769 [WIN_MULTREAD] = { cmd_read_multiple, HD_CFA_OK },
1770 [WIN_MULTWRITE] = { cmd_write_multiple, HD_CFA_OK },
1771 [WIN_SETMULT] = { cmd_set_multiple_mode, HD_CFA_OK | SET_DSC },
1772 [WIN_READDMA] = { cmd_read_dma, HD_CFA_OK },
1773 [WIN_READDMA_ONCE] = { cmd_read_dma, HD_CFA_OK },
1774 [WIN_WRITEDMA] = { cmd_write_dma, HD_CFA_OK },
1775 [WIN_WRITEDMA_ONCE] = { cmd_write_dma, HD_CFA_OK },
1776 [CFA_WRITE_MULTI_WO_ERASE] = { cmd_write_multiple, CFA_OK },
1777 [WIN_STANDBYNOW1] = { cmd_nop, ALL_OK },
1778 [WIN_IDLEIMMEDIATE] = { cmd_nop, ALL_OK },
1779 [WIN_STANDBY] = { cmd_nop, ALL_OK },
1780 [WIN_SETIDLE1] = { cmd_nop, ALL_OK },
1781 [WIN_CHECKPOWERMODE1] = { cmd_check_power_mode, ALL_OK | SET_DSC },
1782 [WIN_SLEEPNOW1] = { cmd_nop, ALL_OK },
1783 [WIN_FLUSH_CACHE] = { cmd_flush_cache, ALL_OK },
1784 [WIN_FLUSH_CACHE_EXT] = { cmd_flush_cache, HD_CFA_OK },
1785 [WIN_IDENTIFY] = { cmd_identify, ALL_OK },
1786 [WIN_SETFEATURES] = { cmd_set_features, ALL_OK | SET_DSC },
1787 [IBM_SENSE_CONDITION] = { cmd_ibm_sense_condition, CFA_OK | SET_DSC },
1788 [CFA_WEAR_LEVEL] = { cmd_cfa_erase_sectors, HD_CFA_OK | SET_DSC },
1789 [WIN_READ_NATIVE_MAX] = { cmd_read_native_max, ALL_OK | SET_DSC },
1790 };
1791
1792 static bool ide_cmd_permitted(IDEState *s, uint32_t cmd)
1793 {
1794 return cmd < ARRAY_SIZE(ide_cmd_table)
1795 && (ide_cmd_table[cmd].flags & (1u << s->drive_kind));
1796 }
1797
1798 void ide_exec_cmd(IDEBus *bus, uint32_t val)
1799 {
1800 IDEState *s;
1801 bool complete;
1802
1803 #if defined(DEBUG_IDE)
1804 printf("ide: CMD=%02x\n", val);
1805 #endif
1806 s = idebus_active_if(bus);
1807 /* ignore commands to non existent slave */
1808 if (s != bus->ifs && !s->blk) {
1809 return;
1810 }
1811
1812 /* Only DEVICE RESET is allowed while BSY or/and DRQ are set */
1813 if ((s->status & (BUSY_STAT|DRQ_STAT)) && val != WIN_DEVICE_RESET)
1814 return;
1815
1816 if (!ide_cmd_permitted(s, val)) {
1817 ide_abort_command(s);
1818 ide_set_irq(s->bus);
1819 return;
1820 }
1821
1822 s->status = READY_STAT | BUSY_STAT;
1823 s->error = 0;
1824
1825 complete = ide_cmd_table[val].handler(s, val);
1826 if (complete) {
1827 s->status &= ~BUSY_STAT;
1828 assert(!!s->error == !!(s->status & ERR_STAT));
1829
1830 if ((ide_cmd_table[val].flags & SET_DSC) && !s->error) {
1831 s->status |= SEEK_STAT;
1832 }
1833
1834 ide_cmd_done(s);
1835 ide_set_irq(s->bus);
1836 }
1837 }
1838
1839 uint32_t ide_ioport_read(void *opaque, uint32_t addr1)
1840 {
1841 IDEBus *bus = opaque;
1842 IDEState *s = idebus_active_if(bus);
1843 uint32_t addr;
1844 int ret, hob;
1845
1846 addr = addr1 & 7;
1847 /* FIXME: HOB readback uses bit 7, but it's always set right now */
1848 //hob = s->select & (1 << 7);
1849 hob = 0;
1850 switch(addr) {
1851 case 0:
1852 ret = 0xff;
1853 break;
1854 case 1:
1855 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
1856 (s != bus->ifs && !s->blk)) {
1857 ret = 0;
1858 } else if (!hob) {
1859 ret = s->error;
1860 } else {
1861 ret = s->hob_feature;
1862 }
1863 break;
1864 case 2:
1865 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
1866 ret = 0;
1867 } else if (!hob) {
1868 ret = s->nsector & 0xff;
1869 } else {
1870 ret = s->hob_nsector;
1871 }
1872 break;
1873 case 3:
1874 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
1875 ret = 0;
1876 } else if (!hob) {
1877 ret = s->sector;
1878 } else {
1879 ret = s->hob_sector;
1880 }
1881 break;
1882 case 4:
1883 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
1884 ret = 0;
1885 } else if (!hob) {
1886 ret = s->lcyl;
1887 } else {
1888 ret = s->hob_lcyl;
1889 }
1890 break;
1891 case 5:
1892 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
1893 ret = 0;
1894 } else if (!hob) {
1895 ret = s->hcyl;
1896 } else {
1897 ret = s->hob_hcyl;
1898 }
1899 break;
1900 case 6:
1901 if (!bus->ifs[0].blk && !bus->ifs[1].blk) {
1902 ret = 0;
1903 } else {
1904 ret = s->select;
1905 }
1906 break;
1907 default:
1908 case 7:
1909 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
1910 (s != bus->ifs && !s->blk)) {
1911 ret = 0;
1912 } else {
1913 ret = s->status;
1914 }
1915 qemu_irq_lower(bus->irq);
1916 break;
1917 }
1918 #ifdef DEBUG_IDE
1919 printf("ide: read addr=0x%x val=%02x\n", addr1, ret);
1920 #endif
1921 return ret;
1922 }
1923
1924 uint32_t ide_status_read(void *opaque, uint32_t addr)
1925 {
1926 IDEBus *bus = opaque;
1927 IDEState *s = idebus_active_if(bus);
1928 int ret;
1929
1930 if ((!bus->ifs[0].blk && !bus->ifs[1].blk) ||
1931 (s != bus->ifs && !s->blk)) {
1932 ret = 0;
1933 } else {
1934 ret = s->status;
1935 }
1936 #ifdef DEBUG_IDE
1937 printf("ide: read status addr=0x%x val=%02x\n", addr, ret);
1938 #endif
1939 return ret;
1940 }
1941
1942 void ide_cmd_write(void *opaque, uint32_t addr, uint32_t val)
1943 {
1944 IDEBus *bus = opaque;
1945 IDEState *s;
1946 int i;
1947
1948 #ifdef DEBUG_IDE
1949 printf("ide: write control addr=0x%x val=%02x\n", addr, val);
1950 #endif
1951 /* common for both drives */
1952 if (!(bus->cmd & IDE_CMD_RESET) &&
1953 (val & IDE_CMD_RESET)) {
1954 /* reset low to high */
1955 for(i = 0;i < 2; i++) {
1956 s = &bus->ifs[i];
1957 s->status = BUSY_STAT | SEEK_STAT;
1958 s->error = 0x01;
1959 }
1960 } else if ((bus->cmd & IDE_CMD_RESET) &&
1961 !(val & IDE_CMD_RESET)) {
1962 /* high to low */
1963 for(i = 0;i < 2; i++) {
1964 s = &bus->ifs[i];
1965 if (s->drive_kind == IDE_CD)
1966 s->status = 0x00; /* NOTE: READY is _not_ set */
1967 else
1968 s->status = READY_STAT | SEEK_STAT;
1969 ide_set_signature(s);
1970 }
1971 }
1972
1973 bus->cmd = val;
1974 }
1975
1976 /*
1977 * Returns true if the running PIO transfer is a PIO out (i.e. data is
1978 * transferred from the device to the guest), false if it's a PIO in
1979 */
1980 static bool ide_is_pio_out(IDEState *s)
1981 {
1982 if (s->end_transfer_func == ide_sector_write ||
1983 s->end_transfer_func == ide_atapi_cmd) {
1984 return false;
1985 } else if (s->end_transfer_func == ide_sector_read ||
1986 s->end_transfer_func == ide_transfer_stop ||
1987 s->end_transfer_func == ide_atapi_cmd_reply_end ||
1988 s->end_transfer_func == ide_dummy_transfer_stop) {
1989 return true;
1990 }
1991
1992 abort();
1993 }
1994
1995 void ide_data_writew(void *opaque, uint32_t addr, uint32_t val)
1996 {
1997 IDEBus *bus = opaque;
1998 IDEState *s = idebus_active_if(bus);
1999 uint8_t *p;
2000
2001 /* PIO data access allowed only when DRQ bit is set. The result of a write
2002 * during PIO out is indeterminate, just ignore it. */
2003 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
2004 return;
2005 }
2006
2007 p = s->data_ptr;
2008 *(uint16_t *)p = le16_to_cpu(val);
2009 p += 2;
2010 s->data_ptr = p;
2011 if (p >= s->data_end)
2012 s->end_transfer_func(s);
2013 }
2014
2015 uint32_t ide_data_readw(void *opaque, uint32_t addr)
2016 {
2017 IDEBus *bus = opaque;
2018 IDEState *s = idebus_active_if(bus);
2019 uint8_t *p;
2020 int ret;
2021
2022 /* PIO data access allowed only when DRQ bit is set. The result of a read
2023 * during PIO in is indeterminate, return 0 and don't move forward. */
2024 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
2025 return 0;
2026 }
2027
2028 p = s->data_ptr;
2029 ret = cpu_to_le16(*(uint16_t *)p);
2030 p += 2;
2031 s->data_ptr = p;
2032 if (p >= s->data_end)
2033 s->end_transfer_func(s);
2034 return ret;
2035 }
2036
2037 void ide_data_writel(void *opaque, uint32_t addr, uint32_t val)
2038 {
2039 IDEBus *bus = opaque;
2040 IDEState *s = idebus_active_if(bus);
2041 uint8_t *p;
2042
2043 /* PIO data access allowed only when DRQ bit is set. The result of a write
2044 * during PIO out is indeterminate, just ignore it. */
2045 if (!(s->status & DRQ_STAT) || ide_is_pio_out(s)) {
2046 return;
2047 }
2048
2049 p = s->data_ptr;
2050 *(uint32_t *)p = le32_to_cpu(val);
2051 p += 4;
2052 s->data_ptr = p;
2053 if (p >= s->data_end)
2054 s->end_transfer_func(s);
2055 }
2056
2057 uint32_t ide_data_readl(void *opaque, uint32_t addr)
2058 {
2059 IDEBus *bus = opaque;
2060 IDEState *s = idebus_active_if(bus);
2061 uint8_t *p;
2062 int ret;
2063
2064 /* PIO data access allowed only when DRQ bit is set. The result of a read
2065 * during PIO in is indeterminate, return 0 and don't move forward. */
2066 if (!(s->status & DRQ_STAT) || !ide_is_pio_out(s)) {
2067 return 0;
2068 }
2069
2070 p = s->data_ptr;
2071 ret = cpu_to_le32(*(uint32_t *)p);
2072 p += 4;
2073 s->data_ptr = p;
2074 if (p >= s->data_end)
2075 s->end_transfer_func(s);
2076 return ret;
2077 }
2078
2079 static void ide_dummy_transfer_stop(IDEState *s)
2080 {
2081 s->data_ptr = s->io_buffer;
2082 s->data_end = s->io_buffer;
2083 s->io_buffer[0] = 0xff;
2084 s->io_buffer[1] = 0xff;
2085 s->io_buffer[2] = 0xff;
2086 s->io_buffer[3] = 0xff;
2087 }
2088
2089 static void ide_reset(IDEState *s)
2090 {
2091 #ifdef DEBUG_IDE
2092 printf("ide: reset\n");
2093 #endif
2094
2095 if (s->pio_aiocb) {
2096 blk_aio_cancel(s->pio_aiocb);
2097 s->pio_aiocb = NULL;
2098 }
2099
2100 if (s->drive_kind == IDE_CFATA)
2101 s->mult_sectors = 0;
2102 else
2103 s->mult_sectors = MAX_MULT_SECTORS;
2104 /* ide regs */
2105 s->feature = 0;
2106 s->error = 0;
2107 s->nsector = 0;
2108 s->sector = 0;
2109 s->lcyl = 0;
2110 s->hcyl = 0;
2111
2112 /* lba48 */
2113 s->hob_feature = 0;
2114 s->hob_sector = 0;
2115 s->hob_nsector = 0;
2116 s->hob_lcyl = 0;
2117 s->hob_hcyl = 0;
2118
2119 s->select = 0xa0;
2120 s->status = READY_STAT | SEEK_STAT;
2121
2122 s->lba48 = 0;
2123
2124 /* ATAPI specific */
2125 s->sense_key = 0;
2126 s->asc = 0;
2127 s->cdrom_changed = 0;
2128 s->packet_transfer_size = 0;
2129 s->elementary_transfer_size = 0;
2130 s->io_buffer_index = 0;
2131 s->cd_sector_size = 0;
2132 s->atapi_dma = 0;
2133 s->tray_locked = 0;
2134 s->tray_open = 0;
2135 /* ATA DMA state */
2136 s->io_buffer_size = 0;
2137 s->req_nb_sectors = 0;
2138
2139 ide_set_signature(s);
2140 /* init the transfer handler so that 0xffff is returned on data
2141 accesses */
2142 s->end_transfer_func = ide_dummy_transfer_stop;
2143 ide_dummy_transfer_stop(s);
2144 s->media_changed = 0;
2145 }
2146
2147 void ide_bus_reset(IDEBus *bus)
2148 {
2149 bus->unit = 0;
2150 bus->cmd = 0;
2151 ide_reset(&bus->ifs[0]);
2152 ide_reset(&bus->ifs[1]);
2153 ide_clear_hob(bus);
2154
2155 /* pending async DMA */
2156 if (bus->dma->aiocb) {
2157 #ifdef DEBUG_AIO
2158 printf("aio_cancel\n");
2159 #endif
2160 blk_aio_cancel(bus->dma->aiocb);
2161 bus->dma->aiocb = NULL;
2162 }
2163
2164 /* reset dma provider too */
2165 if (bus->dma->ops->reset) {
2166 bus->dma->ops->reset(bus->dma);
2167 }
2168 }
2169
2170 static bool ide_cd_is_tray_open(void *opaque)
2171 {
2172 return ((IDEState *)opaque)->tray_open;
2173 }
2174
2175 static bool ide_cd_is_medium_locked(void *opaque)
2176 {
2177 return ((IDEState *)opaque)->tray_locked;
2178 }
2179
2180 static void ide_resize_cb(void *opaque)
2181 {
2182 IDEState *s = opaque;
2183 uint64_t nb_sectors;
2184
2185 if (!s->identify_set) {
2186 return;
2187 }
2188
2189 blk_get_geometry(s->blk, &nb_sectors);
2190 s->nb_sectors = nb_sectors;
2191
2192 /* Update the identify data buffer. */
2193 if (s->drive_kind == IDE_CFATA) {
2194 ide_cfata_identify_size(s);
2195 } else {
2196 /* IDE_CD uses a different set of callbacks entirely. */
2197 assert(s->drive_kind != IDE_CD);
2198 ide_identify_size(s);
2199 }
2200 }
2201
2202 static const BlockDevOps ide_cd_block_ops = {
2203 .change_media_cb = ide_cd_change_cb,
2204 .eject_request_cb = ide_cd_eject_request_cb,
2205 .is_tray_open = ide_cd_is_tray_open,
2206 .is_medium_locked = ide_cd_is_medium_locked,
2207 };
2208
2209 static const BlockDevOps ide_hd_block_ops = {
2210 .resize_cb = ide_resize_cb,
2211 };
2212
2213 int ide_init_drive(IDEState *s, BlockBackend *blk, IDEDriveKind kind,
2214 const char *version, const char *serial, const char *model,
2215 uint64_t wwn,
2216 uint32_t cylinders, uint32_t heads, uint32_t secs,
2217 int chs_trans)
2218 {
2219 uint64_t nb_sectors;
2220
2221 s->blk = blk;
2222 s->drive_kind = kind;
2223
2224 blk_get_geometry(blk, &nb_sectors);
2225 s->cylinders = cylinders;
2226 s->heads = heads;
2227 s->sectors = secs;
2228 s->chs_trans = chs_trans;
2229 s->nb_sectors = nb_sectors;
2230 s->wwn = wwn;
2231 /* The SMART values should be preserved across power cycles
2232 but they aren't. */
2233 s->smart_enabled = 1;
2234 s->smart_autosave = 1;
2235 s->smart_errors = 0;
2236 s->smart_selftest_count = 0;
2237 if (kind == IDE_CD) {
2238 blk_set_dev_ops(blk, &ide_cd_block_ops, s);
2239 blk_set_guest_block_size(blk, 2048);
2240 } else {
2241 if (!blk_is_inserted(s->blk)) {
2242 error_report("Device needs media, but drive is empty");
2243 return -1;
2244 }
2245 if (blk_is_read_only(blk)) {
2246 error_report("Can't use a read-only drive");
2247 return -1;
2248 }
2249 blk_set_dev_ops(blk, &ide_hd_block_ops, s);
2250 }
2251 if (serial) {
2252 pstrcpy(s->drive_serial_str, sizeof(s->drive_serial_str), serial);
2253 } else {
2254 snprintf(s->drive_serial_str, sizeof(s->drive_serial_str),
2255 "QM%05d", s->drive_serial);
2256 }
2257 if (model) {
2258 pstrcpy(s->drive_model_str, sizeof(s->drive_model_str), model);
2259 } else {
2260 switch (kind) {
2261 case IDE_CD:
2262 strcpy(s->drive_model_str, "QEMU DVD-ROM");
2263 break;
2264 case IDE_CFATA:
2265 strcpy(s->drive_model_str, "QEMU MICRODRIVE");
2266 break;
2267 default:
2268 strcpy(s->drive_model_str, "QEMU HARDDISK");
2269 break;
2270 }
2271 }
2272
2273 if (version) {
2274 pstrcpy(s->version, sizeof(s->version), version);
2275 } else {
2276 pstrcpy(s->version, sizeof(s->version), qemu_get_version());
2277 }
2278
2279 ide_reset(s);
2280 blk_iostatus_enable(blk);
2281 return 0;
2282 }
2283
2284 static void ide_init1(IDEBus *bus, int unit)
2285 {
2286 static int drive_serial = 1;
2287 IDEState *s = &bus->ifs[unit];
2288
2289 s->bus = bus;
2290 s->unit = unit;
2291 s->drive_serial = drive_serial++;
2292 /* we need at least 2k alignment for accessing CDROMs using O_DIRECT */
2293 s->io_buffer_total_len = IDE_DMA_BUF_SECTORS*512 + 4;
2294 s->io_buffer = qemu_memalign(2048, s->io_buffer_total_len);
2295 memset(s->io_buffer, 0, s->io_buffer_total_len);
2296
2297 s->smart_selftest_data = blk_blockalign(s->blk, 512);
2298 memset(s->smart_selftest_data, 0, 512);
2299
2300 s->sector_write_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL,
2301 ide_sector_write_timer_cb, s);
2302 }
2303
2304 static int ide_nop_int(IDEDMA *dma, int x)
2305 {
2306 return 0;
2307 }
2308
2309 static void ide_nop_restart(void *opaque, int x, RunState y)
2310 {
2311 }
2312
2313 static const IDEDMAOps ide_dma_nop_ops = {
2314 .prepare_buf = ide_nop_int,
2315 .rw_buf = ide_nop_int,
2316 .set_unit = ide_nop_int,
2317 .restart_cb = ide_nop_restart,
2318 };
2319
2320 static IDEDMA ide_dma_nop = {
2321 .ops = &ide_dma_nop_ops,
2322 .aiocb = NULL,
2323 };
2324
2325 void ide_init2(IDEBus *bus, qemu_irq irq)
2326 {
2327 int i;
2328
2329 for(i = 0; i < 2; i++) {
2330 ide_init1(bus, i);
2331 ide_reset(&bus->ifs[i]);
2332 }
2333 bus->irq = irq;
2334 bus->dma = &ide_dma_nop;
2335 }
2336
2337 static const MemoryRegionPortio ide_portio_list[] = {
2338 { 0, 8, 1, .read = ide_ioport_read, .write = ide_ioport_write },
2339 { 0, 2, 2, .read = ide_data_readw, .write = ide_data_writew },
2340 { 0, 4, 4, .read = ide_data_readl, .write = ide_data_writel },
2341 PORTIO_END_OF_LIST(),
2342 };
2343
2344 static const MemoryRegionPortio ide_portio2_list[] = {
2345 { 0, 1, 1, .read = ide_status_read, .write = ide_cmd_write },
2346 PORTIO_END_OF_LIST(),
2347 };
2348
2349 void ide_init_ioport(IDEBus *bus, ISADevice *dev, int iobase, int iobase2)
2350 {
2351 /* ??? Assume only ISA and PCI configurations, and that the PCI-ISA
2352 bridge has been setup properly to always register with ISA. */
2353 isa_register_portio_list(dev, iobase, ide_portio_list, bus, "ide");
2354
2355 if (iobase2) {
2356 isa_register_portio_list(dev, iobase2, ide_portio2_list, bus, "ide");
2357 }
2358 }
2359
2360 static bool is_identify_set(void *opaque, int version_id)
2361 {
2362 IDEState *s = opaque;
2363
2364 return s->identify_set != 0;
2365 }
2366
2367 static EndTransferFunc* transfer_end_table[] = {
2368 ide_sector_read,
2369 ide_sector_write,
2370 ide_transfer_stop,
2371 ide_atapi_cmd_reply_end,
2372 ide_atapi_cmd,
2373 ide_dummy_transfer_stop,
2374 };
2375
2376 static int transfer_end_table_idx(EndTransferFunc *fn)
2377 {
2378 int i;
2379
2380 for (i = 0; i < ARRAY_SIZE(transfer_end_table); i++)
2381 if (transfer_end_table[i] == fn)
2382 return i;
2383
2384 return -1;
2385 }
2386
2387 static int ide_drive_post_load(void *opaque, int version_id)
2388 {
2389 IDEState *s = opaque;
2390
2391 if (s->identify_set) {
2392 blk_set_enable_write_cache(s->blk, !!(s->identify_data[85] & (1 << 5)));
2393 }
2394 return 0;
2395 }
2396
2397 static int ide_drive_pio_post_load(void *opaque, int version_id)
2398 {
2399 IDEState *s = opaque;
2400
2401 if (s->end_transfer_fn_idx >= ARRAY_SIZE(transfer_end_table)) {
2402 return -EINVAL;
2403 }
2404 s->end_transfer_func = transfer_end_table[s->end_transfer_fn_idx];
2405 s->data_ptr = s->io_buffer + s->cur_io_buffer_offset;
2406 s->data_end = s->data_ptr + s->cur_io_buffer_len;
2407
2408 return 0;
2409 }
2410
2411 static void ide_drive_pio_pre_save(void *opaque)
2412 {
2413 IDEState *s = opaque;
2414 int idx;
2415
2416 s->cur_io_buffer_offset = s->data_ptr - s->io_buffer;
2417 s->cur_io_buffer_len = s->data_end - s->data_ptr;
2418
2419 idx = transfer_end_table_idx(s->end_transfer_func);
2420 if (idx == -1) {
2421 fprintf(stderr, "%s: invalid end_transfer_func for DRQ_STAT\n",
2422 __func__);
2423 s->end_transfer_fn_idx = 2;
2424 } else {
2425 s->end_transfer_fn_idx = idx;
2426 }
2427 }
2428
2429 static bool ide_drive_pio_state_needed(void *opaque)
2430 {
2431 IDEState *s = opaque;
2432
2433 return ((s->status & DRQ_STAT) != 0)
2434 || (s->bus->error_status & IDE_RETRY_PIO);
2435 }
2436
2437 static bool ide_tray_state_needed(void *opaque)
2438 {
2439 IDEState *s = opaque;
2440
2441 return s->tray_open || s->tray_locked;
2442 }
2443
2444 static bool ide_atapi_gesn_needed(void *opaque)
2445 {
2446 IDEState *s = opaque;
2447
2448 return s->events.new_media || s->events.eject_request;
2449 }
2450
2451 static bool ide_error_needed(void *opaque)
2452 {
2453 IDEBus *bus = opaque;
2454
2455 return (bus->error_status != 0);
2456 }
2457
2458 /* Fields for GET_EVENT_STATUS_NOTIFICATION ATAPI command */
2459 static const VMStateDescription vmstate_ide_atapi_gesn_state = {
2460 .name ="ide_drive/atapi/gesn_state",
2461 .version_id = 1,
2462 .minimum_version_id = 1,
2463 .fields = (VMStateField[]) {
2464 VMSTATE_BOOL(events.new_media, IDEState),
2465 VMSTATE_BOOL(events.eject_request, IDEState),
2466 VMSTATE_END_OF_LIST()
2467 }
2468 };
2469
2470 static const VMStateDescription vmstate_ide_tray_state = {
2471 .name = "ide_drive/tray_state",
2472 .version_id = 1,
2473 .minimum_version_id = 1,
2474 .fields = (VMStateField[]) {
2475 VMSTATE_BOOL(tray_open, IDEState),
2476 VMSTATE_BOOL(tray_locked, IDEState),
2477 VMSTATE_END_OF_LIST()
2478 }
2479 };
2480
2481 static const VMStateDescription vmstate_ide_drive_pio_state = {
2482 .name = "ide_drive/pio_state",
2483 .version_id = 1,
2484 .minimum_version_id = 1,
2485 .pre_save = ide_drive_pio_pre_save,
2486 .post_load = ide_drive_pio_post_load,
2487 .fields = (VMStateField[]) {
2488 VMSTATE_INT32(req_nb_sectors, IDEState),
2489 VMSTATE_VARRAY_INT32(io_buffer, IDEState, io_buffer_total_len, 1,
2490 vmstate_info_uint8, uint8_t),
2491 VMSTATE_INT32(cur_io_buffer_offset, IDEState),
2492 VMSTATE_INT32(cur_io_buffer_len, IDEState),
2493 VMSTATE_UINT8(end_transfer_fn_idx, IDEState),
2494 VMSTATE_INT32(elementary_transfer_size, IDEState),
2495 VMSTATE_INT32(packet_transfer_size, IDEState),
2496 VMSTATE_END_OF_LIST()
2497 }
2498 };
2499
2500 const VMStateDescription vmstate_ide_drive = {
2501 .name = "ide_drive",
2502 .version_id = 3,
2503 .minimum_version_id = 0,
2504 .post_load = ide_drive_post_load,
2505 .fields = (VMStateField[]) {
2506 VMSTATE_INT32(mult_sectors, IDEState),
2507 VMSTATE_INT32(identify_set, IDEState),
2508 VMSTATE_BUFFER_TEST(identify_data, IDEState, is_identify_set),
2509 VMSTATE_UINT8(feature, IDEState),
2510 VMSTATE_UINT8(error, IDEState),
2511 VMSTATE_UINT32(nsector, IDEState),
2512 VMSTATE_UINT8(sector, IDEState),
2513 VMSTATE_UINT8(lcyl, IDEState),
2514 VMSTATE_UINT8(hcyl, IDEState),
2515 VMSTATE_UINT8(hob_feature, IDEState),
2516 VMSTATE_UINT8(hob_sector, IDEState),
2517 VMSTATE_UINT8(hob_nsector, IDEState),
2518 VMSTATE_UINT8(hob_lcyl, IDEState),
2519 VMSTATE_UINT8(hob_hcyl, IDEState),
2520 VMSTATE_UINT8(select, IDEState),
2521 VMSTATE_UINT8(status, IDEState),
2522 VMSTATE_UINT8(lba48, IDEState),
2523 VMSTATE_UINT8(sense_key, IDEState),
2524 VMSTATE_UINT8(asc, IDEState),
2525 VMSTATE_UINT8_V(cdrom_changed, IDEState, 3),
2526 VMSTATE_END_OF_LIST()
2527 },
2528 .subsections = (VMStateSubsection []) {
2529 {
2530 .vmsd = &vmstate_ide_drive_pio_state,
2531 .needed = ide_drive_pio_state_needed,
2532 }, {
2533 .vmsd = &vmstate_ide_tray_state,
2534 .needed = ide_tray_state_needed,
2535 }, {
2536 .vmsd = &vmstate_ide_atapi_gesn_state,
2537 .needed = ide_atapi_gesn_needed,
2538 }, {
2539 /* empty */
2540 }
2541 }
2542 };
2543
2544 static const VMStateDescription vmstate_ide_error_status = {
2545 .name ="ide_bus/error",
2546 .version_id = 1,
2547 .minimum_version_id = 1,
2548 .fields = (VMStateField[]) {
2549 VMSTATE_INT32(error_status, IDEBus),
2550 VMSTATE_END_OF_LIST()
2551 }
2552 };
2553
2554 const VMStateDescription vmstate_ide_bus = {
2555 .name = "ide_bus",
2556 .version_id = 1,
2557 .minimum_version_id = 1,
2558 .fields = (VMStateField[]) {
2559 VMSTATE_UINT8(cmd, IDEBus),
2560 VMSTATE_UINT8(unit, IDEBus),
2561 VMSTATE_END_OF_LIST()
2562 },
2563 .subsections = (VMStateSubsection []) {
2564 {
2565 .vmsd = &vmstate_ide_error_status,
2566 .needed = ide_error_needed,
2567 }, {
2568 /* empty */
2569 }
2570 }
2571 };
2572
2573 void ide_drive_get(DriveInfo **hd, int n)
2574 {
2575 int i;
2576 int highest_bus = drive_get_max_bus(IF_IDE) + 1;
2577 int max_devs = drive_get_max_devs(IF_IDE);
2578 int n_buses = max_devs ? (n / max_devs) : n;
2579
2580 /*
2581 * Note: The number of actual buses available is not known.
2582 * We compute this based on the size of the DriveInfo* array, n.
2583 * If it is less than max_devs * <num_real_buses>,
2584 * We will stop looking for drives prematurely instead of overfilling
2585 * the array.
2586 */
2587
2588 if (highest_bus > n_buses) {
2589 error_report("Too many IDE buses defined (%d > %d)",
2590 highest_bus, n_buses);
2591 exit(1);
2592 }
2593
2594 for (i = 0; i < n; i++) {
2595 hd[i] = drive_get_by_index(IF_IDE, i);
2596 }
2597 }
QEMU modified to work with kvm