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PPC: e500: Fix MMUCSR0 emulation
[qemu-kvm.git] / target-ppc / translate_init.c
blob9b342c0438863af89c0addf7300c26c8a72bd029
1 /*
2 * PowerPC CPU initialization for qemu.
3 *
4 * Copyright (c) 2003-2007 Jocelyn Mayer
5 * Copyright 2011 Freescale Semiconductor, Inc.
6 *
7 * This library is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU Lesser General Public
9 * License as published by the Free Software Foundation; either
10 * version 2 of the License, or (at your option) any later version.
11 *
12 * This library is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * Lesser General Public License for more details.
16 *
17 * You should have received a copy of the GNU Lesser General Public
18 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 */
20
21 #include "disas/bfd.h"
22 #include "exec/gdbstub.h"
23 #include <sysemu/kvm.h>
24 #include "kvm_ppc.h"
25 #include "sysemu/arch_init.h"
26 #include "sysemu/cpus.h"
27 #include "cpu-models.h"
28 #include "mmu-hash32.h"
29 #include "mmu-hash64.h"
30 #include "qemu/error-report.h"
31 #include "qapi/visitor.h"
32 #include "hw/qdev-properties.h"
33
34 //#define PPC_DUMP_CPU
35 //#define PPC_DEBUG_SPR
36 //#define PPC_DUMP_SPR_ACCESSES
37
38 /* For user-mode emulation, we don't emulate any IRQ controller */
39 #if defined(CONFIG_USER_ONLY)
40 #define PPC_IRQ_INIT_FN(name) \
41 static inline void glue(glue(ppc, name),_irq_init) (CPUPPCState *env) \
42 { \
43 }
44 #else
45 #define PPC_IRQ_INIT_FN(name) \
46 void glue(glue(ppc, name),_irq_init) (CPUPPCState *env);
47 #endif
48
49 PPC_IRQ_INIT_FN(40x);
50 PPC_IRQ_INIT_FN(6xx);
51 PPC_IRQ_INIT_FN(970);
52 PPC_IRQ_INIT_FN(POWER7);
53 PPC_IRQ_INIT_FN(e500);
54
55 /* Generic callbacks:
56 * do nothing but store/retrieve spr value
57 */
58 static void spr_load_dump_spr(int sprn)
59 {
60 #ifdef PPC_DUMP_SPR_ACCESSES
61 TCGv_i32 t0 = tcg_const_i32(sprn);
62 gen_helper_load_dump_spr(cpu_env, t0);
63 tcg_temp_free_i32(t0);
64 #endif
65 }
66
67 static void spr_read_generic (void *opaque, int gprn, int sprn)
68 {
69 gen_load_spr(cpu_gpr[gprn], sprn);
70 spr_load_dump_spr(sprn);
71 }
72
73 static void spr_store_dump_spr(int sprn)
74 {
75 #ifdef PPC_DUMP_SPR_ACCESSES
76 TCGv_i32 t0 = tcg_const_i32(sprn);
77 gen_helper_store_dump_spr(cpu_env, t0);
78 tcg_temp_free_i32(t0);
79 #endif
80 }
81
82 static void spr_write_generic (void *opaque, int sprn, int gprn)
83 {
84 gen_store_spr(sprn, cpu_gpr[gprn]);
85 spr_store_dump_spr(sprn);
86 }
87
88 #if !defined(CONFIG_USER_ONLY)
89 static void spr_write_generic32(void *opaque, int sprn, int gprn)
90 {
91 #ifdef TARGET_PPC64
92 TCGv t0 = tcg_temp_new();
93 tcg_gen_ext32u_tl(t0, cpu_gpr[gprn]);
94 gen_store_spr(sprn, t0);
95 tcg_temp_free(t0);
96 spr_store_dump_spr(sprn);
97 #else
98 spr_write_generic(opaque, sprn, gprn);
99 #endif
100 }
101
102 static void spr_write_clear (void *opaque, int sprn, int gprn)
103 {
104 TCGv t0 = tcg_temp_new();
105 TCGv t1 = tcg_temp_new();
106 gen_load_spr(t0, sprn);
107 tcg_gen_neg_tl(t1, cpu_gpr[gprn]);
108 tcg_gen_and_tl(t0, t0, t1);
109 gen_store_spr(sprn, t0);
110 tcg_temp_free(t0);
111 tcg_temp_free(t1);
112 }
113
114 static void spr_access_nop(void *opaque, int sprn, int gprn)
115 {
116 }
117
118 #endif
119
120 /* SPR common to all PowerPC */
121 /* XER */
122 static void spr_read_xer (void *opaque, int gprn, int sprn)
123 {
124 gen_read_xer(cpu_gpr[gprn]);
125 }
126
127 static void spr_write_xer (void *opaque, int sprn, int gprn)
128 {
129 gen_write_xer(cpu_gpr[gprn]);
130 }
131
132 /* LR */
133 static void spr_read_lr (void *opaque, int gprn, int sprn)
134 {
135 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_lr);
136 }
137
138 static void spr_write_lr (void *opaque, int sprn, int gprn)
139 {
140 tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]);
141 }
142
143 /* CFAR */
144 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
145 static void spr_read_cfar (void *opaque, int gprn, int sprn)
146 {
147 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar);
148 }
149
150 static void spr_write_cfar (void *opaque, int sprn, int gprn)
151 {
152 tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]);
153 }
154 #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */
155
156 /* CTR */
157 static void spr_read_ctr (void *opaque, int gprn, int sprn)
158 {
159 tcg_gen_mov_tl(cpu_gpr[gprn], cpu_ctr);
160 }
161
162 static void spr_write_ctr (void *opaque, int sprn, int gprn)
163 {
164 tcg_gen_mov_tl(cpu_ctr, cpu_gpr[gprn]);
165 }
166
167 /* User read access to SPR */
168 /* USPRx */
169 /* UMMCRx */
170 /* UPMCx */
171 /* USIA */
172 /* UDECR */
173 static void spr_read_ureg (void *opaque, int gprn, int sprn)
174 {
175 gen_load_spr(cpu_gpr[gprn], sprn + 0x10);
176 }
177
178 /* SPR common to all non-embedded PowerPC */
179 /* DECR */
180 #if !defined(CONFIG_USER_ONLY)
181 static void spr_read_decr (void *opaque, int gprn, int sprn)
182 {
183 if (use_icount) {
184 gen_io_start();
185 }
186 gen_helper_load_decr(cpu_gpr[gprn], cpu_env);
187 if (use_icount) {
188 gen_io_end();
189 gen_stop_exception(opaque);
190 }
191 }
192
193 static void spr_write_decr (void *opaque, int sprn, int gprn)
194 {
195 if (use_icount) {
196 gen_io_start();
197 }
198 gen_helper_store_decr(cpu_env, cpu_gpr[gprn]);
199 if (use_icount) {
200 gen_io_end();
201 gen_stop_exception(opaque);
202 }
203 }
204 #endif
205
206 /* SPR common to all non-embedded PowerPC, except 601 */
207 /* Time base */
208 static void spr_read_tbl (void *opaque, int gprn, int sprn)
209 {
210 if (use_icount) {
211 gen_io_start();
212 }
213 gen_helper_load_tbl(cpu_gpr[gprn], cpu_env);
214 if (use_icount) {
215 gen_io_end();
216 gen_stop_exception(opaque);
217 }
218 }
219
220 static void spr_read_tbu (void *opaque, int gprn, int sprn)
221 {
222 if (use_icount) {
223 gen_io_start();
224 }
225 gen_helper_load_tbu(cpu_gpr[gprn], cpu_env);
226 if (use_icount) {
227 gen_io_end();
228 gen_stop_exception(opaque);
229 }
230 }
231
232 __attribute__ (( unused ))
233 static void spr_read_atbl (void *opaque, int gprn, int sprn)
234 {
235 gen_helper_load_atbl(cpu_gpr[gprn], cpu_env);
236 }
237
238 __attribute__ (( unused ))
239 static void spr_read_atbu (void *opaque, int gprn, int sprn)
240 {
241 gen_helper_load_atbu(cpu_gpr[gprn], cpu_env);
242 }
243
244 #if !defined(CONFIG_USER_ONLY)
245 static void spr_write_tbl (void *opaque, int sprn, int gprn)
246 {
247 if (use_icount) {
248 gen_io_start();
249 }
250 gen_helper_store_tbl(cpu_env, cpu_gpr[gprn]);
251 if (use_icount) {
252 gen_io_end();
253 gen_stop_exception(opaque);
254 }
255 }
256
257 static void spr_write_tbu (void *opaque, int sprn, int gprn)
258 {
259 if (use_icount) {
260 gen_io_start();
261 }
262 gen_helper_store_tbu(cpu_env, cpu_gpr[gprn]);
263 if (use_icount) {
264 gen_io_end();
265 gen_stop_exception(opaque);
266 }
267 }
268
269 __attribute__ (( unused ))
270 static void spr_write_atbl (void *opaque, int sprn, int gprn)
271 {
272 gen_helper_store_atbl(cpu_env, cpu_gpr[gprn]);
273 }
274
275 __attribute__ (( unused ))
276 static void spr_write_atbu (void *opaque, int sprn, int gprn)
277 {
278 gen_helper_store_atbu(cpu_env, cpu_gpr[gprn]);
279 }
280
281 #if defined(TARGET_PPC64)
282 __attribute__ (( unused ))
283 static void spr_read_purr (void *opaque, int gprn, int sprn)
284 {
285 gen_helper_load_purr(cpu_gpr[gprn], cpu_env);
286 }
287 #endif
288 #endif
289
290 #if !defined(CONFIG_USER_ONLY)
291 /* IBAT0U...IBAT0U */
292 /* IBAT0L...IBAT7L */
293 static void spr_read_ibat (void *opaque, int gprn, int sprn)
294 {
295 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
296 }
297
298 static void spr_read_ibat_h (void *opaque, int gprn, int sprn)
299 {
300 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT4U) / 2]));
301 }
302
303 static void spr_write_ibatu (void *opaque, int sprn, int gprn)
304 {
305 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
306 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
307 tcg_temp_free_i32(t0);
308 }
309
310 static void spr_write_ibatu_h (void *opaque, int sprn, int gprn)
311 {
312 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4U) / 2) + 4);
313 gen_helper_store_ibatu(cpu_env, t0, cpu_gpr[gprn]);
314 tcg_temp_free_i32(t0);
315 }
316
317 static void spr_write_ibatl (void *opaque, int sprn, int gprn)
318 {
319 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0L) / 2);
320 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
321 tcg_temp_free_i32(t0);
322 }
323
324 static void spr_write_ibatl_h (void *opaque, int sprn, int gprn)
325 {
326 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_IBAT4L) / 2) + 4);
327 gen_helper_store_ibatl(cpu_env, t0, cpu_gpr[gprn]);
328 tcg_temp_free_i32(t0);
329 }
330
331 /* DBAT0U...DBAT7U */
332 /* DBAT0L...DBAT7L */
333 static void spr_read_dbat (void *opaque, int gprn, int sprn)
334 {
335 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][(sprn - SPR_DBAT0U) / 2]));
336 }
337
338 static void spr_read_dbat_h (void *opaque, int gprn, int sprn)
339 {
340 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, DBAT[sprn & 1][((sprn - SPR_DBAT4U) / 2) + 4]));
341 }
342
343 static void spr_write_dbatu (void *opaque, int sprn, int gprn)
344 {
345 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0U) / 2);
346 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
347 tcg_temp_free_i32(t0);
348 }
349
350 static void spr_write_dbatu_h (void *opaque, int sprn, int gprn)
351 {
352 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4U) / 2) + 4);
353 gen_helper_store_dbatu(cpu_env, t0, cpu_gpr[gprn]);
354 tcg_temp_free_i32(t0);
355 }
356
357 static void spr_write_dbatl (void *opaque, int sprn, int gprn)
358 {
359 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_DBAT0L) / 2);
360 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
361 tcg_temp_free_i32(t0);
362 }
363
364 static void spr_write_dbatl_h (void *opaque, int sprn, int gprn)
365 {
366 TCGv_i32 t0 = tcg_const_i32(((sprn - SPR_DBAT4L) / 2) + 4);
367 gen_helper_store_dbatl(cpu_env, t0, cpu_gpr[gprn]);
368 tcg_temp_free_i32(t0);
369 }
370
371 /* SDR1 */
372 static void spr_write_sdr1 (void *opaque, int sprn, int gprn)
373 {
374 gen_helper_store_sdr1(cpu_env, cpu_gpr[gprn]);
375 }
376
377 /* 64 bits PowerPC specific SPRs */
378 #if defined(TARGET_PPC64)
379 static void spr_read_hior (void *opaque, int gprn, int sprn)
380 {
381 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, excp_prefix));
382 }
383
384 static void spr_write_hior (void *opaque, int sprn, int gprn)
385 {
386 TCGv t0 = tcg_temp_new();
387 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0x3FFFFF00000ULL);
388 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
389 tcg_temp_free(t0);
390 }
391 #endif
392 #endif
393
394 /* PowerPC 601 specific registers */
395 /* RTC */
396 static void spr_read_601_rtcl (void *opaque, int gprn, int sprn)
397 {
398 gen_helper_load_601_rtcl(cpu_gpr[gprn], cpu_env);
399 }
400
401 static void spr_read_601_rtcu (void *opaque, int gprn, int sprn)
402 {
403 gen_helper_load_601_rtcu(cpu_gpr[gprn], cpu_env);
404 }
405
406 #if !defined(CONFIG_USER_ONLY)
407 static void spr_write_601_rtcu (void *opaque, int sprn, int gprn)
408 {
409 gen_helper_store_601_rtcu(cpu_env, cpu_gpr[gprn]);
410 }
411
412 static void spr_write_601_rtcl (void *opaque, int sprn, int gprn)
413 {
414 gen_helper_store_601_rtcl(cpu_env, cpu_gpr[gprn]);
415 }
416
417 static void spr_write_hid0_601 (void *opaque, int sprn, int gprn)
418 {
419 DisasContext *ctx = opaque;
420
421 gen_helper_store_hid0_601(cpu_env, cpu_gpr[gprn]);
422 /* Must stop the translation as endianness may have changed */
423 gen_stop_exception(ctx);
424 }
425 #endif
426
427 /* Unified bats */
428 #if !defined(CONFIG_USER_ONLY)
429 static void spr_read_601_ubat (void *opaque, int gprn, int sprn)
430 {
431 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, IBAT[sprn & 1][(sprn - SPR_IBAT0U) / 2]));
432 }
433
434 static void spr_write_601_ubatu (void *opaque, int sprn, int gprn)
435 {
436 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
437 gen_helper_store_601_batl(cpu_env, t0, cpu_gpr[gprn]);
438 tcg_temp_free_i32(t0);
439 }
440
441 static void spr_write_601_ubatl (void *opaque, int sprn, int gprn)
442 {
443 TCGv_i32 t0 = tcg_const_i32((sprn - SPR_IBAT0U) / 2);
444 gen_helper_store_601_batu(cpu_env, t0, cpu_gpr[gprn]);
445 tcg_temp_free_i32(t0);
446 }
447 #endif
448
449 /* PowerPC 40x specific registers */
450 #if !defined(CONFIG_USER_ONLY)
451 static void spr_read_40x_pit (void *opaque, int gprn, int sprn)
452 {
453 gen_helper_load_40x_pit(cpu_gpr[gprn], cpu_env);
454 }
455
456 static void spr_write_40x_pit (void *opaque, int sprn, int gprn)
457 {
458 gen_helper_store_40x_pit(cpu_env, cpu_gpr[gprn]);
459 }
460
461 static void spr_write_40x_dbcr0 (void *opaque, int sprn, int gprn)
462 {
463 DisasContext *ctx = opaque;
464
465 gen_helper_store_40x_dbcr0(cpu_env, cpu_gpr[gprn]);
466 /* We must stop translation as we may have rebooted */
467 gen_stop_exception(ctx);
468 }
469
470 static void spr_write_40x_sler (void *opaque, int sprn, int gprn)
471 {
472 gen_helper_store_40x_sler(cpu_env, cpu_gpr[gprn]);
473 }
474
475 static void spr_write_booke_tcr (void *opaque, int sprn, int gprn)
476 {
477 gen_helper_store_booke_tcr(cpu_env, cpu_gpr[gprn]);
478 }
479
480 static void spr_write_booke_tsr (void *opaque, int sprn, int gprn)
481 {
482 gen_helper_store_booke_tsr(cpu_env, cpu_gpr[gprn]);
483 }
484 #endif
485
486 /* PowerPC 403 specific registers */
487 /* PBL1 / PBU1 / PBL2 / PBU2 */
488 #if !defined(CONFIG_USER_ONLY)
489 static void spr_read_403_pbr (void *opaque, int gprn, int sprn)
490 {
491 tcg_gen_ld_tl(cpu_gpr[gprn], cpu_env, offsetof(CPUPPCState, pb[sprn - SPR_403_PBL1]));
492 }
493
494 static void spr_write_403_pbr (void *opaque, int sprn, int gprn)
495 {
496 TCGv_i32 t0 = tcg_const_i32(sprn - SPR_403_PBL1);
497 gen_helper_store_403_pbr(cpu_env, t0, cpu_gpr[gprn]);
498 tcg_temp_free_i32(t0);
499 }
500
501 static void spr_write_pir (void *opaque, int sprn, int gprn)
502 {
503 TCGv t0 = tcg_temp_new();
504 tcg_gen_andi_tl(t0, cpu_gpr[gprn], 0xF);
505 gen_store_spr(SPR_PIR, t0);
506 tcg_temp_free(t0);
507 }
508 #endif
509
510 /* SPE specific registers */
511 static void spr_read_spefscr (void *opaque, int gprn, int sprn)
512 {
513 TCGv_i32 t0 = tcg_temp_new_i32();
514 tcg_gen_ld_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
515 tcg_gen_extu_i32_tl(cpu_gpr[gprn], t0);
516 tcg_temp_free_i32(t0);
517 }
518
519 static void spr_write_spefscr (void *opaque, int sprn, int gprn)
520 {
521 TCGv_i32 t0 = tcg_temp_new_i32();
522 tcg_gen_trunc_tl_i32(t0, cpu_gpr[gprn]);
523 tcg_gen_st_i32(t0, cpu_env, offsetof(CPUPPCState, spe_fscr));
524 tcg_temp_free_i32(t0);
525 }
526
527 #if !defined(CONFIG_USER_ONLY)
528 /* Callback used to write the exception vector base */
529 static void spr_write_excp_prefix (void *opaque, int sprn, int gprn)
530 {
531 TCGv t0 = tcg_temp_new();
532 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivpr_mask));
533 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
534 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_prefix));
535 gen_store_spr(sprn, t0);
536 tcg_temp_free(t0);
537 }
538
539 static void spr_write_excp_vector (void *opaque, int sprn, int gprn)
540 {
541 DisasContext *ctx = opaque;
542 int sprn_offs;
543
544 if (sprn >= SPR_BOOKE_IVOR0 && sprn <= SPR_BOOKE_IVOR15) {
545 sprn_offs = sprn - SPR_BOOKE_IVOR0;
546 } else if (sprn >= SPR_BOOKE_IVOR32 && sprn <= SPR_BOOKE_IVOR37) {
547 sprn_offs = sprn - SPR_BOOKE_IVOR32 + 32;
548 } else if (sprn >= SPR_BOOKE_IVOR38 && sprn <= SPR_BOOKE_IVOR42) {
549 sprn_offs = sprn - SPR_BOOKE_IVOR38 + 38;
550 } else {
551 printf("Trying to write an unknown exception vector %d %03x\n",
552 sprn, sprn);
553 gen_inval_exception(ctx, POWERPC_EXCP_PRIV_REG);
554 return;
555 }
556
557 TCGv t0 = tcg_temp_new();
558 tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUPPCState, ivor_mask));
559 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
560 tcg_gen_st_tl(t0, cpu_env, offsetof(CPUPPCState, excp_vectors[sprn_offs]));
561 gen_store_spr(sprn, t0);
562 tcg_temp_free(t0);
563 }
564 #endif
565
566 static inline void vscr_init (CPUPPCState *env, uint32_t val)
567 {
568 env->vscr = val;
569 /* Altivec always uses round-to-nearest */
570 set_float_rounding_mode(float_round_nearest_even, &env->vec_status);
571 set_flush_to_zero(vscr_nj, &env->vec_status);
572 }
573
574 #ifdef CONFIG_USER_ONLY
575 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
576 oea_read, oea_write, one_reg_id, initial_value) \
577 _spr_register(env, num, name, uea_read, uea_write, initial_value)
578 #else
579 #if !defined(CONFIG_KVM)
580 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
581 oea_read, oea_write, one_reg_id, initial_value) \
582 _spr_register(env, num, name, uea_read, uea_write, \
583 oea_read, oea_write, initial_value)
584 #else
585 #define spr_register_kvm(env, num, name, uea_read, uea_write, \
586 oea_read, oea_write, one_reg_id, initial_value) \
587 _spr_register(env, num, name, uea_read, uea_write, \
588 oea_read, oea_write, one_reg_id, initial_value)
589 #endif
590 #endif
591
592 #define spr_register(env, num, name, uea_read, uea_write, \
593 oea_read, oea_write, initial_value) \
594 spr_register_kvm(env, num, name, uea_read, uea_write, \
595 oea_read, oea_write, 0, initial_value)
596
597 static inline void _spr_register(CPUPPCState *env, int num,
598 const char *name,
599 void (*uea_read)(void *opaque, int gprn, int sprn),
600 void (*uea_write)(void *opaque, int sprn, int gprn),
601 #if !defined(CONFIG_USER_ONLY)
602
603 void (*oea_read)(void *opaque, int gprn, int sprn),
604 void (*oea_write)(void *opaque, int sprn, int gprn),
605 #endif
606 #if defined(CONFIG_KVM)
607 uint64_t one_reg_id,
608 #endif
609 target_ulong initial_value)
610 {
611 ppc_spr_t *spr;
612
613 spr = &env->spr_cb[num];
614 if (spr->name != NULL ||env-> spr[num] != 0x00000000 ||
615 #if !defined(CONFIG_USER_ONLY)
616 spr->oea_read != NULL || spr->oea_write != NULL ||
617 #endif
618 spr->uea_read != NULL || spr->uea_write != NULL) {
619 printf("Error: Trying to register SPR %d (%03x) twice !\n", num, num);
620 exit(1);
621 }
622 #if defined(PPC_DEBUG_SPR)
623 printf("*** register spr %d (%03x) %s val " TARGET_FMT_lx "\n", num, num,
624 name, initial_value);
625 #endif
626 spr->name = name;
627 spr->uea_read = uea_read;
628 spr->uea_write = uea_write;
629 #if !defined(CONFIG_USER_ONLY)
630 spr->oea_read = oea_read;
631 spr->oea_write = oea_write;
632 #endif
633 #if defined(CONFIG_KVM)
634 spr->one_reg_id = one_reg_id,
635 #endif
636 env->spr[num] = spr->default_value = initial_value;
637 }
638
639 /* Generic PowerPC SPRs */
640 static void gen_spr_generic (CPUPPCState *env)
641 {
642 /* Integer processing */
643 spr_register(env, SPR_XER, "XER",
644 &spr_read_xer, &spr_write_xer,
645 &spr_read_xer, &spr_write_xer,
646 0x00000000);
647 /* Branch contol */
648 spr_register(env, SPR_LR, "LR",
649 &spr_read_lr, &spr_write_lr,
650 &spr_read_lr, &spr_write_lr,
651 0x00000000);
652 spr_register(env, SPR_CTR, "CTR",
653 &spr_read_ctr, &spr_write_ctr,
654 &spr_read_ctr, &spr_write_ctr,
655 0x00000000);
656 /* Interrupt processing */
657 spr_register(env, SPR_SRR0, "SRR0",
658 SPR_NOACCESS, SPR_NOACCESS,
659 &spr_read_generic, &spr_write_generic,
660 0x00000000);
661 spr_register(env, SPR_SRR1, "SRR1",
662 SPR_NOACCESS, SPR_NOACCESS,
663 &spr_read_generic, &spr_write_generic,
664 0x00000000);
665 /* Processor control */
666 spr_register(env, SPR_SPRG0, "SPRG0",
667 SPR_NOACCESS, SPR_NOACCESS,
668 &spr_read_generic, &spr_write_generic,
669 0x00000000);
670 spr_register(env, SPR_SPRG1, "SPRG1",
671 SPR_NOACCESS, SPR_NOACCESS,
672 &spr_read_generic, &spr_write_generic,
673 0x00000000);
674 spr_register(env, SPR_SPRG2, "SPRG2",
675 SPR_NOACCESS, SPR_NOACCESS,
676 &spr_read_generic, &spr_write_generic,
677 0x00000000);
678 spr_register(env, SPR_SPRG3, "SPRG3",
679 SPR_NOACCESS, SPR_NOACCESS,
680 &spr_read_generic, &spr_write_generic,
681 0x00000000);
682 }
683
684 /* SPR common to all non-embedded PowerPC, including 601 */
685 static void gen_spr_ne_601 (CPUPPCState *env)
686 {
687 /* Exception processing */
688 spr_register_kvm(env, SPR_DSISR, "DSISR",
689 SPR_NOACCESS, SPR_NOACCESS,
690 &spr_read_generic, &spr_write_generic,
691 KVM_REG_PPC_DSISR, 0x00000000);
692 spr_register_kvm(env, SPR_DAR, "DAR",
693 SPR_NOACCESS, SPR_NOACCESS,
694 &spr_read_generic, &spr_write_generic,
695 KVM_REG_PPC_DAR, 0x00000000);
696 /* Timer */
697 spr_register(env, SPR_DECR, "DECR",
698 SPR_NOACCESS, SPR_NOACCESS,
699 &spr_read_decr, &spr_write_decr,
700 0x00000000);
701 /* Memory management */
702 spr_register(env, SPR_SDR1, "SDR1",
703 SPR_NOACCESS, SPR_NOACCESS,
704 &spr_read_generic, &spr_write_sdr1,
705 0x00000000);
706 }
707
708 /* BATs 0-3 */
709 static void gen_low_BATs (CPUPPCState *env)
710 {
711 #if !defined(CONFIG_USER_ONLY)
712 spr_register(env, SPR_IBAT0U, "IBAT0U",
713 SPR_NOACCESS, SPR_NOACCESS,
714 &spr_read_ibat, &spr_write_ibatu,
715 0x00000000);
716 spr_register(env, SPR_IBAT0L, "IBAT0L",
717 SPR_NOACCESS, SPR_NOACCESS,
718 &spr_read_ibat, &spr_write_ibatl,
719 0x00000000);
720 spr_register(env, SPR_IBAT1U, "IBAT1U",
721 SPR_NOACCESS, SPR_NOACCESS,
722 &spr_read_ibat, &spr_write_ibatu,
723 0x00000000);
724 spr_register(env, SPR_IBAT1L, "IBAT1L",
725 SPR_NOACCESS, SPR_NOACCESS,
726 &spr_read_ibat, &spr_write_ibatl,
727 0x00000000);
728 spr_register(env, SPR_IBAT2U, "IBAT2U",
729 SPR_NOACCESS, SPR_NOACCESS,
730 &spr_read_ibat, &spr_write_ibatu,
731 0x00000000);
732 spr_register(env, SPR_IBAT2L, "IBAT2L",
733 SPR_NOACCESS, SPR_NOACCESS,
734 &spr_read_ibat, &spr_write_ibatl,
735 0x00000000);
736 spr_register(env, SPR_IBAT3U, "IBAT3U",
737 SPR_NOACCESS, SPR_NOACCESS,
738 &spr_read_ibat, &spr_write_ibatu,
739 0x00000000);
740 spr_register(env, SPR_IBAT3L, "IBAT3L",
741 SPR_NOACCESS, SPR_NOACCESS,
742 &spr_read_ibat, &spr_write_ibatl,
743 0x00000000);
744 spr_register(env, SPR_DBAT0U, "DBAT0U",
745 SPR_NOACCESS, SPR_NOACCESS,
746 &spr_read_dbat, &spr_write_dbatu,
747 0x00000000);
748 spr_register(env, SPR_DBAT0L, "DBAT0L",
749 SPR_NOACCESS, SPR_NOACCESS,
750 &spr_read_dbat, &spr_write_dbatl,
751 0x00000000);
752 spr_register(env, SPR_DBAT1U, "DBAT1U",
753 SPR_NOACCESS, SPR_NOACCESS,
754 &spr_read_dbat, &spr_write_dbatu,
755 0x00000000);
756 spr_register(env, SPR_DBAT1L, "DBAT1L",
757 SPR_NOACCESS, SPR_NOACCESS,
758 &spr_read_dbat, &spr_write_dbatl,
759 0x00000000);
760 spr_register(env, SPR_DBAT2U, "DBAT2U",
761 SPR_NOACCESS, SPR_NOACCESS,
762 &spr_read_dbat, &spr_write_dbatu,
763 0x00000000);
764 spr_register(env, SPR_DBAT2L, "DBAT2L",
765 SPR_NOACCESS, SPR_NOACCESS,
766 &spr_read_dbat, &spr_write_dbatl,
767 0x00000000);
768 spr_register(env, SPR_DBAT3U, "DBAT3U",
769 SPR_NOACCESS, SPR_NOACCESS,
770 &spr_read_dbat, &spr_write_dbatu,
771 0x00000000);
772 spr_register(env, SPR_DBAT3L, "DBAT3L",
773 SPR_NOACCESS, SPR_NOACCESS,
774 &spr_read_dbat, &spr_write_dbatl,
775 0x00000000);
776 env->nb_BATs += 4;
777 #endif
778 }
779
780 /* BATs 4-7 */
781 static void gen_high_BATs (CPUPPCState *env)
782 {
783 #if !defined(CONFIG_USER_ONLY)
784 spr_register(env, SPR_IBAT4U, "IBAT4U",
785 SPR_NOACCESS, SPR_NOACCESS,
786 &spr_read_ibat_h, &spr_write_ibatu_h,
787 0x00000000);
788 spr_register(env, SPR_IBAT4L, "IBAT4L",
789 SPR_NOACCESS, SPR_NOACCESS,
790 &spr_read_ibat_h, &spr_write_ibatl_h,
791 0x00000000);
792 spr_register(env, SPR_IBAT5U, "IBAT5U",
793 SPR_NOACCESS, SPR_NOACCESS,
794 &spr_read_ibat_h, &spr_write_ibatu_h,
795 0x00000000);
796 spr_register(env, SPR_IBAT5L, "IBAT5L",
797 SPR_NOACCESS, SPR_NOACCESS,
798 &spr_read_ibat_h, &spr_write_ibatl_h,
799 0x00000000);
800 spr_register(env, SPR_IBAT6U, "IBAT6U",
801 SPR_NOACCESS, SPR_NOACCESS,
802 &spr_read_ibat_h, &spr_write_ibatu_h,
803 0x00000000);
804 spr_register(env, SPR_IBAT6L, "IBAT6L",
805 SPR_NOACCESS, SPR_NOACCESS,
806 &spr_read_ibat_h, &spr_write_ibatl_h,
807 0x00000000);
808 spr_register(env, SPR_IBAT7U, "IBAT7U",
809 SPR_NOACCESS, SPR_NOACCESS,
810 &spr_read_ibat_h, &spr_write_ibatu_h,
811 0x00000000);
812 spr_register(env, SPR_IBAT7L, "IBAT7L",
813 SPR_NOACCESS, SPR_NOACCESS,
814 &spr_read_ibat_h, &spr_write_ibatl_h,
815 0x00000000);
816 spr_register(env, SPR_DBAT4U, "DBAT4U",
817 SPR_NOACCESS, SPR_NOACCESS,
818 &spr_read_dbat_h, &spr_write_dbatu_h,
819 0x00000000);
820 spr_register(env, SPR_DBAT4L, "DBAT4L",
821 SPR_NOACCESS, SPR_NOACCESS,
822 &spr_read_dbat_h, &spr_write_dbatl_h,
823 0x00000000);
824 spr_register(env, SPR_DBAT5U, "DBAT5U",
825 SPR_NOACCESS, SPR_NOACCESS,
826 &spr_read_dbat_h, &spr_write_dbatu_h,
827 0x00000000);
828 spr_register(env, SPR_DBAT5L, "DBAT5L",
829 SPR_NOACCESS, SPR_NOACCESS,
830 &spr_read_dbat_h, &spr_write_dbatl_h,
831 0x00000000);
832 spr_register(env, SPR_DBAT6U, "DBAT6U",
833 SPR_NOACCESS, SPR_NOACCESS,
834 &spr_read_dbat_h, &spr_write_dbatu_h,
835 0x00000000);
836 spr_register(env, SPR_DBAT6L, "DBAT6L",
837 SPR_NOACCESS, SPR_NOACCESS,
838 &spr_read_dbat_h, &spr_write_dbatl_h,
839 0x00000000);
840 spr_register(env, SPR_DBAT7U, "DBAT7U",
841 SPR_NOACCESS, SPR_NOACCESS,
842 &spr_read_dbat_h, &spr_write_dbatu_h,
843 0x00000000);
844 spr_register(env, SPR_DBAT7L, "DBAT7L",
845 SPR_NOACCESS, SPR_NOACCESS,
846 &spr_read_dbat_h, &spr_write_dbatl_h,
847 0x00000000);
848 env->nb_BATs += 4;
849 #endif
850 }
851
852 /* Generic PowerPC time base */
853 static void gen_tbl (CPUPPCState *env)
854 {
855 spr_register(env, SPR_VTBL, "TBL",
856 &spr_read_tbl, SPR_NOACCESS,
857 &spr_read_tbl, SPR_NOACCESS,
858 0x00000000);
859 spr_register(env, SPR_TBL, "TBL",
860 &spr_read_tbl, SPR_NOACCESS,
861 &spr_read_tbl, &spr_write_tbl,
862 0x00000000);
863 spr_register(env, SPR_VTBU, "TBU",
864 &spr_read_tbu, SPR_NOACCESS,
865 &spr_read_tbu, SPR_NOACCESS,
866 0x00000000);
867 spr_register(env, SPR_TBU, "TBU",
868 &spr_read_tbu, SPR_NOACCESS,
869 &spr_read_tbu, &spr_write_tbu,
870 0x00000000);
871 }
872
873 /* Softare table search registers */
874 static void gen_6xx_7xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
875 {
876 #if !defined(CONFIG_USER_ONLY)
877 env->nb_tlb = nb_tlbs;
878 env->nb_ways = nb_ways;
879 env->id_tlbs = 1;
880 env->tlb_type = TLB_6XX;
881 spr_register(env, SPR_DMISS, "DMISS",
882 SPR_NOACCESS, SPR_NOACCESS,
883 &spr_read_generic, SPR_NOACCESS,
884 0x00000000);
885 spr_register(env, SPR_DCMP, "DCMP",
886 SPR_NOACCESS, SPR_NOACCESS,
887 &spr_read_generic, SPR_NOACCESS,
888 0x00000000);
889 spr_register(env, SPR_HASH1, "HASH1",
890 SPR_NOACCESS, SPR_NOACCESS,
891 &spr_read_generic, SPR_NOACCESS,
892 0x00000000);
893 spr_register(env, SPR_HASH2, "HASH2",
894 SPR_NOACCESS, SPR_NOACCESS,
895 &spr_read_generic, SPR_NOACCESS,
896 0x00000000);
897 spr_register(env, SPR_IMISS, "IMISS",
898 SPR_NOACCESS, SPR_NOACCESS,
899 &spr_read_generic, SPR_NOACCESS,
900 0x00000000);
901 spr_register(env, SPR_ICMP, "ICMP",
902 SPR_NOACCESS, SPR_NOACCESS,
903 &spr_read_generic, SPR_NOACCESS,
904 0x00000000);
905 spr_register(env, SPR_RPA, "RPA",
906 SPR_NOACCESS, SPR_NOACCESS,
907 &spr_read_generic, &spr_write_generic,
908 0x00000000);
909 #endif
910 }
911
912 /* SPR common to MPC755 and G2 */
913 static void gen_spr_G2_755 (CPUPPCState *env)
914 {
915 /* SGPRs */
916 spr_register(env, SPR_SPRG4, "SPRG4",
917 SPR_NOACCESS, SPR_NOACCESS,
918 &spr_read_generic, &spr_write_generic,
919 0x00000000);
920 spr_register(env, SPR_SPRG5, "SPRG5",
921 SPR_NOACCESS, SPR_NOACCESS,
922 &spr_read_generic, &spr_write_generic,
923 0x00000000);
924 spr_register(env, SPR_SPRG6, "SPRG6",
925 SPR_NOACCESS, SPR_NOACCESS,
926 &spr_read_generic, &spr_write_generic,
927 0x00000000);
928 spr_register(env, SPR_SPRG7, "SPRG7",
929 SPR_NOACCESS, SPR_NOACCESS,
930 &spr_read_generic, &spr_write_generic,
931 0x00000000);
932 }
933
934 /* SPR common to all 7xx PowerPC implementations */
935 static void gen_spr_7xx (CPUPPCState *env)
936 {
937 /* Breakpoints */
938 /* XXX : not implemented */
939 spr_register_kvm(env, SPR_DABR, "DABR",
940 SPR_NOACCESS, SPR_NOACCESS,
941 &spr_read_generic, &spr_write_generic,
942 KVM_REG_PPC_DABR, 0x00000000);
943 /* XXX : not implemented */
944 spr_register(env, SPR_IABR, "IABR",
945 SPR_NOACCESS, SPR_NOACCESS,
946 &spr_read_generic, &spr_write_generic,
947 0x00000000);
948 /* Cache management */
949 /* XXX : not implemented */
950 spr_register(env, SPR_ICTC, "ICTC",
951 SPR_NOACCESS, SPR_NOACCESS,
952 &spr_read_generic, &spr_write_generic,
953 0x00000000);
954 /* Performance monitors */
955 /* XXX : not implemented */
956 spr_register(env, SPR_MMCR0, "MMCR0",
957 SPR_NOACCESS, SPR_NOACCESS,
958 &spr_read_generic, &spr_write_generic,
959 0x00000000);
960 /* XXX : not implemented */
961 spr_register(env, SPR_MMCR1, "MMCR1",
962 SPR_NOACCESS, SPR_NOACCESS,
963 &spr_read_generic, &spr_write_generic,
964 0x00000000);
965 /* XXX : not implemented */
966 spr_register(env, SPR_PMC1, "PMC1",
967 SPR_NOACCESS, SPR_NOACCESS,
968 &spr_read_generic, &spr_write_generic,
969 0x00000000);
970 /* XXX : not implemented */
971 spr_register(env, SPR_PMC2, "PMC2",
972 SPR_NOACCESS, SPR_NOACCESS,
973 &spr_read_generic, &spr_write_generic,
974 0x00000000);
975 /* XXX : not implemented */
976 spr_register(env, SPR_PMC3, "PMC3",
977 SPR_NOACCESS, SPR_NOACCESS,
978 &spr_read_generic, &spr_write_generic,
979 0x00000000);
980 /* XXX : not implemented */
981 spr_register(env, SPR_PMC4, "PMC4",
982 SPR_NOACCESS, SPR_NOACCESS,
983 &spr_read_generic, &spr_write_generic,
984 0x00000000);
985 /* XXX : not implemented */
986 spr_register(env, SPR_SIAR, "SIAR",
987 SPR_NOACCESS, SPR_NOACCESS,
988 &spr_read_generic, SPR_NOACCESS,
989 0x00000000);
990 /* XXX : not implemented */
991 spr_register(env, SPR_UMMCR0, "UMMCR0",
992 &spr_read_ureg, SPR_NOACCESS,
993 &spr_read_ureg, SPR_NOACCESS,
994 0x00000000);
995 /* XXX : not implemented */
996 spr_register(env, SPR_UMMCR1, "UMMCR1",
997 &spr_read_ureg, SPR_NOACCESS,
998 &spr_read_ureg, SPR_NOACCESS,
999 0x00000000);
1000 /* XXX : not implemented */
1001 spr_register(env, SPR_UPMC1, "UPMC1",
1002 &spr_read_ureg, SPR_NOACCESS,
1003 &spr_read_ureg, SPR_NOACCESS,
1004 0x00000000);
1005 /* XXX : not implemented */
1006 spr_register(env, SPR_UPMC2, "UPMC2",
1007 &spr_read_ureg, SPR_NOACCESS,
1008 &spr_read_ureg, SPR_NOACCESS,
1009 0x00000000);
1010 /* XXX : not implemented */
1011 spr_register(env, SPR_UPMC3, "UPMC3",
1012 &spr_read_ureg, SPR_NOACCESS,
1013 &spr_read_ureg, SPR_NOACCESS,
1014 0x00000000);
1015 /* XXX : not implemented */
1016 spr_register(env, SPR_UPMC4, "UPMC4",
1017 &spr_read_ureg, SPR_NOACCESS,
1018 &spr_read_ureg, SPR_NOACCESS,
1019 0x00000000);
1020 /* XXX : not implemented */
1021 spr_register(env, SPR_USIAR, "USIAR",
1022 &spr_read_ureg, SPR_NOACCESS,
1023 &spr_read_ureg, SPR_NOACCESS,
1024 0x00000000);
1025 /* External access control */
1026 /* XXX : not implemented */
1027 spr_register(env, SPR_EAR, "EAR",
1028 SPR_NOACCESS, SPR_NOACCESS,
1029 &spr_read_generic, &spr_write_generic,
1030 0x00000000);
1031 }
1032
1033 #ifdef TARGET_PPC64
1034 #ifndef CONFIG_USER_ONLY
1035 static void spr_read_uamr (void *opaque, int gprn, int sprn)
1036 {
1037 gen_load_spr(cpu_gpr[gprn], SPR_AMR);
1038 spr_load_dump_spr(SPR_AMR);
1039 }
1040
1041 static void spr_write_uamr (void *opaque, int sprn, int gprn)
1042 {
1043 gen_store_spr(SPR_AMR, cpu_gpr[gprn]);
1044 spr_store_dump_spr(SPR_AMR);
1045 }
1046
1047 static void spr_write_uamr_pr (void *opaque, int sprn, int gprn)
1048 {
1049 TCGv t0 = tcg_temp_new();
1050
1051 gen_load_spr(t0, SPR_UAMOR);
1052 tcg_gen_and_tl(t0, t0, cpu_gpr[gprn]);
1053 gen_store_spr(SPR_AMR, t0);
1054 spr_store_dump_spr(SPR_AMR);
1055 }
1056 #endif /* CONFIG_USER_ONLY */
1057
1058 static void gen_spr_amr (CPUPPCState *env)
1059 {
1060 #ifndef CONFIG_USER_ONLY
1061 /* Virtual Page Class Key protection */
1062 /* The AMR is accessible either via SPR 13 or SPR 29. 13 is
1063 * userspace accessible, 29 is privileged. So we only need to set
1064 * the kvm ONE_REG id on one of them, we use 29 */
1065 spr_register(env, SPR_UAMR, "UAMR",
1066 &spr_read_uamr, &spr_write_uamr_pr,
1067 &spr_read_uamr, &spr_write_uamr,
1068 0);
1069 spr_register_kvm(env, SPR_AMR, "AMR",
1070 SPR_NOACCESS, SPR_NOACCESS,
1071 &spr_read_generic, &spr_write_generic,
1072 KVM_REG_PPC_AMR, 0);
1073 spr_register_kvm(env, SPR_UAMOR, "UAMOR",
1074 SPR_NOACCESS, SPR_NOACCESS,
1075 &spr_read_generic, &spr_write_generic,
1076 KVM_REG_PPC_UAMOR, 0);
1077 #endif /* !CONFIG_USER_ONLY */
1078 }
1079 #endif /* TARGET_PPC64 */
1080
1081 static void gen_spr_thrm (CPUPPCState *env)
1082 {
1083 /* Thermal management */
1084 /* XXX : not implemented */
1085 spr_register(env, SPR_THRM1, "THRM1",
1086 SPR_NOACCESS, SPR_NOACCESS,
1087 &spr_read_generic, &spr_write_generic,
1088 0x00000000);
1089 /* XXX : not implemented */
1090 spr_register(env, SPR_THRM2, "THRM2",
1091 SPR_NOACCESS, SPR_NOACCESS,
1092 &spr_read_generic, &spr_write_generic,
1093 0x00000000);
1094 /* XXX : not implemented */
1095 spr_register(env, SPR_THRM3, "THRM3",
1096 SPR_NOACCESS, SPR_NOACCESS,
1097 &spr_read_generic, &spr_write_generic,
1098 0x00000000);
1099 }
1100
1101 /* SPR specific to PowerPC 604 implementation */
1102 static void gen_spr_604 (CPUPPCState *env)
1103 {
1104 /* Processor identification */
1105 spr_register(env, SPR_PIR, "PIR",
1106 SPR_NOACCESS, SPR_NOACCESS,
1107 &spr_read_generic, &spr_write_pir,
1108 0x00000000);
1109 /* Breakpoints */
1110 /* XXX : not implemented */
1111 spr_register(env, SPR_IABR, "IABR",
1112 SPR_NOACCESS, SPR_NOACCESS,
1113 &spr_read_generic, &spr_write_generic,
1114 0x00000000);
1115 /* XXX : not implemented */
1116 spr_register_kvm(env, SPR_DABR, "DABR",
1117 SPR_NOACCESS, SPR_NOACCESS,
1118 &spr_read_generic, &spr_write_generic,
1119 KVM_REG_PPC_DABR, 0x00000000);
1120 /* Performance counters */
1121 /* XXX : not implemented */
1122 spr_register(env, SPR_MMCR0, "MMCR0",
1123 SPR_NOACCESS, SPR_NOACCESS,
1124 &spr_read_generic, &spr_write_generic,
1125 0x00000000);
1126 /* XXX : not implemented */
1127 spr_register(env, SPR_PMC1, "PMC1",
1128 SPR_NOACCESS, SPR_NOACCESS,
1129 &spr_read_generic, &spr_write_generic,
1130 0x00000000);
1131 /* XXX : not implemented */
1132 spr_register(env, SPR_PMC2, "PMC2",
1133 SPR_NOACCESS, SPR_NOACCESS,
1134 &spr_read_generic, &spr_write_generic,
1135 0x00000000);
1136 /* XXX : not implemented */
1137 spr_register(env, SPR_SIAR, "SIAR",
1138 SPR_NOACCESS, SPR_NOACCESS,
1139 &spr_read_generic, SPR_NOACCESS,
1140 0x00000000);
1141 /* XXX : not implemented */
1142 spr_register(env, SPR_SDA, "SDA",
1143 SPR_NOACCESS, SPR_NOACCESS,
1144 &spr_read_generic, SPR_NOACCESS,
1145 0x00000000);
1146 /* External access control */
1147 /* XXX : not implemented */
1148 spr_register(env, SPR_EAR, "EAR",
1149 SPR_NOACCESS, SPR_NOACCESS,
1150 &spr_read_generic, &spr_write_generic,
1151 0x00000000);
1152 }
1153
1154 /* SPR specific to PowerPC 603 implementation */
1155 static void gen_spr_603 (CPUPPCState *env)
1156 {
1157 /* External access control */
1158 /* XXX : not implemented */
1159 spr_register(env, SPR_EAR, "EAR",
1160 SPR_NOACCESS, SPR_NOACCESS,
1161 &spr_read_generic, &spr_write_generic,
1162 0x00000000);
1163 /* Breakpoints */
1164 /* XXX : not implemented */
1165 spr_register(env, SPR_IABR, "IABR",
1166 SPR_NOACCESS, SPR_NOACCESS,
1167 &spr_read_generic, &spr_write_generic,
1168 0x00000000);
1169
1170 }
1171
1172 /* SPR specific to PowerPC G2 implementation */
1173 static void gen_spr_G2 (CPUPPCState *env)
1174 {
1175 /* Memory base address */
1176 /* MBAR */
1177 /* XXX : not implemented */
1178 spr_register(env, SPR_MBAR, "MBAR",
1179 SPR_NOACCESS, SPR_NOACCESS,
1180 &spr_read_generic, &spr_write_generic,
1181 0x00000000);
1182 /* Exception processing */
1183 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1184 SPR_NOACCESS, SPR_NOACCESS,
1185 &spr_read_generic, &spr_write_generic,
1186 0x00000000);
1187 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1188 SPR_NOACCESS, SPR_NOACCESS,
1189 &spr_read_generic, &spr_write_generic,
1190 0x00000000);
1191 /* Breakpoints */
1192 /* XXX : not implemented */
1193 spr_register(env, SPR_DABR, "DABR",
1194 SPR_NOACCESS, SPR_NOACCESS,
1195 &spr_read_generic, &spr_write_generic,
1196 0x00000000);
1197 /* XXX : not implemented */
1198 spr_register(env, SPR_DABR2, "DABR2",
1199 SPR_NOACCESS, SPR_NOACCESS,
1200 &spr_read_generic, &spr_write_generic,
1201 0x00000000);
1202 /* XXX : not implemented */
1203 spr_register(env, SPR_IABR, "IABR",
1204 SPR_NOACCESS, SPR_NOACCESS,
1205 &spr_read_generic, &spr_write_generic,
1206 0x00000000);
1207 /* XXX : not implemented */
1208 spr_register(env, SPR_IABR2, "IABR2",
1209 SPR_NOACCESS, SPR_NOACCESS,
1210 &spr_read_generic, &spr_write_generic,
1211 0x00000000);
1212 /* XXX : not implemented */
1213 spr_register(env, SPR_IBCR, "IBCR",
1214 SPR_NOACCESS, SPR_NOACCESS,
1215 &spr_read_generic, &spr_write_generic,
1216 0x00000000);
1217 /* XXX : not implemented */
1218 spr_register(env, SPR_DBCR, "DBCR",
1219 SPR_NOACCESS, SPR_NOACCESS,
1220 &spr_read_generic, &spr_write_generic,
1221 0x00000000);
1222 }
1223
1224 /* SPR specific to PowerPC 602 implementation */
1225 static void gen_spr_602 (CPUPPCState *env)
1226 {
1227 /* ESA registers */
1228 /* XXX : not implemented */
1229 spr_register(env, SPR_SER, "SER",
1230 SPR_NOACCESS, SPR_NOACCESS,
1231 &spr_read_generic, &spr_write_generic,
1232 0x00000000);
1233 /* XXX : not implemented */
1234 spr_register(env, SPR_SEBR, "SEBR",
1235 SPR_NOACCESS, SPR_NOACCESS,
1236 &spr_read_generic, &spr_write_generic,
1237 0x00000000);
1238 /* XXX : not implemented */
1239 spr_register(env, SPR_ESASRR, "ESASRR",
1240 SPR_NOACCESS, SPR_NOACCESS,
1241 &spr_read_generic, &spr_write_generic,
1242 0x00000000);
1243 /* Floating point status */
1244 /* XXX : not implemented */
1245 spr_register(env, SPR_SP, "SP",
1246 SPR_NOACCESS, SPR_NOACCESS,
1247 &spr_read_generic, &spr_write_generic,
1248 0x00000000);
1249 /* XXX : not implemented */
1250 spr_register(env, SPR_LT, "LT",
1251 SPR_NOACCESS, SPR_NOACCESS,
1252 &spr_read_generic, &spr_write_generic,
1253 0x00000000);
1254 /* Watchdog timer */
1255 /* XXX : not implemented */
1256 spr_register(env, SPR_TCR, "TCR",
1257 SPR_NOACCESS, SPR_NOACCESS,
1258 &spr_read_generic, &spr_write_generic,
1259 0x00000000);
1260 /* Interrupt base */
1261 spr_register(env, SPR_IBR, "IBR",
1262 SPR_NOACCESS, SPR_NOACCESS,
1263 &spr_read_generic, &spr_write_generic,
1264 0x00000000);
1265 /* XXX : not implemented */
1266 spr_register(env, SPR_IABR, "IABR",
1267 SPR_NOACCESS, SPR_NOACCESS,
1268 &spr_read_generic, &spr_write_generic,
1269 0x00000000);
1270 }
1271
1272 /* SPR specific to PowerPC 601 implementation */
1273 static void gen_spr_601 (CPUPPCState *env)
1274 {
1275 /* Multiplication/division register */
1276 /* MQ */
1277 spr_register(env, SPR_MQ, "MQ",
1278 &spr_read_generic, &spr_write_generic,
1279 &spr_read_generic, &spr_write_generic,
1280 0x00000000);
1281 /* RTC registers */
1282 spr_register(env, SPR_601_RTCU, "RTCU",
1283 SPR_NOACCESS, SPR_NOACCESS,
1284 SPR_NOACCESS, &spr_write_601_rtcu,
1285 0x00000000);
1286 spr_register(env, SPR_601_VRTCU, "RTCU",
1287 &spr_read_601_rtcu, SPR_NOACCESS,
1288 &spr_read_601_rtcu, SPR_NOACCESS,
1289 0x00000000);
1290 spr_register(env, SPR_601_RTCL, "RTCL",
1291 SPR_NOACCESS, SPR_NOACCESS,
1292 SPR_NOACCESS, &spr_write_601_rtcl,
1293 0x00000000);
1294 spr_register(env, SPR_601_VRTCL, "RTCL",
1295 &spr_read_601_rtcl, SPR_NOACCESS,
1296 &spr_read_601_rtcl, SPR_NOACCESS,
1297 0x00000000);
1298 /* Timer */
1299 #if 0 /* ? */
1300 spr_register(env, SPR_601_UDECR, "UDECR",
1301 &spr_read_decr, SPR_NOACCESS,
1302 &spr_read_decr, SPR_NOACCESS,
1303 0x00000000);
1304 #endif
1305 /* External access control */
1306 /* XXX : not implemented */
1307 spr_register(env, SPR_EAR, "EAR",
1308 SPR_NOACCESS, SPR_NOACCESS,
1309 &spr_read_generic, &spr_write_generic,
1310 0x00000000);
1311 /* Memory management */
1312 #if !defined(CONFIG_USER_ONLY)
1313 spr_register(env, SPR_IBAT0U, "IBAT0U",
1314 SPR_NOACCESS, SPR_NOACCESS,
1315 &spr_read_601_ubat, &spr_write_601_ubatu,
1316 0x00000000);
1317 spr_register(env, SPR_IBAT0L, "IBAT0L",
1318 SPR_NOACCESS, SPR_NOACCESS,
1319 &spr_read_601_ubat, &spr_write_601_ubatl,
1320 0x00000000);
1321 spr_register(env, SPR_IBAT1U, "IBAT1U",
1322 SPR_NOACCESS, SPR_NOACCESS,
1323 &spr_read_601_ubat, &spr_write_601_ubatu,
1324 0x00000000);
1325 spr_register(env, SPR_IBAT1L, "IBAT1L",
1326 SPR_NOACCESS, SPR_NOACCESS,
1327 &spr_read_601_ubat, &spr_write_601_ubatl,
1328 0x00000000);
1329 spr_register(env, SPR_IBAT2U, "IBAT2U",
1330 SPR_NOACCESS, SPR_NOACCESS,
1331 &spr_read_601_ubat, &spr_write_601_ubatu,
1332 0x00000000);
1333 spr_register(env, SPR_IBAT2L, "IBAT2L",
1334 SPR_NOACCESS, SPR_NOACCESS,
1335 &spr_read_601_ubat, &spr_write_601_ubatl,
1336 0x00000000);
1337 spr_register(env, SPR_IBAT3U, "IBAT3U",
1338 SPR_NOACCESS, SPR_NOACCESS,
1339 &spr_read_601_ubat, &spr_write_601_ubatu,
1340 0x00000000);
1341 spr_register(env, SPR_IBAT3L, "IBAT3L",
1342 SPR_NOACCESS, SPR_NOACCESS,
1343 &spr_read_601_ubat, &spr_write_601_ubatl,
1344 0x00000000);
1345 env->nb_BATs = 4;
1346 #endif
1347 }
1348
1349 static void gen_spr_74xx (CPUPPCState *env)
1350 {
1351 /* Processor identification */
1352 spr_register(env, SPR_PIR, "PIR",
1353 SPR_NOACCESS, SPR_NOACCESS,
1354 &spr_read_generic, &spr_write_pir,
1355 0x00000000);
1356 /* XXX : not implemented */
1357 spr_register(env, SPR_MMCR2, "MMCR2",
1358 SPR_NOACCESS, SPR_NOACCESS,
1359 &spr_read_generic, &spr_write_generic,
1360 0x00000000);
1361 /* XXX : not implemented */
1362 spr_register(env, SPR_UMMCR2, "UMMCR2",
1363 &spr_read_ureg, SPR_NOACCESS,
1364 &spr_read_ureg, SPR_NOACCESS,
1365 0x00000000);
1366 /* XXX: not implemented */
1367 spr_register(env, SPR_BAMR, "BAMR",
1368 SPR_NOACCESS, SPR_NOACCESS,
1369 &spr_read_generic, &spr_write_generic,
1370 0x00000000);
1371 /* XXX : not implemented */
1372 spr_register(env, SPR_MSSCR0, "MSSCR0",
1373 SPR_NOACCESS, SPR_NOACCESS,
1374 &spr_read_generic, &spr_write_generic,
1375 0x00000000);
1376 /* Hardware implementation registers */
1377 /* XXX : not implemented */
1378 spr_register(env, SPR_HID0, "HID0",
1379 SPR_NOACCESS, SPR_NOACCESS,
1380 &spr_read_generic, &spr_write_generic,
1381 0x00000000);
1382 /* XXX : not implemented */
1383 spr_register(env, SPR_HID1, "HID1",
1384 SPR_NOACCESS, SPR_NOACCESS,
1385 &spr_read_generic, &spr_write_generic,
1386 0x00000000);
1387 /* Altivec */
1388 spr_register(env, SPR_VRSAVE, "VRSAVE",
1389 &spr_read_generic, &spr_write_generic,
1390 &spr_read_generic, &spr_write_generic,
1391 0x00000000);
1392 /* XXX : not implemented */
1393 spr_register(env, SPR_L2CR, "L2CR",
1394 SPR_NOACCESS, SPR_NOACCESS,
1395 &spr_read_generic, spr_access_nop,
1396 0x00000000);
1397 /* Not strictly an SPR */
1398 vscr_init(env, 0x00010000);
1399 }
1400
1401 static void gen_l3_ctrl (CPUPPCState *env)
1402 {
1403 /* L3CR */
1404 /* XXX : not implemented */
1405 spr_register(env, SPR_L3CR, "L3CR",
1406 SPR_NOACCESS, SPR_NOACCESS,
1407 &spr_read_generic, &spr_write_generic,
1408 0x00000000);
1409 /* L3ITCR0 */
1410 /* XXX : not implemented */
1411 spr_register(env, SPR_L3ITCR0, "L3ITCR0",
1412 SPR_NOACCESS, SPR_NOACCESS,
1413 &spr_read_generic, &spr_write_generic,
1414 0x00000000);
1415 /* L3PM */
1416 /* XXX : not implemented */
1417 spr_register(env, SPR_L3PM, "L3PM",
1418 SPR_NOACCESS, SPR_NOACCESS,
1419 &spr_read_generic, &spr_write_generic,
1420 0x00000000);
1421 }
1422
1423 static void gen_74xx_soft_tlb (CPUPPCState *env, int nb_tlbs, int nb_ways)
1424 {
1425 #if !defined(CONFIG_USER_ONLY)
1426 env->nb_tlb = nb_tlbs;
1427 env->nb_ways = nb_ways;
1428 env->id_tlbs = 1;
1429 env->tlb_type = TLB_6XX;
1430 /* XXX : not implemented */
1431 spr_register(env, SPR_PTEHI, "PTEHI",
1432 SPR_NOACCESS, SPR_NOACCESS,
1433 &spr_read_generic, &spr_write_generic,
1434 0x00000000);
1435 /* XXX : not implemented */
1436 spr_register(env, SPR_PTELO, "PTELO",
1437 SPR_NOACCESS, SPR_NOACCESS,
1438 &spr_read_generic, &spr_write_generic,
1439 0x00000000);
1440 /* XXX : not implemented */
1441 spr_register(env, SPR_TLBMISS, "TLBMISS",
1442 SPR_NOACCESS, SPR_NOACCESS,
1443 &spr_read_generic, &spr_write_generic,
1444 0x00000000);
1445 #endif
1446 }
1447
1448 #if !defined(CONFIG_USER_ONLY)
1449 static void spr_write_e500_l1csr0 (void *opaque, int sprn, int gprn)
1450 {
1451 TCGv t0 = tcg_temp_new();
1452
1453 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR0_DCE | L1CSR0_CPE);
1454 gen_store_spr(sprn, t0);
1455 tcg_temp_free(t0);
1456 }
1457
1458 static void spr_write_e500_l1csr1(void *opaque, int sprn, int gprn)
1459 {
1460 TCGv t0 = tcg_temp_new();
1461
1462 tcg_gen_andi_tl(t0, cpu_gpr[gprn], L1CSR1_ICE | L1CSR1_CPE);
1463 gen_store_spr(sprn, t0);
1464 tcg_temp_free(t0);
1465 }
1466
1467 static void spr_write_booke206_mmucsr0 (void *opaque, int sprn, int gprn)
1468 {
1469 gen_helper_booke206_tlbflush(cpu_env, cpu_gpr[gprn]);
1470 }
1471
1472 static void spr_write_booke_pid (void *opaque, int sprn, int gprn)
1473 {
1474 TCGv_i32 t0 = tcg_const_i32(sprn);
1475 gen_helper_booke_setpid(cpu_env, t0, cpu_gpr[gprn]);
1476 tcg_temp_free_i32(t0);
1477 }
1478 #endif
1479
1480 static void gen_spr_usprgh (CPUPPCState *env)
1481 {
1482 spr_register(env, SPR_USPRG4, "USPRG4",
1483 &spr_read_ureg, SPR_NOACCESS,
1484 &spr_read_ureg, SPR_NOACCESS,
1485 0x00000000);
1486 spr_register(env, SPR_USPRG5, "USPRG5",
1487 &spr_read_ureg, SPR_NOACCESS,
1488 &spr_read_ureg, SPR_NOACCESS,
1489 0x00000000);
1490 spr_register(env, SPR_USPRG6, "USPRG6",
1491 &spr_read_ureg, SPR_NOACCESS,
1492 &spr_read_ureg, SPR_NOACCESS,
1493 0x00000000);
1494 spr_register(env, SPR_USPRG7, "USPRG7",
1495 &spr_read_ureg, SPR_NOACCESS,
1496 &spr_read_ureg, SPR_NOACCESS,
1497 0x00000000);
1498 }
1499
1500 /* PowerPC BookE SPR */
1501 static void gen_spr_BookE (CPUPPCState *env, uint64_t ivor_mask)
1502 {
1503 const char *ivor_names[64] = {
1504 "IVOR0", "IVOR1", "IVOR2", "IVOR3",
1505 "IVOR4", "IVOR5", "IVOR6", "IVOR7",
1506 "IVOR8", "IVOR9", "IVOR10", "IVOR11",
1507 "IVOR12", "IVOR13", "IVOR14", "IVOR15",
1508 "IVOR16", "IVOR17", "IVOR18", "IVOR19",
1509 "IVOR20", "IVOR21", "IVOR22", "IVOR23",
1510 "IVOR24", "IVOR25", "IVOR26", "IVOR27",
1511 "IVOR28", "IVOR29", "IVOR30", "IVOR31",
1512 "IVOR32", "IVOR33", "IVOR34", "IVOR35",
1513 "IVOR36", "IVOR37", "IVOR38", "IVOR39",
1514 "IVOR40", "IVOR41", "IVOR42", "IVOR43",
1515 "IVOR44", "IVOR45", "IVOR46", "IVOR47",
1516 "IVOR48", "IVOR49", "IVOR50", "IVOR51",
1517 "IVOR52", "IVOR53", "IVOR54", "IVOR55",
1518 "IVOR56", "IVOR57", "IVOR58", "IVOR59",
1519 "IVOR60", "IVOR61", "IVOR62", "IVOR63",
1520 };
1521 #define SPR_BOOKE_IVORxx (-1)
1522 int ivor_sprn[64] = {
1523 SPR_BOOKE_IVOR0, SPR_BOOKE_IVOR1, SPR_BOOKE_IVOR2, SPR_BOOKE_IVOR3,
1524 SPR_BOOKE_IVOR4, SPR_BOOKE_IVOR5, SPR_BOOKE_IVOR6, SPR_BOOKE_IVOR7,
1525 SPR_BOOKE_IVOR8, SPR_BOOKE_IVOR9, SPR_BOOKE_IVOR10, SPR_BOOKE_IVOR11,
1526 SPR_BOOKE_IVOR12, SPR_BOOKE_IVOR13, SPR_BOOKE_IVOR14, SPR_BOOKE_IVOR15,
1527 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1528 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1529 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1530 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1531 SPR_BOOKE_IVOR32, SPR_BOOKE_IVOR33, SPR_BOOKE_IVOR34, SPR_BOOKE_IVOR35,
1532 SPR_BOOKE_IVOR36, SPR_BOOKE_IVOR37, SPR_BOOKE_IVOR38, SPR_BOOKE_IVOR39,
1533 SPR_BOOKE_IVOR40, SPR_BOOKE_IVOR41, SPR_BOOKE_IVOR42, SPR_BOOKE_IVORxx,
1534 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1535 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1536 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1537 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1538 SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx, SPR_BOOKE_IVORxx,
1539 };
1540 int i;
1541
1542 /* Interrupt processing */
1543 spr_register(env, SPR_BOOKE_CSRR0, "CSRR0",
1544 SPR_NOACCESS, SPR_NOACCESS,
1545 &spr_read_generic, &spr_write_generic,
1546 0x00000000);
1547 spr_register(env, SPR_BOOKE_CSRR1, "CSRR1",
1548 SPR_NOACCESS, SPR_NOACCESS,
1549 &spr_read_generic, &spr_write_generic,
1550 0x00000000);
1551 /* Debug */
1552 /* XXX : not implemented */
1553 spr_register(env, SPR_BOOKE_IAC1, "IAC1",
1554 SPR_NOACCESS, SPR_NOACCESS,
1555 &spr_read_generic, &spr_write_generic,
1556 0x00000000);
1557 /* XXX : not implemented */
1558 spr_register(env, SPR_BOOKE_IAC2, "IAC2",
1559 SPR_NOACCESS, SPR_NOACCESS,
1560 &spr_read_generic, &spr_write_generic,
1561 0x00000000);
1562 /* XXX : not implemented */
1563 spr_register(env, SPR_BOOKE_DAC1, "DAC1",
1564 SPR_NOACCESS, SPR_NOACCESS,
1565 &spr_read_generic, &spr_write_generic,
1566 0x00000000);
1567 /* XXX : not implemented */
1568 spr_register(env, SPR_BOOKE_DAC2, "DAC2",
1569 SPR_NOACCESS, SPR_NOACCESS,
1570 &spr_read_generic, &spr_write_generic,
1571 0x00000000);
1572 /* XXX : not implemented */
1573 spr_register(env, SPR_BOOKE_DBCR0, "DBCR0",
1574 SPR_NOACCESS, SPR_NOACCESS,
1575 &spr_read_generic, &spr_write_40x_dbcr0,
1576 0x00000000);
1577 /* XXX : not implemented */
1578 spr_register(env, SPR_BOOKE_DBCR1, "DBCR1",
1579 SPR_NOACCESS, SPR_NOACCESS,
1580 &spr_read_generic, &spr_write_generic,
1581 0x00000000);
1582 /* XXX : not implemented */
1583 spr_register(env, SPR_BOOKE_DBCR2, "DBCR2",
1584 SPR_NOACCESS, SPR_NOACCESS,
1585 &spr_read_generic, &spr_write_generic,
1586 0x00000000);
1587 /* XXX : not implemented */
1588 spr_register(env, SPR_BOOKE_DBSR, "DBSR",
1589 SPR_NOACCESS, SPR_NOACCESS,
1590 &spr_read_generic, &spr_write_clear,
1591 0x00000000);
1592 spr_register(env, SPR_BOOKE_DEAR, "DEAR",
1593 SPR_NOACCESS, SPR_NOACCESS,
1594 &spr_read_generic, &spr_write_generic,
1595 0x00000000);
1596 spr_register(env, SPR_BOOKE_ESR, "ESR",
1597 SPR_NOACCESS, SPR_NOACCESS,
1598 &spr_read_generic, &spr_write_generic,
1599 0x00000000);
1600 spr_register(env, SPR_BOOKE_IVPR, "IVPR",
1601 SPR_NOACCESS, SPR_NOACCESS,
1602 &spr_read_generic, &spr_write_excp_prefix,
1603 0x00000000);
1604 /* Exception vectors */
1605 for (i = 0; i < 64; i++) {
1606 if (ivor_mask & (1ULL << i)) {
1607 if (ivor_sprn[i] == SPR_BOOKE_IVORxx) {
1608 fprintf(stderr, "ERROR: IVOR %d SPR is not defined\n", i);
1609 exit(1);
1610 }
1611 spr_register(env, ivor_sprn[i], ivor_names[i],
1612 SPR_NOACCESS, SPR_NOACCESS,
1613 &spr_read_generic, &spr_write_excp_vector,
1614 0x00000000);
1615 }
1616 }
1617 spr_register(env, SPR_BOOKE_PID, "PID",
1618 SPR_NOACCESS, SPR_NOACCESS,
1619 &spr_read_generic, &spr_write_booke_pid,
1620 0x00000000);
1621 spr_register(env, SPR_BOOKE_TCR, "TCR",
1622 SPR_NOACCESS, SPR_NOACCESS,
1623 &spr_read_generic, &spr_write_booke_tcr,
1624 0x00000000);
1625 spr_register(env, SPR_BOOKE_TSR, "TSR",
1626 SPR_NOACCESS, SPR_NOACCESS,
1627 &spr_read_generic, &spr_write_booke_tsr,
1628 0x00000000);
1629 /* Timer */
1630 spr_register(env, SPR_DECR, "DECR",
1631 SPR_NOACCESS, SPR_NOACCESS,
1632 &spr_read_decr, &spr_write_decr,
1633 0x00000000);
1634 spr_register(env, SPR_BOOKE_DECAR, "DECAR",
1635 SPR_NOACCESS, SPR_NOACCESS,
1636 SPR_NOACCESS, &spr_write_generic,
1637 0x00000000);
1638 /* SPRGs */
1639 spr_register(env, SPR_USPRG0, "USPRG0",
1640 &spr_read_generic, &spr_write_generic,
1641 &spr_read_generic, &spr_write_generic,
1642 0x00000000);
1643 spr_register(env, SPR_SPRG4, "SPRG4",
1644 SPR_NOACCESS, SPR_NOACCESS,
1645 &spr_read_generic, &spr_write_generic,
1646 0x00000000);
1647 spr_register(env, SPR_SPRG5, "SPRG5",
1648 SPR_NOACCESS, SPR_NOACCESS,
1649 &spr_read_generic, &spr_write_generic,
1650 0x00000000);
1651 spr_register(env, SPR_SPRG6, "SPRG6",
1652 SPR_NOACCESS, SPR_NOACCESS,
1653 &spr_read_generic, &spr_write_generic,
1654 0x00000000);
1655 spr_register(env, SPR_SPRG7, "SPRG7",
1656 SPR_NOACCESS, SPR_NOACCESS,
1657 &spr_read_generic, &spr_write_generic,
1658 0x00000000);
1659 }
1660
1661 static inline uint32_t gen_tlbncfg(uint32_t assoc, uint32_t minsize,
1662 uint32_t maxsize, uint32_t flags,
1663 uint32_t nentries)
1664 {
1665 return (assoc << TLBnCFG_ASSOC_SHIFT) |
1666 (minsize << TLBnCFG_MINSIZE_SHIFT) |
1667 (maxsize << TLBnCFG_MAXSIZE_SHIFT) |
1668 flags | nentries;
1669 }
1670
1671 /* BookE 2.06 storage control registers */
1672 static void gen_spr_BookE206(CPUPPCState *env, uint32_t mas_mask,
1673 uint32_t *tlbncfg)
1674 {
1675 #if !defined(CONFIG_USER_ONLY)
1676 const char *mas_names[8] = {
1677 "MAS0", "MAS1", "MAS2", "MAS3", "MAS4", "MAS5", "MAS6", "MAS7",
1678 };
1679 int mas_sprn[8] = {
1680 SPR_BOOKE_MAS0, SPR_BOOKE_MAS1, SPR_BOOKE_MAS2, SPR_BOOKE_MAS3,
1681 SPR_BOOKE_MAS4, SPR_BOOKE_MAS5, SPR_BOOKE_MAS6, SPR_BOOKE_MAS7,
1682 };
1683 int i;
1684
1685 /* TLB assist registers */
1686 /* XXX : not implemented */
1687 for (i = 0; i < 8; i++) {
1688 void (*uea_write)(void *o, int sprn, int gprn) = &spr_write_generic32;
1689 if (i == 2 && (mas_mask & (1 << i)) && (env->insns_flags & PPC_64B)) {
1690 uea_write = &spr_write_generic;
1691 }
1692 if (mas_mask & (1 << i)) {
1693 spr_register(env, mas_sprn[i], mas_names[i],
1694 SPR_NOACCESS, SPR_NOACCESS,
1695 &spr_read_generic, uea_write,
1696 0x00000000);
1697 }
1698 }
1699 if (env->nb_pids > 1) {
1700 /* XXX : not implemented */
1701 spr_register(env, SPR_BOOKE_PID1, "PID1",
1702 SPR_NOACCESS, SPR_NOACCESS,
1703 &spr_read_generic, &spr_write_booke_pid,
1704 0x00000000);
1705 }
1706 if (env->nb_pids > 2) {
1707 /* XXX : not implemented */
1708 spr_register(env, SPR_BOOKE_PID2, "PID2",
1709 SPR_NOACCESS, SPR_NOACCESS,
1710 &spr_read_generic, &spr_write_booke_pid,
1711 0x00000000);
1712 }
1713 /* XXX : not implemented */
1714 spr_register(env, SPR_MMUCFG, "MMUCFG",
1715 SPR_NOACCESS, SPR_NOACCESS,
1716 &spr_read_generic, SPR_NOACCESS,
1717 0x00000000); /* TOFIX */
1718 switch (env->nb_ways) {
1719 case 4:
1720 spr_register(env, SPR_BOOKE_TLB3CFG, "TLB3CFG",
1721 SPR_NOACCESS, SPR_NOACCESS,
1722 &spr_read_generic, SPR_NOACCESS,
1723 tlbncfg[3]);
1724 /* Fallthru */
1725 case 3:
1726 spr_register(env, SPR_BOOKE_TLB2CFG, "TLB2CFG",
1727 SPR_NOACCESS, SPR_NOACCESS,
1728 &spr_read_generic, SPR_NOACCESS,
1729 tlbncfg[2]);
1730 /* Fallthru */
1731 case 2:
1732 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
1733 SPR_NOACCESS, SPR_NOACCESS,
1734 &spr_read_generic, SPR_NOACCESS,
1735 tlbncfg[1]);
1736 /* Fallthru */
1737 case 1:
1738 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
1739 SPR_NOACCESS, SPR_NOACCESS,
1740 &spr_read_generic, SPR_NOACCESS,
1741 tlbncfg[0]);
1742 /* Fallthru */
1743 case 0:
1744 default:
1745 break;
1746 }
1747 #endif
1748
1749 gen_spr_usprgh(env);
1750 }
1751
1752 /* SPR specific to PowerPC 440 implementation */
1753 static void gen_spr_440 (CPUPPCState *env)
1754 {
1755 /* Cache control */
1756 /* XXX : not implemented */
1757 spr_register(env, SPR_440_DNV0, "DNV0",
1758 SPR_NOACCESS, SPR_NOACCESS,
1759 &spr_read_generic, &spr_write_generic,
1760 0x00000000);
1761 /* XXX : not implemented */
1762 spr_register(env, SPR_440_DNV1, "DNV1",
1763 SPR_NOACCESS, SPR_NOACCESS,
1764 &spr_read_generic, &spr_write_generic,
1765 0x00000000);
1766 /* XXX : not implemented */
1767 spr_register(env, SPR_440_DNV2, "DNV2",
1768 SPR_NOACCESS, SPR_NOACCESS,
1769 &spr_read_generic, &spr_write_generic,
1770 0x00000000);
1771 /* XXX : not implemented */
1772 spr_register(env, SPR_440_DNV3, "DNV3",
1773 SPR_NOACCESS, SPR_NOACCESS,
1774 &spr_read_generic, &spr_write_generic,
1775 0x00000000);
1776 /* XXX : not implemented */
1777 spr_register(env, SPR_440_DTV0, "DTV0",
1778 SPR_NOACCESS, SPR_NOACCESS,
1779 &spr_read_generic, &spr_write_generic,
1780 0x00000000);
1781 /* XXX : not implemented */
1782 spr_register(env, SPR_440_DTV1, "DTV1",
1783 SPR_NOACCESS, SPR_NOACCESS,
1784 &spr_read_generic, &spr_write_generic,
1785 0x00000000);
1786 /* XXX : not implemented */
1787 spr_register(env, SPR_440_DTV2, "DTV2",
1788 SPR_NOACCESS, SPR_NOACCESS,
1789 &spr_read_generic, &spr_write_generic,
1790 0x00000000);
1791 /* XXX : not implemented */
1792 spr_register(env, SPR_440_DTV3, "DTV3",
1793 SPR_NOACCESS, SPR_NOACCESS,
1794 &spr_read_generic, &spr_write_generic,
1795 0x00000000);
1796 /* XXX : not implemented */
1797 spr_register(env, SPR_440_DVLIM, "DVLIM",
1798 SPR_NOACCESS, SPR_NOACCESS,
1799 &spr_read_generic, &spr_write_generic,
1800 0x00000000);
1801 /* XXX : not implemented */
1802 spr_register(env, SPR_440_INV0, "INV0",
1803 SPR_NOACCESS, SPR_NOACCESS,
1804 &spr_read_generic, &spr_write_generic,
1805 0x00000000);
1806 /* XXX : not implemented */
1807 spr_register(env, SPR_440_INV1, "INV1",
1808 SPR_NOACCESS, SPR_NOACCESS,
1809 &spr_read_generic, &spr_write_generic,
1810 0x00000000);
1811 /* XXX : not implemented */
1812 spr_register(env, SPR_440_INV2, "INV2",
1813 SPR_NOACCESS, SPR_NOACCESS,
1814 &spr_read_generic, &spr_write_generic,
1815 0x00000000);
1816 /* XXX : not implemented */
1817 spr_register(env, SPR_440_INV3, "INV3",
1818 SPR_NOACCESS, SPR_NOACCESS,
1819 &spr_read_generic, &spr_write_generic,
1820 0x00000000);
1821 /* XXX : not implemented */
1822 spr_register(env, SPR_440_ITV0, "ITV0",
1823 SPR_NOACCESS, SPR_NOACCESS,
1824 &spr_read_generic, &spr_write_generic,
1825 0x00000000);
1826 /* XXX : not implemented */
1827 spr_register(env, SPR_440_ITV1, "ITV1",
1828 SPR_NOACCESS, SPR_NOACCESS,
1829 &spr_read_generic, &spr_write_generic,
1830 0x00000000);
1831 /* XXX : not implemented */
1832 spr_register(env, SPR_440_ITV2, "ITV2",
1833 SPR_NOACCESS, SPR_NOACCESS,
1834 &spr_read_generic, &spr_write_generic,
1835 0x00000000);
1836 /* XXX : not implemented */
1837 spr_register(env, SPR_440_ITV3, "ITV3",
1838 SPR_NOACCESS, SPR_NOACCESS,
1839 &spr_read_generic, &spr_write_generic,
1840 0x00000000);
1841 /* XXX : not implemented */
1842 spr_register(env, SPR_440_IVLIM, "IVLIM",
1843 SPR_NOACCESS, SPR_NOACCESS,
1844 &spr_read_generic, &spr_write_generic,
1845 0x00000000);
1846 /* Cache debug */
1847 /* XXX : not implemented */
1848 spr_register(env, SPR_BOOKE_DCDBTRH, "DCDBTRH",
1849 SPR_NOACCESS, SPR_NOACCESS,
1850 &spr_read_generic, SPR_NOACCESS,
1851 0x00000000);
1852 /* XXX : not implemented */
1853 spr_register(env, SPR_BOOKE_DCDBTRL, "DCDBTRL",
1854 SPR_NOACCESS, SPR_NOACCESS,
1855 &spr_read_generic, SPR_NOACCESS,
1856 0x00000000);
1857 /* XXX : not implemented */
1858 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1859 SPR_NOACCESS, SPR_NOACCESS,
1860 &spr_read_generic, SPR_NOACCESS,
1861 0x00000000);
1862 /* XXX : not implemented */
1863 spr_register(env, SPR_BOOKE_ICDBTRH, "ICDBTRH",
1864 SPR_NOACCESS, SPR_NOACCESS,
1865 &spr_read_generic, SPR_NOACCESS,
1866 0x00000000);
1867 /* XXX : not implemented */
1868 spr_register(env, SPR_BOOKE_ICDBTRL, "ICDBTRL",
1869 SPR_NOACCESS, SPR_NOACCESS,
1870 &spr_read_generic, SPR_NOACCESS,
1871 0x00000000);
1872 /* XXX : not implemented */
1873 spr_register(env, SPR_440_DBDR, "DBDR",
1874 SPR_NOACCESS, SPR_NOACCESS,
1875 &spr_read_generic, &spr_write_generic,
1876 0x00000000);
1877 /* Processor control */
1878 spr_register(env, SPR_4xx_CCR0, "CCR0",
1879 SPR_NOACCESS, SPR_NOACCESS,
1880 &spr_read_generic, &spr_write_generic,
1881 0x00000000);
1882 spr_register(env, SPR_440_RSTCFG, "RSTCFG",
1883 SPR_NOACCESS, SPR_NOACCESS,
1884 &spr_read_generic, SPR_NOACCESS,
1885 0x00000000);
1886 /* Storage control */
1887 spr_register(env, SPR_440_MMUCR, "MMUCR",
1888 SPR_NOACCESS, SPR_NOACCESS,
1889 &spr_read_generic, &spr_write_generic,
1890 0x00000000);
1891 }
1892
1893 /* SPR shared between PowerPC 40x implementations */
1894 static void gen_spr_40x (CPUPPCState *env)
1895 {
1896 /* Cache */
1897 /* not emulated, as QEMU do not emulate caches */
1898 spr_register(env, SPR_40x_DCCR, "DCCR",
1899 SPR_NOACCESS, SPR_NOACCESS,
1900 &spr_read_generic, &spr_write_generic,
1901 0x00000000);
1902 /* not emulated, as QEMU do not emulate caches */
1903 spr_register(env, SPR_40x_ICCR, "ICCR",
1904 SPR_NOACCESS, SPR_NOACCESS,
1905 &spr_read_generic, &spr_write_generic,
1906 0x00000000);
1907 /* not emulated, as QEMU do not emulate caches */
1908 spr_register(env, SPR_BOOKE_ICDBDR, "ICDBDR",
1909 SPR_NOACCESS, SPR_NOACCESS,
1910 &spr_read_generic, SPR_NOACCESS,
1911 0x00000000);
1912 /* Exception */
1913 spr_register(env, SPR_40x_DEAR, "DEAR",
1914 SPR_NOACCESS, SPR_NOACCESS,
1915 &spr_read_generic, &spr_write_generic,
1916 0x00000000);
1917 spr_register(env, SPR_40x_ESR, "ESR",
1918 SPR_NOACCESS, SPR_NOACCESS,
1919 &spr_read_generic, &spr_write_generic,
1920 0x00000000);
1921 spr_register(env, SPR_40x_EVPR, "EVPR",
1922 SPR_NOACCESS, SPR_NOACCESS,
1923 &spr_read_generic, &spr_write_excp_prefix,
1924 0x00000000);
1925 spr_register(env, SPR_40x_SRR2, "SRR2",
1926 &spr_read_generic, &spr_write_generic,
1927 &spr_read_generic, &spr_write_generic,
1928 0x00000000);
1929 spr_register(env, SPR_40x_SRR3, "SRR3",
1930 &spr_read_generic, &spr_write_generic,
1931 &spr_read_generic, &spr_write_generic,
1932 0x00000000);
1933 /* Timers */
1934 spr_register(env, SPR_40x_PIT, "PIT",
1935 SPR_NOACCESS, SPR_NOACCESS,
1936 &spr_read_40x_pit, &spr_write_40x_pit,
1937 0x00000000);
1938 spr_register(env, SPR_40x_TCR, "TCR",
1939 SPR_NOACCESS, SPR_NOACCESS,
1940 &spr_read_generic, &spr_write_booke_tcr,
1941 0x00000000);
1942 spr_register(env, SPR_40x_TSR, "TSR",
1943 SPR_NOACCESS, SPR_NOACCESS,
1944 &spr_read_generic, &spr_write_booke_tsr,
1945 0x00000000);
1946 }
1947
1948 /* SPR specific to PowerPC 405 implementation */
1949 static void gen_spr_405 (CPUPPCState *env)
1950 {
1951 /* MMU */
1952 spr_register(env, SPR_40x_PID, "PID",
1953 SPR_NOACCESS, SPR_NOACCESS,
1954 &spr_read_generic, &spr_write_generic,
1955 0x00000000);
1956 spr_register(env, SPR_4xx_CCR0, "CCR0",
1957 SPR_NOACCESS, SPR_NOACCESS,
1958 &spr_read_generic, &spr_write_generic,
1959 0x00700000);
1960 /* Debug interface */
1961 /* XXX : not implemented */
1962 spr_register(env, SPR_40x_DBCR0, "DBCR0",
1963 SPR_NOACCESS, SPR_NOACCESS,
1964 &spr_read_generic, &spr_write_40x_dbcr0,
1965 0x00000000);
1966 /* XXX : not implemented */
1967 spr_register(env, SPR_405_DBCR1, "DBCR1",
1968 SPR_NOACCESS, SPR_NOACCESS,
1969 &spr_read_generic, &spr_write_generic,
1970 0x00000000);
1971 /* XXX : not implemented */
1972 spr_register(env, SPR_40x_DBSR, "DBSR",
1973 SPR_NOACCESS, SPR_NOACCESS,
1974 &spr_read_generic, &spr_write_clear,
1975 /* Last reset was system reset */
1976 0x00000300);
1977 /* XXX : not implemented */
1978 spr_register(env, SPR_40x_DAC1, "DAC1",
1979 SPR_NOACCESS, SPR_NOACCESS,
1980 &spr_read_generic, &spr_write_generic,
1981 0x00000000);
1982 spr_register(env, SPR_40x_DAC2, "DAC2",
1983 SPR_NOACCESS, SPR_NOACCESS,
1984 &spr_read_generic, &spr_write_generic,
1985 0x00000000);
1986 /* XXX : not implemented */
1987 spr_register(env, SPR_405_DVC1, "DVC1",
1988 SPR_NOACCESS, SPR_NOACCESS,
1989 &spr_read_generic, &spr_write_generic,
1990 0x00000000);
1991 /* XXX : not implemented */
1992 spr_register(env, SPR_405_DVC2, "DVC2",
1993 SPR_NOACCESS, SPR_NOACCESS,
1994 &spr_read_generic, &spr_write_generic,
1995 0x00000000);
1996 /* XXX : not implemented */
1997 spr_register(env, SPR_40x_IAC1, "IAC1",
1998 SPR_NOACCESS, SPR_NOACCESS,
1999 &spr_read_generic, &spr_write_generic,
2000 0x00000000);
2001 spr_register(env, SPR_40x_IAC2, "IAC2",
2002 SPR_NOACCESS, SPR_NOACCESS,
2003 &spr_read_generic, &spr_write_generic,
2004 0x00000000);
2005 /* XXX : not implemented */
2006 spr_register(env, SPR_405_IAC3, "IAC3",
2007 SPR_NOACCESS, SPR_NOACCESS,
2008 &spr_read_generic, &spr_write_generic,
2009 0x00000000);
2010 /* XXX : not implemented */
2011 spr_register(env, SPR_405_IAC4, "IAC4",
2012 SPR_NOACCESS, SPR_NOACCESS,
2013 &spr_read_generic, &spr_write_generic,
2014 0x00000000);
2015 /* Storage control */
2016 /* XXX: TODO: not implemented */
2017 spr_register(env, SPR_405_SLER, "SLER",
2018 SPR_NOACCESS, SPR_NOACCESS,
2019 &spr_read_generic, &spr_write_40x_sler,
2020 0x00000000);
2021 spr_register(env, SPR_40x_ZPR, "ZPR",
2022 SPR_NOACCESS, SPR_NOACCESS,
2023 &spr_read_generic, &spr_write_generic,
2024 0x00000000);
2025 /* XXX : not implemented */
2026 spr_register(env, SPR_405_SU0R, "SU0R",
2027 SPR_NOACCESS, SPR_NOACCESS,
2028 &spr_read_generic, &spr_write_generic,
2029 0x00000000);
2030 /* SPRG */
2031 spr_register(env, SPR_USPRG0, "USPRG0",
2032 &spr_read_ureg, SPR_NOACCESS,
2033 &spr_read_ureg, SPR_NOACCESS,
2034 0x00000000);
2035 spr_register(env, SPR_SPRG4, "SPRG4",
2036 SPR_NOACCESS, SPR_NOACCESS,
2037 &spr_read_generic, &spr_write_generic,
2038 0x00000000);
2039 spr_register(env, SPR_SPRG5, "SPRG5",
2040 SPR_NOACCESS, SPR_NOACCESS,
2041 spr_read_generic, &spr_write_generic,
2042 0x00000000);
2043 spr_register(env, SPR_SPRG6, "SPRG6",
2044 SPR_NOACCESS, SPR_NOACCESS,
2045 spr_read_generic, &spr_write_generic,
2046 0x00000000);
2047 spr_register(env, SPR_SPRG7, "SPRG7",
2048 SPR_NOACCESS, SPR_NOACCESS,
2049 spr_read_generic, &spr_write_generic,
2050 0x00000000);
2051 gen_spr_usprgh(env);
2052 }
2053
2054 /* SPR shared between PowerPC 401 & 403 implementations */
2055 static void gen_spr_401_403 (CPUPPCState *env)
2056 {
2057 /* Time base */
2058 spr_register(env, SPR_403_VTBL, "TBL",
2059 &spr_read_tbl, SPR_NOACCESS,
2060 &spr_read_tbl, SPR_NOACCESS,
2061 0x00000000);
2062 spr_register(env, SPR_403_TBL, "TBL",
2063 SPR_NOACCESS, SPR_NOACCESS,
2064 SPR_NOACCESS, &spr_write_tbl,
2065 0x00000000);
2066 spr_register(env, SPR_403_VTBU, "TBU",
2067 &spr_read_tbu, SPR_NOACCESS,
2068 &spr_read_tbu, SPR_NOACCESS,
2069 0x00000000);
2070 spr_register(env, SPR_403_TBU, "TBU",
2071 SPR_NOACCESS, SPR_NOACCESS,
2072 SPR_NOACCESS, &spr_write_tbu,
2073 0x00000000);
2074 /* Debug */
2075 /* not emulated, as QEMU do not emulate caches */
2076 spr_register(env, SPR_403_CDBCR, "CDBCR",
2077 SPR_NOACCESS, SPR_NOACCESS,
2078 &spr_read_generic, &spr_write_generic,
2079 0x00000000);
2080 }
2081
2082 /* SPR specific to PowerPC 401 implementation */
2083 static void gen_spr_401 (CPUPPCState *env)
2084 {
2085 /* Debug interface */
2086 /* XXX : not implemented */
2087 spr_register(env, SPR_40x_DBCR0, "DBCR",
2088 SPR_NOACCESS, SPR_NOACCESS,
2089 &spr_read_generic, &spr_write_40x_dbcr0,
2090 0x00000000);
2091 /* XXX : not implemented */
2092 spr_register(env, SPR_40x_DBSR, "DBSR",
2093 SPR_NOACCESS, SPR_NOACCESS,
2094 &spr_read_generic, &spr_write_clear,
2095 /* Last reset was system reset */
2096 0x00000300);
2097 /* XXX : not implemented */
2098 spr_register(env, SPR_40x_DAC1, "DAC",
2099 SPR_NOACCESS, SPR_NOACCESS,
2100 &spr_read_generic, &spr_write_generic,
2101 0x00000000);
2102 /* XXX : not implemented */
2103 spr_register(env, SPR_40x_IAC1, "IAC",
2104 SPR_NOACCESS, SPR_NOACCESS,
2105 &spr_read_generic, &spr_write_generic,
2106 0x00000000);
2107 /* Storage control */
2108 /* XXX: TODO: not implemented */
2109 spr_register(env, SPR_405_SLER, "SLER",
2110 SPR_NOACCESS, SPR_NOACCESS,
2111 &spr_read_generic, &spr_write_40x_sler,
2112 0x00000000);
2113 /* not emulated, as QEMU never does speculative access */
2114 spr_register(env, SPR_40x_SGR, "SGR",
2115 SPR_NOACCESS, SPR_NOACCESS,
2116 &spr_read_generic, &spr_write_generic,
2117 0xFFFFFFFF);
2118 /* not emulated, as QEMU do not emulate caches */
2119 spr_register(env, SPR_40x_DCWR, "DCWR",
2120 SPR_NOACCESS, SPR_NOACCESS,
2121 &spr_read_generic, &spr_write_generic,
2122 0x00000000);
2123 }
2124
2125 static void gen_spr_401x2 (CPUPPCState *env)
2126 {
2127 gen_spr_401(env);
2128 spr_register(env, SPR_40x_PID, "PID",
2129 SPR_NOACCESS, SPR_NOACCESS,
2130 &spr_read_generic, &spr_write_generic,
2131 0x00000000);
2132 spr_register(env, SPR_40x_ZPR, "ZPR",
2133 SPR_NOACCESS, SPR_NOACCESS,
2134 &spr_read_generic, &spr_write_generic,
2135 0x00000000);
2136 }
2137
2138 /* SPR specific to PowerPC 403 implementation */
2139 static void gen_spr_403 (CPUPPCState *env)
2140 {
2141 /* Debug interface */
2142 /* XXX : not implemented */
2143 spr_register(env, SPR_40x_DBCR0, "DBCR0",
2144 SPR_NOACCESS, SPR_NOACCESS,
2145 &spr_read_generic, &spr_write_40x_dbcr0,
2146 0x00000000);
2147 /* XXX : not implemented */
2148 spr_register(env, SPR_40x_DBSR, "DBSR",
2149 SPR_NOACCESS, SPR_NOACCESS,
2150 &spr_read_generic, &spr_write_clear,
2151 /* Last reset was system reset */
2152 0x00000300);
2153 /* XXX : not implemented */
2154 spr_register(env, SPR_40x_DAC1, "DAC1",
2155 SPR_NOACCESS, SPR_NOACCESS,
2156 &spr_read_generic, &spr_write_generic,
2157 0x00000000);
2158 /* XXX : not implemented */
2159 spr_register(env, SPR_40x_DAC2, "DAC2",
2160 SPR_NOACCESS, SPR_NOACCESS,
2161 &spr_read_generic, &spr_write_generic,
2162 0x00000000);
2163 /* XXX : not implemented */
2164 spr_register(env, SPR_40x_IAC1, "IAC1",
2165 SPR_NOACCESS, SPR_NOACCESS,
2166 &spr_read_generic, &spr_write_generic,
2167 0x00000000);
2168 /* XXX : not implemented */
2169 spr_register(env, SPR_40x_IAC2, "IAC2",
2170 SPR_NOACCESS, SPR_NOACCESS,
2171 &spr_read_generic, &spr_write_generic,
2172 0x00000000);
2173 }
2174
2175 static void gen_spr_403_real (CPUPPCState *env)
2176 {
2177 spr_register(env, SPR_403_PBL1, "PBL1",
2178 SPR_NOACCESS, SPR_NOACCESS,
2179 &spr_read_403_pbr, &spr_write_403_pbr,
2180 0x00000000);
2181 spr_register(env, SPR_403_PBU1, "PBU1",
2182 SPR_NOACCESS, SPR_NOACCESS,
2183 &spr_read_403_pbr, &spr_write_403_pbr,
2184 0x00000000);
2185 spr_register(env, SPR_403_PBL2, "PBL2",
2186 SPR_NOACCESS, SPR_NOACCESS,
2187 &spr_read_403_pbr, &spr_write_403_pbr,
2188 0x00000000);
2189 spr_register(env, SPR_403_PBU2, "PBU2",
2190 SPR_NOACCESS, SPR_NOACCESS,
2191 &spr_read_403_pbr, &spr_write_403_pbr,
2192 0x00000000);
2193 }
2194
2195 static void gen_spr_403_mmu (CPUPPCState *env)
2196 {
2197 /* MMU */
2198 spr_register(env, SPR_40x_PID, "PID",
2199 SPR_NOACCESS, SPR_NOACCESS,
2200 &spr_read_generic, &spr_write_generic,
2201 0x00000000);
2202 spr_register(env, SPR_40x_ZPR, "ZPR",
2203 SPR_NOACCESS, SPR_NOACCESS,
2204 &spr_read_generic, &spr_write_generic,
2205 0x00000000);
2206 }
2207
2208 /* SPR specific to PowerPC compression coprocessor extension */
2209 static void gen_spr_compress (CPUPPCState *env)
2210 {
2211 /* XXX : not implemented */
2212 spr_register(env, SPR_401_SKR, "SKR",
2213 SPR_NOACCESS, SPR_NOACCESS,
2214 &spr_read_generic, &spr_write_generic,
2215 0x00000000);
2216 }
2217
2218 static void gen_spr_5xx_8xx (CPUPPCState *env)
2219 {
2220 /* Exception processing */
2221 spr_register_kvm(env, SPR_DSISR, "DSISR",
2222 SPR_NOACCESS, SPR_NOACCESS,
2223 &spr_read_generic, &spr_write_generic,
2224 KVM_REG_PPC_DSISR, 0x00000000);
2225 spr_register_kvm(env, SPR_DAR, "DAR",
2226 SPR_NOACCESS, SPR_NOACCESS,
2227 &spr_read_generic, &spr_write_generic,
2228 KVM_REG_PPC_DAR, 0x00000000);
2229 /* Timer */
2230 spr_register(env, SPR_DECR, "DECR",
2231 SPR_NOACCESS, SPR_NOACCESS,
2232 &spr_read_decr, &spr_write_decr,
2233 0x00000000);
2234 /* XXX : not implemented */
2235 spr_register(env, SPR_MPC_EIE, "EIE",
2236 SPR_NOACCESS, SPR_NOACCESS,
2237 &spr_read_generic, &spr_write_generic,
2238 0x00000000);
2239 /* XXX : not implemented */
2240 spr_register(env, SPR_MPC_EID, "EID",
2241 SPR_NOACCESS, SPR_NOACCESS,
2242 &spr_read_generic, &spr_write_generic,
2243 0x00000000);
2244 /* XXX : not implemented */
2245 spr_register(env, SPR_MPC_NRI, "NRI",
2246 SPR_NOACCESS, SPR_NOACCESS,
2247 &spr_read_generic, &spr_write_generic,
2248 0x00000000);
2249 /* XXX : not implemented */
2250 spr_register(env, SPR_MPC_CMPA, "CMPA",
2251 SPR_NOACCESS, SPR_NOACCESS,
2252 &spr_read_generic, &spr_write_generic,
2253 0x00000000);
2254 /* XXX : not implemented */
2255 spr_register(env, SPR_MPC_CMPB, "CMPB",
2256 SPR_NOACCESS, SPR_NOACCESS,
2257 &spr_read_generic, &spr_write_generic,
2258 0x00000000);
2259 /* XXX : not implemented */
2260 spr_register(env, SPR_MPC_CMPC, "CMPC",
2261 SPR_NOACCESS, SPR_NOACCESS,
2262 &spr_read_generic, &spr_write_generic,
2263 0x00000000);
2264 /* XXX : not implemented */
2265 spr_register(env, SPR_MPC_CMPD, "CMPD",
2266 SPR_NOACCESS, SPR_NOACCESS,
2267 &spr_read_generic, &spr_write_generic,
2268 0x00000000);
2269 /* XXX : not implemented */
2270 spr_register(env, SPR_MPC_ECR, "ECR",
2271 SPR_NOACCESS, SPR_NOACCESS,
2272 &spr_read_generic, &spr_write_generic,
2273 0x00000000);
2274 /* XXX : not implemented */
2275 spr_register(env, SPR_MPC_DER, "DER",
2276 SPR_NOACCESS, SPR_NOACCESS,
2277 &spr_read_generic, &spr_write_generic,
2278 0x00000000);
2279 /* XXX : not implemented */
2280 spr_register(env, SPR_MPC_COUNTA, "COUNTA",
2281 SPR_NOACCESS, SPR_NOACCESS,
2282 &spr_read_generic, &spr_write_generic,
2283 0x00000000);
2284 /* XXX : not implemented */
2285 spr_register(env, SPR_MPC_COUNTB, "COUNTB",
2286 SPR_NOACCESS, SPR_NOACCESS,
2287 &spr_read_generic, &spr_write_generic,
2288 0x00000000);
2289 /* XXX : not implemented */
2290 spr_register(env, SPR_MPC_CMPE, "CMPE",
2291 SPR_NOACCESS, SPR_NOACCESS,
2292 &spr_read_generic, &spr_write_generic,
2293 0x00000000);
2294 /* XXX : not implemented */
2295 spr_register(env, SPR_MPC_CMPF, "CMPF",
2296 SPR_NOACCESS, SPR_NOACCESS,
2297 &spr_read_generic, &spr_write_generic,
2298 0x00000000);
2299 /* XXX : not implemented */
2300 spr_register(env, SPR_MPC_CMPG, "CMPG",
2301 SPR_NOACCESS, SPR_NOACCESS,
2302 &spr_read_generic, &spr_write_generic,
2303 0x00000000);
2304 /* XXX : not implemented */
2305 spr_register(env, SPR_MPC_CMPH, "CMPH",
2306 SPR_NOACCESS, SPR_NOACCESS,
2307 &spr_read_generic, &spr_write_generic,
2308 0x00000000);
2309 /* XXX : not implemented */
2310 spr_register(env, SPR_MPC_LCTRL1, "LCTRL1",
2311 SPR_NOACCESS, SPR_NOACCESS,
2312 &spr_read_generic, &spr_write_generic,
2313 0x00000000);
2314 /* XXX : not implemented */
2315 spr_register(env, SPR_MPC_LCTRL2, "LCTRL2",
2316 SPR_NOACCESS, SPR_NOACCESS,
2317 &spr_read_generic, &spr_write_generic,
2318 0x00000000);
2319 /* XXX : not implemented */
2320 spr_register(env, SPR_MPC_BAR, "BAR",
2321 SPR_NOACCESS, SPR_NOACCESS,
2322 &spr_read_generic, &spr_write_generic,
2323 0x00000000);
2324 /* XXX : not implemented */
2325 spr_register(env, SPR_MPC_DPDR, "DPDR",
2326 SPR_NOACCESS, SPR_NOACCESS,
2327 &spr_read_generic, &spr_write_generic,
2328 0x00000000);
2329 /* XXX : not implemented */
2330 spr_register(env, SPR_MPC_IMMR, "IMMR",
2331 SPR_NOACCESS, SPR_NOACCESS,
2332 &spr_read_generic, &spr_write_generic,
2333 0x00000000);
2334 }
2335
2336 static void gen_spr_5xx (CPUPPCState *env)
2337 {
2338 /* XXX : not implemented */
2339 spr_register(env, SPR_RCPU_MI_GRA, "MI_GRA",
2340 SPR_NOACCESS, SPR_NOACCESS,
2341 &spr_read_generic, &spr_write_generic,
2342 0x00000000);
2343 /* XXX : not implemented */
2344 spr_register(env, SPR_RCPU_L2U_GRA, "L2U_GRA",
2345 SPR_NOACCESS, SPR_NOACCESS,
2346 &spr_read_generic, &spr_write_generic,
2347 0x00000000);
2348 /* XXX : not implemented */
2349 spr_register(env, SPR_RPCU_BBCMCR, "L2U_BBCMCR",
2350 SPR_NOACCESS, SPR_NOACCESS,
2351 &spr_read_generic, &spr_write_generic,
2352 0x00000000);
2353 /* XXX : not implemented */
2354 spr_register(env, SPR_RCPU_L2U_MCR, "L2U_MCR",
2355 SPR_NOACCESS, SPR_NOACCESS,
2356 &spr_read_generic, &spr_write_generic,
2357 0x00000000);
2358 /* XXX : not implemented */
2359 spr_register(env, SPR_RCPU_MI_RBA0, "MI_RBA0",
2360 SPR_NOACCESS, SPR_NOACCESS,
2361 &spr_read_generic, &spr_write_generic,
2362 0x00000000);
2363 /* XXX : not implemented */
2364 spr_register(env, SPR_RCPU_MI_RBA1, "MI_RBA1",
2365 SPR_NOACCESS, SPR_NOACCESS,
2366 &spr_read_generic, &spr_write_generic,
2367 0x00000000);
2368 /* XXX : not implemented */
2369 spr_register(env, SPR_RCPU_MI_RBA2, "MI_RBA2",
2370 SPR_NOACCESS, SPR_NOACCESS,
2371 &spr_read_generic, &spr_write_generic,
2372 0x00000000);
2373 /* XXX : not implemented */
2374 spr_register(env, SPR_RCPU_MI_RBA3, "MI_RBA3",
2375 SPR_NOACCESS, SPR_NOACCESS,
2376 &spr_read_generic, &spr_write_generic,
2377 0x00000000);
2378 /* XXX : not implemented */
2379 spr_register(env, SPR_RCPU_L2U_RBA0, "L2U_RBA0",
2380 SPR_NOACCESS, SPR_NOACCESS,
2381 &spr_read_generic, &spr_write_generic,
2382 0x00000000);
2383 /* XXX : not implemented */
2384 spr_register(env, SPR_RCPU_L2U_RBA1, "L2U_RBA1",
2385 SPR_NOACCESS, SPR_NOACCESS,
2386 &spr_read_generic, &spr_write_generic,
2387 0x00000000);
2388 /* XXX : not implemented */
2389 spr_register(env, SPR_RCPU_L2U_RBA2, "L2U_RBA2",
2390 SPR_NOACCESS, SPR_NOACCESS,
2391 &spr_read_generic, &spr_write_generic,
2392 0x00000000);
2393 /* XXX : not implemented */
2394 spr_register(env, SPR_RCPU_L2U_RBA3, "L2U_RBA3",
2395 SPR_NOACCESS, SPR_NOACCESS,
2396 &spr_read_generic, &spr_write_generic,
2397 0x00000000);
2398 /* XXX : not implemented */
2399 spr_register(env, SPR_RCPU_MI_RA0, "MI_RA0",
2400 SPR_NOACCESS, SPR_NOACCESS,
2401 &spr_read_generic, &spr_write_generic,
2402 0x00000000);
2403 /* XXX : not implemented */
2404 spr_register(env, SPR_RCPU_MI_RA1, "MI_RA1",
2405 SPR_NOACCESS, SPR_NOACCESS,
2406 &spr_read_generic, &spr_write_generic,
2407 0x00000000);
2408 /* XXX : not implemented */
2409 spr_register(env, SPR_RCPU_MI_RA2, "MI_RA2",
2410 SPR_NOACCESS, SPR_NOACCESS,
2411 &spr_read_generic, &spr_write_generic,
2412 0x00000000);
2413 /* XXX : not implemented */
2414 spr_register(env, SPR_RCPU_MI_RA3, "MI_RA3",
2415 SPR_NOACCESS, SPR_NOACCESS,
2416 &spr_read_generic, &spr_write_generic,
2417 0x00000000);
2418 /* XXX : not implemented */
2419 spr_register(env, SPR_RCPU_L2U_RA0, "L2U_RA0",
2420 SPR_NOACCESS, SPR_NOACCESS,
2421 &spr_read_generic, &spr_write_generic,
2422 0x00000000);
2423 /* XXX : not implemented */
2424 spr_register(env, SPR_RCPU_L2U_RA1, "L2U_RA1",
2425 SPR_NOACCESS, SPR_NOACCESS,
2426 &spr_read_generic, &spr_write_generic,
2427 0x00000000);
2428 /* XXX : not implemented */
2429 spr_register(env, SPR_RCPU_L2U_RA2, "L2U_RA2",
2430 SPR_NOACCESS, SPR_NOACCESS,
2431 &spr_read_generic, &spr_write_generic,
2432 0x00000000);
2433 /* XXX : not implemented */
2434 spr_register(env, SPR_RCPU_L2U_RA3, "L2U_RA3",
2435 SPR_NOACCESS, SPR_NOACCESS,
2436 &spr_read_generic, &spr_write_generic,
2437 0x00000000);
2438 /* XXX : not implemented */
2439 spr_register(env, SPR_RCPU_FPECR, "FPECR",
2440 SPR_NOACCESS, SPR_NOACCESS,
2441 &spr_read_generic, &spr_write_generic,
2442 0x00000000);
2443 }
2444
2445 static void gen_spr_8xx (CPUPPCState *env)
2446 {
2447 /* XXX : not implemented */
2448 spr_register(env, SPR_MPC_IC_CST, "IC_CST",
2449 SPR_NOACCESS, SPR_NOACCESS,
2450 &spr_read_generic, &spr_write_generic,
2451 0x00000000);
2452 /* XXX : not implemented */
2453 spr_register(env, SPR_MPC_IC_ADR, "IC_ADR",
2454 SPR_NOACCESS, SPR_NOACCESS,
2455 &spr_read_generic, &spr_write_generic,
2456 0x00000000);
2457 /* XXX : not implemented */
2458 spr_register(env, SPR_MPC_IC_DAT, "IC_DAT",
2459 SPR_NOACCESS, SPR_NOACCESS,
2460 &spr_read_generic, &spr_write_generic,
2461 0x00000000);
2462 /* XXX : not implemented */
2463 spr_register(env, SPR_MPC_DC_CST, "DC_CST",
2464 SPR_NOACCESS, SPR_NOACCESS,
2465 &spr_read_generic, &spr_write_generic,
2466 0x00000000);
2467 /* XXX : not implemented */
2468 spr_register(env, SPR_MPC_DC_ADR, "DC_ADR",
2469 SPR_NOACCESS, SPR_NOACCESS,
2470 &spr_read_generic, &spr_write_generic,
2471 0x00000000);
2472 /* XXX : not implemented */
2473 spr_register(env, SPR_MPC_DC_DAT, "DC_DAT",
2474 SPR_NOACCESS, SPR_NOACCESS,
2475 &spr_read_generic, &spr_write_generic,
2476 0x00000000);
2477 /* XXX : not implemented */
2478 spr_register(env, SPR_MPC_MI_CTR, "MI_CTR",
2479 SPR_NOACCESS, SPR_NOACCESS,
2480 &spr_read_generic, &spr_write_generic,
2481 0x00000000);
2482 /* XXX : not implemented */
2483 spr_register(env, SPR_MPC_MI_AP, "MI_AP",
2484 SPR_NOACCESS, SPR_NOACCESS,
2485 &spr_read_generic, &spr_write_generic,
2486 0x00000000);
2487 /* XXX : not implemented */
2488 spr_register(env, SPR_MPC_MI_EPN, "MI_EPN",
2489 SPR_NOACCESS, SPR_NOACCESS,
2490 &spr_read_generic, &spr_write_generic,
2491 0x00000000);
2492 /* XXX : not implemented */
2493 spr_register(env, SPR_MPC_MI_TWC, "MI_TWC",
2494 SPR_NOACCESS, SPR_NOACCESS,
2495 &spr_read_generic, &spr_write_generic,
2496 0x00000000);
2497 /* XXX : not implemented */
2498 spr_register(env, SPR_MPC_MI_RPN, "MI_RPN",
2499 SPR_NOACCESS, SPR_NOACCESS,
2500 &spr_read_generic, &spr_write_generic,
2501 0x00000000);
2502 /* XXX : not implemented */
2503 spr_register(env, SPR_MPC_MI_DBCAM, "MI_DBCAM",
2504 SPR_NOACCESS, SPR_NOACCESS,
2505 &spr_read_generic, &spr_write_generic,
2506 0x00000000);
2507 /* XXX : not implemented */
2508 spr_register(env, SPR_MPC_MI_DBRAM0, "MI_DBRAM0",
2509 SPR_NOACCESS, SPR_NOACCESS,
2510 &spr_read_generic, &spr_write_generic,
2511 0x00000000);
2512 /* XXX : not implemented */
2513 spr_register(env, SPR_MPC_MI_DBRAM1, "MI_DBRAM1",
2514 SPR_NOACCESS, SPR_NOACCESS,
2515 &spr_read_generic, &spr_write_generic,
2516 0x00000000);
2517 /* XXX : not implemented */
2518 spr_register(env, SPR_MPC_MD_CTR, "MD_CTR",
2519 SPR_NOACCESS, SPR_NOACCESS,
2520 &spr_read_generic, &spr_write_generic,
2521 0x00000000);
2522 /* XXX : not implemented */
2523 spr_register(env, SPR_MPC_MD_CASID, "MD_CASID",
2524 SPR_NOACCESS, SPR_NOACCESS,
2525 &spr_read_generic, &spr_write_generic,
2526 0x00000000);
2527 /* XXX : not implemented */
2528 spr_register(env, SPR_MPC_MD_AP, "MD_AP",
2529 SPR_NOACCESS, SPR_NOACCESS,
2530 &spr_read_generic, &spr_write_generic,
2531 0x00000000);
2532 /* XXX : not implemented */
2533 spr_register(env, SPR_MPC_MD_EPN, "MD_EPN",
2534 SPR_NOACCESS, SPR_NOACCESS,
2535 &spr_read_generic, &spr_write_generic,
2536 0x00000000);
2537 /* XXX : not implemented */
2538 spr_register(env, SPR_MPC_MD_TWB, "MD_TWB",
2539 SPR_NOACCESS, SPR_NOACCESS,
2540 &spr_read_generic, &spr_write_generic,
2541 0x00000000);
2542 /* XXX : not implemented */
2543 spr_register(env, SPR_MPC_MD_TWC, "MD_TWC",
2544 SPR_NOACCESS, SPR_NOACCESS,
2545 &spr_read_generic, &spr_write_generic,
2546 0x00000000);
2547 /* XXX : not implemented */
2548 spr_register(env, SPR_MPC_MD_RPN, "MD_RPN",
2549 SPR_NOACCESS, SPR_NOACCESS,
2550 &spr_read_generic, &spr_write_generic,
2551 0x00000000);
2552 /* XXX : not implemented */
2553 spr_register(env, SPR_MPC_MD_TW, "MD_TW",
2554 SPR_NOACCESS, SPR_NOACCESS,
2555 &spr_read_generic, &spr_write_generic,
2556 0x00000000);
2557 /* XXX : not implemented */
2558 spr_register(env, SPR_MPC_MD_DBCAM, "MD_DBCAM",
2559 SPR_NOACCESS, SPR_NOACCESS,
2560 &spr_read_generic, &spr_write_generic,
2561 0x00000000);
2562 /* XXX : not implemented */
2563 spr_register(env, SPR_MPC_MD_DBRAM0, "MD_DBRAM0",
2564 SPR_NOACCESS, SPR_NOACCESS,
2565 &spr_read_generic, &spr_write_generic,
2566 0x00000000);
2567 /* XXX : not implemented */
2568 spr_register(env, SPR_MPC_MD_DBRAM1, "MD_DBRAM1",
2569 SPR_NOACCESS, SPR_NOACCESS,
2570 &spr_read_generic, &spr_write_generic,
2571 0x00000000);
2572 }
2573
2574 // XXX: TODO
2575 /*
2576 * AMR => SPR 29 (Power 2.04)
2577 * CTRL => SPR 136 (Power 2.04)
2578 * CTRL => SPR 152 (Power 2.04)
2579 * SCOMC => SPR 276 (64 bits ?)
2580 * SCOMD => SPR 277 (64 bits ?)
2581 * TBU40 => SPR 286 (Power 2.04 hypv)
2582 * HSPRG0 => SPR 304 (Power 2.04 hypv)
2583 * HSPRG1 => SPR 305 (Power 2.04 hypv)
2584 * HDSISR => SPR 306 (Power 2.04 hypv)
2585 * HDAR => SPR 307 (Power 2.04 hypv)
2586 * PURR => SPR 309 (Power 2.04 hypv)
2587 * HDEC => SPR 310 (Power 2.04 hypv)
2588 * HIOR => SPR 311 (hypv)
2589 * RMOR => SPR 312 (970)
2590 * HRMOR => SPR 313 (Power 2.04 hypv)
2591 * HSRR0 => SPR 314 (Power 2.04 hypv)
2592 * HSRR1 => SPR 315 (Power 2.04 hypv)
2593 * LPIDR => SPR 317 (970)
2594 * EPR => SPR 702 (Power 2.04 emb)
2595 * perf => 768-783 (Power 2.04)
2596 * perf => 784-799 (Power 2.04)
2597 * PPR => SPR 896 (Power 2.04)
2598 * EPLC => SPR 947 (Power 2.04 emb)
2599 * EPSC => SPR 948 (Power 2.04 emb)
2600 * DABRX => 1015 (Power 2.04 hypv)
2601 * FPECR => SPR 1022 (?)
2602 * ... and more (thermal management, performance counters, ...)
2603 */
2604
2605 /*****************************************************************************/
2606 /* Exception vectors models */
2607 static void init_excp_4xx_real (CPUPPCState *env)
2608 {
2609 #if !defined(CONFIG_USER_ONLY)
2610 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2611 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2612 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2613 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2614 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2615 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2616 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2617 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2618 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2619 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2620 env->ivor_mask = 0x0000FFF0UL;
2621 env->ivpr_mask = 0xFFFF0000UL;
2622 /* Hardware reset vector */
2623 env->hreset_vector = 0xFFFFFFFCUL;
2624 #endif
2625 }
2626
2627 static void init_excp_4xx_softmmu (CPUPPCState *env)
2628 {
2629 #if !defined(CONFIG_USER_ONLY)
2630 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000100;
2631 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2632 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2633 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2634 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2635 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2636 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2637 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2638 env->excp_vectors[POWERPC_EXCP_PIT] = 0x00001000;
2639 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00001010;
2640 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001020;
2641 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001100;
2642 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001200;
2643 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00002000;
2644 env->ivor_mask = 0x0000FFF0UL;
2645 env->ivpr_mask = 0xFFFF0000UL;
2646 /* Hardware reset vector */
2647 env->hreset_vector = 0xFFFFFFFCUL;
2648 #endif
2649 }
2650
2651 static void init_excp_MPC5xx (CPUPPCState *env)
2652 {
2653 #if !defined(CONFIG_USER_ONLY)
2654 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2655 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2656 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2657 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2658 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2659 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2660 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2661 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2662 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2663 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2664 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2665 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2666 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2667 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2668 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2669 env->ivor_mask = 0x0000FFF0UL;
2670 env->ivpr_mask = 0xFFFF0000UL;
2671 /* Hardware reset vector */
2672 env->hreset_vector = 0x00000100UL;
2673 #endif
2674 }
2675
2676 static void init_excp_MPC8xx (CPUPPCState *env)
2677 {
2678 #if !defined(CONFIG_USER_ONLY)
2679 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2680 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2681 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2682 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2683 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2684 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2685 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2686 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000900;
2687 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2688 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2689 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2690 env->excp_vectors[POWERPC_EXCP_FPA] = 0x00000E00;
2691 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001000;
2692 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00001100;
2693 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00001200;
2694 env->excp_vectors[POWERPC_EXCP_ITLBE] = 0x00001300;
2695 env->excp_vectors[POWERPC_EXCP_DTLBE] = 0x00001400;
2696 env->excp_vectors[POWERPC_EXCP_DABR] = 0x00001C00;
2697 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001C00;
2698 env->excp_vectors[POWERPC_EXCP_MEXTBR] = 0x00001E00;
2699 env->excp_vectors[POWERPC_EXCP_NMEXTBR] = 0x00001F00;
2700 env->ivor_mask = 0x0000FFF0UL;
2701 env->ivpr_mask = 0xFFFF0000UL;
2702 /* Hardware reset vector */
2703 env->hreset_vector = 0x00000100UL;
2704 #endif
2705 }
2706
2707 static void init_excp_G2 (CPUPPCState *env)
2708 {
2709 #if !defined(CONFIG_USER_ONLY)
2710 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2711 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2712 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2713 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2714 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2715 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2716 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2717 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2718 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2719 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000A00;
2720 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2721 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2722 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2723 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2724 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2725 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2726 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2727 /* Hardware reset vector */
2728 env->hreset_vector = 0x00000100UL;
2729 #endif
2730 }
2731
2732 static void init_excp_e200(CPUPPCState *env, target_ulong ivpr_mask)
2733 {
2734 #if !defined(CONFIG_USER_ONLY)
2735 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000FFC;
2736 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2737 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2738 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2739 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2740 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2741 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2742 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2743 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2744 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2745 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2746 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2747 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2748 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2749 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2750 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2751 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2752 env->excp_vectors[POWERPC_EXCP_SPEU] = 0x00000000;
2753 env->excp_vectors[POWERPC_EXCP_EFPDI] = 0x00000000;
2754 env->excp_vectors[POWERPC_EXCP_EFPRI] = 0x00000000;
2755 env->ivor_mask = 0x0000FFF7UL;
2756 env->ivpr_mask = ivpr_mask;
2757 /* Hardware reset vector */
2758 env->hreset_vector = 0xFFFFFFFCUL;
2759 #endif
2760 }
2761
2762 static void init_excp_BookE (CPUPPCState *env)
2763 {
2764 #if !defined(CONFIG_USER_ONLY)
2765 env->excp_vectors[POWERPC_EXCP_CRITICAL] = 0x00000000;
2766 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000000;
2767 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000000;
2768 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000000;
2769 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000000;
2770 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000000;
2771 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000000;
2772 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000000;
2773 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000000;
2774 env->excp_vectors[POWERPC_EXCP_APU] = 0x00000000;
2775 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000000;
2776 env->excp_vectors[POWERPC_EXCP_FIT] = 0x00000000;
2777 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00000000;
2778 env->excp_vectors[POWERPC_EXCP_DTLB] = 0x00000000;
2779 env->excp_vectors[POWERPC_EXCP_ITLB] = 0x00000000;
2780 env->excp_vectors[POWERPC_EXCP_DEBUG] = 0x00000000;
2781 env->ivor_mask = 0x0000FFE0UL;
2782 env->ivpr_mask = 0xFFFF0000UL;
2783 /* Hardware reset vector */
2784 env->hreset_vector = 0xFFFFFFFCUL;
2785 #endif
2786 }
2787
2788 static void init_excp_601 (CPUPPCState *env)
2789 {
2790 #if !defined(CONFIG_USER_ONLY)
2791 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2792 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2793 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2794 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2795 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2796 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2797 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2798 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2799 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2800 env->excp_vectors[POWERPC_EXCP_IO] = 0x00000A00;
2801 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2802 env->excp_vectors[POWERPC_EXCP_RUNM] = 0x00002000;
2803 /* Hardware reset vector */
2804 env->hreset_vector = 0x00000100UL;
2805 #endif
2806 }
2807
2808 static void init_excp_602 (CPUPPCState *env)
2809 {
2810 #if !defined(CONFIG_USER_ONLY)
2811 /* XXX: exception prefix has a special behavior on 602 */
2812 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2813 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2814 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2815 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2816 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2817 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2818 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2819 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2820 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2821 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2822 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2823 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2824 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2825 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2826 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2827 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2828 env->excp_vectors[POWERPC_EXCP_WDT] = 0x00001500;
2829 env->excp_vectors[POWERPC_EXCP_EMUL] = 0x00001600;
2830 /* Hardware reset vector */
2831 env->hreset_vector = 0x00000100UL;
2832 #endif
2833 }
2834
2835 static void init_excp_603 (CPUPPCState *env)
2836 {
2837 #if !defined(CONFIG_USER_ONLY)
2838 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2839 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2840 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2841 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2842 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2843 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2844 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2845 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2846 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2847 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2848 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2849 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2850 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2851 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2852 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2853 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2854 /* Hardware reset vector */
2855 env->hreset_vector = 0x00000100UL;
2856 #endif
2857 }
2858
2859 static void init_excp_604 (CPUPPCState *env)
2860 {
2861 #if !defined(CONFIG_USER_ONLY)
2862 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2863 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2864 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2865 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2866 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2867 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2868 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2869 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2870 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2871 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2872 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2873 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2874 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2875 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2876 /* Hardware reset vector */
2877 env->hreset_vector = 0x00000100UL;
2878 #endif
2879 }
2880
2881 static void init_excp_7x0 (CPUPPCState *env)
2882 {
2883 #if !defined(CONFIG_USER_ONLY)
2884 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2885 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2886 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2887 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2888 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2889 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2890 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2891 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2892 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2893 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2894 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2895 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2896 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2897 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2898 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2899 /* Hardware reset vector */
2900 env->hreset_vector = 0x00000100UL;
2901 #endif
2902 }
2903
2904 static void init_excp_750cl (CPUPPCState *env)
2905 {
2906 #if !defined(CONFIG_USER_ONLY)
2907 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2908 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2909 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2910 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2911 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2912 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2913 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2914 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2915 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2916 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2917 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2918 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2919 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2920 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2921 /* Hardware reset vector */
2922 env->hreset_vector = 0x00000100UL;
2923 #endif
2924 }
2925
2926 static void init_excp_750cx (CPUPPCState *env)
2927 {
2928 #if !defined(CONFIG_USER_ONLY)
2929 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2930 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2931 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2932 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2933 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2934 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2935 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2936 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2937 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2938 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2939 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2940 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2941 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2942 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2943 /* Hardware reset vector */
2944 env->hreset_vector = 0x00000100UL;
2945 #endif
2946 }
2947
2948 /* XXX: Check if this is correct */
2949 static void init_excp_7x5 (CPUPPCState *env)
2950 {
2951 #if !defined(CONFIG_USER_ONLY)
2952 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2953 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2954 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2955 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2956 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2957 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2958 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2959 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2960 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2961 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2962 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2963 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2964 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
2965 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
2966 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
2967 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2968 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2969 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2970 /* Hardware reset vector */
2971 env->hreset_vector = 0x00000100UL;
2972 #endif
2973 }
2974
2975 static void init_excp_7400 (CPUPPCState *env)
2976 {
2977 #if !defined(CONFIG_USER_ONLY)
2978 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
2979 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
2980 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
2981 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
2982 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
2983 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
2984 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
2985 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
2986 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
2987 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
2988 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
2989 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
2990 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
2991 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
2992 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
2993 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
2994 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001700;
2995 /* Hardware reset vector */
2996 env->hreset_vector = 0x00000100UL;
2997 #endif
2998 }
2999
3000 static void init_excp_7450 (CPUPPCState *env)
3001 {
3002 #if !defined(CONFIG_USER_ONLY)
3003 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3004 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3005 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3006 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3007 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3008 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3009 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3010 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3011 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3012 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3013 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3014 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3015 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3016 env->excp_vectors[POWERPC_EXCP_IFTLB] = 0x00001000;
3017 env->excp_vectors[POWERPC_EXCP_DLTLB] = 0x00001100;
3018 env->excp_vectors[POWERPC_EXCP_DSTLB] = 0x00001200;
3019 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3020 env->excp_vectors[POWERPC_EXCP_SMI] = 0x00001400;
3021 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001600;
3022 /* Hardware reset vector */
3023 env->hreset_vector = 0x00000100UL;
3024 #endif
3025 }
3026
3027 #if defined (TARGET_PPC64)
3028 static void init_excp_970 (CPUPPCState *env)
3029 {
3030 #if !defined(CONFIG_USER_ONLY)
3031 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3032 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3033 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3034 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3035 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3036 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3037 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3038 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3039 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3040 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3041 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3042 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3043 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3044 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3045 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3046 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3047 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3048 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3049 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3050 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3051 /* Hardware reset vector */
3052 env->hreset_vector = 0x0000000000000100ULL;
3053 #endif
3054 }
3055
3056 static void init_excp_POWER7 (CPUPPCState *env)
3057 {
3058 #if !defined(CONFIG_USER_ONLY)
3059 env->excp_vectors[POWERPC_EXCP_RESET] = 0x00000100;
3060 env->excp_vectors[POWERPC_EXCP_MCHECK] = 0x00000200;
3061 env->excp_vectors[POWERPC_EXCP_DSI] = 0x00000300;
3062 env->excp_vectors[POWERPC_EXCP_DSEG] = 0x00000380;
3063 env->excp_vectors[POWERPC_EXCP_ISI] = 0x00000400;
3064 env->excp_vectors[POWERPC_EXCP_ISEG] = 0x00000480;
3065 env->excp_vectors[POWERPC_EXCP_EXTERNAL] = 0x00000500;
3066 env->excp_vectors[POWERPC_EXCP_ALIGN] = 0x00000600;
3067 env->excp_vectors[POWERPC_EXCP_PROGRAM] = 0x00000700;
3068 env->excp_vectors[POWERPC_EXCP_FPU] = 0x00000800;
3069 env->excp_vectors[POWERPC_EXCP_DECR] = 0x00000900;
3070 env->excp_vectors[POWERPC_EXCP_HDECR] = 0x00000980;
3071 env->excp_vectors[POWERPC_EXCP_SYSCALL] = 0x00000C00;
3072 env->excp_vectors[POWERPC_EXCP_TRACE] = 0x00000D00;
3073 env->excp_vectors[POWERPC_EXCP_PERFM] = 0x00000F00;
3074 env->excp_vectors[POWERPC_EXCP_VPU] = 0x00000F20;
3075 env->excp_vectors[POWERPC_EXCP_VSXU] = 0x00000F40;
3076 env->excp_vectors[POWERPC_EXCP_IABR] = 0x00001300;
3077 env->excp_vectors[POWERPC_EXCP_MAINT] = 0x00001600;
3078 env->excp_vectors[POWERPC_EXCP_VPUA] = 0x00001700;
3079 env->excp_vectors[POWERPC_EXCP_THERM] = 0x00001800;
3080 /* Hardware reset vector */
3081 env->hreset_vector = 0x0000000000000100ULL;
3082 #endif
3083 }
3084 #endif
3085
3086 /*****************************************************************************/
3087 /* Power management enable checks */
3088 static int check_pow_none (CPUPPCState *env)
3089 {
3090 return 0;
3091 }
3092
3093 static int check_pow_nocheck (CPUPPCState *env)
3094 {
3095 return 1;
3096 }
3097
3098 static int check_pow_hid0 (CPUPPCState *env)
3099 {
3100 if (env->spr[SPR_HID0] & 0x00E00000)
3101 return 1;
3102
3103 return 0;
3104 }
3105
3106 static int check_pow_hid0_74xx (CPUPPCState *env)
3107 {
3108 if (env->spr[SPR_HID0] & 0x00600000)
3109 return 1;
3110
3111 return 0;
3112 }
3113
3114 static bool ppc_cpu_interrupts_big_endian_always(PowerPCCPU *cpu)
3115 {
3116 return true;
3117 }
3118
3119 #ifdef TARGET_PPC64
3120 static bool ppc_cpu_interrupts_big_endian_lpcr(PowerPCCPU *cpu)
3121 {
3122 return !(cpu->env.spr[SPR_LPCR] & LPCR_ILE);
3123 }
3124 #endif
3125
3126 /*****************************************************************************/
3127 /* PowerPC implementations definitions */
3128
3129 #define POWERPC_FAMILY(_name) \
3130 static void \
3131 glue(glue(ppc_, _name), _cpu_family_class_init)(ObjectClass *, void *); \
3132 \
3133 static const TypeInfo \
3134 glue(glue(ppc_, _name), _cpu_family_type_info) = { \
3135 .name = stringify(_name) "-family-" TYPE_POWERPC_CPU, \
3136 .parent = TYPE_POWERPC_CPU, \
3137 .abstract = true, \
3138 .class_init = glue(glue(ppc_, _name), _cpu_family_class_init), \
3139 }; \
3140 \
3141 static void glue(glue(ppc_, _name), _cpu_family_register_types)(void) \
3142 { \
3143 type_register_static( \
3144 &glue(glue(ppc_, _name), _cpu_family_type_info)); \
3145 } \
3146 \
3147 type_init(glue(glue(ppc_, _name), _cpu_family_register_types)) \
3148 \
3149 static void glue(glue(ppc_, _name), _cpu_family_class_init)
3150
3151 static void init_proc_401 (CPUPPCState *env)
3152 {
3153 gen_spr_40x(env);
3154 gen_spr_401_403(env);
3155 gen_spr_401(env);
3156 init_excp_4xx_real(env);
3157 env->dcache_line_size = 32;
3158 env->icache_line_size = 32;
3159 /* Allocate hardware IRQ controller */
3160 ppc40x_irq_init(env);
3161
3162 SET_FIT_PERIOD(12, 16, 20, 24);
3163 SET_WDT_PERIOD(16, 20, 24, 28);
3164 }
3165
3166 POWERPC_FAMILY(401)(ObjectClass *oc, void *data)
3167 {
3168 DeviceClass *dc = DEVICE_CLASS(oc);
3169 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3170
3171 dc->desc = "PowerPC 401";
3172 pcc->init_proc = init_proc_401;
3173 pcc->check_pow = check_pow_nocheck;
3174 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3175 PPC_WRTEE | PPC_DCR |
3176 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3177 PPC_CACHE_DCBZ |
3178 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3179 PPC_4xx_COMMON | PPC_40x_EXCP;
3180 pcc->msr_mask = (1ull << MSR_KEY) |
3181 (1ull << MSR_POW) |
3182 (1ull << MSR_CE) |
3183 (1ull << MSR_ILE) |
3184 (1ull << MSR_EE) |
3185 (1ull << MSR_PR) |
3186 (1ull << MSR_ME) |
3187 (1ull << MSR_DE) |
3188 (1ull << MSR_LE);
3189 pcc->mmu_model = POWERPC_MMU_REAL;
3190 pcc->excp_model = POWERPC_EXCP_40x;
3191 pcc->bus_model = PPC_FLAGS_INPUT_401;
3192 pcc->bfd_mach = bfd_mach_ppc_403;
3193 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3194 POWERPC_FLAG_BUS_CLK;
3195 }
3196
3197 static void init_proc_401x2 (CPUPPCState *env)
3198 {
3199 gen_spr_40x(env);
3200 gen_spr_401_403(env);
3201 gen_spr_401x2(env);
3202 gen_spr_compress(env);
3203 /* Memory management */
3204 #if !defined(CONFIG_USER_ONLY)
3205 env->nb_tlb = 64;
3206 env->nb_ways = 1;
3207 env->id_tlbs = 0;
3208 env->tlb_type = TLB_EMB;
3209 #endif
3210 init_excp_4xx_softmmu(env);
3211 env->dcache_line_size = 32;
3212 env->icache_line_size = 32;
3213 /* Allocate hardware IRQ controller */
3214 ppc40x_irq_init(env);
3215
3216 SET_FIT_PERIOD(12, 16, 20, 24);
3217 SET_WDT_PERIOD(16, 20, 24, 28);
3218 }
3219
3220 POWERPC_FAMILY(401x2)(ObjectClass *oc, void *data)
3221 {
3222 DeviceClass *dc = DEVICE_CLASS(oc);
3223 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3224
3225 dc->desc = "PowerPC 401x2";
3226 pcc->init_proc = init_proc_401x2;
3227 pcc->check_pow = check_pow_nocheck;
3228 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3229 PPC_DCR | PPC_WRTEE |
3230 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3231 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3232 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3233 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3234 PPC_4xx_COMMON | PPC_40x_EXCP;
3235 pcc->msr_mask = (1ull << 20) |
3236 (1ull << MSR_KEY) |
3237 (1ull << MSR_POW) |
3238 (1ull << MSR_CE) |
3239 (1ull << MSR_ILE) |
3240 (1ull << MSR_EE) |
3241 (1ull << MSR_PR) |
3242 (1ull << MSR_ME) |
3243 (1ull << MSR_DE) |
3244 (1ull << MSR_IR) |
3245 (1ull << MSR_DR) |
3246 (1ull << MSR_LE);
3247 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3248 pcc->excp_model = POWERPC_EXCP_40x;
3249 pcc->bus_model = PPC_FLAGS_INPUT_401;
3250 pcc->bfd_mach = bfd_mach_ppc_403;
3251 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3252 POWERPC_FLAG_BUS_CLK;
3253 }
3254
3255 static void init_proc_401x3 (CPUPPCState *env)
3256 {
3257 gen_spr_40x(env);
3258 gen_spr_401_403(env);
3259 gen_spr_401(env);
3260 gen_spr_401x2(env);
3261 gen_spr_compress(env);
3262 init_excp_4xx_softmmu(env);
3263 env->dcache_line_size = 32;
3264 env->icache_line_size = 32;
3265 /* Allocate hardware IRQ controller */
3266 ppc40x_irq_init(env);
3267
3268 SET_FIT_PERIOD(12, 16, 20, 24);
3269 SET_WDT_PERIOD(16, 20, 24, 28);
3270 }
3271
3272 POWERPC_FAMILY(401x3)(ObjectClass *oc, void *data)
3273 {
3274 DeviceClass *dc = DEVICE_CLASS(oc);
3275 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3276
3277 dc->desc = "PowerPC 401x3";
3278 pcc->init_proc = init_proc_401x3;
3279 pcc->check_pow = check_pow_nocheck;
3280 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3281 PPC_DCR | PPC_WRTEE |
3282 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3283 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3284 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3285 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3286 PPC_4xx_COMMON | PPC_40x_EXCP;
3287 pcc->msr_mask = (1ull << 20) |
3288 (1ull << MSR_KEY) |
3289 (1ull << MSR_POW) |
3290 (1ull << MSR_CE) |
3291 (1ull << MSR_ILE) |
3292 (1ull << MSR_EE) |
3293 (1ull << MSR_PR) |
3294 (1ull << MSR_ME) |
3295 (1ull << MSR_DWE) |
3296 (1ull << MSR_DE) |
3297 (1ull << MSR_IR) |
3298 (1ull << MSR_DR) |
3299 (1ull << MSR_LE);
3300 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3301 pcc->excp_model = POWERPC_EXCP_40x;
3302 pcc->bus_model = PPC_FLAGS_INPUT_401;
3303 pcc->bfd_mach = bfd_mach_ppc_403;
3304 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3305 POWERPC_FLAG_BUS_CLK;
3306 }
3307
3308 static void init_proc_IOP480 (CPUPPCState *env)
3309 {
3310 gen_spr_40x(env);
3311 gen_spr_401_403(env);
3312 gen_spr_401x2(env);
3313 gen_spr_compress(env);
3314 /* Memory management */
3315 #if !defined(CONFIG_USER_ONLY)
3316 env->nb_tlb = 64;
3317 env->nb_ways = 1;
3318 env->id_tlbs = 0;
3319 env->tlb_type = TLB_EMB;
3320 #endif
3321 init_excp_4xx_softmmu(env);
3322 env->dcache_line_size = 32;
3323 env->icache_line_size = 32;
3324 /* Allocate hardware IRQ controller */
3325 ppc40x_irq_init(env);
3326
3327 SET_FIT_PERIOD(8, 12, 16, 20);
3328 SET_WDT_PERIOD(16, 20, 24, 28);
3329 }
3330
3331 POWERPC_FAMILY(IOP480)(ObjectClass *oc, void *data)
3332 {
3333 DeviceClass *dc = DEVICE_CLASS(oc);
3334 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3335
3336 dc->desc = "IOP480";
3337 pcc->init_proc = init_proc_IOP480;
3338 pcc->check_pow = check_pow_nocheck;
3339 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3340 PPC_DCR | PPC_WRTEE |
3341 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3342 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3343 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3344 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3345 PPC_4xx_COMMON | PPC_40x_EXCP;
3346 pcc->msr_mask = (1ull << 20) |
3347 (1ull << MSR_KEY) |
3348 (1ull << MSR_POW) |
3349 (1ull << MSR_CE) |
3350 (1ull << MSR_ILE) |
3351 (1ull << MSR_EE) |
3352 (1ull << MSR_PR) |
3353 (1ull << MSR_ME) |
3354 (1ull << MSR_DE) |
3355 (1ull << MSR_IR) |
3356 (1ull << MSR_DR) |
3357 (1ull << MSR_LE);
3358 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3359 pcc->excp_model = POWERPC_EXCP_40x;
3360 pcc->bus_model = PPC_FLAGS_INPUT_401;
3361 pcc->bfd_mach = bfd_mach_ppc_403;
3362 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
3363 POWERPC_FLAG_BUS_CLK;
3364 }
3365
3366 static void init_proc_403 (CPUPPCState *env)
3367 {
3368 gen_spr_40x(env);
3369 gen_spr_401_403(env);
3370 gen_spr_403(env);
3371 gen_spr_403_real(env);
3372 init_excp_4xx_real(env);
3373 env->dcache_line_size = 32;
3374 env->icache_line_size = 32;
3375 /* Allocate hardware IRQ controller */
3376 ppc40x_irq_init(env);
3377
3378 SET_FIT_PERIOD(8, 12, 16, 20);
3379 SET_WDT_PERIOD(16, 20, 24, 28);
3380 }
3381
3382 POWERPC_FAMILY(403)(ObjectClass *oc, void *data)
3383 {
3384 DeviceClass *dc = DEVICE_CLASS(oc);
3385 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3386
3387 dc->desc = "PowerPC 403";
3388 pcc->init_proc = init_proc_403;
3389 pcc->check_pow = check_pow_nocheck;
3390 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3391 PPC_DCR | PPC_WRTEE |
3392 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3393 PPC_CACHE_DCBZ |
3394 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3395 PPC_4xx_COMMON | PPC_40x_EXCP;
3396 pcc->msr_mask = (1ull << MSR_POW) |
3397 (1ull << MSR_CE) |
3398 (1ull << MSR_ILE) |
3399 (1ull << MSR_EE) |
3400 (1ull << MSR_PR) |
3401 (1ull << MSR_ME) |
3402 (1ull << MSR_PE) |
3403 (1ull << MSR_PX) |
3404 (1ull << MSR_LE);
3405 pcc->mmu_model = POWERPC_MMU_REAL;
3406 pcc->excp_model = POWERPC_EXCP_40x;
3407 pcc->bus_model = PPC_FLAGS_INPUT_401;
3408 pcc->bfd_mach = bfd_mach_ppc_403;
3409 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3410 POWERPC_FLAG_BUS_CLK;
3411 }
3412
3413 static void init_proc_403GCX (CPUPPCState *env)
3414 {
3415 gen_spr_40x(env);
3416 gen_spr_401_403(env);
3417 gen_spr_403(env);
3418 gen_spr_403_real(env);
3419 gen_spr_403_mmu(env);
3420 /* Bus access control */
3421 /* not emulated, as QEMU never does speculative access */
3422 spr_register(env, SPR_40x_SGR, "SGR",
3423 SPR_NOACCESS, SPR_NOACCESS,
3424 &spr_read_generic, &spr_write_generic,
3425 0xFFFFFFFF);
3426 /* not emulated, as QEMU do not emulate caches */
3427 spr_register(env, SPR_40x_DCWR, "DCWR",
3428 SPR_NOACCESS, SPR_NOACCESS,
3429 &spr_read_generic, &spr_write_generic,
3430 0x00000000);
3431 /* Memory management */
3432 #if !defined(CONFIG_USER_ONLY)
3433 env->nb_tlb = 64;
3434 env->nb_ways = 1;
3435 env->id_tlbs = 0;
3436 env->tlb_type = TLB_EMB;
3437 #endif
3438 init_excp_4xx_softmmu(env);
3439 env->dcache_line_size = 32;
3440 env->icache_line_size = 32;
3441 /* Allocate hardware IRQ controller */
3442 ppc40x_irq_init(env);
3443
3444 SET_FIT_PERIOD(8, 12, 16, 20);
3445 SET_WDT_PERIOD(16, 20, 24, 28);
3446 }
3447
3448 POWERPC_FAMILY(403GCX)(ObjectClass *oc, void *data)
3449 {
3450 DeviceClass *dc = DEVICE_CLASS(oc);
3451 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3452
3453 dc->desc = "PowerPC 403 GCX";
3454 pcc->init_proc = init_proc_403GCX;
3455 pcc->check_pow = check_pow_nocheck;
3456 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3457 PPC_DCR | PPC_WRTEE |
3458 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3459 PPC_CACHE_DCBZ |
3460 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3461 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3462 PPC_4xx_COMMON | PPC_40x_EXCP;
3463 pcc->msr_mask = (1ull << MSR_POW) |
3464 (1ull << MSR_CE) |
3465 (1ull << MSR_ILE) |
3466 (1ull << MSR_EE) |
3467 (1ull << MSR_PR) |
3468 (1ull << MSR_ME) |
3469 (1ull << MSR_PE) |
3470 (1ull << MSR_PX) |
3471 (1ull << MSR_LE);
3472 pcc->mmu_model = POWERPC_MMU_SOFT_4xx_Z;
3473 pcc->excp_model = POWERPC_EXCP_40x;
3474 pcc->bus_model = PPC_FLAGS_INPUT_401;
3475 pcc->bfd_mach = bfd_mach_ppc_403;
3476 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_PX |
3477 POWERPC_FLAG_BUS_CLK;
3478 }
3479
3480 static void init_proc_405 (CPUPPCState *env)
3481 {
3482 /* Time base */
3483 gen_tbl(env);
3484 gen_spr_40x(env);
3485 gen_spr_405(env);
3486 /* Bus access control */
3487 /* not emulated, as QEMU never does speculative access */
3488 spr_register(env, SPR_40x_SGR, "SGR",
3489 SPR_NOACCESS, SPR_NOACCESS,
3490 &spr_read_generic, &spr_write_generic,
3491 0xFFFFFFFF);
3492 /* not emulated, as QEMU do not emulate caches */
3493 spr_register(env, SPR_40x_DCWR, "DCWR",
3494 SPR_NOACCESS, SPR_NOACCESS,
3495 &spr_read_generic, &spr_write_generic,
3496 0x00000000);
3497 /* Memory management */
3498 #if !defined(CONFIG_USER_ONLY)
3499 env->nb_tlb = 64;
3500 env->nb_ways = 1;
3501 env->id_tlbs = 0;
3502 env->tlb_type = TLB_EMB;
3503 #endif
3504 init_excp_4xx_softmmu(env);
3505 env->dcache_line_size = 32;
3506 env->icache_line_size = 32;
3507 /* Allocate hardware IRQ controller */
3508 ppc40x_irq_init(env);
3509
3510 SET_FIT_PERIOD(8, 12, 16, 20);
3511 SET_WDT_PERIOD(16, 20, 24, 28);
3512 }
3513
3514 POWERPC_FAMILY(405)(ObjectClass *oc, void *data)
3515 {
3516 DeviceClass *dc = DEVICE_CLASS(oc);
3517 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3518
3519 dc->desc = "PowerPC 405";
3520 pcc->init_proc = init_proc_405;
3521 pcc->check_pow = check_pow_nocheck;
3522 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
3523 PPC_DCR | PPC_WRTEE |
3524 PPC_CACHE | PPC_CACHE_ICBI | PPC_40x_ICBT |
3525 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3526 PPC_MEM_SYNC | PPC_MEM_EIEIO |
3527 PPC_40x_TLB | PPC_MEM_TLBIA | PPC_MEM_TLBSYNC |
3528 PPC_4xx_COMMON | PPC_405_MAC | PPC_40x_EXCP;
3529 pcc->msr_mask = (1ull << MSR_POW) |
3530 (1ull << MSR_CE) |
3531 (1ull << MSR_EE) |
3532 (1ull << MSR_PR) |
3533 (1ull << MSR_FP) |
3534 (1ull << MSR_DWE) |
3535 (1ull << MSR_DE) |
3536 (1ull << MSR_IR) |
3537 (1ull << MSR_DR);
3538 pcc->mmu_model = POWERPC_MMU_SOFT_4xx;
3539 pcc->excp_model = POWERPC_EXCP_40x;
3540 pcc->bus_model = PPC_FLAGS_INPUT_405;
3541 pcc->bfd_mach = bfd_mach_ppc_403;
3542 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3543 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3544 }
3545
3546 static void init_proc_440EP (CPUPPCState *env)
3547 {
3548 /* Time base */
3549 gen_tbl(env);
3550 gen_spr_BookE(env, 0x000000000000FFFFULL);
3551 gen_spr_440(env);
3552 gen_spr_usprgh(env);
3553 /* Processor identification */
3554 spr_register(env, SPR_BOOKE_PIR, "PIR",
3555 SPR_NOACCESS, SPR_NOACCESS,
3556 &spr_read_generic, &spr_write_pir,
3557 0x00000000);
3558 /* XXX : not implemented */
3559 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3560 SPR_NOACCESS, SPR_NOACCESS,
3561 &spr_read_generic, &spr_write_generic,
3562 0x00000000);
3563 /* XXX : not implemented */
3564 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3565 SPR_NOACCESS, SPR_NOACCESS,
3566 &spr_read_generic, &spr_write_generic,
3567 0x00000000);
3568 /* XXX : not implemented */
3569 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3570 SPR_NOACCESS, SPR_NOACCESS,
3571 &spr_read_generic, &spr_write_generic,
3572 0x00000000);
3573 /* XXX : not implemented */
3574 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3575 SPR_NOACCESS, SPR_NOACCESS,
3576 &spr_read_generic, &spr_write_generic,
3577 0x00000000);
3578 /* XXX : not implemented */
3579 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3580 SPR_NOACCESS, SPR_NOACCESS,
3581 &spr_read_generic, &spr_write_generic,
3582 0x00000000);
3583 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3584 SPR_NOACCESS, SPR_NOACCESS,
3585 &spr_read_generic, &spr_write_generic,
3586 0x00000000);
3587 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3588 SPR_NOACCESS, SPR_NOACCESS,
3589 &spr_read_generic, &spr_write_generic,
3590 0x00000000);
3591 /* XXX : not implemented */
3592 spr_register(env, SPR_440_CCR1, "CCR1",
3593 SPR_NOACCESS, SPR_NOACCESS,
3594 &spr_read_generic, &spr_write_generic,
3595 0x00000000);
3596 /* Memory management */
3597 #if !defined(CONFIG_USER_ONLY)
3598 env->nb_tlb = 64;
3599 env->nb_ways = 1;
3600 env->id_tlbs = 0;
3601 env->tlb_type = TLB_EMB;
3602 #endif
3603 init_excp_BookE(env);
3604 env->dcache_line_size = 32;
3605 env->icache_line_size = 32;
3606 ppc40x_irq_init(env);
3607
3608 SET_FIT_PERIOD(12, 16, 20, 24);
3609 SET_WDT_PERIOD(20, 24, 28, 32);
3610 }
3611
3612 POWERPC_FAMILY(440EP)(ObjectClass *oc, void *data)
3613 {
3614 DeviceClass *dc = DEVICE_CLASS(oc);
3615 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3616
3617 dc->desc = "PowerPC 440 EP";
3618 pcc->init_proc = init_proc_440EP;
3619 pcc->check_pow = check_pow_nocheck;
3620 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3621 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
3622 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
3623 PPC_FLOAT_STFIWX |
3624 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3625 PPC_CACHE | PPC_CACHE_ICBI |
3626 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3627 PPC_MEM_TLBSYNC | PPC_MFTB |
3628 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3629 PPC_440_SPEC;
3630 pcc->msr_mask = (1ull << MSR_POW) |
3631 (1ull << MSR_CE) |
3632 (1ull << MSR_EE) |
3633 (1ull << MSR_PR) |
3634 (1ull << MSR_FP) |
3635 (1ull << MSR_ME) |
3636 (1ull << MSR_FE0) |
3637 (1ull << MSR_DWE) |
3638 (1ull << MSR_DE) |
3639 (1ull << MSR_FE1) |
3640 (1ull << MSR_IR) |
3641 (1ull << MSR_DR);
3642 pcc->mmu_model = POWERPC_MMU_BOOKE;
3643 pcc->excp_model = POWERPC_EXCP_BOOKE;
3644 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3645 pcc->bfd_mach = bfd_mach_ppc_403;
3646 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3647 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3648 }
3649
3650 static void init_proc_440GP (CPUPPCState *env)
3651 {
3652 /* Time base */
3653 gen_tbl(env);
3654 gen_spr_BookE(env, 0x000000000000FFFFULL);
3655 gen_spr_440(env);
3656 gen_spr_usprgh(env);
3657 /* Processor identification */
3658 spr_register(env, SPR_BOOKE_PIR, "PIR",
3659 SPR_NOACCESS, SPR_NOACCESS,
3660 &spr_read_generic, &spr_write_pir,
3661 0x00000000);
3662 /* XXX : not implemented */
3663 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3664 SPR_NOACCESS, SPR_NOACCESS,
3665 &spr_read_generic, &spr_write_generic,
3666 0x00000000);
3667 /* XXX : not implemented */
3668 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3669 SPR_NOACCESS, SPR_NOACCESS,
3670 &spr_read_generic, &spr_write_generic,
3671 0x00000000);
3672 /* XXX : not implemented */
3673 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3674 SPR_NOACCESS, SPR_NOACCESS,
3675 &spr_read_generic, &spr_write_generic,
3676 0x00000000);
3677 /* XXX : not implemented */
3678 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3679 SPR_NOACCESS, SPR_NOACCESS,
3680 &spr_read_generic, &spr_write_generic,
3681 0x00000000);
3682 /* Memory management */
3683 #if !defined(CONFIG_USER_ONLY)
3684 env->nb_tlb = 64;
3685 env->nb_ways = 1;
3686 env->id_tlbs = 0;
3687 env->tlb_type = TLB_EMB;
3688 #endif
3689 init_excp_BookE(env);
3690 env->dcache_line_size = 32;
3691 env->icache_line_size = 32;
3692 /* XXX: TODO: allocate internal IRQ controller */
3693
3694 SET_FIT_PERIOD(12, 16, 20, 24);
3695 SET_WDT_PERIOD(20, 24, 28, 32);
3696 }
3697
3698 POWERPC_FAMILY(440GP)(ObjectClass *oc, void *data)
3699 {
3700 DeviceClass *dc = DEVICE_CLASS(oc);
3701 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3702
3703 dc->desc = "PowerPC 440 GP";
3704 pcc->init_proc = init_proc_440GP;
3705 pcc->check_pow = check_pow_nocheck;
3706 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3707 PPC_DCR | PPC_DCRX | PPC_WRTEE | PPC_MFAPIDI |
3708 PPC_CACHE | PPC_CACHE_ICBI |
3709 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3710 PPC_MEM_TLBSYNC | PPC_TLBIVA | PPC_MFTB |
3711 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3712 PPC_440_SPEC;
3713 pcc->msr_mask = (1ull << MSR_POW) |
3714 (1ull << MSR_CE) |
3715 (1ull << MSR_EE) |
3716 (1ull << MSR_PR) |
3717 (1ull << MSR_FP) |
3718 (1ull << MSR_ME) |
3719 (1ull << MSR_FE0) |
3720 (1ull << MSR_DWE) |
3721 (1ull << MSR_DE) |
3722 (1ull << MSR_FE1) |
3723 (1ull << MSR_IR) |
3724 (1ull << MSR_DR);
3725 pcc->mmu_model = POWERPC_MMU_BOOKE;
3726 pcc->excp_model = POWERPC_EXCP_BOOKE;
3727 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3728 pcc->bfd_mach = bfd_mach_ppc_403;
3729 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3730 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3731 }
3732
3733 static void init_proc_440x4 (CPUPPCState *env)
3734 {
3735 /* Time base */
3736 gen_tbl(env);
3737 gen_spr_BookE(env, 0x000000000000FFFFULL);
3738 gen_spr_440(env);
3739 gen_spr_usprgh(env);
3740 /* Processor identification */
3741 spr_register(env, SPR_BOOKE_PIR, "PIR",
3742 SPR_NOACCESS, SPR_NOACCESS,
3743 &spr_read_generic, &spr_write_pir,
3744 0x00000000);
3745 /* XXX : not implemented */
3746 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3747 SPR_NOACCESS, SPR_NOACCESS,
3748 &spr_read_generic, &spr_write_generic,
3749 0x00000000);
3750 /* XXX : not implemented */
3751 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3752 SPR_NOACCESS, SPR_NOACCESS,
3753 &spr_read_generic, &spr_write_generic,
3754 0x00000000);
3755 /* XXX : not implemented */
3756 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3757 SPR_NOACCESS, SPR_NOACCESS,
3758 &spr_read_generic, &spr_write_generic,
3759 0x00000000);
3760 /* XXX : not implemented */
3761 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3762 SPR_NOACCESS, SPR_NOACCESS,
3763 &spr_read_generic, &spr_write_generic,
3764 0x00000000);
3765 /* Memory management */
3766 #if !defined(CONFIG_USER_ONLY)
3767 env->nb_tlb = 64;
3768 env->nb_ways = 1;
3769 env->id_tlbs = 0;
3770 env->tlb_type = TLB_EMB;
3771 #endif
3772 init_excp_BookE(env);
3773 env->dcache_line_size = 32;
3774 env->icache_line_size = 32;
3775 /* XXX: TODO: allocate internal IRQ controller */
3776
3777 SET_FIT_PERIOD(12, 16, 20, 24);
3778 SET_WDT_PERIOD(20, 24, 28, 32);
3779 }
3780
3781 POWERPC_FAMILY(440x4)(ObjectClass *oc, void *data)
3782 {
3783 DeviceClass *dc = DEVICE_CLASS(oc);
3784 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3785
3786 dc->desc = "PowerPC 440x4";
3787 pcc->init_proc = init_proc_440x4;
3788 pcc->check_pow = check_pow_nocheck;
3789 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3790 PPC_DCR | PPC_WRTEE |
3791 PPC_CACHE | PPC_CACHE_ICBI |
3792 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3793 PPC_MEM_TLBSYNC | PPC_MFTB |
3794 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3795 PPC_440_SPEC;
3796 pcc->msr_mask = (1ull << MSR_POW) |
3797 (1ull << MSR_CE) |
3798 (1ull << MSR_EE) |
3799 (1ull << MSR_PR) |
3800 (1ull << MSR_FP) |
3801 (1ull << MSR_ME) |
3802 (1ull << MSR_FE0) |
3803 (1ull << MSR_DWE) |
3804 (1ull << MSR_DE) |
3805 (1ull << MSR_FE1) |
3806 (1ull << MSR_IR) |
3807 (1ull << MSR_DR);
3808 pcc->mmu_model = POWERPC_MMU_BOOKE;
3809 pcc->excp_model = POWERPC_EXCP_BOOKE;
3810 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3811 pcc->bfd_mach = bfd_mach_ppc_403;
3812 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3813 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3814 }
3815
3816 static void init_proc_440x5 (CPUPPCState *env)
3817 {
3818 /* Time base */
3819 gen_tbl(env);
3820 gen_spr_BookE(env, 0x000000000000FFFFULL);
3821 gen_spr_440(env);
3822 gen_spr_usprgh(env);
3823 /* Processor identification */
3824 spr_register(env, SPR_BOOKE_PIR, "PIR",
3825 SPR_NOACCESS, SPR_NOACCESS,
3826 &spr_read_generic, &spr_write_pir,
3827 0x00000000);
3828 /* XXX : not implemented */
3829 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3830 SPR_NOACCESS, SPR_NOACCESS,
3831 &spr_read_generic, &spr_write_generic,
3832 0x00000000);
3833 /* XXX : not implemented */
3834 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3835 SPR_NOACCESS, SPR_NOACCESS,
3836 &spr_read_generic, &spr_write_generic,
3837 0x00000000);
3838 /* XXX : not implemented */
3839 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3840 SPR_NOACCESS, SPR_NOACCESS,
3841 &spr_read_generic, &spr_write_generic,
3842 0x00000000);
3843 /* XXX : not implemented */
3844 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3845 SPR_NOACCESS, SPR_NOACCESS,
3846 &spr_read_generic, &spr_write_generic,
3847 0x00000000);
3848 /* XXX : not implemented */
3849 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3850 SPR_NOACCESS, SPR_NOACCESS,
3851 &spr_read_generic, &spr_write_generic,
3852 0x00000000);
3853 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3854 SPR_NOACCESS, SPR_NOACCESS,
3855 &spr_read_generic, &spr_write_generic,
3856 0x00000000);
3857 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3858 SPR_NOACCESS, SPR_NOACCESS,
3859 &spr_read_generic, &spr_write_generic,
3860 0x00000000);
3861 /* XXX : not implemented */
3862 spr_register(env, SPR_440_CCR1, "CCR1",
3863 SPR_NOACCESS, SPR_NOACCESS,
3864 &spr_read_generic, &spr_write_generic,
3865 0x00000000);
3866 /* Memory management */
3867 #if !defined(CONFIG_USER_ONLY)
3868 env->nb_tlb = 64;
3869 env->nb_ways = 1;
3870 env->id_tlbs = 0;
3871 env->tlb_type = TLB_EMB;
3872 #endif
3873 init_excp_BookE(env);
3874 env->dcache_line_size = 32;
3875 env->icache_line_size = 32;
3876 ppc40x_irq_init(env);
3877
3878 SET_FIT_PERIOD(12, 16, 20, 24);
3879 SET_WDT_PERIOD(20, 24, 28, 32);
3880 }
3881
3882 POWERPC_FAMILY(440x5)(ObjectClass *oc, void *data)
3883 {
3884 DeviceClass *dc = DEVICE_CLASS(oc);
3885 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3886
3887 dc->desc = "PowerPC 440x5";
3888 pcc->init_proc = init_proc_440x5;
3889 pcc->check_pow = check_pow_nocheck;
3890 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3891 PPC_DCR | PPC_WRTEE | PPC_RFMCI |
3892 PPC_CACHE | PPC_CACHE_ICBI |
3893 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
3894 PPC_MEM_TLBSYNC | PPC_MFTB |
3895 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
3896 PPC_440_SPEC;
3897 pcc->msr_mask = (1ull << MSR_POW) |
3898 (1ull << MSR_CE) |
3899 (1ull << MSR_EE) |
3900 (1ull << MSR_PR) |
3901 (1ull << MSR_FP) |
3902 (1ull << MSR_ME) |
3903 (1ull << MSR_FE0) |
3904 (1ull << MSR_DWE) |
3905 (1ull << MSR_DE) |
3906 (1ull << MSR_FE1) |
3907 (1ull << MSR_IR) |
3908 (1ull << MSR_DR);
3909 pcc->mmu_model = POWERPC_MMU_BOOKE;
3910 pcc->excp_model = POWERPC_EXCP_BOOKE;
3911 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
3912 pcc->bfd_mach = bfd_mach_ppc_403;
3913 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
3914 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
3915 }
3916
3917 static void init_proc_460 (CPUPPCState *env)
3918 {
3919 /* Time base */
3920 gen_tbl(env);
3921 gen_spr_BookE(env, 0x000000000000FFFFULL);
3922 gen_spr_440(env);
3923 gen_spr_usprgh(env);
3924 /* Processor identification */
3925 spr_register(env, SPR_BOOKE_PIR, "PIR",
3926 SPR_NOACCESS, SPR_NOACCESS,
3927 &spr_read_generic, &spr_write_pir,
3928 0x00000000);
3929 /* XXX : not implemented */
3930 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
3931 SPR_NOACCESS, SPR_NOACCESS,
3932 &spr_read_generic, &spr_write_generic,
3933 0x00000000);
3934 /* XXX : not implemented */
3935 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
3936 SPR_NOACCESS, SPR_NOACCESS,
3937 &spr_read_generic, &spr_write_generic,
3938 0x00000000);
3939 /* XXX : not implemented */
3940 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
3941 SPR_NOACCESS, SPR_NOACCESS,
3942 &spr_read_generic, &spr_write_generic,
3943 0x00000000);
3944 /* XXX : not implemented */
3945 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
3946 SPR_NOACCESS, SPR_NOACCESS,
3947 &spr_read_generic, &spr_write_generic,
3948 0x00000000);
3949 /* XXX : not implemented */
3950 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
3951 SPR_NOACCESS, SPR_NOACCESS,
3952 &spr_read_generic, &spr_write_generic,
3953 0x00000000);
3954 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
3955 SPR_NOACCESS, SPR_NOACCESS,
3956 &spr_read_generic, &spr_write_generic,
3957 0x00000000);
3958 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
3959 SPR_NOACCESS, SPR_NOACCESS,
3960 &spr_read_generic, &spr_write_generic,
3961 0x00000000);
3962 /* XXX : not implemented */
3963 spr_register(env, SPR_440_CCR1, "CCR1",
3964 SPR_NOACCESS, SPR_NOACCESS,
3965 &spr_read_generic, &spr_write_generic,
3966 0x00000000);
3967 /* XXX : not implemented */
3968 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
3969 &spr_read_generic, &spr_write_generic,
3970 &spr_read_generic, &spr_write_generic,
3971 0x00000000);
3972 /* Memory management */
3973 #if !defined(CONFIG_USER_ONLY)
3974 env->nb_tlb = 64;
3975 env->nb_ways = 1;
3976 env->id_tlbs = 0;
3977 env->tlb_type = TLB_EMB;
3978 #endif
3979 init_excp_BookE(env);
3980 env->dcache_line_size = 32;
3981 env->icache_line_size = 32;
3982 /* XXX: TODO: allocate internal IRQ controller */
3983
3984 SET_FIT_PERIOD(12, 16, 20, 24);
3985 SET_WDT_PERIOD(20, 24, 28, 32);
3986 }
3987
3988 POWERPC_FAMILY(460)(ObjectClass *oc, void *data)
3989 {
3990 DeviceClass *dc = DEVICE_CLASS(oc);
3991 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
3992
3993 dc->desc = "PowerPC 460 (guessed)";
3994 pcc->init_proc = init_proc_460;
3995 pcc->check_pow = check_pow_nocheck;
3996 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
3997 PPC_DCR | PPC_DCRX | PPC_DCRUX |
3998 PPC_WRTEE | PPC_MFAPIDI | PPC_MFTB |
3999 PPC_CACHE | PPC_CACHE_ICBI |
4000 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4001 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4002 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4003 PPC_440_SPEC;
4004 pcc->msr_mask = (1ull << MSR_POW) |
4005 (1ull << MSR_CE) |
4006 (1ull << MSR_EE) |
4007 (1ull << MSR_PR) |
4008 (1ull << MSR_FP) |
4009 (1ull << MSR_ME) |
4010 (1ull << MSR_FE0) |
4011 (1ull << MSR_DWE) |
4012 (1ull << MSR_DE) |
4013 (1ull << MSR_FE1) |
4014 (1ull << MSR_IR) |
4015 (1ull << MSR_DR);
4016 pcc->mmu_model = POWERPC_MMU_BOOKE;
4017 pcc->excp_model = POWERPC_EXCP_BOOKE;
4018 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4019 pcc->bfd_mach = bfd_mach_ppc_403;
4020 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4021 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4022 }
4023
4024 static void init_proc_460F (CPUPPCState *env)
4025 {
4026 /* Time base */
4027 gen_tbl(env);
4028 gen_spr_BookE(env, 0x000000000000FFFFULL);
4029 gen_spr_440(env);
4030 gen_spr_usprgh(env);
4031 /* Processor identification */
4032 spr_register(env, SPR_BOOKE_PIR, "PIR",
4033 SPR_NOACCESS, SPR_NOACCESS,
4034 &spr_read_generic, &spr_write_pir,
4035 0x00000000);
4036 /* XXX : not implemented */
4037 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4038 SPR_NOACCESS, SPR_NOACCESS,
4039 &spr_read_generic, &spr_write_generic,
4040 0x00000000);
4041 /* XXX : not implemented */
4042 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4043 SPR_NOACCESS, SPR_NOACCESS,
4044 &spr_read_generic, &spr_write_generic,
4045 0x00000000);
4046 /* XXX : not implemented */
4047 spr_register(env, SPR_BOOKE_DVC1, "DVC1",
4048 SPR_NOACCESS, SPR_NOACCESS,
4049 &spr_read_generic, &spr_write_generic,
4050 0x00000000);
4051 /* XXX : not implemented */
4052 spr_register(env, SPR_BOOKE_DVC2, "DVC2",
4053 SPR_NOACCESS, SPR_NOACCESS,
4054 &spr_read_generic, &spr_write_generic,
4055 0x00000000);
4056 /* XXX : not implemented */
4057 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4058 SPR_NOACCESS, SPR_NOACCESS,
4059 &spr_read_generic, &spr_write_generic,
4060 0x00000000);
4061 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4062 SPR_NOACCESS, SPR_NOACCESS,
4063 &spr_read_generic, &spr_write_generic,
4064 0x00000000);
4065 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4066 SPR_NOACCESS, SPR_NOACCESS,
4067 &spr_read_generic, &spr_write_generic,
4068 0x00000000);
4069 /* XXX : not implemented */
4070 spr_register(env, SPR_440_CCR1, "CCR1",
4071 SPR_NOACCESS, SPR_NOACCESS,
4072 &spr_read_generic, &spr_write_generic,
4073 0x00000000);
4074 /* XXX : not implemented */
4075 spr_register(env, SPR_DCRIPR, "SPR_DCRIPR",
4076 &spr_read_generic, &spr_write_generic,
4077 &spr_read_generic, &spr_write_generic,
4078 0x00000000);
4079 /* Memory management */
4080 #if !defined(CONFIG_USER_ONLY)
4081 env->nb_tlb = 64;
4082 env->nb_ways = 1;
4083 env->id_tlbs = 0;
4084 env->tlb_type = TLB_EMB;
4085 #endif
4086 init_excp_BookE(env);
4087 env->dcache_line_size = 32;
4088 env->icache_line_size = 32;
4089 /* XXX: TODO: allocate internal IRQ controller */
4090
4091 SET_FIT_PERIOD(12, 16, 20, 24);
4092 SET_WDT_PERIOD(20, 24, 28, 32);
4093 }
4094
4095 POWERPC_FAMILY(460F)(ObjectClass *oc, void *data)
4096 {
4097 DeviceClass *dc = DEVICE_CLASS(oc);
4098 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4099
4100 dc->desc = "PowerPC 460F (guessed)";
4101 pcc->init_proc = init_proc_460F;
4102 pcc->check_pow = check_pow_nocheck;
4103 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4104 PPC_FLOAT | PPC_FLOAT_FRES | PPC_FLOAT_FSEL |
4105 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
4106 PPC_FLOAT_STFIWX | PPC_MFTB |
4107 PPC_DCR | PPC_DCRX | PPC_DCRUX |
4108 PPC_WRTEE | PPC_MFAPIDI |
4109 PPC_CACHE | PPC_CACHE_ICBI |
4110 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4111 PPC_MEM_TLBSYNC | PPC_TLBIVA |
4112 PPC_BOOKE | PPC_4xx_COMMON | PPC_405_MAC |
4113 PPC_440_SPEC;
4114 pcc->msr_mask = (1ull << MSR_POW) |
4115 (1ull << MSR_CE) |
4116 (1ull << MSR_EE) |
4117 (1ull << MSR_PR) |
4118 (1ull << MSR_FP) |
4119 (1ull << MSR_ME) |
4120 (1ull << MSR_FE0) |
4121 (1ull << MSR_DWE) |
4122 (1ull << MSR_DE) |
4123 (1ull << MSR_FE1) |
4124 (1ull << MSR_IR) |
4125 (1ull << MSR_DR);
4126 pcc->mmu_model = POWERPC_MMU_BOOKE;
4127 pcc->excp_model = POWERPC_EXCP_BOOKE;
4128 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4129 pcc->bfd_mach = bfd_mach_ppc_403;
4130 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DWE |
4131 POWERPC_FLAG_DE | POWERPC_FLAG_BUS_CLK;
4132 }
4133
4134 static void init_proc_MPC5xx (CPUPPCState *env)
4135 {
4136 /* Time base */
4137 gen_tbl(env);
4138 gen_spr_5xx_8xx(env);
4139 gen_spr_5xx(env);
4140 init_excp_MPC5xx(env);
4141 env->dcache_line_size = 32;
4142 env->icache_line_size = 32;
4143 /* XXX: TODO: allocate internal IRQ controller */
4144 }
4145
4146 POWERPC_FAMILY(MPC5xx)(ObjectClass *oc, void *data)
4147 {
4148 DeviceClass *dc = DEVICE_CLASS(oc);
4149 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4150
4151 dc->desc = "Freescale 5xx cores (aka RCPU)";
4152 pcc->init_proc = init_proc_MPC5xx;
4153 pcc->check_pow = check_pow_none;
4154 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4155 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4156 PPC_CACHE_ICBI | PPC_FLOAT | PPC_FLOAT_STFIWX |
4157 PPC_MFTB;
4158 pcc->msr_mask = (1ull << MSR_ILE) |
4159 (1ull << MSR_EE) |
4160 (1ull << MSR_PR) |
4161 (1ull << MSR_FP) |
4162 (1ull << MSR_ME) |
4163 (1ull << MSR_FE0) |
4164 (1ull << MSR_SE) |
4165 (1ull << MSR_DE) |
4166 (1ull << MSR_FE1) |
4167 (1ull << MSR_EP) |
4168 (1ull << MSR_RI) |
4169 (1ull << MSR_LE);
4170 pcc->mmu_model = POWERPC_MMU_REAL;
4171 pcc->excp_model = POWERPC_EXCP_603;
4172 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4173 pcc->bfd_mach = bfd_mach_ppc_505;
4174 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4175 POWERPC_FLAG_BUS_CLK;
4176 }
4177
4178 static void init_proc_MPC8xx (CPUPPCState *env)
4179 {
4180 /* Time base */
4181 gen_tbl(env);
4182 gen_spr_5xx_8xx(env);
4183 gen_spr_8xx(env);
4184 init_excp_MPC8xx(env);
4185 env->dcache_line_size = 32;
4186 env->icache_line_size = 32;
4187 /* XXX: TODO: allocate internal IRQ controller */
4188 }
4189
4190 POWERPC_FAMILY(MPC8xx)(ObjectClass *oc, void *data)
4191 {
4192 DeviceClass *dc = DEVICE_CLASS(oc);
4193 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4194
4195 dc->desc = "Freescale 8xx cores (aka PowerQUICC)";
4196 pcc->init_proc = init_proc_MPC8xx;
4197 pcc->check_pow = check_pow_none;
4198 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING |
4199 PPC_MEM_EIEIO | PPC_MEM_SYNC |
4200 PPC_CACHE_ICBI | PPC_MFTB;
4201 pcc->msr_mask = (1ull << MSR_ILE) |
4202 (1ull << MSR_EE) |
4203 (1ull << MSR_PR) |
4204 (1ull << MSR_FP) |
4205 (1ull << MSR_ME) |
4206 (1ull << MSR_SE) |
4207 (1ull << MSR_DE) |
4208 (1ull << MSR_EP) |
4209 (1ull << MSR_IR) |
4210 (1ull << MSR_DR) |
4211 (1ull << MSR_RI) |
4212 (1ull << MSR_LE);
4213 pcc->mmu_model = POWERPC_MMU_MPC8xx;
4214 pcc->excp_model = POWERPC_EXCP_603;
4215 pcc->bus_model = PPC_FLAGS_INPUT_RCPU;
4216 pcc->bfd_mach = bfd_mach_ppc_860;
4217 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
4218 POWERPC_FLAG_BUS_CLK;
4219 }
4220
4221 /* Freescale 82xx cores (aka PowerQUICC-II) */
4222
4223 static void init_proc_G2 (CPUPPCState *env)
4224 {
4225 gen_spr_ne_601(env);
4226 gen_spr_G2_755(env);
4227 gen_spr_G2(env);
4228 /* Time base */
4229 gen_tbl(env);
4230 /* External access control */
4231 /* XXX : not implemented */
4232 spr_register(env, SPR_EAR, "EAR",
4233 SPR_NOACCESS, SPR_NOACCESS,
4234 &spr_read_generic, &spr_write_generic,
4235 0x00000000);
4236 /* Hardware implementation register */
4237 /* XXX : not implemented */
4238 spr_register(env, SPR_HID0, "HID0",
4239 SPR_NOACCESS, SPR_NOACCESS,
4240 &spr_read_generic, &spr_write_generic,
4241 0x00000000);
4242 /* XXX : not implemented */
4243 spr_register(env, SPR_HID1, "HID1",
4244 SPR_NOACCESS, SPR_NOACCESS,
4245 &spr_read_generic, &spr_write_generic,
4246 0x00000000);
4247 /* XXX : not implemented */
4248 spr_register(env, SPR_HID2, "HID2",
4249 SPR_NOACCESS, SPR_NOACCESS,
4250 &spr_read_generic, &spr_write_generic,
4251 0x00000000);
4252 /* Memory management */
4253 gen_low_BATs(env);
4254 gen_high_BATs(env);
4255 gen_6xx_7xx_soft_tlb(env, 64, 2);
4256 init_excp_G2(env);
4257 env->dcache_line_size = 32;
4258 env->icache_line_size = 32;
4259 /* Allocate hardware IRQ controller */
4260 ppc6xx_irq_init(env);
4261 }
4262
4263 POWERPC_FAMILY(G2)(ObjectClass *oc, void *data)
4264 {
4265 DeviceClass *dc = DEVICE_CLASS(oc);
4266 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4267
4268 dc->desc = "PowerPC G2";
4269 pcc->init_proc = init_proc_G2;
4270 pcc->check_pow = check_pow_hid0;
4271 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4272 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4273 PPC_FLOAT_STFIWX |
4274 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4275 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4276 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4277 PPC_SEGMENT | PPC_EXTERN;
4278 pcc->msr_mask = (1ull << MSR_POW) |
4279 (1ull << MSR_TGPR) |
4280 (1ull << MSR_EE) |
4281 (1ull << MSR_PR) |
4282 (1ull << MSR_FP) |
4283 (1ull << MSR_ME) |
4284 (1ull << MSR_FE0) |
4285 (1ull << MSR_SE) |
4286 (1ull << MSR_DE) |
4287 (1ull << MSR_FE1) |
4288 (1ull << MSR_AL) |
4289 (1ull << MSR_EP) |
4290 (1ull << MSR_IR) |
4291 (1ull << MSR_DR) |
4292 (1ull << MSR_RI);
4293 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4294 pcc->excp_model = POWERPC_EXCP_G2;
4295 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4296 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4297 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4298 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4299 }
4300
4301 static void init_proc_G2LE (CPUPPCState *env)
4302 {
4303 gen_spr_ne_601(env);
4304 gen_spr_G2_755(env);
4305 gen_spr_G2(env);
4306 /* Time base */
4307 gen_tbl(env);
4308 /* External access control */
4309 /* XXX : not implemented */
4310 spr_register(env, SPR_EAR, "EAR",
4311 SPR_NOACCESS, SPR_NOACCESS,
4312 &spr_read_generic, &spr_write_generic,
4313 0x00000000);
4314 /* Hardware implementation register */
4315 /* XXX : not implemented */
4316 spr_register(env, SPR_HID0, "HID0",
4317 SPR_NOACCESS, SPR_NOACCESS,
4318 &spr_read_generic, &spr_write_generic,
4319 0x00000000);
4320 /* XXX : not implemented */
4321 spr_register(env, SPR_HID1, "HID1",
4322 SPR_NOACCESS, SPR_NOACCESS,
4323 &spr_read_generic, &spr_write_generic,
4324 0x00000000);
4325 /* XXX : not implemented */
4326 spr_register(env, SPR_HID2, "HID2",
4327 SPR_NOACCESS, SPR_NOACCESS,
4328 &spr_read_generic, &spr_write_generic,
4329 0x00000000);
4330 /* Breakpoints */
4331 /* XXX : not implemented */
4332 spr_register(env, SPR_DABR, "DABR",
4333 SPR_NOACCESS, SPR_NOACCESS,
4334 &spr_read_generic, &spr_write_generic,
4335 0x00000000);
4336 /* XXX : not implemented */
4337 spr_register(env, SPR_DABR2, "DABR2",
4338 SPR_NOACCESS, SPR_NOACCESS,
4339 &spr_read_generic, &spr_write_generic,
4340 0x00000000);
4341 /* XXX : not implemented */
4342 spr_register(env, SPR_IABR2, "IABR2",
4343 SPR_NOACCESS, SPR_NOACCESS,
4344 &spr_read_generic, &spr_write_generic,
4345 0x00000000);
4346 /* XXX : not implemented */
4347 spr_register(env, SPR_IBCR, "IBCR",
4348 SPR_NOACCESS, SPR_NOACCESS,
4349 &spr_read_generic, &spr_write_generic,
4350 0x00000000);
4351 /* XXX : not implemented */
4352 spr_register(env, SPR_DBCR, "DBCR",
4353 SPR_NOACCESS, SPR_NOACCESS,
4354 &spr_read_generic, &spr_write_generic,
4355 0x00000000);
4356
4357 /* Memory management */
4358 gen_low_BATs(env);
4359 gen_high_BATs(env);
4360 gen_6xx_7xx_soft_tlb(env, 64, 2);
4361 init_excp_G2(env);
4362 env->dcache_line_size = 32;
4363 env->icache_line_size = 32;
4364 /* Allocate hardware IRQ controller */
4365 ppc6xx_irq_init(env);
4366 }
4367
4368 POWERPC_FAMILY(G2LE)(ObjectClass *oc, void *data)
4369 {
4370 DeviceClass *dc = DEVICE_CLASS(oc);
4371 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4372
4373 dc->desc = "PowerPC G2LE";
4374 pcc->init_proc = init_proc_G2LE;
4375 pcc->check_pow = check_pow_hid0;
4376 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4377 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4378 PPC_FLOAT_STFIWX |
4379 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4380 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4381 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4382 PPC_SEGMENT | PPC_EXTERN;
4383 pcc->msr_mask = (1ull << MSR_POW) |
4384 (1ull << MSR_TGPR) |
4385 (1ull << MSR_ILE) |
4386 (1ull << MSR_EE) |
4387 (1ull << MSR_PR) |
4388 (1ull << MSR_FP) |
4389 (1ull << MSR_ME) |
4390 (1ull << MSR_FE0) |
4391 (1ull << MSR_SE) |
4392 (1ull << MSR_DE) |
4393 (1ull << MSR_FE1) |
4394 (1ull << MSR_AL) |
4395 (1ull << MSR_EP) |
4396 (1ull << MSR_IR) |
4397 (1ull << MSR_DR) |
4398 (1ull << MSR_RI) |
4399 (1ull << MSR_LE);
4400 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4401 pcc->excp_model = POWERPC_EXCP_G2;
4402 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4403 pcc->bfd_mach = bfd_mach_ppc_ec603e;
4404 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4405 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4406 }
4407
4408 static void init_proc_e200 (CPUPPCState *env)
4409 {
4410 /* Time base */
4411 gen_tbl(env);
4412 gen_spr_BookE(env, 0x000000070000FFFFULL);
4413 /* XXX : not implemented */
4414 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4415 &spr_read_spefscr, &spr_write_spefscr,
4416 &spr_read_spefscr, &spr_write_spefscr,
4417 0x00000000);
4418 /* Memory management */
4419 gen_spr_BookE206(env, 0x0000005D, NULL);
4420 /* XXX : not implemented */
4421 spr_register(env, SPR_HID0, "HID0",
4422 SPR_NOACCESS, SPR_NOACCESS,
4423 &spr_read_generic, &spr_write_generic,
4424 0x00000000);
4425 /* XXX : not implemented */
4426 spr_register(env, SPR_HID1, "HID1",
4427 SPR_NOACCESS, SPR_NOACCESS,
4428 &spr_read_generic, &spr_write_generic,
4429 0x00000000);
4430 /* XXX : not implemented */
4431 spr_register(env, SPR_Exxx_ALTCTXCR, "ALTCTXCR",
4432 SPR_NOACCESS, SPR_NOACCESS,
4433 &spr_read_generic, &spr_write_generic,
4434 0x00000000);
4435 /* XXX : not implemented */
4436 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4437 SPR_NOACCESS, SPR_NOACCESS,
4438 &spr_read_generic, &spr_write_generic,
4439 0x00000000);
4440 /* XXX : not implemented */
4441 spr_register(env, SPR_Exxx_CTXCR, "CTXCR",
4442 SPR_NOACCESS, SPR_NOACCESS,
4443 &spr_read_generic, &spr_write_generic,
4444 0x00000000);
4445 /* XXX : not implemented */
4446 spr_register(env, SPR_Exxx_DBCNT, "DBCNT",
4447 SPR_NOACCESS, SPR_NOACCESS,
4448 &spr_read_generic, &spr_write_generic,
4449 0x00000000);
4450 /* XXX : not implemented */
4451 spr_register(env, SPR_Exxx_DBCR3, "DBCR3",
4452 SPR_NOACCESS, SPR_NOACCESS,
4453 &spr_read_generic, &spr_write_generic,
4454 0x00000000);
4455 /* XXX : not implemented */
4456 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4457 &spr_read_generic, SPR_NOACCESS,
4458 &spr_read_generic, SPR_NOACCESS,
4459 0x00000000);
4460 /* XXX : not implemented */
4461 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4462 SPR_NOACCESS, SPR_NOACCESS,
4463 &spr_read_generic, &spr_write_generic,
4464 0x00000000);
4465 /* XXX : not implemented */
4466 spr_register(env, SPR_Exxx_L1FINV0, "L1FINV0",
4467 SPR_NOACCESS, SPR_NOACCESS,
4468 &spr_read_generic, &spr_write_generic,
4469 0x00000000);
4470 /* XXX : not implemented */
4471 spr_register(env, SPR_BOOKE_TLB0CFG, "TLB0CFG",
4472 SPR_NOACCESS, SPR_NOACCESS,
4473 &spr_read_generic, &spr_write_generic,
4474 0x00000000);
4475 /* XXX : not implemented */
4476 spr_register(env, SPR_BOOKE_TLB1CFG, "TLB1CFG",
4477 SPR_NOACCESS, SPR_NOACCESS,
4478 &spr_read_generic, &spr_write_generic,
4479 0x00000000);
4480 /* XXX : not implemented */
4481 spr_register(env, SPR_BOOKE_IAC3, "IAC3",
4482 SPR_NOACCESS, SPR_NOACCESS,
4483 &spr_read_generic, &spr_write_generic,
4484 0x00000000);
4485 /* XXX : not implemented */
4486 spr_register(env, SPR_BOOKE_IAC4, "IAC4",
4487 SPR_NOACCESS, SPR_NOACCESS,
4488 &spr_read_generic, &spr_write_generic,
4489 0x00000000);
4490 /* XXX : not implemented */
4491 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4492 SPR_NOACCESS, SPR_NOACCESS,
4493 &spr_read_generic, &spr_write_generic,
4494 0x00000000); /* TOFIX */
4495 spr_register(env, SPR_BOOKE_DSRR0, "DSRR0",
4496 SPR_NOACCESS, SPR_NOACCESS,
4497 &spr_read_generic, &spr_write_generic,
4498 0x00000000);
4499 spr_register(env, SPR_BOOKE_DSRR1, "DSRR1",
4500 SPR_NOACCESS, SPR_NOACCESS,
4501 &spr_read_generic, &spr_write_generic,
4502 0x00000000);
4503 #if !defined(CONFIG_USER_ONLY)
4504 env->nb_tlb = 64;
4505 env->nb_ways = 1;
4506 env->id_tlbs = 0;
4507 env->tlb_type = TLB_EMB;
4508 #endif
4509 init_excp_e200(env, 0xFFFF0000UL);
4510 env->dcache_line_size = 32;
4511 env->icache_line_size = 32;
4512 /* XXX: TODO: allocate internal IRQ controller */
4513 }
4514
4515 POWERPC_FAMILY(e200)(ObjectClass *oc, void *data)
4516 {
4517 DeviceClass *dc = DEVICE_CLASS(oc);
4518 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4519
4520 dc->desc = "e200 core";
4521 pcc->init_proc = init_proc_e200;
4522 pcc->check_pow = check_pow_hid0;
4523 /* XXX: unimplemented instructions:
4524 * dcblc
4525 * dcbtlst
4526 * dcbtstls
4527 * icblc
4528 * icbtls
4529 * tlbivax
4530 * all SPE multiply-accumulate instructions
4531 */
4532 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4533 PPC_SPE | PPC_SPE_SINGLE |
4534 PPC_WRTEE | PPC_RFDI |
4535 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4536 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4537 PPC_MEM_TLBSYNC | PPC_TLBIVAX |
4538 PPC_BOOKE;
4539 pcc->msr_mask = (1ull << MSR_UCLE) |
4540 (1ull << MSR_SPE) |
4541 (1ull << MSR_POW) |
4542 (1ull << MSR_CE) |
4543 (1ull << MSR_EE) |
4544 (1ull << MSR_PR) |
4545 (1ull << MSR_FP) |
4546 (1ull << MSR_ME) |
4547 (1ull << MSR_FE0) |
4548 (1ull << MSR_DWE) |
4549 (1ull << MSR_DE) |
4550 (1ull << MSR_FE1) |
4551 (1ull << MSR_IR) |
4552 (1ull << MSR_DR);
4553 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4554 pcc->excp_model = POWERPC_EXCP_BOOKE;
4555 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4556 pcc->bfd_mach = bfd_mach_ppc_860;
4557 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4558 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4559 POWERPC_FLAG_BUS_CLK;
4560 }
4561
4562 static void init_proc_e300 (CPUPPCState *env)
4563 {
4564 gen_spr_ne_601(env);
4565 gen_spr_603(env);
4566 /* Time base */
4567 gen_tbl(env);
4568 /* hardware implementation registers */
4569 /* XXX : not implemented */
4570 spr_register(env, SPR_HID0, "HID0",
4571 SPR_NOACCESS, SPR_NOACCESS,
4572 &spr_read_generic, &spr_write_generic,
4573 0x00000000);
4574 /* XXX : not implemented */
4575 spr_register(env, SPR_HID1, "HID1",
4576 SPR_NOACCESS, SPR_NOACCESS,
4577 &spr_read_generic, &spr_write_generic,
4578 0x00000000);
4579 /* XXX : not implemented */
4580 spr_register(env, SPR_HID2, "HID2",
4581 SPR_NOACCESS, SPR_NOACCESS,
4582 &spr_read_generic, &spr_write_generic,
4583 0x00000000);
4584 /* Memory management */
4585 gen_low_BATs(env);
4586 gen_high_BATs(env);
4587 gen_6xx_7xx_soft_tlb(env, 64, 2);
4588 init_excp_603(env);
4589 env->dcache_line_size = 32;
4590 env->icache_line_size = 32;
4591 /* Allocate hardware IRQ controller */
4592 ppc6xx_irq_init(env);
4593 }
4594
4595 POWERPC_FAMILY(e300)(ObjectClass *oc, void *data)
4596 {
4597 DeviceClass *dc = DEVICE_CLASS(oc);
4598 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4599
4600 dc->desc = "e300 core";
4601 pcc->init_proc = init_proc_e300;
4602 pcc->check_pow = check_pow_hid0;
4603 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
4604 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
4605 PPC_FLOAT_STFIWX |
4606 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
4607 PPC_MEM_SYNC | PPC_MEM_EIEIO |
4608 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
4609 PPC_SEGMENT | PPC_EXTERN;
4610 pcc->msr_mask = (1ull << MSR_POW) |
4611 (1ull << MSR_TGPR) |
4612 (1ull << MSR_ILE) |
4613 (1ull << MSR_EE) |
4614 (1ull << MSR_PR) |
4615 (1ull << MSR_FP) |
4616 (1ull << MSR_ME) |
4617 (1ull << MSR_FE0) |
4618 (1ull << MSR_SE) |
4619 (1ull << MSR_DE) |
4620 (1ull << MSR_FE1) |
4621 (1ull << MSR_AL) |
4622 (1ull << MSR_EP) |
4623 (1ull << MSR_IR) |
4624 (1ull << MSR_DR) |
4625 (1ull << MSR_RI) |
4626 (1ull << MSR_LE);
4627 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
4628 pcc->excp_model = POWERPC_EXCP_603;
4629 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
4630 pcc->bfd_mach = bfd_mach_ppc_603;
4631 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
4632 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
4633 }
4634
4635 #if !defined(CONFIG_USER_ONLY)
4636 static void spr_write_mas73(void *opaque, int sprn, int gprn)
4637 {
4638 TCGv val = tcg_temp_new();
4639 tcg_gen_ext32u_tl(val, cpu_gpr[gprn]);
4640 gen_store_spr(SPR_BOOKE_MAS3, val);
4641 tcg_gen_shri_tl(val, cpu_gpr[gprn], 32);
4642 gen_store_spr(SPR_BOOKE_MAS7, val);
4643 tcg_temp_free(val);
4644 }
4645
4646 static void spr_read_mas73(void *opaque, int gprn, int sprn)
4647 {
4648 TCGv mas7 = tcg_temp_new();
4649 TCGv mas3 = tcg_temp_new();
4650 gen_load_spr(mas7, SPR_BOOKE_MAS7);
4651 tcg_gen_shli_tl(mas7, mas7, 32);
4652 gen_load_spr(mas3, SPR_BOOKE_MAS3);
4653 tcg_gen_or_tl(cpu_gpr[gprn], mas3, mas7);
4654 tcg_temp_free(mas3);
4655 tcg_temp_free(mas7);
4656 }
4657
4658 #endif
4659
4660 enum fsl_e500_version {
4661 fsl_e500v1,
4662 fsl_e500v2,
4663 fsl_e500mc,
4664 fsl_e5500,
4665 };
4666
4667 static void init_proc_e500 (CPUPPCState *env, int version)
4668 {
4669 PowerPCCPU *cpu = ppc_env_get_cpu(env);
4670 uint32_t tlbncfg[2];
4671 uint64_t ivor_mask;
4672 uint64_t ivpr_mask = 0xFFFF0000ULL;
4673 uint32_t l1cfg0 = 0x3800 /* 8 ways */
4674 | 0x0020; /* 32 kb */
4675 uint32_t l1cfg1 = 0x3800 /* 8 ways */
4676 | 0x0020; /* 32 kb */
4677 #if !defined(CONFIG_USER_ONLY)
4678 int i;
4679 #endif
4680
4681 /* Time base */
4682 gen_tbl(env);
4683 /*
4684 * XXX The e500 doesn't implement IVOR7 and IVOR9, but doesn't
4685 * complain when accessing them.
4686 * gen_spr_BookE(env, 0x0000000F0000FD7FULL);
4687 */
4688 switch (version) {
4689 case fsl_e500v1:
4690 case fsl_e500v2:
4691 default:
4692 ivor_mask = 0x0000000F0000FFFFULL;
4693 break;
4694 case fsl_e500mc:
4695 case fsl_e5500:
4696 ivor_mask = 0x000003FE0000FFFFULL;
4697 break;
4698 }
4699 gen_spr_BookE(env, ivor_mask);
4700 /* Processor identification */
4701 spr_register(env, SPR_BOOKE_PIR, "PIR",
4702 SPR_NOACCESS, SPR_NOACCESS,
4703 &spr_read_generic, &spr_write_pir,
4704 0x00000000);
4705 /* XXX : not implemented */
4706 spr_register(env, SPR_BOOKE_SPEFSCR, "SPEFSCR",
4707 &spr_read_spefscr, &spr_write_spefscr,
4708 &spr_read_spefscr, &spr_write_spefscr,
4709 0x00000000);
4710 #if !defined(CONFIG_USER_ONLY)
4711 /* Memory management */
4712 env->nb_pids = 3;
4713 env->nb_ways = 2;
4714 env->id_tlbs = 0;
4715 switch (version) {
4716 case fsl_e500v1:
4717 tlbncfg[0] = gen_tlbncfg(2, 1, 1, 0, 256);
4718 tlbncfg[1] = gen_tlbncfg(16, 1, 9, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4719 break;
4720 case fsl_e500v2:
4721 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4722 tlbncfg[1] = gen_tlbncfg(16, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 16);
4723 break;
4724 case fsl_e500mc:
4725 case fsl_e5500:
4726 tlbncfg[0] = gen_tlbncfg(4, 1, 1, 0, 512);
4727 tlbncfg[1] = gen_tlbncfg(64, 1, 12, TLBnCFG_AVAIL | TLBnCFG_IPROT, 64);
4728 break;
4729 default:
4730 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4731 }
4732 #endif
4733 /* Cache sizes */
4734 switch (version) {
4735 case fsl_e500v1:
4736 case fsl_e500v2:
4737 env->dcache_line_size = 32;
4738 env->icache_line_size = 32;
4739 break;
4740 case fsl_e500mc:
4741 case fsl_e5500:
4742 env->dcache_line_size = 64;
4743 env->icache_line_size = 64;
4744 l1cfg0 |= 0x1000000; /* 64 byte cache block size */
4745 l1cfg1 |= 0x1000000; /* 64 byte cache block size */
4746 break;
4747 default:
4748 cpu_abort(CPU(cpu), "Unknown CPU: " TARGET_FMT_lx "\n", env->spr[SPR_PVR]);
4749 }
4750 gen_spr_BookE206(env, 0x000000DF, tlbncfg);
4751 /* XXX : not implemented */
4752 spr_register(env, SPR_HID0, "HID0",
4753 SPR_NOACCESS, SPR_NOACCESS,
4754 &spr_read_generic, &spr_write_generic,
4755 0x00000000);
4756 /* XXX : not implemented */
4757 spr_register(env, SPR_HID1, "HID1",
4758 SPR_NOACCESS, SPR_NOACCESS,
4759 &spr_read_generic, &spr_write_generic,
4760 0x00000000);
4761 /* XXX : not implemented */
4762 spr_register(env, SPR_Exxx_BBEAR, "BBEAR",
4763 SPR_NOACCESS, SPR_NOACCESS,
4764 &spr_read_generic, &spr_write_generic,
4765 0x00000000);
4766 /* XXX : not implemented */
4767 spr_register(env, SPR_Exxx_BBTAR, "BBTAR",
4768 SPR_NOACCESS, SPR_NOACCESS,
4769 &spr_read_generic, &spr_write_generic,
4770 0x00000000);
4771 /* XXX : not implemented */
4772 spr_register(env, SPR_Exxx_MCAR, "MCAR",
4773 SPR_NOACCESS, SPR_NOACCESS,
4774 &spr_read_generic, &spr_write_generic,
4775 0x00000000);
4776 /* XXX : not implemented */
4777 spr_register(env, SPR_BOOKE_MCSR, "MCSR",
4778 SPR_NOACCESS, SPR_NOACCESS,
4779 &spr_read_generic, &spr_write_generic,
4780 0x00000000);
4781 /* XXX : not implemented */
4782 spr_register(env, SPR_Exxx_NPIDR, "NPIDR",
4783 SPR_NOACCESS, SPR_NOACCESS,
4784 &spr_read_generic, &spr_write_generic,
4785 0x00000000);
4786 /* XXX : not implemented */
4787 spr_register(env, SPR_Exxx_BUCSR, "BUCSR",
4788 SPR_NOACCESS, SPR_NOACCESS,
4789 &spr_read_generic, &spr_write_generic,
4790 0x00000000);
4791 /* XXX : not implemented */
4792 spr_register(env, SPR_Exxx_L1CFG0, "L1CFG0",
4793 &spr_read_generic, SPR_NOACCESS,
4794 &spr_read_generic, SPR_NOACCESS,
4795 l1cfg0);
4796 spr_register(env, SPR_Exxx_L1CFG1, "L1CFG1",
4797 &spr_read_generic, SPR_NOACCESS,
4798 &spr_read_generic, SPR_NOACCESS,
4799 l1cfg1);
4800 spr_register(env, SPR_Exxx_L1CSR0, "L1CSR0",
4801 SPR_NOACCESS, SPR_NOACCESS,
4802 &spr_read_generic, &spr_write_e500_l1csr0,
4803 0x00000000);
4804 spr_register(env, SPR_Exxx_L1CSR1, "L1CSR1",
4805 SPR_NOACCESS, SPR_NOACCESS,
4806 &spr_read_generic, &spr_write_e500_l1csr1,
4807 0x00000000);
4808 spr_register(env, SPR_BOOKE_MCSRR0, "MCSRR0",
4809 SPR_NOACCESS, SPR_NOACCESS,
4810 &spr_read_generic, &spr_write_generic,
4811 0x00000000);
4812 spr_register(env, SPR_BOOKE_MCSRR1, "MCSRR1",
4813 SPR_NOACCESS, SPR_NOACCESS,
4814 &spr_read_generic, &spr_write_generic,
4815 0x00000000);
4816 spr_register(env, SPR_MMUCSR0, "MMUCSR0",
4817 SPR_NOACCESS, SPR_NOACCESS,
4818 &spr_read_generic, &spr_write_booke206_mmucsr0,
4819 0x00000000);
4820 spr_register(env, SPR_BOOKE_EPR, "EPR",
4821 SPR_NOACCESS, SPR_NOACCESS,
4822 &spr_read_generic, SPR_NOACCESS,
4823 0x00000000);
4824 /* XXX better abstract into Emb.xxx features */
4825 if (version == fsl_e5500) {
4826 spr_register(env, SPR_BOOKE_EPCR, "EPCR",
4827 SPR_NOACCESS, SPR_NOACCESS,
4828 &spr_read_generic, &spr_write_generic,
4829 0x00000000);
4830 spr_register(env, SPR_BOOKE_MAS7_MAS3, "MAS7_MAS3",
4831 SPR_NOACCESS, SPR_NOACCESS,
4832 &spr_read_mas73, &spr_write_mas73,
4833 0x00000000);
4834 ivpr_mask = (target_ulong)~0xFFFFULL;
4835 }
4836
4837 #if !defined(CONFIG_USER_ONLY)
4838 env->nb_tlb = 0;
4839 env->tlb_type = TLB_MAS;
4840 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
4841 env->nb_tlb += booke206_tlb_size(env, i);
4842 }
4843 #endif
4844
4845 init_excp_e200(env, ivpr_mask);
4846 /* Allocate hardware IRQ controller */
4847 ppce500_irq_init(env);
4848 }
4849
4850 static void init_proc_e500v1(CPUPPCState *env)
4851 {
4852 init_proc_e500(env, fsl_e500v1);
4853 }
4854
4855 POWERPC_FAMILY(e500v1)(ObjectClass *oc, void *data)
4856 {
4857 DeviceClass *dc = DEVICE_CLASS(oc);
4858 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4859
4860 dc->desc = "e500v1 core";
4861 pcc->init_proc = init_proc_e500v1;
4862 pcc->check_pow = check_pow_hid0;
4863 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4864 PPC_SPE | PPC_SPE_SINGLE |
4865 PPC_WRTEE | PPC_RFDI |
4866 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4867 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4868 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4869 pcc->insns_flags2 = PPC2_BOOKE206;
4870 pcc->msr_mask = (1ull << MSR_UCLE) |
4871 (1ull << MSR_SPE) |
4872 (1ull << MSR_POW) |
4873 (1ull << MSR_CE) |
4874 (1ull << MSR_EE) |
4875 (1ull << MSR_PR) |
4876 (1ull << MSR_FP) |
4877 (1ull << MSR_ME) |
4878 (1ull << MSR_FE0) |
4879 (1ull << MSR_DWE) |
4880 (1ull << MSR_DE) |
4881 (1ull << MSR_FE1) |
4882 (1ull << MSR_IR) |
4883 (1ull << MSR_DR);
4884 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4885 pcc->excp_model = POWERPC_EXCP_BOOKE;
4886 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4887 pcc->bfd_mach = bfd_mach_ppc_860;
4888 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4889 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4890 POWERPC_FLAG_BUS_CLK;
4891 }
4892
4893 static void init_proc_e500v2(CPUPPCState *env)
4894 {
4895 init_proc_e500(env, fsl_e500v2);
4896 }
4897
4898 POWERPC_FAMILY(e500v2)(ObjectClass *oc, void *data)
4899 {
4900 DeviceClass *dc = DEVICE_CLASS(oc);
4901 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4902
4903 dc->desc = "e500v2 core";
4904 pcc->init_proc = init_proc_e500v2;
4905 pcc->check_pow = check_pow_hid0;
4906 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4907 PPC_SPE | PPC_SPE_SINGLE | PPC_SPE_DOUBLE |
4908 PPC_WRTEE | PPC_RFDI |
4909 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4910 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4911 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4912 pcc->insns_flags2 = PPC2_BOOKE206;
4913 pcc->msr_mask = (1ull << MSR_UCLE) |
4914 (1ull << MSR_SPE) |
4915 (1ull << MSR_POW) |
4916 (1ull << MSR_CE) |
4917 (1ull << MSR_EE) |
4918 (1ull << MSR_PR) |
4919 (1ull << MSR_FP) |
4920 (1ull << MSR_ME) |
4921 (1ull << MSR_FE0) |
4922 (1ull << MSR_DWE) |
4923 (1ull << MSR_DE) |
4924 (1ull << MSR_FE1) |
4925 (1ull << MSR_IR) |
4926 (1ull << MSR_DR);
4927 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4928 pcc->excp_model = POWERPC_EXCP_BOOKE;
4929 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4930 pcc->bfd_mach = bfd_mach_ppc_860;
4931 pcc->flags = POWERPC_FLAG_SPE | POWERPC_FLAG_CE |
4932 POWERPC_FLAG_UBLE | POWERPC_FLAG_DE |
4933 POWERPC_FLAG_BUS_CLK;
4934 }
4935
4936 static void init_proc_e500mc(CPUPPCState *env)
4937 {
4938 init_proc_e500(env, fsl_e500mc);
4939 }
4940
4941 POWERPC_FAMILY(e500mc)(ObjectClass *oc, void *data)
4942 {
4943 DeviceClass *dc = DEVICE_CLASS(oc);
4944 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4945
4946 dc->desc = "e500mc core";
4947 pcc->init_proc = init_proc_e500mc;
4948 pcc->check_pow = check_pow_none;
4949 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4950 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4951 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4952 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4953 PPC_FLOAT | PPC_FLOAT_FRES |
4954 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
4955 PPC_FLOAT_STFIWX | PPC_WAIT |
4956 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC;
4957 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL;
4958 pcc->msr_mask = (1ull << MSR_GS) |
4959 (1ull << MSR_UCLE) |
4960 (1ull << MSR_CE) |
4961 (1ull << MSR_EE) |
4962 (1ull << MSR_PR) |
4963 (1ull << MSR_FP) |
4964 (1ull << MSR_ME) |
4965 (1ull << MSR_FE0) |
4966 (1ull << MSR_DE) |
4967 (1ull << MSR_FE1) |
4968 (1ull << MSR_IR) |
4969 (1ull << MSR_DR) |
4970 (1ull << MSR_PX) |
4971 (1ull << MSR_RI);
4972 pcc->mmu_model = POWERPC_MMU_BOOKE206;
4973 pcc->excp_model = POWERPC_EXCP_BOOKE;
4974 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
4975 /* FIXME: figure out the correct flag for e500mc */
4976 pcc->bfd_mach = bfd_mach_ppc_e500;
4977 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
4978 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
4979 }
4980
4981 #ifdef TARGET_PPC64
4982 static void init_proc_e5500(CPUPPCState *env)
4983 {
4984 init_proc_e500(env, fsl_e5500);
4985 }
4986
4987 POWERPC_FAMILY(e5500)(ObjectClass *oc, void *data)
4988 {
4989 DeviceClass *dc = DEVICE_CLASS(oc);
4990 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
4991
4992 dc->desc = "e5500 core";
4993 pcc->init_proc = init_proc_e5500;
4994 pcc->check_pow = check_pow_none;
4995 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL |
4996 PPC_WRTEE | PPC_RFDI | PPC_RFMCI |
4997 PPC_CACHE | PPC_CACHE_LOCK | PPC_CACHE_ICBI |
4998 PPC_CACHE_DCBZ | PPC_CACHE_DCBA |
4999 PPC_FLOAT | PPC_FLOAT_FRES |
5000 PPC_FLOAT_FRSQRTE | PPC_FLOAT_FSEL |
5001 PPC_FLOAT_STFIWX | PPC_WAIT |
5002 PPC_MEM_TLBSYNC | PPC_TLBIVAX | PPC_MEM_SYNC |
5003 PPC_64B | PPC_POPCNTB | PPC_POPCNTWD;
5004 pcc->insns_flags2 = PPC2_BOOKE206 | PPC2_PRCNTL | PPC2_PERM_ISA206;
5005 pcc->msr_mask = (1ull << MSR_CM) |
5006 (1ull << MSR_GS) |
5007 (1ull << MSR_UCLE) |
5008 (1ull << MSR_CE) |
5009 (1ull << MSR_EE) |
5010 (1ull << MSR_PR) |
5011 (1ull << MSR_FP) |
5012 (1ull << MSR_ME) |
5013 (1ull << MSR_FE0) |
5014 (1ull << MSR_DE) |
5015 (1ull << MSR_FE1) |
5016 (1ull << MSR_IR) |
5017 (1ull << MSR_DR) |
5018 (1ull << MSR_PX) |
5019 (1ull << MSR_RI);
5020 pcc->mmu_model = POWERPC_MMU_BOOKE206;
5021 pcc->excp_model = POWERPC_EXCP_BOOKE;
5022 pcc->bus_model = PPC_FLAGS_INPUT_BookE;
5023 /* FIXME: figure out the correct flag for e5500 */
5024 pcc->bfd_mach = bfd_mach_ppc_e500;
5025 pcc->flags = POWERPC_FLAG_CE | POWERPC_FLAG_DE |
5026 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5027 }
5028 #endif
5029
5030 /* Non-embedded PowerPC */
5031
5032 /* POWER : same as 601, without mfmsr, mfsr */
5033 POWERPC_FAMILY(POWER)(ObjectClass *oc, void *data)
5034 {
5035 DeviceClass *dc = DEVICE_CLASS(oc);
5036 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5037
5038 dc->desc = "POWER";
5039 /* pcc->insns_flags = XXX_TODO; */
5040 /* POWER RSC (from RAD6000) */
5041 pcc->msr_mask = (1ull << MSR_EE) |
5042 (1ull << MSR_PR) |
5043 (1ull << MSR_FP) |
5044 (1ull << MSR_ME) |
5045 (1ull << MSR_FE0) |
5046 (1ull << MSR_SE) |
5047 (1ull << MSR_DE) |
5048 (1ull << MSR_AL) |
5049 (1ull << MSR_EP) |
5050 (1ull << MSR_IR) |
5051 (1ull << MSR_DR);
5052 }
5053
5054 #define POWERPC_MSRR_601 (0x0000000000001040ULL)
5055
5056 static void init_proc_601 (CPUPPCState *env)
5057 {
5058 gen_spr_ne_601(env);
5059 gen_spr_601(env);
5060 /* Hardware implementation registers */
5061 /* XXX : not implemented */
5062 spr_register(env, SPR_HID0, "HID0",
5063 SPR_NOACCESS, SPR_NOACCESS,
5064 &spr_read_generic, &spr_write_hid0_601,
5065 0x80010080);
5066 /* XXX : not implemented */
5067 spr_register(env, SPR_HID1, "HID1",
5068 SPR_NOACCESS, SPR_NOACCESS,
5069 &spr_read_generic, &spr_write_generic,
5070 0x00000000);
5071 /* XXX : not implemented */
5072 spr_register(env, SPR_601_HID2, "HID2",
5073 SPR_NOACCESS, SPR_NOACCESS,
5074 &spr_read_generic, &spr_write_generic,
5075 0x00000000);
5076 /* XXX : not implemented */
5077 spr_register(env, SPR_601_HID5, "HID5",
5078 SPR_NOACCESS, SPR_NOACCESS,
5079 &spr_read_generic, &spr_write_generic,
5080 0x00000000);
5081 /* Memory management */
5082 init_excp_601(env);
5083 /* XXX: beware that dcache line size is 64
5084 * but dcbz uses 32 bytes "sectors"
5085 * XXX: this breaks clcs instruction !
5086 */
5087 env->dcache_line_size = 32;
5088 env->icache_line_size = 64;
5089 /* Allocate hardware IRQ controller */
5090 ppc6xx_irq_init(env);
5091 }
5092
5093 POWERPC_FAMILY(601)(ObjectClass *oc, void *data)
5094 {
5095 DeviceClass *dc = DEVICE_CLASS(oc);
5096 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5097
5098 dc->desc = "PowerPC 601";
5099 pcc->init_proc = init_proc_601;
5100 pcc->check_pow = check_pow_none;
5101 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5102 PPC_FLOAT |
5103 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5104 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5105 PPC_SEGMENT | PPC_EXTERN;
5106 pcc->msr_mask = (1ull << MSR_EE) |
5107 (1ull << MSR_PR) |
5108 (1ull << MSR_FP) |
5109 (1ull << MSR_ME) |
5110 (1ull << MSR_FE0) |
5111 (1ull << MSR_SE) |
5112 (1ull << MSR_FE1) |
5113 (1ull << MSR_EP) |
5114 (1ull << MSR_IR) |
5115 (1ull << MSR_DR);
5116 pcc->mmu_model = POWERPC_MMU_601;
5117 #if defined(CONFIG_SOFTMMU)
5118 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5119 #endif
5120 pcc->excp_model = POWERPC_EXCP_601;
5121 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5122 pcc->bfd_mach = bfd_mach_ppc_601;
5123 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5124 }
5125
5126 #define POWERPC_MSRR_601v (0x0000000000001040ULL)
5127
5128 static void init_proc_601v (CPUPPCState *env)
5129 {
5130 init_proc_601(env);
5131 /* XXX : not implemented */
5132 spr_register(env, SPR_601_HID15, "HID15",
5133 SPR_NOACCESS, SPR_NOACCESS,
5134 &spr_read_generic, &spr_write_generic,
5135 0x00000000);
5136 }
5137
5138 POWERPC_FAMILY(601v)(ObjectClass *oc, void *data)
5139 {
5140 DeviceClass *dc = DEVICE_CLASS(oc);
5141 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5142
5143 dc->desc = "PowerPC 601v";
5144 pcc->init_proc = init_proc_601v;
5145 pcc->check_pow = check_pow_none;
5146 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_POWER_BR |
5147 PPC_FLOAT |
5148 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5149 PPC_MEM_SYNC | PPC_MEM_EIEIO | PPC_MEM_TLBIE |
5150 PPC_SEGMENT | PPC_EXTERN;
5151 pcc->msr_mask = (1ull << MSR_EE) |
5152 (1ull << MSR_PR) |
5153 (1ull << MSR_FP) |
5154 (1ull << MSR_ME) |
5155 (1ull << MSR_FE0) |
5156 (1ull << MSR_SE) |
5157 (1ull << MSR_FE1) |
5158 (1ull << MSR_EP) |
5159 (1ull << MSR_IR) |
5160 (1ull << MSR_DR);
5161 pcc->mmu_model = POWERPC_MMU_601;
5162 #if defined(CONFIG_SOFTMMU)
5163 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5164 #endif
5165 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5166 pcc->bfd_mach = bfd_mach_ppc_601;
5167 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_RTC_CLK;
5168 }
5169
5170 static void init_proc_602 (CPUPPCState *env)
5171 {
5172 gen_spr_ne_601(env);
5173 gen_spr_602(env);
5174 /* Time base */
5175 gen_tbl(env);
5176 /* hardware implementation registers */
5177 /* XXX : not implemented */
5178 spr_register(env, SPR_HID0, "HID0",
5179 SPR_NOACCESS, SPR_NOACCESS,
5180 &spr_read_generic, &spr_write_generic,
5181 0x00000000);
5182 /* XXX : not implemented */
5183 spr_register(env, SPR_HID1, "HID1",
5184 SPR_NOACCESS, SPR_NOACCESS,
5185 &spr_read_generic, &spr_write_generic,
5186 0x00000000);
5187 /* Memory management */
5188 gen_low_BATs(env);
5189 gen_6xx_7xx_soft_tlb(env, 64, 2);
5190 init_excp_602(env);
5191 env->dcache_line_size = 32;
5192 env->icache_line_size = 32;
5193 /* Allocate hardware IRQ controller */
5194 ppc6xx_irq_init(env);
5195 }
5196
5197 POWERPC_FAMILY(602)(ObjectClass *oc, void *data)
5198 {
5199 DeviceClass *dc = DEVICE_CLASS(oc);
5200 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5201
5202 dc->desc = "PowerPC 602";
5203 pcc->init_proc = init_proc_602;
5204 pcc->check_pow = check_pow_hid0;
5205 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5206 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5207 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5208 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5209 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5210 PPC_MEM_TLBIE | PPC_6xx_TLB | PPC_MEM_TLBSYNC |
5211 PPC_SEGMENT | PPC_602_SPEC;
5212 pcc->msr_mask = (1ull << MSR_VSX) |
5213 (1ull << MSR_SA) |
5214 (1ull << MSR_POW) |
5215 (1ull << MSR_TGPR) |
5216 (1ull << MSR_ILE) |
5217 (1ull << MSR_EE) |
5218 (1ull << MSR_PR) |
5219 (1ull << MSR_FP) |
5220 (1ull << MSR_ME) |
5221 (1ull << MSR_FE0) |
5222 (1ull << MSR_SE) |
5223 (1ull << MSR_DE) |
5224 (1ull << MSR_FE1) |
5225 (1ull << MSR_EP) |
5226 (1ull << MSR_IR) |
5227 (1ull << MSR_DR) |
5228 (1ull << MSR_RI) |
5229 (1ull << MSR_LE);
5230 /* XXX: 602 MMU is quite specific. Should add a special case */
5231 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5232 pcc->excp_model = POWERPC_EXCP_602;
5233 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5234 pcc->bfd_mach = bfd_mach_ppc_602;
5235 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5236 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5237 }
5238
5239 static void init_proc_603 (CPUPPCState *env)
5240 {
5241 gen_spr_ne_601(env);
5242 gen_spr_603(env);
5243 /* Time base */
5244 gen_tbl(env);
5245 /* hardware implementation registers */
5246 /* XXX : not implemented */
5247 spr_register(env, SPR_HID0, "HID0",
5248 SPR_NOACCESS, SPR_NOACCESS,
5249 &spr_read_generic, &spr_write_generic,
5250 0x00000000);
5251 /* XXX : not implemented */
5252 spr_register(env, SPR_HID1, "HID1",
5253 SPR_NOACCESS, SPR_NOACCESS,
5254 &spr_read_generic, &spr_write_generic,
5255 0x00000000);
5256 /* Memory management */
5257 gen_low_BATs(env);
5258 gen_6xx_7xx_soft_tlb(env, 64, 2);
5259 init_excp_603(env);
5260 env->dcache_line_size = 32;
5261 env->icache_line_size = 32;
5262 /* Allocate hardware IRQ controller */
5263 ppc6xx_irq_init(env);
5264 }
5265
5266 POWERPC_FAMILY(603)(ObjectClass *oc, void *data)
5267 {
5268 DeviceClass *dc = DEVICE_CLASS(oc);
5269 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5270
5271 dc->desc = "PowerPC 603";
5272 pcc->init_proc = init_proc_603;
5273 pcc->check_pow = check_pow_hid0;
5274 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5275 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5276 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5277 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5278 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5279 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5280 PPC_SEGMENT | PPC_EXTERN;
5281 pcc->msr_mask = (1ull << MSR_POW) |
5282 (1ull << MSR_TGPR) |
5283 (1ull << MSR_ILE) |
5284 (1ull << MSR_EE) |
5285 (1ull << MSR_PR) |
5286 (1ull << MSR_FP) |
5287 (1ull << MSR_ME) |
5288 (1ull << MSR_FE0) |
5289 (1ull << MSR_SE) |
5290 (1ull << MSR_DE) |
5291 (1ull << MSR_FE1) |
5292 (1ull << MSR_EP) |
5293 (1ull << MSR_IR) |
5294 (1ull << MSR_DR) |
5295 (1ull << MSR_RI) |
5296 (1ull << MSR_LE);
5297 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5298 pcc->excp_model = POWERPC_EXCP_603;
5299 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5300 pcc->bfd_mach = bfd_mach_ppc_603;
5301 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5302 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5303 }
5304
5305 static void init_proc_603E (CPUPPCState *env)
5306 {
5307 gen_spr_ne_601(env);
5308 gen_spr_603(env);
5309 /* Time base */
5310 gen_tbl(env);
5311 /* hardware implementation registers */
5312 /* XXX : not implemented */
5313 spr_register(env, SPR_HID0, "HID0",
5314 SPR_NOACCESS, SPR_NOACCESS,
5315 &spr_read_generic, &spr_write_generic,
5316 0x00000000);
5317 /* XXX : not implemented */
5318 spr_register(env, SPR_HID1, "HID1",
5319 SPR_NOACCESS, SPR_NOACCESS,
5320 &spr_read_generic, &spr_write_generic,
5321 0x00000000);
5322 /* Memory management */
5323 gen_low_BATs(env);
5324 gen_6xx_7xx_soft_tlb(env, 64, 2);
5325 init_excp_603(env);
5326 env->dcache_line_size = 32;
5327 env->icache_line_size = 32;
5328 /* Allocate hardware IRQ controller */
5329 ppc6xx_irq_init(env);
5330 }
5331
5332 POWERPC_FAMILY(603E)(ObjectClass *oc, void *data)
5333 {
5334 DeviceClass *dc = DEVICE_CLASS(oc);
5335 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5336
5337 dc->desc = "PowerPC 603e";
5338 pcc->init_proc = init_proc_603E;
5339 pcc->check_pow = check_pow_hid0;
5340 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5341 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5342 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5343 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5344 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5345 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
5346 PPC_SEGMENT | PPC_EXTERN;
5347 pcc->msr_mask = (1ull << MSR_POW) |
5348 (1ull << MSR_TGPR) |
5349 (1ull << MSR_ILE) |
5350 (1ull << MSR_EE) |
5351 (1ull << MSR_PR) |
5352 (1ull << MSR_FP) |
5353 (1ull << MSR_ME) |
5354 (1ull << MSR_FE0) |
5355 (1ull << MSR_SE) |
5356 (1ull << MSR_DE) |
5357 (1ull << MSR_FE1) |
5358 (1ull << MSR_EP) |
5359 (1ull << MSR_IR) |
5360 (1ull << MSR_DR) |
5361 (1ull << MSR_RI) |
5362 (1ull << MSR_LE);
5363 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
5364 pcc->excp_model = POWERPC_EXCP_603E;
5365 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5366 pcc->bfd_mach = bfd_mach_ppc_ec603e;
5367 pcc->flags = POWERPC_FLAG_TGPR | POWERPC_FLAG_SE |
5368 POWERPC_FLAG_BE | POWERPC_FLAG_BUS_CLK;
5369 }
5370
5371 static void init_proc_604 (CPUPPCState *env)
5372 {
5373 gen_spr_ne_601(env);
5374 gen_spr_604(env);
5375 /* Time base */
5376 gen_tbl(env);
5377 /* Hardware implementation registers */
5378 /* XXX : not implemented */
5379 spr_register(env, SPR_HID0, "HID0",
5380 SPR_NOACCESS, SPR_NOACCESS,
5381 &spr_read_generic, &spr_write_generic,
5382 0x00000000);
5383 /* Memory management */
5384 gen_low_BATs(env);
5385 init_excp_604(env);
5386 env->dcache_line_size = 32;
5387 env->icache_line_size = 32;
5388 /* Allocate hardware IRQ controller */
5389 ppc6xx_irq_init(env);
5390 }
5391
5392 POWERPC_FAMILY(604)(ObjectClass *oc, void *data)
5393 {
5394 DeviceClass *dc = DEVICE_CLASS(oc);
5395 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5396
5397 dc->desc = "PowerPC 604";
5398 pcc->init_proc = init_proc_604;
5399 pcc->check_pow = check_pow_nocheck;
5400 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5401 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5402 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5403 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5404 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5405 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5406 PPC_SEGMENT | PPC_EXTERN;
5407 pcc->msr_mask = (1ull << MSR_POW) |
5408 (1ull << MSR_ILE) |
5409 (1ull << MSR_EE) |
5410 (1ull << MSR_PR) |
5411 (1ull << MSR_FP) |
5412 (1ull << MSR_ME) |
5413 (1ull << MSR_FE0) |
5414 (1ull << MSR_SE) |
5415 (1ull << MSR_DE) |
5416 (1ull << MSR_FE1) |
5417 (1ull << MSR_EP) |
5418 (1ull << MSR_IR) |
5419 (1ull << MSR_DR) |
5420 (1ull << MSR_PMM) |
5421 (1ull << MSR_RI) |
5422 (1ull << MSR_LE);
5423 pcc->mmu_model = POWERPC_MMU_32B;
5424 #if defined(CONFIG_SOFTMMU)
5425 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5426 #endif
5427 pcc->excp_model = POWERPC_EXCP_604;
5428 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5429 pcc->bfd_mach = bfd_mach_ppc_604;
5430 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5431 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5432 }
5433
5434 static void init_proc_604E (CPUPPCState *env)
5435 {
5436 gen_spr_ne_601(env);
5437 gen_spr_604(env);
5438 /* XXX : not implemented */
5439 spr_register(env, SPR_MMCR1, "MMCR1",
5440 SPR_NOACCESS, SPR_NOACCESS,
5441 &spr_read_generic, &spr_write_generic,
5442 0x00000000);
5443 /* XXX : not implemented */
5444 spr_register(env, SPR_PMC3, "PMC3",
5445 SPR_NOACCESS, SPR_NOACCESS,
5446 &spr_read_generic, &spr_write_generic,
5447 0x00000000);
5448 /* XXX : not implemented */
5449 spr_register(env, SPR_PMC4, "PMC4",
5450 SPR_NOACCESS, SPR_NOACCESS,
5451 &spr_read_generic, &spr_write_generic,
5452 0x00000000);
5453 /* Time base */
5454 gen_tbl(env);
5455 /* Hardware implementation registers */
5456 /* XXX : not implemented */
5457 spr_register(env, SPR_HID0, "HID0",
5458 SPR_NOACCESS, SPR_NOACCESS,
5459 &spr_read_generic, &spr_write_generic,
5460 0x00000000);
5461 /* XXX : not implemented */
5462 spr_register(env, SPR_HID1, "HID1",
5463 SPR_NOACCESS, SPR_NOACCESS,
5464 &spr_read_generic, &spr_write_generic,
5465 0x00000000);
5466 /* Memory management */
5467 gen_low_BATs(env);
5468 init_excp_604(env);
5469 env->dcache_line_size = 32;
5470 env->icache_line_size = 32;
5471 /* Allocate hardware IRQ controller */
5472 ppc6xx_irq_init(env);
5473 }
5474
5475 POWERPC_FAMILY(604E)(ObjectClass *oc, void *data)
5476 {
5477 DeviceClass *dc = DEVICE_CLASS(oc);
5478 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5479
5480 dc->desc = "PowerPC 604E";
5481 pcc->init_proc = init_proc_604E;
5482 pcc->check_pow = check_pow_nocheck;
5483 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5484 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5485 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5486 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5487 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5488 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5489 PPC_SEGMENT | PPC_EXTERN;
5490 pcc->msr_mask = (1ull << MSR_POW) |
5491 (1ull << MSR_ILE) |
5492 (1ull << MSR_EE) |
5493 (1ull << MSR_PR) |
5494 (1ull << MSR_FP) |
5495 (1ull << MSR_ME) |
5496 (1ull << MSR_FE0) |
5497 (1ull << MSR_SE) |
5498 (1ull << MSR_DE) |
5499 (1ull << MSR_FE1) |
5500 (1ull << MSR_EP) |
5501 (1ull << MSR_IR) |
5502 (1ull << MSR_DR) |
5503 (1ull << MSR_PMM) |
5504 (1ull << MSR_RI) |
5505 (1ull << MSR_LE);
5506 pcc->mmu_model = POWERPC_MMU_32B;
5507 #if defined(CONFIG_SOFTMMU)
5508 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5509 #endif
5510 pcc->excp_model = POWERPC_EXCP_604;
5511 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5512 pcc->bfd_mach = bfd_mach_ppc_604;
5513 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5514 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5515 }
5516
5517 static void init_proc_740 (CPUPPCState *env)
5518 {
5519 gen_spr_ne_601(env);
5520 gen_spr_7xx(env);
5521 /* Time base */
5522 gen_tbl(env);
5523 /* Thermal management */
5524 gen_spr_thrm(env);
5525 /* Hardware implementation registers */
5526 /* XXX : not implemented */
5527 spr_register(env, SPR_HID0, "HID0",
5528 SPR_NOACCESS, SPR_NOACCESS,
5529 &spr_read_generic, &spr_write_generic,
5530 0x00000000);
5531 /* XXX : not implemented */
5532 spr_register(env, SPR_HID1, "HID1",
5533 SPR_NOACCESS, SPR_NOACCESS,
5534 &spr_read_generic, &spr_write_generic,
5535 0x00000000);
5536 /* Memory management */
5537 gen_low_BATs(env);
5538 init_excp_7x0(env);
5539 env->dcache_line_size = 32;
5540 env->icache_line_size = 32;
5541 /* Allocate hardware IRQ controller */
5542 ppc6xx_irq_init(env);
5543 }
5544
5545 POWERPC_FAMILY(740)(ObjectClass *oc, void *data)
5546 {
5547 DeviceClass *dc = DEVICE_CLASS(oc);
5548 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5549
5550 dc->desc = "PowerPC 740";
5551 pcc->init_proc = init_proc_740;
5552 pcc->check_pow = check_pow_hid0;
5553 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5554 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5555 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5556 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5557 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5558 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5559 PPC_SEGMENT | PPC_EXTERN;
5560 pcc->msr_mask = (1ull << MSR_POW) |
5561 (1ull << MSR_ILE) |
5562 (1ull << MSR_EE) |
5563 (1ull << MSR_PR) |
5564 (1ull << MSR_FP) |
5565 (1ull << MSR_ME) |
5566 (1ull << MSR_FE0) |
5567 (1ull << MSR_SE) |
5568 (1ull << MSR_DE) |
5569 (1ull << MSR_FE1) |
5570 (1ull << MSR_EP) |
5571 (1ull << MSR_IR) |
5572 (1ull << MSR_DR) |
5573 (1ull << MSR_PMM) |
5574 (1ull << MSR_RI) |
5575 (1ull << MSR_LE);
5576 pcc->mmu_model = POWERPC_MMU_32B;
5577 #if defined(CONFIG_SOFTMMU)
5578 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5579 #endif
5580 pcc->excp_model = POWERPC_EXCP_7x0;
5581 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5582 pcc->bfd_mach = bfd_mach_ppc_750;
5583 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5584 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5585 }
5586
5587 static void init_proc_750 (CPUPPCState *env)
5588 {
5589 gen_spr_ne_601(env);
5590 gen_spr_7xx(env);
5591 /* XXX : not implemented */
5592 spr_register(env, SPR_L2CR, "L2CR",
5593 SPR_NOACCESS, SPR_NOACCESS,
5594 &spr_read_generic, spr_access_nop,
5595 0x00000000);
5596 /* Time base */
5597 gen_tbl(env);
5598 /* Thermal management */
5599 gen_spr_thrm(env);
5600 /* Hardware implementation registers */
5601 /* XXX : not implemented */
5602 spr_register(env, SPR_HID0, "HID0",
5603 SPR_NOACCESS, SPR_NOACCESS,
5604 &spr_read_generic, &spr_write_generic,
5605 0x00000000);
5606 /* XXX : not implemented */
5607 spr_register(env, SPR_HID1, "HID1",
5608 SPR_NOACCESS, SPR_NOACCESS,
5609 &spr_read_generic, &spr_write_generic,
5610 0x00000000);
5611 /* Memory management */
5612 gen_low_BATs(env);
5613 /* XXX: high BATs are also present but are known to be bugged on
5614 * die version 1.x
5615 */
5616 init_excp_7x0(env);
5617 env->dcache_line_size = 32;
5618 env->icache_line_size = 32;
5619 /* Allocate hardware IRQ controller */
5620 ppc6xx_irq_init(env);
5621 }
5622
5623 POWERPC_FAMILY(750)(ObjectClass *oc, void *data)
5624 {
5625 DeviceClass *dc = DEVICE_CLASS(oc);
5626 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5627
5628 dc->desc = "PowerPC 750";
5629 pcc->init_proc = init_proc_750;
5630 pcc->check_pow = check_pow_hid0;
5631 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5632 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5633 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5634 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5635 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5636 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5637 PPC_SEGMENT | PPC_EXTERN;
5638 pcc->msr_mask = (1ull << MSR_POW) |
5639 (1ull << MSR_ILE) |
5640 (1ull << MSR_EE) |
5641 (1ull << MSR_PR) |
5642 (1ull << MSR_FP) |
5643 (1ull << MSR_ME) |
5644 (1ull << MSR_FE0) |
5645 (1ull << MSR_SE) |
5646 (1ull << MSR_DE) |
5647 (1ull << MSR_FE1) |
5648 (1ull << MSR_EP) |
5649 (1ull << MSR_IR) |
5650 (1ull << MSR_DR) |
5651 (1ull << MSR_PMM) |
5652 (1ull << MSR_RI) |
5653 (1ull << MSR_LE);
5654 pcc->mmu_model = POWERPC_MMU_32B;
5655 #if defined(CONFIG_SOFTMMU)
5656 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5657 #endif
5658 pcc->excp_model = POWERPC_EXCP_7x0;
5659 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5660 pcc->bfd_mach = bfd_mach_ppc_750;
5661 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5662 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5663 }
5664
5665 static void init_proc_750cl (CPUPPCState *env)
5666 {
5667 gen_spr_ne_601(env);
5668 gen_spr_7xx(env);
5669 /* XXX : not implemented */
5670 spr_register(env, SPR_L2CR, "L2CR",
5671 SPR_NOACCESS, SPR_NOACCESS,
5672 &spr_read_generic, spr_access_nop,
5673 0x00000000);
5674 /* Time base */
5675 gen_tbl(env);
5676 /* Thermal management */
5677 /* Those registers are fake on 750CL */
5678 spr_register(env, SPR_THRM1, "THRM1",
5679 SPR_NOACCESS, SPR_NOACCESS,
5680 &spr_read_generic, &spr_write_generic,
5681 0x00000000);
5682 spr_register(env, SPR_THRM2, "THRM2",
5683 SPR_NOACCESS, SPR_NOACCESS,
5684 &spr_read_generic, &spr_write_generic,
5685 0x00000000);
5686 spr_register(env, SPR_THRM3, "THRM3",
5687 SPR_NOACCESS, SPR_NOACCESS,
5688 &spr_read_generic, &spr_write_generic,
5689 0x00000000);
5690 /* XXX: not implemented */
5691 spr_register(env, SPR_750_TDCL, "TDCL",
5692 SPR_NOACCESS, SPR_NOACCESS,
5693 &spr_read_generic, &spr_write_generic,
5694 0x00000000);
5695 spr_register(env, SPR_750_TDCH, "TDCH",
5696 SPR_NOACCESS, SPR_NOACCESS,
5697 &spr_read_generic, &spr_write_generic,
5698 0x00000000);
5699 /* DMA */
5700 /* XXX : not implemented */
5701 spr_register(env, SPR_750_WPAR, "WPAR",
5702 SPR_NOACCESS, SPR_NOACCESS,
5703 &spr_read_generic, &spr_write_generic,
5704 0x00000000);
5705 spr_register(env, SPR_750_DMAL, "DMAL",
5706 SPR_NOACCESS, SPR_NOACCESS,
5707 &spr_read_generic, &spr_write_generic,
5708 0x00000000);
5709 spr_register(env, SPR_750_DMAU, "DMAU",
5710 SPR_NOACCESS, SPR_NOACCESS,
5711 &spr_read_generic, &spr_write_generic,
5712 0x00000000);
5713 /* Hardware implementation registers */
5714 /* XXX : not implemented */
5715 spr_register(env, SPR_HID0, "HID0",
5716 SPR_NOACCESS, SPR_NOACCESS,
5717 &spr_read_generic, &spr_write_generic,
5718 0x00000000);
5719 /* XXX : not implemented */
5720 spr_register(env, SPR_HID1, "HID1",
5721 SPR_NOACCESS, SPR_NOACCESS,
5722 &spr_read_generic, &spr_write_generic,
5723 0x00000000);
5724 /* XXX : not implemented */
5725 spr_register(env, SPR_750CL_HID2, "HID2",
5726 SPR_NOACCESS, SPR_NOACCESS,
5727 &spr_read_generic, &spr_write_generic,
5728 0x00000000);
5729 /* XXX : not implemented */
5730 spr_register(env, SPR_750CL_HID4, "HID4",
5731 SPR_NOACCESS, SPR_NOACCESS,
5732 &spr_read_generic, &spr_write_generic,
5733 0x00000000);
5734 /* Quantization registers */
5735 /* XXX : not implemented */
5736 spr_register(env, SPR_750_GQR0, "GQR0",
5737 SPR_NOACCESS, SPR_NOACCESS,
5738 &spr_read_generic, &spr_write_generic,
5739 0x00000000);
5740 /* XXX : not implemented */
5741 spr_register(env, SPR_750_GQR1, "GQR1",
5742 SPR_NOACCESS, SPR_NOACCESS,
5743 &spr_read_generic, &spr_write_generic,
5744 0x00000000);
5745 /* XXX : not implemented */
5746 spr_register(env, SPR_750_GQR2, "GQR2",
5747 SPR_NOACCESS, SPR_NOACCESS,
5748 &spr_read_generic, &spr_write_generic,
5749 0x00000000);
5750 /* XXX : not implemented */
5751 spr_register(env, SPR_750_GQR3, "GQR3",
5752 SPR_NOACCESS, SPR_NOACCESS,
5753 &spr_read_generic, &spr_write_generic,
5754 0x00000000);
5755 /* XXX : not implemented */
5756 spr_register(env, SPR_750_GQR4, "GQR4",
5757 SPR_NOACCESS, SPR_NOACCESS,
5758 &spr_read_generic, &spr_write_generic,
5759 0x00000000);
5760 /* XXX : not implemented */
5761 spr_register(env, SPR_750_GQR5, "GQR5",
5762 SPR_NOACCESS, SPR_NOACCESS,
5763 &spr_read_generic, &spr_write_generic,
5764 0x00000000);
5765 /* XXX : not implemented */
5766 spr_register(env, SPR_750_GQR6, "GQR6",
5767 SPR_NOACCESS, SPR_NOACCESS,
5768 &spr_read_generic, &spr_write_generic,
5769 0x00000000);
5770 /* XXX : not implemented */
5771 spr_register(env, SPR_750_GQR7, "GQR7",
5772 SPR_NOACCESS, SPR_NOACCESS,
5773 &spr_read_generic, &spr_write_generic,
5774 0x00000000);
5775 /* Memory management */
5776 gen_low_BATs(env);
5777 /* PowerPC 750cl has 8 DBATs and 8 IBATs */
5778 gen_high_BATs(env);
5779 init_excp_750cl(env);
5780 env->dcache_line_size = 32;
5781 env->icache_line_size = 32;
5782 /* Allocate hardware IRQ controller */
5783 ppc6xx_irq_init(env);
5784 }
5785
5786 POWERPC_FAMILY(750cl)(ObjectClass *oc, void *data)
5787 {
5788 DeviceClass *dc = DEVICE_CLASS(oc);
5789 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5790
5791 dc->desc = "PowerPC 750 CL";
5792 pcc->init_proc = init_proc_750cl;
5793 pcc->check_pow = check_pow_hid0;
5794 /* XXX: not implemented:
5795 * cache lock instructions:
5796 * dcbz_l
5797 * floating point paired instructions
5798 * psq_lux
5799 * psq_lx
5800 * psq_stux
5801 * psq_stx
5802 * ps_abs
5803 * ps_add
5804 * ps_cmpo0
5805 * ps_cmpo1
5806 * ps_cmpu0
5807 * ps_cmpu1
5808 * ps_div
5809 * ps_madd
5810 * ps_madds0
5811 * ps_madds1
5812 * ps_merge00
5813 * ps_merge01
5814 * ps_merge10
5815 * ps_merge11
5816 * ps_mr
5817 * ps_msub
5818 * ps_mul
5819 * ps_muls0
5820 * ps_muls1
5821 * ps_nabs
5822 * ps_neg
5823 * ps_nmadd
5824 * ps_nmsub
5825 * ps_res
5826 * ps_rsqrte
5827 * ps_sel
5828 * ps_sub
5829 * ps_sum0
5830 * ps_sum1
5831 */
5832 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5833 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5834 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5835 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5836 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5837 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5838 PPC_SEGMENT | PPC_EXTERN;
5839 pcc->msr_mask = (1ull << MSR_POW) |
5840 (1ull << MSR_ILE) |
5841 (1ull << MSR_EE) |
5842 (1ull << MSR_PR) |
5843 (1ull << MSR_FP) |
5844 (1ull << MSR_ME) |
5845 (1ull << MSR_FE0) |
5846 (1ull << MSR_SE) |
5847 (1ull << MSR_DE) |
5848 (1ull << MSR_FE1) |
5849 (1ull << MSR_EP) |
5850 (1ull << MSR_IR) |
5851 (1ull << MSR_DR) |
5852 (1ull << MSR_PMM) |
5853 (1ull << MSR_RI) |
5854 (1ull << MSR_LE);
5855 pcc->mmu_model = POWERPC_MMU_32B;
5856 #if defined(CONFIG_SOFTMMU)
5857 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5858 #endif
5859 pcc->excp_model = POWERPC_EXCP_7x0;
5860 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5861 pcc->bfd_mach = bfd_mach_ppc_750;
5862 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5863 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5864 }
5865
5866 static void init_proc_750cx (CPUPPCState *env)
5867 {
5868 gen_spr_ne_601(env);
5869 gen_spr_7xx(env);
5870 /* XXX : not implemented */
5871 spr_register(env, SPR_L2CR, "L2CR",
5872 SPR_NOACCESS, SPR_NOACCESS,
5873 &spr_read_generic, spr_access_nop,
5874 0x00000000);
5875 /* Time base */
5876 gen_tbl(env);
5877 /* Thermal management */
5878 gen_spr_thrm(env);
5879 /* This register is not implemented but is present for compatibility */
5880 spr_register(env, SPR_SDA, "SDA",
5881 SPR_NOACCESS, SPR_NOACCESS,
5882 &spr_read_generic, &spr_write_generic,
5883 0x00000000);
5884 /* Hardware implementation registers */
5885 /* XXX : not implemented */
5886 spr_register(env, SPR_HID0, "HID0",
5887 SPR_NOACCESS, SPR_NOACCESS,
5888 &spr_read_generic, &spr_write_generic,
5889 0x00000000);
5890 /* XXX : not implemented */
5891 spr_register(env, SPR_HID1, "HID1",
5892 SPR_NOACCESS, SPR_NOACCESS,
5893 &spr_read_generic, &spr_write_generic,
5894 0x00000000);
5895 /* Memory management */
5896 gen_low_BATs(env);
5897 /* PowerPC 750cx has 8 DBATs and 8 IBATs */
5898 gen_high_BATs(env);
5899 init_excp_750cx(env);
5900 env->dcache_line_size = 32;
5901 env->icache_line_size = 32;
5902 /* Allocate hardware IRQ controller */
5903 ppc6xx_irq_init(env);
5904 }
5905
5906 POWERPC_FAMILY(750cx)(ObjectClass *oc, void *data)
5907 {
5908 DeviceClass *dc = DEVICE_CLASS(oc);
5909 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5910
5911 dc->desc = "PowerPC 750CX";
5912 pcc->init_proc = init_proc_750cx;
5913 pcc->check_pow = check_pow_hid0;
5914 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
5915 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
5916 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
5917 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
5918 PPC_MEM_SYNC | PPC_MEM_EIEIO |
5919 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
5920 PPC_SEGMENT | PPC_EXTERN;
5921 pcc->msr_mask = (1ull << MSR_POW) |
5922 (1ull << MSR_ILE) |
5923 (1ull << MSR_EE) |
5924 (1ull << MSR_PR) |
5925 (1ull << MSR_FP) |
5926 (1ull << MSR_ME) |
5927 (1ull << MSR_FE0) |
5928 (1ull << MSR_SE) |
5929 (1ull << MSR_DE) |
5930 (1ull << MSR_FE1) |
5931 (1ull << MSR_EP) |
5932 (1ull << MSR_IR) |
5933 (1ull << MSR_DR) |
5934 (1ull << MSR_PMM) |
5935 (1ull << MSR_RI) |
5936 (1ull << MSR_LE);
5937 pcc->mmu_model = POWERPC_MMU_32B;
5938 #if defined(CONFIG_SOFTMMU)
5939 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
5940 #endif
5941 pcc->excp_model = POWERPC_EXCP_7x0;
5942 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
5943 pcc->bfd_mach = bfd_mach_ppc_750;
5944 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
5945 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
5946 }
5947
5948 static void init_proc_750fx (CPUPPCState *env)
5949 {
5950 gen_spr_ne_601(env);
5951 gen_spr_7xx(env);
5952 /* XXX : not implemented */
5953 spr_register(env, SPR_L2CR, "L2CR",
5954 SPR_NOACCESS, SPR_NOACCESS,
5955 &spr_read_generic, spr_access_nop,
5956 0x00000000);
5957 /* Time base */
5958 gen_tbl(env);
5959 /* Thermal management */
5960 gen_spr_thrm(env);
5961 /* XXX : not implemented */
5962 spr_register(env, SPR_750_THRM4, "THRM4",
5963 SPR_NOACCESS, SPR_NOACCESS,
5964 &spr_read_generic, &spr_write_generic,
5965 0x00000000);
5966 /* Hardware implementation registers */
5967 /* XXX : not implemented */
5968 spr_register(env, SPR_HID0, "HID0",
5969 SPR_NOACCESS, SPR_NOACCESS,
5970 &spr_read_generic, &spr_write_generic,
5971 0x00000000);
5972 /* XXX : not implemented */
5973 spr_register(env, SPR_HID1, "HID1",
5974 SPR_NOACCESS, SPR_NOACCESS,
5975 &spr_read_generic, &spr_write_generic,
5976 0x00000000);
5977 /* XXX : not implemented */
5978 spr_register(env, SPR_750FX_HID2, "HID2",
5979 SPR_NOACCESS, SPR_NOACCESS,
5980 &spr_read_generic, &spr_write_generic,
5981 0x00000000);
5982 /* Memory management */
5983 gen_low_BATs(env);
5984 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
5985 gen_high_BATs(env);
5986 init_excp_7x0(env);
5987 env->dcache_line_size = 32;
5988 env->icache_line_size = 32;
5989 /* Allocate hardware IRQ controller */
5990 ppc6xx_irq_init(env);
5991 }
5992
5993 POWERPC_FAMILY(750fx)(ObjectClass *oc, void *data)
5994 {
5995 DeviceClass *dc = DEVICE_CLASS(oc);
5996 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
5997
5998 dc->desc = "PowerPC 750FX";
5999 pcc->init_proc = init_proc_750fx;
6000 pcc->check_pow = check_pow_hid0;
6001 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6002 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6003 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6004 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6005 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6006 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6007 PPC_SEGMENT | PPC_EXTERN;
6008 pcc->msr_mask = (1ull << MSR_POW) |
6009 (1ull << MSR_ILE) |
6010 (1ull << MSR_EE) |
6011 (1ull << MSR_PR) |
6012 (1ull << MSR_FP) |
6013 (1ull << MSR_ME) |
6014 (1ull << MSR_FE0) |
6015 (1ull << MSR_SE) |
6016 (1ull << MSR_DE) |
6017 (1ull << MSR_FE1) |
6018 (1ull << MSR_EP) |
6019 (1ull << MSR_IR) |
6020 (1ull << MSR_DR) |
6021 (1ull << MSR_PMM) |
6022 (1ull << MSR_RI) |
6023 (1ull << MSR_LE);
6024 pcc->mmu_model = POWERPC_MMU_32B;
6025 #if defined(CONFIG_SOFTMMU)
6026 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6027 #endif
6028 pcc->excp_model = POWERPC_EXCP_7x0;
6029 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6030 pcc->bfd_mach = bfd_mach_ppc_750;
6031 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6032 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6033 }
6034
6035 static void init_proc_750gx (CPUPPCState *env)
6036 {
6037 gen_spr_ne_601(env);
6038 gen_spr_7xx(env);
6039 /* XXX : not implemented (XXX: different from 750fx) */
6040 spr_register(env, SPR_L2CR, "L2CR",
6041 SPR_NOACCESS, SPR_NOACCESS,
6042 &spr_read_generic, spr_access_nop,
6043 0x00000000);
6044 /* Time base */
6045 gen_tbl(env);
6046 /* Thermal management */
6047 gen_spr_thrm(env);
6048 /* XXX : not implemented */
6049 spr_register(env, SPR_750_THRM4, "THRM4",
6050 SPR_NOACCESS, SPR_NOACCESS,
6051 &spr_read_generic, &spr_write_generic,
6052 0x00000000);
6053 /* Hardware implementation registers */
6054 /* XXX : not implemented (XXX: different from 750fx) */
6055 spr_register(env, SPR_HID0, "HID0",
6056 SPR_NOACCESS, SPR_NOACCESS,
6057 &spr_read_generic, &spr_write_generic,
6058 0x00000000);
6059 /* XXX : not implemented */
6060 spr_register(env, SPR_HID1, "HID1",
6061 SPR_NOACCESS, SPR_NOACCESS,
6062 &spr_read_generic, &spr_write_generic,
6063 0x00000000);
6064 /* XXX : not implemented (XXX: different from 750fx) */
6065 spr_register(env, SPR_750FX_HID2, "HID2",
6066 SPR_NOACCESS, SPR_NOACCESS,
6067 &spr_read_generic, &spr_write_generic,
6068 0x00000000);
6069 /* Memory management */
6070 gen_low_BATs(env);
6071 /* PowerPC 750fx & 750gx has 8 DBATs and 8 IBATs */
6072 gen_high_BATs(env);
6073 init_excp_7x0(env);
6074 env->dcache_line_size = 32;
6075 env->icache_line_size = 32;
6076 /* Allocate hardware IRQ controller */
6077 ppc6xx_irq_init(env);
6078 }
6079
6080 POWERPC_FAMILY(750gx)(ObjectClass *oc, void *data)
6081 {
6082 DeviceClass *dc = DEVICE_CLASS(oc);
6083 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6084
6085 dc->desc = "PowerPC 750GX";
6086 pcc->init_proc = init_proc_750gx;
6087 pcc->check_pow = check_pow_hid0;
6088 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6089 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6090 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6091 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6092 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6093 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6094 PPC_SEGMENT | PPC_EXTERN;
6095 pcc->msr_mask = (1ull << MSR_POW) |
6096 (1ull << MSR_ILE) |
6097 (1ull << MSR_EE) |
6098 (1ull << MSR_PR) |
6099 (1ull << MSR_FP) |
6100 (1ull << MSR_ME) |
6101 (1ull << MSR_FE0) |
6102 (1ull << MSR_SE) |
6103 (1ull << MSR_DE) |
6104 (1ull << MSR_FE1) |
6105 (1ull << MSR_EP) |
6106 (1ull << MSR_IR) |
6107 (1ull << MSR_DR) |
6108 (1ull << MSR_PMM) |
6109 (1ull << MSR_RI) |
6110 (1ull << MSR_LE);
6111 pcc->mmu_model = POWERPC_MMU_32B;
6112 #if defined(CONFIG_SOFTMMU)
6113 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6114 #endif
6115 pcc->excp_model = POWERPC_EXCP_7x0;
6116 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6117 pcc->bfd_mach = bfd_mach_ppc_750;
6118 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6119 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6120 }
6121
6122 static void init_proc_745 (CPUPPCState *env)
6123 {
6124 gen_spr_ne_601(env);
6125 gen_spr_7xx(env);
6126 gen_spr_G2_755(env);
6127 /* Time base */
6128 gen_tbl(env);
6129 /* Thermal management */
6130 gen_spr_thrm(env);
6131 /* Hardware implementation registers */
6132 /* XXX : not implemented */
6133 spr_register(env, SPR_HID0, "HID0",
6134 SPR_NOACCESS, SPR_NOACCESS,
6135 &spr_read_generic, &spr_write_generic,
6136 0x00000000);
6137 /* XXX : not implemented */
6138 spr_register(env, SPR_HID1, "HID1",
6139 SPR_NOACCESS, SPR_NOACCESS,
6140 &spr_read_generic, &spr_write_generic,
6141 0x00000000);
6142 /* XXX : not implemented */
6143 spr_register(env, SPR_HID2, "HID2",
6144 SPR_NOACCESS, SPR_NOACCESS,
6145 &spr_read_generic, &spr_write_generic,
6146 0x00000000);
6147 /* Memory management */
6148 gen_low_BATs(env);
6149 gen_high_BATs(env);
6150 gen_6xx_7xx_soft_tlb(env, 64, 2);
6151 init_excp_7x5(env);
6152 env->dcache_line_size = 32;
6153 env->icache_line_size = 32;
6154 /* Allocate hardware IRQ controller */
6155 ppc6xx_irq_init(env);
6156 }
6157
6158 POWERPC_FAMILY(745)(ObjectClass *oc, void *data)
6159 {
6160 DeviceClass *dc = DEVICE_CLASS(oc);
6161 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6162
6163 dc->desc = "PowerPC 745";
6164 pcc->init_proc = init_proc_745;
6165 pcc->check_pow = check_pow_hid0;
6166 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6167 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6168 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6169 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6170 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6171 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6172 PPC_SEGMENT | PPC_EXTERN;
6173 pcc->msr_mask = (1ull << MSR_POW) |
6174 (1ull << MSR_ILE) |
6175 (1ull << MSR_EE) |
6176 (1ull << MSR_PR) |
6177 (1ull << MSR_FP) |
6178 (1ull << MSR_ME) |
6179 (1ull << MSR_FE0) |
6180 (1ull << MSR_SE) |
6181 (1ull << MSR_DE) |
6182 (1ull << MSR_FE1) |
6183 (1ull << MSR_EP) |
6184 (1ull << MSR_IR) |
6185 (1ull << MSR_DR) |
6186 (1ull << MSR_PMM) |
6187 (1ull << MSR_RI) |
6188 (1ull << MSR_LE);
6189 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6190 pcc->excp_model = POWERPC_EXCP_7x5;
6191 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6192 pcc->bfd_mach = bfd_mach_ppc_750;
6193 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6194 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6195 }
6196
6197 static void init_proc_755 (CPUPPCState *env)
6198 {
6199 gen_spr_ne_601(env);
6200 gen_spr_7xx(env);
6201 gen_spr_G2_755(env);
6202 /* Time base */
6203 gen_tbl(env);
6204 /* L2 cache control */
6205 /* XXX : not implemented */
6206 spr_register(env, SPR_L2CR, "L2CR",
6207 SPR_NOACCESS, SPR_NOACCESS,
6208 &spr_read_generic, spr_access_nop,
6209 0x00000000);
6210 /* XXX : not implemented */
6211 spr_register(env, SPR_L2PMCR, "L2PMCR",
6212 SPR_NOACCESS, SPR_NOACCESS,
6213 &spr_read_generic, &spr_write_generic,
6214 0x00000000);
6215 /* Thermal management */
6216 gen_spr_thrm(env);
6217 /* Hardware implementation registers */
6218 /* XXX : not implemented */
6219 spr_register(env, SPR_HID0, "HID0",
6220 SPR_NOACCESS, SPR_NOACCESS,
6221 &spr_read_generic, &spr_write_generic,
6222 0x00000000);
6223 /* XXX : not implemented */
6224 spr_register(env, SPR_HID1, "HID1",
6225 SPR_NOACCESS, SPR_NOACCESS,
6226 &spr_read_generic, &spr_write_generic,
6227 0x00000000);
6228 /* XXX : not implemented */
6229 spr_register(env, SPR_HID2, "HID2",
6230 SPR_NOACCESS, SPR_NOACCESS,
6231 &spr_read_generic, &spr_write_generic,
6232 0x00000000);
6233 /* Memory management */
6234 gen_low_BATs(env);
6235 gen_high_BATs(env);
6236 gen_6xx_7xx_soft_tlb(env, 64, 2);
6237 init_excp_7x5(env);
6238 env->dcache_line_size = 32;
6239 env->icache_line_size = 32;
6240 /* Allocate hardware IRQ controller */
6241 ppc6xx_irq_init(env);
6242 }
6243
6244 POWERPC_FAMILY(755)(ObjectClass *oc, void *data)
6245 {
6246 DeviceClass *dc = DEVICE_CLASS(oc);
6247 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6248
6249 dc->desc = "PowerPC 755";
6250 pcc->init_proc = init_proc_755;
6251 pcc->check_pow = check_pow_hid0;
6252 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6253 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6254 PPC_FLOAT_FRSQRTE | PPC_FLOAT_STFIWX |
6255 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
6256 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6257 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC | PPC_6xx_TLB |
6258 PPC_SEGMENT | PPC_EXTERN;
6259 pcc->msr_mask = (1ull << MSR_POW) |
6260 (1ull << MSR_ILE) |
6261 (1ull << MSR_EE) |
6262 (1ull << MSR_PR) |
6263 (1ull << MSR_FP) |
6264 (1ull << MSR_ME) |
6265 (1ull << MSR_FE0) |
6266 (1ull << MSR_SE) |
6267 (1ull << MSR_DE) |
6268 (1ull << MSR_FE1) |
6269 (1ull << MSR_EP) |
6270 (1ull << MSR_IR) |
6271 (1ull << MSR_DR) |
6272 (1ull << MSR_PMM) |
6273 (1ull << MSR_RI) |
6274 (1ull << MSR_LE);
6275 pcc->mmu_model = POWERPC_MMU_SOFT_6xx;
6276 pcc->excp_model = POWERPC_EXCP_7x5;
6277 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6278 pcc->bfd_mach = bfd_mach_ppc_750;
6279 pcc->flags = POWERPC_FLAG_SE | POWERPC_FLAG_BE |
6280 POWERPC_FLAG_PMM | POWERPC_FLAG_BUS_CLK;
6281 }
6282
6283 static void init_proc_7400 (CPUPPCState *env)
6284 {
6285 gen_spr_ne_601(env);
6286 gen_spr_7xx(env);
6287 /* Time base */
6288 gen_tbl(env);
6289 /* 74xx specific SPR */
6290 gen_spr_74xx(env);
6291 /* XXX : not implemented */
6292 spr_register(env, SPR_UBAMR, "UBAMR",
6293 &spr_read_ureg, SPR_NOACCESS,
6294 &spr_read_ureg, SPR_NOACCESS,
6295 0x00000000);
6296 /* XXX: this seems not implemented on all revisions. */
6297 /* XXX : not implemented */
6298 spr_register(env, SPR_MSSCR1, "MSSCR1",
6299 SPR_NOACCESS, SPR_NOACCESS,
6300 &spr_read_generic, &spr_write_generic,
6301 0x00000000);
6302 /* Thermal management */
6303 gen_spr_thrm(env);
6304 /* Memory management */
6305 gen_low_BATs(env);
6306 init_excp_7400(env);
6307 env->dcache_line_size = 32;
6308 env->icache_line_size = 32;
6309 /* Allocate hardware IRQ controller */
6310 ppc6xx_irq_init(env);
6311 }
6312
6313 POWERPC_FAMILY(7400)(ObjectClass *oc, void *data)
6314 {
6315 DeviceClass *dc = DEVICE_CLASS(oc);
6316 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6317
6318 dc->desc = "PowerPC 7400 (aka G4)";
6319 pcc->init_proc = init_proc_7400;
6320 pcc->check_pow = check_pow_hid0;
6321 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6322 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6323 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6324 PPC_FLOAT_STFIWX |
6325 PPC_CACHE | PPC_CACHE_ICBI |
6326 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6327 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6328 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6329 PPC_MEM_TLBIA |
6330 PPC_SEGMENT | PPC_EXTERN |
6331 PPC_ALTIVEC;
6332 pcc->msr_mask = (1ull << MSR_VR) |
6333 (1ull << MSR_POW) |
6334 (1ull << MSR_ILE) |
6335 (1ull << MSR_EE) |
6336 (1ull << MSR_PR) |
6337 (1ull << MSR_FP) |
6338 (1ull << MSR_ME) |
6339 (1ull << MSR_FE0) |
6340 (1ull << MSR_SE) |
6341 (1ull << MSR_DE) |
6342 (1ull << MSR_FE1) |
6343 (1ull << MSR_EP) |
6344 (1ull << MSR_IR) |
6345 (1ull << MSR_DR) |
6346 (1ull << MSR_PMM) |
6347 (1ull << MSR_RI) |
6348 (1ull << MSR_LE);
6349 pcc->mmu_model = POWERPC_MMU_32B;
6350 #if defined(CONFIG_SOFTMMU)
6351 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6352 #endif
6353 pcc->excp_model = POWERPC_EXCP_74xx;
6354 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6355 pcc->bfd_mach = bfd_mach_ppc_7400;
6356 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6357 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6358 POWERPC_FLAG_BUS_CLK;
6359 }
6360
6361 static void init_proc_7410 (CPUPPCState *env)
6362 {
6363 gen_spr_ne_601(env);
6364 gen_spr_7xx(env);
6365 /* Time base */
6366 gen_tbl(env);
6367 /* 74xx specific SPR */
6368 gen_spr_74xx(env);
6369 /* XXX : not implemented */
6370 spr_register(env, SPR_UBAMR, "UBAMR",
6371 &spr_read_ureg, SPR_NOACCESS,
6372 &spr_read_ureg, SPR_NOACCESS,
6373 0x00000000);
6374 /* Thermal management */
6375 gen_spr_thrm(env);
6376 /* L2PMCR */
6377 /* XXX : not implemented */
6378 spr_register(env, SPR_L2PMCR, "L2PMCR",
6379 SPR_NOACCESS, SPR_NOACCESS,
6380 &spr_read_generic, &spr_write_generic,
6381 0x00000000);
6382 /* LDSTDB */
6383 /* XXX : not implemented */
6384 spr_register(env, SPR_LDSTDB, "LDSTDB",
6385 SPR_NOACCESS, SPR_NOACCESS,
6386 &spr_read_generic, &spr_write_generic,
6387 0x00000000);
6388 /* Memory management */
6389 gen_low_BATs(env);
6390 init_excp_7400(env);
6391 env->dcache_line_size = 32;
6392 env->icache_line_size = 32;
6393 /* Allocate hardware IRQ controller */
6394 ppc6xx_irq_init(env);
6395 }
6396
6397 POWERPC_FAMILY(7410)(ObjectClass *oc, void *data)
6398 {
6399 DeviceClass *dc = DEVICE_CLASS(oc);
6400 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6401
6402 dc->desc = "PowerPC 7410 (aka G4)";
6403 pcc->init_proc = init_proc_7410;
6404 pcc->check_pow = check_pow_hid0;
6405 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6406 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6407 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6408 PPC_FLOAT_STFIWX |
6409 PPC_CACHE | PPC_CACHE_ICBI |
6410 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6411 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6412 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6413 PPC_MEM_TLBIA |
6414 PPC_SEGMENT | PPC_EXTERN |
6415 PPC_ALTIVEC;
6416 pcc->msr_mask = (1ull << MSR_VR) |
6417 (1ull << MSR_POW) |
6418 (1ull << MSR_ILE) |
6419 (1ull << MSR_EE) |
6420 (1ull << MSR_PR) |
6421 (1ull << MSR_FP) |
6422 (1ull << MSR_ME) |
6423 (1ull << MSR_FE0) |
6424 (1ull << MSR_SE) |
6425 (1ull << MSR_DE) |
6426 (1ull << MSR_FE1) |
6427 (1ull << MSR_EP) |
6428 (1ull << MSR_IR) |
6429 (1ull << MSR_DR) |
6430 (1ull << MSR_PMM) |
6431 (1ull << MSR_RI) |
6432 (1ull << MSR_LE);
6433 pcc->mmu_model = POWERPC_MMU_32B;
6434 #if defined(CONFIG_SOFTMMU)
6435 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
6436 #endif
6437 pcc->excp_model = POWERPC_EXCP_74xx;
6438 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6439 pcc->bfd_mach = bfd_mach_ppc_7400;
6440 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6441 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6442 POWERPC_FLAG_BUS_CLK;
6443 }
6444
6445 static void init_proc_7440 (CPUPPCState *env)
6446 {
6447 gen_spr_ne_601(env);
6448 gen_spr_7xx(env);
6449 /* Time base */
6450 gen_tbl(env);
6451 /* 74xx specific SPR */
6452 gen_spr_74xx(env);
6453 /* XXX : not implemented */
6454 spr_register(env, SPR_UBAMR, "UBAMR",
6455 &spr_read_ureg, SPR_NOACCESS,
6456 &spr_read_ureg, SPR_NOACCESS,
6457 0x00000000);
6458 /* LDSTCR */
6459 /* XXX : not implemented */
6460 spr_register(env, SPR_LDSTCR, "LDSTCR",
6461 SPR_NOACCESS, SPR_NOACCESS,
6462 &spr_read_generic, &spr_write_generic,
6463 0x00000000);
6464 /* ICTRL */
6465 /* XXX : not implemented */
6466 spr_register(env, SPR_ICTRL, "ICTRL",
6467 SPR_NOACCESS, SPR_NOACCESS,
6468 &spr_read_generic, &spr_write_generic,
6469 0x00000000);
6470 /* MSSSR0 */
6471 /* XXX : not implemented */
6472 spr_register(env, SPR_MSSSR0, "MSSSR0",
6473 SPR_NOACCESS, SPR_NOACCESS,
6474 &spr_read_generic, &spr_write_generic,
6475 0x00000000);
6476 /* PMC */
6477 /* XXX : not implemented */
6478 spr_register(env, SPR_PMC5, "PMC5",
6479 SPR_NOACCESS, SPR_NOACCESS,
6480 &spr_read_generic, &spr_write_generic,
6481 0x00000000);
6482 /* XXX : not implemented */
6483 spr_register(env, SPR_UPMC5, "UPMC5",
6484 &spr_read_ureg, SPR_NOACCESS,
6485 &spr_read_ureg, SPR_NOACCESS,
6486 0x00000000);
6487 /* XXX : not implemented */
6488 spr_register(env, SPR_PMC6, "PMC6",
6489 SPR_NOACCESS, SPR_NOACCESS,
6490 &spr_read_generic, &spr_write_generic,
6491 0x00000000);
6492 /* XXX : not implemented */
6493 spr_register(env, SPR_UPMC6, "UPMC6",
6494 &spr_read_ureg, SPR_NOACCESS,
6495 &spr_read_ureg, SPR_NOACCESS,
6496 0x00000000);
6497 /* Memory management */
6498 gen_low_BATs(env);
6499 gen_74xx_soft_tlb(env, 128, 2);
6500 init_excp_7450(env);
6501 env->dcache_line_size = 32;
6502 env->icache_line_size = 32;
6503 /* Allocate hardware IRQ controller */
6504 ppc6xx_irq_init(env);
6505 }
6506
6507 POWERPC_FAMILY(7440)(ObjectClass *oc, void *data)
6508 {
6509 DeviceClass *dc = DEVICE_CLASS(oc);
6510 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6511
6512 dc->desc = "PowerPC 7440 (aka G4)";
6513 pcc->init_proc = init_proc_7440;
6514 pcc->check_pow = check_pow_hid0_74xx;
6515 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6516 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6517 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6518 PPC_FLOAT_STFIWX |
6519 PPC_CACHE | PPC_CACHE_ICBI |
6520 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6521 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6522 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6523 PPC_MEM_TLBIA | PPC_74xx_TLB |
6524 PPC_SEGMENT | PPC_EXTERN |
6525 PPC_ALTIVEC;
6526 pcc->msr_mask = (1ull << MSR_VR) |
6527 (1ull << MSR_POW) |
6528 (1ull << MSR_ILE) |
6529 (1ull << MSR_EE) |
6530 (1ull << MSR_PR) |
6531 (1ull << MSR_FP) |
6532 (1ull << MSR_ME) |
6533 (1ull << MSR_FE0) |
6534 (1ull << MSR_SE) |
6535 (1ull << MSR_DE) |
6536 (1ull << MSR_FE1) |
6537 (1ull << MSR_EP) |
6538 (1ull << MSR_IR) |
6539 (1ull << MSR_DR) |
6540 (1ull << MSR_PMM) |
6541 (1ull << MSR_RI) |
6542 (1ull << MSR_LE);
6543 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6544 pcc->excp_model = POWERPC_EXCP_74xx;
6545 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6546 pcc->bfd_mach = bfd_mach_ppc_7400;
6547 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6548 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6549 POWERPC_FLAG_BUS_CLK;
6550 }
6551
6552 static void init_proc_7450 (CPUPPCState *env)
6553 {
6554 gen_spr_ne_601(env);
6555 gen_spr_7xx(env);
6556 /* Time base */
6557 gen_tbl(env);
6558 /* 74xx specific SPR */
6559 gen_spr_74xx(env);
6560 /* Level 3 cache control */
6561 gen_l3_ctrl(env);
6562 /* L3ITCR1 */
6563 /* XXX : not implemented */
6564 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6565 SPR_NOACCESS, SPR_NOACCESS,
6566 &spr_read_generic, &spr_write_generic,
6567 0x00000000);
6568 /* L3ITCR2 */
6569 /* XXX : not implemented */
6570 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6571 SPR_NOACCESS, SPR_NOACCESS,
6572 &spr_read_generic, &spr_write_generic,
6573 0x00000000);
6574 /* L3ITCR3 */
6575 /* XXX : not implemented */
6576 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6577 SPR_NOACCESS, SPR_NOACCESS,
6578 &spr_read_generic, &spr_write_generic,
6579 0x00000000);
6580 /* L3OHCR */
6581 /* XXX : not implemented */
6582 spr_register(env, SPR_L3OHCR, "L3OHCR",
6583 SPR_NOACCESS, SPR_NOACCESS,
6584 &spr_read_generic, &spr_write_generic,
6585 0x00000000);
6586 /* XXX : not implemented */
6587 spr_register(env, SPR_UBAMR, "UBAMR",
6588 &spr_read_ureg, SPR_NOACCESS,
6589 &spr_read_ureg, SPR_NOACCESS,
6590 0x00000000);
6591 /* LDSTCR */
6592 /* XXX : not implemented */
6593 spr_register(env, SPR_LDSTCR, "LDSTCR",
6594 SPR_NOACCESS, SPR_NOACCESS,
6595 &spr_read_generic, &spr_write_generic,
6596 0x00000000);
6597 /* ICTRL */
6598 /* XXX : not implemented */
6599 spr_register(env, SPR_ICTRL, "ICTRL",
6600 SPR_NOACCESS, SPR_NOACCESS,
6601 &spr_read_generic, &spr_write_generic,
6602 0x00000000);
6603 /* MSSSR0 */
6604 /* XXX : not implemented */
6605 spr_register(env, SPR_MSSSR0, "MSSSR0",
6606 SPR_NOACCESS, SPR_NOACCESS,
6607 &spr_read_generic, &spr_write_generic,
6608 0x00000000);
6609 /* PMC */
6610 /* XXX : not implemented */
6611 spr_register(env, SPR_PMC5, "PMC5",
6612 SPR_NOACCESS, SPR_NOACCESS,
6613 &spr_read_generic, &spr_write_generic,
6614 0x00000000);
6615 /* XXX : not implemented */
6616 spr_register(env, SPR_UPMC5, "UPMC5",
6617 &spr_read_ureg, SPR_NOACCESS,
6618 &spr_read_ureg, SPR_NOACCESS,
6619 0x00000000);
6620 /* XXX : not implemented */
6621 spr_register(env, SPR_PMC6, "PMC6",
6622 SPR_NOACCESS, SPR_NOACCESS,
6623 &spr_read_generic, &spr_write_generic,
6624 0x00000000);
6625 /* XXX : not implemented */
6626 spr_register(env, SPR_UPMC6, "UPMC6",
6627 &spr_read_ureg, SPR_NOACCESS,
6628 &spr_read_ureg, SPR_NOACCESS,
6629 0x00000000);
6630 /* Memory management */
6631 gen_low_BATs(env);
6632 gen_74xx_soft_tlb(env, 128, 2);
6633 init_excp_7450(env);
6634 env->dcache_line_size = 32;
6635 env->icache_line_size = 32;
6636 /* Allocate hardware IRQ controller */
6637 ppc6xx_irq_init(env);
6638 }
6639
6640 POWERPC_FAMILY(7450)(ObjectClass *oc, void *data)
6641 {
6642 DeviceClass *dc = DEVICE_CLASS(oc);
6643 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6644
6645 dc->desc = "PowerPC 7450 (aka G4)";
6646 pcc->init_proc = init_proc_7450;
6647 pcc->check_pow = check_pow_hid0_74xx;
6648 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6649 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6650 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6651 PPC_FLOAT_STFIWX |
6652 PPC_CACHE | PPC_CACHE_ICBI |
6653 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6654 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6655 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6656 PPC_MEM_TLBIA | PPC_74xx_TLB |
6657 PPC_SEGMENT | PPC_EXTERN |
6658 PPC_ALTIVEC;
6659 pcc->msr_mask = (1ull << MSR_VR) |
6660 (1ull << MSR_POW) |
6661 (1ull << MSR_ILE) |
6662 (1ull << MSR_EE) |
6663 (1ull << MSR_PR) |
6664 (1ull << MSR_FP) |
6665 (1ull << MSR_ME) |
6666 (1ull << MSR_FE0) |
6667 (1ull << MSR_SE) |
6668 (1ull << MSR_DE) |
6669 (1ull << MSR_FE1) |
6670 (1ull << MSR_EP) |
6671 (1ull << MSR_IR) |
6672 (1ull << MSR_DR) |
6673 (1ull << MSR_PMM) |
6674 (1ull << MSR_RI) |
6675 (1ull << MSR_LE);
6676 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6677 pcc->excp_model = POWERPC_EXCP_74xx;
6678 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6679 pcc->bfd_mach = bfd_mach_ppc_7400;
6680 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6681 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6682 POWERPC_FLAG_BUS_CLK;
6683 }
6684
6685 static void init_proc_7445 (CPUPPCState *env)
6686 {
6687 gen_spr_ne_601(env);
6688 gen_spr_7xx(env);
6689 /* Time base */
6690 gen_tbl(env);
6691 /* 74xx specific SPR */
6692 gen_spr_74xx(env);
6693 /* LDSTCR */
6694 /* XXX : not implemented */
6695 spr_register(env, SPR_LDSTCR, "LDSTCR",
6696 SPR_NOACCESS, SPR_NOACCESS,
6697 &spr_read_generic, &spr_write_generic,
6698 0x00000000);
6699 /* ICTRL */
6700 /* XXX : not implemented */
6701 spr_register(env, SPR_ICTRL, "ICTRL",
6702 SPR_NOACCESS, SPR_NOACCESS,
6703 &spr_read_generic, &spr_write_generic,
6704 0x00000000);
6705 /* MSSSR0 */
6706 /* XXX : not implemented */
6707 spr_register(env, SPR_MSSSR0, "MSSSR0",
6708 SPR_NOACCESS, SPR_NOACCESS,
6709 &spr_read_generic, &spr_write_generic,
6710 0x00000000);
6711 /* PMC */
6712 /* XXX : not implemented */
6713 spr_register(env, SPR_PMC5, "PMC5",
6714 SPR_NOACCESS, SPR_NOACCESS,
6715 &spr_read_generic, &spr_write_generic,
6716 0x00000000);
6717 /* XXX : not implemented */
6718 spr_register(env, SPR_UPMC5, "UPMC5",
6719 &spr_read_ureg, SPR_NOACCESS,
6720 &spr_read_ureg, SPR_NOACCESS,
6721 0x00000000);
6722 /* XXX : not implemented */
6723 spr_register(env, SPR_PMC6, "PMC6",
6724 SPR_NOACCESS, SPR_NOACCESS,
6725 &spr_read_generic, &spr_write_generic,
6726 0x00000000);
6727 /* XXX : not implemented */
6728 spr_register(env, SPR_UPMC6, "UPMC6",
6729 &spr_read_ureg, SPR_NOACCESS,
6730 &spr_read_ureg, SPR_NOACCESS,
6731 0x00000000);
6732 /* SPRGs */
6733 spr_register(env, SPR_SPRG4, "SPRG4",
6734 SPR_NOACCESS, SPR_NOACCESS,
6735 &spr_read_generic, &spr_write_generic,
6736 0x00000000);
6737 spr_register(env, SPR_USPRG4, "USPRG4",
6738 &spr_read_ureg, SPR_NOACCESS,
6739 &spr_read_ureg, SPR_NOACCESS,
6740 0x00000000);
6741 spr_register(env, SPR_SPRG5, "SPRG5",
6742 SPR_NOACCESS, SPR_NOACCESS,
6743 &spr_read_generic, &spr_write_generic,
6744 0x00000000);
6745 spr_register(env, SPR_USPRG5, "USPRG5",
6746 &spr_read_ureg, SPR_NOACCESS,
6747 &spr_read_ureg, SPR_NOACCESS,
6748 0x00000000);
6749 spr_register(env, SPR_SPRG6, "SPRG6",
6750 SPR_NOACCESS, SPR_NOACCESS,
6751 &spr_read_generic, &spr_write_generic,
6752 0x00000000);
6753 spr_register(env, SPR_USPRG6, "USPRG6",
6754 &spr_read_ureg, SPR_NOACCESS,
6755 &spr_read_ureg, SPR_NOACCESS,
6756 0x00000000);
6757 spr_register(env, SPR_SPRG7, "SPRG7",
6758 SPR_NOACCESS, SPR_NOACCESS,
6759 &spr_read_generic, &spr_write_generic,
6760 0x00000000);
6761 spr_register(env, SPR_USPRG7, "USPRG7",
6762 &spr_read_ureg, SPR_NOACCESS,
6763 &spr_read_ureg, SPR_NOACCESS,
6764 0x00000000);
6765 /* Memory management */
6766 gen_low_BATs(env);
6767 gen_high_BATs(env);
6768 gen_74xx_soft_tlb(env, 128, 2);
6769 init_excp_7450(env);
6770 env->dcache_line_size = 32;
6771 env->icache_line_size = 32;
6772 /* Allocate hardware IRQ controller */
6773 ppc6xx_irq_init(env);
6774 }
6775
6776 POWERPC_FAMILY(7445)(ObjectClass *oc, void *data)
6777 {
6778 DeviceClass *dc = DEVICE_CLASS(oc);
6779 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6780
6781 dc->desc = "PowerPC 7445 (aka G4)";
6782 pcc->init_proc = init_proc_7445;
6783 pcc->check_pow = check_pow_hid0_74xx;
6784 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6785 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6786 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6787 PPC_FLOAT_STFIWX |
6788 PPC_CACHE | PPC_CACHE_ICBI |
6789 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6790 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6791 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6792 PPC_MEM_TLBIA | PPC_74xx_TLB |
6793 PPC_SEGMENT | PPC_EXTERN |
6794 PPC_ALTIVEC;
6795 pcc->msr_mask = (1ull << MSR_VR) |
6796 (1ull << MSR_POW) |
6797 (1ull << MSR_ILE) |
6798 (1ull << MSR_EE) |
6799 (1ull << MSR_PR) |
6800 (1ull << MSR_FP) |
6801 (1ull << MSR_ME) |
6802 (1ull << MSR_FE0) |
6803 (1ull << MSR_SE) |
6804 (1ull << MSR_DE) |
6805 (1ull << MSR_FE1) |
6806 (1ull << MSR_EP) |
6807 (1ull << MSR_IR) |
6808 (1ull << MSR_DR) |
6809 (1ull << MSR_PMM) |
6810 (1ull << MSR_RI) |
6811 (1ull << MSR_LE);
6812 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6813 pcc->excp_model = POWERPC_EXCP_74xx;
6814 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6815 pcc->bfd_mach = bfd_mach_ppc_7400;
6816 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6817 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6818 POWERPC_FLAG_BUS_CLK;
6819 }
6820
6821 static void init_proc_7455 (CPUPPCState *env)
6822 {
6823 gen_spr_ne_601(env);
6824 gen_spr_7xx(env);
6825 /* Time base */
6826 gen_tbl(env);
6827 /* 74xx specific SPR */
6828 gen_spr_74xx(env);
6829 /* Level 3 cache control */
6830 gen_l3_ctrl(env);
6831 /* LDSTCR */
6832 /* XXX : not implemented */
6833 spr_register(env, SPR_LDSTCR, "LDSTCR",
6834 SPR_NOACCESS, SPR_NOACCESS,
6835 &spr_read_generic, &spr_write_generic,
6836 0x00000000);
6837 /* ICTRL */
6838 /* XXX : not implemented */
6839 spr_register(env, SPR_ICTRL, "ICTRL",
6840 SPR_NOACCESS, SPR_NOACCESS,
6841 &spr_read_generic, &spr_write_generic,
6842 0x00000000);
6843 /* MSSSR0 */
6844 /* XXX : not implemented */
6845 spr_register(env, SPR_MSSSR0, "MSSSR0",
6846 SPR_NOACCESS, SPR_NOACCESS,
6847 &spr_read_generic, &spr_write_generic,
6848 0x00000000);
6849 /* PMC */
6850 /* XXX : not implemented */
6851 spr_register(env, SPR_PMC5, "PMC5",
6852 SPR_NOACCESS, SPR_NOACCESS,
6853 &spr_read_generic, &spr_write_generic,
6854 0x00000000);
6855 /* XXX : not implemented */
6856 spr_register(env, SPR_UPMC5, "UPMC5",
6857 &spr_read_ureg, SPR_NOACCESS,
6858 &spr_read_ureg, SPR_NOACCESS,
6859 0x00000000);
6860 /* XXX : not implemented */
6861 spr_register(env, SPR_PMC6, "PMC6",
6862 SPR_NOACCESS, SPR_NOACCESS,
6863 &spr_read_generic, &spr_write_generic,
6864 0x00000000);
6865 /* XXX : not implemented */
6866 spr_register(env, SPR_UPMC6, "UPMC6",
6867 &spr_read_ureg, SPR_NOACCESS,
6868 &spr_read_ureg, SPR_NOACCESS,
6869 0x00000000);
6870 /* SPRGs */
6871 spr_register(env, SPR_SPRG4, "SPRG4",
6872 SPR_NOACCESS, SPR_NOACCESS,
6873 &spr_read_generic, &spr_write_generic,
6874 0x00000000);
6875 spr_register(env, SPR_USPRG4, "USPRG4",
6876 &spr_read_ureg, SPR_NOACCESS,
6877 &spr_read_ureg, SPR_NOACCESS,
6878 0x00000000);
6879 spr_register(env, SPR_SPRG5, "SPRG5",
6880 SPR_NOACCESS, SPR_NOACCESS,
6881 &spr_read_generic, &spr_write_generic,
6882 0x00000000);
6883 spr_register(env, SPR_USPRG5, "USPRG5",
6884 &spr_read_ureg, SPR_NOACCESS,
6885 &spr_read_ureg, SPR_NOACCESS,
6886 0x00000000);
6887 spr_register(env, SPR_SPRG6, "SPRG6",
6888 SPR_NOACCESS, SPR_NOACCESS,
6889 &spr_read_generic, &spr_write_generic,
6890 0x00000000);
6891 spr_register(env, SPR_USPRG6, "USPRG6",
6892 &spr_read_ureg, SPR_NOACCESS,
6893 &spr_read_ureg, SPR_NOACCESS,
6894 0x00000000);
6895 spr_register(env, SPR_SPRG7, "SPRG7",
6896 SPR_NOACCESS, SPR_NOACCESS,
6897 &spr_read_generic, &spr_write_generic,
6898 0x00000000);
6899 spr_register(env, SPR_USPRG7, "USPRG7",
6900 &spr_read_ureg, SPR_NOACCESS,
6901 &spr_read_ureg, SPR_NOACCESS,
6902 0x00000000);
6903 /* Memory management */
6904 gen_low_BATs(env);
6905 gen_high_BATs(env);
6906 gen_74xx_soft_tlb(env, 128, 2);
6907 init_excp_7450(env);
6908 env->dcache_line_size = 32;
6909 env->icache_line_size = 32;
6910 /* Allocate hardware IRQ controller */
6911 ppc6xx_irq_init(env);
6912 }
6913
6914 POWERPC_FAMILY(7455)(ObjectClass *oc, void *data)
6915 {
6916 DeviceClass *dc = DEVICE_CLASS(oc);
6917 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
6918
6919 dc->desc = "PowerPC 7455 (aka G4)";
6920 pcc->init_proc = init_proc_7455;
6921 pcc->check_pow = check_pow_hid0_74xx;
6922 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
6923 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
6924 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
6925 PPC_FLOAT_STFIWX |
6926 PPC_CACHE | PPC_CACHE_ICBI |
6927 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
6928 PPC_MEM_SYNC | PPC_MEM_EIEIO |
6929 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
6930 PPC_MEM_TLBIA | PPC_74xx_TLB |
6931 PPC_SEGMENT | PPC_EXTERN |
6932 PPC_ALTIVEC;
6933 pcc->msr_mask = (1ull << MSR_VR) |
6934 (1ull << MSR_POW) |
6935 (1ull << MSR_ILE) |
6936 (1ull << MSR_EE) |
6937 (1ull << MSR_PR) |
6938 (1ull << MSR_FP) |
6939 (1ull << MSR_ME) |
6940 (1ull << MSR_FE0) |
6941 (1ull << MSR_SE) |
6942 (1ull << MSR_DE) |
6943 (1ull << MSR_FE1) |
6944 (1ull << MSR_EP) |
6945 (1ull << MSR_IR) |
6946 (1ull << MSR_DR) |
6947 (1ull << MSR_PMM) |
6948 (1ull << MSR_RI) |
6949 (1ull << MSR_LE);
6950 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
6951 pcc->excp_model = POWERPC_EXCP_74xx;
6952 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
6953 pcc->bfd_mach = bfd_mach_ppc_7400;
6954 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
6955 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
6956 POWERPC_FLAG_BUS_CLK;
6957 }
6958
6959 static void init_proc_7457 (CPUPPCState *env)
6960 {
6961 gen_spr_ne_601(env);
6962 gen_spr_7xx(env);
6963 /* Time base */
6964 gen_tbl(env);
6965 /* 74xx specific SPR */
6966 gen_spr_74xx(env);
6967 /* Level 3 cache control */
6968 gen_l3_ctrl(env);
6969 /* L3ITCR1 */
6970 /* XXX : not implemented */
6971 spr_register(env, SPR_L3ITCR1, "L3ITCR1",
6972 SPR_NOACCESS, SPR_NOACCESS,
6973 &spr_read_generic, &spr_write_generic,
6974 0x00000000);
6975 /* L3ITCR2 */
6976 /* XXX : not implemented */
6977 spr_register(env, SPR_L3ITCR2, "L3ITCR2",
6978 SPR_NOACCESS, SPR_NOACCESS,
6979 &spr_read_generic, &spr_write_generic,
6980 0x00000000);
6981 /* L3ITCR3 */
6982 /* XXX : not implemented */
6983 spr_register(env, SPR_L3ITCR3, "L3ITCR3",
6984 SPR_NOACCESS, SPR_NOACCESS,
6985 &spr_read_generic, &spr_write_generic,
6986 0x00000000);
6987 /* L3OHCR */
6988 /* XXX : not implemented */
6989 spr_register(env, SPR_L3OHCR, "L3OHCR",
6990 SPR_NOACCESS, SPR_NOACCESS,
6991 &spr_read_generic, &spr_write_generic,
6992 0x00000000);
6993 /* LDSTCR */
6994 /* XXX : not implemented */
6995 spr_register(env, SPR_LDSTCR, "LDSTCR",
6996 SPR_NOACCESS, SPR_NOACCESS,
6997 &spr_read_generic, &spr_write_generic,
6998 0x00000000);
6999 /* ICTRL */
7000 /* XXX : not implemented */
7001 spr_register(env, SPR_ICTRL, "ICTRL",
7002 SPR_NOACCESS, SPR_NOACCESS,
7003 &spr_read_generic, &spr_write_generic,
7004 0x00000000);
7005 /* MSSSR0 */
7006 /* XXX : not implemented */
7007 spr_register(env, SPR_MSSSR0, "MSSSR0",
7008 SPR_NOACCESS, SPR_NOACCESS,
7009 &spr_read_generic, &spr_write_generic,
7010 0x00000000);
7011 /* PMC */
7012 /* XXX : not implemented */
7013 spr_register(env, SPR_PMC5, "PMC5",
7014 SPR_NOACCESS, SPR_NOACCESS,
7015 &spr_read_generic, &spr_write_generic,
7016 0x00000000);
7017 /* XXX : not implemented */
7018 spr_register(env, SPR_UPMC5, "UPMC5",
7019 &spr_read_ureg, SPR_NOACCESS,
7020 &spr_read_ureg, SPR_NOACCESS,
7021 0x00000000);
7022 /* XXX : not implemented */
7023 spr_register(env, SPR_PMC6, "PMC6",
7024 SPR_NOACCESS, SPR_NOACCESS,
7025 &spr_read_generic, &spr_write_generic,
7026 0x00000000);
7027 /* XXX : not implemented */
7028 spr_register(env, SPR_UPMC6, "UPMC6",
7029 &spr_read_ureg, SPR_NOACCESS,
7030 &spr_read_ureg, SPR_NOACCESS,
7031 0x00000000);
7032 /* SPRGs */
7033 spr_register(env, SPR_SPRG4, "SPRG4",
7034 SPR_NOACCESS, SPR_NOACCESS,
7035 &spr_read_generic, &spr_write_generic,
7036 0x00000000);
7037 spr_register(env, SPR_USPRG4, "USPRG4",
7038 &spr_read_ureg, SPR_NOACCESS,
7039 &spr_read_ureg, SPR_NOACCESS,
7040 0x00000000);
7041 spr_register(env, SPR_SPRG5, "SPRG5",
7042 SPR_NOACCESS, SPR_NOACCESS,
7043 &spr_read_generic, &spr_write_generic,
7044 0x00000000);
7045 spr_register(env, SPR_USPRG5, "USPRG5",
7046 &spr_read_ureg, SPR_NOACCESS,
7047 &spr_read_ureg, SPR_NOACCESS,
7048 0x00000000);
7049 spr_register(env, SPR_SPRG6, "SPRG6",
7050 SPR_NOACCESS, SPR_NOACCESS,
7051 &spr_read_generic, &spr_write_generic,
7052 0x00000000);
7053 spr_register(env, SPR_USPRG6, "USPRG6",
7054 &spr_read_ureg, SPR_NOACCESS,
7055 &spr_read_ureg, SPR_NOACCESS,
7056 0x00000000);
7057 spr_register(env, SPR_SPRG7, "SPRG7",
7058 SPR_NOACCESS, SPR_NOACCESS,
7059 &spr_read_generic, &spr_write_generic,
7060 0x00000000);
7061 spr_register(env, SPR_USPRG7, "USPRG7",
7062 &spr_read_ureg, SPR_NOACCESS,
7063 &spr_read_ureg, SPR_NOACCESS,
7064 0x00000000);
7065 /* Memory management */
7066 gen_low_BATs(env);
7067 gen_high_BATs(env);
7068 gen_74xx_soft_tlb(env, 128, 2);
7069 init_excp_7450(env);
7070 env->dcache_line_size = 32;
7071 env->icache_line_size = 32;
7072 /* Allocate hardware IRQ controller */
7073 ppc6xx_irq_init(env);
7074 }
7075
7076 POWERPC_FAMILY(7457)(ObjectClass *oc, void *data)
7077 {
7078 DeviceClass *dc = DEVICE_CLASS(oc);
7079 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7080
7081 dc->desc = "PowerPC 7457 (aka G4)";
7082 pcc->init_proc = init_proc_7457;
7083 pcc->check_pow = check_pow_hid0_74xx;
7084 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7085 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7086 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7087 PPC_FLOAT_STFIWX |
7088 PPC_CACHE | PPC_CACHE_ICBI |
7089 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7090 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7091 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7092 PPC_MEM_TLBIA | PPC_74xx_TLB |
7093 PPC_SEGMENT | PPC_EXTERN |
7094 PPC_ALTIVEC;
7095 pcc->msr_mask = (1ull << MSR_VR) |
7096 (1ull << MSR_POW) |
7097 (1ull << MSR_ILE) |
7098 (1ull << MSR_EE) |
7099 (1ull << MSR_PR) |
7100 (1ull << MSR_FP) |
7101 (1ull << MSR_ME) |
7102 (1ull << MSR_FE0) |
7103 (1ull << MSR_SE) |
7104 (1ull << MSR_DE) |
7105 (1ull << MSR_FE1) |
7106 (1ull << MSR_EP) |
7107 (1ull << MSR_IR) |
7108 (1ull << MSR_DR) |
7109 (1ull << MSR_PMM) |
7110 (1ull << MSR_RI) |
7111 (1ull << MSR_LE);
7112 pcc->mmu_model = POWERPC_MMU_SOFT_74xx;
7113 pcc->excp_model = POWERPC_EXCP_74xx;
7114 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7115 pcc->bfd_mach = bfd_mach_ppc_7400;
7116 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7117 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7118 POWERPC_FLAG_BUS_CLK;
7119 }
7120
7121 static void init_proc_e600 (CPUPPCState *env)
7122 {
7123 gen_spr_ne_601(env);
7124 gen_spr_7xx(env);
7125 /* Time base */
7126 gen_tbl(env);
7127 /* 74xx specific SPR */
7128 gen_spr_74xx(env);
7129 /* XXX : not implemented */
7130 spr_register(env, SPR_UBAMR, "UBAMR",
7131 &spr_read_ureg, SPR_NOACCESS,
7132 &spr_read_ureg, SPR_NOACCESS,
7133 0x00000000);
7134 /* XXX : not implemented */
7135 spr_register(env, SPR_LDSTCR, "LDSTCR",
7136 SPR_NOACCESS, SPR_NOACCESS,
7137 &spr_read_generic, &spr_write_generic,
7138 0x00000000);
7139 /* XXX : not implemented */
7140 spr_register(env, SPR_ICTRL, "ICTRL",
7141 SPR_NOACCESS, SPR_NOACCESS,
7142 &spr_read_generic, &spr_write_generic,
7143 0x00000000);
7144 /* XXX : not implemented */
7145 spr_register(env, SPR_MSSSR0, "MSSSR0",
7146 SPR_NOACCESS, SPR_NOACCESS,
7147 &spr_read_generic, &spr_write_generic,
7148 0x00000000);
7149 /* XXX : not implemented */
7150 spr_register(env, SPR_PMC5, "PMC5",
7151 SPR_NOACCESS, SPR_NOACCESS,
7152 &spr_read_generic, &spr_write_generic,
7153 0x00000000);
7154 /* XXX : not implemented */
7155 spr_register(env, SPR_UPMC5, "UPMC5",
7156 &spr_read_ureg, SPR_NOACCESS,
7157 &spr_read_ureg, SPR_NOACCESS,
7158 0x00000000);
7159 /* XXX : not implemented */
7160 spr_register(env, SPR_PMC6, "PMC6",
7161 SPR_NOACCESS, SPR_NOACCESS,
7162 &spr_read_generic, &spr_write_generic,
7163 0x00000000);
7164 /* XXX : not implemented */
7165 spr_register(env, SPR_UPMC6, "UPMC6",
7166 &spr_read_ureg, SPR_NOACCESS,
7167 &spr_read_ureg, SPR_NOACCESS,
7168 0x00000000);
7169 /* SPRGs */
7170 spr_register(env, SPR_SPRG4, "SPRG4",
7171 SPR_NOACCESS, SPR_NOACCESS,
7172 &spr_read_generic, &spr_write_generic,
7173 0x00000000);
7174 spr_register(env, SPR_USPRG4, "USPRG4",
7175 &spr_read_ureg, SPR_NOACCESS,
7176 &spr_read_ureg, SPR_NOACCESS,
7177 0x00000000);
7178 spr_register(env, SPR_SPRG5, "SPRG5",
7179 SPR_NOACCESS, SPR_NOACCESS,
7180 &spr_read_generic, &spr_write_generic,
7181 0x00000000);
7182 spr_register(env, SPR_USPRG5, "USPRG5",
7183 &spr_read_ureg, SPR_NOACCESS,
7184 &spr_read_ureg, SPR_NOACCESS,
7185 0x00000000);
7186 spr_register(env, SPR_SPRG6, "SPRG6",
7187 SPR_NOACCESS, SPR_NOACCESS,
7188 &spr_read_generic, &spr_write_generic,
7189 0x00000000);
7190 spr_register(env, SPR_USPRG6, "USPRG6",
7191 &spr_read_ureg, SPR_NOACCESS,
7192 &spr_read_ureg, SPR_NOACCESS,
7193 0x00000000);
7194 spr_register(env, SPR_SPRG7, "SPRG7",
7195 SPR_NOACCESS, SPR_NOACCESS,
7196 &spr_read_generic, &spr_write_generic,
7197 0x00000000);
7198 spr_register(env, SPR_USPRG7, "USPRG7",
7199 &spr_read_ureg, SPR_NOACCESS,
7200 &spr_read_ureg, SPR_NOACCESS,
7201 0x00000000);
7202 /* Memory management */
7203 gen_low_BATs(env);
7204 gen_high_BATs(env);
7205 gen_74xx_soft_tlb(env, 128, 2);
7206 init_excp_7450(env);
7207 env->dcache_line_size = 32;
7208 env->icache_line_size = 32;
7209 /* Allocate hardware IRQ controller */
7210 ppc6xx_irq_init(env);
7211 }
7212
7213 POWERPC_FAMILY(e600)(ObjectClass *oc, void *data)
7214 {
7215 DeviceClass *dc = DEVICE_CLASS(oc);
7216 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7217
7218 dc->desc = "PowerPC e600";
7219 pcc->init_proc = init_proc_e600;
7220 pcc->check_pow = check_pow_hid0_74xx;
7221 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7222 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7223 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7224 PPC_FLOAT_STFIWX |
7225 PPC_CACHE | PPC_CACHE_ICBI |
7226 PPC_CACHE_DCBA | PPC_CACHE_DCBZ |
7227 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7228 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7229 PPC_MEM_TLBIA | PPC_74xx_TLB |
7230 PPC_SEGMENT | PPC_EXTERN |
7231 PPC_ALTIVEC;
7232 pcc->insns_flags2 = PPC_NONE;
7233 pcc->msr_mask = (1ull << MSR_VR) |
7234 (1ull << MSR_POW) |
7235 (1ull << MSR_ILE) |
7236 (1ull << MSR_EE) |
7237 (1ull << MSR_PR) |
7238 (1ull << MSR_FP) |
7239 (1ull << MSR_ME) |
7240 (1ull << MSR_FE0) |
7241 (1ull << MSR_SE) |
7242 (1ull << MSR_DE) |
7243 (1ull << MSR_FE1) |
7244 (1ull << MSR_EP) |
7245 (1ull << MSR_IR) |
7246 (1ull << MSR_DR) |
7247 (1ull << MSR_PMM) |
7248 (1ull << MSR_RI) |
7249 (1ull << MSR_LE);
7250 pcc->mmu_model = POWERPC_MMU_32B;
7251 #if defined(CONFIG_SOFTMMU)
7252 pcc->handle_mmu_fault = ppc_hash32_handle_mmu_fault;
7253 #endif
7254 pcc->excp_model = POWERPC_EXCP_74xx;
7255 pcc->bus_model = PPC_FLAGS_INPUT_6xx;
7256 pcc->bfd_mach = bfd_mach_ppc_7400;
7257 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7258 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7259 POWERPC_FLAG_BUS_CLK;
7260 }
7261
7262 #if defined (TARGET_PPC64)
7263 #if defined(CONFIG_USER_ONLY)
7264 #define POWERPC970_HID5_INIT 0x00000080
7265 #else
7266 #define POWERPC970_HID5_INIT 0x00000000
7267 #endif
7268
7269 static int check_pow_970 (CPUPPCState *env)
7270 {
7271 if (env->spr[SPR_HID0] & 0x00600000)
7272 return 1;
7273
7274 return 0;
7275 }
7276
7277 static void init_proc_970 (CPUPPCState *env)
7278 {
7279 gen_spr_ne_601(env);
7280 gen_spr_7xx(env);
7281 /* Time base */
7282 gen_tbl(env);
7283 /* Hardware implementation registers */
7284 /* XXX : not implemented */
7285 spr_register(env, SPR_HID0, "HID0",
7286 SPR_NOACCESS, SPR_NOACCESS,
7287 &spr_read_generic, &spr_write_clear,
7288 0x60000000);
7289 /* XXX : not implemented */
7290 spr_register(env, SPR_HID1, "HID1",
7291 SPR_NOACCESS, SPR_NOACCESS,
7292 &spr_read_generic, &spr_write_generic,
7293 0x00000000);
7294 /* XXX : not implemented */
7295 spr_register(env, SPR_970_HID5, "HID5",
7296 SPR_NOACCESS, SPR_NOACCESS,
7297 &spr_read_generic, &spr_write_generic,
7298 POWERPC970_HID5_INIT);
7299 /* Memory management */
7300 /* XXX: not correct */
7301 gen_low_BATs(env);
7302 spr_register(env, SPR_HIOR, "SPR_HIOR",
7303 SPR_NOACCESS, SPR_NOACCESS,
7304 &spr_read_hior, &spr_write_hior,
7305 0x00000000);
7306 #if !defined(CONFIG_USER_ONLY)
7307 env->slb_nr = 32;
7308 #endif
7309 init_excp_970(env);
7310 env->dcache_line_size = 128;
7311 env->icache_line_size = 128;
7312 /* Allocate hardware IRQ controller */
7313 ppc970_irq_init(env);
7314 /* Can't find information on what this should be on reset. This
7315 * value is the one used by 74xx processors. */
7316 vscr_init(env, 0x00010000);
7317 }
7318
7319 POWERPC_FAMILY(970)(ObjectClass *oc, void *data)
7320 {
7321 DeviceClass *dc = DEVICE_CLASS(oc);
7322 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7323
7324 dc->desc = "PowerPC 970";
7325 pcc->init_proc = init_proc_970;
7326 pcc->check_pow = check_pow_970;
7327 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7328 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7329 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7330 PPC_FLOAT_STFIWX |
7331 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7332 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7333 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7334 PPC_64B | PPC_ALTIVEC |
7335 PPC_SEGMENT_64B | PPC_SLBI;
7336 pcc->msr_mask = (1ull << MSR_SF) |
7337 (1ull << MSR_SHV) |
7338 (1ull << MSR_VR) |
7339 (1ull << MSR_POW) |
7340 (1ull << MSR_EE) |
7341 (1ull << MSR_PR) |
7342 (1ull << MSR_FP) |
7343 (1ull << MSR_ME) |
7344 (1ull << MSR_FE0) |
7345 (1ull << MSR_SE) |
7346 (1ull << MSR_DE) |
7347 (1ull << MSR_FE1) |
7348 (1ull << MSR_IR) |
7349 (1ull << MSR_DR) |
7350 (1ull << MSR_PMM) |
7351 (1ull << MSR_RI);
7352 pcc->mmu_model = POWERPC_MMU_64B;
7353 #if defined(CONFIG_SOFTMMU)
7354 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7355 #endif
7356 pcc->excp_model = POWERPC_EXCP_970;
7357 pcc->bus_model = PPC_FLAGS_INPUT_970;
7358 pcc->bfd_mach = bfd_mach_ppc64;
7359 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7360 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7361 POWERPC_FLAG_BUS_CLK;
7362 pcc->l1_dcache_size = 0x8000;
7363 pcc->l1_icache_size = 0x10000;
7364 }
7365
7366 static int check_pow_970FX (CPUPPCState *env)
7367 {
7368 if (env->spr[SPR_HID0] & 0x00600000)
7369 return 1;
7370
7371 return 0;
7372 }
7373
7374 static void init_proc_970FX (CPUPPCState *env)
7375 {
7376 gen_spr_ne_601(env);
7377 gen_spr_7xx(env);
7378 /* Time base */
7379 gen_tbl(env);
7380 /* Hardware implementation registers */
7381 /* XXX : not implemented */
7382 spr_register(env, SPR_HID0, "HID0",
7383 SPR_NOACCESS, SPR_NOACCESS,
7384 &spr_read_generic, &spr_write_clear,
7385 0x60000000);
7386 /* XXX : not implemented */
7387 spr_register(env, SPR_HID1, "HID1",
7388 SPR_NOACCESS, SPR_NOACCESS,
7389 &spr_read_generic, &spr_write_generic,
7390 0x00000000);
7391 /* XXX : not implemented */
7392 spr_register(env, SPR_970_HID5, "HID5",
7393 SPR_NOACCESS, SPR_NOACCESS,
7394 &spr_read_generic, &spr_write_generic,
7395 POWERPC970_HID5_INIT);
7396 /* Memory management */
7397 /* XXX: not correct */
7398 gen_low_BATs(env);
7399 spr_register(env, SPR_HIOR, "SPR_HIOR",
7400 SPR_NOACCESS, SPR_NOACCESS,
7401 &spr_read_hior, &spr_write_hior,
7402 0x00000000);
7403 spr_register(env, SPR_CTRL, "SPR_CTRL",
7404 SPR_NOACCESS, SPR_NOACCESS,
7405 SPR_NOACCESS, &spr_write_generic,
7406 0x00000000);
7407 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
7408 SPR_NOACCESS, SPR_NOACCESS,
7409 &spr_read_generic, SPR_NOACCESS,
7410 0x00000000);
7411 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
7412 &spr_read_generic, &spr_write_generic,
7413 &spr_read_generic, &spr_write_generic,
7414 0x00000000);
7415 #if !defined(CONFIG_USER_ONLY)
7416 env->slb_nr = 64;
7417 #endif
7418 init_excp_970(env);
7419 env->dcache_line_size = 128;
7420 env->icache_line_size = 128;
7421 /* Allocate hardware IRQ controller */
7422 ppc970_irq_init(env);
7423 /* Can't find information on what this should be on reset. This
7424 * value is the one used by 74xx processors. */
7425 vscr_init(env, 0x00010000);
7426 }
7427
7428 POWERPC_FAMILY(970FX)(ObjectClass *oc, void *data)
7429 {
7430 DeviceClass *dc = DEVICE_CLASS(oc);
7431 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7432
7433 dc->desc = "PowerPC 970FX (aka G5)";
7434 pcc->init_proc = init_proc_970FX;
7435 pcc->check_pow = check_pow_970FX;
7436 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7437 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7438 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7439 PPC_FLOAT_STFIWX |
7440 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7441 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7442 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7443 PPC_64B | PPC_ALTIVEC |
7444 PPC_SEGMENT_64B | PPC_SLBI;
7445 pcc->msr_mask = (1ull << MSR_SF) |
7446 (1ull << MSR_VR) |
7447 (1ull << MSR_POW) |
7448 (1ull << MSR_EE) |
7449 (1ull << MSR_PR) |
7450 (1ull << MSR_FP) |
7451 (1ull << MSR_ME) |
7452 (1ull << MSR_FE0) |
7453 (1ull << MSR_SE) |
7454 (1ull << MSR_DE) |
7455 (1ull << MSR_FE1) |
7456 (1ull << MSR_IR) |
7457 (1ull << MSR_DR) |
7458 (1ull << MSR_PMM) |
7459 (1ull << MSR_RI);
7460 pcc->mmu_model = POWERPC_MMU_64B;
7461 #if defined(CONFIG_SOFTMMU)
7462 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7463 #endif
7464 pcc->excp_model = POWERPC_EXCP_970;
7465 pcc->bus_model = PPC_FLAGS_INPUT_970;
7466 pcc->bfd_mach = bfd_mach_ppc64;
7467 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7468 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7469 POWERPC_FLAG_BUS_CLK;
7470 pcc->l1_dcache_size = 0x8000;
7471 pcc->l1_icache_size = 0x10000;
7472 }
7473
7474 static int check_pow_970MP (CPUPPCState *env)
7475 {
7476 if (env->spr[SPR_HID0] & 0x01C00000)
7477 return 1;
7478
7479 return 0;
7480 }
7481
7482 static void init_proc_970MP (CPUPPCState *env)
7483 {
7484 gen_spr_ne_601(env);
7485 gen_spr_7xx(env);
7486 /* Time base */
7487 gen_tbl(env);
7488 /* Hardware implementation registers */
7489 /* XXX : not implemented */
7490 spr_register(env, SPR_HID0, "HID0",
7491 SPR_NOACCESS, SPR_NOACCESS,
7492 &spr_read_generic, &spr_write_clear,
7493 0x60000000);
7494 /* XXX : not implemented */
7495 spr_register(env, SPR_HID1, "HID1",
7496 SPR_NOACCESS, SPR_NOACCESS,
7497 &spr_read_generic, &spr_write_generic,
7498 0x00000000);
7499 /* XXX : not implemented */
7500 spr_register(env, SPR_970_HID5, "HID5",
7501 SPR_NOACCESS, SPR_NOACCESS,
7502 &spr_read_generic, &spr_write_generic,
7503 POWERPC970_HID5_INIT);
7504 /* XXX : not implemented */
7505 /* Memory management */
7506 /* XXX: not correct */
7507 gen_low_BATs(env);
7508 spr_register(env, SPR_HIOR, "SPR_HIOR",
7509 SPR_NOACCESS, SPR_NOACCESS,
7510 &spr_read_hior, &spr_write_hior,
7511 0x00000000);
7512 /* Logical partitionning */
7513 spr_register_kvm(env, SPR_LPCR, "LPCR",
7514 SPR_NOACCESS, SPR_NOACCESS,
7515 &spr_read_generic, &spr_write_generic,
7516 KVM_REG_PPC_LPCR, 0x00000000);
7517 #if !defined(CONFIG_USER_ONLY)
7518 env->slb_nr = 32;
7519 #endif
7520 init_excp_970(env);
7521 env->dcache_line_size = 128;
7522 env->icache_line_size = 128;
7523 /* Allocate hardware IRQ controller */
7524 ppc970_irq_init(env);
7525 /* Can't find information on what this should be on reset. This
7526 * value is the one used by 74xx processors. */
7527 vscr_init(env, 0x00010000);
7528 }
7529
7530 POWERPC_FAMILY(970MP)(ObjectClass *oc, void *data)
7531 {
7532 DeviceClass *dc = DEVICE_CLASS(oc);
7533 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7534
7535 dc->desc = "PowerPC 970 MP";
7536 pcc->init_proc = init_proc_970MP;
7537 pcc->check_pow = check_pow_970MP;
7538 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7539 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7540 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7541 PPC_FLOAT_STFIWX |
7542 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7543 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7544 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7545 PPC_64B | PPC_ALTIVEC |
7546 PPC_SEGMENT_64B | PPC_SLBI;
7547 pcc->msr_mask = (1ull << MSR_SF) |
7548 (1ull << MSR_SHV) |
7549 (1ull << MSR_VR) |
7550 (1ull << MSR_POW) |
7551 (1ull << MSR_EE) |
7552 (1ull << MSR_PR) |
7553 (1ull << MSR_FP) |
7554 (1ull << MSR_ME) |
7555 (1ull << MSR_FE0) |
7556 (1ull << MSR_SE) |
7557 (1ull << MSR_DE) |
7558 (1ull << MSR_FE1) |
7559 (1ull << MSR_IR) |
7560 (1ull << MSR_DR) |
7561 (1ull << MSR_PMM) |
7562 (1ull << MSR_RI);
7563 pcc->mmu_model = POWERPC_MMU_64B;
7564 #if defined(CONFIG_SOFTMMU)
7565 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7566 #endif
7567 pcc->excp_model = POWERPC_EXCP_970;
7568 pcc->bus_model = PPC_FLAGS_INPUT_970;
7569 pcc->bfd_mach = bfd_mach_ppc64;
7570 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7571 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7572 POWERPC_FLAG_BUS_CLK;
7573 pcc->l1_dcache_size = 0x8000;
7574 pcc->l1_icache_size = 0x10000;
7575 }
7576
7577 static void init_proc_power5plus(CPUPPCState *env)
7578 {
7579 gen_spr_ne_601(env);
7580 gen_spr_7xx(env);
7581 /* Time base */
7582 gen_tbl(env);
7583 /* Hardware implementation registers */
7584 /* XXX : not implemented */
7585 spr_register(env, SPR_HID0, "HID0",
7586 SPR_NOACCESS, SPR_NOACCESS,
7587 &spr_read_generic, &spr_write_clear,
7588 0x60000000);
7589 /* XXX : not implemented */
7590 spr_register(env, SPR_HID1, "HID1",
7591 SPR_NOACCESS, SPR_NOACCESS,
7592 &spr_read_generic, &spr_write_generic,
7593 0x00000000);
7594 /* XXX : not implemented */
7595 spr_register(env, SPR_970_HID5, "HID5",
7596 SPR_NOACCESS, SPR_NOACCESS,
7597 &spr_read_generic, &spr_write_generic,
7598 POWERPC970_HID5_INIT);
7599 /* Memory management */
7600 /* XXX: not correct */
7601 gen_low_BATs(env);
7602 spr_register(env, SPR_HIOR, "SPR_HIOR",
7603 SPR_NOACCESS, SPR_NOACCESS,
7604 &spr_read_hior, &spr_write_hior,
7605 0x00000000);
7606 spr_register(env, SPR_CTRL, "SPR_CTRL",
7607 SPR_NOACCESS, SPR_NOACCESS,
7608 SPR_NOACCESS, &spr_write_generic,
7609 0x00000000);
7610 spr_register(env, SPR_UCTRL, "SPR_UCTRL",
7611 SPR_NOACCESS, SPR_NOACCESS,
7612 &spr_read_generic, SPR_NOACCESS,
7613 0x00000000);
7614 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
7615 &spr_read_generic, &spr_write_generic,
7616 &spr_read_generic, &spr_write_generic,
7617 0x00000000);
7618 /* Logical partitionning */
7619 spr_register_kvm(env, SPR_LPCR, "LPCR",
7620 SPR_NOACCESS, SPR_NOACCESS,
7621 &spr_read_generic, &spr_write_generic,
7622 KVM_REG_PPC_LPCR, 0x00000000);
7623 #if !defined(CONFIG_USER_ONLY)
7624 env->slb_nr = 64;
7625 #endif
7626 init_excp_970(env);
7627 env->dcache_line_size = 128;
7628 env->icache_line_size = 128;
7629 /* Allocate hardware IRQ controller */
7630 ppc970_irq_init(env);
7631 /* Can't find information on what this should be on reset. This
7632 * value is the one used by 74xx processors. */
7633 vscr_init(env, 0x00010000);
7634 }
7635
7636 POWERPC_FAMILY(POWER5P)(ObjectClass *oc, void *data)
7637 {
7638 DeviceClass *dc = DEVICE_CLASS(oc);
7639 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7640
7641 dc->fw_name = "PowerPC,POWER5";
7642 dc->desc = "POWER5+";
7643 pcc->init_proc = init_proc_power5plus;
7644 pcc->check_pow = check_pow_970FX;
7645 pcc->insns_flags = PPC_INSNS_BASE | PPC_STRING | PPC_MFTB |
7646 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7647 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7648 PPC_FLOAT_STFIWX |
7649 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7650 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7651 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7652 PPC_64B |
7653 PPC_SEGMENT_64B | PPC_SLBI;
7654 pcc->msr_mask = (1ull << MSR_SF) |
7655 (1ull << MSR_VR) |
7656 (1ull << MSR_POW) |
7657 (1ull << MSR_EE) |
7658 (1ull << MSR_PR) |
7659 (1ull << MSR_FP) |
7660 (1ull << MSR_ME) |
7661 (1ull << MSR_FE0) |
7662 (1ull << MSR_SE) |
7663 (1ull << MSR_DE) |
7664 (1ull << MSR_FE1) |
7665 (1ull << MSR_IR) |
7666 (1ull << MSR_DR) |
7667 (1ull << MSR_PMM) |
7668 (1ull << MSR_RI);
7669 pcc->mmu_model = POWERPC_MMU_64B;
7670 #if defined(CONFIG_SOFTMMU)
7671 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7672 #endif
7673 pcc->excp_model = POWERPC_EXCP_970;
7674 pcc->bus_model = PPC_FLAGS_INPUT_970;
7675 pcc->bfd_mach = bfd_mach_ppc64;
7676 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7677 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7678 POWERPC_FLAG_BUS_CLK;
7679 pcc->l1_dcache_size = 0x8000;
7680 pcc->l1_icache_size = 0x10000;
7681 }
7682
7683 static void powerpc_get_compat(Object *obj, Visitor *v,
7684 void *opaque, const char *name, Error **errp)
7685 {
7686 char *value = (char *)"";
7687 Property *prop = opaque;
7688 uint32_t *max_compat = qdev_get_prop_ptr(DEVICE(obj), prop);
7689
7690 switch (*max_compat) {
7691 case CPU_POWERPC_LOGICAL_2_05:
7692 value = (char *)"power6";
7693 break;
7694 case CPU_POWERPC_LOGICAL_2_06:
7695 value = (char *)"power7";
7696 break;
7697 case CPU_POWERPC_LOGICAL_2_07:
7698 value = (char *)"power8";
7699 break;
7700 case 0:
7701 break;
7702 default:
7703 error_setg(errp, "Internal error: compat is set to %x",
7704 max_compat ? *max_compat : -1);
7705 break;
7706 }
7707
7708 visit_type_str(v, &value, name, errp);
7709 }
7710
7711 static void powerpc_set_compat(Object *obj, Visitor *v,
7712 void *opaque, const char *name, Error **errp)
7713 {
7714 Error *error = NULL;
7715 char *value = NULL;
7716 Property *prop = opaque;
7717 uint32_t *max_compat = qdev_get_prop_ptr(DEVICE(obj), prop);
7718
7719 visit_type_str(v, &value, name, &error);
7720 if (error) {
7721 error_propagate(errp, error);
7722 return;
7723 }
7724
7725 if (strcmp(value, "power6") == 0) {
7726 *max_compat = CPU_POWERPC_LOGICAL_2_05;
7727 } else if (strcmp(value, "power7") == 0) {
7728 *max_compat = CPU_POWERPC_LOGICAL_2_06;
7729 } else if (strcmp(value, "power8") == 0) {
7730 *max_compat = CPU_POWERPC_LOGICAL_2_07;
7731 } else {
7732 error_setg(errp, "Invalid compatibility mode \"%s\"", value);
7733 }
7734
7735 g_free(value);
7736 }
7737
7738 static PropertyInfo powerpc_compat_propinfo = {
7739 .name = "str",
7740 .legacy_name = "powerpc-server-compat",
7741 .get = powerpc_get_compat,
7742 .set = powerpc_set_compat,
7743 };
7744
7745 #define DEFINE_PROP_POWERPC_COMPAT(_n, _s, _f) \
7746 DEFINE_PROP(_n, _s, _f, powerpc_compat_propinfo, uint32_t)
7747
7748 static Property powerpc_servercpu_properties[] = {
7749 DEFINE_PROP_POWERPC_COMPAT("compat", PowerPCCPU, max_compat),
7750 DEFINE_PROP_END_OF_LIST(),
7751 };
7752
7753 static void init_proc_POWER7 (CPUPPCState *env)
7754 {
7755 gen_spr_ne_601(env);
7756 gen_spr_7xx(env);
7757 /* Time base */
7758 gen_tbl(env);
7759 /* Processor identification */
7760 spr_register(env, SPR_PIR, "PIR",
7761 SPR_NOACCESS, SPR_NOACCESS,
7762 &spr_read_generic, &spr_write_pir,
7763 0x00000000);
7764 #if !defined(CONFIG_USER_ONLY)
7765 /* PURR & SPURR: Hack - treat these as aliases for the TB for now */
7766 spr_register_kvm(env, SPR_PURR, "PURR",
7767 &spr_read_purr, SPR_NOACCESS,
7768 &spr_read_purr, SPR_NOACCESS,
7769 KVM_REG_PPC_PURR, 0x00000000);
7770 spr_register_kvm(env, SPR_SPURR, "SPURR",
7771 &spr_read_purr, SPR_NOACCESS,
7772 &spr_read_purr, SPR_NOACCESS,
7773 KVM_REG_PPC_SPURR, 0x00000000);
7774 spr_register(env, SPR_CFAR, "SPR_CFAR",
7775 SPR_NOACCESS, SPR_NOACCESS,
7776 &spr_read_cfar, &spr_write_cfar,
7777 0x00000000);
7778 spr_register_kvm(env, SPR_DSCR, "SPR_DSCR",
7779 SPR_NOACCESS, SPR_NOACCESS,
7780 &spr_read_generic, &spr_write_generic,
7781 KVM_REG_PPC_DSCR, 0x00000000);
7782 spr_register_kvm(env, SPR_MMCRA, "SPR_MMCRA",
7783 SPR_NOACCESS, SPR_NOACCESS,
7784 &spr_read_generic, &spr_write_generic,
7785 KVM_REG_PPC_MMCRA, 0x00000000);
7786 spr_register_kvm(env, SPR_PMC5, "SPR_PMC5",
7787 SPR_NOACCESS, SPR_NOACCESS,
7788 &spr_read_generic, &spr_write_generic,
7789 KVM_REG_PPC_PMC5, 0x00000000);
7790 spr_register_kvm(env, SPR_PMC6, "SPR_PMC6",
7791 SPR_NOACCESS, SPR_NOACCESS,
7792 &spr_read_generic, &spr_write_generic,
7793 KVM_REG_PPC_PMC6, 0x00000000);
7794 #endif /* !CONFIG_USER_ONLY */
7795 gen_spr_amr(env);
7796 /* XXX : not implemented */
7797 spr_register(env, SPR_CTRL, "SPR_CTRLT",
7798 SPR_NOACCESS, SPR_NOACCESS,
7799 SPR_NOACCESS, &spr_write_generic,
7800 0x80800000);
7801 spr_register(env, SPR_UCTRL, "SPR_CTRLF",
7802 SPR_NOACCESS, SPR_NOACCESS,
7803 &spr_read_generic, SPR_NOACCESS,
7804 0x80800000);
7805 spr_register(env, SPR_VRSAVE, "SPR_VRSAVE",
7806 &spr_read_generic, &spr_write_generic,
7807 &spr_read_generic, &spr_write_generic,
7808 0x00000000);
7809 spr_register(env, SPR_PPR, "PPR",
7810 &spr_read_generic, &spr_write_generic,
7811 &spr_read_generic, &spr_write_generic,
7812 0x00000000);
7813 /* Logical partitionning */
7814 spr_register_kvm(env, SPR_LPCR, "LPCR",
7815 SPR_NOACCESS, SPR_NOACCESS,
7816 &spr_read_generic, &spr_write_generic,
7817 KVM_REG_PPC_LPCR, 0x00000000);
7818 #if !defined(CONFIG_USER_ONLY)
7819 env->slb_nr = 32;
7820 #endif
7821 init_excp_POWER7(env);
7822 env->dcache_line_size = 128;
7823 env->icache_line_size = 128;
7824
7825 /* Allocate hardware IRQ controller */
7826 ppcPOWER7_irq_init(env);
7827 /* Can't find information on what this should be on reset. This
7828 * value is the one used by 74xx processors. */
7829 vscr_init(env, 0x00010000);
7830
7831 /*
7832 * Register PCR to report POWERPC_EXCP_PRIV_REG instead of
7833 * POWERPC_EXCP_INVAL_SPR.
7834 */
7835 spr_register(env, SPR_PCR, "PCR",
7836 SPR_NOACCESS, SPR_NOACCESS,
7837 SPR_NOACCESS, SPR_NOACCESS,
7838 0x00000000);
7839 }
7840
7841 POWERPC_FAMILY(POWER7)(ObjectClass *oc, void *data)
7842 {
7843 DeviceClass *dc = DEVICE_CLASS(oc);
7844 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7845
7846 dc->fw_name = "PowerPC,POWER7";
7847 dc->desc = "POWER7";
7848 dc->props = powerpc_servercpu_properties;
7849 pcc->pvr = CPU_POWERPC_POWER7_BASE;
7850 pcc->pvr_mask = CPU_POWERPC_POWER7_MASK;
7851 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06;
7852 pcc->init_proc = init_proc_POWER7;
7853 pcc->check_pow = check_pow_nocheck;
7854 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7855 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7856 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7857 PPC_FLOAT_FRSQRTES |
7858 PPC_FLOAT_STFIWX |
7859 PPC_FLOAT_EXT |
7860 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7861 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7862 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7863 PPC_64B | PPC_ALTIVEC |
7864 PPC_SEGMENT_64B | PPC_SLBI |
7865 PPC_POPCNTB | PPC_POPCNTWD;
7866 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
7867 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7868 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7869 PPC2_FP_TST_ISA206;
7870 pcc->msr_mask = (1ull << MSR_SF) |
7871 (1ull << MSR_VR) |
7872 (1ull << MSR_VSX) |
7873 (1ull << MSR_EE) |
7874 (1ull << MSR_PR) |
7875 (1ull << MSR_FP) |
7876 (1ull << MSR_ME) |
7877 (1ull << MSR_FE0) |
7878 (1ull << MSR_SE) |
7879 (1ull << MSR_DE) |
7880 (1ull << MSR_FE1) |
7881 (1ull << MSR_IR) |
7882 (1ull << MSR_DR) |
7883 (1ull << MSR_PMM) |
7884 (1ull << MSR_RI) |
7885 (1ull << MSR_LE);
7886 pcc->mmu_model = POWERPC_MMU_2_06;
7887 #if defined(CONFIG_SOFTMMU)
7888 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7889 #endif
7890 pcc->excp_model = POWERPC_EXCP_POWER7;
7891 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7892 pcc->bfd_mach = bfd_mach_ppc64;
7893 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7894 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7895 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7896 POWERPC_FLAG_VSX;
7897 pcc->l1_dcache_size = 0x8000;
7898 pcc->l1_icache_size = 0x8000;
7899 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
7900 }
7901
7902 POWERPC_FAMILY(POWER7P)(ObjectClass *oc, void *data)
7903 {
7904 DeviceClass *dc = DEVICE_CLASS(oc);
7905 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7906
7907 dc->fw_name = "PowerPC,POWER7+";
7908 dc->desc = "POWER7+";
7909 dc->props = powerpc_servercpu_properties;
7910 pcc->pvr = CPU_POWERPC_POWER7P_BASE;
7911 pcc->pvr_mask = CPU_POWERPC_POWER7P_MASK;
7912 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06;
7913 pcc->init_proc = init_proc_POWER7;
7914 pcc->check_pow = check_pow_nocheck;
7915 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7916 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7917 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7918 PPC_FLOAT_FRSQRTES |
7919 PPC_FLOAT_STFIWX |
7920 PPC_FLOAT_EXT |
7921 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7922 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7923 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7924 PPC_64B | PPC_ALTIVEC |
7925 PPC_SEGMENT_64B | PPC_SLBI |
7926 PPC_POPCNTB | PPC_POPCNTWD;
7927 pcc->insns_flags2 = PPC2_VSX | PPC2_DFP | PPC2_DBRX | PPC2_ISA205 |
7928 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
7929 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
7930 PPC2_FP_TST_ISA206;
7931 pcc->msr_mask = (1ull << MSR_SF) |
7932 (1ull << MSR_VR) |
7933 (1ull << MSR_VSX) |
7934 (1ull << MSR_EE) |
7935 (1ull << MSR_PR) |
7936 (1ull << MSR_FP) |
7937 (1ull << MSR_ME) |
7938 (1ull << MSR_FE0) |
7939 (1ull << MSR_SE) |
7940 (1ull << MSR_DE) |
7941 (1ull << MSR_FE1) |
7942 (1ull << MSR_IR) |
7943 (1ull << MSR_DR) |
7944 (1ull << MSR_PMM) |
7945 (1ull << MSR_RI) |
7946 (1ull << MSR_LE);
7947 pcc->mmu_model = POWERPC_MMU_2_06;
7948 #if defined(CONFIG_SOFTMMU)
7949 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
7950 #endif
7951 pcc->excp_model = POWERPC_EXCP_POWER7;
7952 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
7953 pcc->bfd_mach = bfd_mach_ppc64;
7954 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
7955 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
7956 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
7957 POWERPC_FLAG_VSX;
7958 pcc->l1_dcache_size = 0x8000;
7959 pcc->l1_icache_size = 0x8000;
7960 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
7961 }
7962
7963 static void init_proc_POWER8(CPUPPCState *env)
7964 {
7965 /* inherit P7 */
7966 init_proc_POWER7(env);
7967
7968 /* P8 supports the TAR */
7969 spr_register(env, SPR_TAR, "TAR",
7970 &spr_read_generic, &spr_write_generic,
7971 &spr_read_generic, &spr_write_generic,
7972 0x00000000);
7973 }
7974
7975 POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
7976 {
7977 DeviceClass *dc = DEVICE_CLASS(oc);
7978 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
7979
7980 dc->fw_name = "PowerPC,POWER8";
7981 dc->desc = "POWER8";
7982 dc->props = powerpc_servercpu_properties;
7983 pcc->pvr = CPU_POWERPC_POWER8_BASE;
7984 pcc->pvr_mask = CPU_POWERPC_POWER8_MASK;
7985 pcc->pcr_mask = PCR_COMPAT_2_05 | PCR_COMPAT_2_06;
7986 pcc->init_proc = init_proc_POWER8;
7987 pcc->check_pow = check_pow_nocheck;
7988 pcc->insns_flags = PPC_INSNS_BASE | PPC_ISEL | PPC_STRING | PPC_MFTB |
7989 PPC_FLOAT | PPC_FLOAT_FSEL | PPC_FLOAT_FRES |
7990 PPC_FLOAT_FSQRT | PPC_FLOAT_FRSQRTE |
7991 PPC_FLOAT_FRSQRTES |
7992 PPC_FLOAT_STFIWX |
7993 PPC_FLOAT_EXT |
7994 PPC_CACHE | PPC_CACHE_ICBI | PPC_CACHE_DCBZ |
7995 PPC_MEM_SYNC | PPC_MEM_EIEIO |
7996 PPC_MEM_TLBIE | PPC_MEM_TLBSYNC |
7997 PPC_64B | PPC_64BX | PPC_ALTIVEC |
7998 PPC_SEGMENT_64B | PPC_SLBI |
7999 PPC_POPCNTB | PPC_POPCNTWD;
8000 pcc->insns_flags2 = PPC2_VSX | PPC2_VSX207 | PPC2_DFP | PPC2_DBRX |
8001 PPC2_PERM_ISA206 | PPC2_DIVE_ISA206 |
8002 PPC2_ATOMIC_ISA206 | PPC2_FP_CVT_ISA206 |
8003 PPC2_FP_TST_ISA206 | PPC2_BCTAR_ISA207 |
8004 PPC2_LSQ_ISA207 | PPC2_ALTIVEC_207 |
8005 PPC2_ISA205 | PPC2_ISA207S;
8006 pcc->msr_mask = (1ull << MSR_SF) |
8007 (1ull << MSR_VR) |
8008 (1ull << MSR_VSX) |
8009 (1ull << MSR_EE) |
8010 (1ull << MSR_PR) |
8011 (1ull << MSR_FP) |
8012 (1ull << MSR_ME) |
8013 (1ull << MSR_FE0) |
8014 (1ull << MSR_SE) |
8015 (1ull << MSR_DE) |
8016 (1ull << MSR_FE1) |
8017 (1ull << MSR_IR) |
8018 (1ull << MSR_DR) |
8019 (1ull << MSR_PMM) |
8020 (1ull << MSR_RI) |
8021 (1ull << MSR_LE);
8022 pcc->mmu_model = POWERPC_MMU_2_06;
8023 #if defined(CONFIG_SOFTMMU)
8024 pcc->handle_mmu_fault = ppc_hash64_handle_mmu_fault;
8025 #endif
8026 pcc->excp_model = POWERPC_EXCP_POWER7;
8027 pcc->bus_model = PPC_FLAGS_INPUT_POWER7;
8028 pcc->bfd_mach = bfd_mach_ppc64;
8029 pcc->flags = POWERPC_FLAG_VRE | POWERPC_FLAG_SE |
8030 POWERPC_FLAG_BE | POWERPC_FLAG_PMM |
8031 POWERPC_FLAG_BUS_CLK | POWERPC_FLAG_CFAR |
8032 POWERPC_FLAG_VSX;
8033 pcc->l1_dcache_size = 0x8000;
8034 pcc->l1_icache_size = 0x8000;
8035 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_lpcr;
8036 }
8037 #endif /* defined (TARGET_PPC64) */
8038
8039
8040 /*****************************************************************************/
8041 /* Generic CPU instantiation routine */
8042 static void init_ppc_proc(PowerPCCPU *cpu)
8043 {
8044 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8045 CPUPPCState *env = &cpu->env;
8046 #if !defined(CONFIG_USER_ONLY)
8047 int i;
8048
8049 env->irq_inputs = NULL;
8050 /* Set all exception vectors to an invalid address */
8051 for (i = 0; i < POWERPC_EXCP_NB; i++)
8052 env->excp_vectors[i] = (target_ulong)(-1ULL);
8053 env->ivor_mask = 0x00000000;
8054 env->ivpr_mask = 0x00000000;
8055 /* Default MMU definitions */
8056 env->nb_BATs = 0;
8057 env->nb_tlb = 0;
8058 env->nb_ways = 0;
8059 env->tlb_type = TLB_NONE;
8060 #endif
8061 /* Register SPR common to all PowerPC implementations */
8062 gen_spr_generic(env);
8063 spr_register(env, SPR_PVR, "PVR",
8064 /* Linux permits userspace to read PVR */
8065 #if defined(CONFIG_LINUX_USER)
8066 &spr_read_generic,
8067 #else
8068 SPR_NOACCESS,
8069 #endif
8070 SPR_NOACCESS,
8071 &spr_read_generic, SPR_NOACCESS,
8072 pcc->pvr);
8073 /* Register SVR if it's defined to anything else than POWERPC_SVR_NONE */
8074 if (pcc->svr != POWERPC_SVR_NONE) {
8075 if (pcc->svr & POWERPC_SVR_E500) {
8076 spr_register(env, SPR_E500_SVR, "SVR",
8077 SPR_NOACCESS, SPR_NOACCESS,
8078 &spr_read_generic, SPR_NOACCESS,
8079 pcc->svr & ~POWERPC_SVR_E500);
8080 } else {
8081 spr_register(env, SPR_SVR, "SVR",
8082 SPR_NOACCESS, SPR_NOACCESS,
8083 &spr_read_generic, SPR_NOACCESS,
8084 pcc->svr);
8085 }
8086 }
8087 /* PowerPC implementation specific initialisations (SPRs, timers, ...) */
8088 (*pcc->init_proc)(env);
8089
8090 /* MSR bits & flags consistency checks */
8091 if (env->msr_mask & (1 << 25)) {
8092 switch (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8093 case POWERPC_FLAG_SPE:
8094 case POWERPC_FLAG_VRE:
8095 break;
8096 default:
8097 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8098 "Should define POWERPC_FLAG_SPE or POWERPC_FLAG_VRE\n");
8099 exit(1);
8100 }
8101 } else if (env->flags & (POWERPC_FLAG_SPE | POWERPC_FLAG_VRE)) {
8102 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8103 "Should not define POWERPC_FLAG_SPE nor POWERPC_FLAG_VRE\n");
8104 exit(1);
8105 }
8106 if (env->msr_mask & (1 << 17)) {
8107 switch (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8108 case POWERPC_FLAG_TGPR:
8109 case POWERPC_FLAG_CE:
8110 break;
8111 default:
8112 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8113 "Should define POWERPC_FLAG_TGPR or POWERPC_FLAG_CE\n");
8114 exit(1);
8115 }
8116 } else if (env->flags & (POWERPC_FLAG_TGPR | POWERPC_FLAG_CE)) {
8117 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8118 "Should not define POWERPC_FLAG_TGPR nor POWERPC_FLAG_CE\n");
8119 exit(1);
8120 }
8121 if (env->msr_mask & (1 << 10)) {
8122 switch (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8123 POWERPC_FLAG_UBLE)) {
8124 case POWERPC_FLAG_SE:
8125 case POWERPC_FLAG_DWE:
8126 case POWERPC_FLAG_UBLE:
8127 break;
8128 default:
8129 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8130 "Should define POWERPC_FLAG_SE or POWERPC_FLAG_DWE or "
8131 "POWERPC_FLAG_UBLE\n");
8132 exit(1);
8133 }
8134 } else if (env->flags & (POWERPC_FLAG_SE | POWERPC_FLAG_DWE |
8135 POWERPC_FLAG_UBLE)) {
8136 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8137 "Should not define POWERPC_FLAG_SE nor POWERPC_FLAG_DWE nor "
8138 "POWERPC_FLAG_UBLE\n");
8139 exit(1);
8140 }
8141 if (env->msr_mask & (1 << 9)) {
8142 switch (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8143 case POWERPC_FLAG_BE:
8144 case POWERPC_FLAG_DE:
8145 break;
8146 default:
8147 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8148 "Should define POWERPC_FLAG_BE or POWERPC_FLAG_DE\n");
8149 exit(1);
8150 }
8151 } else if (env->flags & (POWERPC_FLAG_BE | POWERPC_FLAG_DE)) {
8152 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8153 "Should not define POWERPC_FLAG_BE nor POWERPC_FLAG_DE\n");
8154 exit(1);
8155 }
8156 if (env->msr_mask & (1 << 2)) {
8157 switch (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8158 case POWERPC_FLAG_PX:
8159 case POWERPC_FLAG_PMM:
8160 break;
8161 default:
8162 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8163 "Should define POWERPC_FLAG_PX or POWERPC_FLAG_PMM\n");
8164 exit(1);
8165 }
8166 } else if (env->flags & (POWERPC_FLAG_PX | POWERPC_FLAG_PMM)) {
8167 fprintf(stderr, "PowerPC MSR definition inconsistency\n"
8168 "Should not define POWERPC_FLAG_PX nor POWERPC_FLAG_PMM\n");
8169 exit(1);
8170 }
8171 if ((env->flags & (POWERPC_FLAG_RTC_CLK | POWERPC_FLAG_BUS_CLK)) == 0) {
8172 fprintf(stderr, "PowerPC flags inconsistency\n"
8173 "Should define the time-base and decrementer clock source\n");
8174 exit(1);
8175 }
8176 /* Allocate TLBs buffer when needed */
8177 #if !defined(CONFIG_USER_ONLY)
8178 if (env->nb_tlb != 0) {
8179 int nb_tlb = env->nb_tlb;
8180 if (env->id_tlbs != 0)
8181 nb_tlb *= 2;
8182 switch (env->tlb_type) {
8183 case TLB_6XX:
8184 env->tlb.tlb6 = g_malloc0(nb_tlb * sizeof(ppc6xx_tlb_t));
8185 break;
8186 case TLB_EMB:
8187 env->tlb.tlbe = g_malloc0(nb_tlb * sizeof(ppcemb_tlb_t));
8188 break;
8189 case TLB_MAS:
8190 env->tlb.tlbm = g_malloc0(nb_tlb * sizeof(ppcmas_tlb_t));
8191 break;
8192 }
8193 /* Pre-compute some useful values */
8194 env->tlb_per_way = env->nb_tlb / env->nb_ways;
8195 }
8196 if (env->irq_inputs == NULL) {
8197 fprintf(stderr, "WARNING: no internal IRQ controller registered.\n"
8198 " Attempt QEMU to crash very soon !\n");
8199 }
8200 #endif
8201 if (env->check_pow == NULL) {
8202 fprintf(stderr, "WARNING: no power management check handler "
8203 "registered.\n"
8204 " Attempt QEMU to crash very soon !\n");
8205 }
8206 }
8207
8208 #if defined(PPC_DUMP_CPU)
8209 static void dump_ppc_sprs (CPUPPCState *env)
8210 {
8211 ppc_spr_t *spr;
8212 #if !defined(CONFIG_USER_ONLY)
8213 uint32_t sr, sw;
8214 #endif
8215 uint32_t ur, uw;
8216 int i, j, n;
8217
8218 printf("Special purpose registers:\n");
8219 for (i = 0; i < 32; i++) {
8220 for (j = 0; j < 32; j++) {
8221 n = (i << 5) | j;
8222 spr = &env->spr_cb[n];
8223 uw = spr->uea_write != NULL && spr->uea_write != SPR_NOACCESS;
8224 ur = spr->uea_read != NULL && spr->uea_read != SPR_NOACCESS;
8225 #if !defined(CONFIG_USER_ONLY)
8226 sw = spr->oea_write != NULL && spr->oea_write != SPR_NOACCESS;
8227 sr = spr->oea_read != NULL && spr->oea_read != SPR_NOACCESS;
8228 if (sw || sr || uw || ur) {
8229 printf("SPR: %4d (%03x) %-8s s%c%c u%c%c\n",
8230 (i << 5) | j, (i << 5) | j, spr->name,
8231 sw ? 'w' : '-', sr ? 'r' : '-',
8232 uw ? 'w' : '-', ur ? 'r' : '-');
8233 }
8234 #else
8235 if (uw || ur) {
8236 printf("SPR: %4d (%03x) %-8s u%c%c\n",
8237 (i << 5) | j, (i << 5) | j, spr->name,
8238 uw ? 'w' : '-', ur ? 'r' : '-');
8239 }
8240 #endif
8241 }
8242 }
8243 fflush(stdout);
8244 fflush(stderr);
8245 }
8246 #endif
8247
8248 /*****************************************************************************/
8249 #include <stdlib.h>
8250 #include <string.h>
8251
8252 /* Opcode types */
8253 enum {
8254 PPC_DIRECT = 0, /* Opcode routine */
8255 PPC_INDIRECT = 1, /* Indirect opcode table */
8256 };
8257
8258 static inline int is_indirect_opcode (void *handler)
8259 {
8260 return ((uintptr_t)handler & 0x03) == PPC_INDIRECT;
8261 }
8262
8263 static inline opc_handler_t **ind_table(void *handler)
8264 {
8265 return (opc_handler_t **)((uintptr_t)handler & ~3);
8266 }
8267
8268 /* Instruction table creation */
8269 /* Opcodes tables creation */
8270 static void fill_new_table (opc_handler_t **table, int len)
8271 {
8272 int i;
8273
8274 for (i = 0; i < len; i++)
8275 table[i] = &invalid_handler;
8276 }
8277
8278 static int create_new_table (opc_handler_t **table, unsigned char idx)
8279 {
8280 opc_handler_t **tmp;
8281
8282 tmp = g_new(opc_handler_t *, 0x20);
8283 fill_new_table(tmp, 0x20);
8284 table[idx] = (opc_handler_t *)((uintptr_t)tmp | PPC_INDIRECT);
8285
8286 return 0;
8287 }
8288
8289 static int insert_in_table (opc_handler_t **table, unsigned char idx,
8290 opc_handler_t *handler)
8291 {
8292 if (table[idx] != &invalid_handler)
8293 return -1;
8294 table[idx] = handler;
8295
8296 return 0;
8297 }
8298
8299 static int register_direct_insn (opc_handler_t **ppc_opcodes,
8300 unsigned char idx, opc_handler_t *handler)
8301 {
8302 if (insert_in_table(ppc_opcodes, idx, handler) < 0) {
8303 printf("*** ERROR: opcode %02x already assigned in main "
8304 "opcode table\n", idx);
8305 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8306 printf(" Registered handler '%s' - new handler '%s'\n",
8307 ppc_opcodes[idx]->oname, handler->oname);
8308 #endif
8309 return -1;
8310 }
8311
8312 return 0;
8313 }
8314
8315 static int register_ind_in_table (opc_handler_t **table,
8316 unsigned char idx1, unsigned char idx2,
8317 opc_handler_t *handler)
8318 {
8319 if (table[idx1] == &invalid_handler) {
8320 if (create_new_table(table, idx1) < 0) {
8321 printf("*** ERROR: unable to create indirect table "
8322 "idx=%02x\n", idx1);
8323 return -1;
8324 }
8325 } else {
8326 if (!is_indirect_opcode(table[idx1])) {
8327 printf("*** ERROR: idx %02x already assigned to a direct "
8328 "opcode\n", idx1);
8329 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8330 printf(" Registered handler '%s' - new handler '%s'\n",
8331 ind_table(table[idx1])[idx2]->oname, handler->oname);
8332 #endif
8333 return -1;
8334 }
8335 }
8336 if (handler != NULL &&
8337 insert_in_table(ind_table(table[idx1]), idx2, handler) < 0) {
8338 printf("*** ERROR: opcode %02x already assigned in "
8339 "opcode table %02x\n", idx2, idx1);
8340 #if defined(DO_PPC_STATISTICS) || defined(PPC_DUMP_CPU)
8341 printf(" Registered handler '%s' - new handler '%s'\n",
8342 ind_table(table[idx1])[idx2]->oname, handler->oname);
8343 #endif
8344 return -1;
8345 }
8346
8347 return 0;
8348 }
8349
8350 static int register_ind_insn (opc_handler_t **ppc_opcodes,
8351 unsigned char idx1, unsigned char idx2,
8352 opc_handler_t *handler)
8353 {
8354 int ret;
8355
8356 ret = register_ind_in_table(ppc_opcodes, idx1, idx2, handler);
8357
8358 return ret;
8359 }
8360
8361 static int register_dblind_insn (opc_handler_t **ppc_opcodes,
8362 unsigned char idx1, unsigned char idx2,
8363 unsigned char idx3, opc_handler_t *handler)
8364 {
8365 if (register_ind_in_table(ppc_opcodes, idx1, idx2, NULL) < 0) {
8366 printf("*** ERROR: unable to join indirect table idx "
8367 "[%02x-%02x]\n", idx1, idx2);
8368 return -1;
8369 }
8370 if (register_ind_in_table(ind_table(ppc_opcodes[idx1]), idx2, idx3,
8371 handler) < 0) {
8372 printf("*** ERROR: unable to insert opcode "
8373 "[%02x-%02x-%02x]\n", idx1, idx2, idx3);
8374 return -1;
8375 }
8376
8377 return 0;
8378 }
8379
8380 static int register_insn (opc_handler_t **ppc_opcodes, opcode_t *insn)
8381 {
8382 if (insn->opc2 != 0xFF) {
8383 if (insn->opc3 != 0xFF) {
8384 if (register_dblind_insn(ppc_opcodes, insn->opc1, insn->opc2,
8385 insn->opc3, &insn->handler) < 0)
8386 return -1;
8387 } else {
8388 if (register_ind_insn(ppc_opcodes, insn->opc1,
8389 insn->opc2, &insn->handler) < 0)
8390 return -1;
8391 }
8392 } else {
8393 if (register_direct_insn(ppc_opcodes, insn->opc1, &insn->handler) < 0)
8394 return -1;
8395 }
8396
8397 return 0;
8398 }
8399
8400 static int test_opcode_table (opc_handler_t **table, int len)
8401 {
8402 int i, count, tmp;
8403
8404 for (i = 0, count = 0; i < len; i++) {
8405 /* Consistency fixup */
8406 if (table[i] == NULL)
8407 table[i] = &invalid_handler;
8408 if (table[i] != &invalid_handler) {
8409 if (is_indirect_opcode(table[i])) {
8410 tmp = test_opcode_table(ind_table(table[i]), 0x20);
8411 if (tmp == 0) {
8412 free(table[i]);
8413 table[i] = &invalid_handler;
8414 } else {
8415 count++;
8416 }
8417 } else {
8418 count++;
8419 }
8420 }
8421 }
8422
8423 return count;
8424 }
8425
8426 static void fix_opcode_tables (opc_handler_t **ppc_opcodes)
8427 {
8428 if (test_opcode_table(ppc_opcodes, 0x40) == 0)
8429 printf("*** WARNING: no opcode defined !\n");
8430 }
8431
8432 /*****************************************************************************/
8433 static void create_ppc_opcodes(PowerPCCPU *cpu, Error **errp)
8434 {
8435 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8436 CPUPPCState *env = &cpu->env;
8437 opcode_t *opc;
8438
8439 fill_new_table(env->opcodes, 0x40);
8440 for (opc = opcodes; opc < &opcodes[ARRAY_SIZE(opcodes)]; opc++) {
8441 if (((opc->handler.type & pcc->insns_flags) != 0) ||
8442 ((opc->handler.type2 & pcc->insns_flags2) != 0)) {
8443 if (register_insn(env->opcodes, opc) < 0) {
8444 error_setg(errp, "ERROR initializing PowerPC instruction "
8445 "0x%02x 0x%02x 0x%02x", opc->opc1, opc->opc2,
8446 opc->opc3);
8447 return;
8448 }
8449 }
8450 }
8451 fix_opcode_tables(env->opcodes);
8452 fflush(stdout);
8453 fflush(stderr);
8454 }
8455
8456 #if defined(PPC_DUMP_CPU)
8457 static void dump_ppc_insns (CPUPPCState *env)
8458 {
8459 opc_handler_t **table, *handler;
8460 const char *p, *q;
8461 uint8_t opc1, opc2, opc3;
8462
8463 printf("Instructions set:\n");
8464 /* opc1 is 6 bits long */
8465 for (opc1 = 0x00; opc1 < 0x40; opc1++) {
8466 table = env->opcodes;
8467 handler = table[opc1];
8468 if (is_indirect_opcode(handler)) {
8469 /* opc2 is 5 bits long */
8470 for (opc2 = 0; opc2 < 0x20; opc2++) {
8471 table = env->opcodes;
8472 handler = env->opcodes[opc1];
8473 table = ind_table(handler);
8474 handler = table[opc2];
8475 if (is_indirect_opcode(handler)) {
8476 table = ind_table(handler);
8477 /* opc3 is 5 bits long */
8478 for (opc3 = 0; opc3 < 0x20; opc3++) {
8479 handler = table[opc3];
8480 if (handler->handler != &gen_invalid) {
8481 /* Special hack to properly dump SPE insns */
8482 p = strchr(handler->oname, '_');
8483 if (p == NULL) {
8484 printf("INSN: %02x %02x %02x (%02d %04d) : "
8485 "%s\n",
8486 opc1, opc2, opc3, opc1,
8487 (opc3 << 5) | opc2,
8488 handler->oname);
8489 } else {
8490 q = "speundef";
8491 if ((p - handler->oname) != strlen(q) ||
8492 memcmp(handler->oname, q, strlen(q)) != 0) {
8493 /* First instruction */
8494 printf("INSN: %02x %02x %02x (%02d %04d) : "
8495 "%.*s\n",
8496 opc1, opc2 << 1, opc3, opc1,
8497 (opc3 << 6) | (opc2 << 1),
8498 (int)(p - handler->oname),
8499 handler->oname);
8500 }
8501 if (strcmp(p + 1, q) != 0) {
8502 /* Second instruction */
8503 printf("INSN: %02x %02x %02x (%02d %04d) : "
8504 "%s\n",
8505 opc1, (opc2 << 1) | 1, opc3, opc1,
8506 (opc3 << 6) | (opc2 << 1) | 1,
8507 p + 1);
8508 }
8509 }
8510 }
8511 }
8512 } else {
8513 if (handler->handler != &gen_invalid) {
8514 printf("INSN: %02x %02x -- (%02d %04d) : %s\n",
8515 opc1, opc2, opc1, opc2, handler->oname);
8516 }
8517 }
8518 }
8519 } else {
8520 if (handler->handler != &gen_invalid) {
8521 printf("INSN: %02x -- -- (%02d ----) : %s\n",
8522 opc1, opc1, handler->oname);
8523 }
8524 }
8525 }
8526 }
8527 #endif
8528
8529 static int gdb_get_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8530 {
8531 if (n < 32) {
8532 stfq_p(mem_buf, env->fpr[n]);
8533 return 8;
8534 }
8535 if (n == 32) {
8536 stl_p(mem_buf, env->fpscr);
8537 return 4;
8538 }
8539 return 0;
8540 }
8541
8542 static int gdb_set_float_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8543 {
8544 if (n < 32) {
8545 env->fpr[n] = ldfq_p(mem_buf);
8546 return 8;
8547 }
8548 if (n == 32) {
8549 helper_store_fpscr(env, ldl_p(mem_buf), 0xffffffff);
8550 return 4;
8551 }
8552 return 0;
8553 }
8554
8555 static int gdb_get_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8556 {
8557 if (n < 32) {
8558 #ifdef HOST_WORDS_BIGENDIAN
8559 stq_p(mem_buf, env->avr[n].u64[0]);
8560 stq_p(mem_buf+8, env->avr[n].u64[1]);
8561 #else
8562 stq_p(mem_buf, env->avr[n].u64[1]);
8563 stq_p(mem_buf+8, env->avr[n].u64[0]);
8564 #endif
8565 return 16;
8566 }
8567 if (n == 32) {
8568 stl_p(mem_buf, env->vscr);
8569 return 4;
8570 }
8571 if (n == 33) {
8572 stl_p(mem_buf, (uint32_t)env->spr[SPR_VRSAVE]);
8573 return 4;
8574 }
8575 return 0;
8576 }
8577
8578 static int gdb_set_avr_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8579 {
8580 if (n < 32) {
8581 #ifdef HOST_WORDS_BIGENDIAN
8582 env->avr[n].u64[0] = ldq_p(mem_buf);
8583 env->avr[n].u64[1] = ldq_p(mem_buf+8);
8584 #else
8585 env->avr[n].u64[1] = ldq_p(mem_buf);
8586 env->avr[n].u64[0] = ldq_p(mem_buf+8);
8587 #endif
8588 return 16;
8589 }
8590 if (n == 32) {
8591 env->vscr = ldl_p(mem_buf);
8592 return 4;
8593 }
8594 if (n == 33) {
8595 env->spr[SPR_VRSAVE] = (target_ulong)ldl_p(mem_buf);
8596 return 4;
8597 }
8598 return 0;
8599 }
8600
8601 static int gdb_get_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8602 {
8603 if (n < 32) {
8604 #if defined(TARGET_PPC64)
8605 stl_p(mem_buf, env->gpr[n] >> 32);
8606 #else
8607 stl_p(mem_buf, env->gprh[n]);
8608 #endif
8609 return 4;
8610 }
8611 if (n == 32) {
8612 stq_p(mem_buf, env->spe_acc);
8613 return 8;
8614 }
8615 if (n == 33) {
8616 stl_p(mem_buf, env->spe_fscr);
8617 return 4;
8618 }
8619 return 0;
8620 }
8621
8622 static int gdb_set_spe_reg(CPUPPCState *env, uint8_t *mem_buf, int n)
8623 {
8624 if (n < 32) {
8625 #if defined(TARGET_PPC64)
8626 target_ulong lo = (uint32_t)env->gpr[n];
8627 target_ulong hi = (target_ulong)ldl_p(mem_buf) << 32;
8628 env->gpr[n] = lo | hi;
8629 #else
8630 env->gprh[n] = ldl_p(mem_buf);
8631 #endif
8632 return 4;
8633 }
8634 if (n == 32) {
8635 env->spe_acc = ldq_p(mem_buf);
8636 return 8;
8637 }
8638 if (n == 33) {
8639 env->spe_fscr = ldl_p(mem_buf);
8640 return 4;
8641 }
8642 return 0;
8643 }
8644
8645 static int ppc_fixup_cpu(PowerPCCPU *cpu)
8646 {
8647 CPUPPCState *env = &cpu->env;
8648
8649 /* TCG doesn't (yet) emulate some groups of instructions that
8650 * are implemented on some otherwise supported CPUs (e.g. VSX
8651 * and decimal floating point instructions on POWER7). We
8652 * remove unsupported instruction groups from the cpu state's
8653 * instruction masks and hope the guest can cope. For at
8654 * least the pseries machine, the unavailability of these
8655 * instructions can be advertised to the guest via the device
8656 * tree. */
8657 if ((env->insns_flags & ~PPC_TCG_INSNS)
8658 || (env->insns_flags2 & ~PPC_TCG_INSNS2)) {
8659 fprintf(stderr, "Warning: Disabling some instructions which are not "
8660 "emulated by TCG (0x%" PRIx64 ", 0x%" PRIx64 ")\n",
8661 env->insns_flags & ~PPC_TCG_INSNS,
8662 env->insns_flags2 & ~PPC_TCG_INSNS2);
8663 }
8664 env->insns_flags &= PPC_TCG_INSNS;
8665 env->insns_flags2 &= PPC_TCG_INSNS2;
8666 return 0;
8667 }
8668
8669 static inline bool ppc_cpu_is_valid(PowerPCCPUClass *pcc)
8670 {
8671 #ifdef TARGET_PPCEMB
8672 return pcc->mmu_model == POWERPC_MMU_BOOKE ||
8673 pcc->mmu_model == POWERPC_MMU_SOFT_4xx ||
8674 pcc->mmu_model == POWERPC_MMU_SOFT_4xx_Z;
8675 #else
8676 return true;
8677 #endif
8678 }
8679
8680 static void ppc_cpu_realizefn(DeviceState *dev, Error **errp)
8681 {
8682 CPUState *cs = CPU(dev);
8683 PowerPCCPU *cpu = POWERPC_CPU(dev);
8684 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8685 Error *local_err = NULL;
8686 #if !defined(CONFIG_USER_ONLY)
8687 int max_smt = kvm_enabled() ? kvmppc_smt_threads() : 1;
8688 #endif
8689
8690 #if !defined(CONFIG_USER_ONLY)
8691 if (smp_threads > max_smt) {
8692 error_setg(errp, "Cannot support more than %d threads on PPC with %s",
8693 max_smt, kvm_enabled() ? "KVM" : "TCG");
8694 return;
8695 }
8696 if (!is_power_of_2(smp_threads)) {
8697 error_setg(errp, "Cannot support %d threads on PPC with %s, "
8698 "threads count must be a power of 2.",
8699 smp_threads, kvm_enabled() ? "KVM" : "TCG");
8700 return;
8701 }
8702
8703 cpu->cpu_dt_id = (cs->cpu_index / smp_threads) * max_smt
8704 + (cs->cpu_index % smp_threads);
8705 #endif
8706
8707 if (tcg_enabled()) {
8708 if (ppc_fixup_cpu(cpu) != 0) {
8709 error_setg(errp, "Unable to emulate selected CPU with TCG");
8710 return;
8711 }
8712 }
8713
8714 #if defined(TARGET_PPCEMB)
8715 if (!ppc_cpu_is_valid(pcc)) {
8716 error_setg(errp, "CPU does not possess a BookE or 4xx MMU. "
8717 "Please use qemu-system-ppc or qemu-system-ppc64 instead "
8718 "or choose another CPU model.");
8719 return;
8720 }
8721 #endif
8722
8723 create_ppc_opcodes(cpu, &local_err);
8724 if (local_err != NULL) {
8725 error_propagate(errp, local_err);
8726 return;
8727 }
8728 init_ppc_proc(cpu);
8729
8730 if (pcc->insns_flags & PPC_FLOAT) {
8731 gdb_register_coprocessor(cs, gdb_get_float_reg, gdb_set_float_reg,
8732 33, "power-fpu.xml", 0);
8733 }
8734 if (pcc->insns_flags & PPC_ALTIVEC) {
8735 gdb_register_coprocessor(cs, gdb_get_avr_reg, gdb_set_avr_reg,
8736 34, "power-altivec.xml", 0);
8737 }
8738 if (pcc->insns_flags & PPC_SPE) {
8739 gdb_register_coprocessor(cs, gdb_get_spe_reg, gdb_set_spe_reg,
8740 34, "power-spe.xml", 0);
8741 }
8742
8743 qemu_init_vcpu(cs);
8744
8745 pcc->parent_realize(dev, errp);
8746
8747 #if defined(PPC_DUMP_CPU)
8748 {
8749 CPUPPCState *env = &cpu->env;
8750 const char *mmu_model, *excp_model, *bus_model;
8751 switch (env->mmu_model) {
8752 case POWERPC_MMU_32B:
8753 mmu_model = "PowerPC 32";
8754 break;
8755 case POWERPC_MMU_SOFT_6xx:
8756 mmu_model = "PowerPC 6xx/7xx with software driven TLBs";
8757 break;
8758 case POWERPC_MMU_SOFT_74xx:
8759 mmu_model = "PowerPC 74xx with software driven TLBs";
8760 break;
8761 case POWERPC_MMU_SOFT_4xx:
8762 mmu_model = "PowerPC 4xx with software driven TLBs";
8763 break;
8764 case POWERPC_MMU_SOFT_4xx_Z:
8765 mmu_model = "PowerPC 4xx with software driven TLBs "
8766 "and zones protections";
8767 break;
8768 case POWERPC_MMU_REAL:
8769 mmu_model = "PowerPC real mode only";
8770 break;
8771 case POWERPC_MMU_MPC8xx:
8772 mmu_model = "PowerPC MPC8xx";
8773 break;
8774 case POWERPC_MMU_BOOKE:
8775 mmu_model = "PowerPC BookE";
8776 break;
8777 case POWERPC_MMU_BOOKE206:
8778 mmu_model = "PowerPC BookE 2.06";
8779 break;
8780 case POWERPC_MMU_601:
8781 mmu_model = "PowerPC 601";
8782 break;
8783 #if defined (TARGET_PPC64)
8784 case POWERPC_MMU_64B:
8785 mmu_model = "PowerPC 64";
8786 break;
8787 #endif
8788 default:
8789 mmu_model = "Unknown or invalid";
8790 break;
8791 }
8792 switch (env->excp_model) {
8793 case POWERPC_EXCP_STD:
8794 excp_model = "PowerPC";
8795 break;
8796 case POWERPC_EXCP_40x:
8797 excp_model = "PowerPC 40x";
8798 break;
8799 case POWERPC_EXCP_601:
8800 excp_model = "PowerPC 601";
8801 break;
8802 case POWERPC_EXCP_602:
8803 excp_model = "PowerPC 602";
8804 break;
8805 case POWERPC_EXCP_603:
8806 excp_model = "PowerPC 603";
8807 break;
8808 case POWERPC_EXCP_603E:
8809 excp_model = "PowerPC 603e";
8810 break;
8811 case POWERPC_EXCP_604:
8812 excp_model = "PowerPC 604";
8813 break;
8814 case POWERPC_EXCP_7x0:
8815 excp_model = "PowerPC 740/750";
8816 break;
8817 case POWERPC_EXCP_7x5:
8818 excp_model = "PowerPC 745/755";
8819 break;
8820 case POWERPC_EXCP_74xx:
8821 excp_model = "PowerPC 74xx";
8822 break;
8823 case POWERPC_EXCP_BOOKE:
8824 excp_model = "PowerPC BookE";
8825 break;
8826 #if defined (TARGET_PPC64)
8827 case POWERPC_EXCP_970:
8828 excp_model = "PowerPC 970";
8829 break;
8830 #endif
8831 default:
8832 excp_model = "Unknown or invalid";
8833 break;
8834 }
8835 switch (env->bus_model) {
8836 case PPC_FLAGS_INPUT_6xx:
8837 bus_model = "PowerPC 6xx";
8838 break;
8839 case PPC_FLAGS_INPUT_BookE:
8840 bus_model = "PowerPC BookE";
8841 break;
8842 case PPC_FLAGS_INPUT_405:
8843 bus_model = "PowerPC 405";
8844 break;
8845 case PPC_FLAGS_INPUT_401:
8846 bus_model = "PowerPC 401/403";
8847 break;
8848 case PPC_FLAGS_INPUT_RCPU:
8849 bus_model = "RCPU / MPC8xx";
8850 break;
8851 #if defined (TARGET_PPC64)
8852 case PPC_FLAGS_INPUT_970:
8853 bus_model = "PowerPC 970";
8854 break;
8855 #endif
8856 default:
8857 bus_model = "Unknown or invalid";
8858 break;
8859 }
8860 printf("PowerPC %-12s : PVR %08x MSR %016" PRIx64 "\n"
8861 " MMU model : %s\n",
8862 object_class_get_name(OBJECT_CLASS(pcc)),
8863 pcc->pvr, pcc->msr_mask, mmu_model);
8864 #if !defined(CONFIG_USER_ONLY)
8865 if (env->tlb.tlb6) {
8866 printf(" %d %s TLB in %d ways\n",
8867 env->nb_tlb, env->id_tlbs ? "splitted" : "merged",
8868 env->nb_ways);
8869 }
8870 #endif
8871 printf(" Exceptions model : %s\n"
8872 " Bus model : %s\n",
8873 excp_model, bus_model);
8874 printf(" MSR features :\n");
8875 if (env->flags & POWERPC_FLAG_SPE)
8876 printf(" signal processing engine enable"
8877 "\n");
8878 else if (env->flags & POWERPC_FLAG_VRE)
8879 printf(" vector processor enable\n");
8880 if (env->flags & POWERPC_FLAG_TGPR)
8881 printf(" temporary GPRs\n");
8882 else if (env->flags & POWERPC_FLAG_CE)
8883 printf(" critical input enable\n");
8884 if (env->flags & POWERPC_FLAG_SE)
8885 printf(" single-step trace mode\n");
8886 else if (env->flags & POWERPC_FLAG_DWE)
8887 printf(" debug wait enable\n");
8888 else if (env->flags & POWERPC_FLAG_UBLE)
8889 printf(" user BTB lock enable\n");
8890 if (env->flags & POWERPC_FLAG_BE)
8891 printf(" branch-step trace mode\n");
8892 else if (env->flags & POWERPC_FLAG_DE)
8893 printf(" debug interrupt enable\n");
8894 if (env->flags & POWERPC_FLAG_PX)
8895 printf(" inclusive protection\n");
8896 else if (env->flags & POWERPC_FLAG_PMM)
8897 printf(" performance monitor mark\n");
8898 if (env->flags == POWERPC_FLAG_NONE)
8899 printf(" none\n");
8900 printf(" Time-base/decrementer clock source: %s\n",
8901 env->flags & POWERPC_FLAG_RTC_CLK ? "RTC clock" : "bus clock");
8902 dump_ppc_insns(env);
8903 dump_ppc_sprs(env);
8904 fflush(stdout);
8905 }
8906 #endif
8907 }
8908
8909 static void ppc_cpu_unrealizefn(DeviceState *dev, Error **errp)
8910 {
8911 PowerPCCPU *cpu = POWERPC_CPU(dev);
8912 CPUPPCState *env = &cpu->env;
8913 int i;
8914
8915 for (i = 0; i < PPC_CPU_OPCODES_LEN; i++) {
8916 if (env->opcodes[i] != &invalid_handler) {
8917 g_free(env->opcodes[i]);
8918 }
8919 }
8920 }
8921
8922 int ppc_get_compat_smt_threads(PowerPCCPU *cpu)
8923 {
8924 int ret = smp_threads;
8925 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
8926
8927 switch (cpu->cpu_version) {
8928 case CPU_POWERPC_LOGICAL_2_05:
8929 ret = 2;
8930 break;
8931 case CPU_POWERPC_LOGICAL_2_06:
8932 ret = 4;
8933 break;
8934 case CPU_POWERPC_LOGICAL_2_07:
8935 ret = 8;
8936 break;
8937 default:
8938 if (pcc->pcr_mask & PCR_COMPAT_2_06) {
8939 ret = 4;
8940 } else if (pcc->pcr_mask & PCR_COMPAT_2_05) {
8941 ret = 2;
8942 }
8943 break;
8944 }
8945
8946 return MIN(ret, smp_threads);
8947 }
8948
8949 int ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version)
8950 {
8951 int ret = 0;
8952 CPUPPCState *env = &cpu->env;
8953
8954 cpu->cpu_version = cpu_version;
8955
8956 switch (cpu_version) {
8957 case CPU_POWERPC_LOGICAL_2_05:
8958 env->spr[SPR_PCR] = PCR_COMPAT_2_05;
8959 break;
8960 case CPU_POWERPC_LOGICAL_2_06:
8961 env->spr[SPR_PCR] = PCR_COMPAT_2_06;
8962 break;
8963 case CPU_POWERPC_LOGICAL_2_06_PLUS:
8964 env->spr[SPR_PCR] = PCR_COMPAT_2_06;
8965 break;
8966 default:
8967 env->spr[SPR_PCR] = 0;
8968 break;
8969 }
8970
8971 if (kvm_enabled() && kvmppc_set_compat(cpu, cpu->max_compat) < 0) {
8972 error_report("Unable to set compatibility mode in KVM");
8973 ret = -1;
8974 }
8975
8976 return ret;
8977 }
8978
8979 static gint ppc_cpu_compare_class_pvr(gconstpointer a, gconstpointer b)
8980 {
8981 ObjectClass *oc = (ObjectClass *)a;
8982 uint32_t pvr = *(uint32_t *)b;
8983 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
8984
8985 /* -cpu host does a PVR lookup during construction */
8986 if (unlikely(strcmp(object_class_get_name(oc),
8987 TYPE_HOST_POWERPC_CPU) == 0)) {
8988 return -1;
8989 }
8990
8991 if (!ppc_cpu_is_valid(pcc)) {
8992 return -1;
8993 }
8994
8995 return pcc->pvr == pvr ? 0 : -1;
8996 }
8997
8998 PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr)
8999 {
9000 GSList *list, *item;
9001 PowerPCCPUClass *pcc = NULL;
9002
9003 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9004 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr);
9005 if (item != NULL) {
9006 pcc = POWERPC_CPU_CLASS(item->data);
9007 }
9008 g_slist_free(list);
9009
9010 return pcc;
9011 }
9012
9013 static gint ppc_cpu_compare_class_pvr_mask(gconstpointer a, gconstpointer b)
9014 {
9015 ObjectClass *oc = (ObjectClass *)a;
9016 uint32_t pvr = *(uint32_t *)b;
9017 PowerPCCPUClass *pcc = (PowerPCCPUClass *)a;
9018 gint ret;
9019
9020 /* -cpu host does a PVR lookup during construction */
9021 if (unlikely(strcmp(object_class_get_name(oc),
9022 TYPE_HOST_POWERPC_CPU) == 0)) {
9023 return -1;
9024 }
9025
9026 if (!ppc_cpu_is_valid(pcc)) {
9027 return -1;
9028 }
9029
9030 ret = (((pcc->pvr & pcc->pvr_mask) == (pvr & pcc->pvr_mask)) ? 0 : -1);
9031
9032 return ret;
9033 }
9034
9035 PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr)
9036 {
9037 GSList *list, *item;
9038 PowerPCCPUClass *pcc = NULL;
9039
9040 list = object_class_get_list(TYPE_POWERPC_CPU, true);
9041 item = g_slist_find_custom(list, &pvr, ppc_cpu_compare_class_pvr_mask);
9042 if (item != NULL) {
9043 pcc = POWERPC_CPU_CLASS(item->data);
9044 }
9045 g_slist_free(list);
9046
9047 return pcc;
9048 }
9049
9050 static gint ppc_cpu_compare_class_name(gconstpointer a, gconstpointer b)
9051 {
9052 ObjectClass *oc = (ObjectClass *)a;
9053 const char *name = b;
9054 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9055
9056 if (strncasecmp(name, object_class_get_name(oc), strlen(name)) == 0 &&
9057 ppc_cpu_is_valid(pcc) &&
9058 strcmp(object_class_get_name(oc) + strlen(name),
9059 "-" TYPE_POWERPC_CPU) == 0) {
9060 return 0;
9061 }
9062 return -1;
9063 }
9064
9065 #include <ctype.h>
9066
9067 static ObjectClass *ppc_cpu_class_by_name(const char *name);
9068
9069 static ObjectClass *ppc_cpu_class_by_alias(PowerPCCPUAlias *alias)
9070 {
9071 ObjectClass *invalid_class = (void*)ppc_cpu_class_by_alias;
9072
9073 /* Cache target class lookups in the alias table */
9074 if (!alias->oc) {
9075 alias->oc = ppc_cpu_class_by_name(alias->model);
9076 if (!alias->oc) {
9077 /* Fast check for non-existing aliases */
9078 alias->oc = invalid_class;
9079 }
9080 }
9081
9082 if (alias->oc == invalid_class) {
9083 return NULL;
9084 } else {
9085 return alias->oc;
9086 }
9087 }
9088
9089 static ObjectClass *ppc_cpu_class_by_name(const char *name)
9090 {
9091 GSList *list, *item;
9092 ObjectClass *ret = NULL;
9093 const char *p;
9094 int i, len;
9095
9096 /* Check if the given name is a PVR */
9097 len = strlen(name);
9098 if (len == 10 && name[0] == '0' && name[1] == 'x') {
9099 p = name + 2;
9100 goto check_pvr;
9101 } else if (len == 8) {
9102 p = name;
9103 check_pvr:
9104 for (i = 0; i < 8; i++) {
9105 if (!qemu_isxdigit(*p++))
9106 break;
9107 }
9108 if (i == 8) {
9109 ret = OBJECT_CLASS(ppc_cpu_class_by_pvr(strtoul(name, NULL, 16)));
9110 return ret;
9111 }
9112 }
9113
9114 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9115 item = g_slist_find_custom(list, name, ppc_cpu_compare_class_name);
9116 if (item != NULL) {
9117 ret = OBJECT_CLASS(item->data);
9118 }
9119 g_slist_free(list);
9120
9121 if (ret) {
9122 return ret;
9123 }
9124
9125 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9126 if (strcmp(ppc_cpu_aliases[i].alias, name) == 0) {
9127 return ppc_cpu_class_by_alias(&ppc_cpu_aliases[i]);
9128 }
9129 }
9130
9131 return NULL;
9132 }
9133
9134 PowerPCCPU *cpu_ppc_init(const char *cpu_model)
9135 {
9136 return POWERPC_CPU(cpu_generic_init(TYPE_POWERPC_CPU, cpu_model));
9137 }
9138
9139 /* Sort by PVR, ordering special case "host" last. */
9140 static gint ppc_cpu_list_compare(gconstpointer a, gconstpointer b)
9141 {
9142 ObjectClass *oc_a = (ObjectClass *)a;
9143 ObjectClass *oc_b = (ObjectClass *)b;
9144 PowerPCCPUClass *pcc_a = POWERPC_CPU_CLASS(oc_a);
9145 PowerPCCPUClass *pcc_b = POWERPC_CPU_CLASS(oc_b);
9146 const char *name_a = object_class_get_name(oc_a);
9147 const char *name_b = object_class_get_name(oc_b);
9148
9149 if (strcmp(name_a, TYPE_HOST_POWERPC_CPU) == 0) {
9150 return 1;
9151 } else if (strcmp(name_b, TYPE_HOST_POWERPC_CPU) == 0) {
9152 return -1;
9153 } else {
9154 /* Avoid an integer overflow during subtraction */
9155 if (pcc_a->pvr < pcc_b->pvr) {
9156 return -1;
9157 } else if (pcc_a->pvr > pcc_b->pvr) {
9158 return 1;
9159 } else {
9160 return 0;
9161 }
9162 }
9163 }
9164
9165 static void ppc_cpu_list_entry(gpointer data, gpointer user_data)
9166 {
9167 ObjectClass *oc = data;
9168 CPUListState *s = user_data;
9169 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9170 const char *typename = object_class_get_name(oc);
9171 char *name;
9172 int i;
9173
9174 if (!ppc_cpu_is_valid(pcc)) {
9175 return;
9176 }
9177 if (unlikely(strcmp(typename, TYPE_HOST_POWERPC_CPU) == 0)) {
9178 return;
9179 }
9180
9181 name = g_strndup(typename,
9182 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
9183 (*s->cpu_fprintf)(s->file, "PowerPC %-16s PVR %08x\n",
9184 name, pcc->pvr);
9185 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9186 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
9187 ObjectClass *alias_oc = ppc_cpu_class_by_alias(alias);
9188
9189 if (alias_oc != oc) {
9190 continue;
9191 }
9192 (*s->cpu_fprintf)(s->file, "PowerPC %-16s (alias for %s)\n",
9193 alias->alias, name);
9194 }
9195 g_free(name);
9196 }
9197
9198 void ppc_cpu_list(FILE *f, fprintf_function cpu_fprintf)
9199 {
9200 CPUListState s = {
9201 .file = f,
9202 .cpu_fprintf = cpu_fprintf,
9203 };
9204 GSList *list;
9205
9206 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9207 list = g_slist_sort(list, ppc_cpu_list_compare);
9208 g_slist_foreach(list, ppc_cpu_list_entry, &s);
9209 g_slist_free(list);
9210
9211 #ifdef CONFIG_KVM
9212 cpu_fprintf(f, "\n");
9213 cpu_fprintf(f, "PowerPC %-16s\n", "host");
9214 #endif
9215 }
9216
9217 static void ppc_cpu_defs_entry(gpointer data, gpointer user_data)
9218 {
9219 ObjectClass *oc = data;
9220 CpuDefinitionInfoList **first = user_data;
9221 const char *typename;
9222 CpuDefinitionInfoList *entry;
9223 CpuDefinitionInfo *info;
9224 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9225
9226 if (!ppc_cpu_is_valid(pcc)) {
9227 return;
9228 }
9229
9230 typename = object_class_get_name(oc);
9231 info = g_malloc0(sizeof(*info));
9232 info->name = g_strndup(typename,
9233 strlen(typename) - strlen("-" TYPE_POWERPC_CPU));
9234
9235 entry = g_malloc0(sizeof(*entry));
9236 entry->value = info;
9237 entry->next = *first;
9238 *first = entry;
9239 }
9240
9241 CpuDefinitionInfoList *arch_query_cpu_definitions(Error **errp)
9242 {
9243 CpuDefinitionInfoList *cpu_list = NULL;
9244 GSList *list;
9245 int i;
9246
9247 list = object_class_get_list(TYPE_POWERPC_CPU, false);
9248 g_slist_foreach(list, ppc_cpu_defs_entry, &cpu_list);
9249 g_slist_free(list);
9250
9251 for (i = 0; ppc_cpu_aliases[i].alias != NULL; i++) {
9252 PowerPCCPUAlias *alias = &ppc_cpu_aliases[i];
9253 ObjectClass *oc;
9254 CpuDefinitionInfoList *entry;
9255 CpuDefinitionInfo *info;
9256
9257 oc = ppc_cpu_class_by_alias(alias);
9258 if (oc == NULL) {
9259 continue;
9260 }
9261
9262 info = g_malloc0(sizeof(*info));
9263 info->name = g_strdup(alias->alias);
9264
9265 entry = g_malloc0(sizeof(*entry));
9266 entry->value = info;
9267 entry->next = cpu_list;
9268 cpu_list = entry;
9269 }
9270
9271 return cpu_list;
9272 }
9273
9274 static void ppc_cpu_set_pc(CPUState *cs, vaddr value)
9275 {
9276 PowerPCCPU *cpu = POWERPC_CPU(cs);
9277
9278 cpu->env.nip = value;
9279 }
9280
9281 static bool ppc_cpu_has_work(CPUState *cs)
9282 {
9283 PowerPCCPU *cpu = POWERPC_CPU(cs);
9284 CPUPPCState *env = &cpu->env;
9285
9286 return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
9287 }
9288
9289 /* CPUClass::reset() */
9290 static void ppc_cpu_reset(CPUState *s)
9291 {
9292 PowerPCCPU *cpu = POWERPC_CPU(s);
9293 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9294 CPUPPCState *env = &cpu->env;
9295 target_ulong msr;
9296 int i;
9297
9298 pcc->parent_reset(s);
9299
9300 msr = (target_ulong)0;
9301 if (0) {
9302 /* XXX: find a suitable condition to enable the hypervisor mode */
9303 msr |= (target_ulong)MSR_HVB;
9304 }
9305 msr |= (target_ulong)0 << MSR_AP; /* TO BE CHECKED */
9306 msr |= (target_ulong)0 << MSR_SA; /* TO BE CHECKED */
9307 msr |= (target_ulong)1 << MSR_EP;
9308 #if defined(DO_SINGLE_STEP) && 0
9309 /* Single step trace mode */
9310 msr |= (target_ulong)1 << MSR_SE;
9311 msr |= (target_ulong)1 << MSR_BE;
9312 #endif
9313 #if defined(CONFIG_USER_ONLY)
9314 msr |= (target_ulong)1 << MSR_FP; /* Allow floating point usage */
9315 msr |= (target_ulong)1 << MSR_VR; /* Allow altivec usage */
9316 msr |= (target_ulong)1 << MSR_SPE; /* Allow SPE usage */
9317 msr |= (target_ulong)1 << MSR_PR;
9318 #endif
9319
9320 #if defined(TARGET_PPC64)
9321 if (env->mmu_model & POWERPC_MMU_64) {
9322 env->msr |= (1ULL << MSR_SF);
9323 }
9324 #endif
9325
9326 hreg_store_msr(env, msr, 1);
9327
9328 #if !defined(CONFIG_USER_ONLY)
9329 env->nip = env->hreset_vector | env->excp_prefix;
9330 if (env->mmu_model != POWERPC_MMU_REAL) {
9331 ppc_tlb_invalidate_all(env);
9332 }
9333 #endif
9334
9335 hreg_compute_hflags(env);
9336 env->reserve_addr = (target_ulong)-1ULL;
9337 /* Be sure no exception or interrupt is pending */
9338 env->pending_interrupts = 0;
9339 s->exception_index = POWERPC_EXCP_NONE;
9340 env->error_code = 0;
9341
9342 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
9343 env->vpa_addr = 0;
9344 env->slb_shadow_addr = 0;
9345 env->slb_shadow_size = 0;
9346 env->dtl_addr = 0;
9347 env->dtl_size = 0;
9348 #endif /* TARGET_PPC64 */
9349
9350 for (i = 0; i < ARRAY_SIZE(env->spr_cb); i++) {
9351 ppc_spr_t *spr = &env->spr_cb[i];
9352
9353 if (!spr->name) {
9354 continue;
9355 }
9356 env->spr[i] = spr->default_value;
9357 }
9358
9359 /* Flush all TLBs */
9360 tlb_flush(s, 1);
9361 }
9362
9363 static void ppc_cpu_initfn(Object *obj)
9364 {
9365 CPUState *cs = CPU(obj);
9366 PowerPCCPU *cpu = POWERPC_CPU(obj);
9367 PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu);
9368 CPUPPCState *env = &cpu->env;
9369
9370 cs->env_ptr = env;
9371 cpu_exec_init(env);
9372 cpu->cpu_dt_id = cs->cpu_index;
9373
9374 env->msr_mask = pcc->msr_mask;
9375 env->mmu_model = pcc->mmu_model;
9376 env->excp_model = pcc->excp_model;
9377 env->bus_model = pcc->bus_model;
9378 env->insns_flags = pcc->insns_flags;
9379 env->insns_flags2 = pcc->insns_flags2;
9380 env->flags = pcc->flags;
9381 env->bfd_mach = pcc->bfd_mach;
9382 env->check_pow = pcc->check_pow;
9383
9384 #if defined(TARGET_PPC64)
9385 if (pcc->sps) {
9386 env->sps = *pcc->sps;
9387 } else if (env->mmu_model & POWERPC_MMU_64) {
9388 /* Use default sets of page sizes */
9389 static const struct ppc_segment_page_sizes defsps = {
9390 .sps = {
9391 { .page_shift = 12, /* 4K */
9392 .slb_enc = 0,
9393 .enc = { { .page_shift = 12, .pte_enc = 0 } }
9394 },
9395 { .page_shift = 24, /* 16M */
9396 .slb_enc = 0x100,
9397 .enc = { { .page_shift = 24, .pte_enc = 0 } }
9398 },
9399 },
9400 };
9401 env->sps = defsps;
9402 }
9403 #endif /* defined(TARGET_PPC64) */
9404
9405 if (tcg_enabled()) {
9406 ppc_translate_init();
9407 }
9408 }
9409
9410 static void ppc_cpu_class_init(ObjectClass *oc, void *data)
9411 {
9412 PowerPCCPUClass *pcc = POWERPC_CPU_CLASS(oc);
9413 CPUClass *cc = CPU_CLASS(oc);
9414 DeviceClass *dc = DEVICE_CLASS(oc);
9415
9416 pcc->parent_realize = dc->realize;
9417 pcc->pvr = CPU_POWERPC_DEFAULT_MASK;
9418 pcc->pvr_mask = CPU_POWERPC_DEFAULT_MASK;
9419 pcc->interrupts_big_endian = ppc_cpu_interrupts_big_endian_always;
9420 dc->realize = ppc_cpu_realizefn;
9421 dc->unrealize = ppc_cpu_unrealizefn;
9422
9423 pcc->parent_reset = cc->reset;
9424 cc->reset = ppc_cpu_reset;
9425
9426 cc->class_by_name = ppc_cpu_class_by_name;
9427 cc->has_work = ppc_cpu_has_work;
9428 cc->do_interrupt = ppc_cpu_do_interrupt;
9429 cc->dump_state = ppc_cpu_dump_state;
9430 cc->dump_statistics = ppc_cpu_dump_statistics;
9431 cc->set_pc = ppc_cpu_set_pc;
9432 cc->gdb_read_register = ppc_cpu_gdb_read_register;
9433 cc->gdb_write_register = ppc_cpu_gdb_write_register;
9434 #ifdef CONFIG_USER_ONLY
9435 cc->handle_mmu_fault = ppc_cpu_handle_mmu_fault;
9436 #else
9437 cc->get_phys_page_debug = ppc_cpu_get_phys_page_debug;
9438 cc->vmsd = &vmstate_ppc_cpu;
9439 #if defined(TARGET_PPC64)
9440 cc->write_elf64_note = ppc64_cpu_write_elf64_note;
9441 cc->write_elf64_qemunote = ppc64_cpu_write_elf64_qemunote;
9442 #endif
9443 #endif
9444
9445 cc->gdb_num_core_regs = 71;
9446 #if defined(TARGET_PPC64)
9447 cc->gdb_core_xml_file = "power64-core.xml";
9448 #else
9449 cc->gdb_core_xml_file = "power-core.xml";
9450 #endif
9451
9452 dc->fw_name = "PowerPC,UNKNOWN";
9453 }
9454
9455 static const TypeInfo ppc_cpu_type_info = {
9456 .name = TYPE_POWERPC_CPU,
9457 .parent = TYPE_CPU,
9458 .instance_size = sizeof(PowerPCCPU),
9459 .instance_init = ppc_cpu_initfn,
9460 .abstract = true,
9461 .class_size = sizeof(PowerPCCPUClass),
9462 .class_init = ppc_cpu_class_init,
9463 };
9464
9465 static void ppc_cpu_register_types(void)
9466 {
9467 type_register_static(&ppc_cpu_type_info);
9468 }
9469
9470 type_init(ppc_cpu_register_types)
QEMU modified to work with kvm