2 * i386 emulator main execution loop
4 * Copyright (c) 2003-2005 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #if !defined(TARGET_IA64)
26 #include "qemu-barrier.h"
28 #if !defined(CONFIG_SOFTMMU)
40 #include <sys/ucontext.h>
46 #if defined(__sparc__) && !defined(CONFIG_SOLARIS)
47 // Work around ugly bugs in glibc that mangle global register contents
49 #define env cpu_single_env
52 int tb_invalidated_flag
;
54 //#define CONFIG_DEBUG_EXEC
55 //#define DEBUG_SIGNAL
57 int qemu_cpu_has_work(CPUState
*env
)
59 return cpu_has_work(env
);
62 void cpu_loop_exit(void)
64 env
->current_tb
= NULL
;
65 longjmp(env
->jmp_env
, 1);
68 /* exit the current TB from a signal handler. The host registers are
69 restored in a state compatible with the CPU emulator
71 void cpu_resume_from_signal(CPUState
*env1
, void *puc
)
73 #if !defined(CONFIG_SOFTMMU)
75 struct ucontext
*uc
= puc
;
76 #elif defined(__OpenBSD__)
77 struct sigcontext
*uc
= puc
;
83 /* XXX: restore cpu registers saved in host registers */
85 #if !defined(CONFIG_SOFTMMU)
87 /* XXX: use siglongjmp ? */
90 sigprocmask(SIG_SETMASK
, (sigset_t
*)&uc
->uc_sigmask
, NULL
);
92 sigprocmask(SIG_SETMASK
, &uc
->uc_sigmask
, NULL
);
94 #elif defined(__OpenBSD__)
95 sigprocmask(SIG_SETMASK
, &uc
->sc_mask
, NULL
);
99 env
->exception_index
= -1;
100 longjmp(env
->jmp_env
, 1);
103 /* Execute the code without caching the generated code. An interpreter
104 could be used if available. */
105 static void cpu_exec_nocache(int max_cycles
, TranslationBlock
*orig_tb
)
107 unsigned long next_tb
;
108 TranslationBlock
*tb
;
110 /* Should never happen.
111 We only end up here when an existing TB is too long. */
112 if (max_cycles
> CF_COUNT_MASK
)
113 max_cycles
= CF_COUNT_MASK
;
115 tb
= tb_gen_code(env
, orig_tb
->pc
, orig_tb
->cs_base
, orig_tb
->flags
,
117 env
->current_tb
= tb
;
118 /* execute the generated code */
119 next_tb
= tcg_qemu_tb_exec(tb
->tc_ptr
);
120 env
->current_tb
= NULL
;
122 if ((next_tb
& 3) == 2) {
123 /* Restore PC. This may happen if async event occurs before
124 the TB starts executing. */
125 cpu_pc_from_tb(env
, tb
);
127 tb_phys_invalidate(tb
, -1);
131 static TranslationBlock
*tb_find_slow(target_ulong pc
,
132 target_ulong cs_base
,
135 TranslationBlock
*tb
, **ptb1
;
137 tb_page_addr_t phys_pc
, phys_page1
, phys_page2
;
138 target_ulong virt_page2
;
140 tb_invalidated_flag
= 0;
142 /* find translated block using physical mappings */
143 phys_pc
= get_page_addr_code(env
, pc
);
144 phys_page1
= phys_pc
& TARGET_PAGE_MASK
;
146 h
= tb_phys_hash_func(phys_pc
);
147 ptb1
= &tb_phys_hash
[h
];
153 tb
->page_addr
[0] == phys_page1
&&
154 tb
->cs_base
== cs_base
&&
155 tb
->flags
== flags
) {
156 /* check next page if needed */
157 if (tb
->page_addr
[1] != -1) {
158 virt_page2
= (pc
& TARGET_PAGE_MASK
) +
160 phys_page2
= get_page_addr_code(env
, virt_page2
);
161 if (tb
->page_addr
[1] == phys_page2
)
167 ptb1
= &tb
->phys_hash_next
;
170 /* if no translated code available, then translate it now */
171 tb
= tb_gen_code(env
, pc
, cs_base
, flags
, 0);
174 /* Move the last found TB to the head of the list */
176 *ptb1
= tb
->phys_hash_next
;
177 tb
->phys_hash_next
= tb_phys_hash
[h
];
178 tb_phys_hash
[h
] = tb
;
180 /* we add the TB in the virtual pc hash table */
181 env
->tb_jmp_cache
[tb_jmp_cache_hash_func(pc
)] = tb
;
185 static inline TranslationBlock
*tb_find_fast(void)
187 TranslationBlock
*tb
;
188 target_ulong cs_base
, pc
;
191 /* we record a subset of the CPU state. It will
192 always be the same before a given translated block
194 cpu_get_tb_cpu_state(env
, &pc
, &cs_base
, &flags
);
195 tb
= env
->tb_jmp_cache
[tb_jmp_cache_hash_func(pc
)];
196 if (unlikely(!tb
|| tb
->pc
!= pc
|| tb
->cs_base
!= cs_base
||
197 tb
->flags
!= flags
)) {
198 tb
= tb_find_slow(pc
, cs_base
, flags
);
203 static CPUDebugExcpHandler
*debug_excp_handler
;
205 CPUDebugExcpHandler
*cpu_set_debug_excp_handler(CPUDebugExcpHandler
*handler
)
207 CPUDebugExcpHandler
*old_handler
= debug_excp_handler
;
209 debug_excp_handler
= handler
;
213 static void cpu_handle_debug_exception(CPUState
*env
)
217 if (!env
->watchpoint_hit
)
218 QTAILQ_FOREACH(wp
, &env
->watchpoints
, entry
)
219 wp
->flags
&= ~BP_WATCHPOINT_HIT
;
221 if (debug_excp_handler
)
222 debug_excp_handler(env
);
225 /* main execution loop */
227 volatile sig_atomic_t exit_request
;
229 int cpu_exec(CPUState
*env1
)
231 volatile host_reg_t saved_env_reg
;
232 int ret
, interrupt_request
;
233 TranslationBlock
*tb
;
235 unsigned long next_tb
;
237 if (cpu_halted(env1
) == EXCP_HALTED
)
240 cpu_single_env
= env1
;
242 /* the access to env below is actually saving the global register's
243 value, so that files not including target-xyz/exec.h are free to
245 QEMU_BUILD_BUG_ON (sizeof (saved_env_reg
) != sizeof (env
));
246 saved_env_reg
= (host_reg_t
) env
;
250 if (unlikely(exit_request
)) {
251 env
->exit_request
= 1;
254 #if defined(TARGET_I386)
255 if (!kvm_enabled()) {
256 /* put eflags in CPU temporary format */
257 CC_SRC
= env
->eflags
& (CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
258 DF
= 1 - (2 * ((env
->eflags
>> 10) & 1));
259 CC_OP
= CC_OP_EFLAGS
;
260 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
262 #elif defined(TARGET_SPARC)
263 #elif defined(TARGET_M68K)
264 env
->cc_op
= CC_OP_FLAGS
;
265 env
->cc_dest
= env
->sr
& 0xf;
266 env
->cc_x
= (env
->sr
>> 4) & 1;
267 #elif defined(TARGET_ALPHA)
268 #elif defined(TARGET_ARM)
269 #elif defined(TARGET_PPC)
270 #elif defined(TARGET_MICROBLAZE)
271 #elif defined(TARGET_MIPS)
272 #elif defined(TARGET_SH4)
273 #elif defined(TARGET_CRIS)
274 #elif defined(TARGET_S390X)
275 #elif defined(TARGET_IA64)
278 #error unsupported target CPU
280 env
->exception_index
= -1;
282 /* prepare setjmp context for exception handling */
284 if (setjmp(env
->jmp_env
) == 0) {
285 #if defined(__sparc__) && !defined(CONFIG_SOLARIS)
287 env
= cpu_single_env
;
288 #define env cpu_single_env
290 /* if an exception is pending, we execute it here */
291 if (env
->exception_index
>= 0) {
292 if (env
->exception_index
>= EXCP_INTERRUPT
) {
293 /* exit request from the cpu execution loop */
294 ret
= env
->exception_index
;
295 if (ret
== EXCP_DEBUG
)
296 cpu_handle_debug_exception(env
);
299 #if defined(CONFIG_USER_ONLY)
300 /* if user mode only, we simulate a fake exception
301 which will be handled outside the cpu execution
303 #if defined(TARGET_I386)
304 do_interrupt_user(env
->exception_index
,
305 env
->exception_is_int
,
307 env
->exception_next_eip
);
308 /* successfully delivered */
309 env
->old_exception
= -1;
311 ret
= env
->exception_index
;
314 #if defined(TARGET_I386)
315 /* simulate a real cpu exception. On i386, it can
316 trigger new exceptions, but we do not handle
317 double or triple faults yet. */
318 do_interrupt(env
->exception_index
,
319 env
->exception_is_int
,
321 env
->exception_next_eip
, 0);
322 /* successfully delivered */
323 env
->old_exception
= -1;
324 #elif defined(TARGET_PPC)
326 #elif defined(TARGET_MICROBLAZE)
328 #elif defined(TARGET_MIPS)
330 #elif defined(TARGET_SPARC)
332 #elif defined(TARGET_ARM)
334 #elif defined(TARGET_SH4)
336 #elif defined(TARGET_ALPHA)
338 #elif defined(TARGET_CRIS)
340 #elif defined(TARGET_M68K)
342 #elif defined(TARGET_IA64)
345 env
->exception_index
= -1;
352 longjmp(env
->jmp_env
, 1);
355 next_tb
= 0; /* force lookup of first TB */
357 interrupt_request
= env
->interrupt_request
;
358 if (unlikely(interrupt_request
)) {
359 if (unlikely(env
->singlestep_enabled
& SSTEP_NOIRQ
)) {
360 /* Mask out external interrupts for this step. */
361 interrupt_request
&= ~(CPU_INTERRUPT_HARD
|
366 if (interrupt_request
& CPU_INTERRUPT_DEBUG
) {
367 env
->interrupt_request
&= ~CPU_INTERRUPT_DEBUG
;
368 env
->exception_index
= EXCP_DEBUG
;
371 #if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \
372 defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \
373 defined(TARGET_MICROBLAZE)
374 if (interrupt_request
& CPU_INTERRUPT_HALT
) {
375 env
->interrupt_request
&= ~CPU_INTERRUPT_HALT
;
377 env
->exception_index
= EXCP_HLT
;
381 #if defined(TARGET_I386)
382 if (interrupt_request
& CPU_INTERRUPT_INIT
) {
383 svm_check_intercept(SVM_EXIT_INIT
);
385 env
->exception_index
= EXCP_HALTED
;
387 } else if (interrupt_request
& CPU_INTERRUPT_SIPI
) {
389 } else if (env
->hflags2
& HF2_GIF_MASK
) {
390 if ((interrupt_request
& CPU_INTERRUPT_SMI
) &&
391 !(env
->hflags
& HF_SMM_MASK
)) {
392 svm_check_intercept(SVM_EXIT_SMI
);
393 env
->interrupt_request
&= ~CPU_INTERRUPT_SMI
;
396 } else if ((interrupt_request
& CPU_INTERRUPT_NMI
) &&
397 !(env
->hflags2
& HF2_NMI_MASK
)) {
398 env
->interrupt_request
&= ~CPU_INTERRUPT_NMI
;
399 env
->hflags2
|= HF2_NMI_MASK
;
400 do_interrupt(EXCP02_NMI
, 0, 0, 0, 1);
402 } else if (interrupt_request
& CPU_INTERRUPT_MCE
) {
403 env
->interrupt_request
&= ~CPU_INTERRUPT_MCE
;
404 do_interrupt(EXCP12_MCHK
, 0, 0, 0, 0);
406 } else if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
407 (((env
->hflags2
& HF2_VINTR_MASK
) &&
408 (env
->hflags2
& HF2_HIF_MASK
)) ||
409 (!(env
->hflags2
& HF2_VINTR_MASK
) &&
410 (env
->eflags
& IF_MASK
&&
411 !(env
->hflags
& HF_INHIBIT_IRQ_MASK
))))) {
413 svm_check_intercept(SVM_EXIT_INTR
);
414 env
->interrupt_request
&= ~(CPU_INTERRUPT_HARD
| CPU_INTERRUPT_VIRQ
);
415 intno
= cpu_get_pic_interrupt(env
);
416 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "Servicing hardware INT=0x%02x\n", intno
);
417 #if defined(__sparc__) && !defined(CONFIG_SOLARIS)
419 env
= cpu_single_env
;
420 #define env cpu_single_env
422 do_interrupt(intno
, 0, 0, 0, 1);
423 /* ensure that no TB jump will be modified as
424 the program flow was changed */
426 #if !defined(CONFIG_USER_ONLY)
427 } else if ((interrupt_request
& CPU_INTERRUPT_VIRQ
) &&
428 (env
->eflags
& IF_MASK
) &&
429 !(env
->hflags
& HF_INHIBIT_IRQ_MASK
)) {
431 /* FIXME: this should respect TPR */
432 svm_check_intercept(SVM_EXIT_VINTR
);
433 intno
= ldl_phys(env
->vm_vmcb
+ offsetof(struct vmcb
, control
.int_vector
));
434 qemu_log_mask(CPU_LOG_TB_IN_ASM
, "Servicing virtual hardware INT=0x%02x\n", intno
);
435 do_interrupt(intno
, 0, 0, 0, 1);
436 env
->interrupt_request
&= ~CPU_INTERRUPT_VIRQ
;
441 #elif defined(TARGET_PPC)
443 if ((interrupt_request
& CPU_INTERRUPT_RESET
)) {
447 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
448 ppc_hw_interrupt(env
);
449 if (env
->pending_interrupts
== 0)
450 env
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
453 #elif defined(TARGET_MICROBLAZE)
454 if ((interrupt_request
& CPU_INTERRUPT_HARD
)
455 && (env
->sregs
[SR_MSR
] & MSR_IE
)
456 && !(env
->sregs
[SR_MSR
] & (MSR_EIP
| MSR_BIP
))
457 && !(env
->iflags
& (D_FLAG
| IMM_FLAG
))) {
458 env
->exception_index
= EXCP_IRQ
;
462 #elif defined(TARGET_MIPS)
463 if ((interrupt_request
& CPU_INTERRUPT_HARD
) &&
464 cpu_mips_hw_interrupts_pending(env
)) {
466 env
->exception_index
= EXCP_EXT_INTERRUPT
;
471 #elif defined(TARGET_SPARC)
472 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
473 if (cpu_interrupts_enabled(env
) &&
474 env
->interrupt_index
> 0) {
475 int pil
= env
->interrupt_index
& 0xf;
476 int type
= env
->interrupt_index
& 0xf0;
478 if (((type
== TT_EXTINT
) &&
479 cpu_pil_allowed(env
, pil
)) ||
481 env
->exception_index
= env
->interrupt_index
;
486 } else if (interrupt_request
& CPU_INTERRUPT_TIMER
) {
487 //do_interrupt(0, 0, 0, 0, 0);
488 env
->interrupt_request
&= ~CPU_INTERRUPT_TIMER
;
490 #elif defined(TARGET_ARM)
491 if (interrupt_request
& CPU_INTERRUPT_FIQ
492 && !(env
->uncached_cpsr
& CPSR_F
)) {
493 env
->exception_index
= EXCP_FIQ
;
497 /* ARMv7-M interrupt return works by loading a magic value
498 into the PC. On real hardware the load causes the
499 return to occur. The qemu implementation performs the
500 jump normally, then does the exception return when the
501 CPU tries to execute code at the magic address.
502 This will cause the magic PC value to be pushed to
503 the stack if an interrupt occured at the wrong time.
504 We avoid this by disabling interrupts when
505 pc contains a magic address. */
506 if (interrupt_request
& CPU_INTERRUPT_HARD
507 && ((IS_M(env
) && env
->regs
[15] < 0xfffffff0)
508 || !(env
->uncached_cpsr
& CPSR_I
))) {
509 env
->exception_index
= EXCP_IRQ
;
513 #elif defined(TARGET_SH4)
514 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
518 #elif defined(TARGET_ALPHA)
519 if (interrupt_request
& CPU_INTERRUPT_HARD
) {
523 #elif defined(TARGET_CRIS)
524 if (interrupt_request
& CPU_INTERRUPT_HARD
525 && (env
->pregs
[PR_CCS
] & I_FLAG
)
526 && !env
->locked_irq
) {
527 env
->exception_index
= EXCP_IRQ
;
531 if (interrupt_request
& CPU_INTERRUPT_NMI
532 && (env
->pregs
[PR_CCS
] & M_FLAG
)) {
533 env
->exception_index
= EXCP_NMI
;
537 #elif defined(TARGET_M68K)
538 if (interrupt_request
& CPU_INTERRUPT_HARD
539 && ((env
->sr
& SR_I
) >> SR_I_SHIFT
)
540 < env
->pending_level
) {
541 /* Real hardware gets the interrupt vector via an
542 IACK cycle at this point. Current emulated
543 hardware doesn't rely on this, so we
544 provide/save the vector when the interrupt is
546 env
->exception_index
= env
->pending_vector
;
551 /* Don't use the cached interupt_request value,
552 do_interrupt may have updated the EXITTB flag. */
553 if (env
->interrupt_request
& CPU_INTERRUPT_EXITTB
) {
554 env
->interrupt_request
&= ~CPU_INTERRUPT_EXITTB
;
555 /* ensure that no TB jump will be modified as
556 the program flow was changed */
560 if (unlikely(env
->exit_request
)) {
561 env
->exit_request
= 0;
562 env
->exception_index
= EXCP_INTERRUPT
;
565 #if defined(DEBUG_DISAS) || defined(CONFIG_DEBUG_EXEC)
566 if (qemu_loglevel_mask(CPU_LOG_TB_CPU
)) {
567 /* restore flags in standard format */
568 #if defined(TARGET_I386)
569 env
->eflags
= env
->eflags
| helper_cc_compute_all(CC_OP
) | (DF
& DF_MASK
);
570 log_cpu_state(env
, X86_DUMP_CCOP
);
571 env
->eflags
&= ~(DF_MASK
| CC_O
| CC_S
| CC_Z
| CC_A
| CC_P
| CC_C
);
572 #elif defined(TARGET_M68K)
573 cpu_m68k_flush_flags(env
, env
->cc_op
);
574 env
->cc_op
= CC_OP_FLAGS
;
575 env
->sr
= (env
->sr
& 0xffe0)
576 | env
->cc_dest
| (env
->cc_x
<< 4);
577 log_cpu_state(env
, 0);
579 log_cpu_state(env
, 0);
582 #endif /* DEBUG_DISAS || CONFIG_DEBUG_EXEC */
585 /* Note: we do it here to avoid a gcc bug on Mac OS X when
586 doing it in tb_find_slow */
587 if (tb_invalidated_flag
) {
588 /* as some TB could have been invalidated because
589 of memory exceptions while generating the code, we
590 must recompute the hash index here */
592 tb_invalidated_flag
= 0;
594 #ifdef CONFIG_DEBUG_EXEC
595 qemu_log_mask(CPU_LOG_EXEC
, "Trace 0x%08lx [" TARGET_FMT_lx
"] %s\n",
596 (long)tb
->tc_ptr
, tb
->pc
,
597 lookup_symbol(tb
->pc
));
599 /* see if we can patch the calling TB. When the TB
600 spans two pages, we cannot safely do a direct
602 if (next_tb
!= 0 && tb
->page_addr
[1] == -1) {
603 tb_add_jump((TranslationBlock
*)(next_tb
& ~3), next_tb
& 3, tb
);
605 spin_unlock(&tb_lock
);
607 /* cpu_interrupt might be called while translating the
608 TB, but before it is linked into a potentially
609 infinite loop and becomes env->current_tb. Avoid
610 starting execution if there is a pending interrupt. */
611 env
->current_tb
= tb
;
613 if (likely(!env
->exit_request
)) {
615 /* execute the generated code */
616 #if defined(__sparc__) && !defined(CONFIG_SOLARIS)
618 env
= cpu_single_env
;
619 #define env cpu_single_env
621 next_tb
= tcg_qemu_tb_exec(tc_ptr
);
622 if ((next_tb
& 3) == 2) {
623 /* Instruction counter expired. */
625 tb
= (TranslationBlock
*)(long)(next_tb
& ~3);
627 cpu_pc_from_tb(env
, tb
);
628 insns_left
= env
->icount_decr
.u32
;
629 if (env
->icount_extra
&& insns_left
>= 0) {
630 /* Refill decrementer and continue execution. */
631 env
->icount_extra
+= insns_left
;
632 if (env
->icount_extra
> 0xffff) {
635 insns_left
= env
->icount_extra
;
637 env
->icount_extra
-= insns_left
;
638 env
->icount_decr
.u16
.low
= insns_left
;
640 if (insns_left
> 0) {
641 /* Execute remaining instructions. */
642 cpu_exec_nocache(insns_left
, tb
);
644 env
->exception_index
= EXCP_INTERRUPT
;
650 env
->current_tb
= NULL
;
651 /* reset soft MMU for next block (it can currently
652 only be set by a memory fault) */
658 #if defined(TARGET_I386)
659 /* restore flags in standard format */
660 env
->eflags
= env
->eflags
| helper_cc_compute_all(CC_OP
) | (DF
& DF_MASK
);
661 #elif defined(TARGET_ARM)
662 /* XXX: Save/restore host fpu exception state?. */
663 #elif defined(TARGET_SPARC)
664 #elif defined(TARGET_PPC)
665 #elif defined(TARGET_M68K)
666 cpu_m68k_flush_flags(env
, env
->cc_op
);
667 env
->cc_op
= CC_OP_FLAGS
;
668 env
->sr
= (env
->sr
& 0xffe0)
669 | env
->cc_dest
| (env
->cc_x
<< 4);
670 #elif defined(TARGET_MICROBLAZE)
671 #elif defined(TARGET_MIPS)
672 #elif defined(TARGET_SH4)
673 #elif defined(TARGET_IA64)
674 #elif defined(TARGET_ALPHA)
675 #elif defined(TARGET_CRIS)
676 #elif defined(TARGET_S390X)
679 #error unsupported target CPU
682 /* restore global registers */
684 env
= (void *) saved_env_reg
;
686 /* fail safe : never use cpu_single_env outside cpu_exec() */
687 cpu_single_env
= NULL
;
691 /* must only be called from the generated code as an exception can be
693 void tb_invalidate_page_range(target_ulong start
, target_ulong end
)
695 /* XXX: cannot enable it yet because it yields to MMU exception
696 where NIP != read address on PowerPC */
698 target_ulong phys_addr
;
699 phys_addr
= get_phys_addr_code(env
, start
);
700 tb_invalidate_phys_page_range(phys_addr
, phys_addr
+ end
- start
, 0);
704 #if defined(TARGET_I386) && defined(CONFIG_USER_ONLY)
706 void cpu_x86_load_seg(CPUX86State
*s
, int seg_reg
, int selector
)
708 CPUX86State
*saved_env
;
712 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
)) {
714 cpu_x86_load_seg_cache(env
, seg_reg
, selector
,
715 (selector
<< 4), 0xffff, 0);
717 helper_load_seg(seg_reg
, selector
);
722 void cpu_x86_fsave(CPUX86State
*s
, target_ulong ptr
, int data32
)
724 CPUX86State
*saved_env
;
729 helper_fsave(ptr
, data32
);
734 void cpu_x86_frstor(CPUX86State
*s
, target_ulong ptr
, int data32
)
736 CPUX86State
*saved_env
;
741 helper_frstor(ptr
, data32
);
746 #endif /* TARGET_I386 */
748 #if !defined(CONFIG_SOFTMMU)
750 #if defined(TARGET_I386)
751 #define EXCEPTION_ACTION raise_exception_err(env->exception_index, env->error_code)
753 #define EXCEPTION_ACTION cpu_loop_exit()
756 /* 'pc' is the host PC at which the exception was raised. 'address' is
757 the effective address of the memory exception. 'is_write' is 1 if a
758 write caused the exception and otherwise 0'. 'old_set' is the
759 signal set which should be restored */
760 static inline int handle_cpu_signal(unsigned long pc
, unsigned long address
,
761 int is_write
, sigset_t
*old_set
,
764 TranslationBlock
*tb
;
768 env
= cpu_single_env
; /* XXX: find a correct solution for multithread */
769 #if defined(DEBUG_SIGNAL)
770 qemu_printf("qemu: SIGSEGV pc=0x%08lx address=%08lx w=%d oldset=0x%08lx\n",
771 pc
, address
, is_write
, *(unsigned long *)old_set
);
773 /* XXX: locking issue */
774 if (is_write
&& page_unprotect(h2g(address
), pc
, puc
)) {
778 /* see if it is an MMU fault */
779 ret
= cpu_handle_mmu_fault(env
, address
, is_write
, MMU_USER_IDX
, 0);
781 return 0; /* not an MMU fault */
783 return 1; /* the MMU fault was handled without causing real CPU fault */
784 /* now we have a real cpu fault */
787 /* the PC is inside the translated code. It means that we have
788 a virtual CPU fault */
789 cpu_restore_state(tb
, env
, pc
, puc
);
792 /* we restore the process signal mask as the sigreturn should
793 do it (XXX: use sigsetjmp) */
794 sigprocmask(SIG_SETMASK
, old_set
, NULL
);
797 /* never comes here */
801 #if defined(__i386__)
803 #if defined(__APPLE__)
804 # include <sys/ucontext.h>
806 # define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext->ss.eip))
807 # define TRAP_sig(context) ((context)->uc_mcontext->es.trapno)
808 # define ERROR_sig(context) ((context)->uc_mcontext->es.err)
809 # define MASK_sig(context) ((context)->uc_sigmask)
810 #elif defined (__NetBSD__)
811 # include <ucontext.h>
813 # define EIP_sig(context) ((context)->uc_mcontext.__gregs[_REG_EIP])
814 # define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
815 # define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
816 # define MASK_sig(context) ((context)->uc_sigmask)
817 #elif defined (__FreeBSD__) || defined(__DragonFly__)
818 # include <ucontext.h>
820 # define EIP_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_eip))
821 # define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
822 # define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
823 # define MASK_sig(context) ((context)->uc_sigmask)
824 #elif defined(__OpenBSD__)
825 # define EIP_sig(context) ((context)->sc_eip)
826 # define TRAP_sig(context) ((context)->sc_trapno)
827 # define ERROR_sig(context) ((context)->sc_err)
828 # define MASK_sig(context) ((context)->sc_mask)
830 # define EIP_sig(context) ((context)->uc_mcontext.gregs[REG_EIP])
831 # define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
832 # define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
833 # define MASK_sig(context) ((context)->uc_sigmask)
836 int cpu_signal_handler(int host_signum
, void *pinfo
,
839 siginfo_t
*info
= pinfo
;
840 #if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
841 ucontext_t
*uc
= puc
;
842 #elif defined(__OpenBSD__)
843 struct sigcontext
*uc
= puc
;
845 struct ucontext
*uc
= puc
;
854 #define REG_TRAPNO TRAPNO
857 trapno
= TRAP_sig(uc
);
858 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
860 (ERROR_sig(uc
) >> 1) & 1 : 0,
864 #elif defined(__x86_64__)
867 #define PC_sig(context) _UC_MACHINE_PC(context)
868 #define TRAP_sig(context) ((context)->uc_mcontext.__gregs[_REG_TRAPNO])
869 #define ERROR_sig(context) ((context)->uc_mcontext.__gregs[_REG_ERR])
870 #define MASK_sig(context) ((context)->uc_sigmask)
871 #elif defined(__OpenBSD__)
872 #define PC_sig(context) ((context)->sc_rip)
873 #define TRAP_sig(context) ((context)->sc_trapno)
874 #define ERROR_sig(context) ((context)->sc_err)
875 #define MASK_sig(context) ((context)->sc_mask)
876 #elif defined (__FreeBSD__) || defined(__DragonFly__)
877 #include <ucontext.h>
879 #define PC_sig(context) (*((unsigned long*)&(context)->uc_mcontext.mc_rip))
880 #define TRAP_sig(context) ((context)->uc_mcontext.mc_trapno)
881 #define ERROR_sig(context) ((context)->uc_mcontext.mc_err)
882 #define MASK_sig(context) ((context)->uc_sigmask)
884 #define PC_sig(context) ((context)->uc_mcontext.gregs[REG_RIP])
885 #define TRAP_sig(context) ((context)->uc_mcontext.gregs[REG_TRAPNO])
886 #define ERROR_sig(context) ((context)->uc_mcontext.gregs[REG_ERR])
887 #define MASK_sig(context) ((context)->uc_sigmask)
890 int cpu_signal_handler(int host_signum
, void *pinfo
,
893 siginfo_t
*info
= pinfo
;
895 #if defined(__NetBSD__) || defined (__FreeBSD__) || defined(__DragonFly__)
896 ucontext_t
*uc
= puc
;
897 #elif defined(__OpenBSD__)
898 struct sigcontext
*uc
= puc
;
900 struct ucontext
*uc
= puc
;
904 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
905 TRAP_sig(uc
) == 0xe ?
906 (ERROR_sig(uc
) >> 1) & 1 : 0,
910 #elif defined(_ARCH_PPC)
912 /***********************************************************************
913 * signal context platform-specific definitions
917 /* All Registers access - only for local access */
918 # define REG_sig(reg_name, context) ((context)->uc_mcontext.regs->reg_name)
919 /* Gpr Registers access */
920 # define GPR_sig(reg_num, context) REG_sig(gpr[reg_num], context)
921 # define IAR_sig(context) REG_sig(nip, context) /* Program counter */
922 # define MSR_sig(context) REG_sig(msr, context) /* Machine State Register (Supervisor) */
923 # define CTR_sig(context) REG_sig(ctr, context) /* Count register */
924 # define XER_sig(context) REG_sig(xer, context) /* User's integer exception register */
925 # define LR_sig(context) REG_sig(link, context) /* Link register */
926 # define CR_sig(context) REG_sig(ccr, context) /* Condition register */
927 /* Float Registers access */
928 # define FLOAT_sig(reg_num, context) (((double*)((char*)((context)->uc_mcontext.regs+48*4)))[reg_num])
929 # define FPSCR_sig(context) (*(int*)((char*)((context)->uc_mcontext.regs+(48+32*2)*4)))
930 /* Exception Registers access */
931 # define DAR_sig(context) REG_sig(dar, context)
932 # define DSISR_sig(context) REG_sig(dsisr, context)
933 # define TRAP_sig(context) REG_sig(trap, context)
936 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
937 #include <ucontext.h>
938 # define IAR_sig(context) ((context)->uc_mcontext.mc_srr0)
939 # define MSR_sig(context) ((context)->uc_mcontext.mc_srr1)
940 # define CTR_sig(context) ((context)->uc_mcontext.mc_ctr)
941 # define XER_sig(context) ((context)->uc_mcontext.mc_xer)
942 # define LR_sig(context) ((context)->uc_mcontext.mc_lr)
943 # define CR_sig(context) ((context)->uc_mcontext.mc_cr)
944 /* Exception Registers access */
945 # define DAR_sig(context) ((context)->uc_mcontext.mc_dar)
946 # define DSISR_sig(context) ((context)->uc_mcontext.mc_dsisr)
947 # define TRAP_sig(context) ((context)->uc_mcontext.mc_exc)
948 #endif /* __FreeBSD__|| __FreeBSD_kernel__ */
951 # include <sys/ucontext.h>
952 typedef struct ucontext SIGCONTEXT
;
953 /* All Registers access - only for local access */
954 # define REG_sig(reg_name, context) ((context)->uc_mcontext->ss.reg_name)
955 # define FLOATREG_sig(reg_name, context) ((context)->uc_mcontext->fs.reg_name)
956 # define EXCEPREG_sig(reg_name, context) ((context)->uc_mcontext->es.reg_name)
957 # define VECREG_sig(reg_name, context) ((context)->uc_mcontext->vs.reg_name)
958 /* Gpr Registers access */
959 # define GPR_sig(reg_num, context) REG_sig(r##reg_num, context)
960 # define IAR_sig(context) REG_sig(srr0, context) /* Program counter */
961 # define MSR_sig(context) REG_sig(srr1, context) /* Machine State Register (Supervisor) */
962 # define CTR_sig(context) REG_sig(ctr, context)
963 # define XER_sig(context) REG_sig(xer, context) /* Link register */
964 # define LR_sig(context) REG_sig(lr, context) /* User's integer exception register */
965 # define CR_sig(context) REG_sig(cr, context) /* Condition register */
966 /* Float Registers access */
967 # define FLOAT_sig(reg_num, context) FLOATREG_sig(fpregs[reg_num], context)
968 # define FPSCR_sig(context) ((double)FLOATREG_sig(fpscr, context))
969 /* Exception Registers access */
970 # define DAR_sig(context) EXCEPREG_sig(dar, context) /* Fault registers for coredump */
971 # define DSISR_sig(context) EXCEPREG_sig(dsisr, context)
972 # define TRAP_sig(context) EXCEPREG_sig(exception, context) /* number of powerpc exception taken */
973 #endif /* __APPLE__ */
975 int cpu_signal_handler(int host_signum
, void *pinfo
,
978 siginfo_t
*info
= pinfo
;
979 #if defined(__FreeBSD__) || defined(__FreeBSD_kernel__)
980 ucontext_t
*uc
= puc
;
982 struct ucontext
*uc
= puc
;
991 if (DSISR_sig(uc
) & 0x00800000)
994 if (TRAP_sig(uc
) != 0x400 && (DSISR_sig(uc
) & 0x02000000))
997 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
998 is_write
, &uc
->uc_sigmask
, puc
);
1001 #elif defined(__alpha__)
1003 int cpu_signal_handler(int host_signum
, void *pinfo
,
1006 siginfo_t
*info
= pinfo
;
1007 struct ucontext
*uc
= puc
;
1008 uint32_t *pc
= uc
->uc_mcontext
.sc_pc
;
1009 uint32_t insn
= *pc
;
1012 /* XXX: need kernel patch to get write flag faster */
1013 switch (insn
>> 26) {
1028 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1029 is_write
, &uc
->uc_sigmask
, puc
);
1031 #elif defined(__sparc__)
1033 int cpu_signal_handler(int host_signum
, void *pinfo
,
1036 siginfo_t
*info
= pinfo
;
1039 #if !defined(__arch64__) || defined(CONFIG_SOLARIS)
1040 uint32_t *regs
= (uint32_t *)(info
+ 1);
1041 void *sigmask
= (regs
+ 20);
1042 /* XXX: is there a standard glibc define ? */
1043 unsigned long pc
= regs
[1];
1046 struct sigcontext
*sc
= puc
;
1047 unsigned long pc
= sc
->sigc_regs
.tpc
;
1048 void *sigmask
= (void *)sc
->sigc_mask
;
1049 #elif defined(__OpenBSD__)
1050 struct sigcontext
*uc
= puc
;
1051 unsigned long pc
= uc
->sc_pc
;
1052 void *sigmask
= (void *)(long)uc
->sc_mask
;
1056 /* XXX: need kernel patch to get write flag faster */
1058 insn
= *(uint32_t *)pc
;
1059 if ((insn
>> 30) == 3) {
1060 switch((insn
>> 19) & 0x3f) {
1084 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1085 is_write
, sigmask
, NULL
);
1088 #elif defined(__arm__)
1090 int cpu_signal_handler(int host_signum
, void *pinfo
,
1093 siginfo_t
*info
= pinfo
;
1094 struct ucontext
*uc
= puc
;
1098 #if (__GLIBC__ < 2 || (__GLIBC__ == 2 && __GLIBC_MINOR__ <= 3))
1099 pc
= uc
->uc_mcontext
.gregs
[R15
];
1101 pc
= uc
->uc_mcontext
.arm_pc
;
1103 /* XXX: compute is_write */
1105 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1107 &uc
->uc_sigmask
, puc
);
1110 #elif defined(__mc68000)
1112 int cpu_signal_handler(int host_signum
, void *pinfo
,
1115 siginfo_t
*info
= pinfo
;
1116 struct ucontext
*uc
= puc
;
1120 pc
= uc
->uc_mcontext
.gregs
[16];
1121 /* XXX: compute is_write */
1123 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1125 &uc
->uc_sigmask
, puc
);
1128 #elif defined(__ia64)
1131 /* This ought to be in <bits/siginfo.h>... */
1132 # define __ISR_VALID 1
1135 int cpu_signal_handler(int host_signum
, void *pinfo
, void *puc
)
1137 siginfo_t
*info
= pinfo
;
1138 struct ucontext
*uc
= puc
;
1142 ip
= uc
->uc_mcontext
.sc_ip
;
1143 switch (host_signum
) {
1149 if (info
->si_code
&& (info
->si_segvflags
& __ISR_VALID
))
1150 /* ISR.W (write-access) is bit 33: */
1151 is_write
= (info
->si_isr
>> 33) & 1;
1157 return handle_cpu_signal(ip
, (unsigned long)info
->si_addr
,
1159 (sigset_t
*)&uc
->uc_sigmask
, puc
);
1162 #elif defined(__s390__)
1164 int cpu_signal_handler(int host_signum
, void *pinfo
,
1167 siginfo_t
*info
= pinfo
;
1168 struct ucontext
*uc
= puc
;
1173 pc
= uc
->uc_mcontext
.psw
.addr
;
1175 /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead
1176 of the normal 2 arguments. The 3rd argument contains the "int_code"
1177 from the hardware which does in fact contain the is_write value.
1178 The rt signal handler, as far as I can tell, does not give this value
1179 at all. Not that we could get to it from here even if it were. */
1180 /* ??? This is not even close to complete, since it ignores all
1181 of the read-modify-write instructions. */
1182 pinsn
= (uint16_t *)pc
;
1183 switch (pinsn
[0] >> 8) {
1185 case 0x42: /* STC */
1186 case 0x40: /* STH */
1189 case 0xc4: /* RIL format insns */
1190 switch (pinsn
[0] & 0xf) {
1191 case 0xf: /* STRL */
1192 case 0xb: /* STGRL */
1193 case 0x7: /* STHRL */
1197 case 0xe3: /* RXY format insns */
1198 switch (pinsn
[2] & 0xff) {
1199 case 0x50: /* STY */
1200 case 0x24: /* STG */
1201 case 0x72: /* STCY */
1202 case 0x70: /* STHY */
1203 case 0x8e: /* STPQ */
1204 case 0x3f: /* STRVH */
1205 case 0x3e: /* STRV */
1206 case 0x2f: /* STRVG */
1211 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1212 is_write
, &uc
->uc_sigmask
, puc
);
1215 #elif defined(__mips__)
1217 int cpu_signal_handler(int host_signum
, void *pinfo
,
1220 siginfo_t
*info
= pinfo
;
1221 struct ucontext
*uc
= puc
;
1222 greg_t pc
= uc
->uc_mcontext
.pc
;
1225 /* XXX: compute is_write */
1227 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1228 is_write
, &uc
->uc_sigmask
, puc
);
1231 #elif defined(__hppa__)
1233 int cpu_signal_handler(int host_signum
, void *pinfo
,
1236 struct siginfo
*info
= pinfo
;
1237 struct ucontext
*uc
= puc
;
1238 unsigned long pc
= uc
->uc_mcontext
.sc_iaoq
[0];
1239 uint32_t insn
= *(uint32_t *)pc
;
1242 /* XXX: need kernel patch to get write flag faster. */
1243 switch (insn
>> 26) {
1244 case 0x1a: /* STW */
1245 case 0x19: /* STH */
1246 case 0x18: /* STB */
1247 case 0x1b: /* STWM */
1251 case 0x09: /* CSTWX, FSTWX, FSTWS */
1252 case 0x0b: /* CSTDX, FSTDX, FSTDS */
1253 /* Distinguish from coprocessor load ... */
1254 is_write
= (insn
>> 9) & 1;
1258 switch ((insn
>> 6) & 15) {
1259 case 0xa: /* STWS */
1260 case 0x9: /* STHS */
1261 case 0x8: /* STBS */
1262 case 0xe: /* STWAS */
1263 case 0xc: /* STBYS */
1269 return handle_cpu_signal(pc
, (unsigned long)info
->si_addr
,
1270 is_write
, &uc
->uc_sigmask
, puc
);
1275 #error host CPU specific signal handler needed
1279 #endif /* !defined(CONFIG_SOFTMMU) */