hw/sun4u.c

   1 /*
   2  * QEMU Sun4u/Sun4v System Emulator
   3  *
   4  * Copyright (c) 2005 Fabrice Bellard
   5  *
   6  * Permission is hereby granted, free of charge, to any person obtaining a copy
   7  * of this software and associated documentation files (the "Software"), to deal
   8  * in the Software without restriction, including without limitation the rights
   9  * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
  10  * copies of the Software, and to permit persons to whom the Software is
  11  * furnished to do so, subject to the following conditions:
  12  *
  13  * The above copyright notice and this permission notice shall be included in
  14  * all copies or substantial portions of the Software.
  15  *
  16  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  20  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  21  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
  22  * THE SOFTWARE.
  23  */
  24 #include "hw.h"
  25 #include "pci.h"
  26 #include "apb_pci.h"
  27 #include "pc.h"
  28 #include "nvram.h"
  29 #include "fdc.h"
  30 #include "net.h"
  31 #include "qemu-timer.h"
  32 #include "sysemu.h"
  33 #include "boards.h"
  34 #include "firmware_abi.h"
  35 #include "fw_cfg.h"
  36 #include "sysbus.h"
  37 #include "ide.h"
  38 #include "loader.h"
  39 #include "elf.h"
  40
  41 //#define DEBUG_IRQ
  42 //#define DEBUG_EBUS
  43 //#define DEBUG_TIMER
  44
  45 #ifdef DEBUG_IRQ
  46 #define CPUIRQ_DPRINTF(fmt, ...)                                \
  47     do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0)
  48 #else
  49 #define CPUIRQ_DPRINTF(fmt, ...)
  50 #endif
  51
  52 #ifdef DEBUG_EBUS
  53 #define EBUS_DPRINTF(fmt, ...)                                  \
  54     do { printf("EBUS: " fmt , ## __VA_ARGS__); } while (0)
  55 #else
  56 #define EBUS_DPRINTF(fmt, ...)
  57 #endif
  58
  59 #ifdef DEBUG_TIMER
  60 #define TIMER_DPRINTF(fmt, ...)                                  \
  61     do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0)
  62 #else
  63 #define TIMER_DPRINTF(fmt, ...)
  64 #endif
  65
  66 #define KERNEL_LOAD_ADDR     0x00404000
  67 #define CMDLINE_ADDR         0x003ff000
  68 #define INITRD_LOAD_ADDR     0x00300000
  69 #define PROM_SIZE_MAX        (4 * 1024 * 1024)
  70 #define PROM_VADDR           0x000ffd00000ULL
  71 #define APB_SPECIAL_BASE     0x1fe00000000ULL
  72 #define APB_MEM_BASE         0x1ff00000000ULL
  73 #define VGA_BASE             (APB_MEM_BASE + 0x400000ULL)
  74 #define PROM_FILENAME        "openbios-sparc64"
  75 #define NVRAM_SIZE           0x2000
  76 #define MAX_IDE_BUS          2
  77 #define BIOS_CFG_IOPORT      0x510
  78 #define FW_CFG_SPARC64_WIDTH (FW_CFG_ARCH_LOCAL + 0x00)
  79 #define FW_CFG_SPARC64_HEIGHT (FW_CFG_ARCH_LOCAL + 0x01)
  80 #define FW_CFG_SPARC64_DEPTH (FW_CFG_ARCH_LOCAL + 0x02)
  81
  82 #define MAX_PILS 16
  83
  84 #define TICK_MAX             0x7fffffffffffffffULL
  85
  86 struct hwdef {
  87     const char * const default_cpu_model;
  88     uint16_t machine_id;
  89     uint64_t prom_addr;
  90     uint64_t console_serial_base;
  91 };
  92
  93 int DMA_get_channel_mode (int nchan)
  94 {
  95     return 0;
  96 }
  97 int DMA_read_memory (int nchan, void *buf, int pos, int size)
  98 {
  99     return 0;
 100 }
 101 int DMA_write_memory (int nchan, void *buf, int pos, int size)
 102 {
 103     return 0;
 104 }
 105 void DMA_hold_DREQ (int nchan) {}
 106 void DMA_release_DREQ (int nchan) {}
 107 void DMA_schedule(int nchan) {}
 108 void DMA_init (int high_page_enable) {}
 109 void DMA_register_channel (int nchan,
 110                            DMA_transfer_handler transfer_handler,
 111                            void *opaque)
 112 {
 113 }
 114
 115 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
 116 {
 117     fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
 118     return 0;
 119 }
 120
 121 static int sun4u_NVRAM_set_params (m48t59_t *nvram, uint16_t NVRAM_size,
 122                                    const char *arch,
 123                                    ram_addr_t RAM_size,
 124                                    const char *boot_devices,
 125                                    uint32_t kernel_image, uint32_t kernel_size,
 126                                    const char *cmdline,
 127                                    uint32_t initrd_image, uint32_t initrd_size,
 128                                    uint32_t NVRAM_image,
 129                                    int width, int height, int depth,
 130                                    const uint8_t *macaddr)
 131 {
 132     unsigned int i;
 133     uint32_t start, end;
 134     uint8_t image[0x1ff0];
 135     struct OpenBIOS_nvpart_v1 *part_header;
 136
 137     memset(image, '\0', sizeof(image));
 138
 139     start = 0;
 140
 141     // OpenBIOS nvram variables
 142     // Variable partition
 143     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 144     part_header->signature = OPENBIOS_PART_SYSTEM;
 145     pstrcpy(part_header->name, sizeof(part_header->name), "system");
 146
 147     end = start + sizeof(struct OpenBIOS_nvpart_v1);
 148     for (i = 0; i < nb_prom_envs; i++)
 149         end = OpenBIOS_set_var(image, end, prom_envs[i]);
 150
 151     // End marker
 152     image[end++] = '\0';
 153
 154     end = start + ((end - start + 15) & ~15);
 155     OpenBIOS_finish_partition(part_header, end - start);
 156
 157     // free partition
 158     start = end;
 159     part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
 160     part_header->signature = OPENBIOS_PART_FREE;
 161     pstrcpy(part_header->name, sizeof(part_header->name), "free");
 162
 163     end = 0x1fd0;
 164     OpenBIOS_finish_partition(part_header, end - start);
 165
 166     Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr, 0x80);
 167
 168     for (i = 0; i < sizeof(image); i++)
 169         m48t59_write(nvram, i, image[i]);
 170
 171     return 0;
 172 }
 173 static unsigned long sun4u_load_kernel(const char *kernel_filename,
 174                                        const char *initrd_filename,
 175                                        ram_addr_t RAM_size, long *initrd_size)
 176 {
 177     int linux_boot;
 178     unsigned int i;
 179     long kernel_size;
 180     uint8_t *ptr;
 181
 182     linux_boot = (kernel_filename != NULL);
 183
 184     kernel_size = 0;
 185     if (linux_boot) {
 186         int bswap_needed;
 187
 188 #ifdef BSWAP_NEEDED
 189         bswap_needed = 1;
 190 #else
 191         bswap_needed = 0;
 192 #endif
 193         kernel_size = load_elf(kernel_filename, 0, NULL, NULL, NULL,
 194                                1, ELF_MACHINE, 0);
 195         if (kernel_size < 0)
 196             kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
 197                                     RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
 198                                     TARGET_PAGE_SIZE);
 199         if (kernel_size < 0)
 200             kernel_size = load_image_targphys(kernel_filename,
 201                                               KERNEL_LOAD_ADDR,
 202                                               RAM_size - KERNEL_LOAD_ADDR);
 203         if (kernel_size < 0) {
 204             fprintf(stderr, "qemu: could not load kernel '%s'\n",
 205                     kernel_filename);
 206             exit(1);
 207         }
 208
 209         /* load initrd */
 210         *initrd_size = 0;
 211         if (initrd_filename) {
 212             *initrd_size = load_image_targphys(initrd_filename,
 213                                                INITRD_LOAD_ADDR,
 214                                                RAM_size - INITRD_LOAD_ADDR);
 215             if (*initrd_size < 0) {
 216                 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
 217                         initrd_filename);
 218                 exit(1);
 219             }
 220         }
 221         if (*initrd_size > 0) {
 222             for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
 223                 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
 224                 if (ldl_p(ptr + 8) == 0x48647253) { /* HdrS */
 225                     stl_p(ptr + 24, INITRD_LOAD_ADDR + KERNEL_LOAD_ADDR - 0x4000);
 226                     stl_p(ptr + 28, *initrd_size);
 227                     break;
 228                 }
 229             }
 230         }
 231     }
 232     return kernel_size;
 233 }
 234
 235 void pic_info(Monitor *mon)
 236 {
 237 }
 238
 239 void irq_info(Monitor *mon)
 240 {
 241 }
 242
 243 void cpu_check_irqs(CPUState *env)
 244 {
 245     uint32_t pil = env->pil_in |
 246                   (env->softint & ~(SOFTINT_TIMER | SOFTINT_STIMER));
 247
 248     /* check if TM or SM in SOFTINT are set
 249        setting these also causes interrupt 14 */
 250     if (env->softint & (SOFTINT_TIMER | SOFTINT_STIMER)) {
 251         pil |= 1 << 14;
 252     }
 253
 254     if (!pil) {
 255         if (env->interrupt_request & CPU_INTERRUPT_HARD) {
 256             CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n",
 257                            env->interrupt_index);
 258             env->interrupt_index = 0;
 259             cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
 260         }
 261         return;
 262     }
 263
 264     if (cpu_interrupts_enabled(env)) {
 265
 266         unsigned int i;
 267
 268         for (i = 15; i > env->psrpil; i--) {
 269             if (pil & (1 << i)) {
 270                 int old_interrupt = env->interrupt_index;
 271                 int new_interrupt = TT_EXTINT | i;
 272
 273                 if (env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt) {
 274                     CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d "
 275                                    "current %x >= pending %x\n",
 276                                    env->tl, cpu_tsptr(env)->tt, new_interrupt);
 277                 } else if (old_interrupt != new_interrupt) {
 278                     env->interrupt_index = new_interrupt;
 279                     CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i,
 280                                    old_interrupt, new_interrupt);
 281                     cpu_interrupt(env, CPU_INTERRUPT_HARD);
 282                 }
 283                 break;
 284             }
 285         }
 286     } else {
 287         CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x "
 288                        "current interrupt %x\n",
 289                        pil, env->pil_in, env->softint, env->interrupt_index);
 290     }
 291 }
 292
 293 static void cpu_kick_irq(CPUState *env)
 294 {
 295     env->halted = 0;
 296     cpu_check_irqs(env);
 297 }
 298
 299 static void cpu_set_irq(void *opaque, int irq, int level)
 300 {
 301     CPUState *env = opaque;
 302
 303     if (level) {
 304         CPUIRQ_DPRINTF("Raise CPU IRQ %d\n", irq);
 305         env->halted = 0;
 306         env->pil_in |= 1 << irq;
 307         cpu_check_irqs(env);
 308     } else {
 309         CPUIRQ_DPRINTF("Lower CPU IRQ %d\n", irq);
 310         env->pil_in &= ~(1 << irq);
 311         cpu_check_irqs(env);
 312     }
 313 }
 314
 315 typedef struct ResetData {
 316     CPUState *env;
 317     uint64_t prom_addr;
 318 } ResetData;
 319
 320 void cpu_put_timer(QEMUFile *f, CPUTimer *s)
 321 {
 322     qemu_put_be32s(f, &s->frequency);
 323     qemu_put_be32s(f, &s->disabled);
 324     qemu_put_be64s(f, &s->disabled_mask);
 325     qemu_put_sbe64s(f, &s->clock_offset);
 326
 327     qemu_put_timer(f, s->qtimer);
 328 }
 329
 330 void cpu_get_timer(QEMUFile *f, CPUTimer *s)
 331 {
 332     qemu_get_be32s(f, &s->frequency);
 333     qemu_get_be32s(f, &s->disabled);
 334     qemu_get_be64s(f, &s->disabled_mask);
 335     qemu_get_sbe64s(f, &s->clock_offset);
 336
 337     qemu_get_timer(f, s->qtimer);
 338 }
 339
 340 static CPUTimer* cpu_timer_create(const char* name, CPUState *env,
 341                                   QEMUBHFunc *cb, uint32_t frequency,
 342                                   uint64_t disabled_mask)
 343 {
 344     CPUTimer *timer = qemu_mallocz(sizeof (CPUTimer));
 345
 346     timer->name = name;
 347     timer->frequency = frequency;
 348     timer->disabled_mask = disabled_mask;
 349
 350     timer->disabled = 1;
 351     timer->clock_offset = qemu_get_clock(vm_clock);
 352
 353     timer->qtimer = qemu_new_timer(vm_clock, cb, env);
 354
 355     return timer;
 356 }
 357
 358 static void cpu_timer_reset(CPUTimer *timer)
 359 {
 360     timer->disabled = 1;
 361     timer->clock_offset = qemu_get_clock(vm_clock);
 362
 363     qemu_del_timer(timer->qtimer);
 364 }
 365
 366 static void main_cpu_reset(void *opaque)
 367 {
 368     ResetData *s = (ResetData *)opaque;
 369     CPUState *env = s->env;
 370     static unsigned int nr_resets;
 371
 372     cpu_reset(env);
 373
 374     cpu_timer_reset(env->tick);
 375     cpu_timer_reset(env->stick);
 376     cpu_timer_reset(env->hstick);
 377
 378     env->gregs[1] = 0; // Memory start
 379     env->gregs[2] = ram_size; // Memory size
 380     env->gregs[3] = 0; // Machine description XXX
 381     if (nr_resets++ == 0) {
 382         /* Power on reset */
 383         env->pc = s->prom_addr + 0x20ULL;
 384     } else {
 385         env->pc = s->prom_addr + 0x40ULL;
 386     }
 387     env->npc = env->pc + 4;
 388 }
 389
 390 static void tick_irq(void *opaque)
 391 {
 392     CPUState *env = opaque;
 393
 394     CPUTimer* timer = env->tick;
 395
 396     if (timer->disabled) {
 397         CPUIRQ_DPRINTF("tick_irq: softint disabled\n");
 398         return;
 399     } else {
 400         CPUIRQ_DPRINTF("tick: fire\n");
 401     }
 402
 403     env->softint |= SOFTINT_TIMER;
 404     cpu_kick_irq(env);
 405 }
 406
 407 static void stick_irq(void *opaque)
 408 {
 409     CPUState *env = opaque;
 410
 411     CPUTimer* timer = env->stick;
 412
 413     if (timer->disabled) {
 414         CPUIRQ_DPRINTF("stick_irq: softint disabled\n");
 415         return;
 416     } else {
 417         CPUIRQ_DPRINTF("stick: fire\n");
 418     }
 419
 420     env->softint |= SOFTINT_STIMER;
 421     cpu_kick_irq(env);
 422 }
 423
 424 static void hstick_irq(void *opaque)
 425 {
 426     CPUState *env = opaque;
 427
 428     CPUTimer* timer = env->hstick;
 429
 430     if (timer->disabled) {
 431         CPUIRQ_DPRINTF("hstick_irq: softint disabled\n");
 432         return;
 433     } else {
 434         CPUIRQ_DPRINTF("hstick: fire\n");
 435     }
 436
 437     env->softint |= SOFTINT_STIMER;
 438     cpu_kick_irq(env);
 439 }
 440
 441 static int64_t cpu_to_timer_ticks(int64_t cpu_ticks, uint32_t frequency)
 442 {
 443     return muldiv64(cpu_ticks, get_ticks_per_sec(), frequency);
 444 }
 445
 446 static uint64_t timer_to_cpu_ticks(int64_t timer_ticks, uint32_t frequency)
 447 {
 448     return muldiv64(timer_ticks, frequency, get_ticks_per_sec());
 449 }
 450
 451 void cpu_tick_set_count(CPUTimer *timer, uint64_t count)
 452 {
 453     uint64_t real_count = count & ~timer->disabled_mask;
 454     uint64_t disabled_bit = count & timer->disabled_mask;
 455
 456     int64_t vm_clock_offset = qemu_get_clock(vm_clock) -
 457                     cpu_to_timer_ticks(real_count, timer->frequency);
 458
 459     TIMER_DPRINTF("%s set_count count=0x%016lx (%s) p=%p\n",
 460                   timer->name, real_count,
 461                   timer->disabled?"disabled":"enabled", timer);
 462
 463     timer->disabled = disabled_bit ? 1 : 0;
 464     timer->clock_offset = vm_clock_offset;
 465 }
 466
 467 uint64_t cpu_tick_get_count(CPUTimer *timer)
 468 {
 469     uint64_t real_count = timer_to_cpu_ticks(
 470                     qemu_get_clock(vm_clock) - timer->clock_offset,
 471                     timer->frequency);
 472
 473     TIMER_DPRINTF("%s get_count count=0x%016lx (%s) p=%p\n",
 474            timer->name, real_count,
 475            timer->disabled?"disabled":"enabled", timer);
 476
 477     if (timer->disabled)
 478         real_count |= timer->disabled_mask;
 479
 480     return real_count;
 481 }
 482
 483 void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit)
 484 {
 485     int64_t now = qemu_get_clock(vm_clock);
 486
 487     uint64_t real_limit = limit & ~timer->disabled_mask;
 488     timer->disabled = (limit & timer->disabled_mask) ? 1 : 0;
 489
 490     int64_t expires = cpu_to_timer_ticks(real_limit, timer->frequency) +
 491                     timer->clock_offset;
 492
 493     if (expires < now) {
 494         expires = now + 1;
 495     }
 496
 497     TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p "
 498                   "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n",
 499                   timer->name, real_limit,
 500                   timer->disabled?"disabled":"enabled",
 501                   timer, limit,
 502                   timer_to_cpu_ticks(now - timer->clock_offset,
 503                                      timer->frequency),
 504                   timer_to_cpu_ticks(expires - now, timer->frequency));
 505
 506     if (!real_limit) {
 507         TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n",
 508                 timer->name);
 509         qemu_del_timer(timer->qtimer);
 510     } else if (timer->disabled) {
 511         qemu_del_timer(timer->qtimer);
 512     } else {
 513         qemu_mod_timer(timer->qtimer, expires);
 514     }
 515 }
 516
 517 static void ebus_mmio_mapfunc(PCIDevice *pci_dev, int region_num,
 518                               pcibus_t addr, pcibus_t size, int type)
 519 {
 520     EBUS_DPRINTF("Mapping region %d registers at %" FMT_PCIBUS "\n",
 521                  region_num, addr);
 522     switch (region_num) {
 523     case 0:
 524         isa_mmio_init(addr, 0x1000000);
 525         break;
 526     case 1:
 527         isa_mmio_init(addr, 0x800000);
 528         break;
 529     }
 530 }
 531
 532 static void dummy_isa_irq_handler(void *opaque, int n, int level)
 533 {
 534 }
 535
 536 /* EBUS (Eight bit bus) bridge */
 537 static void
 538 pci_ebus_init(PCIBus *bus, int devfn)
 539 {
 540     qemu_irq *isa_irq;
 541
 542     pci_create_simple(bus, devfn, "ebus");
 543     isa_irq = qemu_allocate_irqs(dummy_isa_irq_handler, NULL, 16);
 544     isa_bus_irqs(isa_irq);
 545 }
 546
 547 static int
 548 pci_ebus_init1(PCIDevice *s)
 549 {
 550     isa_bus_new(&s->qdev);
 551
 552     pci_config_set_vendor_id(s->config, PCI_VENDOR_ID_SUN);
 553     pci_config_set_device_id(s->config, PCI_DEVICE_ID_SUN_EBUS);
 554     s->config[0x04] = 0x06; // command = bus master, pci mem
 555     s->config[0x05] = 0x00;
 556     s->config[0x06] = 0xa0; // status = fast back-to-back, 66MHz, no error
 557     s->config[0x07] = 0x03; // status = medium devsel
 558     s->config[0x08] = 0x01; // revision
 559     s->config[0x09] = 0x00; // programming i/f
 560     pci_config_set_class(s->config, PCI_CLASS_BRIDGE_OTHER);
 561     s->config[0x0D] = 0x0a; // latency_timer
 562     s->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; // header_type
 563
 564     pci_register_bar(s, 0, 0x1000000, PCI_BASE_ADDRESS_SPACE_MEMORY,
 565                            ebus_mmio_mapfunc);
 566     pci_register_bar(s, 1, 0x800000,  PCI_BASE_ADDRESS_SPACE_MEMORY,
 567                            ebus_mmio_mapfunc);
 568     return 0;
 569 }
 570
 571 static PCIDeviceInfo ebus_info = {
 572     .qdev.name = "ebus",
 573     .qdev.size = sizeof(PCIDevice),
 574     .init = pci_ebus_init1,
 575 };
 576
 577 static void pci_ebus_register(void)
 578 {
 579     pci_qdev_register(&ebus_info);
 580 }
 581
 582 device_init(pci_ebus_register);
 583
 584 /* Boot PROM (OpenBIOS) */
 585 static void prom_init(target_phys_addr_t addr, const char *bios_name)
 586 {
 587     DeviceState *dev;
 588     SysBusDevice *s;
 589     char *filename;
 590     int ret;
 591
 592     dev = qdev_create(NULL, "openprom");
 593     qdev_init_nofail(dev);
 594     s = sysbus_from_qdev(dev);
 595
 596     sysbus_mmio_map(s, 0, addr);
 597
 598     /* load boot prom */
 599     if (bios_name == NULL) {
 600         bios_name = PROM_FILENAME;
 601     }
 602     filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
 603     if (filename) {
 604         ret = load_elf(filename, addr - PROM_VADDR, NULL, NULL, NULL,
 605                        1, ELF_MACHINE, 0);
 606         if (ret < 0 || ret > PROM_SIZE_MAX) {
 607             ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
 608         }
 609         qemu_free(filename);
 610     } else {
 611         ret = -1;
 612     }
 613     if (ret < 0 || ret > PROM_SIZE_MAX) {
 614         fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
 615         exit(1);
 616     }
 617 }
 618
 619 static int prom_init1(SysBusDevice *dev)
 620 {
 621     ram_addr_t prom_offset;
 622
 623     prom_offset = qemu_ram_alloc(PROM_SIZE_MAX);
 624     sysbus_init_mmio(dev, PROM_SIZE_MAX, prom_offset | IO_MEM_ROM);
 625     return 0;
 626 }
 627
 628 static SysBusDeviceInfo prom_info = {
 629     .init = prom_init1,
 630     .qdev.name  = "openprom",
 631     .qdev.size  = sizeof(SysBusDevice),
 632     .qdev.props = (Property[]) {
 633         {/* end of property list */}
 634     }
 635 };
 636
 637 static void prom_register_devices(void)
 638 {
 639     sysbus_register_withprop(&prom_info);
 640 }
 641
 642 device_init(prom_register_devices);
 643
 644
 645 typedef struct RamDevice
 646 {
 647     SysBusDevice busdev;
 648     uint64_t size;
 649 } RamDevice;
 650
 651 /* System RAM */
 652 static int ram_init1(SysBusDevice *dev)
 653 {
 654     ram_addr_t RAM_size, ram_offset;
 655     RamDevice *d = FROM_SYSBUS(RamDevice, dev);
 656
 657     RAM_size = d->size;
 658
 659     ram_offset = qemu_ram_alloc(RAM_size);
 660     sysbus_init_mmio(dev, RAM_size, ram_offset);
 661     return 0;
 662 }
 663
 664 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size)
 665 {
 666     DeviceState *dev;
 667     SysBusDevice *s;
 668     RamDevice *d;
 669
 670     /* allocate RAM */
 671     dev = qdev_create(NULL, "memory");
 672     s = sysbus_from_qdev(dev);
 673
 674     d = FROM_SYSBUS(RamDevice, s);
 675     d->size = RAM_size;
 676     qdev_init_nofail(dev);
 677
 678     sysbus_mmio_map(s, 0, addr);
 679 }
 680
 681 static SysBusDeviceInfo ram_info = {
 682     .init = ram_init1,
 683     .qdev.name  = "memory",
 684     .qdev.size  = sizeof(RamDevice),
 685     .qdev.props = (Property[]) {
 686         DEFINE_PROP_UINT64("size", RamDevice, size, 0),
 687         DEFINE_PROP_END_OF_LIST(),
 688     }
 689 };
 690
 691 static void ram_register_devices(void)
 692 {
 693     sysbus_register_withprop(&ram_info);
 694 }
 695
 696 device_init(ram_register_devices);
 697
 698 static CPUState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef)
 699 {
 700     CPUState *env;
 701     ResetData *reset_info;
 702
 703     uint32_t   tick_frequency = 100*1000000;
 704     uint32_t  stick_frequency = 100*1000000;
 705     uint32_t hstick_frequency = 100*1000000;
 706
 707     if (!cpu_model)
 708         cpu_model = hwdef->default_cpu_model;
 709     env = cpu_init(cpu_model);
 710     if (!env) {
 711         fprintf(stderr, "Unable to find Sparc CPU definition\n");
 712         exit(1);
 713     }
 714
 715     env->tick = cpu_timer_create("tick", env, tick_irq,
 716                                   tick_frequency, TICK_NPT_MASK);
 717
 718     env->stick = cpu_timer_create("stick", env, stick_irq,
 719                                    stick_frequency, TICK_INT_DIS);
 720
 721     env->hstick = cpu_timer_create("hstick", env, hstick_irq,
 722                                     hstick_frequency, TICK_INT_DIS);
 723
 724     reset_info = qemu_mallocz(sizeof(ResetData));
 725     reset_info->env = env;
 726     reset_info->prom_addr = hwdef->prom_addr;
 727     qemu_register_reset(main_cpu_reset, reset_info);
 728
 729     return env;
 730 }
 731
 732 static void sun4uv_init(ram_addr_t RAM_size,
 733                         const char *boot_devices,
 734                         const char *kernel_filename, const char *kernel_cmdline,
 735                         const char *initrd_filename, const char *cpu_model,
 736                         const struct hwdef *hwdef)
 737 {
 738     CPUState *env;
 739     m48t59_t *nvram;
 740     unsigned int i;
 741     long initrd_size, kernel_size;
 742     PCIBus *pci_bus, *pci_bus2, *pci_bus3;
 743     qemu_irq *irq;
 744     DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS];
 745     DriveInfo *fd[MAX_FD];
 746     void *fw_cfg;
 747
 748     /* init CPUs */
 749     env = cpu_devinit(cpu_model, hwdef);
 750
 751     /* set up devices */
 752     ram_init(0, RAM_size);
 753
 754     prom_init(hwdef->prom_addr, bios_name);
 755
 756
 757     irq = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
 758     pci_bus = pci_apb_init(APB_SPECIAL_BASE, APB_MEM_BASE, irq, &pci_bus2,
 759                            &pci_bus3);
 760     isa_mem_base = VGA_BASE;
 761     pci_vga_init(pci_bus, 0, 0);
 762
 763     // XXX Should be pci_bus3
 764     pci_ebus_init(pci_bus, -1);
 765
 766     i = 0;
 767     if (hwdef->console_serial_base) {
 768         serial_mm_init(hwdef->console_serial_base, 0, NULL, 115200,
 769                        serial_hds[i], 1);
 770         i++;
 771     }
 772     for(; i < MAX_SERIAL_PORTS; i++) {
 773         if (serial_hds[i]) {
 774             serial_isa_init(i, serial_hds[i]);
 775         }
 776     }
 777
 778     for(i = 0; i < MAX_PARALLEL_PORTS; i++) {
 779         if (parallel_hds[i]) {
 780             parallel_init(i, parallel_hds[i]);
 781         }
 782     }
 783
 784     for(i = 0; i < nb_nics; i++)
 785         pci_nic_init_nofail(&nd_table[i], "ne2k_pci", NULL);
 786
 787     if (drive_get_max_bus(IF_IDE) >= MAX_IDE_BUS) {
 788         fprintf(stderr, "qemu: too many IDE bus\n");
 789         exit(1);
 790     }
 791     for(i = 0; i < MAX_IDE_BUS * MAX_IDE_DEVS; i++) {
 792         hd[i] = drive_get(IF_IDE, i / MAX_IDE_DEVS,
 793                           i % MAX_IDE_DEVS);
 794     }
 795
 796     pci_cmd646_ide_init(pci_bus, hd, 1);
 797
 798     isa_create_simple("i8042");
 799     for(i = 0; i < MAX_FD; i++) {
 800         fd[i] = drive_get(IF_FLOPPY, 0, i);
 801     }
 802     fdctrl_init_isa(fd);
 803     nvram = m48t59_init_isa(0x0074, NVRAM_SIZE, 59);
 804
 805     initrd_size = 0;
 806     kernel_size = sun4u_load_kernel(kernel_filename, initrd_filename,
 807                                     ram_size, &initrd_size);
 808
 809     sun4u_NVRAM_set_params(nvram, NVRAM_SIZE, "Sun4u", RAM_size, boot_devices,
 810                            KERNEL_LOAD_ADDR, kernel_size,
 811                            kernel_cmdline,
 812                            INITRD_LOAD_ADDR, initrd_size,
 813                            /* XXX: need an option to load a NVRAM image */
 814                            0,
 815                            graphic_width, graphic_height, graphic_depth,
 816                            (uint8_t *)&nd_table[0].macaddr);
 817
 818     fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0);
 819     fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
 820     fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
 821     fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
 822     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
 823     fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
 824     if (kernel_cmdline) {
 825         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
 826                        strlen(kernel_cmdline) + 1);
 827         fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
 828                          (uint8_t*)strdup(kernel_cmdline),
 829                          strlen(kernel_cmdline) + 1);
 830     } else {
 831         fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
 832     }
 833     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
 834     fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, initrd_size);
 835     fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_devices[0]);
 836
 837     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_WIDTH, graphic_width);
 838     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_HEIGHT, graphic_height);
 839     fw_cfg_add_i16(fw_cfg, FW_CFG_SPARC64_DEPTH, graphic_depth);
 840
 841     qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
 842 }
 843
 844 enum {
 845     sun4u_id = 0,
 846     sun4v_id = 64,
 847     niagara_id,
 848 };
 849
 850 static const struct hwdef hwdefs[] = {
 851     /* Sun4u generic PC-like machine */
 852     {
 853         .default_cpu_model = "TI UltraSparc II",
 854         .machine_id = sun4u_id,
 855         .prom_addr = 0x1fff0000000ULL,
 856         .console_serial_base = 0,
 857     },
 858     /* Sun4v generic PC-like machine */
 859     {
 860         .default_cpu_model = "Sun UltraSparc T1",
 861         .machine_id = sun4v_id,
 862         .prom_addr = 0x1fff0000000ULL,
 863         .console_serial_base = 0,
 864     },
 865     /* Sun4v generic Niagara machine */
 866     {
 867         .default_cpu_model = "Sun UltraSparc T1",
 868         .machine_id = niagara_id,
 869         .prom_addr = 0xfff0000000ULL,
 870         .console_serial_base = 0xfff0c2c000ULL,
 871     },
 872 };
 873
 874 /* Sun4u hardware initialisation */
 875 static void sun4u_init(ram_addr_t RAM_size,
 876                        const char *boot_devices,
 877                        const char *kernel_filename, const char *kernel_cmdline,
 878                        const char *initrd_filename, const char *cpu_model)
 879 {
 880     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 881                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[0]);
 882 }
 883
 884 /* Sun4v hardware initialisation */
 885 static void sun4v_init(ram_addr_t RAM_size,
 886                        const char *boot_devices,
 887                        const char *kernel_filename, const char *kernel_cmdline,
 888                        const char *initrd_filename, const char *cpu_model)
 889 {
 890     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 891                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[1]);
 892 }
 893
 894 /* Niagara hardware initialisation */
 895 static void niagara_init(ram_addr_t RAM_size,
 896                          const char *boot_devices,
 897                          const char *kernel_filename, const char *kernel_cmdline,
 898                          const char *initrd_filename, const char *cpu_model)
 899 {
 900     sun4uv_init(RAM_size, boot_devices, kernel_filename,
 901                 kernel_cmdline, initrd_filename, cpu_model, &hwdefs[2]);
 902 }
 903
 904 static QEMUMachine sun4u_machine = {
 905     .name = "sun4u",
 906     .desc = "Sun4u platform",
 907     .init = sun4u_init,
 908     .max_cpus = 1, // XXX for now
 909     .is_default = 1,
 910 };
 911
 912 static QEMUMachine sun4v_machine = {
 913     .name = "sun4v",
 914     .desc = "Sun4v platform",
 915     .init = sun4v_init,
 916     .max_cpus = 1, // XXX for now
 917 };
 918
 919 static QEMUMachine niagara_machine = {
 920     .name = "Niagara",
 921     .desc = "Sun4v platform, Niagara",
 922     .init = niagara_init,
 923     .max_cpus = 1, // XXX for now
 924 };
 925
 926 static void sun4u_machine_init(void)
 927 {
 928     qemu_register_machine(&sun4u_machine);
 929     qemu_register_machine(&sun4v_machine);
 930     qemu_register_machine(&niagara_machine);
 931 }
 932
 933 machine_init(sun4u_machine_init);