hw/nand.c

   1 /*
   2  * Flash NAND memory emulation.  Based on "16M x 8 Bit NAND Flash
   3  * Memory" datasheet for the KM29U128AT / K9F2808U0A chips from
   4  * Samsung Electronic.
   5  *
   6  * Copyright (c) 2006 Openedhand Ltd.
   7  * Written by Andrzej Zaborowski <balrog@zabor.org>
   8  *
   9  * Support for additional features based on "MT29F2G16ABCWP 2Gx16"
  10  * datasheet from Micron Technology and "NAND02G-B2C" datasheet
  11  * from ST Microelectronics.
  12  *
  13  * This code is licensed under the GNU GPL v2.
  14  *
  15  * Contributions after 2012-01-13 are licensed under the terms of the
  16  * GNU GPL, version 2 or (at your option) any later version.
  17  */
  18
  19 #ifndef NAND_IO
  20
  21 # include "hw.h"
  22 # include "flash.h"
  23 # include "sysemu/blockdev.h"
  24 # include "sysbus.h"
  25 #include "qemu/error-report.h"
  26
  27 # define NAND_CMD_READ0         0x00
  28 # define NAND_CMD_READ1         0x01
  29 # define NAND_CMD_READ2         0x50
  30 # define NAND_CMD_LPREAD2       0x30
  31 # define NAND_CMD_NOSERIALREAD2 0x35
  32 # define NAND_CMD_RANDOMREAD1   0x05
  33 # define NAND_CMD_RANDOMREAD2   0xe0
  34 # define NAND_CMD_READID        0x90
  35 # define NAND_CMD_RESET         0xff
  36 # define NAND_CMD_PAGEPROGRAM1  0x80
  37 # define NAND_CMD_PAGEPROGRAM2  0x10
  38 # define NAND_CMD_CACHEPROGRAM2 0x15
  39 # define NAND_CMD_BLOCKERASE1   0x60
  40 # define NAND_CMD_BLOCKERASE2   0xd0
  41 # define NAND_CMD_READSTATUS    0x70
  42 # define NAND_CMD_COPYBACKPRG1  0x85
  43
  44 # define NAND_IOSTATUS_ERROR    (1 << 0)
  45 # define NAND_IOSTATUS_PLANE0   (1 << 1)
  46 # define NAND_IOSTATUS_PLANE1   (1 << 2)
  47 # define NAND_IOSTATUS_PLANE2   (1 << 3)
  48 # define NAND_IOSTATUS_PLANE3   (1 << 4)
  49 # define NAND_IOSTATUS_READY    (1 << 6)
  50 # define NAND_IOSTATUS_UNPROTCT (1 << 7)
  51
  52 # define MAX_PAGE               0x800
  53 # define MAX_OOB                0x40
  54
  55 typedef struct NANDFlashState NANDFlashState;
  56 struct NANDFlashState {
  57     SysBusDevice busdev;
  58     uint8_t manf_id, chip_id;
  59     uint8_t buswidth; /* in BYTES */
  60     int size, pages;
  61     int page_shift, oob_shift, erase_shift, addr_shift;
  62     uint8_t *storage;
  63     BlockDriverState *bdrv;
  64     int mem_oob;
  65
  66     uint8_t cle, ale, ce, wp, gnd;
  67
  68     uint8_t io[MAX_PAGE + MAX_OOB + 0x400];
  69     uint8_t *ioaddr;
  70     int iolen;
  71
  72     uint32_t cmd;
  73     uint64_t addr;
  74     int addrlen;
  75     int status;
  76     int offset;
  77
  78     void (*blk_write)(NANDFlashState *s);
  79     void (*blk_erase)(NANDFlashState *s);
  80     void (*blk_load)(NANDFlashState *s, uint64_t addr, int offset);
  81
  82     uint32_t ioaddr_vmstate;
  83 };
  84
  85 static void mem_and(uint8_t *dest, const uint8_t *src, size_t n)
  86 {
  87     /* Like memcpy() but we logical-AND the data into the destination */
  88     int i;
  89     for (i = 0; i < n; i++) {
  90         dest[i] &= src[i];
  91     }
  92 }
  93
  94 # define NAND_NO_AUTOINCR       0x00000001
  95 # define NAND_BUSWIDTH_16       0x00000002
  96 # define NAND_NO_PADDING        0x00000004
  97 # define NAND_CACHEPRG          0x00000008
  98 # define NAND_COPYBACK          0x00000010
  99 # define NAND_IS_AND            0x00000020
 100 # define NAND_4PAGE_ARRAY       0x00000040
 101 # define NAND_NO_READRDY        0x00000100
 102 # define NAND_SAMSUNG_LP        (NAND_NO_PADDING | NAND_COPYBACK)
 103
 104 # define NAND_IO
 105
 106 # define PAGE(addr)             ((addr) >> ADDR_SHIFT)
 107 # define PAGE_START(page)       (PAGE(page) * (PAGE_SIZE + OOB_SIZE))
 108 # define PAGE_MASK              ((1 << ADDR_SHIFT) - 1)
 109 # define OOB_SHIFT              (PAGE_SHIFT - 5)
 110 # define OOB_SIZE               (1 << OOB_SHIFT)
 111 # define SECTOR(addr)           ((addr) >> (9 + ADDR_SHIFT - PAGE_SHIFT))
 112 # define SECTOR_OFFSET(addr)    ((addr) & ((511 >> PAGE_SHIFT) << 8))
 113
 114 # define PAGE_SIZE              256
 115 # define PAGE_SHIFT             8
 116 # define PAGE_SECTORS           1
 117 # define ADDR_SHIFT             8
 118 # include "nand.c"
 119 # define PAGE_SIZE              512
 120 # define PAGE_SHIFT             9
 121 # define PAGE_SECTORS           1
 122 # define ADDR_SHIFT             8
 123 # include "nand.c"
 124 # define PAGE_SIZE              2048
 125 # define PAGE_SHIFT             11
 126 # define PAGE_SECTORS           4
 127 # define ADDR_SHIFT             16
 128 # include "nand.c"
 129
 130 /* Information based on Linux drivers/mtd/nand/nand_ids.c */
 131 static const struct {
 132     int size;
 133     int width;
 134     int page_shift;
 135     int erase_shift;
 136     uint32_t options;
 137 } nand_flash_ids[0x100] = {
 138     [0 ... 0xff] = { 0 },
 139
 140     [0x6e] = { 1,       8,      8, 4, 0 },
 141     [0x64] = { 2,       8,      8, 4, 0 },
 142     [0x6b] = { 4,       8,      9, 4, 0 },
 143     [0xe8] = { 1,       8,      8, 4, 0 },
 144     [0xec] = { 1,       8,      8, 4, 0 },
 145     [0xea] = { 2,       8,      8, 4, 0 },
 146     [0xd5] = { 4,       8,      9, 4, 0 },
 147     [0xe3] = { 4,       8,      9, 4, 0 },
 148     [0xe5] = { 4,       8,      9, 4, 0 },
 149     [0xd6] = { 8,       8,      9, 4, 0 },
 150
 151     [0x39] = { 8,       8,      9, 4, 0 },
 152     [0xe6] = { 8,       8,      9, 4, 0 },
 153     [0x49] = { 8,       16,     9, 4, NAND_BUSWIDTH_16 },
 154     [0x59] = { 8,       16,     9, 4, NAND_BUSWIDTH_16 },
 155
 156     [0x33] = { 16,      8,      9, 5, 0 },
 157     [0x73] = { 16,      8,      9, 5, 0 },
 158     [0x43] = { 16,      16,     9, 5, NAND_BUSWIDTH_16 },
 159     [0x53] = { 16,      16,     9, 5, NAND_BUSWIDTH_16 },
 160
 161     [0x35] = { 32,      8,      9, 5, 0 },
 162     [0x75] = { 32,      8,      9, 5, 0 },
 163     [0x45] = { 32,      16,     9, 5, NAND_BUSWIDTH_16 },
 164     [0x55] = { 32,      16,     9, 5, NAND_BUSWIDTH_16 },
 165
 166     [0x36] = { 64,      8,      9, 5, 0 },
 167     [0x76] = { 64,      8,      9, 5, 0 },
 168     [0x46] = { 64,      16,     9, 5, NAND_BUSWIDTH_16 },
 169     [0x56] = { 64,      16,     9, 5, NAND_BUSWIDTH_16 },
 170
 171     [0x78] = { 128,     8,      9, 5, 0 },
 172     [0x39] = { 128,     8,      9, 5, 0 },
 173     [0x79] = { 128,     8,      9, 5, 0 },
 174     [0x72] = { 128,     16,     9, 5, NAND_BUSWIDTH_16 },
 175     [0x49] = { 128,     16,     9, 5, NAND_BUSWIDTH_16 },
 176     [0x74] = { 128,     16,     9, 5, NAND_BUSWIDTH_16 },
 177     [0x59] = { 128,     16,     9, 5, NAND_BUSWIDTH_16 },
 178
 179     [0x71] = { 256,     8,      9, 5, 0 },
 180
 181     /*
 182      * These are the new chips with large page size. The pagesize and the
 183      * erasesize is determined from the extended id bytes
 184      */
 185 # define LP_OPTIONS     (NAND_SAMSUNG_LP | NAND_NO_READRDY | NAND_NO_AUTOINCR)
 186 # define LP_OPTIONS16   (LP_OPTIONS | NAND_BUSWIDTH_16)
 187
 188     /* 512 Megabit */
 189     [0xa2] = { 64,      8,      0, 0, LP_OPTIONS },
 190     [0xf2] = { 64,      8,      0, 0, LP_OPTIONS },
 191     [0xb2] = { 64,      16,     0, 0, LP_OPTIONS16 },
 192     [0xc2] = { 64,      16,     0, 0, LP_OPTIONS16 },
 193
 194     /* 1 Gigabit */
 195     [0xa1] = { 128,     8,      0, 0, LP_OPTIONS },
 196     [0xf1] = { 128,     8,      0, 0, LP_OPTIONS },
 197     [0xb1] = { 128,     16,     0, 0, LP_OPTIONS16 },
 198     [0xc1] = { 128,     16,     0, 0, LP_OPTIONS16 },
 199
 200     /* 2 Gigabit */
 201     [0xaa] = { 256,     8,      0, 0, LP_OPTIONS },
 202     [0xda] = { 256,     8,      0, 0, LP_OPTIONS },
 203     [0xba] = { 256,     16,     0, 0, LP_OPTIONS16 },
 204     [0xca] = { 256,     16,     0, 0, LP_OPTIONS16 },
 205
 206     /* 4 Gigabit */
 207     [0xac] = { 512,     8,      0, 0, LP_OPTIONS },
 208     [0xdc] = { 512,     8,      0, 0, LP_OPTIONS },
 209     [0xbc] = { 512,     16,     0, 0, LP_OPTIONS16 },
 210     [0xcc] = { 512,     16,     0, 0, LP_OPTIONS16 },
 211
 212     /* 8 Gigabit */
 213     [0xa3] = { 1024,    8,      0, 0, LP_OPTIONS },
 214     [0xd3] = { 1024,    8,      0, 0, LP_OPTIONS },
 215     [0xb3] = { 1024,    16,     0, 0, LP_OPTIONS16 },
 216     [0xc3] = { 1024,    16,     0, 0, LP_OPTIONS16 },
 217
 218     /* 16 Gigabit */
 219     [0xa5] = { 2048,    8,      0, 0, LP_OPTIONS },
 220     [0xd5] = { 2048,    8,      0, 0, LP_OPTIONS },
 221     [0xb5] = { 2048,    16,     0, 0, LP_OPTIONS16 },
 222     [0xc5] = { 2048,    16,     0, 0, LP_OPTIONS16 },
 223 };
 224
 225 static void nand_reset(DeviceState *dev)
 226 {
 227     NANDFlashState *s = FROM_SYSBUS(NANDFlashState, SYS_BUS_DEVICE(dev));
 228     s->cmd = NAND_CMD_READ0;
 229     s->addr = 0;
 230     s->addrlen = 0;
 231     s->iolen = 0;
 232     s->offset = 0;
 233     s->status &= NAND_IOSTATUS_UNPROTCT;
 234     s->status |= NAND_IOSTATUS_READY;
 235 }
 236
 237 static inline void nand_pushio_byte(NANDFlashState *s, uint8_t value)
 238 {
 239     s->ioaddr[s->iolen++] = value;
 240     for (value = s->buswidth; --value;) {
 241         s->ioaddr[s->iolen++] = 0;
 242     }
 243 }
 244
 245 static void nand_command(NANDFlashState *s)
 246 {
 247     unsigned int offset;
 248     switch (s->cmd) {
 249     case NAND_CMD_READ0:
 250         s->iolen = 0;
 251         break;
 252
 253     case NAND_CMD_READID:
 254         s->ioaddr = s->io;
 255         s->iolen = 0;
 256         nand_pushio_byte(s, s->manf_id);
 257         nand_pushio_byte(s, s->chip_id);
 258         nand_pushio_byte(s, 'Q'); /* Don't-care byte (often 0xa5) */
 259         if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
 260             /* Page Size, Block Size, Spare Size; bit 6 indicates
 261              * 8 vs 16 bit width NAND.
 262              */
 263             nand_pushio_byte(s, (s->buswidth == 2) ? 0x55 : 0x15);
 264         } else {
 265             nand_pushio_byte(s, 0xc0); /* Multi-plane */
 266         }
 267         break;
 268
 269     case NAND_CMD_RANDOMREAD2:
 270     case NAND_CMD_NOSERIALREAD2:
 271         if (!(nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP))
 272             break;
 273         offset = s->addr & ((1 << s->addr_shift) - 1);
 274         s->blk_load(s, s->addr, offset);
 275         if (s->gnd)
 276             s->iolen = (1 << s->page_shift) - offset;
 277         else
 278             s->iolen = (1 << s->page_shift) + (1 << s->oob_shift) - offset;
 279         break;
 280
 281     case NAND_CMD_RESET:
 282         nand_reset(&s->busdev.qdev);
 283         break;
 284
 285     case NAND_CMD_PAGEPROGRAM1:
 286         s->ioaddr = s->io;
 287         s->iolen = 0;
 288         break;
 289
 290     case NAND_CMD_PAGEPROGRAM2:
 291         if (s->wp) {
 292             s->blk_write(s);
 293         }
 294         break;
 295
 296     case NAND_CMD_BLOCKERASE1:
 297         break;
 298
 299     case NAND_CMD_BLOCKERASE2:
 300         if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP)
 301             s->addr <<= 16;
 302         else
 303             s->addr <<= 8;
 304
 305         if (s->wp) {
 306             s->blk_erase(s);
 307         }
 308         break;
 309
 310     case NAND_CMD_READSTATUS:
 311         s->ioaddr = s->io;
 312         s->iolen = 0;
 313         nand_pushio_byte(s, s->status);
 314         break;
 315
 316     default:
 317         printf("%s: Unknown NAND command 0x%02x\n", __FUNCTION__, s->cmd);
 318     }
 319 }
 320
 321 static void nand_pre_save(void *opaque)
 322 {
 323     NANDFlashState *s = opaque;
 324
 325     s->ioaddr_vmstate = s->ioaddr - s->io;
 326 }
 327
 328 static int nand_post_load(void *opaque, int version_id)
 329 {
 330     NANDFlashState *s = opaque;
 331
 332     if (s->ioaddr_vmstate > sizeof(s->io)) {
 333         return -EINVAL;
 334     }
 335     s->ioaddr = s->io + s->ioaddr_vmstate;
 336
 337     return 0;
 338 }
 339
 340 static const VMStateDescription vmstate_nand = {
 341     .name = "nand",
 342     .version_id = 1,
 343     .minimum_version_id = 1,
 344     .minimum_version_id_old = 1,
 345     .pre_save = nand_pre_save,
 346     .post_load = nand_post_load,
 347     .fields      = (VMStateField[]) {
 348         VMSTATE_UINT8(cle, NANDFlashState),
 349         VMSTATE_UINT8(ale, NANDFlashState),
 350         VMSTATE_UINT8(ce, NANDFlashState),
 351         VMSTATE_UINT8(wp, NANDFlashState),
 352         VMSTATE_UINT8(gnd, NANDFlashState),
 353         VMSTATE_BUFFER(io, NANDFlashState),
 354         VMSTATE_UINT32(ioaddr_vmstate, NANDFlashState),
 355         VMSTATE_INT32(iolen, NANDFlashState),
 356         VMSTATE_UINT32(cmd, NANDFlashState),
 357         VMSTATE_UINT64(addr, NANDFlashState),
 358         VMSTATE_INT32(addrlen, NANDFlashState),
 359         VMSTATE_INT32(status, NANDFlashState),
 360         VMSTATE_INT32(offset, NANDFlashState),
 361         /* XXX: do we want to save s->storage too? */
 362         VMSTATE_END_OF_LIST()
 363     }
 364 };
 365
 366 static int nand_device_init(SysBusDevice *dev)
 367 {
 368     int pagesize;
 369     NANDFlashState *s = FROM_SYSBUS(NANDFlashState, dev);
 370
 371     s->buswidth = nand_flash_ids[s->chip_id].width >> 3;
 372     s->size = nand_flash_ids[s->chip_id].size << 20;
 373     if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
 374         s->page_shift = 11;
 375         s->erase_shift = 6;
 376     } else {
 377         s->page_shift = nand_flash_ids[s->chip_id].page_shift;
 378         s->erase_shift = nand_flash_ids[s->chip_id].erase_shift;
 379     }
 380
 381     switch (1 << s->page_shift) {
 382     case 256:
 383         nand_init_256(s);
 384         break;
 385     case 512:
 386         nand_init_512(s);
 387         break;
 388     case 2048:
 389         nand_init_2048(s);
 390         break;
 391     default:
 392         error_report("Unsupported NAND block size");
 393         return -1;
 394     }
 395
 396     pagesize = 1 << s->oob_shift;
 397     s->mem_oob = 1;
 398     if (s->bdrv) {
 399         if (bdrv_is_read_only(s->bdrv)) {
 400             error_report("Can't use a read-only drive");
 401             return -1;
 402         }
 403         if (bdrv_getlength(s->bdrv) >=
 404                 (s->pages << s->page_shift) + (s->pages << s->oob_shift)) {
 405             pagesize = 0;
 406             s->mem_oob = 0;
 407         }
 408     } else {
 409         pagesize += 1 << s->page_shift;
 410     }
 411     if (pagesize) {
 412         s->storage = (uint8_t *) memset(g_malloc(s->pages * pagesize),
 413                         0xff, s->pages * pagesize);
 414     }
 415     /* Give s->ioaddr a sane value in case we save state before it is used. */
 416     s->ioaddr = s->io;
 417
 418     return 0;
 419 }
 420
 421 static Property nand_properties[] = {
 422     DEFINE_PROP_UINT8("manufacturer_id", NANDFlashState, manf_id, 0),
 423     DEFINE_PROP_UINT8("chip_id", NANDFlashState, chip_id, 0),
 424     DEFINE_PROP_DRIVE("drive", NANDFlashState, bdrv),
 425     DEFINE_PROP_END_OF_LIST(),
 426 };
 427
 428 static void nand_class_init(ObjectClass *klass, void *data)
 429 {
 430     DeviceClass *dc = DEVICE_CLASS(klass);
 431     SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
 432
 433     k->init = nand_device_init;
 434     dc->reset = nand_reset;
 435     dc->vmsd = &vmstate_nand;
 436     dc->props = nand_properties;
 437 }
 438
 439 static const TypeInfo nand_info = {
 440     .name          = "nand",
 441     .parent        = TYPE_SYS_BUS_DEVICE,
 442     .instance_size = sizeof(NANDFlashState),
 443     .class_init    = nand_class_init,
 444 };
 445
 446 static void nand_register_types(void)
 447 {
 448     type_register_static(&nand_info);
 449 }
 450
 451 /*
 452  * Chip inputs are CLE, ALE, CE, WP, GND and eight I/O pins.  Chip
 453  * outputs are R/B and eight I/O pins.
 454  *
 455  * CE, WP and R/B are active low.
 456  */
 457 void nand_setpins(DeviceState *dev, uint8_t cle, uint8_t ale,
 458                   uint8_t ce, uint8_t wp, uint8_t gnd)
 459 {
 460     NANDFlashState *s = (NANDFlashState *) dev;
 461     s->cle = cle;
 462     s->ale = ale;
 463     s->ce = ce;
 464     s->wp = wp;
 465     s->gnd = gnd;
 466     if (wp)
 467         s->status |= NAND_IOSTATUS_UNPROTCT;
 468     else
 469         s->status &= ~NAND_IOSTATUS_UNPROTCT;
 470 }
 471
 472 void nand_getpins(DeviceState *dev, int *rb)
 473 {
 474     *rb = 1;
 475 }
 476
 477 void nand_setio(DeviceState *dev, uint32_t value)
 478 {
 479     int i;
 480     NANDFlashState *s = (NANDFlashState *) dev;
 481     if (!s->ce && s->cle) {
 482         if (nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) {
 483             if (s->cmd == NAND_CMD_READ0 && value == NAND_CMD_LPREAD2)
 484                 return;
 485             if (value == NAND_CMD_RANDOMREAD1) {
 486                 s->addr &= ~((1 << s->addr_shift) - 1);
 487                 s->addrlen = 0;
 488                 return;
 489             }
 490         }
 491         if (value == NAND_CMD_READ0)
 492             s->offset = 0;
 493         else if (value == NAND_CMD_READ1) {
 494             s->offset = 0x100;
 495             value = NAND_CMD_READ0;
 496         }
 497         else if (value == NAND_CMD_READ2) {
 498             s->offset = 1 << s->page_shift;
 499             value = NAND_CMD_READ0;
 500         }
 501
 502         s->cmd = value;
 503
 504         if (s->cmd == NAND_CMD_READSTATUS ||
 505                 s->cmd == NAND_CMD_PAGEPROGRAM2 ||
 506                 s->cmd == NAND_CMD_BLOCKERASE1 ||
 507                 s->cmd == NAND_CMD_BLOCKERASE2 ||
 508                 s->cmd == NAND_CMD_NOSERIALREAD2 ||
 509                 s->cmd == NAND_CMD_RANDOMREAD2 ||
 510                 s->cmd == NAND_CMD_RESET)
 511             nand_command(s);
 512
 513         if (s->cmd != NAND_CMD_RANDOMREAD2) {
 514             s->addrlen = 0;
 515         }
 516     }
 517
 518     if (s->ale) {
 519         unsigned int shift = s->addrlen * 8;
 520         unsigned int mask = ~(0xff << shift);
 521         unsigned int v = value << shift;
 522
 523         s->addr = (s->addr & mask) | v;
 524         s->addrlen ++;
 525
 526         switch (s->addrlen) {
 527         case 1:
 528             if (s->cmd == NAND_CMD_READID) {
 529                 nand_command(s);
 530             }
 531             break;
 532         case 2: /* fix cache address as a byte address */
 533             s->addr <<= (s->buswidth - 1);
 534             break;
 535         case 3:
 536             if (!(nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
 537                     (s->cmd == NAND_CMD_READ0 ||
 538                      s->cmd == NAND_CMD_PAGEPROGRAM1)) {
 539                 nand_command(s);
 540             }
 541             break;
 542         case 4:
 543             if ((nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
 544                     nand_flash_ids[s->chip_id].size < 256 && /* 1Gb or less */
 545                     (s->cmd == NAND_CMD_READ0 ||
 546                      s->cmd == NAND_CMD_PAGEPROGRAM1)) {
 547                 nand_command(s);
 548             }
 549             break;
 550         case 5:
 551             if ((nand_flash_ids[s->chip_id].options & NAND_SAMSUNG_LP) &&
 552                     nand_flash_ids[s->chip_id].size >= 256 && /* 2Gb or more */
 553                     (s->cmd == NAND_CMD_READ0 ||
 554                      s->cmd == NAND_CMD_PAGEPROGRAM1)) {
 555                 nand_command(s);
 556             }
 557             break;
 558         default:
 559             break;
 560         }
 561     }
 562
 563     if (!s->cle && !s->ale && s->cmd == NAND_CMD_PAGEPROGRAM1) {
 564         if (s->iolen < (1 << s->page_shift) + (1 << s->oob_shift)) {
 565             for (i = s->buswidth; i--; value >>= 8) {
 566                 s->io[s->iolen ++] = (uint8_t) (value & 0xff);
 567             }
 568         }
 569     } else if (!s->cle && !s->ale && s->cmd == NAND_CMD_COPYBACKPRG1) {
 570         if ((s->addr & ((1 << s->addr_shift) - 1)) <
 571                 (1 << s->page_shift) + (1 << s->oob_shift)) {
 572             for (i = s->buswidth; i--; s->addr++, value >>= 8) {
 573                 s->io[s->iolen + (s->addr & ((1 << s->addr_shift) - 1))] =
 574                     (uint8_t) (value & 0xff);
 575             }
 576         }
 577     }
 578 }
 579
 580 uint32_t nand_getio(DeviceState *dev)
 581 {
 582     int offset;
 583     uint32_t x = 0;
 584     NANDFlashState *s = (NANDFlashState *) dev;
 585
 586     /* Allow sequential reading */
 587     if (!s->iolen && s->cmd == NAND_CMD_READ0) {
 588         offset = (int) (s->addr & ((1 << s->addr_shift) - 1)) + s->offset;
 589         s->offset = 0;
 590
 591         s->blk_load(s, s->addr, offset);
 592         if (s->gnd)
 593             s->iolen = (1 << s->page_shift) - offset;
 594         else
 595             s->iolen = (1 << s->page_shift) + (1 << s->oob_shift) - offset;
 596     }
 597
 598     if (s->ce || s->iolen <= 0)
 599         return 0;
 600
 601     for (offset = s->buswidth; offset--;) {
 602         x |= s->ioaddr[offset] << (offset << 3);
 603     }
 604     /* after receiving READ STATUS command all subsequent reads will
 605      * return the status register value until another command is issued
 606      */
 607     if (s->cmd != NAND_CMD_READSTATUS) {
 608         s->addr   += s->buswidth;
 609         s->ioaddr += s->buswidth;
 610         s->iolen  -= s->buswidth;
 611     }
 612     return x;
 613 }
 614
 615 uint32_t nand_getbuswidth(DeviceState *dev)
 616 {
 617     NANDFlashState *s = (NANDFlashState *) dev;
 618     return s->buswidth << 3;
 619 }
 620
 621 DeviceState *nand_init(BlockDriverState *bdrv, int manf_id, int chip_id)
 622 {
 623     DeviceState *dev;
 624
 625     if (nand_flash_ids[chip_id].size == 0) {
 626         hw_error("%s: Unsupported NAND chip ID.\n", __FUNCTION__);
 627     }
 628     dev = qdev_create(NULL, "nand");
 629     qdev_prop_set_uint8(dev, "manufacturer_id", manf_id);
 630     qdev_prop_set_uint8(dev, "chip_id", chip_id);
 631     if (bdrv) {
 632         qdev_prop_set_drive_nofail(dev, "drive", bdrv);
 633     }
 634
 635     qdev_init_nofail(dev);
 636     return dev;
 637 }
 638
 639 type_init(nand_register_types)
 640
 641 #else
 642
 643 /* Program a single page */
 644 static void glue(nand_blk_write_, PAGE_SIZE)(NANDFlashState *s)
 645 {
 646     uint64_t off, page, sector, soff;
 647     uint8_t iobuf[(PAGE_SECTORS + 2) * 0x200];
 648     if (PAGE(s->addr) >= s->pages)
 649         return;
 650
 651     if (!s->bdrv) {
 652         mem_and(s->storage + PAGE_START(s->addr) + (s->addr & PAGE_MASK) +
 653                         s->offset, s->io, s->iolen);
 654     } else if (s->mem_oob) {
 655         sector = SECTOR(s->addr);
 656         off = (s->addr & PAGE_MASK) + s->offset;
 657         soff = SECTOR_OFFSET(s->addr);
 658         if (bdrv_read(s->bdrv, sector, iobuf, PAGE_SECTORS) < 0) {
 659             printf("%s: read error in sector %" PRIu64 "\n", __func__, sector);
 660             return;
 661         }
 662
 663         mem_and(iobuf + (soff | off), s->io, MIN(s->iolen, PAGE_SIZE - off));
 664         if (off + s->iolen > PAGE_SIZE) {
 665             page = PAGE(s->addr);
 666             mem_and(s->storage + (page << OOB_SHIFT), s->io + PAGE_SIZE - off,
 667                             MIN(OOB_SIZE, off + s->iolen - PAGE_SIZE));
 668         }
 669
 670         if (bdrv_write(s->bdrv, sector, iobuf, PAGE_SECTORS) < 0) {
 671             printf("%s: write error in sector %" PRIu64 "\n", __func__, sector);
 672         }
 673     } else {
 674         off = PAGE_START(s->addr) + (s->addr & PAGE_MASK) + s->offset;
 675         sector = off >> 9;
 676         soff = off & 0x1ff;
 677         if (bdrv_read(s->bdrv, sector, iobuf, PAGE_SECTORS + 2) < 0) {
 678             printf("%s: read error in sector %" PRIu64 "\n", __func__, sector);
 679             return;
 680         }
 681
 682         mem_and(iobuf + soff, s->io, s->iolen);
 683
 684         if (bdrv_write(s->bdrv, sector, iobuf, PAGE_SECTORS + 2) < 0) {
 685             printf("%s: write error in sector %" PRIu64 "\n", __func__, sector);
 686         }
 687     }
 688     s->offset = 0;
 689 }
 690
 691 /* Erase a single block */
 692 static void glue(nand_blk_erase_, PAGE_SIZE)(NANDFlashState *s)
 693 {
 694     uint64_t i, page, addr;
 695     uint8_t iobuf[0x200] = { [0 ... 0x1ff] = 0xff, };
 696     addr = s->addr & ~((1 << (ADDR_SHIFT + s->erase_shift)) - 1);
 697
 698     if (PAGE(addr) >= s->pages)
 699         return;
 700
 701     if (!s->bdrv) {
 702         memset(s->storage + PAGE_START(addr),
 703                         0xff, (PAGE_SIZE + OOB_SIZE) << s->erase_shift);
 704     } else if (s->mem_oob) {
 705         memset(s->storage + (PAGE(addr) << OOB_SHIFT),
 706                         0xff, OOB_SIZE << s->erase_shift);
 707         i = SECTOR(addr);
 708         page = SECTOR(addr + (ADDR_SHIFT + s->erase_shift));
 709         for (; i < page; i ++)
 710             if (bdrv_write(s->bdrv, i, iobuf, 1) < 0) {
 711                 printf("%s: write error in sector %" PRIu64 "\n", __func__, i);
 712             }
 713     } else {
 714         addr = PAGE_START(addr);
 715         page = addr >> 9;
 716         if (bdrv_read(s->bdrv, page, iobuf, 1) < 0) {
 717             printf("%s: read error in sector %" PRIu64 "\n", __func__, page);
 718         }
 719         memset(iobuf + (addr & 0x1ff), 0xff, (~addr & 0x1ff) + 1);
 720         if (bdrv_write(s->bdrv, page, iobuf, 1) < 0) {
 721             printf("%s: write error in sector %" PRIu64 "\n", __func__, page);
 722         }
 723
 724         memset(iobuf, 0xff, 0x200);
 725         i = (addr & ~0x1ff) + 0x200;
 726         for (addr += ((PAGE_SIZE + OOB_SIZE) << s->erase_shift) - 0x200;
 727                         i < addr; i += 0x200)
 728             if (bdrv_write(s->bdrv, i >> 9, iobuf, 1) < 0) {
 729                 printf("%s: write error in sector %" PRIu64 "\n",
 730                        __func__, i >> 9);
 731             }
 732
 733         page = i >> 9;
 734         if (bdrv_read(s->bdrv, page, iobuf, 1) < 0) {
 735             printf("%s: read error in sector %" PRIu64 "\n", __func__, page);
 736         }
 737         memset(iobuf, 0xff, ((addr - 1) & 0x1ff) + 1);
 738         if (bdrv_write(s->bdrv, page, iobuf, 1) < 0) {
 739             printf("%s: write error in sector %" PRIu64 "\n", __func__, page);
 740         }
 741     }
 742 }
 743
 744 static void glue(nand_blk_load_, PAGE_SIZE)(NANDFlashState *s,
 745                 uint64_t addr, int offset)
 746 {
 747     if (PAGE(addr) >= s->pages)
 748         return;
 749
 750     if (s->bdrv) {
 751         if (s->mem_oob) {
 752             if (bdrv_read(s->bdrv, SECTOR(addr), s->io, PAGE_SECTORS) < 0) {
 753                 printf("%s: read error in sector %" PRIu64 "\n",
 754                                 __func__, SECTOR(addr));
 755             }
 756             memcpy(s->io + SECTOR_OFFSET(s->addr) + PAGE_SIZE,
 757                             s->storage + (PAGE(s->addr) << OOB_SHIFT),
 758                             OOB_SIZE);
 759             s->ioaddr = s->io + SECTOR_OFFSET(s->addr) + offset;
 760         } else {
 761             if (bdrv_read(s->bdrv, PAGE_START(addr) >> 9,
 762                                     s->io, (PAGE_SECTORS + 2)) < 0) {
 763                 printf("%s: read error in sector %" PRIu64 "\n",
 764                                 __func__, PAGE_START(addr) >> 9);
 765             }
 766             s->ioaddr = s->io + (PAGE_START(addr) & 0x1ff) + offset;
 767         }
 768     } else {
 769         memcpy(s->io, s->storage + PAGE_START(s->addr) +
 770                         offset, PAGE_SIZE + OOB_SIZE - offset);
 771         s->ioaddr = s->io;
 772     }
 773 }
 774
 775 static void glue(nand_init_, PAGE_SIZE)(NANDFlashState *s)
 776 {
 777     s->oob_shift = PAGE_SHIFT - 5;
 778     s->pages = s->size >> PAGE_SHIFT;
 779     s->addr_shift = ADDR_SHIFT;
 780
 781     s->blk_erase = glue(nand_blk_erase_, PAGE_SIZE);
 782     s->blk_write = glue(nand_blk_write_, PAGE_SIZE);
 783     s->blk_load = glue(nand_blk_load_, PAGE_SIZE);
 784 }
 785
 786 # undef PAGE_SIZE
 787 # undef PAGE_SHIFT
 788 # undef PAGE_SECTORS
 789 # undef ADDR_SHIFT
 790 #endif  /* NAND_IO */