4 * Copyright (C) 2006-2008 Qumranet Technologies
5 * Copyright IBM, Corp. 2008
8 * Anthony Liguori <aliguori@us.ibm.com>
10 * This work is licensed under the terms of the GNU GPL, version 2 or later.
11 * See the COPYING file in the top-level directory.
15 #include <sys/types.h>
16 #include <sys/ioctl.h>
18 #include <sys/utsname.h>
20 #include <linux/kvm.h>
21 #include <linux/kvm_para.h>
23 #include "qemu-common.h"
24 #include "sysemu/sysemu.h"
25 #include "sysemu/kvm.h"
28 #include "exec/gdbstub.h"
29 #include "qemu/host-utils.h"
30 #include "qemu/config-file.h"
31 #include "hw/i386/pc.h"
32 #include "hw/i386/apic.h"
33 #include "hw/i386/apic_internal.h"
34 #include "hw/i386/apic-msidef.h"
35 #include "exec/ioport.h"
36 #include <asm/hyperv.h>
37 #include "hw/pci/pci.h"
42 #define DPRINTF(fmt, ...) \
43 do { fprintf(stderr, fmt, ## __VA_ARGS__); } while (0)
45 #define DPRINTF(fmt, ...) \
49 #define MSR_KVM_WALL_CLOCK 0x11
50 #define MSR_KVM_SYSTEM_TIME 0x12
53 #define BUS_MCEERR_AR 4
56 #define BUS_MCEERR_AO 5
59 const KVMCapabilityInfo kvm_arch_required_capabilities
[] = {
60 KVM_CAP_INFO(SET_TSS_ADDR
),
61 KVM_CAP_INFO(EXT_CPUID
),
62 KVM_CAP_INFO(MP_STATE
),
66 static bool has_msr_star
;
67 static bool has_msr_hsave_pa
;
68 static bool has_msr_tsc_adjust
;
69 static bool has_msr_tsc_deadline
;
70 static bool has_msr_feature_control
;
71 static bool has_msr_async_pf_en
;
72 static bool has_msr_pv_eoi_en
;
73 static bool has_msr_misc_enable
;
74 static bool has_msr_bndcfgs
;
75 static bool has_msr_kvm_steal_time
;
76 static int lm_capable_kernel
;
77 static bool has_msr_hv_hypercall
;
78 static bool has_msr_hv_vapic
;
79 static bool has_msr_hv_tsc
;
81 static bool has_msr_architectural_pmu
;
82 static uint32_t num_architectural_pmu_counters
;
84 bool kvm_allows_irq0_override(void)
86 return !kvm_irqchip_in_kernel() || kvm_has_gsi_routing();
89 static struct kvm_cpuid2
*try_get_cpuid(KVMState
*s
, int max
)
91 struct kvm_cpuid2
*cpuid
;
94 size
= sizeof(*cpuid
) + max
* sizeof(*cpuid
->entries
);
95 cpuid
= (struct kvm_cpuid2
*)g_malloc0(size
);
97 r
= kvm_ioctl(s
, KVM_GET_SUPPORTED_CPUID
, cpuid
);
98 if (r
== 0 && cpuid
->nent
>= max
) {
106 fprintf(stderr
, "KVM_GET_SUPPORTED_CPUID failed: %s\n",
114 /* Run KVM_GET_SUPPORTED_CPUID ioctl(), allocating a buffer large enough
117 static struct kvm_cpuid2
*get_supported_cpuid(KVMState
*s
)
119 struct kvm_cpuid2
*cpuid
;
121 while ((cpuid
= try_get_cpuid(s
, max
)) == NULL
) {
127 static const struct kvm_para_features
{
130 } para_features
[] = {
131 { KVM_CAP_CLOCKSOURCE
, KVM_FEATURE_CLOCKSOURCE
},
132 { KVM_CAP_NOP_IO_DELAY
, KVM_FEATURE_NOP_IO_DELAY
},
133 { KVM_CAP_PV_MMU
, KVM_FEATURE_MMU_OP
},
134 { KVM_CAP_ASYNC_PF
, KVM_FEATURE_ASYNC_PF
},
137 static int get_para_features(KVMState
*s
)
141 for (i
= 0; i
< ARRAY_SIZE(para_features
); i
++) {
142 if (kvm_check_extension(s
, para_features
[i
].cap
)) {
143 features
|= (1 << para_features
[i
].feature
);
151 /* Returns the value for a specific register on the cpuid entry
153 static uint32_t cpuid_entry_get_reg(struct kvm_cpuid_entry2
*entry
, int reg
)
173 /* Find matching entry for function/index on kvm_cpuid2 struct
175 static struct kvm_cpuid_entry2
*cpuid_find_entry(struct kvm_cpuid2
*cpuid
,
180 for (i
= 0; i
< cpuid
->nent
; ++i
) {
181 if (cpuid
->entries
[i
].function
== function
&&
182 cpuid
->entries
[i
].index
== index
) {
183 return &cpuid
->entries
[i
];
190 uint32_t kvm_arch_get_supported_cpuid(KVMState
*s
, uint32_t function
,
191 uint32_t index
, int reg
)
193 struct kvm_cpuid2
*cpuid
;
195 uint32_t cpuid_1_edx
;
198 cpuid
= get_supported_cpuid(s
);
200 struct kvm_cpuid_entry2
*entry
= cpuid_find_entry(cpuid
, function
, index
);
203 ret
= cpuid_entry_get_reg(entry
, reg
);
206 /* Fixups for the data returned by KVM, below */
208 if (function
== 1 && reg
== R_EDX
) {
209 /* KVM before 2.6.30 misreports the following features */
210 ret
|= CPUID_MTRR
| CPUID_PAT
| CPUID_MCE
| CPUID_MCA
;
211 } else if (function
== 1 && reg
== R_ECX
) {
212 /* We can set the hypervisor flag, even if KVM does not return it on
213 * GET_SUPPORTED_CPUID
215 ret
|= CPUID_EXT_HYPERVISOR
;
216 /* tsc-deadline flag is not returned by GET_SUPPORTED_CPUID, but it
217 * can be enabled if the kernel has KVM_CAP_TSC_DEADLINE_TIMER,
218 * and the irqchip is in the kernel.
220 if (kvm_irqchip_in_kernel() &&
221 kvm_check_extension(s
, KVM_CAP_TSC_DEADLINE_TIMER
)) {
222 ret
|= CPUID_EXT_TSC_DEADLINE_TIMER
;
225 /* x2apic is reported by GET_SUPPORTED_CPUID, but it can't be enabled
226 * without the in-kernel irqchip
228 if (!kvm_irqchip_in_kernel()) {
229 ret
&= ~CPUID_EXT_X2APIC
;
231 } else if (function
== 0x80000001 && reg
== R_EDX
) {
232 /* On Intel, kvm returns cpuid according to the Intel spec,
233 * so add missing bits according to the AMD spec:
235 cpuid_1_edx
= kvm_arch_get_supported_cpuid(s
, 1, 0, R_EDX
);
236 ret
|= cpuid_1_edx
& CPUID_EXT2_AMD_ALIASES
;
241 /* fallback for older kernels */
242 if ((function
== KVM_CPUID_FEATURES
) && !found
) {
243 ret
= get_para_features(s
);
249 typedef struct HWPoisonPage
{
251 QLIST_ENTRY(HWPoisonPage
) list
;
254 static QLIST_HEAD(, HWPoisonPage
) hwpoison_page_list
=
255 QLIST_HEAD_INITIALIZER(hwpoison_page_list
);
257 static void kvm_unpoison_all(void *param
)
259 HWPoisonPage
*page
, *next_page
;
261 QLIST_FOREACH_SAFE(page
, &hwpoison_page_list
, list
, next_page
) {
262 QLIST_REMOVE(page
, list
);
263 qemu_ram_remap(page
->ram_addr
, TARGET_PAGE_SIZE
);
268 static void kvm_hwpoison_page_add(ram_addr_t ram_addr
)
272 QLIST_FOREACH(page
, &hwpoison_page_list
, list
) {
273 if (page
->ram_addr
== ram_addr
) {
277 page
= g_malloc(sizeof(HWPoisonPage
));
278 page
->ram_addr
= ram_addr
;
279 QLIST_INSERT_HEAD(&hwpoison_page_list
, page
, list
);
282 static int kvm_get_mce_cap_supported(KVMState
*s
, uint64_t *mce_cap
,
287 r
= kvm_check_extension(s
, KVM_CAP_MCE
);
290 return kvm_ioctl(s
, KVM_X86_GET_MCE_CAP_SUPPORTED
, mce_cap
);
295 static void kvm_mce_inject(X86CPU
*cpu
, hwaddr paddr
, int code
)
297 CPUX86State
*env
= &cpu
->env
;
298 uint64_t status
= MCI_STATUS_VAL
| MCI_STATUS_UC
| MCI_STATUS_EN
|
299 MCI_STATUS_MISCV
| MCI_STATUS_ADDRV
| MCI_STATUS_S
;
300 uint64_t mcg_status
= MCG_STATUS_MCIP
;
302 if (code
== BUS_MCEERR_AR
) {
303 status
|= MCI_STATUS_AR
| 0x134;
304 mcg_status
|= MCG_STATUS_EIPV
;
307 mcg_status
|= MCG_STATUS_RIPV
;
309 cpu_x86_inject_mce(NULL
, cpu
, 9, status
, mcg_status
, paddr
,
310 (MCM_ADDR_PHYS
<< 6) | 0xc,
311 cpu_x86_support_mca_broadcast(env
) ?
312 MCE_INJECT_BROADCAST
: 0);
315 static void hardware_memory_error(void)
317 fprintf(stderr
, "Hardware memory error!\n");
321 int kvm_arch_on_sigbus_vcpu(CPUState
*c
, int code
, void *addr
)
323 X86CPU
*cpu
= X86_CPU(c
);
324 CPUX86State
*env
= &cpu
->env
;
328 if ((env
->mcg_cap
& MCG_SER_P
) && addr
329 && (code
== BUS_MCEERR_AR
|| code
== BUS_MCEERR_AO
)) {
330 if (qemu_ram_addr_from_host(addr
, &ram_addr
) == NULL
||
331 !kvm_physical_memory_addr_from_host(c
->kvm_state
, addr
, &paddr
)) {
332 fprintf(stderr
, "Hardware memory error for memory used by "
333 "QEMU itself instead of guest system!\n");
334 /* Hope we are lucky for AO MCE */
335 if (code
== BUS_MCEERR_AO
) {
338 hardware_memory_error();
341 kvm_hwpoison_page_add(ram_addr
);
342 kvm_mce_inject(cpu
, paddr
, code
);
344 if (code
== BUS_MCEERR_AO
) {
346 } else if (code
== BUS_MCEERR_AR
) {
347 hardware_memory_error();
355 int kvm_arch_on_sigbus(int code
, void *addr
)
357 X86CPU
*cpu
= X86_CPU(first_cpu
);
359 if ((cpu
->env
.mcg_cap
& MCG_SER_P
) && addr
&& code
== BUS_MCEERR_AO
) {
363 /* Hope we are lucky for AO MCE */
364 if (qemu_ram_addr_from_host(addr
, &ram_addr
) == NULL
||
365 !kvm_physical_memory_addr_from_host(first_cpu
->kvm_state
,
367 fprintf(stderr
, "Hardware memory error for memory used by "
368 "QEMU itself instead of guest system!: %p\n", addr
);
371 kvm_hwpoison_page_add(ram_addr
);
372 kvm_mce_inject(X86_CPU(first_cpu
), paddr
, code
);
374 if (code
== BUS_MCEERR_AO
) {
376 } else if (code
== BUS_MCEERR_AR
) {
377 hardware_memory_error();
385 static int kvm_inject_mce_oldstyle(X86CPU
*cpu
)
387 CPUX86State
*env
= &cpu
->env
;
389 if (!kvm_has_vcpu_events() && env
->exception_injected
== EXCP12_MCHK
) {
390 unsigned int bank
, bank_num
= env
->mcg_cap
& 0xff;
391 struct kvm_x86_mce mce
;
393 env
->exception_injected
= -1;
396 * There must be at least one bank in use if an MCE is pending.
397 * Find it and use its values for the event injection.
399 for (bank
= 0; bank
< bank_num
; bank
++) {
400 if (env
->mce_banks
[bank
* 4 + 1] & MCI_STATUS_VAL
) {
404 assert(bank
< bank_num
);
407 mce
.status
= env
->mce_banks
[bank
* 4 + 1];
408 mce
.mcg_status
= env
->mcg_status
;
409 mce
.addr
= env
->mce_banks
[bank
* 4 + 2];
410 mce
.misc
= env
->mce_banks
[bank
* 4 + 3];
412 return kvm_vcpu_ioctl(CPU(cpu
), KVM_X86_SET_MCE
, &mce
);
417 static void cpu_update_state(void *opaque
, int running
, RunState state
)
419 CPUX86State
*env
= opaque
;
422 env
->tsc_valid
= false;
426 unsigned long kvm_arch_vcpu_id(CPUState
*cs
)
428 X86CPU
*cpu
= X86_CPU(cs
);
429 return cpu
->env
.cpuid_apic_id
;
432 #ifndef KVM_CPUID_SIGNATURE_NEXT
433 #define KVM_CPUID_SIGNATURE_NEXT 0x40000100
436 static bool hyperv_hypercall_available(X86CPU
*cpu
)
438 return cpu
->hyperv_vapic
||
439 (cpu
->hyperv_spinlock_attempts
!= HYPERV_SPINLOCK_NEVER_RETRY
);
442 static bool hyperv_enabled(X86CPU
*cpu
)
444 CPUState
*cs
= CPU(cpu
);
445 return kvm_check_extension(cs
->kvm_state
, KVM_CAP_HYPERV
) > 0 &&
446 (hyperv_hypercall_available(cpu
) ||
448 cpu
->hyperv_relaxed_timing
);
451 #define KVM_MAX_CPUID_ENTRIES 100
453 int kvm_arch_init_vcpu(CPUState
*cs
)
456 struct kvm_cpuid2 cpuid
;
457 struct kvm_cpuid_entry2 entries
[KVM_MAX_CPUID_ENTRIES
];
458 } QEMU_PACKED cpuid_data
;
459 X86CPU
*cpu
= X86_CPU(cs
);
460 CPUX86State
*env
= &cpu
->env
;
461 uint32_t limit
, i
, j
, cpuid_i
;
463 struct kvm_cpuid_entry2
*c
;
464 uint32_t signature
[3];
465 int kvm_base
= KVM_CPUID_SIGNATURE
;
468 memset(&cpuid_data
, 0, sizeof(cpuid_data
));
472 /* Paravirtualization CPUIDs */
473 if (hyperv_enabled(cpu
)) {
474 c
= &cpuid_data
.entries
[cpuid_i
++];
475 c
->function
= HYPERV_CPUID_VENDOR_AND_MAX_FUNCTIONS
;
476 memcpy(signature
, "Microsoft Hv", 12);
477 c
->eax
= HYPERV_CPUID_MIN
;
478 c
->ebx
= signature
[0];
479 c
->ecx
= signature
[1];
480 c
->edx
= signature
[2];
482 c
= &cpuid_data
.entries
[cpuid_i
++];
483 c
->function
= HYPERV_CPUID_INTERFACE
;
484 memcpy(signature
, "Hv#1\0\0\0\0\0\0\0\0", 12);
485 c
->eax
= signature
[0];
490 c
= &cpuid_data
.entries
[cpuid_i
++];
491 c
->function
= HYPERV_CPUID_VERSION
;
495 c
= &cpuid_data
.entries
[cpuid_i
++];
496 c
->function
= HYPERV_CPUID_FEATURES
;
497 if (cpu
->hyperv_relaxed_timing
) {
498 c
->eax
|= HV_X64_MSR_HYPERCALL_AVAILABLE
;
500 if (cpu
->hyperv_vapic
) {
501 c
->eax
|= HV_X64_MSR_HYPERCALL_AVAILABLE
;
502 c
->eax
|= HV_X64_MSR_APIC_ACCESS_AVAILABLE
;
503 has_msr_hv_vapic
= true;
505 if (cpu
->hyperv_time
&&
506 kvm_check_extension(cs
->kvm_state
, KVM_CAP_HYPERV_TIME
) > 0) {
507 c
->eax
|= HV_X64_MSR_HYPERCALL_AVAILABLE
;
508 c
->eax
|= HV_X64_MSR_TIME_REF_COUNT_AVAILABLE
;
510 has_msr_hv_tsc
= true;
512 c
= &cpuid_data
.entries
[cpuid_i
++];
513 c
->function
= HYPERV_CPUID_ENLIGHTMENT_INFO
;
514 if (cpu
->hyperv_relaxed_timing
) {
515 c
->eax
|= HV_X64_RELAXED_TIMING_RECOMMENDED
;
517 if (has_msr_hv_vapic
) {
518 c
->eax
|= HV_X64_APIC_ACCESS_RECOMMENDED
;
520 c
->ebx
= cpu
->hyperv_spinlock_attempts
;
522 c
= &cpuid_data
.entries
[cpuid_i
++];
523 c
->function
= HYPERV_CPUID_IMPLEMENT_LIMITS
;
527 kvm_base
= KVM_CPUID_SIGNATURE_NEXT
;
528 has_msr_hv_hypercall
= true;
531 if (cpu
->expose_kvm
) {
532 memcpy(signature
, "KVMKVMKVM\0\0\0", 12);
533 c
= &cpuid_data
.entries
[cpuid_i
++];
534 c
->function
= KVM_CPUID_SIGNATURE
| kvm_base
;
535 c
->eax
= KVM_CPUID_FEATURES
| kvm_base
;
536 c
->ebx
= signature
[0];
537 c
->ecx
= signature
[1];
538 c
->edx
= signature
[2];
540 c
= &cpuid_data
.entries
[cpuid_i
++];
541 c
->function
= KVM_CPUID_FEATURES
| kvm_base
;
542 c
->eax
= env
->features
[FEAT_KVM
];
544 has_msr_async_pf_en
= c
->eax
& (1 << KVM_FEATURE_ASYNC_PF
);
546 has_msr_pv_eoi_en
= c
->eax
& (1 << KVM_FEATURE_PV_EOI
);
548 has_msr_kvm_steal_time
= c
->eax
& (1 << KVM_FEATURE_STEAL_TIME
);
551 cpu_x86_cpuid(env
, 0, 0, &limit
, &unused
, &unused
, &unused
);
553 for (i
= 0; i
<= limit
; i
++) {
554 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
555 fprintf(stderr
, "unsupported level value: 0x%x\n", limit
);
558 c
= &cpuid_data
.entries
[cpuid_i
++];
562 /* Keep reading function 2 till all the input is received */
566 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
|
567 KVM_CPUID_FLAG_STATE_READ_NEXT
;
568 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
569 times
= c
->eax
& 0xff;
571 for (j
= 1; j
< times
; ++j
) {
572 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
573 fprintf(stderr
, "cpuid_data is full, no space for "
574 "cpuid(eax:2):eax & 0xf = 0x%x\n", times
);
577 c
= &cpuid_data
.entries
[cpuid_i
++];
579 c
->flags
= KVM_CPUID_FLAG_STATEFUL_FUNC
;
580 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
588 if (i
== 0xd && j
== 64) {
592 c
->flags
= KVM_CPUID_FLAG_SIGNIFCANT_INDEX
;
594 cpu_x86_cpuid(env
, i
, j
, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
596 if (i
== 4 && c
->eax
== 0) {
599 if (i
== 0xb && !(c
->ecx
& 0xff00)) {
602 if (i
== 0xd && c
->eax
== 0) {
605 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
606 fprintf(stderr
, "cpuid_data is full, no space for "
607 "cpuid(eax:0x%x,ecx:0x%x)\n", i
, j
);
610 c
= &cpuid_data
.entries
[cpuid_i
++];
616 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
624 cpu_x86_cpuid(env
, 0x0a, 0, &ver
, &unused
, &unused
, &unused
);
625 if ((ver
& 0xff) > 0) {
626 has_msr_architectural_pmu
= true;
627 num_architectural_pmu_counters
= (ver
& 0xff00) >> 8;
629 /* Shouldn't be more than 32, since that's the number of bits
630 * available in EBX to tell us _which_ counters are available.
633 if (num_architectural_pmu_counters
> MAX_GP_COUNTERS
) {
634 num_architectural_pmu_counters
= MAX_GP_COUNTERS
;
639 cpu_x86_cpuid(env
, 0x80000000, 0, &limit
, &unused
, &unused
, &unused
);
641 for (i
= 0x80000000; i
<= limit
; i
++) {
642 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
643 fprintf(stderr
, "unsupported xlevel value: 0x%x\n", limit
);
646 c
= &cpuid_data
.entries
[cpuid_i
++];
650 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
653 /* Call Centaur's CPUID instructions they are supported. */
654 if (env
->cpuid_xlevel2
> 0) {
655 cpu_x86_cpuid(env
, 0xC0000000, 0, &limit
, &unused
, &unused
, &unused
);
657 for (i
= 0xC0000000; i
<= limit
; i
++) {
658 if (cpuid_i
== KVM_MAX_CPUID_ENTRIES
) {
659 fprintf(stderr
, "unsupported xlevel2 value: 0x%x\n", limit
);
662 c
= &cpuid_data
.entries
[cpuid_i
++];
666 cpu_x86_cpuid(env
, i
, 0, &c
->eax
, &c
->ebx
, &c
->ecx
, &c
->edx
);
670 cpuid_data
.cpuid
.nent
= cpuid_i
;
672 if (((env
->cpuid_version
>> 8)&0xF) >= 6
673 && (env
->features
[FEAT_1_EDX
] & (CPUID_MCE
| CPUID_MCA
)) ==
674 (CPUID_MCE
| CPUID_MCA
)
675 && kvm_check_extension(cs
->kvm_state
, KVM_CAP_MCE
) > 0) {
680 ret
= kvm_get_mce_cap_supported(cs
->kvm_state
, &mcg_cap
, &banks
);
682 fprintf(stderr
, "kvm_get_mce_cap_supported: %s", strerror(-ret
));
686 if (banks
> MCE_BANKS_DEF
) {
687 banks
= MCE_BANKS_DEF
;
689 mcg_cap
&= MCE_CAP_DEF
;
691 ret
= kvm_vcpu_ioctl(cs
, KVM_X86_SETUP_MCE
, &mcg_cap
);
693 fprintf(stderr
, "KVM_X86_SETUP_MCE: %s", strerror(-ret
));
697 env
->mcg_cap
= mcg_cap
;
700 qemu_add_vm_change_state_handler(cpu_update_state
, env
);
702 c
= cpuid_find_entry(&cpuid_data
.cpuid
, 1, 0);
704 has_msr_feature_control
= !!(c
->ecx
& CPUID_EXT_VMX
) ||
705 !!(c
->ecx
& CPUID_EXT_SMX
);
708 cpuid_data
.cpuid
.padding
= 0;
709 r
= kvm_vcpu_ioctl(cs
, KVM_SET_CPUID2
, &cpuid_data
);
714 r
= kvm_check_extension(cs
->kvm_state
, KVM_CAP_TSC_CONTROL
);
715 if (r
&& env
->tsc_khz
) {
716 r
= kvm_vcpu_ioctl(cs
, KVM_SET_TSC_KHZ
, env
->tsc_khz
);
718 fprintf(stderr
, "KVM_SET_TSC_KHZ failed\n");
723 if (kvm_has_xsave()) {
724 env
->kvm_xsave_buf
= qemu_memalign(4096, sizeof(struct kvm_xsave
));
730 void kvm_arch_reset_vcpu(X86CPU
*cpu
)
732 CPUX86State
*env
= &cpu
->env
;
734 env
->exception_injected
= -1;
735 env
->interrupt_injected
= -1;
737 if (kvm_irqchip_in_kernel()) {
738 env
->mp_state
= cpu_is_bsp(cpu
) ? KVM_MP_STATE_RUNNABLE
:
739 KVM_MP_STATE_UNINITIALIZED
;
741 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
745 void kvm_arch_do_init_vcpu(X86CPU
*cpu
)
747 CPUX86State
*env
= &cpu
->env
;
749 /* APs get directly into wait-for-SIPI state. */
750 if (env
->mp_state
== KVM_MP_STATE_UNINITIALIZED
) {
751 env
->mp_state
= KVM_MP_STATE_INIT_RECEIVED
;
755 static int kvm_get_supported_msrs(KVMState
*s
)
757 static int kvm_supported_msrs
;
761 if (kvm_supported_msrs
== 0) {
762 struct kvm_msr_list msr_list
, *kvm_msr_list
;
764 kvm_supported_msrs
= -1;
766 /* Obtain MSR list from KVM. These are the MSRs that we must
769 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, &msr_list
);
770 if (ret
< 0 && ret
!= -E2BIG
) {
773 /* Old kernel modules had a bug and could write beyond the provided
774 memory. Allocate at least a safe amount of 1K. */
775 kvm_msr_list
= g_malloc0(MAX(1024, sizeof(msr_list
) +
777 sizeof(msr_list
.indices
[0])));
779 kvm_msr_list
->nmsrs
= msr_list
.nmsrs
;
780 ret
= kvm_ioctl(s
, KVM_GET_MSR_INDEX_LIST
, kvm_msr_list
);
784 for (i
= 0; i
< kvm_msr_list
->nmsrs
; i
++) {
785 if (kvm_msr_list
->indices
[i
] == MSR_STAR
) {
789 if (kvm_msr_list
->indices
[i
] == MSR_VM_HSAVE_PA
) {
790 has_msr_hsave_pa
= true;
793 if (kvm_msr_list
->indices
[i
] == MSR_TSC_ADJUST
) {
794 has_msr_tsc_adjust
= true;
797 if (kvm_msr_list
->indices
[i
] == MSR_IA32_TSCDEADLINE
) {
798 has_msr_tsc_deadline
= true;
801 if (kvm_msr_list
->indices
[i
] == MSR_IA32_MISC_ENABLE
) {
802 has_msr_misc_enable
= true;
805 if (kvm_msr_list
->indices
[i
] == MSR_IA32_BNDCFGS
) {
806 has_msr_bndcfgs
= true;
812 g_free(kvm_msr_list
);
818 int kvm_arch_init(KVMState
*s
)
820 uint64_t identity_base
= 0xfffbc000;
823 struct utsname utsname
;
825 ret
= kvm_get_supported_msrs(s
);
831 lm_capable_kernel
= strcmp(utsname
.machine
, "x86_64") == 0;
834 * On older Intel CPUs, KVM uses vm86 mode to emulate 16-bit code directly.
835 * In order to use vm86 mode, an EPT identity map and a TSS are needed.
836 * Since these must be part of guest physical memory, we need to allocate
837 * them, both by setting their start addresses in the kernel and by
838 * creating a corresponding e820 entry. We need 4 pages before the BIOS.
840 * Older KVM versions may not support setting the identity map base. In
841 * that case we need to stick with the default, i.e. a 256K maximum BIOS
844 if (kvm_check_extension(s
, KVM_CAP_SET_IDENTITY_MAP_ADDR
)) {
845 /* Allows up to 16M BIOSes. */
846 identity_base
= 0xfeffc000;
848 ret
= kvm_vm_ioctl(s
, KVM_SET_IDENTITY_MAP_ADDR
, &identity_base
);
854 /* Set TSS base one page after EPT identity map. */
855 ret
= kvm_vm_ioctl(s
, KVM_SET_TSS_ADDR
, identity_base
+ 0x1000);
860 /* Tell fw_cfg to notify the BIOS to reserve the range. */
861 ret
= e820_add_entry(identity_base
, 0x4000, E820_RESERVED
);
863 fprintf(stderr
, "e820_add_entry() table is full\n");
866 qemu_register_reset(kvm_unpoison_all
, NULL
);
868 shadow_mem
= qemu_opt_get_size(qemu_get_machine_opts(),
869 "kvm_shadow_mem", -1);
870 if (shadow_mem
!= -1) {
872 ret
= kvm_vm_ioctl(s
, KVM_SET_NR_MMU_PAGES
, shadow_mem
);
880 static void set_v8086_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
882 lhs
->selector
= rhs
->selector
;
883 lhs
->base
= rhs
->base
;
884 lhs
->limit
= rhs
->limit
;
896 static void set_seg(struct kvm_segment
*lhs
, const SegmentCache
*rhs
)
898 unsigned flags
= rhs
->flags
;
899 lhs
->selector
= rhs
->selector
;
900 lhs
->base
= rhs
->base
;
901 lhs
->limit
= rhs
->limit
;
902 lhs
->type
= (flags
>> DESC_TYPE_SHIFT
) & 15;
903 lhs
->present
= (flags
& DESC_P_MASK
) != 0;
904 lhs
->dpl
= (flags
>> DESC_DPL_SHIFT
) & 3;
905 lhs
->db
= (flags
>> DESC_B_SHIFT
) & 1;
906 lhs
->s
= (flags
& DESC_S_MASK
) != 0;
907 lhs
->l
= (flags
>> DESC_L_SHIFT
) & 1;
908 lhs
->g
= (flags
& DESC_G_MASK
) != 0;
909 lhs
->avl
= (flags
& DESC_AVL_MASK
) != 0;
914 static void get_seg(SegmentCache
*lhs
, const struct kvm_segment
*rhs
)
916 lhs
->selector
= rhs
->selector
;
917 lhs
->base
= rhs
->base
;
918 lhs
->limit
= rhs
->limit
;
919 lhs
->flags
= (rhs
->type
<< DESC_TYPE_SHIFT
) |
920 (rhs
->present
* DESC_P_MASK
) |
921 (rhs
->dpl
<< DESC_DPL_SHIFT
) |
922 (rhs
->db
<< DESC_B_SHIFT
) |
923 (rhs
->s
* DESC_S_MASK
) |
924 (rhs
->l
<< DESC_L_SHIFT
) |
925 (rhs
->g
* DESC_G_MASK
) |
926 (rhs
->avl
* DESC_AVL_MASK
);
929 static void kvm_getput_reg(__u64
*kvm_reg
, target_ulong
*qemu_reg
, int set
)
932 *kvm_reg
= *qemu_reg
;
934 *qemu_reg
= *kvm_reg
;
938 static int kvm_getput_regs(X86CPU
*cpu
, int set
)
940 CPUX86State
*env
= &cpu
->env
;
941 struct kvm_regs regs
;
945 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_REGS
, ®s
);
951 kvm_getput_reg(®s
.rax
, &env
->regs
[R_EAX
], set
);
952 kvm_getput_reg(®s
.rbx
, &env
->regs
[R_EBX
], set
);
953 kvm_getput_reg(®s
.rcx
, &env
->regs
[R_ECX
], set
);
954 kvm_getput_reg(®s
.rdx
, &env
->regs
[R_EDX
], set
);
955 kvm_getput_reg(®s
.rsi
, &env
->regs
[R_ESI
], set
);
956 kvm_getput_reg(®s
.rdi
, &env
->regs
[R_EDI
], set
);
957 kvm_getput_reg(®s
.rsp
, &env
->regs
[R_ESP
], set
);
958 kvm_getput_reg(®s
.rbp
, &env
->regs
[R_EBP
], set
);
960 kvm_getput_reg(®s
.r8
, &env
->regs
[8], set
);
961 kvm_getput_reg(®s
.r9
, &env
->regs
[9], set
);
962 kvm_getput_reg(®s
.r10
, &env
->regs
[10], set
);
963 kvm_getput_reg(®s
.r11
, &env
->regs
[11], set
);
964 kvm_getput_reg(®s
.r12
, &env
->regs
[12], set
);
965 kvm_getput_reg(®s
.r13
, &env
->regs
[13], set
);
966 kvm_getput_reg(®s
.r14
, &env
->regs
[14], set
);
967 kvm_getput_reg(®s
.r15
, &env
->regs
[15], set
);
970 kvm_getput_reg(®s
.rflags
, &env
->eflags
, set
);
971 kvm_getput_reg(®s
.rip
, &env
->eip
, set
);
974 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_REGS
, ®s
);
980 static int kvm_put_fpu(X86CPU
*cpu
)
982 CPUX86State
*env
= &cpu
->env
;
986 memset(&fpu
, 0, sizeof fpu
);
987 fpu
.fsw
= env
->fpus
& ~(7 << 11);
988 fpu
.fsw
|= (env
->fpstt
& 7) << 11;
990 fpu
.last_opcode
= env
->fpop
;
991 fpu
.last_ip
= env
->fpip
;
992 fpu
.last_dp
= env
->fpdp
;
993 for (i
= 0; i
< 8; ++i
) {
994 fpu
.ftwx
|= (!env
->fptags
[i
]) << i
;
996 memcpy(fpu
.fpr
, env
->fpregs
, sizeof env
->fpregs
);
997 memcpy(fpu
.xmm
, env
->xmm_regs
, sizeof env
->xmm_regs
);
998 fpu
.mxcsr
= env
->mxcsr
;
1000 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_FPU
, &fpu
);
1003 #define XSAVE_FCW_FSW 0
1004 #define XSAVE_FTW_FOP 1
1005 #define XSAVE_CWD_RIP 2
1006 #define XSAVE_CWD_RDP 4
1007 #define XSAVE_MXCSR 6
1008 #define XSAVE_ST_SPACE 8
1009 #define XSAVE_XMM_SPACE 40
1010 #define XSAVE_XSTATE_BV 128
1011 #define XSAVE_YMMH_SPACE 144
1012 #define XSAVE_BNDREGS 240
1013 #define XSAVE_BNDCSR 256
1015 static int kvm_put_xsave(X86CPU
*cpu
)
1017 CPUX86State
*env
= &cpu
->env
;
1018 struct kvm_xsave
* xsave
= env
->kvm_xsave_buf
;
1019 uint16_t cwd
, swd
, twd
;
1022 if (!kvm_has_xsave()) {
1023 return kvm_put_fpu(cpu
);
1026 memset(xsave
, 0, sizeof(struct kvm_xsave
));
1028 swd
= env
->fpus
& ~(7 << 11);
1029 swd
|= (env
->fpstt
& 7) << 11;
1031 for (i
= 0; i
< 8; ++i
) {
1032 twd
|= (!env
->fptags
[i
]) << i
;
1034 xsave
->region
[XSAVE_FCW_FSW
] = (uint32_t)(swd
<< 16) + cwd
;
1035 xsave
->region
[XSAVE_FTW_FOP
] = (uint32_t)(env
->fpop
<< 16) + twd
;
1036 memcpy(&xsave
->region
[XSAVE_CWD_RIP
], &env
->fpip
, sizeof(env
->fpip
));
1037 memcpy(&xsave
->region
[XSAVE_CWD_RDP
], &env
->fpdp
, sizeof(env
->fpdp
));
1038 memcpy(&xsave
->region
[XSAVE_ST_SPACE
], env
->fpregs
,
1039 sizeof env
->fpregs
);
1040 memcpy(&xsave
->region
[XSAVE_XMM_SPACE
], env
->xmm_regs
,
1041 sizeof env
->xmm_regs
);
1042 xsave
->region
[XSAVE_MXCSR
] = env
->mxcsr
;
1043 *(uint64_t *)&xsave
->region
[XSAVE_XSTATE_BV
] = env
->xstate_bv
;
1044 memcpy(&xsave
->region
[XSAVE_YMMH_SPACE
], env
->ymmh_regs
,
1045 sizeof env
->ymmh_regs
);
1046 memcpy(&xsave
->region
[XSAVE_BNDREGS
], env
->bnd_regs
,
1047 sizeof env
->bnd_regs
);
1048 memcpy(&xsave
->region
[XSAVE_BNDCSR
], &env
->bndcs_regs
,
1049 sizeof(env
->bndcs_regs
));
1050 r
= kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_XSAVE
, xsave
);
1054 static int kvm_put_xcrs(X86CPU
*cpu
)
1056 CPUX86State
*env
= &cpu
->env
;
1057 struct kvm_xcrs xcrs
;
1059 if (!kvm_has_xcrs()) {
1065 xcrs
.xcrs
[0].xcr
= 0;
1066 xcrs
.xcrs
[0].value
= env
->xcr0
;
1067 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_XCRS
, &xcrs
);
1070 static int kvm_put_sregs(X86CPU
*cpu
)
1072 CPUX86State
*env
= &cpu
->env
;
1073 struct kvm_sregs sregs
;
1075 memset(sregs
.interrupt_bitmap
, 0, sizeof(sregs
.interrupt_bitmap
));
1076 if (env
->interrupt_injected
>= 0) {
1077 sregs
.interrupt_bitmap
[env
->interrupt_injected
/ 64] |=
1078 (uint64_t)1 << (env
->interrupt_injected
% 64);
1081 if ((env
->eflags
& VM_MASK
)) {
1082 set_v8086_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
1083 set_v8086_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
1084 set_v8086_seg(&sregs
.es
, &env
->segs
[R_ES
]);
1085 set_v8086_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
1086 set_v8086_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
1087 set_v8086_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
1089 set_seg(&sregs
.cs
, &env
->segs
[R_CS
]);
1090 set_seg(&sregs
.ds
, &env
->segs
[R_DS
]);
1091 set_seg(&sregs
.es
, &env
->segs
[R_ES
]);
1092 set_seg(&sregs
.fs
, &env
->segs
[R_FS
]);
1093 set_seg(&sregs
.gs
, &env
->segs
[R_GS
]);
1094 set_seg(&sregs
.ss
, &env
->segs
[R_SS
]);
1097 set_seg(&sregs
.tr
, &env
->tr
);
1098 set_seg(&sregs
.ldt
, &env
->ldt
);
1100 sregs
.idt
.limit
= env
->idt
.limit
;
1101 sregs
.idt
.base
= env
->idt
.base
;
1102 memset(sregs
.idt
.padding
, 0, sizeof sregs
.idt
.padding
);
1103 sregs
.gdt
.limit
= env
->gdt
.limit
;
1104 sregs
.gdt
.base
= env
->gdt
.base
;
1105 memset(sregs
.gdt
.padding
, 0, sizeof sregs
.gdt
.padding
);
1107 sregs
.cr0
= env
->cr
[0];
1108 sregs
.cr2
= env
->cr
[2];
1109 sregs
.cr3
= env
->cr
[3];
1110 sregs
.cr4
= env
->cr
[4];
1112 sregs
.cr8
= cpu_get_apic_tpr(cpu
->apic_state
);
1113 sregs
.apic_base
= cpu_get_apic_base(cpu
->apic_state
);
1115 sregs
.efer
= env
->efer
;
1117 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_SREGS
, &sregs
);
1120 static void kvm_msr_entry_set(struct kvm_msr_entry
*entry
,
1121 uint32_t index
, uint64_t value
)
1123 entry
->index
= index
;
1124 entry
->data
= value
;
1127 static int kvm_put_tscdeadline_msr(X86CPU
*cpu
)
1129 CPUX86State
*env
= &cpu
->env
;
1131 struct kvm_msrs info
;
1132 struct kvm_msr_entry entries
[1];
1134 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
1136 if (!has_msr_tsc_deadline
) {
1140 kvm_msr_entry_set(&msrs
[0], MSR_IA32_TSCDEADLINE
, env
->tsc_deadline
);
1142 msr_data
.info
.nmsrs
= 1;
1144 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MSRS
, &msr_data
);
1148 * Provide a separate write service for the feature control MSR in order to
1149 * kick the VCPU out of VMXON or even guest mode on reset. This has to be done
1150 * before writing any other state because forcibly leaving nested mode
1151 * invalidates the VCPU state.
1153 static int kvm_put_msr_feature_control(X86CPU
*cpu
)
1156 struct kvm_msrs info
;
1157 struct kvm_msr_entry entry
;
1160 kvm_msr_entry_set(&msr_data
.entry
, MSR_IA32_FEATURE_CONTROL
,
1161 cpu
->env
.msr_ia32_feature_control
);
1162 msr_data
.info
.nmsrs
= 1;
1163 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MSRS
, &msr_data
);
1166 static int kvm_put_msrs(X86CPU
*cpu
, int level
)
1168 CPUX86State
*env
= &cpu
->env
;
1170 struct kvm_msrs info
;
1171 struct kvm_msr_entry entries
[100];
1173 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
1176 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_CS
, env
->sysenter_cs
);
1177 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_ESP
, env
->sysenter_esp
);
1178 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_SYSENTER_EIP
, env
->sysenter_eip
);
1179 kvm_msr_entry_set(&msrs
[n
++], MSR_PAT
, env
->pat
);
1181 kvm_msr_entry_set(&msrs
[n
++], MSR_STAR
, env
->star
);
1183 if (has_msr_hsave_pa
) {
1184 kvm_msr_entry_set(&msrs
[n
++], MSR_VM_HSAVE_PA
, env
->vm_hsave
);
1186 if (has_msr_tsc_adjust
) {
1187 kvm_msr_entry_set(&msrs
[n
++], MSR_TSC_ADJUST
, env
->tsc_adjust
);
1189 if (has_msr_misc_enable
) {
1190 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_MISC_ENABLE
,
1191 env
->msr_ia32_misc_enable
);
1193 if (has_msr_bndcfgs
) {
1194 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_BNDCFGS
, env
->msr_bndcfgs
);
1196 #ifdef TARGET_X86_64
1197 if (lm_capable_kernel
) {
1198 kvm_msr_entry_set(&msrs
[n
++], MSR_CSTAR
, env
->cstar
);
1199 kvm_msr_entry_set(&msrs
[n
++], MSR_KERNELGSBASE
, env
->kernelgsbase
);
1200 kvm_msr_entry_set(&msrs
[n
++], MSR_FMASK
, env
->fmask
);
1201 kvm_msr_entry_set(&msrs
[n
++], MSR_LSTAR
, env
->lstar
);
1205 * The following MSRs have side effects on the guest or are too heavy
1206 * for normal writeback. Limit them to reset or full state updates.
1208 if (level
>= KVM_PUT_RESET_STATE
) {
1209 kvm_msr_entry_set(&msrs
[n
++], MSR_IA32_TSC
, env
->tsc
);
1210 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_SYSTEM_TIME
,
1211 env
->system_time_msr
);
1212 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_WALL_CLOCK
, env
->wall_clock_msr
);
1213 if (has_msr_async_pf_en
) {
1214 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_ASYNC_PF_EN
,
1215 env
->async_pf_en_msr
);
1217 if (has_msr_pv_eoi_en
) {
1218 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_PV_EOI_EN
,
1219 env
->pv_eoi_en_msr
);
1221 if (has_msr_kvm_steal_time
) {
1222 kvm_msr_entry_set(&msrs
[n
++], MSR_KVM_STEAL_TIME
,
1223 env
->steal_time_msr
);
1225 if (has_msr_architectural_pmu
) {
1226 /* Stop the counter. */
1227 kvm_msr_entry_set(&msrs
[n
++], MSR_CORE_PERF_FIXED_CTR_CTRL
, 0);
1228 kvm_msr_entry_set(&msrs
[n
++], MSR_CORE_PERF_GLOBAL_CTRL
, 0);
1230 /* Set the counter values. */
1231 for (i
= 0; i
< MAX_FIXED_COUNTERS
; i
++) {
1232 kvm_msr_entry_set(&msrs
[n
++], MSR_CORE_PERF_FIXED_CTR0
+ i
,
1233 env
->msr_fixed_counters
[i
]);
1235 for (i
= 0; i
< num_architectural_pmu_counters
; i
++) {
1236 kvm_msr_entry_set(&msrs
[n
++], MSR_P6_PERFCTR0
+ i
,
1237 env
->msr_gp_counters
[i
]);
1238 kvm_msr_entry_set(&msrs
[n
++], MSR_P6_EVNTSEL0
+ i
,
1239 env
->msr_gp_evtsel
[i
]);
1241 kvm_msr_entry_set(&msrs
[n
++], MSR_CORE_PERF_GLOBAL_STATUS
,
1242 env
->msr_global_status
);
1243 kvm_msr_entry_set(&msrs
[n
++], MSR_CORE_PERF_GLOBAL_OVF_CTRL
,
1244 env
->msr_global_ovf_ctrl
);
1246 /* Now start the PMU. */
1247 kvm_msr_entry_set(&msrs
[n
++], MSR_CORE_PERF_FIXED_CTR_CTRL
,
1248 env
->msr_fixed_ctr_ctrl
);
1249 kvm_msr_entry_set(&msrs
[n
++], MSR_CORE_PERF_GLOBAL_CTRL
,
1250 env
->msr_global_ctrl
);
1252 if (has_msr_hv_hypercall
) {
1253 kvm_msr_entry_set(&msrs
[n
++], HV_X64_MSR_GUEST_OS_ID
,
1254 env
->msr_hv_guest_os_id
);
1255 kvm_msr_entry_set(&msrs
[n
++], HV_X64_MSR_HYPERCALL
,
1256 env
->msr_hv_hypercall
);
1258 if (has_msr_hv_vapic
) {
1259 kvm_msr_entry_set(&msrs
[n
++], HV_X64_MSR_APIC_ASSIST_PAGE
,
1262 if (has_msr_hv_tsc
) {
1263 kvm_msr_entry_set(&msrs
[n
++], HV_X64_MSR_REFERENCE_TSC
,
1267 /* Note: MSR_IA32_FEATURE_CONTROL is written separately, see
1268 * kvm_put_msr_feature_control. */
1273 kvm_msr_entry_set(&msrs
[n
++], MSR_MCG_STATUS
, env
->mcg_status
);
1274 kvm_msr_entry_set(&msrs
[n
++], MSR_MCG_CTL
, env
->mcg_ctl
);
1275 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
1276 kvm_msr_entry_set(&msrs
[n
++], MSR_MC0_CTL
+ i
, env
->mce_banks
[i
]);
1280 msr_data
.info
.nmsrs
= n
;
1282 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MSRS
, &msr_data
);
1287 static int kvm_get_fpu(X86CPU
*cpu
)
1289 CPUX86State
*env
= &cpu
->env
;
1293 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_FPU
, &fpu
);
1298 env
->fpstt
= (fpu
.fsw
>> 11) & 7;
1299 env
->fpus
= fpu
.fsw
;
1300 env
->fpuc
= fpu
.fcw
;
1301 env
->fpop
= fpu
.last_opcode
;
1302 env
->fpip
= fpu
.last_ip
;
1303 env
->fpdp
= fpu
.last_dp
;
1304 for (i
= 0; i
< 8; ++i
) {
1305 env
->fptags
[i
] = !((fpu
.ftwx
>> i
) & 1);
1307 memcpy(env
->fpregs
, fpu
.fpr
, sizeof env
->fpregs
);
1308 memcpy(env
->xmm_regs
, fpu
.xmm
, sizeof env
->xmm_regs
);
1309 env
->mxcsr
= fpu
.mxcsr
;
1314 static int kvm_get_xsave(X86CPU
*cpu
)
1316 CPUX86State
*env
= &cpu
->env
;
1317 struct kvm_xsave
* xsave
= env
->kvm_xsave_buf
;
1319 uint16_t cwd
, swd
, twd
;
1321 if (!kvm_has_xsave()) {
1322 return kvm_get_fpu(cpu
);
1325 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_XSAVE
, xsave
);
1330 cwd
= (uint16_t)xsave
->region
[XSAVE_FCW_FSW
];
1331 swd
= (uint16_t)(xsave
->region
[XSAVE_FCW_FSW
] >> 16);
1332 twd
= (uint16_t)xsave
->region
[XSAVE_FTW_FOP
];
1333 env
->fpop
= (uint16_t)(xsave
->region
[XSAVE_FTW_FOP
] >> 16);
1334 env
->fpstt
= (swd
>> 11) & 7;
1337 for (i
= 0; i
< 8; ++i
) {
1338 env
->fptags
[i
] = !((twd
>> i
) & 1);
1340 memcpy(&env
->fpip
, &xsave
->region
[XSAVE_CWD_RIP
], sizeof(env
->fpip
));
1341 memcpy(&env
->fpdp
, &xsave
->region
[XSAVE_CWD_RDP
], sizeof(env
->fpdp
));
1342 env
->mxcsr
= xsave
->region
[XSAVE_MXCSR
];
1343 memcpy(env
->fpregs
, &xsave
->region
[XSAVE_ST_SPACE
],
1344 sizeof env
->fpregs
);
1345 memcpy(env
->xmm_regs
, &xsave
->region
[XSAVE_XMM_SPACE
],
1346 sizeof env
->xmm_regs
);
1347 env
->xstate_bv
= *(uint64_t *)&xsave
->region
[XSAVE_XSTATE_BV
];
1348 memcpy(env
->ymmh_regs
, &xsave
->region
[XSAVE_YMMH_SPACE
],
1349 sizeof env
->ymmh_regs
);
1350 memcpy(env
->bnd_regs
, &xsave
->region
[XSAVE_BNDREGS
],
1351 sizeof env
->bnd_regs
);
1352 memcpy(&env
->bndcs_regs
, &xsave
->region
[XSAVE_BNDCSR
],
1353 sizeof(env
->bndcs_regs
));
1357 static int kvm_get_xcrs(X86CPU
*cpu
)
1359 CPUX86State
*env
= &cpu
->env
;
1361 struct kvm_xcrs xcrs
;
1363 if (!kvm_has_xcrs()) {
1367 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_XCRS
, &xcrs
);
1372 for (i
= 0; i
< xcrs
.nr_xcrs
; i
++) {
1373 /* Only support xcr0 now */
1374 if (xcrs
.xcrs
[i
].xcr
== 0) {
1375 env
->xcr0
= xcrs
.xcrs
[i
].value
;
1382 static int kvm_get_sregs(X86CPU
*cpu
)
1384 CPUX86State
*env
= &cpu
->env
;
1385 struct kvm_sregs sregs
;
1389 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_SREGS
, &sregs
);
1394 /* There can only be one pending IRQ set in the bitmap at a time, so try
1395 to find it and save its number instead (-1 for none). */
1396 env
->interrupt_injected
= -1;
1397 for (i
= 0; i
< ARRAY_SIZE(sregs
.interrupt_bitmap
); i
++) {
1398 if (sregs
.interrupt_bitmap
[i
]) {
1399 bit
= ctz64(sregs
.interrupt_bitmap
[i
]);
1400 env
->interrupt_injected
= i
* 64 + bit
;
1405 get_seg(&env
->segs
[R_CS
], &sregs
.cs
);
1406 get_seg(&env
->segs
[R_DS
], &sregs
.ds
);
1407 get_seg(&env
->segs
[R_ES
], &sregs
.es
);
1408 get_seg(&env
->segs
[R_FS
], &sregs
.fs
);
1409 get_seg(&env
->segs
[R_GS
], &sregs
.gs
);
1410 get_seg(&env
->segs
[R_SS
], &sregs
.ss
);
1412 get_seg(&env
->tr
, &sregs
.tr
);
1413 get_seg(&env
->ldt
, &sregs
.ldt
);
1415 env
->idt
.limit
= sregs
.idt
.limit
;
1416 env
->idt
.base
= sregs
.idt
.base
;
1417 env
->gdt
.limit
= sregs
.gdt
.limit
;
1418 env
->gdt
.base
= sregs
.gdt
.base
;
1420 env
->cr
[0] = sregs
.cr0
;
1421 env
->cr
[2] = sregs
.cr2
;
1422 env
->cr
[3] = sregs
.cr3
;
1423 env
->cr
[4] = sregs
.cr4
;
1425 env
->efer
= sregs
.efer
;
1427 /* changes to apic base and cr8/tpr are read back via kvm_arch_post_run */
1429 #define HFLAG_COPY_MASK \
1430 ~( HF_CPL_MASK | HF_PE_MASK | HF_MP_MASK | HF_EM_MASK | \
1431 HF_TS_MASK | HF_TF_MASK | HF_VM_MASK | HF_IOPL_MASK | \
1432 HF_OSFXSR_MASK | HF_LMA_MASK | HF_CS32_MASK | \
1433 HF_SS32_MASK | HF_CS64_MASK | HF_ADDSEG_MASK)
1435 hflags
= (env
->segs
[R_SS
].flags
>> DESC_DPL_SHIFT
) & HF_CPL_MASK
;
1436 hflags
|= (env
->cr
[0] & CR0_PE_MASK
) << (HF_PE_SHIFT
- CR0_PE_SHIFT
);
1437 hflags
|= (env
->cr
[0] << (HF_MP_SHIFT
- CR0_MP_SHIFT
)) &
1438 (HF_MP_MASK
| HF_EM_MASK
| HF_TS_MASK
);
1439 hflags
|= (env
->eflags
& (HF_TF_MASK
| HF_VM_MASK
| HF_IOPL_MASK
));
1440 hflags
|= (env
->cr
[4] & CR4_OSFXSR_MASK
) <<
1441 (HF_OSFXSR_SHIFT
- CR4_OSFXSR_SHIFT
);
1443 if (env
->efer
& MSR_EFER_LMA
) {
1444 hflags
|= HF_LMA_MASK
;
1447 if ((hflags
& HF_LMA_MASK
) && (env
->segs
[R_CS
].flags
& DESC_L_MASK
)) {
1448 hflags
|= HF_CS32_MASK
| HF_SS32_MASK
| HF_CS64_MASK
;
1450 hflags
|= (env
->segs
[R_CS
].flags
& DESC_B_MASK
) >>
1451 (DESC_B_SHIFT
- HF_CS32_SHIFT
);
1452 hflags
|= (env
->segs
[R_SS
].flags
& DESC_B_MASK
) >>
1453 (DESC_B_SHIFT
- HF_SS32_SHIFT
);
1454 if (!(env
->cr
[0] & CR0_PE_MASK
) || (env
->eflags
& VM_MASK
) ||
1455 !(hflags
& HF_CS32_MASK
)) {
1456 hflags
|= HF_ADDSEG_MASK
;
1458 hflags
|= ((env
->segs
[R_DS
].base
| env
->segs
[R_ES
].base
|
1459 env
->segs
[R_SS
].base
) != 0) << HF_ADDSEG_SHIFT
;
1462 env
->hflags
= (env
->hflags
& HFLAG_COPY_MASK
) | hflags
;
1467 static int kvm_get_msrs(X86CPU
*cpu
)
1469 CPUX86State
*env
= &cpu
->env
;
1471 struct kvm_msrs info
;
1472 struct kvm_msr_entry entries
[100];
1474 struct kvm_msr_entry
*msrs
= msr_data
.entries
;
1478 msrs
[n
++].index
= MSR_IA32_SYSENTER_CS
;
1479 msrs
[n
++].index
= MSR_IA32_SYSENTER_ESP
;
1480 msrs
[n
++].index
= MSR_IA32_SYSENTER_EIP
;
1481 msrs
[n
++].index
= MSR_PAT
;
1483 msrs
[n
++].index
= MSR_STAR
;
1485 if (has_msr_hsave_pa
) {
1486 msrs
[n
++].index
= MSR_VM_HSAVE_PA
;
1488 if (has_msr_tsc_adjust
) {
1489 msrs
[n
++].index
= MSR_TSC_ADJUST
;
1491 if (has_msr_tsc_deadline
) {
1492 msrs
[n
++].index
= MSR_IA32_TSCDEADLINE
;
1494 if (has_msr_misc_enable
) {
1495 msrs
[n
++].index
= MSR_IA32_MISC_ENABLE
;
1497 if (has_msr_feature_control
) {
1498 msrs
[n
++].index
= MSR_IA32_FEATURE_CONTROL
;
1500 if (has_msr_bndcfgs
) {
1501 msrs
[n
++].index
= MSR_IA32_BNDCFGS
;
1504 if (!env
->tsc_valid
) {
1505 msrs
[n
++].index
= MSR_IA32_TSC
;
1506 env
->tsc_valid
= !runstate_is_running();
1509 #ifdef TARGET_X86_64
1510 if (lm_capable_kernel
) {
1511 msrs
[n
++].index
= MSR_CSTAR
;
1512 msrs
[n
++].index
= MSR_KERNELGSBASE
;
1513 msrs
[n
++].index
= MSR_FMASK
;
1514 msrs
[n
++].index
= MSR_LSTAR
;
1517 msrs
[n
++].index
= MSR_KVM_SYSTEM_TIME
;
1518 msrs
[n
++].index
= MSR_KVM_WALL_CLOCK
;
1519 if (has_msr_async_pf_en
) {
1520 msrs
[n
++].index
= MSR_KVM_ASYNC_PF_EN
;
1522 if (has_msr_pv_eoi_en
) {
1523 msrs
[n
++].index
= MSR_KVM_PV_EOI_EN
;
1525 if (has_msr_kvm_steal_time
) {
1526 msrs
[n
++].index
= MSR_KVM_STEAL_TIME
;
1528 if (has_msr_architectural_pmu
) {
1529 msrs
[n
++].index
= MSR_CORE_PERF_FIXED_CTR_CTRL
;
1530 msrs
[n
++].index
= MSR_CORE_PERF_GLOBAL_CTRL
;
1531 msrs
[n
++].index
= MSR_CORE_PERF_GLOBAL_STATUS
;
1532 msrs
[n
++].index
= MSR_CORE_PERF_GLOBAL_OVF_CTRL
;
1533 for (i
= 0; i
< MAX_FIXED_COUNTERS
; i
++) {
1534 msrs
[n
++].index
= MSR_CORE_PERF_FIXED_CTR0
+ i
;
1536 for (i
= 0; i
< num_architectural_pmu_counters
; i
++) {
1537 msrs
[n
++].index
= MSR_P6_PERFCTR0
+ i
;
1538 msrs
[n
++].index
= MSR_P6_EVNTSEL0
+ i
;
1543 msrs
[n
++].index
= MSR_MCG_STATUS
;
1544 msrs
[n
++].index
= MSR_MCG_CTL
;
1545 for (i
= 0; i
< (env
->mcg_cap
& 0xff) * 4; i
++) {
1546 msrs
[n
++].index
= MSR_MC0_CTL
+ i
;
1550 if (has_msr_hv_hypercall
) {
1551 msrs
[n
++].index
= HV_X64_MSR_HYPERCALL
;
1552 msrs
[n
++].index
= HV_X64_MSR_GUEST_OS_ID
;
1554 if (has_msr_hv_vapic
) {
1555 msrs
[n
++].index
= HV_X64_MSR_APIC_ASSIST_PAGE
;
1557 if (has_msr_hv_tsc
) {
1558 msrs
[n
++].index
= HV_X64_MSR_REFERENCE_TSC
;
1561 msr_data
.info
.nmsrs
= n
;
1562 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_MSRS
, &msr_data
);
1567 for (i
= 0; i
< ret
; i
++) {
1568 uint32_t index
= msrs
[i
].index
;
1570 case MSR_IA32_SYSENTER_CS
:
1571 env
->sysenter_cs
= msrs
[i
].data
;
1573 case MSR_IA32_SYSENTER_ESP
:
1574 env
->sysenter_esp
= msrs
[i
].data
;
1576 case MSR_IA32_SYSENTER_EIP
:
1577 env
->sysenter_eip
= msrs
[i
].data
;
1580 env
->pat
= msrs
[i
].data
;
1583 env
->star
= msrs
[i
].data
;
1585 #ifdef TARGET_X86_64
1587 env
->cstar
= msrs
[i
].data
;
1589 case MSR_KERNELGSBASE
:
1590 env
->kernelgsbase
= msrs
[i
].data
;
1593 env
->fmask
= msrs
[i
].data
;
1596 env
->lstar
= msrs
[i
].data
;
1600 env
->tsc
= msrs
[i
].data
;
1602 case MSR_TSC_ADJUST
:
1603 env
->tsc_adjust
= msrs
[i
].data
;
1605 case MSR_IA32_TSCDEADLINE
:
1606 env
->tsc_deadline
= msrs
[i
].data
;
1608 case MSR_VM_HSAVE_PA
:
1609 env
->vm_hsave
= msrs
[i
].data
;
1611 case MSR_KVM_SYSTEM_TIME
:
1612 env
->system_time_msr
= msrs
[i
].data
;
1614 case MSR_KVM_WALL_CLOCK
:
1615 env
->wall_clock_msr
= msrs
[i
].data
;
1617 case MSR_MCG_STATUS
:
1618 env
->mcg_status
= msrs
[i
].data
;
1621 env
->mcg_ctl
= msrs
[i
].data
;
1623 case MSR_IA32_MISC_ENABLE
:
1624 env
->msr_ia32_misc_enable
= msrs
[i
].data
;
1626 case MSR_IA32_FEATURE_CONTROL
:
1627 env
->msr_ia32_feature_control
= msrs
[i
].data
;
1629 case MSR_IA32_BNDCFGS
:
1630 env
->msr_bndcfgs
= msrs
[i
].data
;
1633 if (msrs
[i
].index
>= MSR_MC0_CTL
&&
1634 msrs
[i
].index
< MSR_MC0_CTL
+ (env
->mcg_cap
& 0xff) * 4) {
1635 env
->mce_banks
[msrs
[i
].index
- MSR_MC0_CTL
] = msrs
[i
].data
;
1638 case MSR_KVM_ASYNC_PF_EN
:
1639 env
->async_pf_en_msr
= msrs
[i
].data
;
1641 case MSR_KVM_PV_EOI_EN
:
1642 env
->pv_eoi_en_msr
= msrs
[i
].data
;
1644 case MSR_KVM_STEAL_TIME
:
1645 env
->steal_time_msr
= msrs
[i
].data
;
1647 case MSR_CORE_PERF_FIXED_CTR_CTRL
:
1648 env
->msr_fixed_ctr_ctrl
= msrs
[i
].data
;
1650 case MSR_CORE_PERF_GLOBAL_CTRL
:
1651 env
->msr_global_ctrl
= msrs
[i
].data
;
1653 case MSR_CORE_PERF_GLOBAL_STATUS
:
1654 env
->msr_global_status
= msrs
[i
].data
;
1656 case MSR_CORE_PERF_GLOBAL_OVF_CTRL
:
1657 env
->msr_global_ovf_ctrl
= msrs
[i
].data
;
1659 case MSR_CORE_PERF_FIXED_CTR0
... MSR_CORE_PERF_FIXED_CTR0
+ MAX_FIXED_COUNTERS
- 1:
1660 env
->msr_fixed_counters
[index
- MSR_CORE_PERF_FIXED_CTR0
] = msrs
[i
].data
;
1662 case MSR_P6_PERFCTR0
... MSR_P6_PERFCTR0
+ MAX_GP_COUNTERS
- 1:
1663 env
->msr_gp_counters
[index
- MSR_P6_PERFCTR0
] = msrs
[i
].data
;
1665 case MSR_P6_EVNTSEL0
... MSR_P6_EVNTSEL0
+ MAX_GP_COUNTERS
- 1:
1666 env
->msr_gp_evtsel
[index
- MSR_P6_EVNTSEL0
] = msrs
[i
].data
;
1668 case HV_X64_MSR_HYPERCALL
:
1669 env
->msr_hv_hypercall
= msrs
[i
].data
;
1671 case HV_X64_MSR_GUEST_OS_ID
:
1672 env
->msr_hv_guest_os_id
= msrs
[i
].data
;
1674 case HV_X64_MSR_APIC_ASSIST_PAGE
:
1675 env
->msr_hv_vapic
= msrs
[i
].data
;
1677 case HV_X64_MSR_REFERENCE_TSC
:
1678 env
->msr_hv_tsc
= msrs
[i
].data
;
1686 static int kvm_put_mp_state(X86CPU
*cpu
)
1688 struct kvm_mp_state mp_state
= { .mp_state
= cpu
->env
.mp_state
};
1690 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_MP_STATE
, &mp_state
);
1693 static int kvm_get_mp_state(X86CPU
*cpu
)
1695 CPUState
*cs
= CPU(cpu
);
1696 CPUX86State
*env
= &cpu
->env
;
1697 struct kvm_mp_state mp_state
;
1700 ret
= kvm_vcpu_ioctl(cs
, KVM_GET_MP_STATE
, &mp_state
);
1704 env
->mp_state
= mp_state
.mp_state
;
1705 if (kvm_irqchip_in_kernel()) {
1706 cs
->halted
= (mp_state
.mp_state
== KVM_MP_STATE_HALTED
);
1711 static int kvm_get_apic(X86CPU
*cpu
)
1713 DeviceState
*apic
= cpu
->apic_state
;
1714 struct kvm_lapic_state kapic
;
1717 if (apic
&& kvm_irqchip_in_kernel()) {
1718 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_LAPIC
, &kapic
);
1723 kvm_get_apic_state(apic
, &kapic
);
1728 static int kvm_put_apic(X86CPU
*cpu
)
1730 DeviceState
*apic
= cpu
->apic_state
;
1731 struct kvm_lapic_state kapic
;
1733 if (apic
&& kvm_irqchip_in_kernel()) {
1734 kvm_put_apic_state(apic
, &kapic
);
1736 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_LAPIC
, &kapic
);
1741 static int kvm_put_vcpu_events(X86CPU
*cpu
, int level
)
1743 CPUX86State
*env
= &cpu
->env
;
1744 struct kvm_vcpu_events events
;
1746 if (!kvm_has_vcpu_events()) {
1750 events
.exception
.injected
= (env
->exception_injected
>= 0);
1751 events
.exception
.nr
= env
->exception_injected
;
1752 events
.exception
.has_error_code
= env
->has_error_code
;
1753 events
.exception
.error_code
= env
->error_code
;
1754 events
.exception
.pad
= 0;
1756 events
.interrupt
.injected
= (env
->interrupt_injected
>= 0);
1757 events
.interrupt
.nr
= env
->interrupt_injected
;
1758 events
.interrupt
.soft
= env
->soft_interrupt
;
1760 events
.nmi
.injected
= env
->nmi_injected
;
1761 events
.nmi
.pending
= env
->nmi_pending
;
1762 events
.nmi
.masked
= !!(env
->hflags2
& HF2_NMI_MASK
);
1765 events
.sipi_vector
= env
->sipi_vector
;
1768 if (level
>= KVM_PUT_RESET_STATE
) {
1770 KVM_VCPUEVENT_VALID_NMI_PENDING
| KVM_VCPUEVENT_VALID_SIPI_VECTOR
;
1773 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_VCPU_EVENTS
, &events
);
1776 static int kvm_get_vcpu_events(X86CPU
*cpu
)
1778 CPUX86State
*env
= &cpu
->env
;
1779 struct kvm_vcpu_events events
;
1782 if (!kvm_has_vcpu_events()) {
1786 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_VCPU_EVENTS
, &events
);
1790 env
->exception_injected
=
1791 events
.exception
.injected
? events
.exception
.nr
: -1;
1792 env
->has_error_code
= events
.exception
.has_error_code
;
1793 env
->error_code
= events
.exception
.error_code
;
1795 env
->interrupt_injected
=
1796 events
.interrupt
.injected
? events
.interrupt
.nr
: -1;
1797 env
->soft_interrupt
= events
.interrupt
.soft
;
1799 env
->nmi_injected
= events
.nmi
.injected
;
1800 env
->nmi_pending
= events
.nmi
.pending
;
1801 if (events
.nmi
.masked
) {
1802 env
->hflags2
|= HF2_NMI_MASK
;
1804 env
->hflags2
&= ~HF2_NMI_MASK
;
1807 env
->sipi_vector
= events
.sipi_vector
;
1812 static int kvm_guest_debug_workarounds(X86CPU
*cpu
)
1814 CPUState
*cs
= CPU(cpu
);
1815 CPUX86State
*env
= &cpu
->env
;
1817 unsigned long reinject_trap
= 0;
1819 if (!kvm_has_vcpu_events()) {
1820 if (env
->exception_injected
== 1) {
1821 reinject_trap
= KVM_GUESTDBG_INJECT_DB
;
1822 } else if (env
->exception_injected
== 3) {
1823 reinject_trap
= KVM_GUESTDBG_INJECT_BP
;
1825 env
->exception_injected
= -1;
1829 * Kernels before KVM_CAP_X86_ROBUST_SINGLESTEP overwrote flags.TF
1830 * injected via SET_GUEST_DEBUG while updating GP regs. Work around this
1831 * by updating the debug state once again if single-stepping is on.
1832 * Another reason to call kvm_update_guest_debug here is a pending debug
1833 * trap raise by the guest. On kernels without SET_VCPU_EVENTS we have to
1834 * reinject them via SET_GUEST_DEBUG.
1836 if (reinject_trap
||
1837 (!kvm_has_robust_singlestep() && cs
->singlestep_enabled
)) {
1838 ret
= kvm_update_guest_debug(cs
, reinject_trap
);
1843 static int kvm_put_debugregs(X86CPU
*cpu
)
1845 CPUX86State
*env
= &cpu
->env
;
1846 struct kvm_debugregs dbgregs
;
1849 if (!kvm_has_debugregs()) {
1853 for (i
= 0; i
< 4; i
++) {
1854 dbgregs
.db
[i
] = env
->dr
[i
];
1856 dbgregs
.dr6
= env
->dr
[6];
1857 dbgregs
.dr7
= env
->dr
[7];
1860 return kvm_vcpu_ioctl(CPU(cpu
), KVM_SET_DEBUGREGS
, &dbgregs
);
1863 static int kvm_get_debugregs(X86CPU
*cpu
)
1865 CPUX86State
*env
= &cpu
->env
;
1866 struct kvm_debugregs dbgregs
;
1869 if (!kvm_has_debugregs()) {
1873 ret
= kvm_vcpu_ioctl(CPU(cpu
), KVM_GET_DEBUGREGS
, &dbgregs
);
1877 for (i
= 0; i
< 4; i
++) {
1878 env
->dr
[i
] = dbgregs
.db
[i
];
1880 env
->dr
[4] = env
->dr
[6] = dbgregs
.dr6
;
1881 env
->dr
[5] = env
->dr
[7] = dbgregs
.dr7
;
1886 int kvm_arch_put_registers(CPUState
*cpu
, int level
)
1888 X86CPU
*x86_cpu
= X86_CPU(cpu
);
1891 assert(cpu_is_stopped(cpu
) || qemu_cpu_is_self(cpu
));
1893 if (level
>= KVM_PUT_RESET_STATE
&& has_msr_feature_control
) {
1894 ret
= kvm_put_msr_feature_control(x86_cpu
);
1900 ret
= kvm_getput_regs(x86_cpu
, 1);
1904 ret
= kvm_put_xsave(x86_cpu
);
1908 ret
= kvm_put_xcrs(x86_cpu
);
1912 ret
= kvm_put_sregs(x86_cpu
);
1916 /* must be before kvm_put_msrs */
1917 ret
= kvm_inject_mce_oldstyle(x86_cpu
);
1921 ret
= kvm_put_msrs(x86_cpu
, level
);
1925 if (level
>= KVM_PUT_RESET_STATE
) {
1926 ret
= kvm_put_mp_state(x86_cpu
);
1930 ret
= kvm_put_apic(x86_cpu
);
1936 ret
= kvm_put_tscdeadline_msr(x86_cpu
);
1941 ret
= kvm_put_vcpu_events(x86_cpu
, level
);
1945 ret
= kvm_put_debugregs(x86_cpu
);
1950 ret
= kvm_guest_debug_workarounds(x86_cpu
);
1957 int kvm_arch_get_registers(CPUState
*cs
)
1959 X86CPU
*cpu
= X86_CPU(cs
);
1962 assert(cpu_is_stopped(cs
) || qemu_cpu_is_self(cs
));
1964 ret
= kvm_getput_regs(cpu
, 0);
1968 ret
= kvm_get_xsave(cpu
);
1972 ret
= kvm_get_xcrs(cpu
);
1976 ret
= kvm_get_sregs(cpu
);
1980 ret
= kvm_get_msrs(cpu
);
1984 ret
= kvm_get_mp_state(cpu
);
1988 ret
= kvm_get_apic(cpu
);
1992 ret
= kvm_get_vcpu_events(cpu
);
1996 ret
= kvm_get_debugregs(cpu
);
2003 void kvm_arch_pre_run(CPUState
*cpu
, struct kvm_run
*run
)
2005 X86CPU
*x86_cpu
= X86_CPU(cpu
);
2006 CPUX86State
*env
= &x86_cpu
->env
;
2010 if (cpu
->interrupt_request
& CPU_INTERRUPT_NMI
) {
2011 cpu
->interrupt_request
&= ~CPU_INTERRUPT_NMI
;
2012 DPRINTF("injected NMI\n");
2013 ret
= kvm_vcpu_ioctl(cpu
, KVM_NMI
);
2015 fprintf(stderr
, "KVM: injection failed, NMI lost (%s)\n",
2020 /* Force the VCPU out of its inner loop to process any INIT requests
2021 * or (for userspace APIC, but it is cheap to combine the checks here)
2022 * pending TPR access reports.
2024 if (cpu
->interrupt_request
& (CPU_INTERRUPT_INIT
| CPU_INTERRUPT_TPR
)) {
2025 cpu
->exit_request
= 1;
2028 if (!kvm_irqchip_in_kernel()) {
2029 /* Try to inject an interrupt if the guest can accept it */
2030 if (run
->ready_for_interrupt_injection
&&
2031 (cpu
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
2032 (env
->eflags
& IF_MASK
)) {
2035 cpu
->interrupt_request
&= ~CPU_INTERRUPT_HARD
;
2036 irq
= cpu_get_pic_interrupt(env
);
2038 struct kvm_interrupt intr
;
2041 DPRINTF("injected interrupt %d\n", irq
);
2042 ret
= kvm_vcpu_ioctl(cpu
, KVM_INTERRUPT
, &intr
);
2045 "KVM: injection failed, interrupt lost (%s)\n",
2051 /* If we have an interrupt but the guest is not ready to receive an
2052 * interrupt, request an interrupt window exit. This will
2053 * cause a return to userspace as soon as the guest is ready to
2054 * receive interrupts. */
2055 if ((cpu
->interrupt_request
& CPU_INTERRUPT_HARD
)) {
2056 run
->request_interrupt_window
= 1;
2058 run
->request_interrupt_window
= 0;
2061 DPRINTF("setting tpr\n");
2062 run
->cr8
= cpu_get_apic_tpr(x86_cpu
->apic_state
);
2066 void kvm_arch_post_run(CPUState
*cpu
, struct kvm_run
*run
)
2068 X86CPU
*x86_cpu
= X86_CPU(cpu
);
2069 CPUX86State
*env
= &x86_cpu
->env
;
2072 env
->eflags
|= IF_MASK
;
2074 env
->eflags
&= ~IF_MASK
;
2076 cpu_set_apic_tpr(x86_cpu
->apic_state
, run
->cr8
);
2077 cpu_set_apic_base(x86_cpu
->apic_state
, run
->apic_base
);
2080 int kvm_arch_process_async_events(CPUState
*cs
)
2082 X86CPU
*cpu
= X86_CPU(cs
);
2083 CPUX86State
*env
= &cpu
->env
;
2085 if (cs
->interrupt_request
& CPU_INTERRUPT_MCE
) {
2086 /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */
2087 assert(env
->mcg_cap
);
2089 cs
->interrupt_request
&= ~CPU_INTERRUPT_MCE
;
2091 kvm_cpu_synchronize_state(cs
);
2093 if (env
->exception_injected
== EXCP08_DBLE
) {
2094 /* this means triple fault */
2095 qemu_system_reset_request();
2096 cs
->exit_request
= 1;
2099 env
->exception_injected
= EXCP12_MCHK
;
2100 env
->has_error_code
= 0;
2103 if (kvm_irqchip_in_kernel() && env
->mp_state
== KVM_MP_STATE_HALTED
) {
2104 env
->mp_state
= KVM_MP_STATE_RUNNABLE
;
2108 if (cs
->interrupt_request
& CPU_INTERRUPT_INIT
) {
2109 kvm_cpu_synchronize_state(cs
);
2113 if (kvm_irqchip_in_kernel()) {
2117 if (cs
->interrupt_request
& CPU_INTERRUPT_POLL
) {
2118 cs
->interrupt_request
&= ~CPU_INTERRUPT_POLL
;
2119 apic_poll_irq(cpu
->apic_state
);
2121 if (((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
2122 (env
->eflags
& IF_MASK
)) ||
2123 (cs
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
2126 if (cs
->interrupt_request
& CPU_INTERRUPT_SIPI
) {
2127 kvm_cpu_synchronize_state(cs
);
2130 if (cs
->interrupt_request
& CPU_INTERRUPT_TPR
) {
2131 cs
->interrupt_request
&= ~CPU_INTERRUPT_TPR
;
2132 kvm_cpu_synchronize_state(cs
);
2133 apic_handle_tpr_access_report(cpu
->apic_state
, env
->eip
,
2134 env
->tpr_access_type
);
2140 static int kvm_handle_halt(X86CPU
*cpu
)
2142 CPUState
*cs
= CPU(cpu
);
2143 CPUX86State
*env
= &cpu
->env
;
2145 if (!((cs
->interrupt_request
& CPU_INTERRUPT_HARD
) &&
2146 (env
->eflags
& IF_MASK
)) &&
2147 !(cs
->interrupt_request
& CPU_INTERRUPT_NMI
)) {
2155 static int kvm_handle_tpr_access(X86CPU
*cpu
)
2157 CPUState
*cs
= CPU(cpu
);
2158 struct kvm_run
*run
= cs
->kvm_run
;
2160 apic_handle_tpr_access_report(cpu
->apic_state
, run
->tpr_access
.rip
,
2161 run
->tpr_access
.is_write
? TPR_ACCESS_WRITE
2166 int kvm_arch_insert_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
2168 static const uint8_t int3
= 0xcc;
2170 if (cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 0) ||
2171 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&int3
, 1, 1)) {
2177 int kvm_arch_remove_sw_breakpoint(CPUState
*cs
, struct kvm_sw_breakpoint
*bp
)
2181 if (cpu_memory_rw_debug(cs
, bp
->pc
, &int3
, 1, 0) || int3
!= 0xcc ||
2182 cpu_memory_rw_debug(cs
, bp
->pc
, (uint8_t *)&bp
->saved_insn
, 1, 1)) {
2194 static int nb_hw_breakpoint
;
2196 static int find_hw_breakpoint(target_ulong addr
, int len
, int type
)
2200 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
2201 if (hw_breakpoint
[n
].addr
== addr
&& hw_breakpoint
[n
].type
== type
&&
2202 (hw_breakpoint
[n
].len
== len
|| len
== -1)) {
2209 int kvm_arch_insert_hw_breakpoint(target_ulong addr
,
2210 target_ulong len
, int type
)
2213 case GDB_BREAKPOINT_HW
:
2216 case GDB_WATCHPOINT_WRITE
:
2217 case GDB_WATCHPOINT_ACCESS
:
2224 if (addr
& (len
- 1)) {
2236 if (nb_hw_breakpoint
== 4) {
2239 if (find_hw_breakpoint(addr
, len
, type
) >= 0) {
2242 hw_breakpoint
[nb_hw_breakpoint
].addr
= addr
;
2243 hw_breakpoint
[nb_hw_breakpoint
].len
= len
;
2244 hw_breakpoint
[nb_hw_breakpoint
].type
= type
;
2250 int kvm_arch_remove_hw_breakpoint(target_ulong addr
,
2251 target_ulong len
, int type
)
2255 n
= find_hw_breakpoint(addr
, (type
== GDB_BREAKPOINT_HW
) ? 1 : len
, type
);
2260 hw_breakpoint
[n
] = hw_breakpoint
[nb_hw_breakpoint
];
2265 void kvm_arch_remove_all_hw_breakpoints(void)
2267 nb_hw_breakpoint
= 0;
2270 static CPUWatchpoint hw_watchpoint
;
2272 static int kvm_handle_debug(X86CPU
*cpu
,
2273 struct kvm_debug_exit_arch
*arch_info
)
2275 CPUState
*cs
= CPU(cpu
);
2276 CPUX86State
*env
= &cpu
->env
;
2280 if (arch_info
->exception
== 1) {
2281 if (arch_info
->dr6
& (1 << 14)) {
2282 if (cs
->singlestep_enabled
) {
2286 for (n
= 0; n
< 4; n
++) {
2287 if (arch_info
->dr6
& (1 << n
)) {
2288 switch ((arch_info
->dr7
>> (16 + n
*4)) & 0x3) {
2294 cs
->watchpoint_hit
= &hw_watchpoint
;
2295 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
2296 hw_watchpoint
.flags
= BP_MEM_WRITE
;
2300 cs
->watchpoint_hit
= &hw_watchpoint
;
2301 hw_watchpoint
.vaddr
= hw_breakpoint
[n
].addr
;
2302 hw_watchpoint
.flags
= BP_MEM_ACCESS
;
2308 } else if (kvm_find_sw_breakpoint(cs
, arch_info
->pc
)) {
2312 cpu_synchronize_state(cs
);
2313 assert(env
->exception_injected
== -1);
2316 env
->exception_injected
= arch_info
->exception
;
2317 env
->has_error_code
= 0;
2323 void kvm_arch_update_guest_debug(CPUState
*cpu
, struct kvm_guest_debug
*dbg
)
2325 const uint8_t type_code
[] = {
2326 [GDB_BREAKPOINT_HW
] = 0x0,
2327 [GDB_WATCHPOINT_WRITE
] = 0x1,
2328 [GDB_WATCHPOINT_ACCESS
] = 0x3
2330 const uint8_t len_code
[] = {
2331 [1] = 0x0, [2] = 0x1, [4] = 0x3, [8] = 0x2
2335 if (kvm_sw_breakpoints_active(cpu
)) {
2336 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_SW_BP
;
2338 if (nb_hw_breakpoint
> 0) {
2339 dbg
->control
|= KVM_GUESTDBG_ENABLE
| KVM_GUESTDBG_USE_HW_BP
;
2340 dbg
->arch
.debugreg
[7] = 0x0600;
2341 for (n
= 0; n
< nb_hw_breakpoint
; n
++) {
2342 dbg
->arch
.debugreg
[n
] = hw_breakpoint
[n
].addr
;
2343 dbg
->arch
.debugreg
[7] |= (2 << (n
* 2)) |
2344 (type_code
[hw_breakpoint
[n
].type
] << (16 + n
*4)) |
2345 ((uint32_t)len_code
[hw_breakpoint
[n
].len
] << (18 + n
*4));
2350 static bool host_supports_vmx(void)
2352 uint32_t ecx
, unused
;
2354 host_cpuid(1, 0, &unused
, &unused
, &ecx
, &unused
);
2355 return ecx
& CPUID_EXT_VMX
;
2358 #define VMX_INVALID_GUEST_STATE 0x80000021
2360 int kvm_arch_handle_exit(CPUState
*cs
, struct kvm_run
*run
)
2362 X86CPU
*cpu
= X86_CPU(cs
);
2366 switch (run
->exit_reason
) {
2368 DPRINTF("handle_hlt\n");
2369 ret
= kvm_handle_halt(cpu
);
2371 case KVM_EXIT_SET_TPR
:
2374 case KVM_EXIT_TPR_ACCESS
:
2375 ret
= kvm_handle_tpr_access(cpu
);
2377 case KVM_EXIT_FAIL_ENTRY
:
2378 code
= run
->fail_entry
.hardware_entry_failure_reason
;
2379 fprintf(stderr
, "KVM: entry failed, hardware error 0x%" PRIx64
"\n",
2381 if (host_supports_vmx() && code
== VMX_INVALID_GUEST_STATE
) {
2383 "\nIf you're running a guest on an Intel machine without "
2384 "unrestricted mode\n"
2385 "support, the failure can be most likely due to the guest "
2386 "entering an invalid\n"
2387 "state for Intel VT. For example, the guest maybe running "
2388 "in big real mode\n"
2389 "which is not supported on less recent Intel processors."
2394 case KVM_EXIT_EXCEPTION
:
2395 fprintf(stderr
, "KVM: exception %d exit (error code 0x%x)\n",
2396 run
->ex
.exception
, run
->ex
.error_code
);
2399 case KVM_EXIT_DEBUG
:
2400 DPRINTF("kvm_exit_debug\n");
2401 ret
= kvm_handle_debug(cpu
, &run
->debug
.arch
);
2404 fprintf(stderr
, "KVM: unknown exit reason %d\n", run
->exit_reason
);
2412 bool kvm_arch_stop_on_emulation_error(CPUState
*cs
)
2414 X86CPU
*cpu
= X86_CPU(cs
);
2415 CPUX86State
*env
= &cpu
->env
;
2417 kvm_cpu_synchronize_state(cs
);
2418 return !(env
->cr
[0] & CR0_PE_MASK
) ||
2419 ((env
->segs
[R_CS
].selector
& 3) != 3);
2422 void kvm_arch_init_irq_routing(KVMState
*s
)
2424 if (!kvm_check_extension(s
, KVM_CAP_IRQ_ROUTING
)) {
2425 /* If kernel can't do irq routing, interrupt source
2426 * override 0->2 cannot be set up as required by HPET.
2427 * So we have to disable it.
2431 /* We know at this point that we're using the in-kernel
2432 * irqchip, so we can use irqfds, and on x86 we know
2433 * we can use msi via irqfd and GSI routing.
2435 kvm_irqfds_allowed
= true;
2436 kvm_msi_via_irqfd_allowed
= true;
2437 kvm_gsi_routing_allowed
= true;
2440 /* Classic KVM device assignment interface. Will remain x86 only. */
2441 int kvm_device_pci_assign(KVMState
*s
, PCIHostDeviceAddress
*dev_addr
,
2442 uint32_t flags
, uint32_t *dev_id
)
2444 struct kvm_assigned_pci_dev dev_data
= {
2445 .segnr
= dev_addr
->domain
,
2446 .busnr
= dev_addr
->bus
,
2447 .devfn
= PCI_DEVFN(dev_addr
->slot
, dev_addr
->function
),
2452 dev_data
.assigned_dev_id
=
2453 (dev_addr
->domain
<< 16) | (dev_addr
->bus
<< 8) | dev_data
.devfn
;
2455 ret
= kvm_vm_ioctl(s
, KVM_ASSIGN_PCI_DEVICE
, &dev_data
);
2460 *dev_id
= dev_data
.assigned_dev_id
;
2465 int kvm_device_pci_deassign(KVMState
*s
, uint32_t dev_id
)
2467 struct kvm_assigned_pci_dev dev_data
= {
2468 .assigned_dev_id
= dev_id
,
2471 return kvm_vm_ioctl(s
, KVM_DEASSIGN_PCI_DEVICE
, &dev_data
);
2474 static int kvm_assign_irq_internal(KVMState
*s
, uint32_t dev_id
,
2475 uint32_t irq_type
, uint32_t guest_irq
)
2477 struct kvm_assigned_irq assigned_irq
= {
2478 .assigned_dev_id
= dev_id
,
2479 .guest_irq
= guest_irq
,
2483 if (kvm_check_extension(s
, KVM_CAP_ASSIGN_DEV_IRQ
)) {
2484 return kvm_vm_ioctl(s
, KVM_ASSIGN_DEV_IRQ
, &assigned_irq
);
2486 return kvm_vm_ioctl(s
, KVM_ASSIGN_IRQ
, &assigned_irq
);
2490 int kvm_device_intx_assign(KVMState
*s
, uint32_t dev_id
, bool use_host_msi
,
2493 uint32_t irq_type
= KVM_DEV_IRQ_GUEST_INTX
|
2494 (use_host_msi
? KVM_DEV_IRQ_HOST_MSI
: KVM_DEV_IRQ_HOST_INTX
);
2496 return kvm_assign_irq_internal(s
, dev_id
, irq_type
, guest_irq
);
2499 int kvm_device_intx_set_mask(KVMState
*s
, uint32_t dev_id
, bool masked
)
2501 struct kvm_assigned_pci_dev dev_data
= {
2502 .assigned_dev_id
= dev_id
,
2503 .flags
= masked
? KVM_DEV_ASSIGN_MASK_INTX
: 0,
2506 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_INTX_MASK
, &dev_data
);
2509 static int kvm_deassign_irq_internal(KVMState
*s
, uint32_t dev_id
,
2512 struct kvm_assigned_irq assigned_irq
= {
2513 .assigned_dev_id
= dev_id
,
2517 return kvm_vm_ioctl(s
, KVM_DEASSIGN_DEV_IRQ
, &assigned_irq
);
2520 int kvm_device_intx_deassign(KVMState
*s
, uint32_t dev_id
, bool use_host_msi
)
2522 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_INTX
|
2523 (use_host_msi
? KVM_DEV_IRQ_HOST_MSI
: KVM_DEV_IRQ_HOST_INTX
));
2526 int kvm_device_msi_assign(KVMState
*s
, uint32_t dev_id
, int virq
)
2528 return kvm_assign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_HOST_MSI
|
2529 KVM_DEV_IRQ_GUEST_MSI
, virq
);
2532 int kvm_device_msi_deassign(KVMState
*s
, uint32_t dev_id
)
2534 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_MSI
|
2535 KVM_DEV_IRQ_HOST_MSI
);
2538 bool kvm_device_msix_supported(KVMState
*s
)
2540 /* The kernel lacks a corresponding KVM_CAP, so we probe by calling
2541 * KVM_ASSIGN_SET_MSIX_NR with an invalid parameter. */
2542 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_NR
, NULL
) == -EFAULT
;
2545 int kvm_device_msix_init_vectors(KVMState
*s
, uint32_t dev_id
,
2546 uint32_t nr_vectors
)
2548 struct kvm_assigned_msix_nr msix_nr
= {
2549 .assigned_dev_id
= dev_id
,
2550 .entry_nr
= nr_vectors
,
2553 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_NR
, &msix_nr
);
2556 int kvm_device_msix_set_vector(KVMState
*s
, uint32_t dev_id
, uint32_t vector
,
2559 struct kvm_assigned_msix_entry msix_entry
= {
2560 .assigned_dev_id
= dev_id
,
2565 return kvm_vm_ioctl(s
, KVM_ASSIGN_SET_MSIX_ENTRY
, &msix_entry
);
2568 int kvm_device_msix_assign(KVMState
*s
, uint32_t dev_id
)
2570 return kvm_assign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_HOST_MSIX
|
2571 KVM_DEV_IRQ_GUEST_MSIX
, 0);
2574 int kvm_device_msix_deassign(KVMState
*s
, uint32_t dev_id
)
2576 return kvm_deassign_irq_internal(s
, dev_id
, KVM_DEV_IRQ_GUEST_MSIX
|
2577 KVM_DEV_IRQ_HOST_MSIX
);