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memory: drop AddressSpaceOps
[qemu-kvm.git] / hw / sun4m.c
blobb79d14c35a374e69ae0cb9ae5703a5e00cbadb42
1 /*
2 * QEMU Sun4m & Sun4d & Sun4c System Emulator
3 *
4 * Copyright (c) 2003-2005 Fabrice Bellard
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24 #include "sysbus.h"
25 #include "qemu-timer.h"
26 #include "sun4m.h"
27 #include "nvram.h"
28 #include "sparc32_dma.h"
29 #include "fdc.h"
30 #include "sysemu.h"
31 #include "net.h"
32 #include "boards.h"
33 #include "firmware_abi.h"
34 #include "esp.h"
35 #include "pc.h"
36 #include "isa.h"
37 #include "fw_cfg.h"
38 #include "escc.h"
39 #include "empty_slot.h"
40 #include "qdev-addr.h"
41 #include "loader.h"
42 #include "elf.h"
43 #include "blockdev.h"
44 #include "trace.h"
45
46 /*
47 * Sun4m architecture was used in the following machines:
48 *
49 * SPARCserver 6xxMP/xx
50 * SPARCclassic (SPARCclassic Server)(SPARCstation LC) (4/15),
51 * SPARCclassic X (4/10)
52 * SPARCstation LX/ZX (4/30)
53 * SPARCstation Voyager
54 * SPARCstation 10/xx, SPARCserver 10/xx
55 * SPARCstation 5, SPARCserver 5
56 * SPARCstation 20/xx, SPARCserver 20
57 * SPARCstation 4
58 *
59 * Sun4d architecture was used in the following machines:
60 *
61 * SPARCcenter 2000
62 * SPARCserver 1000
63 *
64 * Sun4c architecture was used in the following machines:
65 * SPARCstation 1/1+, SPARCserver 1/1+
66 * SPARCstation SLC
67 * SPARCstation IPC
68 * SPARCstation ELC
69 * SPARCstation IPX
70 *
71 * See for example: http://www.sunhelp.org/faq/sunref1.html
72 */
73
74 #define KERNEL_LOAD_ADDR 0x00004000
75 #define CMDLINE_ADDR 0x007ff000
76 #define INITRD_LOAD_ADDR 0x00800000
77 #define PROM_SIZE_MAX (1024 * 1024)
78 #define PROM_VADDR 0xffd00000
79 #define PROM_FILENAME "openbios-sparc32"
80 #define CFG_ADDR 0xd00000510ULL
81 #define FW_CFG_SUN4M_DEPTH (FW_CFG_ARCH_LOCAL + 0x00)
82
83 #define MAX_CPUS 16
84 #define MAX_PILS 16
85 #define MAX_VSIMMS 4
86
87 #define ESCC_CLOCK 4915200
88
89 struct sun4m_hwdef {
90 target_phys_addr_t iommu_base, iommu_pad_base, iommu_pad_len, slavio_base;
91 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
92 target_phys_addr_t serial_base, fd_base;
93 target_phys_addr_t afx_base, idreg_base, dma_base, esp_base, le_base;
94 target_phys_addr_t tcx_base, cs_base, apc_base, aux1_base, aux2_base;
95 target_phys_addr_t bpp_base, dbri_base, sx_base;
96 struct {
97 target_phys_addr_t reg_base, vram_base;
98 } vsimm[MAX_VSIMMS];
99 target_phys_addr_t ecc_base;
100 uint64_t max_mem;
101 const char * const default_cpu_model;
102 uint32_t ecc_version;
103 uint32_t iommu_version;
104 uint16_t machine_id;
105 uint8_t nvram_machine_id;
106 };
107
108 #define MAX_IOUNITS 5
109
110 struct sun4d_hwdef {
111 target_phys_addr_t iounit_bases[MAX_IOUNITS], slavio_base;
112 target_phys_addr_t counter_base, nvram_base, ms_kb_base;
113 target_phys_addr_t serial_base;
114 target_phys_addr_t espdma_base, esp_base;
115 target_phys_addr_t ledma_base, le_base;
116 target_phys_addr_t tcx_base;
117 target_phys_addr_t sbi_base;
118 uint64_t max_mem;
119 const char * const default_cpu_model;
120 uint32_t iounit_version;
121 uint16_t machine_id;
122 uint8_t nvram_machine_id;
123 };
124
125 struct sun4c_hwdef {
126 target_phys_addr_t iommu_base, slavio_base;
127 target_phys_addr_t intctl_base, counter_base, nvram_base, ms_kb_base;
128 target_phys_addr_t serial_base, fd_base;
129 target_phys_addr_t idreg_base, dma_base, esp_base, le_base;
130 target_phys_addr_t tcx_base, aux1_base;
131 uint64_t max_mem;
132 const char * const default_cpu_model;
133 uint32_t iommu_version;
134 uint16_t machine_id;
135 uint8_t nvram_machine_id;
136 };
137
138 int DMA_get_channel_mode (int nchan)
139 {
140 return 0;
141 }
142 int DMA_read_memory (int nchan, void *buf, int pos, int size)
143 {
144 return 0;
145 }
146 int DMA_write_memory (int nchan, void *buf, int pos, int size)
147 {
148 return 0;
149 }
150 void DMA_hold_DREQ (int nchan) {}
151 void DMA_release_DREQ (int nchan) {}
152 void DMA_schedule(int nchan) {}
153
154 void DMA_init(int high_page_enable, qemu_irq *cpu_request_exit)
155 {
156 }
157
158 void DMA_register_channel (int nchan,
159 DMA_transfer_handler transfer_handler,
160 void *opaque)
161 {
162 }
163
164 static int fw_cfg_boot_set(void *opaque, const char *boot_device)
165 {
166 fw_cfg_add_i16(opaque, FW_CFG_BOOT_DEVICE, boot_device[0]);
167 return 0;
168 }
169
170 static void nvram_init(M48t59State *nvram, uint8_t *macaddr,
171 const char *cmdline, const char *boot_devices,
172 ram_addr_t RAM_size, uint32_t kernel_size,
173 int width, int height, int depth,
174 int nvram_machine_id, const char *arch)
175 {
176 unsigned int i;
177 uint32_t start, end;
178 uint8_t image[0x1ff0];
179 struct OpenBIOS_nvpart_v1 *part_header;
180
181 memset(image, '\0', sizeof(image));
182
183 start = 0;
184
185 // OpenBIOS nvram variables
186 // Variable partition
187 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
188 part_header->signature = OPENBIOS_PART_SYSTEM;
189 pstrcpy(part_header->name, sizeof(part_header->name), "system");
190
191 end = start + sizeof(struct OpenBIOS_nvpart_v1);
192 for (i = 0; i < nb_prom_envs; i++)
193 end = OpenBIOS_set_var(image, end, prom_envs[i]);
194
195 // End marker
196 image[end++] = '\0';
197
198 end = start + ((end - start + 15) & ~15);
199 OpenBIOS_finish_partition(part_header, end - start);
200
201 // free partition
202 start = end;
203 part_header = (struct OpenBIOS_nvpart_v1 *)&image[start];
204 part_header->signature = OPENBIOS_PART_FREE;
205 pstrcpy(part_header->name, sizeof(part_header->name), "free");
206
207 end = 0x1fd0;
208 OpenBIOS_finish_partition(part_header, end - start);
209
210 Sun_init_header((struct Sun_nvram *)&image[0x1fd8], macaddr,
211 nvram_machine_id);
212
213 for (i = 0; i < sizeof(image); i++)
214 m48t59_write(nvram, i, image[i]);
215 }
216
217 static DeviceState *slavio_intctl;
218
219 void sun4m_pic_info(Monitor *mon)
220 {
221 if (slavio_intctl)
222 slavio_pic_info(mon, slavio_intctl);
223 }
224
225 void sun4m_irq_info(Monitor *mon)
226 {
227 if (slavio_intctl)
228 slavio_irq_info(mon, slavio_intctl);
229 }
230
231 void cpu_check_irqs(CPUState *env)
232 {
233 if (env->pil_in && (env->interrupt_index == 0 ||
234 (env->interrupt_index & ~15) == TT_EXTINT)) {
235 unsigned int i;
236
237 for (i = 15; i > 0; i--) {
238 if (env->pil_in & (1 << i)) {
239 int old_interrupt = env->interrupt_index;
240
241 env->interrupt_index = TT_EXTINT | i;
242 if (old_interrupt != env->interrupt_index) {
243 trace_sun4m_cpu_interrupt(i);
244 cpu_interrupt(env, CPU_INTERRUPT_HARD);
245 }
246 break;
247 }
248 }
249 } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
250 trace_sun4m_cpu_reset_interrupt(env->interrupt_index & 15);
251 env->interrupt_index = 0;
252 cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
253 }
254 }
255
256 static void cpu_kick_irq(CPUState *env)
257 {
258 env->halted = 0;
259 cpu_check_irqs(env);
260 qemu_cpu_kick(env);
261 }
262
263 static void cpu_set_irq(void *opaque, int irq, int level)
264 {
265 CPUState *env = opaque;
266
267 if (level) {
268 trace_sun4m_cpu_set_irq_raise(irq);
269 env->pil_in |= 1 << irq;
270 cpu_kick_irq(env);
271 } else {
272 trace_sun4m_cpu_set_irq_lower(irq);
273 env->pil_in &= ~(1 << irq);
274 cpu_check_irqs(env);
275 }
276 }
277
278 static void dummy_cpu_set_irq(void *opaque, int irq, int level)
279 {
280 }
281
282 static void main_cpu_reset(void *opaque)
283 {
284 CPUState *env = opaque;
285
286 cpu_reset(env);
287 env->halted = 0;
288 }
289
290 static void secondary_cpu_reset(void *opaque)
291 {
292 CPUState *env = opaque;
293
294 cpu_reset(env);
295 env->halted = 1;
296 }
297
298 static void cpu_halt_signal(void *opaque, int irq, int level)
299 {
300 if (level && cpu_single_env)
301 cpu_interrupt(cpu_single_env, CPU_INTERRUPT_HALT);
302 }
303
304 static uint64_t translate_kernel_address(void *opaque, uint64_t addr)
305 {
306 return addr - 0xf0000000ULL;
307 }
308
309 static unsigned long sun4m_load_kernel(const char *kernel_filename,
310 const char *initrd_filename,
311 ram_addr_t RAM_size)
312 {
313 int linux_boot;
314 unsigned int i;
315 long initrd_size, kernel_size;
316 uint8_t *ptr;
317
318 linux_boot = (kernel_filename != NULL);
319
320 kernel_size = 0;
321 if (linux_boot) {
322 int bswap_needed;
323
324 #ifdef BSWAP_NEEDED
325 bswap_needed = 1;
326 #else
327 bswap_needed = 0;
328 #endif
329 kernel_size = load_elf(kernel_filename, translate_kernel_address, NULL,
330 NULL, NULL, NULL, 1, ELF_MACHINE, 0);
331 if (kernel_size < 0)
332 kernel_size = load_aout(kernel_filename, KERNEL_LOAD_ADDR,
333 RAM_size - KERNEL_LOAD_ADDR, bswap_needed,
334 TARGET_PAGE_SIZE);
335 if (kernel_size < 0)
336 kernel_size = load_image_targphys(kernel_filename,
337 KERNEL_LOAD_ADDR,
338 RAM_size - KERNEL_LOAD_ADDR);
339 if (kernel_size < 0) {
340 fprintf(stderr, "qemu: could not load kernel '%s'\n",
341 kernel_filename);
342 exit(1);
343 }
344
345 /* load initrd */
346 initrd_size = 0;
347 if (initrd_filename) {
348 initrd_size = load_image_targphys(initrd_filename,
349 INITRD_LOAD_ADDR,
350 RAM_size - INITRD_LOAD_ADDR);
351 if (initrd_size < 0) {
352 fprintf(stderr, "qemu: could not load initial ram disk '%s'\n",
353 initrd_filename);
354 exit(1);
355 }
356 }
357 if (initrd_size > 0) {
358 for (i = 0; i < 64 * TARGET_PAGE_SIZE; i += TARGET_PAGE_SIZE) {
359 ptr = rom_ptr(KERNEL_LOAD_ADDR + i);
360 if (ldl_p(ptr) == 0x48647253) { // HdrS
361 stl_p(ptr + 16, INITRD_LOAD_ADDR);
362 stl_p(ptr + 20, initrd_size);
363 break;
364 }
365 }
366 }
367 }
368 return kernel_size;
369 }
370
371 static void *iommu_init(target_phys_addr_t addr, uint32_t version, qemu_irq irq)
372 {
373 DeviceState *dev;
374 SysBusDevice *s;
375
376 dev = qdev_create(NULL, "iommu");
377 qdev_prop_set_uint32(dev, "version", version);
378 qdev_init_nofail(dev);
379 s = sysbus_from_qdev(dev);
380 sysbus_connect_irq(s, 0, irq);
381 sysbus_mmio_map(s, 0, addr);
382
383 return s;
384 }
385
386 static void *sparc32_dma_init(target_phys_addr_t daddr, qemu_irq parent_irq,
387 void *iommu, qemu_irq *dev_irq, int is_ledma)
388 {
389 DeviceState *dev;
390 SysBusDevice *s;
391
392 dev = qdev_create(NULL, "sparc32_dma");
393 qdev_prop_set_ptr(dev, "iommu_opaque", iommu);
394 qdev_prop_set_uint32(dev, "is_ledma", is_ledma);
395 qdev_init_nofail(dev);
396 s = sysbus_from_qdev(dev);
397 sysbus_connect_irq(s, 0, parent_irq);
398 *dev_irq = qdev_get_gpio_in(dev, 0);
399 sysbus_mmio_map(s, 0, daddr);
400
401 return s;
402 }
403
404 static void lance_init(NICInfo *nd, target_phys_addr_t leaddr,
405 void *dma_opaque, qemu_irq irq)
406 {
407 DeviceState *dev;
408 SysBusDevice *s;
409 qemu_irq reset;
410
411 qemu_check_nic_model(&nd_table[0], "lance");
412
413 dev = qdev_create(NULL, "lance");
414 qdev_set_nic_properties(dev, nd);
415 qdev_prop_set_ptr(dev, "dma", dma_opaque);
416 qdev_init_nofail(dev);
417 s = sysbus_from_qdev(dev);
418 sysbus_mmio_map(s, 0, leaddr);
419 sysbus_connect_irq(s, 0, irq);
420 reset = qdev_get_gpio_in(dev, 0);
421 qdev_connect_gpio_out(dma_opaque, 0, reset);
422 }
423
424 static DeviceState *slavio_intctl_init(target_phys_addr_t addr,
425 target_phys_addr_t addrg,
426 qemu_irq **parent_irq)
427 {
428 DeviceState *dev;
429 SysBusDevice *s;
430 unsigned int i, j;
431
432 dev = qdev_create(NULL, "slavio_intctl");
433 qdev_init_nofail(dev);
434
435 s = sysbus_from_qdev(dev);
436
437 for (i = 0; i < MAX_CPUS; i++) {
438 for (j = 0; j < MAX_PILS; j++) {
439 sysbus_connect_irq(s, i * MAX_PILS + j, parent_irq[i][j]);
440 }
441 }
442 sysbus_mmio_map(s, 0, addrg);
443 for (i = 0; i < MAX_CPUS; i++) {
444 sysbus_mmio_map(s, i + 1, addr + i * TARGET_PAGE_SIZE);
445 }
446
447 return dev;
448 }
449
450 #define SYS_TIMER_OFFSET 0x10000ULL
451 #define CPU_TIMER_OFFSET(cpu) (0x1000ULL * cpu)
452
453 static void slavio_timer_init_all(target_phys_addr_t addr, qemu_irq master_irq,
454 qemu_irq *cpu_irqs, unsigned int num_cpus)
455 {
456 DeviceState *dev;
457 SysBusDevice *s;
458 unsigned int i;
459
460 dev = qdev_create(NULL, "slavio_timer");
461 qdev_prop_set_uint32(dev, "num_cpus", num_cpus);
462 qdev_init_nofail(dev);
463 s = sysbus_from_qdev(dev);
464 sysbus_connect_irq(s, 0, master_irq);
465 sysbus_mmio_map(s, 0, addr + SYS_TIMER_OFFSET);
466
467 for (i = 0; i < MAX_CPUS; i++) {
468 sysbus_mmio_map(s, i + 1, addr + (target_phys_addr_t)CPU_TIMER_OFFSET(i));
469 sysbus_connect_irq(s, i + 1, cpu_irqs[i]);
470 }
471 }
472
473 #define MISC_LEDS 0x01600000
474 #define MISC_CFG 0x01800000
475 #define MISC_DIAG 0x01a00000
476 #define MISC_MDM 0x01b00000
477 #define MISC_SYS 0x01f00000
478
479 static void slavio_misc_init(target_phys_addr_t base,
480 target_phys_addr_t aux1_base,
481 target_phys_addr_t aux2_base, qemu_irq irq,
482 qemu_irq fdc_tc)
483 {
484 DeviceState *dev;
485 SysBusDevice *s;
486
487 dev = qdev_create(NULL, "slavio_misc");
488 qdev_init_nofail(dev);
489 s = sysbus_from_qdev(dev);
490 if (base) {
491 /* 8 bit registers */
492 /* Slavio control */
493 sysbus_mmio_map(s, 0, base + MISC_CFG);
494 /* Diagnostics */
495 sysbus_mmio_map(s, 1, base + MISC_DIAG);
496 /* Modem control */
497 sysbus_mmio_map(s, 2, base + MISC_MDM);
498 /* 16 bit registers */
499 /* ss600mp diag LEDs */
500 sysbus_mmio_map(s, 3, base + MISC_LEDS);
501 /* 32 bit registers */
502 /* System control */
503 sysbus_mmio_map(s, 4, base + MISC_SYS);
504 }
505 if (aux1_base) {
506 /* AUX 1 (Misc System Functions) */
507 sysbus_mmio_map(s, 5, aux1_base);
508 }
509 if (aux2_base) {
510 /* AUX 2 (Software Powerdown Control) */
511 sysbus_mmio_map(s, 6, aux2_base);
512 }
513 sysbus_connect_irq(s, 0, irq);
514 sysbus_connect_irq(s, 1, fdc_tc);
515 qemu_system_powerdown = qdev_get_gpio_in(dev, 0);
516 }
517
518 static void ecc_init(target_phys_addr_t base, qemu_irq irq, uint32_t version)
519 {
520 DeviceState *dev;
521 SysBusDevice *s;
522
523 dev = qdev_create(NULL, "eccmemctl");
524 qdev_prop_set_uint32(dev, "version", version);
525 qdev_init_nofail(dev);
526 s = sysbus_from_qdev(dev);
527 sysbus_connect_irq(s, 0, irq);
528 sysbus_mmio_map(s, 0, base);
529 if (version == 0) { // SS-600MP only
530 sysbus_mmio_map(s, 1, base + 0x1000);
531 }
532 }
533
534 static void apc_init(target_phys_addr_t power_base, qemu_irq cpu_halt)
535 {
536 DeviceState *dev;
537 SysBusDevice *s;
538
539 dev = qdev_create(NULL, "apc");
540 qdev_init_nofail(dev);
541 s = sysbus_from_qdev(dev);
542 /* Power management (APC) XXX: not a Slavio device */
543 sysbus_mmio_map(s, 0, power_base);
544 sysbus_connect_irq(s, 0, cpu_halt);
545 }
546
547 static void tcx_init(target_phys_addr_t addr, int vram_size, int width,
548 int height, int depth)
549 {
550 DeviceState *dev;
551 SysBusDevice *s;
552
553 dev = qdev_create(NULL, "SUNW,tcx");
554 qdev_prop_set_taddr(dev, "addr", addr);
555 qdev_prop_set_uint32(dev, "vram_size", vram_size);
556 qdev_prop_set_uint16(dev, "width", width);
557 qdev_prop_set_uint16(dev, "height", height);
558 qdev_prop_set_uint16(dev, "depth", depth);
559 qdev_init_nofail(dev);
560 s = sysbus_from_qdev(dev);
561 /* 8-bit plane */
562 sysbus_mmio_map(s, 0, addr + 0x00800000ULL);
563 /* DAC */
564 sysbus_mmio_map(s, 1, addr + 0x00200000ULL);
565 /* TEC (dummy) */
566 sysbus_mmio_map(s, 2, addr + 0x00700000ULL);
567 /* THC 24 bit: NetBSD writes here even with 8-bit display: dummy */
568 sysbus_mmio_map(s, 3, addr + 0x00301000ULL);
569 if (depth == 24) {
570 /* 24-bit plane */
571 sysbus_mmio_map(s, 4, addr + 0x02000000ULL);
572 /* Control plane */
573 sysbus_mmio_map(s, 5, addr + 0x0a000000ULL);
574 } else {
575 /* THC 8 bit (dummy) */
576 sysbus_mmio_map(s, 4, addr + 0x00300000ULL);
577 }
578 }
579
580 /* NCR89C100/MACIO Internal ID register */
581 static const uint8_t idreg_data[] = { 0xfe, 0x81, 0x01, 0x03 };
582
583 static void idreg_init(target_phys_addr_t addr)
584 {
585 DeviceState *dev;
586 SysBusDevice *s;
587
588 dev = qdev_create(NULL, "macio_idreg");
589 qdev_init_nofail(dev);
590 s = sysbus_from_qdev(dev);
591
592 sysbus_mmio_map(s, 0, addr);
593 cpu_physical_memory_write_rom(addr, idreg_data, sizeof(idreg_data));
594 }
595
596 typedef struct IDRegState {
597 SysBusDevice busdev;
598 MemoryRegion mem;
599 } IDRegState;
600
601 static int idreg_init1(SysBusDevice *dev)
602 {
603 IDRegState *s = FROM_SYSBUS(IDRegState, dev);
604
605 memory_region_init_ram(&s->mem, "sun4m.idreg", sizeof(idreg_data));
606 vmstate_register_ram_global(&s->mem);
607 memory_region_set_readonly(&s->mem, true);
608 sysbus_init_mmio(dev, &s->mem);
609 return 0;
610 }
611
612 static void idreg_class_init(ObjectClass *klass, void *data)
613 {
614 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
615
616 k->init = idreg_init1;
617 }
618
619 static TypeInfo idreg_info = {
620 .name = "macio_idreg",
621 .parent = TYPE_SYS_BUS_DEVICE,
622 .instance_size = sizeof(IDRegState),
623 .class_init = idreg_class_init,
624 };
625
626 static void idreg_register_devices(void)
627 {
628 type_register_static(&idreg_info);
629 }
630
631 device_init(idreg_register_devices);
632
633 typedef struct AFXState {
634 SysBusDevice busdev;
635 MemoryRegion mem;
636 } AFXState;
637
638 /* SS-5 TCX AFX register */
639 static void afx_init(target_phys_addr_t addr)
640 {
641 DeviceState *dev;
642 SysBusDevice *s;
643
644 dev = qdev_create(NULL, "tcx_afx");
645 qdev_init_nofail(dev);
646 s = sysbus_from_qdev(dev);
647
648 sysbus_mmio_map(s, 0, addr);
649 }
650
651 static int afx_init1(SysBusDevice *dev)
652 {
653 AFXState *s = FROM_SYSBUS(AFXState, dev);
654
655 memory_region_init_ram(&s->mem, "sun4m.afx", 4);
656 vmstate_register_ram_global(&s->mem);
657 sysbus_init_mmio(dev, &s->mem);
658 return 0;
659 }
660
661 static void afx_class_init(ObjectClass *klass, void *data)
662 {
663 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
664
665 k->init = afx_init1;
666 }
667
668 static TypeInfo afx_info = {
669 .name = "tcx_afx",
670 .parent = TYPE_SYS_BUS_DEVICE,
671 .instance_size = sizeof(AFXState),
672 .class_init = afx_class_init,
673 };
674
675 static void afx_register_devices(void)
676 {
677 type_register_static(&afx_info);
678 }
679
680 device_init(afx_register_devices);
681
682 typedef struct PROMState {
683 SysBusDevice busdev;
684 MemoryRegion prom;
685 } PROMState;
686
687 /* Boot PROM (OpenBIOS) */
688 static uint64_t translate_prom_address(void *opaque, uint64_t addr)
689 {
690 target_phys_addr_t *base_addr = (target_phys_addr_t *)opaque;
691 return addr + *base_addr - PROM_VADDR;
692 }
693
694 static void prom_init(target_phys_addr_t addr, const char *bios_name)
695 {
696 DeviceState *dev;
697 SysBusDevice *s;
698 char *filename;
699 int ret;
700
701 dev = qdev_create(NULL, "openprom");
702 qdev_init_nofail(dev);
703 s = sysbus_from_qdev(dev);
704
705 sysbus_mmio_map(s, 0, addr);
706
707 /* load boot prom */
708 if (bios_name == NULL) {
709 bios_name = PROM_FILENAME;
710 }
711 filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name);
712 if (filename) {
713 ret = load_elf(filename, translate_prom_address, &addr, NULL,
714 NULL, NULL, 1, ELF_MACHINE, 0);
715 if (ret < 0 || ret > PROM_SIZE_MAX) {
716 ret = load_image_targphys(filename, addr, PROM_SIZE_MAX);
717 }
718 g_free(filename);
719 } else {
720 ret = -1;
721 }
722 if (ret < 0 || ret > PROM_SIZE_MAX) {
723 fprintf(stderr, "qemu: could not load prom '%s'\n", bios_name);
724 exit(1);
725 }
726 }
727
728 static int prom_init1(SysBusDevice *dev)
729 {
730 PROMState *s = FROM_SYSBUS(PROMState, dev);
731
732 memory_region_init_ram(&s->prom, "sun4m.prom", PROM_SIZE_MAX);
733 vmstate_register_ram_global(&s->prom);
734 memory_region_set_readonly(&s->prom, true);
735 sysbus_init_mmio(dev, &s->prom);
736 return 0;
737 }
738
739 static Property prom_properties[] = {
740 {/* end of property list */},
741 };
742
743 static void prom_class_init(ObjectClass *klass, void *data)
744 {
745 DeviceClass *dc = DEVICE_CLASS(klass);
746 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
747
748 k->init = prom_init1;
749 dc->props = prom_properties;
750 }
751
752 static TypeInfo prom_info = {
753 .name = "openprom",
754 .parent = TYPE_SYS_BUS_DEVICE,
755 .instance_size = sizeof(PROMState),
756 .class_init = prom_class_init,
757 };
758
759 static void prom_register_devices(void)
760 {
761 type_register_static(&prom_info);
762 }
763
764 device_init(prom_register_devices);
765
766 typedef struct RamDevice
767 {
768 SysBusDevice busdev;
769 MemoryRegion ram;
770 uint64_t size;
771 } RamDevice;
772
773 /* System RAM */
774 static int ram_init1(SysBusDevice *dev)
775 {
776 RamDevice *d = FROM_SYSBUS(RamDevice, dev);
777
778 memory_region_init_ram(&d->ram, "sun4m.ram", d->size);
779 vmstate_register_ram_global(&d->ram);
780 sysbus_init_mmio(dev, &d->ram);
781 return 0;
782 }
783
784 static void ram_init(target_phys_addr_t addr, ram_addr_t RAM_size,
785 uint64_t max_mem)
786 {
787 DeviceState *dev;
788 SysBusDevice *s;
789 RamDevice *d;
790
791 /* allocate RAM */
792 if ((uint64_t)RAM_size > max_mem) {
793 fprintf(stderr,
794 "qemu: Too much memory for this machine: %d, maximum %d\n",
795 (unsigned int)(RAM_size / (1024 * 1024)),
796 (unsigned int)(max_mem / (1024 * 1024)));
797 exit(1);
798 }
799 dev = qdev_create(NULL, "memory");
800 s = sysbus_from_qdev(dev);
801
802 d = FROM_SYSBUS(RamDevice, s);
803 d->size = RAM_size;
804 qdev_init_nofail(dev);
805
806 sysbus_mmio_map(s, 0, addr);
807 }
808
809 static Property ram_properties[] = {
810 DEFINE_PROP_UINT64("size", RamDevice, size, 0),
811 DEFINE_PROP_END_OF_LIST(),
812 };
813
814 static void ram_class_init(ObjectClass *klass, void *data)
815 {
816 DeviceClass *dc = DEVICE_CLASS(klass);
817 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
818
819 k->init = ram_init1;
820 dc->props = ram_properties;
821 }
822
823 static TypeInfo ram_info = {
824 .name = "memory",
825 .parent = TYPE_SYS_BUS_DEVICE,
826 .instance_size = sizeof(RamDevice),
827 .class_init = ram_class_init,
828 };
829
830 static void ram_register_devices(void)
831 {
832 type_register_static(&ram_info);
833 }
834
835 device_init(ram_register_devices);
836
837 static void cpu_devinit(const char *cpu_model, unsigned int id,
838 uint64_t prom_addr, qemu_irq **cpu_irqs)
839 {
840 CPUState *env;
841
842 env = cpu_init(cpu_model);
843 if (!env) {
844 fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n");
845 exit(1);
846 }
847
848 cpu_sparc_set_id(env, id);
849 if (id == 0) {
850 qemu_register_reset(main_cpu_reset, env);
851 } else {
852 qemu_register_reset(secondary_cpu_reset, env);
853 env->halted = 1;
854 }
855 *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS);
856 env->prom_addr = prom_addr;
857 }
858
859 static void sun4m_hw_init(const struct sun4m_hwdef *hwdef, ram_addr_t RAM_size,
860 const char *boot_device,
861 const char *kernel_filename,
862 const char *kernel_cmdline,
863 const char *initrd_filename, const char *cpu_model)
864 {
865 unsigned int i;
866 void *iommu, *espdma, *ledma, *nvram;
867 qemu_irq *cpu_irqs[MAX_CPUS], slavio_irq[32], slavio_cpu_irq[MAX_CPUS],
868 espdma_irq, ledma_irq;
869 qemu_irq esp_reset, dma_enable;
870 qemu_irq fdc_tc;
871 qemu_irq *cpu_halt;
872 unsigned long kernel_size;
873 DriveInfo *fd[MAX_FD];
874 void *fw_cfg;
875 unsigned int num_vsimms;
876
877 /* init CPUs */
878 if (!cpu_model)
879 cpu_model = hwdef->default_cpu_model;
880
881 for(i = 0; i < smp_cpus; i++) {
882 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
883 }
884
885 for (i = smp_cpus; i < MAX_CPUS; i++)
886 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
887
888
889 /* set up devices */
890 ram_init(0, RAM_size, hwdef->max_mem);
891 /* models without ECC don't trap when missing ram is accessed */
892 if (!hwdef->ecc_base) {
893 empty_slot_init(RAM_size, hwdef->max_mem - RAM_size);
894 }
895
896 prom_init(hwdef->slavio_base, bios_name);
897
898 slavio_intctl = slavio_intctl_init(hwdef->intctl_base,
899 hwdef->intctl_base + 0x10000ULL,
900 cpu_irqs);
901
902 for (i = 0; i < 32; i++) {
903 slavio_irq[i] = qdev_get_gpio_in(slavio_intctl, i);
904 }
905 for (i = 0; i < MAX_CPUS; i++) {
906 slavio_cpu_irq[i] = qdev_get_gpio_in(slavio_intctl, 32 + i);
907 }
908
909 if (hwdef->idreg_base) {
910 idreg_init(hwdef->idreg_base);
911 }
912
913 if (hwdef->afx_base) {
914 afx_init(hwdef->afx_base);
915 }
916
917 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
918 slavio_irq[30]);
919
920 if (hwdef->iommu_pad_base) {
921 /* On the real hardware (SS-5, LX) the MMU is not padded, but aliased.
922 Software shouldn't use aliased addresses, neither should it crash
923 when does. Using empty_slot instead of aliasing can help with
924 debugging such accesses */
925 empty_slot_init(hwdef->iommu_pad_base,hwdef->iommu_pad_len);
926 }
927
928 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[18],
929 iommu, &espdma_irq, 0);
930
931 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
932 slavio_irq[16], iommu, &ledma_irq, 1);
933
934 if (graphic_depth != 8 && graphic_depth != 24) {
935 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
936 exit (1);
937 }
938 num_vsimms = 0;
939 if (num_vsimms == 0) {
940 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
941 graphic_depth);
942 }
943
944 for (i = num_vsimms; i < MAX_VSIMMS; i++) {
945 /* vsimm registers probed by OBP */
946 if (hwdef->vsimm[i].reg_base) {
947 empty_slot_init(hwdef->vsimm[i].reg_base, 0x2000);
948 }
949 }
950
951 if (hwdef->sx_base) {
952 empty_slot_init(hwdef->sx_base, 0x2000);
953 }
954
955 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
956
957 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
958
959 slavio_timer_init_all(hwdef->counter_base, slavio_irq[19], slavio_cpu_irq, smp_cpus);
960
961 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[14],
962 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
963 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
964 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
965 escc_init(hwdef->serial_base, slavio_irq[15], slavio_irq[15],
966 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
967
968 cpu_halt = qemu_allocate_irqs(cpu_halt_signal, NULL, 1);
969 slavio_misc_init(hwdef->slavio_base, hwdef->aux1_base, hwdef->aux2_base,
970 slavio_irq[30], fdc_tc);
971
972 if (hwdef->apc_base) {
973 apc_init(hwdef->apc_base, cpu_halt[0]);
974 }
975
976 if (hwdef->fd_base) {
977 /* there is zero or one floppy drive */
978 memset(fd, 0, sizeof(fd));
979 fd[0] = drive_get(IF_FLOPPY, 0, 0);
980 sun4m_fdctrl_init(slavio_irq[22], hwdef->fd_base, fd,
981 &fdc_tc);
982 }
983
984 if (drive_get_max_bus(IF_SCSI) > 0) {
985 fprintf(stderr, "qemu: too many SCSI bus\n");
986 exit(1);
987 }
988
989 esp_init(hwdef->esp_base, 2,
990 espdma_memory_read, espdma_memory_write,
991 espdma, espdma_irq, &esp_reset, &dma_enable);
992
993 qdev_connect_gpio_out(espdma, 0, esp_reset);
994 qdev_connect_gpio_out(espdma, 1, dma_enable);
995
996 if (hwdef->cs_base) {
997 sysbus_create_simple("SUNW,CS4231", hwdef->cs_base,
998 slavio_irq[5]);
999 }
1000
1001 if (hwdef->dbri_base) {
1002 /* ISDN chip with attached CS4215 audio codec */
1003 /* prom space */
1004 empty_slot_init(hwdef->dbri_base+0x1000, 0x30);
1005 /* reg space */
1006 empty_slot_init(hwdef->dbri_base+0x10000, 0x100);
1007 }
1008
1009 if (hwdef->bpp_base) {
1010 /* parallel port */
1011 empty_slot_init(hwdef->bpp_base, 0x20);
1012 }
1013
1014 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1015 RAM_size);
1016
1017 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1018 boot_device, RAM_size, kernel_size, graphic_width,
1019 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1020 "Sun4m");
1021
1022 if (hwdef->ecc_base)
1023 ecc_init(hwdef->ecc_base, slavio_irq[28],
1024 hwdef->ecc_version);
1025
1026 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1027 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1028 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1029 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1030 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1031 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1032 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1033 if (kernel_cmdline) {
1034 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1035 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1036 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1037 (uint8_t*)strdup(kernel_cmdline),
1038 strlen(kernel_cmdline) + 1);
1039 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE,
1040 strlen(kernel_cmdline) + 1);
1041 } else {
1042 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1043 fw_cfg_add_i32(fw_cfg, FW_CFG_CMDLINE_SIZE, 0);
1044 }
1045 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1046 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1047 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1048 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1049 }
1050
1051 enum {
1052 ss2_id = 0,
1053 ss5_id = 32,
1054 vger_id,
1055 lx_id,
1056 ss4_id,
1057 scls_id,
1058 sbook_id,
1059 ss10_id = 64,
1060 ss20_id,
1061 ss600mp_id,
1062 ss1000_id = 96,
1063 ss2000_id,
1064 };
1065
1066 static const struct sun4m_hwdef sun4m_hwdefs[] = {
1067 /* SS-5 */
1068 {
1069 .iommu_base = 0x10000000,
1070 .iommu_pad_base = 0x10004000,
1071 .iommu_pad_len = 0x0fffb000,
1072 .tcx_base = 0x50000000,
1073 .cs_base = 0x6c000000,
1074 .slavio_base = 0x70000000,
1075 .ms_kb_base = 0x71000000,
1076 .serial_base = 0x71100000,
1077 .nvram_base = 0x71200000,
1078 .fd_base = 0x71400000,
1079 .counter_base = 0x71d00000,
1080 .intctl_base = 0x71e00000,
1081 .idreg_base = 0x78000000,
1082 .dma_base = 0x78400000,
1083 .esp_base = 0x78800000,
1084 .le_base = 0x78c00000,
1085 .apc_base = 0x6a000000,
1086 .afx_base = 0x6e000000,
1087 .aux1_base = 0x71900000,
1088 .aux2_base = 0x71910000,
1089 .nvram_machine_id = 0x80,
1090 .machine_id = ss5_id,
1091 .iommu_version = 0x05000000,
1092 .max_mem = 0x10000000,
1093 .default_cpu_model = "Fujitsu MB86904",
1094 },
1095 /* SS-10 */
1096 {
1097 .iommu_base = 0xfe0000000ULL,
1098 .tcx_base = 0xe20000000ULL,
1099 .slavio_base = 0xff0000000ULL,
1100 .ms_kb_base = 0xff1000000ULL,
1101 .serial_base = 0xff1100000ULL,
1102 .nvram_base = 0xff1200000ULL,
1103 .fd_base = 0xff1700000ULL,
1104 .counter_base = 0xff1300000ULL,
1105 .intctl_base = 0xff1400000ULL,
1106 .idreg_base = 0xef0000000ULL,
1107 .dma_base = 0xef0400000ULL,
1108 .esp_base = 0xef0800000ULL,
1109 .le_base = 0xef0c00000ULL,
1110 .apc_base = 0xefa000000ULL, // XXX should not exist
1111 .aux1_base = 0xff1800000ULL,
1112 .aux2_base = 0xff1a01000ULL,
1113 .ecc_base = 0xf00000000ULL,
1114 .ecc_version = 0x10000000, // version 0, implementation 1
1115 .nvram_machine_id = 0x72,
1116 .machine_id = ss10_id,
1117 .iommu_version = 0x03000000,
1118 .max_mem = 0xf00000000ULL,
1119 .default_cpu_model = "TI SuperSparc II",
1120 },
1121 /* SS-600MP */
1122 {
1123 .iommu_base = 0xfe0000000ULL,
1124 .tcx_base = 0xe20000000ULL,
1125 .slavio_base = 0xff0000000ULL,
1126 .ms_kb_base = 0xff1000000ULL,
1127 .serial_base = 0xff1100000ULL,
1128 .nvram_base = 0xff1200000ULL,
1129 .counter_base = 0xff1300000ULL,
1130 .intctl_base = 0xff1400000ULL,
1131 .dma_base = 0xef0081000ULL,
1132 .esp_base = 0xef0080000ULL,
1133 .le_base = 0xef0060000ULL,
1134 .apc_base = 0xefa000000ULL, // XXX should not exist
1135 .aux1_base = 0xff1800000ULL,
1136 .aux2_base = 0xff1a01000ULL, // XXX should not exist
1137 .ecc_base = 0xf00000000ULL,
1138 .ecc_version = 0x00000000, // version 0, implementation 0
1139 .nvram_machine_id = 0x71,
1140 .machine_id = ss600mp_id,
1141 .iommu_version = 0x01000000,
1142 .max_mem = 0xf00000000ULL,
1143 .default_cpu_model = "TI SuperSparc II",
1144 },
1145 /* SS-20 */
1146 {
1147 .iommu_base = 0xfe0000000ULL,
1148 .tcx_base = 0xe20000000ULL,
1149 .slavio_base = 0xff0000000ULL,
1150 .ms_kb_base = 0xff1000000ULL,
1151 .serial_base = 0xff1100000ULL,
1152 .nvram_base = 0xff1200000ULL,
1153 .fd_base = 0xff1700000ULL,
1154 .counter_base = 0xff1300000ULL,
1155 .intctl_base = 0xff1400000ULL,
1156 .idreg_base = 0xef0000000ULL,
1157 .dma_base = 0xef0400000ULL,
1158 .esp_base = 0xef0800000ULL,
1159 .le_base = 0xef0c00000ULL,
1160 .bpp_base = 0xef4800000ULL,
1161 .apc_base = 0xefa000000ULL, // XXX should not exist
1162 .aux1_base = 0xff1800000ULL,
1163 .aux2_base = 0xff1a01000ULL,
1164 .dbri_base = 0xee0000000ULL,
1165 .sx_base = 0xf80000000ULL,
1166 .vsimm = {
1167 {
1168 .reg_base = 0x9c000000ULL,
1169 .vram_base = 0xfc000000ULL
1170 }, {
1171 .reg_base = 0x90000000ULL,
1172 .vram_base = 0xf0000000ULL
1173 }, {
1174 .reg_base = 0x94000000ULL
1175 }, {
1176 .reg_base = 0x98000000ULL
1177 }
1178 },
1179 .ecc_base = 0xf00000000ULL,
1180 .ecc_version = 0x20000000, // version 0, implementation 2
1181 .nvram_machine_id = 0x72,
1182 .machine_id = ss20_id,
1183 .iommu_version = 0x13000000,
1184 .max_mem = 0xf00000000ULL,
1185 .default_cpu_model = "TI SuperSparc II",
1186 },
1187 /* Voyager */
1188 {
1189 .iommu_base = 0x10000000,
1190 .tcx_base = 0x50000000,
1191 .slavio_base = 0x70000000,
1192 .ms_kb_base = 0x71000000,
1193 .serial_base = 0x71100000,
1194 .nvram_base = 0x71200000,
1195 .fd_base = 0x71400000,
1196 .counter_base = 0x71d00000,
1197 .intctl_base = 0x71e00000,
1198 .idreg_base = 0x78000000,
1199 .dma_base = 0x78400000,
1200 .esp_base = 0x78800000,
1201 .le_base = 0x78c00000,
1202 .apc_base = 0x71300000, // pmc
1203 .aux1_base = 0x71900000,
1204 .aux2_base = 0x71910000,
1205 .nvram_machine_id = 0x80,
1206 .machine_id = vger_id,
1207 .iommu_version = 0x05000000,
1208 .max_mem = 0x10000000,
1209 .default_cpu_model = "Fujitsu MB86904",
1210 },
1211 /* LX */
1212 {
1213 .iommu_base = 0x10000000,
1214 .iommu_pad_base = 0x10004000,
1215 .iommu_pad_len = 0x0fffb000,
1216 .tcx_base = 0x50000000,
1217 .slavio_base = 0x70000000,
1218 .ms_kb_base = 0x71000000,
1219 .serial_base = 0x71100000,
1220 .nvram_base = 0x71200000,
1221 .fd_base = 0x71400000,
1222 .counter_base = 0x71d00000,
1223 .intctl_base = 0x71e00000,
1224 .idreg_base = 0x78000000,
1225 .dma_base = 0x78400000,
1226 .esp_base = 0x78800000,
1227 .le_base = 0x78c00000,
1228 .aux1_base = 0x71900000,
1229 .aux2_base = 0x71910000,
1230 .nvram_machine_id = 0x80,
1231 .machine_id = lx_id,
1232 .iommu_version = 0x04000000,
1233 .max_mem = 0x10000000,
1234 .default_cpu_model = "TI MicroSparc I",
1235 },
1236 /* SS-4 */
1237 {
1238 .iommu_base = 0x10000000,
1239 .tcx_base = 0x50000000,
1240 .cs_base = 0x6c000000,
1241 .slavio_base = 0x70000000,
1242 .ms_kb_base = 0x71000000,
1243 .serial_base = 0x71100000,
1244 .nvram_base = 0x71200000,
1245 .fd_base = 0x71400000,
1246 .counter_base = 0x71d00000,
1247 .intctl_base = 0x71e00000,
1248 .idreg_base = 0x78000000,
1249 .dma_base = 0x78400000,
1250 .esp_base = 0x78800000,
1251 .le_base = 0x78c00000,
1252 .apc_base = 0x6a000000,
1253 .aux1_base = 0x71900000,
1254 .aux2_base = 0x71910000,
1255 .nvram_machine_id = 0x80,
1256 .machine_id = ss4_id,
1257 .iommu_version = 0x05000000,
1258 .max_mem = 0x10000000,
1259 .default_cpu_model = "Fujitsu MB86904",
1260 },
1261 /* SPARCClassic */
1262 {
1263 .iommu_base = 0x10000000,
1264 .tcx_base = 0x50000000,
1265 .slavio_base = 0x70000000,
1266 .ms_kb_base = 0x71000000,
1267 .serial_base = 0x71100000,
1268 .nvram_base = 0x71200000,
1269 .fd_base = 0x71400000,
1270 .counter_base = 0x71d00000,
1271 .intctl_base = 0x71e00000,
1272 .idreg_base = 0x78000000,
1273 .dma_base = 0x78400000,
1274 .esp_base = 0x78800000,
1275 .le_base = 0x78c00000,
1276 .apc_base = 0x6a000000,
1277 .aux1_base = 0x71900000,
1278 .aux2_base = 0x71910000,
1279 .nvram_machine_id = 0x80,
1280 .machine_id = scls_id,
1281 .iommu_version = 0x05000000,
1282 .max_mem = 0x10000000,
1283 .default_cpu_model = "TI MicroSparc I",
1284 },
1285 /* SPARCbook */
1286 {
1287 .iommu_base = 0x10000000,
1288 .tcx_base = 0x50000000, // XXX
1289 .slavio_base = 0x70000000,
1290 .ms_kb_base = 0x71000000,
1291 .serial_base = 0x71100000,
1292 .nvram_base = 0x71200000,
1293 .fd_base = 0x71400000,
1294 .counter_base = 0x71d00000,
1295 .intctl_base = 0x71e00000,
1296 .idreg_base = 0x78000000,
1297 .dma_base = 0x78400000,
1298 .esp_base = 0x78800000,
1299 .le_base = 0x78c00000,
1300 .apc_base = 0x6a000000,
1301 .aux1_base = 0x71900000,
1302 .aux2_base = 0x71910000,
1303 .nvram_machine_id = 0x80,
1304 .machine_id = sbook_id,
1305 .iommu_version = 0x05000000,
1306 .max_mem = 0x10000000,
1307 .default_cpu_model = "TI MicroSparc I",
1308 },
1309 };
1310
1311 /* SPARCstation 5 hardware initialisation */
1312 static void ss5_init(ram_addr_t RAM_size,
1313 const char *boot_device,
1314 const char *kernel_filename, const char *kernel_cmdline,
1315 const char *initrd_filename, const char *cpu_model)
1316 {
1317 sun4m_hw_init(&sun4m_hwdefs[0], RAM_size, boot_device, kernel_filename,
1318 kernel_cmdline, initrd_filename, cpu_model);
1319 }
1320
1321 /* SPARCstation 10 hardware initialisation */
1322 static void ss10_init(ram_addr_t RAM_size,
1323 const char *boot_device,
1324 const char *kernel_filename, const char *kernel_cmdline,
1325 const char *initrd_filename, const char *cpu_model)
1326 {
1327 sun4m_hw_init(&sun4m_hwdefs[1], RAM_size, boot_device, kernel_filename,
1328 kernel_cmdline, initrd_filename, cpu_model);
1329 }
1330
1331 /* SPARCserver 600MP hardware initialisation */
1332 static void ss600mp_init(ram_addr_t RAM_size,
1333 const char *boot_device,
1334 const char *kernel_filename,
1335 const char *kernel_cmdline,
1336 const char *initrd_filename, const char *cpu_model)
1337 {
1338 sun4m_hw_init(&sun4m_hwdefs[2], RAM_size, boot_device, kernel_filename,
1339 kernel_cmdline, initrd_filename, cpu_model);
1340 }
1341
1342 /* SPARCstation 20 hardware initialisation */
1343 static void ss20_init(ram_addr_t RAM_size,
1344 const char *boot_device,
1345 const char *kernel_filename, const char *kernel_cmdline,
1346 const char *initrd_filename, const char *cpu_model)
1347 {
1348 sun4m_hw_init(&sun4m_hwdefs[3], RAM_size, boot_device, kernel_filename,
1349 kernel_cmdline, initrd_filename, cpu_model);
1350 }
1351
1352 /* SPARCstation Voyager hardware initialisation */
1353 static void vger_init(ram_addr_t RAM_size,
1354 const char *boot_device,
1355 const char *kernel_filename, const char *kernel_cmdline,
1356 const char *initrd_filename, const char *cpu_model)
1357 {
1358 sun4m_hw_init(&sun4m_hwdefs[4], RAM_size, boot_device, kernel_filename,
1359 kernel_cmdline, initrd_filename, cpu_model);
1360 }
1361
1362 /* SPARCstation LX hardware initialisation */
1363 static void ss_lx_init(ram_addr_t RAM_size,
1364 const char *boot_device,
1365 const char *kernel_filename, const char *kernel_cmdline,
1366 const char *initrd_filename, const char *cpu_model)
1367 {
1368 sun4m_hw_init(&sun4m_hwdefs[5], RAM_size, boot_device, kernel_filename,
1369 kernel_cmdline, initrd_filename, cpu_model);
1370 }
1371
1372 /* SPARCstation 4 hardware initialisation */
1373 static void ss4_init(ram_addr_t RAM_size,
1374 const char *boot_device,
1375 const char *kernel_filename, const char *kernel_cmdline,
1376 const char *initrd_filename, const char *cpu_model)
1377 {
1378 sun4m_hw_init(&sun4m_hwdefs[6], RAM_size, boot_device, kernel_filename,
1379 kernel_cmdline, initrd_filename, cpu_model);
1380 }
1381
1382 /* SPARCClassic hardware initialisation */
1383 static void scls_init(ram_addr_t RAM_size,
1384 const char *boot_device,
1385 const char *kernel_filename, const char *kernel_cmdline,
1386 const char *initrd_filename, const char *cpu_model)
1387 {
1388 sun4m_hw_init(&sun4m_hwdefs[7], RAM_size, boot_device, kernel_filename,
1389 kernel_cmdline, initrd_filename, cpu_model);
1390 }
1391
1392 /* SPARCbook hardware initialisation */
1393 static void sbook_init(ram_addr_t RAM_size,
1394 const char *boot_device,
1395 const char *kernel_filename, const char *kernel_cmdline,
1396 const char *initrd_filename, const char *cpu_model)
1397 {
1398 sun4m_hw_init(&sun4m_hwdefs[8], RAM_size, boot_device, kernel_filename,
1399 kernel_cmdline, initrd_filename, cpu_model);
1400 }
1401
1402 static QEMUMachine ss5_machine = {
1403 .name = "SS-5",
1404 .desc = "Sun4m platform, SPARCstation 5",
1405 .init = ss5_init,
1406 .use_scsi = 1,
1407 .is_default = 1,
1408 };
1409
1410 static QEMUMachine ss10_machine = {
1411 .name = "SS-10",
1412 .desc = "Sun4m platform, SPARCstation 10",
1413 .init = ss10_init,
1414 .use_scsi = 1,
1415 .max_cpus = 4,
1416 };
1417
1418 static QEMUMachine ss600mp_machine = {
1419 .name = "SS-600MP",
1420 .desc = "Sun4m platform, SPARCserver 600MP",
1421 .init = ss600mp_init,
1422 .use_scsi = 1,
1423 .max_cpus = 4,
1424 };
1425
1426 static QEMUMachine ss20_machine = {
1427 .name = "SS-20",
1428 .desc = "Sun4m platform, SPARCstation 20",
1429 .init = ss20_init,
1430 .use_scsi = 1,
1431 .max_cpus = 4,
1432 };
1433
1434 static QEMUMachine voyager_machine = {
1435 .name = "Voyager",
1436 .desc = "Sun4m platform, SPARCstation Voyager",
1437 .init = vger_init,
1438 .use_scsi = 1,
1439 };
1440
1441 static QEMUMachine ss_lx_machine = {
1442 .name = "LX",
1443 .desc = "Sun4m platform, SPARCstation LX",
1444 .init = ss_lx_init,
1445 .use_scsi = 1,
1446 };
1447
1448 static QEMUMachine ss4_machine = {
1449 .name = "SS-4",
1450 .desc = "Sun4m platform, SPARCstation 4",
1451 .init = ss4_init,
1452 .use_scsi = 1,
1453 };
1454
1455 static QEMUMachine scls_machine = {
1456 .name = "SPARCClassic",
1457 .desc = "Sun4m platform, SPARCClassic",
1458 .init = scls_init,
1459 .use_scsi = 1,
1460 };
1461
1462 static QEMUMachine sbook_machine = {
1463 .name = "SPARCbook",
1464 .desc = "Sun4m platform, SPARCbook",
1465 .init = sbook_init,
1466 .use_scsi = 1,
1467 };
1468
1469 static const struct sun4d_hwdef sun4d_hwdefs[] = {
1470 /* SS-1000 */
1471 {
1472 .iounit_bases = {
1473 0xfe0200000ULL,
1474 0xfe1200000ULL,
1475 0xfe2200000ULL,
1476 0xfe3200000ULL,
1477 -1,
1478 },
1479 .tcx_base = 0x820000000ULL,
1480 .slavio_base = 0xf00000000ULL,
1481 .ms_kb_base = 0xf00240000ULL,
1482 .serial_base = 0xf00200000ULL,
1483 .nvram_base = 0xf00280000ULL,
1484 .counter_base = 0xf00300000ULL,
1485 .espdma_base = 0x800081000ULL,
1486 .esp_base = 0x800080000ULL,
1487 .ledma_base = 0x800040000ULL,
1488 .le_base = 0x800060000ULL,
1489 .sbi_base = 0xf02800000ULL,
1490 .nvram_machine_id = 0x80,
1491 .machine_id = ss1000_id,
1492 .iounit_version = 0x03000000,
1493 .max_mem = 0xf00000000ULL,
1494 .default_cpu_model = "TI SuperSparc II",
1495 },
1496 /* SS-2000 */
1497 {
1498 .iounit_bases = {
1499 0xfe0200000ULL,
1500 0xfe1200000ULL,
1501 0xfe2200000ULL,
1502 0xfe3200000ULL,
1503 0xfe4200000ULL,
1504 },
1505 .tcx_base = 0x820000000ULL,
1506 .slavio_base = 0xf00000000ULL,
1507 .ms_kb_base = 0xf00240000ULL,
1508 .serial_base = 0xf00200000ULL,
1509 .nvram_base = 0xf00280000ULL,
1510 .counter_base = 0xf00300000ULL,
1511 .espdma_base = 0x800081000ULL,
1512 .esp_base = 0x800080000ULL,
1513 .ledma_base = 0x800040000ULL,
1514 .le_base = 0x800060000ULL,
1515 .sbi_base = 0xf02800000ULL,
1516 .nvram_machine_id = 0x80,
1517 .machine_id = ss2000_id,
1518 .iounit_version = 0x03000000,
1519 .max_mem = 0xf00000000ULL,
1520 .default_cpu_model = "TI SuperSparc II",
1521 },
1522 };
1523
1524 static DeviceState *sbi_init(target_phys_addr_t addr, qemu_irq **parent_irq)
1525 {
1526 DeviceState *dev;
1527 SysBusDevice *s;
1528 unsigned int i;
1529
1530 dev = qdev_create(NULL, "sbi");
1531 qdev_init_nofail(dev);
1532
1533 s = sysbus_from_qdev(dev);
1534
1535 for (i = 0; i < MAX_CPUS; i++) {
1536 sysbus_connect_irq(s, i, *parent_irq[i]);
1537 }
1538
1539 sysbus_mmio_map(s, 0, addr);
1540
1541 return dev;
1542 }
1543
1544 static void sun4d_hw_init(const struct sun4d_hwdef *hwdef, ram_addr_t RAM_size,
1545 const char *boot_device,
1546 const char *kernel_filename,
1547 const char *kernel_cmdline,
1548 const char *initrd_filename, const char *cpu_model)
1549 {
1550 unsigned int i;
1551 void *iounits[MAX_IOUNITS], *espdma, *ledma, *nvram;
1552 qemu_irq *cpu_irqs[MAX_CPUS], sbi_irq[32], sbi_cpu_irq[MAX_CPUS],
1553 espdma_irq, ledma_irq;
1554 qemu_irq esp_reset, dma_enable;
1555 unsigned long kernel_size;
1556 void *fw_cfg;
1557 DeviceState *dev;
1558
1559 /* init CPUs */
1560 if (!cpu_model)
1561 cpu_model = hwdef->default_cpu_model;
1562
1563 for(i = 0; i < smp_cpus; i++) {
1564 cpu_devinit(cpu_model, i, hwdef->slavio_base, &cpu_irqs[i]);
1565 }
1566
1567 for (i = smp_cpus; i < MAX_CPUS; i++)
1568 cpu_irqs[i] = qemu_allocate_irqs(dummy_cpu_set_irq, NULL, MAX_PILS);
1569
1570 /* set up devices */
1571 ram_init(0, RAM_size, hwdef->max_mem);
1572
1573 prom_init(hwdef->slavio_base, bios_name);
1574
1575 dev = sbi_init(hwdef->sbi_base, cpu_irqs);
1576
1577 for (i = 0; i < 32; i++) {
1578 sbi_irq[i] = qdev_get_gpio_in(dev, i);
1579 }
1580 for (i = 0; i < MAX_CPUS; i++) {
1581 sbi_cpu_irq[i] = qdev_get_gpio_in(dev, 32 + i);
1582 }
1583
1584 for (i = 0; i < MAX_IOUNITS; i++)
1585 if (hwdef->iounit_bases[i] != (target_phys_addr_t)-1)
1586 iounits[i] = iommu_init(hwdef->iounit_bases[i],
1587 hwdef->iounit_version,
1588 sbi_irq[0]);
1589
1590 espdma = sparc32_dma_init(hwdef->espdma_base, sbi_irq[3],
1591 iounits[0], &espdma_irq, 0);
1592
1593 /* should be lebuffer instead */
1594 ledma = sparc32_dma_init(hwdef->ledma_base, sbi_irq[4],
1595 iounits[0], &ledma_irq, 0);
1596
1597 if (graphic_depth != 8 && graphic_depth != 24) {
1598 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1599 exit (1);
1600 }
1601 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1602 graphic_depth);
1603
1604 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1605
1606 nvram = m48t59_init(sbi_irq[0], hwdef->nvram_base, 0, 0x2000, 8);
1607
1608 slavio_timer_init_all(hwdef->counter_base, sbi_irq[10], sbi_cpu_irq, smp_cpus);
1609
1610 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, sbi_irq[12],
1611 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1612 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1613 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1614 escc_init(hwdef->serial_base, sbi_irq[12], sbi_irq[12],
1615 serial_hds[0], serial_hds[1], ESCC_CLOCK, 1);
1616
1617 if (drive_get_max_bus(IF_SCSI) > 0) {
1618 fprintf(stderr, "qemu: too many SCSI bus\n");
1619 exit(1);
1620 }
1621
1622 esp_init(hwdef->esp_base, 2,
1623 espdma_memory_read, espdma_memory_write,
1624 espdma, espdma_irq, &esp_reset, &dma_enable);
1625
1626 qdev_connect_gpio_out(espdma, 0, esp_reset);
1627 qdev_connect_gpio_out(espdma, 1, dma_enable);
1628
1629 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1630 RAM_size);
1631
1632 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1633 boot_device, RAM_size, kernel_size, graphic_width,
1634 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1635 "Sun4d");
1636
1637 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1638 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1639 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1640 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1641 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1642 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1643 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1644 if (kernel_cmdline) {
1645 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1646 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1647 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1648 (uint8_t*)strdup(kernel_cmdline),
1649 strlen(kernel_cmdline) + 1);
1650 } else {
1651 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1652 }
1653 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1654 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1655 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1656 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1657 }
1658
1659 /* SPARCserver 1000 hardware initialisation */
1660 static void ss1000_init(ram_addr_t RAM_size,
1661 const char *boot_device,
1662 const char *kernel_filename, const char *kernel_cmdline,
1663 const char *initrd_filename, const char *cpu_model)
1664 {
1665 sun4d_hw_init(&sun4d_hwdefs[0], RAM_size, boot_device, kernel_filename,
1666 kernel_cmdline, initrd_filename, cpu_model);
1667 }
1668
1669 /* SPARCcenter 2000 hardware initialisation */
1670 static void ss2000_init(ram_addr_t RAM_size,
1671 const char *boot_device,
1672 const char *kernel_filename, const char *kernel_cmdline,
1673 const char *initrd_filename, const char *cpu_model)
1674 {
1675 sun4d_hw_init(&sun4d_hwdefs[1], RAM_size, boot_device, kernel_filename,
1676 kernel_cmdline, initrd_filename, cpu_model);
1677 }
1678
1679 static QEMUMachine ss1000_machine = {
1680 .name = "SS-1000",
1681 .desc = "Sun4d platform, SPARCserver 1000",
1682 .init = ss1000_init,
1683 .use_scsi = 1,
1684 .max_cpus = 8,
1685 };
1686
1687 static QEMUMachine ss2000_machine = {
1688 .name = "SS-2000",
1689 .desc = "Sun4d platform, SPARCcenter 2000",
1690 .init = ss2000_init,
1691 .use_scsi = 1,
1692 .max_cpus = 20,
1693 };
1694
1695 static const struct sun4c_hwdef sun4c_hwdefs[] = {
1696 /* SS-2 */
1697 {
1698 .iommu_base = 0xf8000000,
1699 .tcx_base = 0xfe000000,
1700 .slavio_base = 0xf6000000,
1701 .intctl_base = 0xf5000000,
1702 .counter_base = 0xf3000000,
1703 .ms_kb_base = 0xf0000000,
1704 .serial_base = 0xf1000000,
1705 .nvram_base = 0xf2000000,
1706 .fd_base = 0xf7200000,
1707 .dma_base = 0xf8400000,
1708 .esp_base = 0xf8800000,
1709 .le_base = 0xf8c00000,
1710 .aux1_base = 0xf7400003,
1711 .nvram_machine_id = 0x55,
1712 .machine_id = ss2_id,
1713 .max_mem = 0x10000000,
1714 .default_cpu_model = "Cypress CY7C601",
1715 },
1716 };
1717
1718 static DeviceState *sun4c_intctl_init(target_phys_addr_t addr,
1719 qemu_irq *parent_irq)
1720 {
1721 DeviceState *dev;
1722 SysBusDevice *s;
1723 unsigned int i;
1724
1725 dev = qdev_create(NULL, "sun4c_intctl");
1726 qdev_init_nofail(dev);
1727
1728 s = sysbus_from_qdev(dev);
1729
1730 for (i = 0; i < MAX_PILS; i++) {
1731 sysbus_connect_irq(s, i, parent_irq[i]);
1732 }
1733 sysbus_mmio_map(s, 0, addr);
1734
1735 return dev;
1736 }
1737
1738 static void sun4c_hw_init(const struct sun4c_hwdef *hwdef, ram_addr_t RAM_size,
1739 const char *boot_device,
1740 const char *kernel_filename,
1741 const char *kernel_cmdline,
1742 const char *initrd_filename, const char *cpu_model)
1743 {
1744 void *iommu, *espdma, *ledma, *nvram;
1745 qemu_irq *cpu_irqs, slavio_irq[8], espdma_irq, ledma_irq;
1746 qemu_irq esp_reset, dma_enable;
1747 qemu_irq fdc_tc;
1748 unsigned long kernel_size;
1749 DriveInfo *fd[MAX_FD];
1750 void *fw_cfg;
1751 DeviceState *dev;
1752 unsigned int i;
1753
1754 /* init CPU */
1755 if (!cpu_model)
1756 cpu_model = hwdef->default_cpu_model;
1757
1758 cpu_devinit(cpu_model, 0, hwdef->slavio_base, &cpu_irqs);
1759
1760 /* set up devices */
1761 ram_init(0, RAM_size, hwdef->max_mem);
1762
1763 prom_init(hwdef->slavio_base, bios_name);
1764
1765 dev = sun4c_intctl_init(hwdef->intctl_base, cpu_irqs);
1766
1767 for (i = 0; i < 8; i++) {
1768 slavio_irq[i] = qdev_get_gpio_in(dev, i);
1769 }
1770
1771 iommu = iommu_init(hwdef->iommu_base, hwdef->iommu_version,
1772 slavio_irq[1]);
1773
1774 espdma = sparc32_dma_init(hwdef->dma_base, slavio_irq[2],
1775 iommu, &espdma_irq, 0);
1776
1777 ledma = sparc32_dma_init(hwdef->dma_base + 16ULL,
1778 slavio_irq[3], iommu, &ledma_irq, 1);
1779
1780 if (graphic_depth != 8 && graphic_depth != 24) {
1781 fprintf(stderr, "qemu: Unsupported depth: %d\n", graphic_depth);
1782 exit (1);
1783 }
1784 tcx_init(hwdef->tcx_base, 0x00100000, graphic_width, graphic_height,
1785 graphic_depth);
1786
1787 lance_init(&nd_table[0], hwdef->le_base, ledma, ledma_irq);
1788
1789 nvram = m48t59_init(slavio_irq[0], hwdef->nvram_base, 0, 0x800, 2);
1790
1791 slavio_serial_ms_kbd_init(hwdef->ms_kb_base, slavio_irq[1],
1792 display_type == DT_NOGRAPHIC, ESCC_CLOCK, 1);
1793 // Slavio TTYA (base+4, Linux ttyS0) is the first Qemu serial device
1794 // Slavio TTYB (base+0, Linux ttyS1) is the second Qemu serial device
1795 escc_init(hwdef->serial_base, slavio_irq[1],
1796 slavio_irq[1], serial_hds[0], serial_hds[1],
1797 ESCC_CLOCK, 1);
1798
1799 slavio_misc_init(0, hwdef->aux1_base, 0, slavio_irq[1], fdc_tc);
1800
1801 if (hwdef->fd_base != (target_phys_addr_t)-1) {
1802 /* there is zero or one floppy drive */
1803 memset(fd, 0, sizeof(fd));
1804 fd[0] = drive_get(IF_FLOPPY, 0, 0);
1805 sun4m_fdctrl_init(slavio_irq[1], hwdef->fd_base, fd,
1806 &fdc_tc);
1807 }
1808
1809 if (drive_get_max_bus(IF_SCSI) > 0) {
1810 fprintf(stderr, "qemu: too many SCSI bus\n");
1811 exit(1);
1812 }
1813
1814 esp_init(hwdef->esp_base, 2,
1815 espdma_memory_read, espdma_memory_write,
1816 espdma, espdma_irq, &esp_reset, &dma_enable);
1817
1818 qdev_connect_gpio_out(espdma, 0, esp_reset);
1819 qdev_connect_gpio_out(espdma, 1, dma_enable);
1820
1821 kernel_size = sun4m_load_kernel(kernel_filename, initrd_filename,
1822 RAM_size);
1823
1824 nvram_init(nvram, (uint8_t *)&nd_table[0].macaddr, kernel_cmdline,
1825 boot_device, RAM_size, kernel_size, graphic_width,
1826 graphic_height, graphic_depth, hwdef->nvram_machine_id,
1827 "Sun4c");
1828
1829 fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2);
1830 fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1);
1831 fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size);
1832 fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, hwdef->machine_id);
1833 fw_cfg_add_i16(fw_cfg, FW_CFG_SUN4M_DEPTH, graphic_depth);
1834 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, KERNEL_LOAD_ADDR);
1835 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size);
1836 if (kernel_cmdline) {
1837 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, CMDLINE_ADDR);
1838 pstrcpy_targphys("cmdline", CMDLINE_ADDR, TARGET_PAGE_SIZE, kernel_cmdline);
1839 fw_cfg_add_bytes(fw_cfg, FW_CFG_CMDLINE_DATA,
1840 (uint8_t*)strdup(kernel_cmdline),
1841 strlen(kernel_cmdline) + 1);
1842 } else {
1843 fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_CMDLINE, 0);
1844 }
1845 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_ADDR, INITRD_LOAD_ADDR);
1846 fw_cfg_add_i32(fw_cfg, FW_CFG_INITRD_SIZE, 0); // not used
1847 fw_cfg_add_i16(fw_cfg, FW_CFG_BOOT_DEVICE, boot_device[0]);
1848 qemu_register_boot_set(fw_cfg_boot_set, fw_cfg);
1849 }
1850
1851 /* SPARCstation 2 hardware initialisation */
1852 static void ss2_init(ram_addr_t RAM_size,
1853 const char *boot_device,
1854 const char *kernel_filename, const char *kernel_cmdline,
1855 const char *initrd_filename, const char *cpu_model)
1856 {
1857 sun4c_hw_init(&sun4c_hwdefs[0], RAM_size, boot_device, kernel_filename,
1858 kernel_cmdline, initrd_filename, cpu_model);
1859 }
1860
1861 static QEMUMachine ss2_machine = {
1862 .name = "SS-2",
1863 .desc = "Sun4c platform, SPARCstation 2",
1864 .init = ss2_init,
1865 .use_scsi = 1,
1866 };
1867
1868 static void ss2_machine_init(void)
1869 {
1870 qemu_register_machine(&ss5_machine);
1871 qemu_register_machine(&ss10_machine);
1872 qemu_register_machine(&ss600mp_machine);
1873 qemu_register_machine(&ss20_machine);
1874 qemu_register_machine(&voyager_machine);
1875 qemu_register_machine(&ss_lx_machine);
1876 qemu_register_machine(&ss4_machine);
1877 qemu_register_machine(&scls_machine);
1878 qemu_register_machine(&sbook_machine);
1879 qemu_register_machine(&ss1000_machine);
1880 qemu_register_machine(&ss2000_machine);
1881 qemu_register_machine(&ss2_machine);
1882 }
1883
1884 machine_init(ss2_machine_init);
QEMU modified to work with kvm