hw/apic_common.c

   1 /*
   2  *  APIC support - common bits of emulated and KVM kernel model
   3  *
   4  *  Copyright (c) 2004-2005 Fabrice Bellard
   5  *  Copyright (c) 2011      Jan Kiszka, Siemens AG
   6  *
   7  * This library is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU Lesser General Public
   9  * License as published by the Free Software Foundation; either
  10  * version 2 of the License, or (at your option) any later version.
  11  *
  12  * This library is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  15  * Lesser General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU Lesser General Public
  18  * License along with this library; if not, see <http://www.gnu.org/licenses/>
  19  */
  20 #include "apic.h"
  21 #include "apic_internal.h"
  22 #include "trace.h"
  23
  24 static int apic_irq_delivered;
  25
  26 void cpu_set_apic_base(DeviceState *d, uint64_t val)
  27 {
  28     trace_cpu_set_apic_base(val);
  29
  30     if (d) {
  31         APICCommonState *s = APIC_COMMON(d);
  32         APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
  33         info->set_base(s, val);
  34     }
  35 }
  36
  37 uint64_t cpu_get_apic_base(DeviceState *d)
  38 {
  39     if (d) {
  40         APICCommonState *s = APIC_COMMON(d);
  41         trace_cpu_get_apic_base((uint64_t)s->apicbase);
  42         return s->apicbase;
  43     } else {
  44         trace_cpu_get_apic_base(0);
  45         return 0;
  46     }
  47 }
  48
  49 void cpu_set_apic_tpr(DeviceState *d, uint8_t val)
  50 {
  51     APICCommonState *s;
  52     APICCommonClass *info;
  53
  54     if (!d) {
  55         return;
  56     }
  57
  58     s = APIC_COMMON(d);
  59     info = APIC_COMMON_GET_CLASS(s);
  60
  61     info->set_tpr(s, val);
  62 }
  63
  64 uint8_t cpu_get_apic_tpr(DeviceState *d)
  65 {
  66     APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
  67
  68     return s ? s->tpr >> 4 : 0;
  69 }
  70
  71 void apic_report_irq_delivered(int delivered)
  72 {
  73     apic_irq_delivered += delivered;
  74
  75     trace_apic_report_irq_delivered(apic_irq_delivered);
  76 }
  77
  78 void apic_reset_irq_delivered(void)
  79 {
  80     trace_apic_reset_irq_delivered(apic_irq_delivered);
  81
  82     apic_irq_delivered = 0;
  83 }
  84
  85 int apic_get_irq_delivered(void)
  86 {
  87     trace_apic_get_irq_delivered(apic_irq_delivered);
  88
  89     return apic_irq_delivered;
  90 }
  91
  92 void apic_deliver_nmi(DeviceState *d)
  93 {
  94     APICCommonState *s = APIC_COMMON(d);
  95     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
  96
  97     info->external_nmi(s);
  98 }
  99
 100 bool apic_next_timer(APICCommonState *s, int64_t current_time)
 101 {
 102     int64_t d;
 103
 104     /* We need to store the timer state separately to support APIC
 105      * implementations that maintain a non-QEMU timer, e.g. inside the
 106      * host kernel. This open-coded state allows us to migrate between
 107      * both models. */
 108     s->timer_expiry = -1;
 109
 110     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_MASKED) {
 111         return false;
 112     }
 113
 114     d = (current_time - s->initial_count_load_time) >> s->count_shift;
 115
 116     if (s->lvt[APIC_LVT_TIMER] & APIC_LVT_TIMER_PERIODIC) {
 117         if (!s->initial_count) {
 118             return false;
 119         }
 120         d = ((d / ((uint64_t)s->initial_count + 1)) + 1) *
 121             ((uint64_t)s->initial_count + 1);
 122     } else {
 123         if (d >= s->initial_count) {
 124             return false;
 125         }
 126         d = (uint64_t)s->initial_count + 1;
 127     }
 128     s->next_time = s->initial_count_load_time + (d << s->count_shift);
 129     s->timer_expiry = s->next_time;
 130     return true;
 131 }
 132
 133 void apic_init_reset(DeviceState *d)
 134 {
 135     APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
 136     int i;
 137
 138     if (!s) {
 139         return;
 140     }
 141     s->tpr = 0;
 142     s->spurious_vec = 0xff;
 143     s->log_dest = 0;
 144     s->dest_mode = 0xf;
 145     memset(s->isr, 0, sizeof(s->isr));
 146     memset(s->tmr, 0, sizeof(s->tmr));
 147     memset(s->irr, 0, sizeof(s->irr));
 148     for (i = 0; i < APIC_LVT_NB; i++) {
 149         s->lvt[i] = APIC_LVT_MASKED;
 150     }
 151     s->esr = 0;
 152     memset(s->icr, 0, sizeof(s->icr));
 153     s->divide_conf = 0;
 154     s->count_shift = 0;
 155     s->initial_count = 0;
 156     s->initial_count_load_time = 0;
 157     s->next_time = 0;
 158     s->wait_for_sipi = 1;
 159
 160     if (s->timer) {
 161         qemu_del_timer(s->timer);
 162     }
 163     s->timer_expiry = -1;
 164 }
 165
 166 static void apic_reset_common(DeviceState *d)
 167 {
 168     APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d);
 169     bool bsp;
 170
 171     bsp = cpu_is_bsp(s->cpu_env);
 172     s->apicbase = 0xfee00000 |
 173         (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE;
 174
 175     apic_init_reset(d);
 176
 177     if (bsp) {
 178         /*
 179          * LINT0 delivery mode on CPU #0 is set to ExtInt at initialization
 180          * time typically by BIOS, so PIC interrupt can be delivered to the
 181          * processor when local APIC is enabled.
 182          */
 183         s->lvt[APIC_LVT_LINT0] = 0x700;
 184     }
 185 }
 186
 187 /* This function is only used for old state version 1 and 2 */
 188 static int apic_load_old(QEMUFile *f, void *opaque, int version_id)
 189 {
 190     APICCommonState *s = opaque;
 191     int i;
 192
 193     if (version_id > 2) {
 194         return -EINVAL;
 195     }
 196
 197     /* XXX: what if the base changes? (registered memory regions) */
 198     qemu_get_be32s(f, &s->apicbase);
 199     qemu_get_8s(f, &s->id);
 200     qemu_get_8s(f, &s->arb_id);
 201     qemu_get_8s(f, &s->tpr);
 202     qemu_get_be32s(f, &s->spurious_vec);
 203     qemu_get_8s(f, &s->log_dest);
 204     qemu_get_8s(f, &s->dest_mode);
 205     for (i = 0; i < 8; i++) {
 206         qemu_get_be32s(f, &s->isr[i]);
 207         qemu_get_be32s(f, &s->tmr[i]);
 208         qemu_get_be32s(f, &s->irr[i]);
 209     }
 210     for (i = 0; i < APIC_LVT_NB; i++) {
 211         qemu_get_be32s(f, &s->lvt[i]);
 212     }
 213     qemu_get_be32s(f, &s->esr);
 214     qemu_get_be32s(f, &s->icr[0]);
 215     qemu_get_be32s(f, &s->icr[1]);
 216     qemu_get_be32s(f, &s->divide_conf);
 217     s->count_shift = qemu_get_be32(f);
 218     qemu_get_be32s(f, &s->initial_count);
 219     s->initial_count_load_time = qemu_get_be64(f);
 220     s->next_time = qemu_get_be64(f);
 221
 222     if (version_id >= 2) {
 223         qemu_get_timer(f, s->timer);
 224     }
 225     return 0;
 226 }
 227
 228 static int apic_init_common(SysBusDevice *dev)
 229 {
 230     APICCommonState *s = APIC_COMMON(dev);
 231     APICCommonClass *info;
 232     static int apic_no;
 233
 234     if (apic_no >= MAX_APICS) {
 235         return -1;
 236     }
 237     s->idx = apic_no++;
 238
 239     info = APIC_COMMON_GET_CLASS(s);
 240     info->init(s);
 241
 242     sysbus_init_mmio(&s->busdev, &s->io_memory);
 243     return 0;
 244 }
 245
 246 static int apic_dispatch_post_load(void *opaque, int version_id)
 247 {
 248     APICCommonState *s = APIC_COMMON(opaque);
 249     APICCommonClass *info = APIC_COMMON_GET_CLASS(s);
 250
 251     if (info->post_load) {
 252         info->post_load(s);
 253     }
 254     return 0;
 255 }
 256
 257 static const VMStateDescription vmstate_apic_common = {
 258     .name = "apic",
 259     .version_id = 3,
 260     .minimum_version_id = 3,
 261     .minimum_version_id_old = 1,
 262     .load_state_old = apic_load_old,
 263     .post_load = apic_dispatch_post_load,
 264     .fields = (VMStateField[]) {
 265         VMSTATE_UINT32(apicbase, APICCommonState),
 266         VMSTATE_UINT8(id, APICCommonState),
 267         VMSTATE_UINT8(arb_id, APICCommonState),
 268         VMSTATE_UINT8(tpr, APICCommonState),
 269         VMSTATE_UINT32(spurious_vec, APICCommonState),
 270         VMSTATE_UINT8(log_dest, APICCommonState),
 271         VMSTATE_UINT8(dest_mode, APICCommonState),
 272         VMSTATE_UINT32_ARRAY(isr, APICCommonState, 8),
 273         VMSTATE_UINT32_ARRAY(tmr, APICCommonState, 8),
 274         VMSTATE_UINT32_ARRAY(irr, APICCommonState, 8),
 275         VMSTATE_UINT32_ARRAY(lvt, APICCommonState, APIC_LVT_NB),
 276         VMSTATE_UINT32(esr, APICCommonState),
 277         VMSTATE_UINT32_ARRAY(icr, APICCommonState, 2),
 278         VMSTATE_UINT32(divide_conf, APICCommonState),
 279         VMSTATE_INT32(count_shift, APICCommonState),
 280         VMSTATE_UINT32(initial_count, APICCommonState),
 281         VMSTATE_INT64(initial_count_load_time, APICCommonState),
 282         VMSTATE_INT64(next_time, APICCommonState),
 283         VMSTATE_INT64(timer_expiry,
 284                       APICCommonState), /* open-coded timer state */
 285         VMSTATE_END_OF_LIST()
 286     }
 287 };
 288
 289 static Property apic_properties_common[] = {
 290     DEFINE_PROP_UINT8("id", APICCommonState, id, -1),
 291     DEFINE_PROP_PTR("cpu_env", APICCommonState, cpu_env),
 292     DEFINE_PROP_END_OF_LIST(),
 293 };
 294
 295 static void apic_common_class_init(ObjectClass *klass, void *data)
 296 {
 297     SysBusDeviceClass *sc = SYS_BUS_DEVICE_CLASS(klass);
 298     DeviceClass *dc = DEVICE_CLASS(klass);
 299
 300     dc->vmsd = &vmstate_apic_common;
 301     dc->reset = apic_reset_common;
 302     dc->no_user = 1;
 303     dc->props = apic_properties_common;
 304     sc->init = apic_init_common;
 305 }
 306
 307 static TypeInfo apic_common_type = {
 308     .name = TYPE_APIC_COMMON,
 309     .parent = TYPE_SYS_BUS_DEVICE,
 310     .instance_size = sizeof(APICCommonState),
 311     .class_size = sizeof(APICCommonClass),
 312     .class_init = apic_common_class_init,
 313     .abstract = true,
 314 };
 315
 316 static void register_devices(void)
 317 {
 318     type_register_static(&apic_common_type);
 319 }
 320
 321 device_init(register_devices);