Merge remote-tracking branch 'afaerber-or/qom-next-2' into staging
[qemu-kvm.git] / hw / pci.c
blobbdfb3d6540ee654e4ddc0711912b88feab2c5b4f
1 /*
2 * QEMU PCI bus manager
4 * Copyright (c) 2004 Fabrice Bellard
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
24 #include "hw.h"
25 #include "pci.h"
26 #include "pci_bridge.h"
27 #include "pci_internals.h"
28 #include "monitor.h"
29 #include "net.h"
30 #include "sysemu.h"
31 #include "loader.h"
32 #include "range.h"
33 #include "qmp-commands.h"
34 #include "msi.h"
35 #include "msix.h"
37 //#define DEBUG_PCI
38 #ifdef DEBUG_PCI
39 # define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
40 #else
41 # define PCI_DPRINTF(format, ...) do { } while (0)
42 #endif
44 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
45 static char *pcibus_get_dev_path(DeviceState *dev);
46 static char *pcibus_get_fw_dev_path(DeviceState *dev);
47 static int pcibus_reset(BusState *qbus);
49 static Property pci_props[] = {
50 DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
51 DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
52 DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
53 DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
54 QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
55 DEFINE_PROP_BIT("command_serr_enable", PCIDevice, cap_present,
56 QEMU_PCI_CAP_SERR_BITNR, true),
57 DEFINE_PROP_END_OF_LIST()
60 static void pci_bus_class_init(ObjectClass *klass, void *data)
62 BusClass *k = BUS_CLASS(klass);
64 k->print_dev = pcibus_dev_print;
65 k->get_dev_path = pcibus_get_dev_path;
66 k->get_fw_dev_path = pcibus_get_fw_dev_path;
67 k->reset = pcibus_reset;
70 static const TypeInfo pci_bus_info = {
71 .name = TYPE_PCI_BUS,
72 .parent = TYPE_BUS,
73 .instance_size = sizeof(PCIBus),
74 .class_init = pci_bus_class_init,
77 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num);
78 static void pci_update_mappings(PCIDevice *d);
79 static void pci_set_irq(void *opaque, int irq_num, int level);
80 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom);
81 static void pci_del_option_rom(PCIDevice *pdev);
83 static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
84 static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
86 struct PCIHostBus {
87 int domain;
88 struct PCIBus *bus;
89 QLIST_ENTRY(PCIHostBus) next;
91 static QLIST_HEAD(, PCIHostBus) host_buses;
93 static const VMStateDescription vmstate_pcibus = {
94 .name = "PCIBUS",
95 .version_id = 1,
96 .minimum_version_id = 1,
97 .minimum_version_id_old = 1,
98 .fields = (VMStateField []) {
99 VMSTATE_INT32_EQUAL(nirq, PCIBus),
100 VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
101 VMSTATE_END_OF_LIST()
104 static int pci_bar(PCIDevice *d, int reg)
106 uint8_t type;
108 if (reg != PCI_ROM_SLOT)
109 return PCI_BASE_ADDRESS_0 + reg * 4;
111 type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
112 return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
115 static inline int pci_irq_state(PCIDevice *d, int irq_num)
117 return (d->irq_state >> irq_num) & 0x1;
120 static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
122 d->irq_state &= ~(0x1 << irq_num);
123 d->irq_state |= level << irq_num;
126 static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
128 PCIBus *bus;
129 for (;;) {
130 bus = pci_dev->bus;
131 irq_num = bus->map_irq(pci_dev, irq_num);
132 if (bus->set_irq)
133 break;
134 pci_dev = bus->parent_dev;
136 bus->irq_count[irq_num] += change;
137 bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
140 int pci_bus_get_irq_level(PCIBus *bus, int irq_num)
142 assert(irq_num >= 0);
143 assert(irq_num < bus->nirq);
144 return !!bus->irq_count[irq_num];
147 /* Update interrupt status bit in config space on interrupt
148 * state change. */
149 static void pci_update_irq_status(PCIDevice *dev)
151 if (dev->irq_state) {
152 dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
153 } else {
154 dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
158 void pci_device_deassert_intx(PCIDevice *dev)
160 int i;
161 for (i = 0; i < PCI_NUM_PINS; ++i) {
162 qemu_set_irq(dev->irq[i], 0);
167 * This function is called on #RST and FLR.
168 * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
170 void pci_device_reset(PCIDevice *dev)
172 int r;
174 qdev_reset_all(&dev->qdev);
176 dev->irq_state = 0;
177 pci_update_irq_status(dev);
178 pci_device_deassert_intx(dev);
179 /* Clear all writable bits */
180 pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
181 pci_get_word(dev->wmask + PCI_COMMAND) |
182 pci_get_word(dev->w1cmask + PCI_COMMAND));
183 pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
184 pci_get_word(dev->wmask + PCI_STATUS) |
185 pci_get_word(dev->w1cmask + PCI_STATUS));
186 dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
187 dev->config[PCI_INTERRUPT_LINE] = 0x0;
188 for (r = 0; r < PCI_NUM_REGIONS; ++r) {
189 PCIIORegion *region = &dev->io_regions[r];
190 if (!region->size) {
191 continue;
194 if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
195 region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
196 pci_set_quad(dev->config + pci_bar(dev, r), region->type);
197 } else {
198 pci_set_long(dev->config + pci_bar(dev, r), region->type);
201 pci_update_mappings(dev);
203 msi_reset(dev);
204 msix_reset(dev);
208 * Trigger pci bus reset under a given bus.
209 * To be called on RST# assert.
211 void pci_bus_reset(PCIBus *bus)
213 int i;
215 for (i = 0; i < bus->nirq; i++) {
216 bus->irq_count[i] = 0;
218 for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
219 if (bus->devices[i]) {
220 pci_device_reset(bus->devices[i]);
225 static int pcibus_reset(BusState *qbus)
227 pci_bus_reset(DO_UPCAST(PCIBus, qbus, qbus));
229 /* topology traverse is done by pci_bus_reset().
230 Tell qbus/qdev walker not to traverse the tree */
231 return 1;
234 static void pci_host_bus_register(int domain, PCIBus *bus)
236 struct PCIHostBus *host;
237 host = g_malloc0(sizeof(*host));
238 host->domain = domain;
239 host->bus = bus;
240 QLIST_INSERT_HEAD(&host_buses, host, next);
243 PCIBus *pci_find_root_bus(int domain)
245 struct PCIHostBus *host;
247 QLIST_FOREACH(host, &host_buses, next) {
248 if (host->domain == domain) {
249 return host->bus;
253 return NULL;
256 int pci_find_domain(const PCIBus *bus)
258 PCIDevice *d;
259 struct PCIHostBus *host;
261 /* obtain root bus */
262 while ((d = bus->parent_dev) != NULL) {
263 bus = d->bus;
266 QLIST_FOREACH(host, &host_buses, next) {
267 if (host->bus == bus) {
268 return host->domain;
272 abort(); /* should not be reached */
273 return -1;
276 void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
277 const char *name,
278 MemoryRegion *address_space_mem,
279 MemoryRegion *address_space_io,
280 uint8_t devfn_min)
282 qbus_create_inplace(&bus->qbus, TYPE_PCI_BUS, parent, name);
283 assert(PCI_FUNC(devfn_min) == 0);
284 bus->devfn_min = devfn_min;
285 bus->address_space_mem = address_space_mem;
286 bus->address_space_io = address_space_io;
288 /* host bridge */
289 QLIST_INIT(&bus->child);
290 pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
292 vmstate_register(NULL, -1, &vmstate_pcibus, bus);
295 PCIBus *pci_bus_new(DeviceState *parent, const char *name,
296 MemoryRegion *address_space_mem,
297 MemoryRegion *address_space_io,
298 uint8_t devfn_min)
300 PCIBus *bus;
302 bus = g_malloc0(sizeof(*bus));
303 bus->qbus.glib_allocated = true;
304 pci_bus_new_inplace(bus, parent, name, address_space_mem,
305 address_space_io, devfn_min);
306 return bus;
309 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
310 void *irq_opaque, int nirq)
312 bus->set_irq = set_irq;
313 bus->map_irq = map_irq;
314 bus->irq_opaque = irq_opaque;
315 bus->nirq = nirq;
316 bus->irq_count = g_malloc0(nirq * sizeof(bus->irq_count[0]));
319 void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
321 bus->qbus.allow_hotplug = 1;
322 bus->hotplug = hotplug;
323 bus->hotplug_qdev = qdev;
326 PCIBus *pci_register_bus(DeviceState *parent, const char *name,
327 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
328 void *irq_opaque,
329 MemoryRegion *address_space_mem,
330 MemoryRegion *address_space_io,
331 uint8_t devfn_min, int nirq)
333 PCIBus *bus;
335 bus = pci_bus_new(parent, name, address_space_mem,
336 address_space_io, devfn_min);
337 pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
338 return bus;
341 int pci_bus_num(PCIBus *s)
343 if (!s->parent_dev)
344 return 0; /* pci host bridge */
345 return s->parent_dev->config[PCI_SECONDARY_BUS];
348 static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
350 PCIDevice *s = container_of(pv, PCIDevice, config);
351 uint8_t *config;
352 int i;
354 assert(size == pci_config_size(s));
355 config = g_malloc(size);
357 qemu_get_buffer(f, config, size);
358 for (i = 0; i < size; ++i) {
359 if ((config[i] ^ s->config[i]) &
360 s->cmask[i] & ~s->wmask[i] & ~s->w1cmask[i]) {
361 g_free(config);
362 return -EINVAL;
365 memcpy(s->config, config, size);
367 pci_update_mappings(s);
369 g_free(config);
370 return 0;
373 /* just put buffer */
374 static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
376 const uint8_t **v = pv;
377 assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
378 qemu_put_buffer(f, *v, size);
381 static VMStateInfo vmstate_info_pci_config = {
382 .name = "pci config",
383 .get = get_pci_config_device,
384 .put = put_pci_config_device,
387 static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
389 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
390 uint32_t irq_state[PCI_NUM_PINS];
391 int i;
392 for (i = 0; i < PCI_NUM_PINS; ++i) {
393 irq_state[i] = qemu_get_be32(f);
394 if (irq_state[i] != 0x1 && irq_state[i] != 0) {
395 fprintf(stderr, "irq state %d: must be 0 or 1.\n",
396 irq_state[i]);
397 return -EINVAL;
401 for (i = 0; i < PCI_NUM_PINS; ++i) {
402 pci_set_irq_state(s, i, irq_state[i]);
405 return 0;
408 static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
410 int i;
411 PCIDevice *s = container_of(pv, PCIDevice, irq_state);
413 for (i = 0; i < PCI_NUM_PINS; ++i) {
414 qemu_put_be32(f, pci_irq_state(s, i));
418 static VMStateInfo vmstate_info_pci_irq_state = {
419 .name = "pci irq state",
420 .get = get_pci_irq_state,
421 .put = put_pci_irq_state,
424 const VMStateDescription vmstate_pci_device = {
425 .name = "PCIDevice",
426 .version_id = 2,
427 .minimum_version_id = 1,
428 .minimum_version_id_old = 1,
429 .fields = (VMStateField []) {
430 VMSTATE_INT32_LE(version_id, PCIDevice),
431 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
432 vmstate_info_pci_config,
433 PCI_CONFIG_SPACE_SIZE),
434 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
435 vmstate_info_pci_irq_state,
436 PCI_NUM_PINS * sizeof(int32_t)),
437 VMSTATE_END_OF_LIST()
441 const VMStateDescription vmstate_pcie_device = {
442 .name = "PCIDevice",
443 .version_id = 2,
444 .minimum_version_id = 1,
445 .minimum_version_id_old = 1,
446 .fields = (VMStateField []) {
447 VMSTATE_INT32_LE(version_id, PCIDevice),
448 VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
449 vmstate_info_pci_config,
450 PCIE_CONFIG_SPACE_SIZE),
451 VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
452 vmstate_info_pci_irq_state,
453 PCI_NUM_PINS * sizeof(int32_t)),
454 VMSTATE_END_OF_LIST()
458 static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
460 return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
463 void pci_device_save(PCIDevice *s, QEMUFile *f)
465 /* Clear interrupt status bit: it is implicit
466 * in irq_state which we are saving.
467 * This makes us compatible with old devices
468 * which never set or clear this bit. */
469 s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
470 vmstate_save_state(f, pci_get_vmstate(s), s);
471 /* Restore the interrupt status bit. */
472 pci_update_irq_status(s);
475 int pci_device_load(PCIDevice *s, QEMUFile *f)
477 int ret;
478 ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
479 /* Restore the interrupt status bit. */
480 pci_update_irq_status(s);
481 return ret;
484 static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
486 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
487 pci_default_sub_vendor_id);
488 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
489 pci_default_sub_device_id);
493 * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
494 * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
496 static int pci_parse_devaddr(const char *addr, int *domp, int *busp,
497 unsigned int *slotp, unsigned int *funcp)
499 const char *p;
500 char *e;
501 unsigned long val;
502 unsigned long dom = 0, bus = 0;
503 unsigned int slot = 0;
504 unsigned int func = 0;
506 p = addr;
507 val = strtoul(p, &e, 16);
508 if (e == p)
509 return -1;
510 if (*e == ':') {
511 bus = val;
512 p = e + 1;
513 val = strtoul(p, &e, 16);
514 if (e == p)
515 return -1;
516 if (*e == ':') {
517 dom = bus;
518 bus = val;
519 p = e + 1;
520 val = strtoul(p, &e, 16);
521 if (e == p)
522 return -1;
526 slot = val;
528 if (funcp != NULL) {
529 if (*e != '.')
530 return -1;
532 p = e + 1;
533 val = strtoul(p, &e, 16);
534 if (e == p)
535 return -1;
537 func = val;
540 /* if funcp == NULL func is 0 */
541 if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
542 return -1;
544 if (*e)
545 return -1;
547 *domp = dom;
548 *busp = bus;
549 *slotp = slot;
550 if (funcp != NULL)
551 *funcp = func;
552 return 0;
555 int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
556 unsigned *slotp)
558 /* strip legacy tag */
559 if (!strncmp(addr, "pci_addr=", 9)) {
560 addr += 9;
562 if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) {
563 monitor_printf(mon, "Invalid pci address\n");
564 return -1;
566 return 0;
569 PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
571 int dom, bus;
572 unsigned slot;
574 if (!devaddr) {
575 *devfnp = -1;
576 return pci_find_bus_nr(pci_find_root_bus(0), 0);
579 if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
580 return NULL;
583 *devfnp = PCI_DEVFN(slot, 0);
584 return pci_find_bus_nr(pci_find_root_bus(dom), bus);
587 static void pci_init_cmask(PCIDevice *dev)
589 pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
590 pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
591 dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
592 dev->cmask[PCI_REVISION_ID] = 0xff;
593 dev->cmask[PCI_CLASS_PROG] = 0xff;
594 pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
595 dev->cmask[PCI_HEADER_TYPE] = 0xff;
596 dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
599 static void pci_init_wmask(PCIDevice *dev)
601 int config_size = pci_config_size(dev);
603 dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
604 dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
605 pci_set_word(dev->wmask + PCI_COMMAND,
606 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
607 PCI_COMMAND_INTX_DISABLE);
608 if (dev->cap_present & QEMU_PCI_CAP_SERR) {
609 pci_word_test_and_set_mask(dev->wmask + PCI_COMMAND, PCI_COMMAND_SERR);
612 memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
613 config_size - PCI_CONFIG_HEADER_SIZE);
616 static void pci_init_w1cmask(PCIDevice *dev)
619 * Note: It's okay to set w1cmask even for readonly bits as
620 * long as their value is hardwired to 0.
622 pci_set_word(dev->w1cmask + PCI_STATUS,
623 PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
624 PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
625 PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
628 static void pci_init_mask_bridge(PCIDevice *d)
630 /* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
631 PCI_SEC_LETENCY_TIMER */
632 memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
634 /* base and limit */
635 d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
636 d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
637 pci_set_word(d->wmask + PCI_MEMORY_BASE,
638 PCI_MEMORY_RANGE_MASK & 0xffff);
639 pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
640 PCI_MEMORY_RANGE_MASK & 0xffff);
641 pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
642 PCI_PREF_RANGE_MASK & 0xffff);
643 pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
644 PCI_PREF_RANGE_MASK & 0xffff);
646 /* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
647 memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
649 /* Supported memory and i/o types */
650 d->config[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_16;
651 d->config[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_16;
652 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_BASE,
653 PCI_PREF_RANGE_TYPE_64);
654 pci_word_test_and_set_mask(d->config + PCI_PREF_MEMORY_LIMIT,
655 PCI_PREF_RANGE_TYPE_64);
657 /* TODO: add this define to pci_regs.h in linux and then in qemu. */
658 #define PCI_BRIDGE_CTL_VGA_16BIT 0x10 /* VGA 16-bit decode */
659 #define PCI_BRIDGE_CTL_DISCARD 0x100 /* Primary discard timer */
660 #define PCI_BRIDGE_CTL_SEC_DISCARD 0x200 /* Secondary discard timer */
661 #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */
662 #define PCI_BRIDGE_CTL_DISCARD_SERR 0x800 /* Discard timer SERR# enable */
663 pci_set_word(d->wmask + PCI_BRIDGE_CONTROL,
664 PCI_BRIDGE_CTL_PARITY |
665 PCI_BRIDGE_CTL_SERR |
666 PCI_BRIDGE_CTL_ISA |
667 PCI_BRIDGE_CTL_VGA |
668 PCI_BRIDGE_CTL_VGA_16BIT |
669 PCI_BRIDGE_CTL_MASTER_ABORT |
670 PCI_BRIDGE_CTL_BUS_RESET |
671 PCI_BRIDGE_CTL_FAST_BACK |
672 PCI_BRIDGE_CTL_DISCARD |
673 PCI_BRIDGE_CTL_SEC_DISCARD |
674 PCI_BRIDGE_CTL_DISCARD_SERR);
675 /* Below does not do anything as we never set this bit, put here for
676 * completeness. */
677 pci_set_word(d->w1cmask + PCI_BRIDGE_CONTROL,
678 PCI_BRIDGE_CTL_DISCARD_STATUS);
679 d->cmask[PCI_IO_BASE] |= PCI_IO_RANGE_TYPE_MASK;
680 d->cmask[PCI_IO_LIMIT] |= PCI_IO_RANGE_TYPE_MASK;
681 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_BASE,
682 PCI_PREF_RANGE_TYPE_MASK);
683 pci_word_test_and_set_mask(d->cmask + PCI_PREF_MEMORY_LIMIT,
684 PCI_PREF_RANGE_TYPE_MASK);
687 static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
689 uint8_t slot = PCI_SLOT(dev->devfn);
690 uint8_t func;
692 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
693 dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
697 * multifunction bit is interpreted in two ways as follows.
698 * - all functions must set the bit to 1.
699 * Example: Intel X53
700 * - function 0 must set the bit, but the rest function (> 0)
701 * is allowed to leave the bit to 0.
702 * Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
704 * So OS (at least Linux) checks the bit of only function 0,
705 * and doesn't see the bit of function > 0.
707 * The below check allows both interpretation.
709 if (PCI_FUNC(dev->devfn)) {
710 PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
711 if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
712 /* function 0 should set multifunction bit */
713 error_report("PCI: single function device can't be populated "
714 "in function %x.%x", slot, PCI_FUNC(dev->devfn));
715 return -1;
717 return 0;
720 if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
721 return 0;
723 /* function 0 indicates single function, so function > 0 must be NULL */
724 for (func = 1; func < PCI_FUNC_MAX; ++func) {
725 if (bus->devices[PCI_DEVFN(slot, func)]) {
726 error_report("PCI: %x.0 indicates single function, "
727 "but %x.%x is already populated.",
728 slot, slot, func);
729 return -1;
732 return 0;
735 static void pci_config_alloc(PCIDevice *pci_dev)
737 int config_size = pci_config_size(pci_dev);
739 pci_dev->config = g_malloc0(config_size);
740 pci_dev->cmask = g_malloc0(config_size);
741 pci_dev->wmask = g_malloc0(config_size);
742 pci_dev->w1cmask = g_malloc0(config_size);
743 pci_dev->used = g_malloc0(config_size);
746 static void pci_config_free(PCIDevice *pci_dev)
748 g_free(pci_dev->config);
749 g_free(pci_dev->cmask);
750 g_free(pci_dev->wmask);
751 g_free(pci_dev->w1cmask);
752 g_free(pci_dev->used);
755 /* -1 for devfn means auto assign */
756 static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
757 const char *name, int devfn)
759 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
760 PCIConfigReadFunc *config_read = pc->config_read;
761 PCIConfigWriteFunc *config_write = pc->config_write;
763 if (devfn < 0) {
764 for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
765 devfn += PCI_FUNC_MAX) {
766 if (!bus->devices[devfn])
767 goto found;
769 error_report("PCI: no slot/function available for %s, all in use", name);
770 return NULL;
771 found: ;
772 } else if (bus->devices[devfn]) {
773 error_report("PCI: slot %d function %d not available for %s, in use by %s",
774 PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
775 return NULL;
777 pci_dev->bus = bus;
778 pci_dev->devfn = devfn;
779 pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
780 pci_dev->irq_state = 0;
781 pci_config_alloc(pci_dev);
783 pci_config_set_vendor_id(pci_dev->config, pc->vendor_id);
784 pci_config_set_device_id(pci_dev->config, pc->device_id);
785 pci_config_set_revision(pci_dev->config, pc->revision);
786 pci_config_set_class(pci_dev->config, pc->class_id);
788 if (!pc->is_bridge) {
789 if (pc->subsystem_vendor_id || pc->subsystem_id) {
790 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
791 pc->subsystem_vendor_id);
792 pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
793 pc->subsystem_id);
794 } else {
795 pci_set_default_subsystem_id(pci_dev);
797 } else {
798 /* subsystem_vendor_id/subsystem_id are only for header type 0 */
799 assert(!pc->subsystem_vendor_id);
800 assert(!pc->subsystem_id);
802 pci_init_cmask(pci_dev);
803 pci_init_wmask(pci_dev);
804 pci_init_w1cmask(pci_dev);
805 if (pc->is_bridge) {
806 pci_init_mask_bridge(pci_dev);
808 if (pci_init_multifunction(bus, pci_dev)) {
809 pci_config_free(pci_dev);
810 return NULL;
813 if (!config_read)
814 config_read = pci_default_read_config;
815 if (!config_write)
816 config_write = pci_default_write_config;
817 pci_dev->config_read = config_read;
818 pci_dev->config_write = config_write;
819 bus->devices[devfn] = pci_dev;
820 pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
821 pci_dev->version_id = 2; /* Current pci device vmstate version */
822 return pci_dev;
825 static void do_pci_unregister_device(PCIDevice *pci_dev)
827 qemu_free_irqs(pci_dev->irq);
828 pci_dev->bus->devices[pci_dev->devfn] = NULL;
829 pci_config_free(pci_dev);
832 static void pci_unregister_io_regions(PCIDevice *pci_dev)
834 PCIIORegion *r;
835 int i;
837 for(i = 0; i < PCI_NUM_REGIONS; i++) {
838 r = &pci_dev->io_regions[i];
839 if (!r->size || r->addr == PCI_BAR_UNMAPPED)
840 continue;
841 memory_region_del_subregion(r->address_space, r->memory);
845 static int pci_unregister_device(DeviceState *dev)
847 PCIDevice *pci_dev = PCI_DEVICE(dev);
848 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
849 int ret = 0;
851 if (pc->exit)
852 ret = pc->exit(pci_dev);
853 if (ret)
854 return ret;
856 pci_unregister_io_regions(pci_dev);
857 pci_del_option_rom(pci_dev);
858 do_pci_unregister_device(pci_dev);
859 return 0;
862 void pci_register_bar(PCIDevice *pci_dev, int region_num,
863 uint8_t type, MemoryRegion *memory)
865 PCIIORegion *r;
866 uint32_t addr;
867 uint64_t wmask;
868 pcibus_t size = memory_region_size(memory);
870 assert(region_num >= 0);
871 assert(region_num < PCI_NUM_REGIONS);
872 if (size & (size-1)) {
873 fprintf(stderr, "ERROR: PCI region size must be pow2 "
874 "type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
875 exit(1);
878 r = &pci_dev->io_regions[region_num];
879 r->addr = PCI_BAR_UNMAPPED;
880 r->size = size;
881 r->type = type;
882 r->memory = NULL;
884 wmask = ~(size - 1);
885 addr = pci_bar(pci_dev, region_num);
886 if (region_num == PCI_ROM_SLOT) {
887 /* ROM enable bit is writable */
888 wmask |= PCI_ROM_ADDRESS_ENABLE;
890 pci_set_long(pci_dev->config + addr, type);
891 if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
892 r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
893 pci_set_quad(pci_dev->wmask + addr, wmask);
894 pci_set_quad(pci_dev->cmask + addr, ~0ULL);
895 } else {
896 pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
897 pci_set_long(pci_dev->cmask + addr, 0xffffffff);
899 pci_dev->io_regions[region_num].memory = memory;
900 pci_dev->io_regions[region_num].address_space
901 = type & PCI_BASE_ADDRESS_SPACE_IO
902 ? pci_dev->bus->address_space_io
903 : pci_dev->bus->address_space_mem;
906 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num)
908 return pci_dev->io_regions[region_num].addr;
911 static pcibus_t pci_bar_address(PCIDevice *d,
912 int reg, uint8_t type, pcibus_t size)
914 pcibus_t new_addr, last_addr;
915 int bar = pci_bar(d, reg);
916 uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
918 if (type & PCI_BASE_ADDRESS_SPACE_IO) {
919 if (!(cmd & PCI_COMMAND_IO)) {
920 return PCI_BAR_UNMAPPED;
922 new_addr = pci_get_long(d->config + bar) & ~(size - 1);
923 last_addr = new_addr + size - 1;
924 /* NOTE: we have only 64K ioports on PC */
925 if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
926 return PCI_BAR_UNMAPPED;
928 return new_addr;
931 if (!(cmd & PCI_COMMAND_MEMORY)) {
932 return PCI_BAR_UNMAPPED;
934 if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
935 new_addr = pci_get_quad(d->config + bar);
936 } else {
937 new_addr = pci_get_long(d->config + bar);
939 /* the ROM slot has a specific enable bit */
940 if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
941 return PCI_BAR_UNMAPPED;
943 new_addr &= ~(size - 1);
944 last_addr = new_addr + size - 1;
945 /* NOTE: we do not support wrapping */
946 /* XXX: as we cannot support really dynamic
947 mappings, we handle specific values as invalid
948 mappings. */
949 if (last_addr <= new_addr || new_addr == 0 ||
950 last_addr == PCI_BAR_UNMAPPED) {
951 return PCI_BAR_UNMAPPED;
954 /* Now pcibus_t is 64bit.
955 * Check if 32 bit BAR wraps around explicitly.
956 * Without this, PC ide doesn't work well.
957 * TODO: remove this work around.
959 if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
960 return PCI_BAR_UNMAPPED;
964 * OS is allowed to set BAR beyond its addressable
965 * bits. For example, 32 bit OS can set 64bit bar
966 * to >4G. Check it. TODO: we might need to support
967 * it in the future for e.g. PAE.
969 if (last_addr >= TARGET_PHYS_ADDR_MAX) {
970 return PCI_BAR_UNMAPPED;
973 return new_addr;
976 static void pci_update_mappings(PCIDevice *d)
978 PCIIORegion *r;
979 int i;
980 pcibus_t new_addr;
982 for(i = 0; i < PCI_NUM_REGIONS; i++) {
983 r = &d->io_regions[i];
985 /* this region isn't registered */
986 if (!r->size)
987 continue;
989 new_addr = pci_bar_address(d, i, r->type, r->size);
991 /* This bar isn't changed */
992 if (new_addr == r->addr)
993 continue;
995 /* now do the real mapping */
996 if (r->addr != PCI_BAR_UNMAPPED) {
997 memory_region_del_subregion(r->address_space, r->memory);
999 r->addr = new_addr;
1000 if (r->addr != PCI_BAR_UNMAPPED) {
1001 memory_region_add_subregion_overlap(r->address_space,
1002 r->addr, r->memory, 1);
1007 static inline int pci_irq_disabled(PCIDevice *d)
1009 return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
1012 /* Called after interrupt disabled field update in config space,
1013 * assert/deassert interrupts if necessary.
1014 * Gets original interrupt disable bit value (before update). */
1015 static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
1017 int i, disabled = pci_irq_disabled(d);
1018 if (disabled == was_irq_disabled)
1019 return;
1020 for (i = 0; i < PCI_NUM_PINS; ++i) {
1021 int state = pci_irq_state(d, i);
1022 pci_change_irq_level(d, i, disabled ? -state : state);
1026 uint32_t pci_default_read_config(PCIDevice *d,
1027 uint32_t address, int len)
1029 uint32_t val = 0;
1031 memcpy(&val, d->config + address, len);
1032 return le32_to_cpu(val);
1035 void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
1037 int i, was_irq_disabled = pci_irq_disabled(d);
1039 for (i = 0; i < l; val >>= 8, ++i) {
1040 uint8_t wmask = d->wmask[addr + i];
1041 uint8_t w1cmask = d->w1cmask[addr + i];
1042 assert(!(wmask & w1cmask));
1043 d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
1044 d->config[addr + i] &= ~(val & w1cmask); /* W1C: Write 1 to Clear */
1046 if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
1047 ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
1048 ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
1049 range_covers_byte(addr, l, PCI_COMMAND))
1050 pci_update_mappings(d);
1052 if (range_covers_byte(addr, l, PCI_COMMAND))
1053 pci_update_irq_disabled(d, was_irq_disabled);
1055 msi_write_config(d, addr, val, l);
1056 msix_write_config(d, addr, val, l);
1059 /***********************************************************/
1060 /* generic PCI irq support */
1062 /* 0 <= irq_num <= 3. level must be 0 or 1 */
1063 static void pci_set_irq(void *opaque, int irq_num, int level)
1065 PCIDevice *pci_dev = opaque;
1066 int change;
1068 change = level - pci_irq_state(pci_dev, irq_num);
1069 if (!change)
1070 return;
1072 pci_set_irq_state(pci_dev, irq_num, level);
1073 pci_update_irq_status(pci_dev);
1074 if (pci_irq_disabled(pci_dev))
1075 return;
1076 pci_change_irq_level(pci_dev, irq_num, change);
1079 /***********************************************************/
1080 /* monitor info on PCI */
1082 typedef struct {
1083 uint16_t class;
1084 const char *desc;
1085 const char *fw_name;
1086 uint16_t fw_ign_bits;
1087 } pci_class_desc;
1089 static const pci_class_desc pci_class_descriptions[] =
1091 { 0x0001, "VGA controller", "display"},
1092 { 0x0100, "SCSI controller", "scsi"},
1093 { 0x0101, "IDE controller", "ide"},
1094 { 0x0102, "Floppy controller", "fdc"},
1095 { 0x0103, "IPI controller", "ipi"},
1096 { 0x0104, "RAID controller", "raid"},
1097 { 0x0106, "SATA controller"},
1098 { 0x0107, "SAS controller"},
1099 { 0x0180, "Storage controller"},
1100 { 0x0200, "Ethernet controller", "ethernet"},
1101 { 0x0201, "Token Ring controller", "token-ring"},
1102 { 0x0202, "FDDI controller", "fddi"},
1103 { 0x0203, "ATM controller", "atm"},
1104 { 0x0280, "Network controller"},
1105 { 0x0300, "VGA controller", "display", 0x00ff},
1106 { 0x0301, "XGA controller"},
1107 { 0x0302, "3D controller"},
1108 { 0x0380, "Display controller"},
1109 { 0x0400, "Video controller", "video"},
1110 { 0x0401, "Audio controller", "sound"},
1111 { 0x0402, "Phone"},
1112 { 0x0403, "Audio controller", "sound"},
1113 { 0x0480, "Multimedia controller"},
1114 { 0x0500, "RAM controller", "memory"},
1115 { 0x0501, "Flash controller", "flash"},
1116 { 0x0580, "Memory controller"},
1117 { 0x0600, "Host bridge", "host"},
1118 { 0x0601, "ISA bridge", "isa"},
1119 { 0x0602, "EISA bridge", "eisa"},
1120 { 0x0603, "MC bridge", "mca"},
1121 { 0x0604, "PCI bridge", "pci"},
1122 { 0x0605, "PCMCIA bridge", "pcmcia"},
1123 { 0x0606, "NUBUS bridge", "nubus"},
1124 { 0x0607, "CARDBUS bridge", "cardbus"},
1125 { 0x0608, "RACEWAY bridge"},
1126 { 0x0680, "Bridge"},
1127 { 0x0700, "Serial port", "serial"},
1128 { 0x0701, "Parallel port", "parallel"},
1129 { 0x0800, "Interrupt controller", "interrupt-controller"},
1130 { 0x0801, "DMA controller", "dma-controller"},
1131 { 0x0802, "Timer", "timer"},
1132 { 0x0803, "RTC", "rtc"},
1133 { 0x0900, "Keyboard", "keyboard"},
1134 { 0x0901, "Pen", "pen"},
1135 { 0x0902, "Mouse", "mouse"},
1136 { 0x0A00, "Dock station", "dock", 0x00ff},
1137 { 0x0B00, "i386 cpu", "cpu", 0x00ff},
1138 { 0x0c00, "Fireware contorller", "fireware"},
1139 { 0x0c01, "Access bus controller", "access-bus"},
1140 { 0x0c02, "SSA controller", "ssa"},
1141 { 0x0c03, "USB controller", "usb"},
1142 { 0x0c04, "Fibre channel controller", "fibre-channel"},
1143 { 0, NULL}
1146 static void pci_for_each_device_under_bus(PCIBus *bus,
1147 void (*fn)(PCIBus *b, PCIDevice *d))
1149 PCIDevice *d;
1150 int devfn;
1152 for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1153 d = bus->devices[devfn];
1154 if (d) {
1155 fn(bus, d);
1160 void pci_for_each_device(PCIBus *bus, int bus_num,
1161 void (*fn)(PCIBus *b, PCIDevice *d))
1163 bus = pci_find_bus_nr(bus, bus_num);
1165 if (bus) {
1166 pci_for_each_device_under_bus(bus, fn);
1170 static const pci_class_desc *get_class_desc(int class)
1172 const pci_class_desc *desc;
1174 desc = pci_class_descriptions;
1175 while (desc->desc && class != desc->class) {
1176 desc++;
1179 return desc;
1182 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num);
1184 static PciMemoryRegionList *qmp_query_pci_regions(const PCIDevice *dev)
1186 PciMemoryRegionList *head = NULL, *cur_item = NULL;
1187 int i;
1189 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1190 const PCIIORegion *r = &dev->io_regions[i];
1191 PciMemoryRegionList *region;
1193 if (!r->size) {
1194 continue;
1197 region = g_malloc0(sizeof(*region));
1198 region->value = g_malloc0(sizeof(*region->value));
1200 if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
1201 region->value->type = g_strdup("io");
1202 } else {
1203 region->value->type = g_strdup("memory");
1204 region->value->has_prefetch = true;
1205 region->value->prefetch = !!(r->type & PCI_BASE_ADDRESS_MEM_PREFETCH);
1206 region->value->has_mem_type_64 = true;
1207 region->value->mem_type_64 = !!(r->type & PCI_BASE_ADDRESS_MEM_TYPE_64);
1210 region->value->bar = i;
1211 region->value->address = r->addr;
1212 region->value->size = r->size;
1214 /* XXX: waiting for the qapi to support GSList */
1215 if (!cur_item) {
1216 head = cur_item = region;
1217 } else {
1218 cur_item->next = region;
1219 cur_item = region;
1223 return head;
1226 static PciBridgeInfo *qmp_query_pci_bridge(PCIDevice *dev, PCIBus *bus,
1227 int bus_num)
1229 PciBridgeInfo *info;
1231 info = g_malloc0(sizeof(*info));
1233 info->bus.number = dev->config[PCI_PRIMARY_BUS];
1234 info->bus.secondary = dev->config[PCI_SECONDARY_BUS];
1235 info->bus.subordinate = dev->config[PCI_SUBORDINATE_BUS];
1237 info->bus.io_range = g_malloc0(sizeof(*info->bus.io_range));
1238 info->bus.io_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO);
1239 info->bus.io_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO);
1241 info->bus.memory_range = g_malloc0(sizeof(*info->bus.memory_range));
1242 info->bus.memory_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1243 info->bus.memory_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY);
1245 info->bus.prefetchable_range = g_malloc0(sizeof(*info->bus.prefetchable_range));
1246 info->bus.prefetchable_range->base = pci_bridge_get_base(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1247 info->bus.prefetchable_range->limit = pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_MEM_PREFETCH);
1249 if (dev->config[PCI_SECONDARY_BUS] != 0) {
1250 PCIBus *child_bus = pci_find_bus_nr(bus, dev->config[PCI_SECONDARY_BUS]);
1251 if (child_bus) {
1252 info->has_devices = true;
1253 info->devices = qmp_query_pci_devices(child_bus, dev->config[PCI_SECONDARY_BUS]);
1257 return info;
1260 static PciDeviceInfo *qmp_query_pci_device(PCIDevice *dev, PCIBus *bus,
1261 int bus_num)
1263 const pci_class_desc *desc;
1264 PciDeviceInfo *info;
1265 uint8_t type;
1266 int class;
1268 info = g_malloc0(sizeof(*info));
1269 info->bus = bus_num;
1270 info->slot = PCI_SLOT(dev->devfn);
1271 info->function = PCI_FUNC(dev->devfn);
1273 class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
1274 info->class_info.class = class;
1275 desc = get_class_desc(class);
1276 if (desc->desc) {
1277 info->class_info.has_desc = true;
1278 info->class_info.desc = g_strdup(desc->desc);
1281 info->id.vendor = pci_get_word(dev->config + PCI_VENDOR_ID);
1282 info->id.device = pci_get_word(dev->config + PCI_DEVICE_ID);
1283 info->regions = qmp_query_pci_regions(dev);
1284 info->qdev_id = g_strdup(dev->qdev.id ? dev->qdev.id : "");
1286 if (dev->config[PCI_INTERRUPT_PIN] != 0) {
1287 info->has_irq = true;
1288 info->irq = dev->config[PCI_INTERRUPT_LINE];
1291 type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
1292 if (type == PCI_HEADER_TYPE_BRIDGE) {
1293 info->has_pci_bridge = true;
1294 info->pci_bridge = qmp_query_pci_bridge(dev, bus, bus_num);
1297 return info;
1300 static PciDeviceInfoList *qmp_query_pci_devices(PCIBus *bus, int bus_num)
1302 PciDeviceInfoList *info, *head = NULL, *cur_item = NULL;
1303 PCIDevice *dev;
1304 int devfn;
1306 for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
1307 dev = bus->devices[devfn];
1308 if (dev) {
1309 info = g_malloc0(sizeof(*info));
1310 info->value = qmp_query_pci_device(dev, bus, bus_num);
1312 /* XXX: waiting for the qapi to support GSList */
1313 if (!cur_item) {
1314 head = cur_item = info;
1315 } else {
1316 cur_item->next = info;
1317 cur_item = info;
1322 return head;
1325 static PciInfo *qmp_query_pci_bus(PCIBus *bus, int bus_num)
1327 PciInfo *info = NULL;
1329 bus = pci_find_bus_nr(bus, bus_num);
1330 if (bus) {
1331 info = g_malloc0(sizeof(*info));
1332 info->bus = bus_num;
1333 info->devices = qmp_query_pci_devices(bus, bus_num);
1336 return info;
1339 PciInfoList *qmp_query_pci(Error **errp)
1341 PciInfoList *info, *head = NULL, *cur_item = NULL;
1342 struct PCIHostBus *host;
1344 QLIST_FOREACH(host, &host_buses, next) {
1345 info = g_malloc0(sizeof(*info));
1346 info->value = qmp_query_pci_bus(host->bus, 0);
1348 /* XXX: waiting for the qapi to support GSList */
1349 if (!cur_item) {
1350 head = cur_item = info;
1351 } else {
1352 cur_item->next = info;
1353 cur_item = info;
1357 return head;
1360 static const char * const pci_nic_models[] = {
1361 "ne2k_pci",
1362 "i82551",
1363 "i82557b",
1364 "i82559er",
1365 "rtl8139",
1366 "e1000",
1367 "pcnet",
1368 "virtio",
1369 NULL
1372 static const char * const pci_nic_names[] = {
1373 "ne2k_pci",
1374 "i82551",
1375 "i82557b",
1376 "i82559er",
1377 "rtl8139",
1378 "e1000",
1379 "pcnet",
1380 "virtio-net-pci",
1381 NULL
1384 /* Initialize a PCI NIC. */
1385 /* FIXME callers should check for failure, but don't */
1386 PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
1387 const char *default_devaddr)
1389 const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
1390 PCIBus *bus;
1391 int devfn;
1392 PCIDevice *pci_dev;
1393 DeviceState *dev;
1394 int i;
1396 i = qemu_find_nic_model(nd, pci_nic_models, default_model);
1397 if (i < 0)
1398 return NULL;
1400 bus = pci_get_bus_devfn(&devfn, devaddr);
1401 if (!bus) {
1402 error_report("Invalid PCI device address %s for device %s",
1403 devaddr, pci_nic_names[i]);
1404 return NULL;
1407 pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
1408 dev = &pci_dev->qdev;
1409 qdev_set_nic_properties(dev, nd);
1410 if (qdev_init(dev) < 0)
1411 return NULL;
1412 return pci_dev;
1415 PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
1416 const char *default_devaddr)
1418 PCIDevice *res;
1420 if (qemu_show_nic_models(nd->model, pci_nic_models))
1421 exit(0);
1423 res = pci_nic_init(nd, default_model, default_devaddr);
1424 if (!res)
1425 exit(1);
1426 return res;
1429 /* Whether a given bus number is in range of the secondary
1430 * bus of the given bridge device. */
1431 static bool pci_secondary_bus_in_range(PCIDevice *dev, int bus_num)
1433 return !(pci_get_word(dev->config + PCI_BRIDGE_CONTROL) &
1434 PCI_BRIDGE_CTL_BUS_RESET) /* Don't walk the bus if it's reset. */ &&
1435 dev->config[PCI_SECONDARY_BUS] < bus_num &&
1436 bus_num <= dev->config[PCI_SUBORDINATE_BUS];
1439 static PCIBus *pci_find_bus_nr(PCIBus *bus, int bus_num)
1441 PCIBus *sec;
1443 if (!bus) {
1444 return NULL;
1447 if (pci_bus_num(bus) == bus_num) {
1448 return bus;
1451 /* Consider all bus numbers in range for the host pci bridge. */
1452 if (bus->parent_dev &&
1453 !pci_secondary_bus_in_range(bus->parent_dev, bus_num)) {
1454 return NULL;
1457 /* try child bus */
1458 for (; bus; bus = sec) {
1459 QLIST_FOREACH(sec, &bus->child, sibling) {
1460 assert(sec->parent_dev);
1461 if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
1462 return sec;
1464 if (pci_secondary_bus_in_range(sec->parent_dev, bus_num)) {
1465 break;
1470 return NULL;
1473 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn)
1475 bus = pci_find_bus_nr(bus, bus_num);
1477 if (!bus)
1478 return NULL;
1480 return bus->devices[devfn];
1483 static int pci_qdev_init(DeviceState *qdev)
1485 PCIDevice *pci_dev = (PCIDevice *)qdev;
1486 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(pci_dev);
1487 PCIBus *bus;
1488 int rc;
1489 bool is_default_rom;
1491 /* initialize cap_present for pci_is_express() and pci_config_size() */
1492 if (pc->is_express) {
1493 pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
1496 bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
1497 pci_dev = do_pci_register_device(pci_dev, bus,
1498 object_get_typename(OBJECT(qdev)),
1499 pci_dev->devfn);
1500 if (pci_dev == NULL)
1501 return -1;
1502 if (qdev->hotplugged && pc->no_hotplug) {
1503 qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(pci_dev)));
1504 do_pci_unregister_device(pci_dev);
1505 return -1;
1507 if (pc->init) {
1508 rc = pc->init(pci_dev);
1509 if (rc != 0) {
1510 do_pci_unregister_device(pci_dev);
1511 return rc;
1515 /* rom loading */
1516 is_default_rom = false;
1517 if (pci_dev->romfile == NULL && pc->romfile != NULL) {
1518 pci_dev->romfile = g_strdup(pc->romfile);
1519 is_default_rom = true;
1521 pci_add_option_rom(pci_dev, is_default_rom);
1523 if (bus->hotplug) {
1524 /* Let buses differentiate between hotplug and when device is
1525 * enabled during qemu machine creation. */
1526 rc = bus->hotplug(bus->hotplug_qdev, pci_dev,
1527 qdev->hotplugged ? PCI_HOTPLUG_ENABLED:
1528 PCI_COLDPLUG_ENABLED);
1529 if (rc != 0) {
1530 int r = pci_unregister_device(&pci_dev->qdev);
1531 assert(!r);
1532 return rc;
1535 return 0;
1538 static int pci_unplug_device(DeviceState *qdev)
1540 PCIDevice *dev = PCI_DEVICE(qdev);
1541 PCIDeviceClass *pc = PCI_DEVICE_GET_CLASS(dev);
1543 if (pc->no_hotplug) {
1544 qerror_report(QERR_DEVICE_NO_HOTPLUG, object_get_typename(OBJECT(dev)));
1545 return -1;
1547 return dev->bus->hotplug(dev->bus->hotplug_qdev, dev,
1548 PCI_HOTPLUG_DISABLED);
1551 PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
1552 const char *name)
1554 DeviceState *dev;
1556 dev = qdev_create(&bus->qbus, name);
1557 qdev_prop_set_int32(dev, "addr", devfn);
1558 qdev_prop_set_bit(dev, "multifunction", multifunction);
1559 return PCI_DEVICE(dev);
1562 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
1563 bool multifunction,
1564 const char *name)
1566 PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
1567 qdev_init_nofail(&dev->qdev);
1568 return dev;
1571 PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
1573 return pci_create_multifunction(bus, devfn, false, name);
1576 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
1578 return pci_create_simple_multifunction(bus, devfn, false, name);
1581 static int pci_find_space(PCIDevice *pdev, uint8_t size)
1583 int config_size = pci_config_size(pdev);
1584 int offset = PCI_CONFIG_HEADER_SIZE;
1585 int i;
1586 for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
1587 if (pdev->used[i])
1588 offset = i + 1;
1589 else if (i - offset + 1 == size)
1590 return offset;
1591 return 0;
1594 static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
1595 uint8_t *prev_p)
1597 uint8_t next, prev;
1599 if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
1600 return 0;
1602 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1603 prev = next + PCI_CAP_LIST_NEXT)
1604 if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
1605 break;
1607 if (prev_p)
1608 *prev_p = prev;
1609 return next;
1612 static uint8_t pci_find_capability_at_offset(PCIDevice *pdev, uint8_t offset)
1614 uint8_t next, prev, found = 0;
1616 if (!(pdev->used[offset])) {
1617 return 0;
1620 assert(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST);
1622 for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
1623 prev = next + PCI_CAP_LIST_NEXT) {
1624 if (next <= offset && next > found) {
1625 found = next;
1628 return found;
1631 /* Patch the PCI vendor and device ids in a PCI rom image if necessary.
1632 This is needed for an option rom which is used for more than one device. */
1633 static void pci_patch_ids(PCIDevice *pdev, uint8_t *ptr, int size)
1635 uint16_t vendor_id;
1636 uint16_t device_id;
1637 uint16_t rom_vendor_id;
1638 uint16_t rom_device_id;
1639 uint16_t rom_magic;
1640 uint16_t pcir_offset;
1641 uint8_t checksum;
1643 /* Words in rom data are little endian (like in PCI configuration),
1644 so they can be read / written with pci_get_word / pci_set_word. */
1646 /* Only a valid rom will be patched. */
1647 rom_magic = pci_get_word(ptr);
1648 if (rom_magic != 0xaa55) {
1649 PCI_DPRINTF("Bad ROM magic %04x\n", rom_magic);
1650 return;
1652 pcir_offset = pci_get_word(ptr + 0x18);
1653 if (pcir_offset + 8 >= size || memcmp(ptr + pcir_offset, "PCIR", 4)) {
1654 PCI_DPRINTF("Bad PCIR offset 0x%x or signature\n", pcir_offset);
1655 return;
1658 vendor_id = pci_get_word(pdev->config + PCI_VENDOR_ID);
1659 device_id = pci_get_word(pdev->config + PCI_DEVICE_ID);
1660 rom_vendor_id = pci_get_word(ptr + pcir_offset + 4);
1661 rom_device_id = pci_get_word(ptr + pcir_offset + 6);
1663 PCI_DPRINTF("%s: ROM id %04x%04x / PCI id %04x%04x\n", pdev->romfile,
1664 vendor_id, device_id, rom_vendor_id, rom_device_id);
1666 checksum = ptr[6];
1668 if (vendor_id != rom_vendor_id) {
1669 /* Patch vendor id and checksum (at offset 6 for etherboot roms). */
1670 checksum += (uint8_t)rom_vendor_id + (uint8_t)(rom_vendor_id >> 8);
1671 checksum -= (uint8_t)vendor_id + (uint8_t)(vendor_id >> 8);
1672 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1673 ptr[6] = checksum;
1674 pci_set_word(ptr + pcir_offset + 4, vendor_id);
1677 if (device_id != rom_device_id) {
1678 /* Patch device id and checksum (at offset 6 for etherboot roms). */
1679 checksum += (uint8_t)rom_device_id + (uint8_t)(rom_device_id >> 8);
1680 checksum -= (uint8_t)device_id + (uint8_t)(device_id >> 8);
1681 PCI_DPRINTF("ROM checksum %02x / %02x\n", ptr[6], checksum);
1682 ptr[6] = checksum;
1683 pci_set_word(ptr + pcir_offset + 6, device_id);
1687 /* Add an option rom for the device */
1688 static int pci_add_option_rom(PCIDevice *pdev, bool is_default_rom)
1690 int size;
1691 char *path;
1692 void *ptr;
1693 char name[32];
1694 const VMStateDescription *vmsd;
1696 if (!pdev->romfile)
1697 return 0;
1698 if (strlen(pdev->romfile) == 0)
1699 return 0;
1701 if (!pdev->rom_bar) {
1703 * Load rom via fw_cfg instead of creating a rom bar,
1704 * for 0.11 compatibility.
1706 int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
1707 if (class == 0x0300) {
1708 rom_add_vga(pdev->romfile);
1709 } else {
1710 rom_add_option(pdev->romfile, -1);
1712 return 0;
1715 path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
1716 if (path == NULL) {
1717 path = g_strdup(pdev->romfile);
1720 size = get_image_size(path);
1721 if (size < 0) {
1722 error_report("%s: failed to find romfile \"%s\"",
1723 __FUNCTION__, pdev->romfile);
1724 g_free(path);
1725 return -1;
1727 if (size & (size - 1)) {
1728 size = 1 << qemu_fls(size);
1731 vmsd = qdev_get_vmsd(DEVICE(pdev));
1733 if (vmsd) {
1734 snprintf(name, sizeof(name), "%s.rom", vmsd->name);
1735 } else {
1736 snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev)));
1738 pdev->has_rom = true;
1739 memory_region_init_ram(&pdev->rom, name, size);
1740 vmstate_register_ram(&pdev->rom, &pdev->qdev);
1741 ptr = memory_region_get_ram_ptr(&pdev->rom);
1742 load_image(path, ptr);
1743 g_free(path);
1745 if (is_default_rom) {
1746 /* Only the default rom images will be patched (if needed). */
1747 pci_patch_ids(pdev, ptr, size);
1750 qemu_put_ram_ptr(ptr);
1752 pci_register_bar(pdev, PCI_ROM_SLOT, 0, &pdev->rom);
1754 return 0;
1757 static void pci_del_option_rom(PCIDevice *pdev)
1759 if (!pdev->has_rom)
1760 return;
1762 vmstate_unregister_ram(&pdev->rom, &pdev->qdev);
1763 memory_region_destroy(&pdev->rom);
1764 pdev->has_rom = false;
1768 * if !offset
1769 * Reserve space and add capability to the linked list in pci config space
1771 * if offset = 0,
1772 * Find and reserve space and add capability to the linked list
1773 * in pci config space */
1774 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
1775 uint8_t offset, uint8_t size)
1777 uint8_t *config;
1778 int i, overlapping_cap;
1780 if (!offset) {
1781 offset = pci_find_space(pdev, size);
1782 if (!offset) {
1783 return -ENOSPC;
1785 } else {
1786 /* Verify that capabilities don't overlap. Note: device assignment
1787 * depends on this check to verify that the device is not broken.
1788 * Should never trigger for emulated devices, but it's helpful
1789 * for debugging these. */
1790 for (i = offset; i < offset + size; i++) {
1791 overlapping_cap = pci_find_capability_at_offset(pdev, i);
1792 if (overlapping_cap) {
1793 fprintf(stderr, "ERROR: %04x:%02x:%02x.%x "
1794 "Attempt to add PCI capability %x at offset "
1795 "%x overlaps existing capability %x at offset %x\n",
1796 pci_find_domain(pdev->bus), pci_bus_num(pdev->bus),
1797 PCI_SLOT(pdev->devfn), PCI_FUNC(pdev->devfn),
1798 cap_id, offset, overlapping_cap, i);
1799 return -EINVAL;
1804 config = pdev->config + offset;
1805 config[PCI_CAP_LIST_ID] = cap_id;
1806 config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
1807 pdev->config[PCI_CAPABILITY_LIST] = offset;
1808 pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
1809 memset(pdev->used + offset, 0xFF, size);
1810 /* Make capability read-only by default */
1811 memset(pdev->wmask + offset, 0, size);
1812 /* Check capability by default */
1813 memset(pdev->cmask + offset, 0xFF, size);
1814 return offset;
1817 /* Unlink capability from the pci config space. */
1818 void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
1820 uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
1821 if (!offset)
1822 return;
1823 pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
1824 /* Make capability writable again */
1825 memset(pdev->wmask + offset, 0xff, size);
1826 memset(pdev->w1cmask + offset, 0, size);
1827 /* Clear cmask as device-specific registers can't be checked */
1828 memset(pdev->cmask + offset, 0, size);
1829 memset(pdev->used + offset, 0, size);
1831 if (!pdev->config[PCI_CAPABILITY_LIST])
1832 pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
1835 uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
1837 return pci_find_capability_list(pdev, cap_id, NULL);
1840 static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
1842 PCIDevice *d = (PCIDevice *)dev;
1843 const pci_class_desc *desc;
1844 char ctxt[64];
1845 PCIIORegion *r;
1846 int i, class;
1848 class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1849 desc = pci_class_descriptions;
1850 while (desc->desc && class != desc->class)
1851 desc++;
1852 if (desc->desc) {
1853 snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
1854 } else {
1855 snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
1858 monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
1859 "pci id %04x:%04x (sub %04x:%04x)\n",
1860 indent, "", ctxt, pci_bus_num(d->bus),
1861 PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
1862 pci_get_word(d->config + PCI_VENDOR_ID),
1863 pci_get_word(d->config + PCI_DEVICE_ID),
1864 pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
1865 pci_get_word(d->config + PCI_SUBSYSTEM_ID));
1866 for (i = 0; i < PCI_NUM_REGIONS; i++) {
1867 r = &d->io_regions[i];
1868 if (!r->size)
1869 continue;
1870 monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
1871 " [0x%"FMT_PCIBUS"]\n",
1872 indent, "",
1873 i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
1874 r->addr, r->addr + r->size - 1);
1878 static char *pci_dev_fw_name(DeviceState *dev, char *buf, int len)
1880 PCIDevice *d = (PCIDevice *)dev;
1881 const char *name = NULL;
1882 const pci_class_desc *desc = pci_class_descriptions;
1883 int class = pci_get_word(d->config + PCI_CLASS_DEVICE);
1885 while (desc->desc &&
1886 (class & ~desc->fw_ign_bits) !=
1887 (desc->class & ~desc->fw_ign_bits)) {
1888 desc++;
1891 if (desc->desc) {
1892 name = desc->fw_name;
1895 if (name) {
1896 pstrcpy(buf, len, name);
1897 } else {
1898 snprintf(buf, len, "pci%04x,%04x",
1899 pci_get_word(d->config + PCI_VENDOR_ID),
1900 pci_get_word(d->config + PCI_DEVICE_ID));
1903 return buf;
1906 static char *pcibus_get_fw_dev_path(DeviceState *dev)
1908 PCIDevice *d = (PCIDevice *)dev;
1909 char path[50], name[33];
1910 int off;
1912 off = snprintf(path, sizeof(path), "%s@%x",
1913 pci_dev_fw_name(dev, name, sizeof name),
1914 PCI_SLOT(d->devfn));
1915 if (PCI_FUNC(d->devfn))
1916 snprintf(path + off, sizeof(path) + off, ",%x", PCI_FUNC(d->devfn));
1917 return strdup(path);
1920 static char *pcibus_get_dev_path(DeviceState *dev)
1922 PCIDevice *d = container_of(dev, PCIDevice, qdev);
1923 PCIDevice *t;
1924 int slot_depth;
1925 /* Path format: Domain:00:Slot.Function:Slot.Function....:Slot.Function.
1926 * 00 is added here to make this format compatible with
1927 * domain:Bus:Slot.Func for systems without nested PCI bridges.
1928 * Slot.Function list specifies the slot and function numbers for all
1929 * devices on the path from root to the specific device. */
1930 char domain[] = "DDDD:00";
1931 char slot[] = ":SS.F";
1932 int domain_len = sizeof domain - 1 /* For '\0' */;
1933 int slot_len = sizeof slot - 1 /* For '\0' */;
1934 int path_len;
1935 char *path, *p;
1936 int s;
1938 /* Calculate # of slots on path between device and root. */;
1939 slot_depth = 0;
1940 for (t = d; t; t = t->bus->parent_dev) {
1941 ++slot_depth;
1944 path_len = domain_len + slot_len * slot_depth;
1946 /* Allocate memory, fill in the terminating null byte. */
1947 path = g_malloc(path_len + 1 /* For '\0' */);
1948 path[path_len] = '\0';
1950 /* First field is the domain. */
1951 s = snprintf(domain, sizeof domain, "%04x:00", pci_find_domain(d->bus));
1952 assert(s == domain_len);
1953 memcpy(path, domain, domain_len);
1955 /* Fill in slot numbers. We walk up from device to root, so need to print
1956 * them in the reverse order, last to first. */
1957 p = path + path_len;
1958 for (t = d; t; t = t->bus->parent_dev) {
1959 p -= slot_len;
1960 s = snprintf(slot, sizeof slot, ":%02x.%x",
1961 PCI_SLOT(t->devfn), PCI_FUNC(t->devfn));
1962 assert(s == slot_len);
1963 memcpy(p, slot, slot_len);
1966 return path;
1969 static int pci_qdev_find_recursive(PCIBus *bus,
1970 const char *id, PCIDevice **pdev)
1972 DeviceState *qdev = qdev_find_recursive(&bus->qbus, id);
1973 if (!qdev) {
1974 return -ENODEV;
1977 /* roughly check if given qdev is pci device */
1978 if (object_dynamic_cast(OBJECT(qdev), TYPE_PCI_DEVICE)) {
1979 *pdev = PCI_DEVICE(qdev);
1980 return 0;
1982 return -EINVAL;
1985 int pci_qdev_find_device(const char *id, PCIDevice **pdev)
1987 struct PCIHostBus *host;
1988 int rc = -ENODEV;
1990 QLIST_FOREACH(host, &host_buses, next) {
1991 int tmp = pci_qdev_find_recursive(host->bus, id, pdev);
1992 if (!tmp) {
1993 rc = 0;
1994 break;
1996 if (tmp != -ENODEV) {
1997 rc = tmp;
2001 return rc;
2004 MemoryRegion *pci_address_space(PCIDevice *dev)
2006 return dev->bus->address_space_mem;
2009 MemoryRegion *pci_address_space_io(PCIDevice *dev)
2011 return dev->bus->address_space_io;
2014 static void pci_device_class_init(ObjectClass *klass, void *data)
2016 DeviceClass *k = DEVICE_CLASS(klass);
2017 k->init = pci_qdev_init;
2018 k->unplug = pci_unplug_device;
2019 k->exit = pci_unregister_device;
2020 k->bus_type = TYPE_PCI_BUS;
2021 k->props = pci_props;
2024 static TypeInfo pci_device_type_info = {
2025 .name = TYPE_PCI_DEVICE,
2026 .parent = TYPE_DEVICE,
2027 .instance_size = sizeof(PCIDevice),
2028 .abstract = true,
2029 .class_size = sizeof(PCIDeviceClass),
2030 .class_init = pci_device_class_init,
2033 static void pci_register_types(void)
2035 type_register_static(&pci_bus_info);
2036 type_register_static(&pci_device_type_info);
2039 type_init(pci_register_types)